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authorGeert Uytterhoeven <geert+renesas@glider.be>2017-10-12 05:35:16 -0400
committerSimon Horman <horms+renesas@verge.net.au>2017-10-16 05:43:49 -0400
commite5042d0b97be6a831f9f204f3574d73b3f947fa5 (patch)
tree95e3070246e08f424efb8bc4f8b3594f800e6f57
parent5614e69269232da1f378e5be92714b96cdb090ef (diff)
ARM: dts: sh73a0: Add clocks for CA9 CPU cores
Improve hardware description by adding clocks properties to the device nodes corresponding to the CA9 CPU cores. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
-rw-r--r--arch/arm/boot/dts/sh73a0.dtsi2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi
index 4ea5c5a16c57..88d7e5631d34 100644
--- a/arch/arm/boot/dts/sh73a0.dtsi
+++ b/arch/arm/boot/dts/sh73a0.dtsi
@@ -27,6 +27,7 @@
27 compatible = "arm,cortex-a9"; 27 compatible = "arm,cortex-a9";
28 reg = <0>; 28 reg = <0>;
29 clock-frequency = <1196000000>; 29 clock-frequency = <1196000000>;
30 clocks = <&cpg_clocks SH73A0_CLK_Z>;
30 power-domains = <&pd_a2sl>; 31 power-domains = <&pd_a2sl>;
31 next-level-cache = <&L2>; 32 next-level-cache = <&L2>;
32 }; 33 };
@@ -35,6 +36,7 @@
35 compatible = "arm,cortex-a9"; 36 compatible = "arm,cortex-a9";
36 reg = <1>; 37 reg = <1>;
37 clock-frequency = <1196000000>; 38 clock-frequency = <1196000000>;
39 clocks = <&cpg_clocks SH73A0_CLK_Z>;
38 power-domains = <&pd_a2sl>; 40 power-domains = <&pd_a2sl>;
39 next-level-cache = <&L2>; 41 next-level-cache = <&L2>;
40 }; 42 };