diff options
| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2017-10-12 05:35:15 -0400 |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2017-10-16 05:43:35 -0400 |
| commit | 5614e69269232da1f378e5be92714b96cdb090ef (patch) | |
| tree | 140c1b6f122131e5414c9d076495b6665b1bedeb | |
| parent | f359fd3bba71176a122939fe3db9c7f20000d3f0 (diff) | |
ARM: dts: r8a7794: Add missing clock for secondary CA7 CPU core
Currently only the primary CPU in the CA7 cluster has a clocks property,
while the secondary CPU core is driven by the same clock.
Add the missing clocks property to fix this.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| -rw-r--r-- | arch/arm/boot/dts/r8a7794.dtsi | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index 7720a6ca8702..905e50c9b524 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi | |||
| @@ -53,6 +53,7 @@ | |||
| 53 | compatible = "arm,cortex-a7"; | 53 | compatible = "arm,cortex-a7"; |
| 54 | reg = <1>; | 54 | reg = <1>; |
| 55 | clock-frequency = <1000000000>; | 55 | clock-frequency = <1000000000>; |
| 56 | clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>; | ||
| 56 | power-domains = <&sysc R8A7794_PD_CA7_CPU1>; | 57 | power-domains = <&sysc R8A7794_PD_CA7_CPU1>; |
| 57 | next-level-cache = <&L2_CA7>; | 58 | next-level-cache = <&L2_CA7>; |
| 58 | }; | 59 | }; |