diff options
author | Bibby Hsieh <bibby.hsieh@mediatek.com> | 2016-07-27 22:22:53 -0400 |
---|---|---|
committer | Philipp Zabel <p.zabel@pengutronix.de> | 2016-08-11 02:41:39 -0400 |
commit | e0a5d33702451329b7da70a15fad3b919e441401 (patch) | |
tree | b3b68e74e1dbc7bcaf3d4eef31324d9389dce338 | |
parent | 0664d1392c26a8bfcdd6c6f0ff7c63eb0e1a10b0 (diff) |
drm/mediatek: Add GAMMA engine basic function
In order to correct brightness values, we have
to support gamma funciton on MT8173. In MT8173,
we have two engines for supporting gamma function:
AAL and GAMMA. This patch add some GAMMA engine
basic function, include config, start and stop
function.
Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
-rw-r--r-- | drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 29 |
1 files changed, 28 insertions, 1 deletions
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index 5fc967157cb8..ba895c8fd91d 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | |||
@@ -41,6 +41,9 @@ | |||
41 | #define DISP_AAL_EN 0x0000 | 41 | #define DISP_AAL_EN 0x0000 |
42 | #define DISP_AAL_SIZE 0x0030 | 42 | #define DISP_AAL_SIZE 0x0030 |
43 | 43 | ||
44 | #define DISP_GAMMA_EN 0x0000 | ||
45 | #define DISP_GAMMA_SIZE 0x0030 | ||
46 | |||
44 | #define OD_RELAY_MODE BIT(0) | 47 | #define OD_RELAY_MODE BIT(0) |
45 | 48 | ||
46 | #define UFO_BYPASS BIT(2) | 49 | #define UFO_BYPASS BIT(2) |
@@ -50,6 +53,8 @@ | |||
50 | 53 | ||
51 | #define AAL_EN BIT(0) | 54 | #define AAL_EN BIT(0) |
52 | 55 | ||
56 | #define GAMMA_EN BIT(0) | ||
57 | |||
53 | static void mtk_color_config(struct mtk_ddp_comp *comp, unsigned int w, | 58 | static void mtk_color_config(struct mtk_ddp_comp *comp, unsigned int w, |
54 | unsigned int h, unsigned int vrefresh) | 59 | unsigned int h, unsigned int vrefresh) |
55 | { | 60 | { |
@@ -97,12 +102,34 @@ static void mtk_aal_stop(struct mtk_ddp_comp *comp) | |||
97 | writel_relaxed(0x0, comp->regs + DISP_AAL_EN); | 102 | writel_relaxed(0x0, comp->regs + DISP_AAL_EN); |
98 | } | 103 | } |
99 | 104 | ||
105 | static void mtk_gamma_config(struct mtk_ddp_comp *comp, unsigned int w, | ||
106 | unsigned int h, unsigned int vrefresh) | ||
107 | { | ||
108 | writel(h << 16 | w, comp->regs + DISP_GAMMA_SIZE); | ||
109 | } | ||
110 | |||
111 | static void mtk_gamma_start(struct mtk_ddp_comp *comp) | ||
112 | { | ||
113 | writel(GAMMA_EN, comp->regs + DISP_GAMMA_EN); | ||
114 | } | ||
115 | |||
116 | static void mtk_gamma_stop(struct mtk_ddp_comp *comp) | ||
117 | { | ||
118 | writel_relaxed(0x0, comp->regs + DISP_GAMMA_EN); | ||
119 | } | ||
120 | |||
100 | static const struct mtk_ddp_comp_funcs ddp_aal = { | 121 | static const struct mtk_ddp_comp_funcs ddp_aal = { |
101 | .config = mtk_aal_config, | 122 | .config = mtk_aal_config, |
102 | .start = mtk_aal_start, | 123 | .start = mtk_aal_start, |
103 | .stop = mtk_aal_stop, | 124 | .stop = mtk_aal_stop, |
104 | }; | 125 | }; |
105 | 126 | ||
127 | static const struct mtk_ddp_comp_funcs ddp_gamma = { | ||
128 | .config = mtk_gamma_config, | ||
129 | .start = mtk_gamma_start, | ||
130 | .stop = mtk_gamma_stop, | ||
131 | }; | ||
132 | |||
106 | static const struct mtk_ddp_comp_funcs ddp_color = { | 133 | static const struct mtk_ddp_comp_funcs ddp_color = { |
107 | .config = mtk_color_config, | 134 | .config = mtk_color_config, |
108 | .start = mtk_color_start, | 135 | .start = mtk_color_start, |
@@ -145,7 +172,7 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { | |||
145 | [DDP_COMPONENT_DPI0] = { MTK_DPI, 0, NULL }, | 172 | [DDP_COMPONENT_DPI0] = { MTK_DPI, 0, NULL }, |
146 | [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, NULL }, | 173 | [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, NULL }, |
147 | [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, NULL }, | 174 | [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, NULL }, |
148 | [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, NULL }, | 175 | [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma }, |
149 | [DDP_COMPONENT_OD] = { MTK_DISP_OD, 0, &ddp_od }, | 176 | [DDP_COMPONENT_OD] = { MTK_DISP_OD, 0, &ddp_od }, |
150 | [DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, NULL }, | 177 | [DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, NULL }, |
151 | [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, NULL }, | 178 | [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, NULL }, |