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authorBibby Hsieh <bibby.hsieh@mediatek.com>2016-07-27 22:22:52 -0400
committerPhilipp Zabel <p.zabel@pengutronix.de>2016-08-11 02:41:39 -0400
commit0664d1392c26a8bfcdd6c6f0ff7c63eb0e1a10b0 (patch)
treef641341325f1a26007bebba87ebdd76168159720
parent37b2a2149bd39d80b2e2724e370f83c934eeff15 (diff)
drm/mediatek: Add AAL engine basic function
In order to correct brightness values, we have to support gamma funciton on MT8173. In MT8173, we have two engines for supporting gamma function: AAL and GAMMA. This patch add some AAL engine basic function, include config, start and stop function. Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
-rw-r--r--drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c29
1 files changed, 28 insertions, 1 deletions
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 3970fcf0f05f..5fc967157cb8 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -38,6 +38,9 @@
38#define DISP_COLOR_WIDTH 0x0c50 38#define DISP_COLOR_WIDTH 0x0c50
39#define DISP_COLOR_HEIGHT 0x0c54 39#define DISP_COLOR_HEIGHT 0x0c54
40 40
41#define DISP_AAL_EN 0x0000
42#define DISP_AAL_SIZE 0x0030
43
41#define OD_RELAY_MODE BIT(0) 44#define OD_RELAY_MODE BIT(0)
42 45
43#define UFO_BYPASS BIT(2) 46#define UFO_BYPASS BIT(2)
@@ -45,6 +48,8 @@
45#define COLOR_BYPASS_ALL BIT(7) 48#define COLOR_BYPASS_ALL BIT(7)
46#define COLOR_SEQ_SEL BIT(13) 49#define COLOR_SEQ_SEL BIT(13)
47 50
51#define AAL_EN BIT(0)
52
48static void mtk_color_config(struct mtk_ddp_comp *comp, unsigned int w, 53static void mtk_color_config(struct mtk_ddp_comp *comp, unsigned int w,
49 unsigned int h, unsigned int vrefresh) 54 unsigned int h, unsigned int vrefresh)
50{ 55{
@@ -76,6 +81,28 @@ static void mtk_ufoe_start(struct mtk_ddp_comp *comp)
76 writel(UFO_BYPASS, comp->regs + DISP_REG_UFO_START); 81 writel(UFO_BYPASS, comp->regs + DISP_REG_UFO_START);
77} 82}
78 83
84static void mtk_aal_config(struct mtk_ddp_comp *comp, unsigned int w,
85 unsigned int h, unsigned int vrefresh)
86{
87 writel(h << 16 | w, comp->regs + DISP_AAL_SIZE);
88}
89
90static void mtk_aal_start(struct mtk_ddp_comp *comp)
91{
92 writel(AAL_EN, comp->regs + DISP_AAL_EN);
93}
94
95static void mtk_aal_stop(struct mtk_ddp_comp *comp)
96{
97 writel_relaxed(0x0, comp->regs + DISP_AAL_EN);
98}
99
100static const struct mtk_ddp_comp_funcs ddp_aal = {
101 .config = mtk_aal_config,
102 .start = mtk_aal_start,
103 .stop = mtk_aal_stop,
104};
105
79static const struct mtk_ddp_comp_funcs ddp_color = { 106static const struct mtk_ddp_comp_funcs ddp_color = {
80 .config = mtk_color_config, 107 .config = mtk_color_config,
81 .start = mtk_color_start, 108 .start = mtk_color_start,
@@ -112,7 +139,7 @@ struct mtk_ddp_comp_match {
112}; 139};
113 140
114static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { 141static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
115 [DDP_COMPONENT_AAL] = { MTK_DISP_AAL, 0, NULL }, 142 [DDP_COMPONENT_AAL] = { MTK_DISP_AAL, 0, &ddp_aal },
116 [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, &ddp_color }, 143 [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, &ddp_color },
117 [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, &ddp_color }, 144 [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, &ddp_color },
118 [DDP_COMPONENT_DPI0] = { MTK_DPI, 0, NULL }, 145 [DDP_COMPONENT_DPI0] = { MTK_DPI, 0, NULL },