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authorRex Zhu <Rex.Zhu@amd.com>2016-12-23 01:07:25 -0500
committerAlex Deucher <alexander.deucher@amd.com>2017-01-27 11:12:52 -0500
commitdb7da7aa3a8c6a25964f2216fed35f4bf11ceac1 (patch)
treea952d0759a3c80cd8ea56960e5dd13f19bc6ffae
parent634a24d8af026d7e7df9b8c3a5efe3802de1299c (diff)
drm/amd/powerplay: delete dpm code for Cz/St.
The powerplay implementation has been the default for a while now. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat
-rw-r--r--drivers/gpu/drm/amd/amdgpu/Makefile3
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c8
-rw-r--r--drivers/gpu/drm/amd/amdgpu/cz_dpm.c2320
-rw-r--r--drivers/gpu/drm/amd/amdgpu/cz_dpm.h239
-rw-r--r--drivers/gpu/drm/amd/amdgpu/cz_smc.c995
-rw-r--r--drivers/gpu/drm/amd/amdgpu/cz_smumgr.h94
6 files changed, 2 insertions, 3657 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
index 41bd2bf28f4c..dba097ccdd9b 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -52,8 +52,7 @@ amdgpu-y += \
52# add SMC block 52# add SMC block
53amdgpu-y += \ 53amdgpu-y += \
54 amdgpu_dpm.o \ 54 amdgpu_dpm.o \
55 amdgpu_powerplay.o \ 55 amdgpu_powerplay.o
56 cz_smc.o cz_dpm.o
57 56
58# add DCE block 57# add DCE block
59amdgpu-y += \ 58amdgpu-y += \
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
index 95a568df8551..b1921c7da36b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
@@ -78,10 +78,6 @@ static int amdgpu_powerplay_init(struct amdgpu_device *adev)
78 amd_pp->ip_funcs = &kv_dpm_ip_funcs; 78 amd_pp->ip_funcs = &kv_dpm_ip_funcs;
79 break; 79 break;
80#endif 80#endif
81 case CHIP_CARRIZO:
82 case CHIP_STONEY:
83 amd_pp->ip_funcs = &cz_dpm_ip_funcs;
84 break;
85 default: 81 default:
86 ret = -EINVAL; 82 ret = -EINVAL;
87 break; 83 break;
@@ -102,11 +98,9 @@ static int amdgpu_pp_early_init(void *handle)
102 case CHIP_TONGA: 98 case CHIP_TONGA:
103 case CHIP_FIJI: 99 case CHIP_FIJI:
104 case CHIP_TOPAZ: 100 case CHIP_TOPAZ:
105 adev->pp_enabled = true;
106 break;
107 case CHIP_CARRIZO: 101 case CHIP_CARRIZO:
108 case CHIP_STONEY: 102 case CHIP_STONEY:
109 adev->pp_enabled = (amdgpu_powerplay == 0) ? false : true; 103 adev->pp_enabled = true;
110 break; 104 break;
111 /* These chips don't have powerplay implemenations */ 105 /* These chips don't have powerplay implemenations */
112 case CHIP_BONAIRE: 106 case CHIP_BONAIRE:
diff --git a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
deleted file mode 100644
index ba2b66be9022..000000000000
--- a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
+++ /dev/null
@@ -1,2320 +0,0 @@
1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <linux/firmware.h>
25#include <linux/seq_file.h>
26#include "drmP.h"
27#include "amdgpu.h"
28#include "amdgpu_pm.h"
29#include "amdgpu_atombios.h"
30#include "vid.h"
31#include "vi_dpm.h"
32#include "amdgpu_dpm.h"
33#include "cz_dpm.h"
34#include "cz_ppsmc.h"
35#include "atom.h"
36
37#include "smu/smu_8_0_d.h"
38#include "smu/smu_8_0_sh_mask.h"
39#include "gca/gfx_8_0_d.h"
40#include "gca/gfx_8_0_sh_mask.h"
41#include "gmc/gmc_8_1_d.h"
42#include "bif/bif_5_1_d.h"
43#include "gfx_v8_0.h"
44
45static void cz_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate);
46static void cz_dpm_powergate_vce(struct amdgpu_device *adev, bool gate);
47static void cz_dpm_fini(struct amdgpu_device *adev);
48
49static struct cz_ps *cz_get_ps(struct amdgpu_ps *rps)
50{
51 struct cz_ps *ps = rps->ps_priv;
52
53 return ps;
54}
55
56static struct cz_power_info *cz_get_pi(struct amdgpu_device *adev)
57{
58 struct cz_power_info *pi = adev->pm.dpm.priv;
59
60 return pi;
61}
62
63static uint16_t cz_convert_8bit_index_to_voltage(struct amdgpu_device *adev,
64 uint16_t voltage)
65{
66 uint16_t tmp = 6200 - voltage * 25;
67
68 return tmp;
69}
70
71static void cz_construct_max_power_limits_table(struct amdgpu_device *adev,
72 struct amdgpu_clock_and_voltage_limits *table)
73{
74 struct cz_power_info *pi = cz_get_pi(adev);
75 struct amdgpu_clock_voltage_dependency_table *dep_table =
76 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
77
78 if (dep_table->count > 0) {
79 table->sclk = dep_table->entries[dep_table->count - 1].clk;
80 table->vddc = cz_convert_8bit_index_to_voltage(adev,
81 dep_table->entries[dep_table->count - 1].v);
82 }
83
84 table->mclk = pi->sys_info.nbp_memory_clock[0];
85
86}
87
88union igp_info {
89 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
90 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7;
91 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8;
92 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_9 info_9;
93};
94
95static int cz_parse_sys_info_table(struct amdgpu_device *adev)
96{
97 struct cz_power_info *pi = cz_get_pi(adev);
98 struct amdgpu_mode_info *mode_info = &adev->mode_info;
99 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
100 union igp_info *igp_info;
101 u8 frev, crev;
102 u16 data_offset;
103 int i = 0;
104
105 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
106 &frev, &crev, &data_offset)) {
107 igp_info = (union igp_info *)(mode_info->atom_context->bios +
108 data_offset);
109
110 if (crev != 9) {
111 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
112 return -EINVAL;
113 }
114 pi->sys_info.bootup_sclk =
115 le32_to_cpu(igp_info->info_9.ulBootUpEngineClock);
116 pi->sys_info.bootup_uma_clk =
117 le32_to_cpu(igp_info->info_9.ulBootUpUMAClock);
118 pi->sys_info.dentist_vco_freq =
119 le32_to_cpu(igp_info->info_9.ulDentistVCOFreq);
120 pi->sys_info.bootup_nb_voltage_index =
121 le16_to_cpu(igp_info->info_9.usBootUpNBVoltage);
122
123 if (igp_info->info_9.ucHtcTmpLmt == 0)
124 pi->sys_info.htc_tmp_lmt = 203;
125 else
126 pi->sys_info.htc_tmp_lmt = igp_info->info_9.ucHtcTmpLmt;
127
128 if (igp_info->info_9.ucHtcHystLmt == 0)
129 pi->sys_info.htc_hyst_lmt = 5;
130 else
131 pi->sys_info.htc_hyst_lmt = igp_info->info_9.ucHtcHystLmt;
132
133 if (pi->sys_info.htc_tmp_lmt <= pi->sys_info.htc_hyst_lmt) {
134 DRM_ERROR("The htcTmpLmt should be larger than htcHystLmt.\n");
135 return -EINVAL;
136 }
137
138 if (le32_to_cpu(igp_info->info_9.ulSystemConfig) & (1 << 3) &&
139 pi->enable_nb_ps_policy)
140 pi->sys_info.nb_dpm_enable = true;
141 else
142 pi->sys_info.nb_dpm_enable = false;
143
144 for (i = 0; i < CZ_NUM_NBPSTATES; i++) {
145 if (i < CZ_NUM_NBPMEMORY_CLOCK)
146 pi->sys_info.nbp_memory_clock[i] =
147 le32_to_cpu(igp_info->info_9.ulNbpStateMemclkFreq[i]);
148 pi->sys_info.nbp_n_clock[i] =
149 le32_to_cpu(igp_info->info_9.ulNbpStateNClkFreq[i]);
150 }
151
152 for (i = 0; i < CZ_MAX_DISPLAY_CLOCK_LEVEL; i++)
153 pi->sys_info.display_clock[i] =
154 le32_to_cpu(igp_info->info_9.sDispClkVoltageMapping[i].ulMaximumSupportedCLK);
155
156 for (i = 0; i < CZ_NUM_NBPSTATES; i++)
157 pi->sys_info.nbp_voltage_index[i] =
158 le32_to_cpu(igp_info->info_9.usNBPStateVoltage[i]);
159
160 if (le32_to_cpu(igp_info->info_9.ulGPUCapInfo) &
161 SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS)
162 pi->caps_enable_dfs_bypass = true;
163
164 pi->sys_info.uma_channel_number =
165 igp_info->info_9.ucUMAChannelNumber;
166
167 cz_construct_max_power_limits_table(adev,
168 &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac);
169 }
170
171 return 0;
172}
173
174static void cz_patch_voltage_values(struct amdgpu_device *adev)
175{
176 int i;
177 struct amdgpu_uvd_clock_voltage_dependency_table *uvd_table =
178 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
179 struct amdgpu_vce_clock_voltage_dependency_table *vce_table =
180 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
181 struct amdgpu_clock_voltage_dependency_table *acp_table =
182 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
183
184 if (uvd_table->count) {
185 for (i = 0; i < uvd_table->count; i++)
186 uvd_table->entries[i].v =
187 cz_convert_8bit_index_to_voltage(adev,
188 uvd_table->entries[i].v);
189 }
190
191 if (vce_table->count) {
192 for (i = 0; i < vce_table->count; i++)
193 vce_table->entries[i].v =
194 cz_convert_8bit_index_to_voltage(adev,
195 vce_table->entries[i].v);
196 }
197
198 if (acp_table->count) {
199 for (i = 0; i < acp_table->count; i++)
200 acp_table->entries[i].v =
201 cz_convert_8bit_index_to_voltage(adev,
202 acp_table->entries[i].v);
203 }
204
205}
206
207static void cz_construct_boot_state(struct amdgpu_device *adev)
208{
209 struct cz_power_info *pi = cz_get_pi(adev);
210
211 pi->boot_pl.sclk = pi->sys_info.bootup_sclk;
212 pi->boot_pl.vddc_index = pi->sys_info.bootup_nb_voltage_index;
213 pi->boot_pl.ds_divider_index = 0;
214 pi->boot_pl.ss_divider_index = 0;
215 pi->boot_pl.allow_gnb_slow = 1;
216 pi->boot_pl.force_nbp_state = 0;
217 pi->boot_pl.display_wm = 0;
218 pi->boot_pl.vce_wm = 0;
219
220}
221
222static void cz_patch_boot_state(struct amdgpu_device *adev,
223 struct cz_ps *ps)
224{
225 struct cz_power_info *pi = cz_get_pi(adev);
226
227 ps->num_levels = 1;
228 ps->levels[0] = pi->boot_pl;
229}
230
231union pplib_clock_info {
232 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
233 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
234 struct _ATOM_PPLIB_CZ_CLOCK_INFO carrizo;
235};
236
237static void cz_parse_pplib_clock_info(struct amdgpu_device *adev,
238 struct amdgpu_ps *rps, int index,
239 union pplib_clock_info *clock_info)
240{
241 struct cz_power_info *pi = cz_get_pi(adev);
242 struct cz_ps *ps = cz_get_ps(rps);
243 struct cz_pl *pl = &ps->levels[index];
244 struct amdgpu_clock_voltage_dependency_table *table =
245 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
246
247 pl->sclk = table->entries[clock_info->carrizo.index].clk;
248 pl->vddc_index = table->entries[clock_info->carrizo.index].v;
249
250 ps->num_levels = index + 1;
251
252 if (pi->caps_sclk_ds) {
253 pl->ds_divider_index = 5;
254 pl->ss_divider_index = 5;
255 }
256
257}
258
259static void cz_parse_pplib_non_clock_info(struct amdgpu_device *adev,
260 struct amdgpu_ps *rps,
261 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
262 u8 table_rev)
263{
264 struct cz_ps *ps = cz_get_ps(rps);
265
266 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
267 rps->class = le16_to_cpu(non_clock_info->usClassification);
268 rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
269
270 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
271 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
272 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
273 } else {
274 rps->vclk = 0;
275 rps->dclk = 0;
276 }
277
278 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
279 adev->pm.dpm.boot_ps = rps;
280 cz_patch_boot_state(adev, ps);
281 }
282 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
283 adev->pm.dpm.uvd_ps = rps;
284
285}
286
287union power_info {
288 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
289 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
290 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
291 struct _ATOM_PPLIB_POWERPLAYTABLE4 pplib4;
292 struct _ATOM_PPLIB_POWERPLAYTABLE5 pplib5;
293};
294
295union pplib_power_state {
296 struct _ATOM_PPLIB_STATE v1;
297 struct _ATOM_PPLIB_STATE_V2 v2;
298};
299
300static int cz_parse_power_table(struct amdgpu_device *adev)
301{
302 struct amdgpu_mode_info *mode_info = &adev->mode_info;
303 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
304 union pplib_power_state *power_state;
305 int i, j, k, non_clock_array_index, clock_array_index;
306 union pplib_clock_info *clock_info;
307 struct _StateArray *state_array;
308 struct _ClockInfoArray *clock_info_array;
309 struct _NonClockInfoArray *non_clock_info_array;
310 union power_info *power_info;
311 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
312 u16 data_offset;
313 u8 frev, crev;
314 u8 *power_state_offset;
315 struct cz_ps *ps;
316
317 if (!amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
318 &frev, &crev, &data_offset))
319 return -EINVAL;
320 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
321
322 state_array = (struct _StateArray *)
323 (mode_info->atom_context->bios + data_offset +
324 le16_to_cpu(power_info->pplib.usStateArrayOffset));
325 clock_info_array = (struct _ClockInfoArray *)
326 (mode_info->atom_context->bios + data_offset +
327 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
328 non_clock_info_array = (struct _NonClockInfoArray *)
329 (mode_info->atom_context->bios + data_offset +
330 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
331
332 adev->pm.dpm.ps = kzalloc(sizeof(struct amdgpu_ps) *
333 state_array->ucNumEntries, GFP_KERNEL);
334
335 if (!adev->pm.dpm.ps)
336 return -ENOMEM;
337
338 power_state_offset = (u8 *)state_array->states;
339 adev->pm.dpm.platform_caps =
340 le32_to_cpu(power_info->pplib.ulPlatformCaps);
341 adev->pm.dpm.backbias_response_time =
342 le16_to_cpu(power_info->pplib.usBackbiasTime);
343 adev->pm.dpm.voltage_response_time =
344 le16_to_cpu(power_info->pplib.usVoltageTime);
345
346 for (i = 0; i < state_array->ucNumEntries; i++) {
347 power_state = (union pplib_power_state *)power_state_offset;
348 non_clock_array_index = power_state->v2.nonClockInfoIndex;
349 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
350 &non_clock_info_array->nonClockInfo[non_clock_array_index];
351
352 ps = kzalloc(sizeof(struct cz_ps), GFP_KERNEL);
353 if (ps == NULL) {
354 for (j = 0; j < i; j++)
355 kfree(adev->pm.dpm.ps[j].ps_priv);
356 kfree(adev->pm.dpm.ps);
357 return -ENOMEM;
358 }
359
360 adev->pm.dpm.ps[i].ps_priv = ps;
361 k = 0;
362 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
363 clock_array_index = power_state->v2.clockInfoIndex[j];
364 if (clock_array_index >= clock_info_array->ucNumEntries)
365 continue;
366 if (k >= CZ_MAX_HARDWARE_POWERLEVELS)
367 break;
368 clock_info = (union pplib_clock_info *)
369 &clock_info_array->clockInfo[clock_array_index *
370 clock_info_array->ucEntrySize];
371 cz_parse_pplib_clock_info(adev, &adev->pm.dpm.ps[i],
372 k, clock_info);
373 k++;
374 }
375 cz_parse_pplib_non_clock_info(adev, &adev->pm.dpm.ps[i],
376 non_clock_info,
377 non_clock_info_array->ucEntrySize);
378 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
379 }
380 adev->pm.dpm.num_ps = state_array->ucNumEntries;
381
382 return 0;
383}
384
385static int cz_process_firmware_header(struct amdgpu_device *adev)
386{
387 struct cz_power_info *pi = cz_get_pi(adev);
388 u32 tmp;
389 int ret;
390
391 ret = cz_read_smc_sram_dword(adev, SMU8_FIRMWARE_HEADER_LOCATION +
392 offsetof(struct SMU8_Firmware_Header,
393 DpmTable),
394 &tmp, pi->sram_end);
395
396 if (ret == 0)
397 pi->dpm_table_start = tmp;
398
399 return ret;
400}
401
402static int cz_dpm_init(struct amdgpu_device *adev)
403{
404 struct cz_power_info *pi;
405 int ret, i;
406
407 pi = kzalloc(sizeof(struct cz_power_info), GFP_KERNEL);
408 if (NULL == pi)
409 return -ENOMEM;
410
411 adev->pm.dpm.priv = pi;
412
413 ret = amdgpu_get_platform_caps(adev);
414 if (ret)
415 goto err;
416
417 ret = amdgpu_parse_extended_power_table(adev);
418 if (ret)
419 goto err;
420
421 pi->sram_end = SMC_RAM_END;
422
423 /* set up DPM defaults */
424 for (i = 0; i < CZ_MAX_HARDWARE_POWERLEVELS; i++)
425 pi->active_target[i] = CZ_AT_DFLT;
426
427 pi->mgcg_cgtt_local0 = 0x0;
428 pi->mgcg_cgtt_local1 = 0x0;
429 pi->clock_slow_down_step = 25000;
430 pi->skip_clock_slow_down = 1;
431 pi->enable_nb_ps_policy = false;
432 pi->caps_power_containment = true;
433 pi->caps_cac = true;
434 pi->didt_enabled = false;
435 if (pi->didt_enabled) {
436 pi->caps_sq_ramping = true;
437 pi->caps_db_ramping = true;
438 pi->caps_td_ramping = true;
439 pi->caps_tcp_ramping = true;
440 }
441 if (amdgpu_pp_feature_mask & SCLK_DEEP_SLEEP_MASK)
442 pi->caps_sclk_ds = true;
443 else
444 pi->caps_sclk_ds = false;
445
446 pi->voting_clients = 0x00c00033;
447 pi->auto_thermal_throttling_enabled = true;
448 pi->bapm_enabled = false;
449 pi->disable_nb_ps3_in_battery = false;
450 pi->voltage_drop_threshold = 0;
451 pi->caps_sclk_throttle_low_notification = false;
452 pi->gfx_pg_threshold = 500;
453 pi->caps_fps = true;
454 /* uvd */
455 pi->caps_uvd_pg = (adev->pg_flags & AMD_PG_SUPPORT_UVD) ? true : false;
456 pi->caps_uvd_dpm = true;
457 /* vce */
458 pi->caps_vce_pg = (adev->pg_flags & AMD_PG_SUPPORT_VCE) ? true : false;
459 pi->caps_vce_dpm = true;
460 /* acp */
461 pi->caps_acp_pg = (adev->pg_flags & AMD_PG_SUPPORT_ACP) ? true : false;
462 pi->caps_acp_dpm = true;
463
464 pi->caps_stable_power_state = false;
465 pi->nb_dpm_enabled_by_driver = true;
466 pi->nb_dpm_enabled = false;
467 pi->caps_voltage_island = false;
468 /* flags which indicate need to upload pptable */
469 pi->need_pptable_upload = true;
470
471 ret = cz_parse_sys_info_table(adev);
472 if (ret)
473 goto err;
474
475 cz_patch_voltage_values(adev);
476 cz_construct_boot_state(adev);
477
478 ret = cz_parse_power_table(adev);
479 if (ret)
480 goto err;
481
482 ret = cz_process_firmware_header(adev);
483 if (ret)
484 goto err;
485
486 pi->dpm_enabled = true;
487 pi->uvd_dynamic_pg = false;
488
489 return 0;
490err:
491 cz_dpm_fini(adev);
492 return ret;
493}
494
495static void cz_dpm_fini(struct amdgpu_device *adev)
496{
497 int i;
498
499 for (i = 0; i < adev->pm.dpm.num_ps; i++)
500 kfree(adev->pm.dpm.ps[i].ps_priv);
501
502 kfree(adev->pm.dpm.ps);
503 kfree(adev->pm.dpm.priv);
504 amdgpu_free_extended_power_table(adev);
505}
506
507#define ixSMUSVI_NB_CURRENTVID 0xD8230044
508#define CURRENT_NB_VID_MASK 0xff000000
509#define CURRENT_NB_VID__SHIFT 24
510#define ixSMUSVI_GFX_CURRENTVID 0xD8230048
511#define CURRENT_GFX_VID_MASK 0xff000000
512#define CURRENT_GFX_VID__SHIFT 24
513
514static void
515cz_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev,
516 struct seq_file *m)
517{
518 struct cz_power_info *pi = cz_get_pi(adev);
519 struct amdgpu_clock_voltage_dependency_table *table =
520 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
521 struct amdgpu_uvd_clock_voltage_dependency_table *uvd_table =
522 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
523 struct amdgpu_vce_clock_voltage_dependency_table *vce_table =
524 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
525 u32 sclk_index = REG_GET_FIELD(RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX),
526 TARGET_AND_CURRENT_PROFILE_INDEX, CURR_SCLK_INDEX);
527 u32 uvd_index = REG_GET_FIELD(RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX_2),
528 TARGET_AND_CURRENT_PROFILE_INDEX_2, CURR_UVD_INDEX);
529 u32 vce_index = REG_GET_FIELD(RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX_2),
530 TARGET_AND_CURRENT_PROFILE_INDEX_2, CURR_VCE_INDEX);
531 u32 sclk, vclk, dclk, ecclk, tmp;
532 u16 vddnb, vddgfx;
533
534 if (sclk_index >= NUM_SCLK_LEVELS) {
535 seq_printf(m, "invalid sclk dpm profile %d\n", sclk_index);
536 } else {
537 sclk = table->entries[sclk_index].clk;
538 seq_printf(m, "%u sclk: %u\n", sclk_index, sclk);
539 }
540
541 tmp = (RREG32_SMC(ixSMUSVI_NB_CURRENTVID) &
542 CURRENT_NB_VID_MASK) >> CURRENT_NB_VID__SHIFT;
543 vddnb = cz_convert_8bit_index_to_voltage(adev, (u16)tmp);
544 tmp = (RREG32_SMC(ixSMUSVI_GFX_CURRENTVID) &
545 CURRENT_GFX_VID_MASK) >> CURRENT_GFX_VID__SHIFT;
546 vddgfx = cz_convert_8bit_index_to_voltage(adev, (u16)tmp);
547 seq_printf(m, "vddnb: %u vddgfx: %u\n", vddnb, vddgfx);
548
549 seq_printf(m, "uvd %sabled\n", pi->uvd_power_gated ? "dis" : "en");
550 if (!pi->uvd_power_gated) {
551 if (uvd_index >= CZ_MAX_HARDWARE_POWERLEVELS) {
552 seq_printf(m, "invalid uvd dpm level %d\n", uvd_index);
553 } else {
554 vclk = uvd_table->entries[uvd_index].vclk;
555 dclk = uvd_table->entries[uvd_index].dclk;
556 seq_printf(m, "%u uvd vclk: %u dclk: %u\n", uvd_index, vclk, dclk);
557 }
558 }
559
560 seq_printf(m, "vce %sabled\n", pi->vce_power_gated ? "dis" : "en");
561 if (!pi->vce_power_gated) {
562 if (vce_index >= CZ_MAX_HARDWARE_POWERLEVELS) {
563 seq_printf(m, "invalid vce dpm level %d\n", vce_index);
564 } else {
565 ecclk = vce_table->entries[vce_index].ecclk;
566 seq_printf(m, "%u vce ecclk: %u\n", vce_index, ecclk);
567 }
568 }
569}
570
571static void cz_dpm_print_power_state(struct amdgpu_device *adev,
572 struct amdgpu_ps *rps)
573{
574 int i;
575 struct cz_ps *ps = cz_get_ps(rps);
576
577 amdgpu_dpm_print_class_info(rps->class, rps->class2);
578 amdgpu_dpm_print_cap_info(rps->caps);
579
580 DRM_INFO("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
581 for (i = 0; i < ps->num_levels; i++) {
582 struct cz_pl *pl = &ps->levels[i];
583
584 DRM_INFO("\t\tpower level %d sclk: %u vddc: %u\n",
585 i, pl->sclk,
586 cz_convert_8bit_index_to_voltage(adev, pl->vddc_index));
587 }
588
589 amdgpu_dpm_print_ps_status(adev, rps);
590}
591
592static void cz_dpm_set_funcs(struct amdgpu_device *adev);
593
594static int cz_dpm_early_init(void *handle)
595{
596 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
597
598 cz_dpm_set_funcs(adev);
599
600 return 0;
601}
602
603
604static int cz_dpm_late_init(void *handle)
605{
606 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
607
608 if (amdgpu_dpm) {
609 int ret;
610 /* init the sysfs and debugfs files late */
611 ret = amdgpu_pm_sysfs_init(adev);
612 if (ret)
613 return ret;
614
615 /* powerdown unused blocks for now */
616 cz_dpm_powergate_uvd(adev, true);
617 cz_dpm_powergate_vce(adev, true);
618 }
619
620 return 0;
621}
622
623static int cz_dpm_sw_init(void *handle)
624{
625 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
626 int ret = 0;
627 /* fix me to add thermal support TODO */
628
629 /* default to balanced state */
630 adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
631 adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
632 adev->pm.dpm.forced_level = AMDGPU_DPM_FORCED_LEVEL_AUTO;
633 adev->pm.default_sclk = adev->clock.default_sclk;
634 adev->pm.default_mclk = adev->clock.default_mclk;
635 adev->pm.current_sclk = adev->clock.default_sclk;
636 adev->pm.current_mclk = adev->clock.default_mclk;
637 adev->pm.int_thermal_type = THERMAL_TYPE_NONE;
638
639 if (amdgpu_dpm == 0)
640 return 0;
641
642 mutex_lock(&adev->pm.mutex);
643 ret = cz_dpm_init(adev);
644 if (ret)
645 goto dpm_init_failed;
646
647 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
648 if (amdgpu_dpm == 1)
649 amdgpu_pm_print_power_states(adev);
650
651 mutex_unlock(&adev->pm.mutex);
652 DRM_INFO("amdgpu: dpm initialized\n");
653
654 return 0;
655
656dpm_init_failed:
657 cz_dpm_fini(adev);
658 mutex_unlock(&adev->pm.mutex);
659 DRM_ERROR("amdgpu: dpm initialization failed\n");
660
661 return ret;
662}
663
664static int cz_dpm_sw_fini(void *handle)
665{
666 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
667
668 mutex_lock(&adev->pm.mutex);
669 amdgpu_pm_sysfs_fini(adev);
670 cz_dpm_fini(adev);
671 mutex_unlock(&adev->pm.mutex);
672
673 return 0;
674}
675
676static void cz_reset_ap_mask(struct amdgpu_device *adev)
677{
678 struct cz_power_info *pi = cz_get_pi(adev);
679
680 pi->active_process_mask = 0;
681}
682
683static int cz_dpm_download_pptable_from_smu(struct amdgpu_device *adev,
684 void **table)
685{
686 return cz_smu_download_pptable(adev, table);
687}
688
689static int cz_dpm_upload_pptable_to_smu(struct amdgpu_device *adev)
690{
691 struct cz_power_info *pi = cz_get_pi(adev);
692 struct SMU8_Fusion_ClkTable *clock_table;
693 struct atom_clock_dividers dividers;
694 void *table = NULL;
695 uint8_t i = 0;
696 int ret = 0;
697
698 struct amdgpu_clock_voltage_dependency_table *vddc_table =
699 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
700 struct amdgpu_clock_voltage_dependency_table *vddgfx_table =
701 &adev->pm.dpm.dyn_state.vddgfx_dependency_on_sclk;
702 struct amdgpu_uvd_clock_voltage_dependency_table *uvd_table =
703 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
704 struct amdgpu_vce_clock_voltage_dependency_table *vce_table =
705 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
706 struct amdgpu_clock_voltage_dependency_table *acp_table =
707 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
708
709 if (!pi->need_pptable_upload)
710 return 0;
711
712 ret = cz_dpm_download_pptable_from_smu(adev, &table);
713 if (ret) {
714 DRM_ERROR("amdgpu: Failed to get power play table from SMU!\n");
715 return -EINVAL;
716 }
717
718 clock_table = (struct SMU8_Fusion_ClkTable *)table;
719 /* patch clock table */
720 if (vddc_table->count > CZ_MAX_HARDWARE_POWERLEVELS ||
721 vddgfx_table->count > CZ_MAX_HARDWARE_POWERLEVELS ||
722 uvd_table->count > CZ_MAX_HARDWARE_POWERLEVELS ||
723 vce_table->count > CZ_MAX_HARDWARE_POWERLEVELS ||
724 acp_table->count > CZ_MAX_HARDWARE_POWERLEVELS) {
725 DRM_ERROR("amdgpu: Invalid Clock Voltage Dependency Table!\n");
726 return -EINVAL;
727 }
728
729 for (i = 0; i < CZ_MAX_HARDWARE_POWERLEVELS; i++) {
730
731 /* vddc sclk */
732 clock_table->SclkBreakdownTable.ClkLevel[i].GnbVid =
733 (i < vddc_table->count) ? (uint8_t)vddc_table->entries[i].v : 0;
734 clock_table->SclkBreakdownTable.ClkLevel[i].Frequency =
735 (i < vddc_table->count) ? vddc_table->entries[i].clk : 0;
736 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
737 clock_table->SclkBreakdownTable.ClkLevel[i].Frequency,
738 false, &dividers);
739 if (ret)
740 return ret;
741 clock_table->SclkBreakdownTable.ClkLevel[i].DfsDid =
742 (uint8_t)dividers.post_divider;
743
744 /* vddgfx sclk */
745 clock_table->SclkBreakdownTable.ClkLevel[i].GfxVid =
746 (i < vddgfx_table->count) ? (uint8_t)vddgfx_table->entries[i].v : 0;
747
748 /* acp breakdown */
749 clock_table->AclkBreakdownTable.ClkLevel[i].GfxVid =
750 (i < acp_table->count) ? (uint8_t)acp_table->entries[i].v : 0;
751 clock_table->AclkBreakdownTable.ClkLevel[i].Frequency =
752 (i < acp_table->count) ? acp_table->entries[i].clk : 0;
753 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
754 clock_table->SclkBreakdownTable.ClkLevel[i].Frequency,
755 false, &dividers);
756 if (ret)
757 return ret;
758 clock_table->AclkBreakdownTable.ClkLevel[i].DfsDid =
759 (uint8_t)dividers.post_divider;
760
761 /* uvd breakdown */
762 clock_table->VclkBreakdownTable.ClkLevel[i].GfxVid =
763 (i < uvd_table->count) ? (uint8_t)uvd_table->entries[i].v : 0;
764 clock_table->VclkBreakdownTable.ClkLevel[i].Frequency =
765 (i < uvd_table->count) ? uvd_table->entries[i].vclk : 0;
766 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
767 clock_table->VclkBreakdownTable.ClkLevel[i].Frequency,
768 false, &dividers);
769 if (ret)
770 return ret;
771 clock_table->VclkBreakdownTable.ClkLevel[i].DfsDid =
772 (uint8_t)dividers.post_divider;
773
774 clock_table->DclkBreakdownTable.ClkLevel[i].GfxVid =
775 (i < uvd_table->count) ? (uint8_t)uvd_table->entries[i].v : 0;
776 clock_table->DclkBreakdownTable.ClkLevel[i].Frequency =
777 (i < uvd_table->count) ? uvd_table->entries[i].dclk : 0;
778 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
779 clock_table->DclkBreakdownTable.ClkLevel[i].Frequency,
780 false, &dividers);
781 if (ret)
782 return ret;
783 clock_table->DclkBreakdownTable.ClkLevel[i].DfsDid =
784 (uint8_t)dividers.post_divider;
785
786 /* vce breakdown */
787 clock_table->EclkBreakdownTable.ClkLevel[i].GfxVid =
788 (i < vce_table->count) ? (uint8_t)vce_table->entries[i].v : 0;
789 clock_table->EclkBreakdownTable.ClkLevel[i].Frequency =
790 (i < vce_table->count) ? vce_table->entries[i].ecclk : 0;
791 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
792 clock_table->EclkBreakdownTable.ClkLevel[i].Frequency,
793 false, &dividers);
794 if (ret)
795 return ret;
796 clock_table->EclkBreakdownTable.ClkLevel[i].DfsDid =
797 (uint8_t)dividers.post_divider;
798 }
799
800 /* its time to upload to SMU */
801 ret = cz_smu_upload_pptable(adev);
802 if (ret) {
803 DRM_ERROR("amdgpu: Failed to put power play table to SMU!\n");
804 return ret;
805 }
806
807 return 0;
808}
809
810static void cz_init_sclk_limit(struct amdgpu_device *adev)
811{
812 struct cz_power_info *pi = cz_get_pi(adev);
813 struct amdgpu_clock_voltage_dependency_table *table =
814 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
815 uint32_t clock = 0, level;
816
817 if (!table || !table->count) {
818 DRM_ERROR("Invalid Voltage Dependency table.\n");
819 return;
820 }
821
822 pi->sclk_dpm.soft_min_clk = 0;
823 pi->sclk_dpm.hard_min_clk = 0;
824 cz_send_msg_to_smc(adev, PPSMC_MSG_GetMaxSclkLevel);
825 level = cz_get_argument(adev);
826 if (level < table->count) {
827 clock = table->entries[level].clk;
828 } else {
829 DRM_ERROR("Invalid SLCK Voltage Dependency table entry.\n");
830 clock = table->entries[table->count - 1].clk;
831 }
832
833 pi->sclk_dpm.soft_max_clk = clock;
834 pi->sclk_dpm.hard_max_clk = clock;
835
836}
837
838static void cz_init_uvd_limit(struct amdgpu_device *adev)
839{
840 struct cz_power_info *pi = cz_get_pi(adev);
841 struct amdgpu_uvd_clock_voltage_dependency_table *table =
842 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
843 uint32_t clock = 0, level;
844
845 if (!table || !table->count) {
846 DRM_ERROR("Invalid Voltage Dependency table.\n");
847 return;
848 }
849
850 pi->uvd_dpm.soft_min_clk = 0;
851 pi->uvd_dpm.hard_min_clk = 0;
852 cz_send_msg_to_smc(adev, PPSMC_MSG_GetMaxUvdLevel);
853 level = cz_get_argument(adev);
854 if (level < table->count) {
855 clock = table->entries[level].vclk;
856 } else {
857 DRM_ERROR("Invalid UVD Voltage Dependency table entry.\n");
858 clock = table->entries[table->count - 1].vclk;
859 }
860
861 pi->uvd_dpm.soft_max_clk = clock;
862 pi->uvd_dpm.hard_max_clk = clock;
863
864}
865
866static void cz_init_vce_limit(struct amdgpu_device *adev)
867{
868 struct cz_power_info *pi = cz_get_pi(adev);
869 struct amdgpu_vce_clock_voltage_dependency_table *table =
870 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
871 uint32_t clock = 0, level;
872
873 if (!table || !table->count) {
874 DRM_ERROR("Invalid Voltage Dependency table.\n");
875 return;
876 }
877
878 pi->vce_dpm.soft_min_clk = table->entries[0].ecclk;
879 pi->vce_dpm.hard_min_clk = table->entries[0].ecclk;
880 cz_send_msg_to_smc(adev, PPSMC_MSG_GetMaxEclkLevel);
881 level = cz_get_argument(adev);
882 if (level < table->count) {
883 clock = table->entries[level].ecclk;
884 } else {
885 /* future BIOS would fix this error */
886 DRM_ERROR("Invalid VCE Voltage Dependency table entry.\n");
887 clock = table->entries[table->count - 1].ecclk;
888 }
889
890 pi->vce_dpm.soft_max_clk = clock;
891 pi->vce_dpm.hard_max_clk = clock;
892
893}
894
895static void cz_init_acp_limit(struct amdgpu_device *adev)
896{
897 struct cz_power_info *pi = cz_get_pi(adev);
898 struct amdgpu_clock_voltage_dependency_table *table =
899 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
900 uint32_t clock = 0, level;
901
902 if (!table || !table->count) {
903 DRM_ERROR("Invalid Voltage Dependency table.\n");
904 return;
905 }
906
907 pi->acp_dpm.soft_min_clk = 0;
908 pi->acp_dpm.hard_min_clk = 0;
909 cz_send_msg_to_smc(adev, PPSMC_MSG_GetMaxAclkLevel);
910 level = cz_get_argument(adev);
911 if (level < table->count) {
912 clock = table->entries[level].clk;
913 } else {
914 DRM_ERROR("Invalid ACP Voltage Dependency table entry.\n");
915 clock = table->entries[table->count - 1].clk;
916 }
917
918 pi->acp_dpm.soft_max_clk = clock;
919 pi->acp_dpm.hard_max_clk = clock;
920
921}
922
923static void cz_init_pg_state(struct amdgpu_device *adev)
924{
925 struct cz_power_info *pi = cz_get_pi(adev);
926
927 pi->uvd_power_gated = false;
928 pi->vce_power_gated = false;
929 pi->acp_power_gated = false;
930
931}
932
933static void cz_init_sclk_threshold(struct amdgpu_device *adev)
934{
935 struct cz_power_info *pi = cz_get_pi(adev);
936
937 pi->low_sclk_interrupt_threshold = 0;
938}
939
940static void cz_dpm_setup_asic(struct amdgpu_device *adev)
941{
942 cz_reset_ap_mask(adev);
943 cz_dpm_upload_pptable_to_smu(adev);
944 cz_init_sclk_limit(adev);
945 cz_init_uvd_limit(adev);
946 cz_init_vce_limit(adev);
947 cz_init_acp_limit(adev);
948 cz_init_pg_state(adev);
949 cz_init_sclk_threshold(adev);
950
951}
952
953static bool cz_check_smu_feature(struct amdgpu_device *adev,
954 uint32_t feature)
955{
956 uint32_t smu_feature = 0;
957 int ret;
958
959 ret = cz_send_msg_to_smc_with_parameter(adev,
960 PPSMC_MSG_GetFeatureStatus, 0);
961 if (ret) {
962 DRM_ERROR("Failed to get SMU features from SMC.\n");
963 return false;
964 } else {
965 smu_feature = cz_get_argument(adev);
966 if (feature & smu_feature)
967 return true;
968 }
969
970 return false;
971}
972
973static bool cz_check_for_dpm_enabled(struct amdgpu_device *adev)
974{
975 if (cz_check_smu_feature(adev,
976 SMU_EnabledFeatureScoreboard_SclkDpmOn))
977 return true;
978
979 return false;
980}
981
982static void cz_program_voting_clients(struct amdgpu_device *adev)
983{
984 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_0, PPCZ_VOTINGRIGHTSCLIENTS_DFLT0);
985}
986
987static void cz_clear_voting_clients(struct amdgpu_device *adev)
988{
989 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_0, 0);
990}
991
992static int cz_start_dpm(struct amdgpu_device *adev)
993{
994 int ret = 0;
995
996 if (amdgpu_dpm) {
997 ret = cz_send_msg_to_smc_with_parameter(adev,
998 PPSMC_MSG_EnableAllSmuFeatures, SCLK_DPM_MASK);
999 if (ret) {
1000 DRM_ERROR("SMU feature: SCLK_DPM enable failed\n");
1001 return -EINVAL;
1002 }
1003 }
1004
1005 return 0;
1006}
1007
1008static int cz_stop_dpm(struct amdgpu_device *adev)
1009{
1010 int ret = 0;
1011
1012 if (amdgpu_dpm && adev->pm.dpm_enabled) {
1013 ret = cz_send_msg_to_smc_with_parameter(adev,
1014 PPSMC_MSG_DisableAllSmuFeatures, SCLK_DPM_MASK);
1015 if (ret) {
1016 DRM_ERROR("SMU feature: SCLK_DPM disable failed\n");
1017 return -EINVAL;
1018 }
1019 }
1020
1021 return 0;
1022}
1023
1024static uint32_t cz_get_sclk_level(struct amdgpu_device *adev,
1025 uint32_t clock, uint16_t msg)
1026{
1027 int i = 0;
1028 struct amdgpu_clock_voltage_dependency_table *table =
1029 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
1030
1031 switch (msg) {
1032 case PPSMC_MSG_SetSclkSoftMin:
1033 case PPSMC_MSG_SetSclkHardMin:
1034 for (i = 0; i < table->count; i++)
1035 if (clock <= table->entries[i].clk)
1036 break;
1037 if (i == table->count)
1038 i = table->count - 1;
1039 break;
1040 case PPSMC_MSG_SetSclkSoftMax:
1041 case PPSMC_MSG_SetSclkHardMax:
1042 for (i = table->count - 1; i >= 0; i--)
1043 if (clock >= table->entries[i].clk)
1044 break;
1045 if (i < 0)
1046 i = 0;
1047 break;
1048 default:
1049 break;
1050 }
1051
1052 return i;
1053}
1054
1055static uint32_t cz_get_eclk_level(struct amdgpu_device *adev,
1056 uint32_t clock, uint16_t msg)
1057{
1058 int i = 0;
1059 struct amdgpu_vce_clock_voltage_dependency_table *table =
1060 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
1061
1062 if (table->count == 0)
1063 return 0;
1064
1065 switch (msg) {
1066 case PPSMC_MSG_SetEclkSoftMin:
1067 case PPSMC_MSG_SetEclkHardMin:
1068 for (i = 0; i < table->count-1; i++)
1069 if (clock <= table->entries[i].ecclk)
1070 break;
1071 break;
1072 case PPSMC_MSG_SetEclkSoftMax:
1073 case PPSMC_MSG_SetEclkHardMax:
1074 for (i = table->count - 1; i > 0; i--)
1075 if (clock >= table->entries[i].ecclk)
1076 break;
1077 break;
1078 default:
1079 break;
1080 }
1081
1082 return i;
1083}
1084
1085static uint32_t cz_get_uvd_level(struct amdgpu_device *adev,
1086 uint32_t clock, uint16_t msg)
1087{
1088 int i = 0;
1089 struct amdgpu_uvd_clock_voltage_dependency_table *table =
1090 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
1091
1092 switch (msg) {
1093 case PPSMC_MSG_SetUvdSoftMin:
1094 case PPSMC_MSG_SetUvdHardMin:
1095 for (i = 0; i < table->count; i++)
1096 if (clock <= table->entries[i].vclk)
1097 break;
1098 if (i == table->count)
1099 i = table->count - 1;
1100 break;
1101 case PPSMC_MSG_SetUvdSoftMax:
1102 case PPSMC_MSG_SetUvdHardMax:
1103 for (i = table->count - 1; i >= 0; i--)
1104 if (clock >= table->entries[i].vclk)
1105 break;
1106 if (i < 0)
1107 i = 0;
1108 break;
1109 default:
1110 break;
1111 }
1112
1113 return i;
1114}
1115
1116static int cz_program_bootup_state(struct amdgpu_device *adev)
1117{
1118 struct cz_power_info *pi = cz_get_pi(adev);
1119 uint32_t soft_min_clk = 0;
1120 uint32_t soft_max_clk = 0;
1121 int ret = 0;
1122
1123 pi->sclk_dpm.soft_min_clk = pi->sys_info.bootup_sclk;
1124 pi->sclk_dpm.soft_max_clk = pi->sys_info.bootup_sclk;
1125
1126 soft_min_clk = cz_get_sclk_level(adev,
1127 pi->sclk_dpm.soft_min_clk,
1128 PPSMC_MSG_SetSclkSoftMin);
1129 soft_max_clk = cz_get_sclk_level(adev,
1130 pi->sclk_dpm.soft_max_clk,
1131 PPSMC_MSG_SetSclkSoftMax);
1132
1133 ret = cz_send_msg_to_smc_with_parameter(adev,
1134 PPSMC_MSG_SetSclkSoftMin, soft_min_clk);
1135 if (ret)
1136 return -EINVAL;
1137
1138 ret = cz_send_msg_to_smc_with_parameter(adev,
1139 PPSMC_MSG_SetSclkSoftMax, soft_max_clk);
1140 if (ret)
1141 return -EINVAL;
1142
1143 return 0;
1144}
1145
1146/* TODO */
1147static int cz_disable_cgpg(struct amdgpu_device *adev)
1148{
1149 return 0;
1150}
1151
1152/* TODO */
1153static int cz_enable_cgpg(struct amdgpu_device *adev)
1154{
1155 return 0;
1156}
1157
1158/* TODO */
1159static int cz_program_pt_config_registers(struct amdgpu_device *adev)
1160{
1161 return 0;
1162}
1163
1164static void cz_do_enable_didt(struct amdgpu_device *adev, bool enable)
1165{
1166 struct cz_power_info *pi = cz_get_pi(adev);
1167 uint32_t reg = 0;
1168
1169 if (pi->caps_sq_ramping) {
1170 reg = RREG32_DIDT(ixDIDT_SQ_CTRL0);
1171 if (enable)
1172 reg = REG_SET_FIELD(reg, DIDT_SQ_CTRL0, DIDT_CTRL_EN, 1);
1173 else
1174 reg = REG_SET_FIELD(reg, DIDT_SQ_CTRL0, DIDT_CTRL_EN, 0);
1175 WREG32_DIDT(ixDIDT_SQ_CTRL0, reg);
1176 }
1177 if (pi->caps_db_ramping) {
1178 reg = RREG32_DIDT(ixDIDT_DB_CTRL0);
1179 if (enable)
1180 reg = REG_SET_FIELD(reg, DIDT_DB_CTRL0, DIDT_CTRL_EN, 1);
1181 else
1182 reg = REG_SET_FIELD(reg, DIDT_DB_CTRL0, DIDT_CTRL_EN, 0);
1183 WREG32_DIDT(ixDIDT_DB_CTRL0, reg);
1184 }
1185 if (pi->caps_td_ramping) {
1186 reg = RREG32_DIDT(ixDIDT_TD_CTRL0);
1187 if (enable)
1188 reg = REG_SET_FIELD(reg, DIDT_TD_CTRL0, DIDT_CTRL_EN, 1);
1189 else
1190 reg = REG_SET_FIELD(reg, DIDT_TD_CTRL0, DIDT_CTRL_EN, 0);
1191 WREG32_DIDT(ixDIDT_TD_CTRL0, reg);
1192 }
1193 if (pi->caps_tcp_ramping) {
1194 reg = RREG32_DIDT(ixDIDT_TCP_CTRL0);
1195 if (enable)
1196 reg = REG_SET_FIELD(reg, DIDT_SQ_CTRL0, DIDT_CTRL_EN, 1);
1197 else
1198 reg = REG_SET_FIELD(reg, DIDT_SQ_CTRL0, DIDT_CTRL_EN, 0);
1199 WREG32_DIDT(ixDIDT_TCP_CTRL0, reg);
1200 }
1201
1202}
1203
1204static int cz_enable_didt(struct amdgpu_device *adev, bool enable)
1205{
1206 struct cz_power_info *pi = cz_get_pi(adev);
1207 int ret;
1208
1209 if (pi->caps_sq_ramping || pi->caps_db_ramping ||
1210 pi->caps_td_ramping || pi->caps_tcp_ramping) {
1211 if (adev->gfx.gfx_current_status != AMDGPU_GFX_SAFE_MODE) {
1212 ret = cz_disable_cgpg(adev);
1213 if (ret) {
1214 DRM_ERROR("Pre Di/Dt disable cg/pg failed\n");
1215 return -EINVAL;
1216 }
1217 adev->gfx.gfx_current_status = AMDGPU_GFX_SAFE_MODE;
1218 }
1219
1220 ret = cz_program_pt_config_registers(adev);
1221 if (ret) {
1222 DRM_ERROR("Di/Dt config failed\n");
1223 return -EINVAL;
1224 }
1225 cz_do_enable_didt(adev, enable);
1226
1227 if (adev->gfx.gfx_current_status == AMDGPU_GFX_SAFE_MODE) {
1228 ret = cz_enable_cgpg(adev);
1229 if (ret) {
1230 DRM_ERROR("Post Di/Dt enable cg/pg failed\n");
1231 return -EINVAL;
1232 }
1233 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
1234 }
1235 }
1236
1237 return 0;
1238}
1239
1240/* TODO */
1241static void cz_reset_acp_boot_level(struct amdgpu_device *adev)
1242{
1243}
1244
1245static void cz_update_current_ps(struct amdgpu_device *adev,
1246 struct amdgpu_ps *rps)
1247{
1248 struct cz_power_info *pi = cz_get_pi(adev);
1249 struct cz_ps *ps = cz_get_ps(rps);
1250
1251 pi->current_ps = *ps;
1252 pi->current_rps = *rps;
1253 pi->current_rps.ps_priv = &pi->current_ps;
1254 adev->pm.dpm.current_ps = &pi->current_rps;
1255
1256}
1257
1258static void cz_update_requested_ps(struct amdgpu_device *adev,
1259 struct amdgpu_ps *rps)
1260{
1261 struct cz_power_info *pi = cz_get_pi(adev);
1262 struct cz_ps *ps = cz_get_ps(rps);
1263
1264 pi->requested_ps = *ps;
1265 pi->requested_rps = *rps;
1266 pi->requested_rps.ps_priv = &pi->requested_ps;
1267 adev->pm.dpm.requested_ps = &pi->requested_rps;
1268
1269}
1270
1271/* PP arbiter support needed TODO */
1272static void cz_apply_state_adjust_rules(struct amdgpu_device *adev,
1273 struct amdgpu_ps *new_rps,
1274 struct amdgpu_ps *old_rps)
1275{
1276 struct cz_ps *ps = cz_get_ps(new_rps);
1277 struct cz_power_info *pi = cz_get_pi(adev);
1278 struct amdgpu_clock_and_voltage_limits *limits =
1279 &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
1280 /* 10kHz memory clock */
1281 uint32_t mclk = 0;
1282
1283 ps->force_high = false;
1284 ps->need_dfs_bypass = true;
1285 pi->video_start = new_rps->dclk || new_rps->vclk ||
1286 new_rps->evclk || new_rps->ecclk;
1287
1288 if ((new_rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==
1289 ATOM_PPLIB_CLASSIFICATION_UI_BATTERY)
1290 pi->battery_state = true;
1291 else
1292 pi->battery_state = false;
1293
1294 if (pi->caps_stable_power_state)
1295 mclk = limits->mclk;
1296
1297 if (mclk > pi->sys_info.nbp_memory_clock[CZ_NUM_NBPMEMORY_CLOCK - 1])
1298 ps->force_high = true;
1299
1300}
1301
1302static int cz_dpm_enable(struct amdgpu_device *adev)
1303{
1304 const char *chip_name;
1305 int ret = 0;
1306
1307 /* renable will hang up SMU, so check first */
1308 if (cz_check_for_dpm_enabled(adev))
1309 return -EINVAL;
1310
1311 cz_program_voting_clients(adev);
1312
1313 switch (adev->asic_type) {
1314 case CHIP_CARRIZO:
1315 chip_name = "carrizo";
1316 break;
1317 case CHIP_STONEY:
1318 chip_name = "stoney";
1319 break;
1320 default:
1321 BUG();
1322 }
1323
1324
1325 ret = cz_start_dpm(adev);
1326 if (ret) {
1327 DRM_ERROR("%s DPM enable failed\n", chip_name);
1328 return -EINVAL;
1329 }
1330
1331 ret = cz_program_bootup_state(adev);
1332 if (ret) {
1333 DRM_ERROR("%s bootup state program failed\n", chip_name);
1334 return -EINVAL;
1335 }
1336
1337 ret = cz_enable_didt(adev, true);
1338 if (ret) {
1339 DRM_ERROR("%s enable di/dt failed\n", chip_name);
1340 return -EINVAL;
1341 }
1342
1343 cz_reset_acp_boot_level(adev);
1344 cz_update_current_ps(adev, adev->pm.dpm.boot_ps);
1345
1346 return 0;
1347}
1348
1349static int cz_dpm_hw_init(void *handle)
1350{
1351 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1352 int ret = 0;
1353
1354 mutex_lock(&adev->pm.mutex);
1355
1356 /* smu init only needs to be called at startup, not resume.
1357 * It should be in sw_init, but requires the fw info gathered
1358 * in sw_init from other IP modules.
1359 */
1360 ret = cz_smu_init(adev);
1361 if (ret) {
1362 DRM_ERROR("amdgpu: smc initialization failed\n");
1363 mutex_unlock(&adev->pm.mutex);
1364 return ret;
1365 }
1366
1367 /* do the actual fw loading */
1368 ret = cz_smu_start(adev);
1369 if (ret) {
1370 DRM_ERROR("amdgpu: smc start failed\n");
1371 mutex_unlock(&adev->pm.mutex);
1372 return ret;
1373 }
1374
1375 if (!amdgpu_dpm) {
1376 adev->pm.dpm_enabled = false;
1377 mutex_unlock(&adev->pm.mutex);
1378 return ret;
1379 }
1380
1381 /* cz dpm setup asic */
1382 cz_dpm_setup_asic(adev);
1383
1384 /* cz dpm enable */
1385 ret = cz_dpm_enable(adev);
1386 if (ret)
1387 adev->pm.dpm_enabled = false;
1388 else
1389 adev->pm.dpm_enabled = true;
1390
1391 mutex_unlock(&adev->pm.mutex);
1392
1393 return 0;
1394}
1395
1396static int cz_dpm_disable(struct amdgpu_device *adev)
1397{
1398 int ret = 0;
1399
1400 if (!cz_check_for_dpm_enabled(adev))
1401 return -EINVAL;
1402
1403 ret = cz_enable_didt(adev, false);
1404 if (ret) {
1405 DRM_ERROR("disable di/dt failed\n");
1406 return -EINVAL;
1407 }
1408
1409 /* powerup blocks */
1410 cz_dpm_powergate_uvd(adev, false);
1411 cz_dpm_powergate_vce(adev, false);
1412
1413 cz_clear_voting_clients(adev);
1414 cz_stop_dpm(adev);
1415 cz_update_current_ps(adev, adev->pm.dpm.boot_ps);
1416
1417 return 0;
1418}
1419
1420static int cz_dpm_hw_fini(void *handle)
1421{
1422 int ret = 0;
1423 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1424
1425 mutex_lock(&adev->pm.mutex);
1426
1427 /* smu fini only needs to be called at teardown, not suspend.
1428 * It should be in sw_fini, but we put it here for symmetry
1429 * with smu init.
1430 */
1431 cz_smu_fini(adev);
1432
1433 if (adev->pm.dpm_enabled) {
1434 ret = cz_dpm_disable(adev);
1435
1436 adev->pm.dpm.current_ps =
1437 adev->pm.dpm.requested_ps =
1438 adev->pm.dpm.boot_ps;
1439 }
1440
1441 adev->pm.dpm_enabled = false;
1442
1443 mutex_unlock(&adev->pm.mutex);
1444
1445 return ret;
1446}
1447
1448static int cz_dpm_suspend(void *handle)
1449{
1450 int ret = 0;
1451 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1452
1453 if (adev->pm.dpm_enabled) {
1454 mutex_lock(&adev->pm.mutex);
1455
1456 ret = cz_dpm_disable(adev);
1457
1458 adev->pm.dpm.current_ps =
1459 adev->pm.dpm.requested_ps =
1460 adev->pm.dpm.boot_ps;
1461
1462 mutex_unlock(&adev->pm.mutex);
1463 }
1464
1465 return ret;
1466}
1467
1468static int cz_dpm_resume(void *handle)
1469{
1470 int ret = 0;
1471 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1472
1473 mutex_lock(&adev->pm.mutex);
1474
1475 /* do the actual fw loading */
1476 ret = cz_smu_start(adev);
1477 if (ret) {
1478 DRM_ERROR("amdgpu: smc start failed\n");
1479 mutex_unlock(&adev->pm.mutex);
1480 return ret;
1481 }
1482
1483 if (!amdgpu_dpm) {
1484 adev->pm.dpm_enabled = false;
1485 mutex_unlock(&adev->pm.mutex);
1486 return ret;
1487 }
1488
1489 /* cz dpm setup asic */
1490 cz_dpm_setup_asic(adev);
1491
1492 /* cz dpm enable */
1493 ret = cz_dpm_enable(adev);
1494 if (ret)
1495 adev->pm.dpm_enabled = false;
1496 else
1497 adev->pm.dpm_enabled = true;
1498
1499 mutex_unlock(&adev->pm.mutex);
1500 /* upon resume, re-compute the clocks */
1501 if (adev->pm.dpm_enabled)
1502 amdgpu_pm_compute_clocks(adev);
1503
1504 return 0;
1505}
1506
1507static int cz_dpm_set_clockgating_state(void *handle,
1508 enum amd_clockgating_state state)
1509{
1510 return 0;
1511}
1512
1513static int cz_dpm_set_powergating_state(void *handle,
1514 enum amd_powergating_state state)
1515{
1516 return 0;
1517}
1518
1519static int cz_dpm_get_temperature(struct amdgpu_device *adev)
1520{
1521 int actual_temp = 0;
1522 uint32_t val = RREG32_SMC(ixTHM_TCON_CUR_TMP);
1523 uint32_t temp = REG_GET_FIELD(val, THM_TCON_CUR_TMP, CUR_TEMP);
1524
1525 if (REG_GET_FIELD(val, THM_TCON_CUR_TMP, CUR_TEMP_RANGE_SEL))
1526 actual_temp = 1000 * ((temp / 8) - 49);
1527 else
1528 actual_temp = 1000 * (temp / 8);
1529
1530 return actual_temp;
1531}
1532
1533static int cz_dpm_pre_set_power_state(struct amdgpu_device *adev)
1534{
1535 struct cz_power_info *pi = cz_get_pi(adev);
1536 struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps;
1537 struct amdgpu_ps *new_ps = &requested_ps;
1538
1539 cz_update_requested_ps(adev, new_ps);
1540 cz_apply_state_adjust_rules(adev, &pi->requested_rps,
1541 &pi->current_rps);
1542
1543 return 0;
1544}
1545
1546static int cz_dpm_update_sclk_limit(struct amdgpu_device *adev)
1547{
1548 struct cz_power_info *pi = cz_get_pi(adev);
1549 struct amdgpu_clock_and_voltage_limits *limits =
1550 &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
1551 uint32_t clock, stable_ps_clock = 0;
1552
1553 clock = pi->sclk_dpm.soft_min_clk;
1554
1555 if (pi->caps_stable_power_state) {
1556 stable_ps_clock = limits->sclk * 75 / 100;
1557 if (clock < stable_ps_clock)
1558 clock = stable_ps_clock;
1559 }
1560
1561 if (clock != pi->sclk_dpm.soft_min_clk) {
1562 pi->sclk_dpm.soft_min_clk = clock;
1563 cz_send_msg_to_smc_with_parameter(adev,
1564 PPSMC_MSG_SetSclkSoftMin,
1565 cz_get_sclk_level(adev, clock,
1566 PPSMC_MSG_SetSclkSoftMin));
1567 }
1568
1569 if (pi->caps_stable_power_state &&
1570 pi->sclk_dpm.soft_max_clk != clock) {
1571 pi->sclk_dpm.soft_max_clk = clock;
1572 cz_send_msg_to_smc_with_parameter(adev,
1573 PPSMC_MSG_SetSclkSoftMax,
1574 cz_get_sclk_level(adev, clock,
1575 PPSMC_MSG_SetSclkSoftMax));
1576 } else {
1577 cz_send_msg_to_smc_with_parameter(adev,
1578 PPSMC_MSG_SetSclkSoftMax,
1579 cz_get_sclk_level(adev,
1580 pi->sclk_dpm.soft_max_clk,
1581 PPSMC_MSG_SetSclkSoftMax));
1582 }
1583
1584 return 0;
1585}
1586
1587static int cz_dpm_set_deep_sleep_sclk_threshold(struct amdgpu_device *adev)
1588{
1589 struct cz_power_info *pi = cz_get_pi(adev);
1590
1591 if (pi->caps_sclk_ds) {
1592 cz_send_msg_to_smc_with_parameter(adev,
1593 PPSMC_MSG_SetMinDeepSleepSclk,
1594 CZ_MIN_DEEP_SLEEP_SCLK);
1595 }
1596
1597 return 0;
1598}
1599
1600/* ?? without dal support, is this still needed in setpowerstate list*/
1601static int cz_dpm_set_watermark_threshold(struct amdgpu_device *adev)
1602{
1603 struct cz_power_info *pi = cz_get_pi(adev);
1604
1605 cz_send_msg_to_smc_with_parameter(adev,
1606 PPSMC_MSG_SetWatermarkFrequency,
1607 pi->sclk_dpm.soft_max_clk);
1608
1609 return 0;
1610}
1611
1612static int cz_dpm_enable_nbdpm(struct amdgpu_device *adev)
1613{
1614 int ret = 0;
1615 struct cz_power_info *pi = cz_get_pi(adev);
1616
1617 /* also depend on dal NBPStateDisableRequired */
1618 if (pi->nb_dpm_enabled_by_driver && !pi->nb_dpm_enabled) {
1619 ret = cz_send_msg_to_smc_with_parameter(adev,
1620 PPSMC_MSG_EnableAllSmuFeatures,
1621 NB_DPM_MASK);
1622 if (ret) {
1623 DRM_ERROR("amdgpu: nb dpm enable failed\n");
1624 return ret;
1625 }
1626 pi->nb_dpm_enabled = true;
1627 }
1628
1629 return ret;
1630}
1631
1632static void cz_dpm_nbdpm_lm_pstate_enable(struct amdgpu_device *adev,
1633 bool enable)
1634{
1635 if (enable)
1636 cz_send_msg_to_smc(adev, PPSMC_MSG_EnableLowMemoryPstate);
1637 else
1638 cz_send_msg_to_smc(adev, PPSMC_MSG_DisableLowMemoryPstate);
1639
1640}
1641
1642static int cz_dpm_update_low_memory_pstate(struct amdgpu_device *adev)
1643{
1644 struct cz_power_info *pi = cz_get_pi(adev);
1645 struct cz_ps *ps = &pi->requested_ps;
1646
1647 if (pi->sys_info.nb_dpm_enable) {
1648 if (ps->force_high)
1649 cz_dpm_nbdpm_lm_pstate_enable(adev, false);
1650 else
1651 cz_dpm_nbdpm_lm_pstate_enable(adev, true);
1652 }
1653
1654 return 0;
1655}
1656
1657/* with dpm enabled */
1658static int cz_dpm_set_power_state(struct amdgpu_device *adev)
1659{
1660 cz_dpm_update_sclk_limit(adev);
1661 cz_dpm_set_deep_sleep_sclk_threshold(adev);
1662 cz_dpm_set_watermark_threshold(adev);
1663 cz_dpm_enable_nbdpm(adev);
1664 cz_dpm_update_low_memory_pstate(adev);
1665
1666 return 0;
1667}
1668
1669static void cz_dpm_post_set_power_state(struct amdgpu_device *adev)
1670{
1671 struct cz_power_info *pi = cz_get_pi(adev);
1672 struct amdgpu_ps *ps = &pi->requested_rps;
1673
1674 cz_update_current_ps(adev, ps);
1675}
1676
1677static int cz_dpm_force_highest(struct amdgpu_device *adev)
1678{
1679 struct cz_power_info *pi = cz_get_pi(adev);
1680 int ret = 0;
1681
1682 if (pi->sclk_dpm.soft_min_clk != pi->sclk_dpm.soft_max_clk) {
1683 pi->sclk_dpm.soft_min_clk =
1684 pi->sclk_dpm.soft_max_clk;
1685 ret = cz_send_msg_to_smc_with_parameter(adev,
1686 PPSMC_MSG_SetSclkSoftMin,
1687 cz_get_sclk_level(adev,
1688 pi->sclk_dpm.soft_min_clk,
1689 PPSMC_MSG_SetSclkSoftMin));
1690 if (ret)
1691 return ret;
1692 }
1693
1694 return ret;
1695}
1696
1697static int cz_dpm_force_lowest(struct amdgpu_device *adev)
1698{
1699 struct cz_power_info *pi = cz_get_pi(adev);
1700 int ret = 0;
1701
1702 if (pi->sclk_dpm.soft_max_clk != pi->sclk_dpm.soft_min_clk) {
1703 pi->sclk_dpm.soft_max_clk = pi->sclk_dpm.soft_min_clk;
1704 ret = cz_send_msg_to_smc_with_parameter(adev,
1705 PPSMC_MSG_SetSclkSoftMax,
1706 cz_get_sclk_level(adev,
1707 pi->sclk_dpm.soft_max_clk,
1708 PPSMC_MSG_SetSclkSoftMax));
1709 if (ret)
1710 return ret;
1711 }
1712
1713 return ret;
1714}
1715
1716static uint32_t cz_dpm_get_max_sclk_level(struct amdgpu_device *adev)
1717{
1718 struct cz_power_info *pi = cz_get_pi(adev);
1719
1720 if (!pi->max_sclk_level) {
1721 cz_send_msg_to_smc(adev, PPSMC_MSG_GetMaxSclkLevel);
1722 pi->max_sclk_level = cz_get_argument(adev) + 1;
1723 }
1724
1725 if (pi->max_sclk_level > CZ_MAX_HARDWARE_POWERLEVELS) {
1726 DRM_ERROR("Invalid max sclk level!\n");
1727 return -EINVAL;
1728 }
1729
1730 return pi->max_sclk_level;
1731}
1732
1733static int cz_dpm_unforce_dpm_levels(struct amdgpu_device *adev)
1734{
1735 struct cz_power_info *pi = cz_get_pi(adev);
1736 struct amdgpu_clock_voltage_dependency_table *dep_table =
1737 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
1738 uint32_t level = 0;
1739 int ret = 0;
1740
1741 pi->sclk_dpm.soft_min_clk = dep_table->entries[0].clk;
1742 level = cz_dpm_get_max_sclk_level(adev) - 1;
1743 if (level < dep_table->count)
1744 pi->sclk_dpm.soft_max_clk = dep_table->entries[level].clk;
1745 else
1746 pi->sclk_dpm.soft_max_clk =
1747 dep_table->entries[dep_table->count - 1].clk;
1748
1749 /* get min/max sclk soft value
1750 * notify SMU to execute */
1751 ret = cz_send_msg_to_smc_with_parameter(adev,
1752 PPSMC_MSG_SetSclkSoftMin,
1753 cz_get_sclk_level(adev,
1754 pi->sclk_dpm.soft_min_clk,
1755 PPSMC_MSG_SetSclkSoftMin));
1756 if (ret)
1757 return ret;
1758
1759 ret = cz_send_msg_to_smc_with_parameter(adev,
1760 PPSMC_MSG_SetSclkSoftMax,
1761 cz_get_sclk_level(adev,
1762 pi->sclk_dpm.soft_max_clk,
1763 PPSMC_MSG_SetSclkSoftMax));
1764 if (ret)
1765 return ret;
1766
1767 DRM_DEBUG("DPM unforce state min=%d, max=%d.\n",
1768 pi->sclk_dpm.soft_min_clk,
1769 pi->sclk_dpm.soft_max_clk);
1770
1771 return 0;
1772}
1773
1774static int cz_dpm_uvd_force_highest(struct amdgpu_device *adev)
1775{
1776 struct cz_power_info *pi = cz_get_pi(adev);
1777 int ret = 0;
1778
1779 if (pi->uvd_dpm.soft_min_clk != pi->uvd_dpm.soft_max_clk) {
1780 pi->uvd_dpm.soft_min_clk =
1781 pi->uvd_dpm.soft_max_clk;
1782 ret = cz_send_msg_to_smc_with_parameter(adev,
1783 PPSMC_MSG_SetUvdSoftMin,
1784 cz_get_uvd_level(adev,
1785 pi->uvd_dpm.soft_min_clk,
1786 PPSMC_MSG_SetUvdSoftMin));
1787 if (ret)
1788 return ret;
1789 }
1790
1791 return ret;
1792}
1793
1794static int cz_dpm_uvd_force_lowest(struct amdgpu_device *adev)
1795{
1796 struct cz_power_info *pi = cz_get_pi(adev);
1797 int ret = 0;
1798
1799 if (pi->uvd_dpm.soft_max_clk != pi->uvd_dpm.soft_min_clk) {
1800 pi->uvd_dpm.soft_max_clk = pi->uvd_dpm.soft_min_clk;
1801 ret = cz_send_msg_to_smc_with_parameter(adev,
1802 PPSMC_MSG_SetUvdSoftMax,
1803 cz_get_uvd_level(adev,
1804 pi->uvd_dpm.soft_max_clk,
1805 PPSMC_MSG_SetUvdSoftMax));
1806 if (ret)
1807 return ret;
1808 }
1809
1810 return ret;
1811}
1812
1813static uint32_t cz_dpm_get_max_uvd_level(struct amdgpu_device *adev)
1814{
1815 struct cz_power_info *pi = cz_get_pi(adev);
1816
1817 if (!pi->max_uvd_level) {
1818 cz_send_msg_to_smc(adev, PPSMC_MSG_GetMaxUvdLevel);
1819 pi->max_uvd_level = cz_get_argument(adev) + 1;
1820 }
1821
1822 if (pi->max_uvd_level > CZ_MAX_HARDWARE_POWERLEVELS) {
1823 DRM_ERROR("Invalid max uvd level!\n");
1824 return -EINVAL;
1825 }
1826
1827 return pi->max_uvd_level;
1828}
1829
1830static int cz_dpm_unforce_uvd_dpm_levels(struct amdgpu_device *adev)
1831{
1832 struct cz_power_info *pi = cz_get_pi(adev);
1833 struct amdgpu_uvd_clock_voltage_dependency_table *dep_table =
1834 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
1835 uint32_t level = 0;
1836 int ret = 0;
1837
1838 pi->uvd_dpm.soft_min_clk = dep_table->entries[0].vclk;
1839 level = cz_dpm_get_max_uvd_level(adev) - 1;
1840 if (level < dep_table->count)
1841 pi->uvd_dpm.soft_max_clk = dep_table->entries[level].vclk;
1842 else
1843 pi->uvd_dpm.soft_max_clk =
1844 dep_table->entries[dep_table->count - 1].vclk;
1845
1846 /* get min/max sclk soft value
1847 * notify SMU to execute */
1848 ret = cz_send_msg_to_smc_with_parameter(adev,
1849 PPSMC_MSG_SetUvdSoftMin,
1850 cz_get_uvd_level(adev,
1851 pi->uvd_dpm.soft_min_clk,
1852 PPSMC_MSG_SetUvdSoftMin));
1853 if (ret)
1854 return ret;
1855
1856 ret = cz_send_msg_to_smc_with_parameter(adev,
1857 PPSMC_MSG_SetUvdSoftMax,
1858 cz_get_uvd_level(adev,
1859 pi->uvd_dpm.soft_max_clk,
1860 PPSMC_MSG_SetUvdSoftMax));
1861 if (ret)
1862 return ret;
1863
1864 DRM_DEBUG("DPM uvd unforce state min=%d, max=%d.\n",
1865 pi->uvd_dpm.soft_min_clk,
1866 pi->uvd_dpm.soft_max_clk);
1867
1868 return 0;
1869}
1870
1871static int cz_dpm_vce_force_highest(struct amdgpu_device *adev)
1872{
1873 struct cz_power_info *pi = cz_get_pi(adev);
1874 int ret = 0;
1875
1876 if (pi->vce_dpm.soft_min_clk != pi->vce_dpm.soft_max_clk) {
1877 pi->vce_dpm.soft_min_clk =
1878 pi->vce_dpm.soft_max_clk;
1879 ret = cz_send_msg_to_smc_with_parameter(adev,
1880 PPSMC_MSG_SetEclkSoftMin,
1881 cz_get_eclk_level(adev,
1882 pi->vce_dpm.soft_min_clk,
1883 PPSMC_MSG_SetEclkSoftMin));
1884 if (ret)
1885 return ret;
1886 }
1887
1888 return ret;
1889}
1890
1891static int cz_dpm_vce_force_lowest(struct amdgpu_device *adev)
1892{
1893 struct cz_power_info *pi = cz_get_pi(adev);
1894 int ret = 0;
1895
1896 if (pi->vce_dpm.soft_max_clk != pi->vce_dpm.soft_min_clk) {
1897 pi->vce_dpm.soft_max_clk = pi->vce_dpm.soft_min_clk;
1898 ret = cz_send_msg_to_smc_with_parameter(adev,
1899 PPSMC_MSG_SetEclkSoftMax,
1900 cz_get_uvd_level(adev,
1901 pi->vce_dpm.soft_max_clk,
1902 PPSMC_MSG_SetEclkSoftMax));
1903 if (ret)
1904 return ret;
1905 }
1906
1907 return ret;
1908}
1909
1910static uint32_t cz_dpm_get_max_vce_level(struct amdgpu_device *adev)
1911{
1912 struct cz_power_info *pi = cz_get_pi(adev);
1913
1914 if (!pi->max_vce_level) {
1915 cz_send_msg_to_smc(adev, PPSMC_MSG_GetMaxEclkLevel);
1916 pi->max_vce_level = cz_get_argument(adev) + 1;
1917 }
1918
1919 if (pi->max_vce_level > CZ_MAX_HARDWARE_POWERLEVELS) {
1920 DRM_ERROR("Invalid max vce level!\n");
1921 return -EINVAL;
1922 }
1923
1924 return pi->max_vce_level;
1925}
1926
1927static int cz_dpm_unforce_vce_dpm_levels(struct amdgpu_device *adev)
1928{
1929 struct cz_power_info *pi = cz_get_pi(adev);
1930 struct amdgpu_vce_clock_voltage_dependency_table *dep_table =
1931 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
1932 uint32_t level = 0;
1933 int ret = 0;
1934
1935 pi->vce_dpm.soft_min_clk = dep_table->entries[0].ecclk;
1936 level = cz_dpm_get_max_vce_level(adev) - 1;
1937 if (level < dep_table->count)
1938 pi->vce_dpm.soft_max_clk = dep_table->entries[level].ecclk;
1939 else
1940 pi->vce_dpm.soft_max_clk =
1941 dep_table->entries[dep_table->count - 1].ecclk;
1942
1943 /* get min/max sclk soft value
1944 * notify SMU to execute */
1945 ret = cz_send_msg_to_smc_with_parameter(adev,
1946 PPSMC_MSG_SetEclkSoftMin,
1947 cz_get_eclk_level(adev,
1948 pi->vce_dpm.soft_min_clk,
1949 PPSMC_MSG_SetEclkSoftMin));
1950 if (ret)
1951 return ret;
1952
1953 ret = cz_send_msg_to_smc_with_parameter(adev,
1954 PPSMC_MSG_SetEclkSoftMax,
1955 cz_get_eclk_level(adev,
1956 pi->vce_dpm.soft_max_clk,
1957 PPSMC_MSG_SetEclkSoftMax));
1958 if (ret)
1959 return ret;
1960
1961 DRM_DEBUG("DPM vce unforce state min=%d, max=%d.\n",
1962 pi->vce_dpm.soft_min_clk,
1963 pi->vce_dpm.soft_max_clk);
1964
1965 return 0;
1966}
1967
1968static int cz_dpm_force_dpm_level(struct amdgpu_device *adev,
1969 enum amdgpu_dpm_forced_level level)
1970{
1971 int ret = 0;
1972
1973 switch (level) {
1974 case AMDGPU_DPM_FORCED_LEVEL_HIGH:
1975 /* sclk */
1976 ret = cz_dpm_unforce_dpm_levels(adev);
1977 if (ret)
1978 return ret;
1979 ret = cz_dpm_force_highest(adev);
1980 if (ret)
1981 return ret;
1982
1983 /* uvd */
1984 ret = cz_dpm_unforce_uvd_dpm_levels(adev);
1985 if (ret)
1986 return ret;
1987 ret = cz_dpm_uvd_force_highest(adev);
1988 if (ret)
1989 return ret;
1990
1991 /* vce */
1992 ret = cz_dpm_unforce_vce_dpm_levels(adev);
1993 if (ret)
1994 return ret;
1995 ret = cz_dpm_vce_force_highest(adev);
1996 if (ret)
1997 return ret;
1998 break;
1999 case AMDGPU_DPM_FORCED_LEVEL_LOW:
2000 /* sclk */
2001 ret = cz_dpm_unforce_dpm_levels(adev);
2002 if (ret)
2003 return ret;
2004 ret = cz_dpm_force_lowest(adev);
2005 if (ret)
2006 return ret;
2007
2008 /* uvd */
2009 ret = cz_dpm_unforce_uvd_dpm_levels(adev);
2010 if (ret)
2011 return ret;
2012 ret = cz_dpm_uvd_force_lowest(adev);
2013 if (ret)
2014 return ret;
2015
2016 /* vce */
2017 ret = cz_dpm_unforce_vce_dpm_levels(adev);
2018 if (ret)
2019 return ret;
2020 ret = cz_dpm_vce_force_lowest(adev);
2021 if (ret)
2022 return ret;
2023 break;
2024 case AMDGPU_DPM_FORCED_LEVEL_AUTO:
2025 /* sclk */
2026 ret = cz_dpm_unforce_dpm_levels(adev);
2027 if (ret)
2028 return ret;
2029
2030 /* uvd */
2031 ret = cz_dpm_unforce_uvd_dpm_levels(adev);
2032 if (ret)
2033 return ret;
2034
2035 /* vce */
2036 ret = cz_dpm_unforce_vce_dpm_levels(adev);
2037 if (ret)
2038 return ret;
2039 break;
2040 default:
2041 break;
2042 }
2043
2044 adev->pm.dpm.forced_level = level;
2045
2046 return ret;
2047}
2048
2049/* fix me, display configuration change lists here
2050 * mostly dal related*/
2051static void cz_dpm_display_configuration_changed(struct amdgpu_device *adev)
2052{
2053}
2054
2055static uint32_t cz_dpm_get_sclk(struct amdgpu_device *adev, bool low)
2056{
2057 struct cz_power_info *pi = cz_get_pi(adev);
2058 struct cz_ps *requested_state = cz_get_ps(&pi->requested_rps);
2059
2060 if (low)
2061 return requested_state->levels[0].sclk;
2062 else
2063 return requested_state->levels[requested_state->num_levels - 1].sclk;
2064
2065}
2066
2067static uint32_t cz_dpm_get_mclk(struct amdgpu_device *adev, bool low)
2068{
2069 struct cz_power_info *pi = cz_get_pi(adev);
2070
2071 return pi->sys_info.bootup_uma_clk;
2072}
2073
2074static int cz_enable_uvd_dpm(struct amdgpu_device *adev, bool enable)
2075{
2076 struct cz_power_info *pi = cz_get_pi(adev);
2077 int ret = 0;
2078
2079 if (enable && pi->caps_uvd_dpm ) {
2080 pi->dpm_flags |= DPMFlags_UVD_Enabled;
2081 DRM_DEBUG("UVD DPM Enabled.\n");
2082
2083 ret = cz_send_msg_to_smc_with_parameter(adev,
2084 PPSMC_MSG_EnableAllSmuFeatures, UVD_DPM_MASK);
2085 } else {
2086 pi->dpm_flags &= ~DPMFlags_UVD_Enabled;
2087 DRM_DEBUG("UVD DPM Stopped\n");
2088
2089 ret = cz_send_msg_to_smc_with_parameter(adev,
2090 PPSMC_MSG_DisableAllSmuFeatures, UVD_DPM_MASK);
2091 }
2092
2093 return ret;
2094}
2095
2096static int cz_update_uvd_dpm(struct amdgpu_device *adev, bool gate)
2097{
2098 return cz_enable_uvd_dpm(adev, !gate);
2099}
2100
2101
2102static void cz_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate)
2103{
2104 struct cz_power_info *pi = cz_get_pi(adev);
2105 int ret;
2106
2107 if (pi->uvd_power_gated == gate)
2108 return;
2109
2110 pi->uvd_power_gated = gate;
2111
2112 if (gate) {
2113 if (pi->caps_uvd_pg) {
2114 ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
2115 AMD_CG_STATE_GATE);
2116 if (ret) {
2117 DRM_ERROR("UVD DPM Power Gating failed to set clockgating state\n");
2118 return;
2119 }
2120
2121 /* shutdown the UVD block */
2122 ret = amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
2123 AMD_PG_STATE_GATE);
2124
2125 if (ret) {
2126 DRM_ERROR("UVD DPM Power Gating failed to set powergating state\n");
2127 return;
2128 }
2129 }
2130 cz_update_uvd_dpm(adev, gate);
2131 if (pi->caps_uvd_pg) {
2132 /* power off the UVD block */
2133 ret = cz_send_msg_to_smc(adev, PPSMC_MSG_UVDPowerOFF);
2134 if (ret) {
2135 DRM_ERROR("UVD DPM Power Gating failed to send SMU PowerOFF message\n");
2136 return;
2137 }
2138 }
2139 } else {
2140 if (pi->caps_uvd_pg) {
2141 /* power on the UVD block */
2142 if (pi->uvd_dynamic_pg)
2143 ret = cz_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_UVDPowerON, 1);
2144 else
2145 ret = cz_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_UVDPowerON, 0);
2146
2147 if (ret) {
2148 DRM_ERROR("UVD DPM Power Gating Failed to send SMU PowerON message\n");
2149 return;
2150 }
2151
2152 /* re-init the UVD block */
2153 ret = amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
2154 AMD_PG_STATE_UNGATE);
2155
2156 if (ret) {
2157 DRM_ERROR("UVD DPM Power Gating Failed to set powergating state\n");
2158 return;
2159 }
2160
2161 ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
2162 AMD_CG_STATE_UNGATE);
2163 if (ret) {
2164 DRM_ERROR("UVD DPM Power Gating Failed to set clockgating state\n");
2165 return;
2166 }
2167 }
2168 cz_update_uvd_dpm(adev, gate);
2169 }
2170}
2171
2172static int cz_enable_vce_dpm(struct amdgpu_device *adev, bool enable)
2173{
2174 struct cz_power_info *pi = cz_get_pi(adev);
2175 int ret = 0;
2176
2177 if (enable && pi->caps_vce_dpm) {
2178 pi->dpm_flags |= DPMFlags_VCE_Enabled;
2179 DRM_DEBUG("VCE DPM Enabled.\n");
2180
2181 ret = cz_send_msg_to_smc_with_parameter(adev,
2182 PPSMC_MSG_EnableAllSmuFeatures, VCE_DPM_MASK);
2183
2184 } else {
2185 pi->dpm_flags &= ~DPMFlags_VCE_Enabled;
2186 DRM_DEBUG("VCE DPM Stopped\n");
2187
2188 ret = cz_send_msg_to_smc_with_parameter(adev,
2189 PPSMC_MSG_DisableAllSmuFeatures, VCE_DPM_MASK);
2190 }
2191
2192 return ret;
2193}
2194
2195static int cz_update_vce_dpm(struct amdgpu_device *adev)
2196{
2197 struct cz_power_info *pi = cz_get_pi(adev);
2198 struct amdgpu_vce_clock_voltage_dependency_table *table =
2199 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
2200
2201 /* Stable Pstate is enabled and we need to set the VCE DPM to highest level */
2202 if (pi->caps_stable_power_state) {
2203 pi->vce_dpm.hard_min_clk = table->entries[table->count-1].ecclk;
2204 } else { /* non-stable p-state cases. without vce.Arbiter.EcclkHardMin */
2205 /* leave it as set by user */
2206 /*pi->vce_dpm.hard_min_clk = table->entries[0].ecclk;*/
2207 }
2208
2209 cz_send_msg_to_smc_with_parameter(adev,
2210 PPSMC_MSG_SetEclkHardMin,
2211 cz_get_eclk_level(adev,
2212 pi->vce_dpm.hard_min_clk,
2213 PPSMC_MSG_SetEclkHardMin));
2214 return 0;
2215}
2216
2217static void cz_dpm_powergate_vce(struct amdgpu_device *adev, bool gate)
2218{
2219 struct cz_power_info *pi = cz_get_pi(adev);
2220
2221 if (pi->caps_vce_pg) {
2222 if (pi->vce_power_gated != gate) {
2223 if (gate) {
2224 /* disable clockgating so we can properly shut down the block */
2225 amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
2226 AMD_CG_STATE_UNGATE);
2227 /* shutdown the VCE block */
2228 amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
2229 AMD_PG_STATE_GATE);
2230
2231 cz_enable_vce_dpm(adev, false);
2232 cz_send_msg_to_smc(adev, PPSMC_MSG_VCEPowerOFF);
2233 pi->vce_power_gated = true;
2234 } else {
2235 cz_send_msg_to_smc(adev, PPSMC_MSG_VCEPowerON);
2236 pi->vce_power_gated = false;
2237
2238 /* re-init the VCE block */
2239 amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
2240 AMD_PG_STATE_UNGATE);
2241 /* enable clockgating. hw will dynamically gate/ungate clocks on the fly */
2242 amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
2243 AMD_CG_STATE_GATE);
2244
2245 cz_update_vce_dpm(adev);
2246 cz_enable_vce_dpm(adev, true);
2247 }
2248 } else {
2249 if (! pi->vce_power_gated) {
2250 cz_update_vce_dpm(adev);
2251 }
2252 }
2253 } else { /*pi->caps_vce_pg*/
2254 pi->vce_power_gated = gate;
2255 cz_update_vce_dpm(adev);
2256 cz_enable_vce_dpm(adev, !gate);
2257 }
2258}
2259
2260static int cz_check_state_equal(struct amdgpu_device *adev,
2261 struct amdgpu_ps *cps,
2262 struct amdgpu_ps *rps,
2263 bool *equal)
2264{
2265 if (equal == NULL)
2266 return -EINVAL;
2267
2268 *equal = false;
2269 return 0;
2270}
2271
2272const struct amd_ip_funcs cz_dpm_ip_funcs = {
2273 .name = "cz_dpm",
2274 .early_init = cz_dpm_early_init,
2275 .late_init = cz_dpm_late_init,
2276 .sw_init = cz_dpm_sw_init,
2277 .sw_fini = cz_dpm_sw_fini,
2278 .hw_init = cz_dpm_hw_init,
2279 .hw_fini = cz_dpm_hw_fini,
2280 .suspend = cz_dpm_suspend,
2281 .resume = cz_dpm_resume,
2282 .is_idle = NULL,
2283 .wait_for_idle = NULL,
2284 .soft_reset = NULL,
2285 .set_clockgating_state = cz_dpm_set_clockgating_state,
2286 .set_powergating_state = cz_dpm_set_powergating_state,
2287};
2288
2289static const struct amdgpu_dpm_funcs cz_dpm_funcs = {
2290 .get_temperature = cz_dpm_get_temperature,
2291 .pre_set_power_state = cz_dpm_pre_set_power_state,
2292 .set_power_state = cz_dpm_set_power_state,
2293 .post_set_power_state = cz_dpm_post_set_power_state,
2294 .display_configuration_changed = cz_dpm_display_configuration_changed,
2295 .get_sclk = cz_dpm_get_sclk,
2296 .get_mclk = cz_dpm_get_mclk,
2297 .print_power_state = cz_dpm_print_power_state,
2298 .debugfs_print_current_performance_level =
2299 cz_dpm_debugfs_print_current_performance_level,
2300 .force_performance_level = cz_dpm_force_dpm_level,
2301 .vblank_too_short = NULL,
2302 .powergate_uvd = cz_dpm_powergate_uvd,
2303 .powergate_vce = cz_dpm_powergate_vce,
2304 .check_state_equal = cz_check_state_equal,
2305};
2306
2307static void cz_dpm_set_funcs(struct amdgpu_device *adev)
2308{
2309 if (NULL == adev->pm.funcs)
2310 adev->pm.funcs = &cz_dpm_funcs;
2311}
2312
2313const struct amdgpu_ip_block_version cz_dpm_ip_block =
2314{
2315 .type = AMD_IP_BLOCK_TYPE_SMC,
2316 .major = 8,
2317 .minor = 0,
2318 .rev = 0,
2319 .funcs = &cz_dpm_ip_funcs,
2320};
diff --git a/drivers/gpu/drm/amd/amdgpu/cz_dpm.h b/drivers/gpu/drm/amd/amdgpu/cz_dpm.h
deleted file mode 100644
index 5df8c1faab51..000000000000
--- a/drivers/gpu/drm/amd/amdgpu/cz_dpm.h
+++ /dev/null
@@ -1,239 +0,0 @@
1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#ifndef __CZ_DPM_H__
25#define __CZ_DPM_H__
26
27#include "smu8_fusion.h"
28
29#define CZ_AT_DFLT 30
30#define CZ_NUM_NBPSTATES 4
31#define CZ_NUM_NBPMEMORY_CLOCK 2
32#define CZ_MAX_HARDWARE_POWERLEVELS 8
33#define CZ_MAX_DISPLAY_CLOCK_LEVEL 8
34#define CZ_MAX_DISPLAYPHY_IDS 10
35
36#define PPCZ_VOTINGRIGHTSCLIENTS_DFLT0 0x3FFFC102
37
38#define SMC_RAM_END 0x40000
39
40#define DPMFlags_SCLK_Enabled 0x00000001
41#define DPMFlags_UVD_Enabled 0x00000002
42#define DPMFlags_VCE_Enabled 0x00000004
43#define DPMFlags_ACP_Enabled 0x00000008
44#define DPMFlags_ForceHighestValid 0x40000000
45#define DPMFlags_Debug 0x80000000
46
47/* Do not change the following, it is also defined in SMU8.h */
48#define SMU_EnabledFeatureScoreboard_AcpDpmOn 0x00000001
49#define SMU_EnabledFeatureScoreboard_SclkDpmOn 0x00200000
50#define SMU_EnabledFeatureScoreboard_UvdDpmOn 0x00800000
51#define SMU_EnabledFeatureScoreboard_VceDpmOn 0x01000000
52
53/* temporary solution to SetMinDeepSleepSclk
54 * should indicate by display adaptor
55 * 10k Hz unit*/
56#define CZ_MIN_DEEP_SLEEP_SCLK 800
57
58enum cz_pt_config_reg_type {
59 CZ_CONFIGREG_MMR = 0,
60 CZ_CONFIGREG_SMC_IND,
61 CZ_CONFIGREG_DIDT_IND,
62 CZ_CONFIGREG_CACHE,
63 CZ_CONFIGREG_MAX
64};
65
66struct cz_pt_config_reg {
67 uint32_t offset;
68 uint32_t mask;
69 uint32_t shift;
70 uint32_t value;
71 enum cz_pt_config_reg_type type;
72};
73
74struct cz_dpm_entry {
75 uint32_t soft_min_clk;
76 uint32_t hard_min_clk;
77 uint32_t soft_max_clk;
78 uint32_t hard_max_clk;
79};
80
81struct cz_pl {
82 uint32_t sclk;
83 uint8_t vddc_index;
84 uint8_t ds_divider_index;
85 uint8_t ss_divider_index;
86 uint8_t allow_gnb_slow;
87 uint8_t force_nbp_state;
88 uint8_t display_wm;
89 uint8_t vce_wm;
90};
91
92struct cz_ps {
93 struct cz_pl levels[CZ_MAX_HARDWARE_POWERLEVELS];
94 uint32_t num_levels;
95 bool need_dfs_bypass;
96 uint8_t dpm0_pg_nb_ps_lo;
97 uint8_t dpm0_pg_nb_ps_hi;
98 uint8_t dpmx_nb_ps_lo;
99 uint8_t dpmx_nb_ps_hi;
100 bool force_high;
101};
102
103struct cz_displayphy_entry {
104 uint8_t phy_present;
105 uint8_t active_lane_mapping;
106 uint8_t display_conf_type;
107 uint8_t num_active_lanes;
108};
109
110struct cz_displayphy_info {
111 bool phy_access_initialized;
112 struct cz_displayphy_entry entries[CZ_MAX_DISPLAYPHY_IDS];
113};
114
115struct cz_sys_info {
116 uint32_t bootup_uma_clk;
117 uint32_t bootup_sclk;
118 uint32_t dentist_vco_freq;
119 uint32_t nb_dpm_enable;
120 uint32_t nbp_memory_clock[CZ_NUM_NBPMEMORY_CLOCK];
121 uint32_t nbp_n_clock[CZ_NUM_NBPSTATES];
122 uint8_t nbp_voltage_index[CZ_NUM_NBPSTATES];
123 uint32_t display_clock[CZ_MAX_DISPLAY_CLOCK_LEVEL];
124 uint16_t bootup_nb_voltage_index;
125 uint8_t htc_tmp_lmt;
126 uint8_t htc_hyst_lmt;
127 uint32_t uma_channel_number;
128};
129
130struct cz_power_info {
131 uint32_t active_target[CZ_MAX_HARDWARE_POWERLEVELS];
132 struct cz_sys_info sys_info;
133 struct cz_pl boot_pl;
134 bool disable_nb_ps3_in_battery;
135 bool battery_state;
136 uint32_t lowest_valid;
137 uint32_t highest_valid;
138 uint16_t high_voltage_threshold;
139 /* smc offsets */
140 uint32_t sram_end;
141 uint32_t dpm_table_start;
142 uint32_t soft_regs_start;
143 /* dpm SMU tables */
144 uint8_t uvd_level_count;
145 uint8_t vce_level_count;
146 uint8_t acp_level_count;
147 uint32_t fps_high_threshold;
148 uint32_t fps_low_threshold;
149 /* dpm table */
150 uint32_t dpm_flags;
151 struct cz_dpm_entry sclk_dpm;
152 struct cz_dpm_entry uvd_dpm;
153 struct cz_dpm_entry vce_dpm;
154 struct cz_dpm_entry acp_dpm;
155
156 uint8_t uvd_boot_level;
157 uint8_t uvd_interval;
158 uint8_t vce_boot_level;
159 uint8_t vce_interval;
160 uint8_t acp_boot_level;
161 uint8_t acp_interval;
162
163 uint8_t graphics_boot_level;
164 uint8_t graphics_interval;
165 uint8_t graphics_therm_throttle_enable;
166 uint8_t graphics_voltage_change_enable;
167 uint8_t graphics_clk_slow_enable;
168 uint8_t graphics_clk_slow_divider;
169
170 uint32_t low_sclk_interrupt_threshold;
171 bool uvd_power_gated;
172 bool vce_power_gated;
173 bool acp_power_gated;
174
175 uint32_t active_process_mask;
176
177 uint32_t mgcg_cgtt_local0;
178 uint32_t mgcg_cgtt_local1;
179 uint32_t clock_slow_down_step;
180 uint32_t skip_clock_slow_down;
181 bool enable_nb_ps_policy;
182 uint32_t voting_clients;
183 uint32_t voltage_drop_threshold;
184 uint32_t gfx_pg_threshold;
185 uint32_t max_sclk_level;
186 uint32_t max_uvd_level;
187 uint32_t max_vce_level;
188 /* flags */
189 bool didt_enabled;
190 bool video_start;
191 bool cac_enabled;
192 bool bapm_enabled;
193 bool nb_dpm_enabled_by_driver;
194 bool nb_dpm_enabled;
195 bool auto_thermal_throttling_enabled;
196 bool dpm_enabled;
197 bool need_pptable_upload;
198 /* caps */
199 bool caps_cac;
200 bool caps_power_containment;
201 bool caps_sq_ramping;
202 bool caps_db_ramping;
203 bool caps_td_ramping;
204 bool caps_tcp_ramping;
205 bool caps_sclk_throttle_low_notification;
206 bool caps_fps;
207 bool caps_uvd_dpm;
208 bool caps_uvd_pg;
209 bool caps_vce_dpm;
210 bool caps_vce_pg;
211 bool caps_acp_dpm;
212 bool caps_acp_pg;
213 bool caps_stable_power_state;
214 bool caps_enable_dfs_bypass;
215 bool caps_sclk_ds;
216 bool caps_voltage_island;
217 /* power state */
218 struct amdgpu_ps current_rps;
219 struct cz_ps current_ps;
220 struct amdgpu_ps requested_rps;
221 struct cz_ps requested_ps;
222
223 bool uvd_power_down;
224 bool vce_power_down;
225 bool acp_power_down;
226
227 bool uvd_dynamic_pg;
228};
229
230/* cz_smc.c */
231uint32_t cz_get_argument(struct amdgpu_device *adev);
232int cz_send_msg_to_smc(struct amdgpu_device *adev, uint16_t msg);
233int cz_send_msg_to_smc_with_parameter(struct amdgpu_device *adev,
234 uint16_t msg, uint32_t parameter);
235int cz_read_smc_sram_dword(struct amdgpu_device *adev,
236 uint32_t smc_address, uint32_t *value, uint32_t limit);
237int cz_smu_upload_pptable(struct amdgpu_device *adev);
238int cz_smu_download_pptable(struct amdgpu_device *adev, void **table);
239#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/cz_smc.c b/drivers/gpu/drm/amd/amdgpu/cz_smc.c
deleted file mode 100644
index aed7033c0973..000000000000
--- a/drivers/gpu/drm/amd/amdgpu/cz_smc.c
+++ /dev/null
@@ -1,995 +0,0 @@
1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24#include "drmP.h"
25#include "amdgpu.h"
26#include "smu8.h"
27#include "smu8_fusion.h"
28#include "cz_ppsmc.h"
29#include "cz_smumgr.h"
30#include "smu_ucode_xfer_cz.h"
31#include "amdgpu_ucode.h"
32#include "cz_dpm.h"
33#include "vi_dpm.h"
34
35#include "smu/smu_8_0_d.h"
36#include "smu/smu_8_0_sh_mask.h"
37#include "gca/gfx_8_0_d.h"
38#include "gca/gfx_8_0_sh_mask.h"
39
40uint32_t cz_get_argument(struct amdgpu_device *adev)
41{
42 return RREG32(mmSMU_MP1_SRBM2P_ARG_0);
43}
44
45static struct cz_smu_private_data *cz_smu_get_priv(struct amdgpu_device *adev)
46{
47 struct cz_smu_private_data *priv =
48 (struct cz_smu_private_data *)(adev->smu.priv);
49
50 return priv;
51}
52
53static int cz_send_msg_to_smc_async(struct amdgpu_device *adev, u16 msg)
54{
55 int i;
56 u32 content = 0, tmp;
57
58 for (i = 0; i < adev->usec_timeout; i++) {
59 tmp = REG_GET_FIELD(RREG32(mmSMU_MP1_SRBM2P_RESP_0),
60 SMU_MP1_SRBM2P_RESP_0, CONTENT);
61 if (content != tmp)
62 break;
63 udelay(1);
64 }
65
66 /* timeout means wrong logic*/
67 if (i == adev->usec_timeout)
68 return -EINVAL;
69
70 WREG32(mmSMU_MP1_SRBM2P_RESP_0, 0);
71 WREG32(mmSMU_MP1_SRBM2P_MSG_0, msg);
72
73 return 0;
74}
75
76int cz_send_msg_to_smc(struct amdgpu_device *adev, u16 msg)
77{
78 int i;
79 u32 content = 0, tmp = 0;
80
81 if (cz_send_msg_to_smc_async(adev, msg))
82 return -EINVAL;
83
84 for (i = 0; i < adev->usec_timeout; i++) {
85 tmp = REG_GET_FIELD(RREG32(mmSMU_MP1_SRBM2P_RESP_0),
86 SMU_MP1_SRBM2P_RESP_0, CONTENT);
87 if (content != tmp)
88 break;
89 udelay(1);
90 }
91
92 /* timeout means wrong logic*/
93 if (i == adev->usec_timeout)
94 return -EINVAL;
95
96 if (PPSMC_Result_OK != tmp) {
97 dev_err(adev->dev, "SMC Failed to send Message.\n");
98 return -EINVAL;
99 }
100
101 return 0;
102}
103
104int cz_send_msg_to_smc_with_parameter(struct amdgpu_device *adev,
105 u16 msg, u32 parameter)
106{
107 WREG32(mmSMU_MP1_SRBM2P_ARG_0, parameter);
108 return cz_send_msg_to_smc(adev, msg);
109}
110
111static int cz_set_smc_sram_address(struct amdgpu_device *adev,
112 u32 smc_address, u32 limit)
113{
114 if (smc_address & 3)
115 return -EINVAL;
116 if ((smc_address + 3) > limit)
117 return -EINVAL;
118
119 WREG32(mmMP0PUB_IND_INDEX_0, SMN_MP1_SRAM_START_ADDR + smc_address);
120
121 return 0;
122}
123
124int cz_read_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address,
125 u32 *value, u32 limit)
126{
127 int ret;
128
129 ret = cz_set_smc_sram_address(adev, smc_address, limit);
130 if (ret)
131 return ret;
132
133 *value = RREG32(mmMP0PUB_IND_DATA_0);
134
135 return 0;
136}
137
138static int cz_write_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address,
139 u32 value, u32 limit)
140{
141 int ret;
142
143 ret = cz_set_smc_sram_address(adev, smc_address, limit);
144 if (ret)
145 return ret;
146
147 WREG32(mmMP0PUB_IND_DATA_0, value);
148
149 return 0;
150}
151
152static int cz_smu_request_load_fw(struct amdgpu_device *adev)
153{
154 struct cz_smu_private_data *priv = cz_smu_get_priv(adev);
155
156 uint32_t smc_addr = SMU8_FIRMWARE_HEADER_LOCATION +
157 offsetof(struct SMU8_Firmware_Header, UcodeLoadStatus);
158
159 cz_write_smc_sram_dword(adev, smc_addr, 0, smc_addr + 4);
160
161 /*prepare toc buffers*/
162 cz_send_msg_to_smc_with_parameter(adev,
163 PPSMC_MSG_DriverDramAddrHi,
164 priv->toc_buffer.mc_addr_high);
165 cz_send_msg_to_smc_with_parameter(adev,
166 PPSMC_MSG_DriverDramAddrLo,
167 priv->toc_buffer.mc_addr_low);
168 cz_send_msg_to_smc(adev, PPSMC_MSG_InitJobs);
169
170 /*execute jobs*/
171 cz_send_msg_to_smc_with_parameter(adev,
172 PPSMC_MSG_ExecuteJob,
173 priv->toc_entry_aram);
174
175 cz_send_msg_to_smc_with_parameter(adev,
176 PPSMC_MSG_ExecuteJob,
177 priv->toc_entry_power_profiling_index);
178
179 cz_send_msg_to_smc_with_parameter(adev,
180 PPSMC_MSG_ExecuteJob,
181 priv->toc_entry_initialize_index);
182
183 return 0;
184}
185
186/*
187 *Check if the FW has been loaded, SMU will not return if loading
188 *has not finished.
189 */
190static int cz_smu_check_fw_load_finish(struct amdgpu_device *adev,
191 uint32_t fw_mask)
192{
193 int i;
194 uint32_t index = SMN_MP1_SRAM_START_ADDR +
195 SMU8_FIRMWARE_HEADER_LOCATION +
196 offsetof(struct SMU8_Firmware_Header, UcodeLoadStatus);
197
198 WREG32(mmMP0PUB_IND_INDEX, index);
199
200 for (i = 0; i < adev->usec_timeout; i++) {
201 if (fw_mask == (RREG32(mmMP0PUB_IND_DATA) & fw_mask))
202 break;
203 udelay(1);
204 }
205
206 if (i >= adev->usec_timeout) {
207 dev_err(adev->dev,
208 "SMU check loaded firmware failed, expecting 0x%x, getting 0x%x",
209 fw_mask, RREG32(mmMP0PUB_IND_DATA));
210 return -EINVAL;
211 }
212
213 return 0;
214}
215
216/*
217 * interfaces for different ip blocks to check firmware loading status
218 * 0 for success otherwise failed
219 */
220static int cz_smu_check_finished(struct amdgpu_device *adev,
221 enum AMDGPU_UCODE_ID id)
222{
223 switch (id) {
224 case AMDGPU_UCODE_ID_SDMA0:
225 if (adev->smu.fw_flags & AMDGPU_SDMA0_UCODE_LOADED)
226 return 0;
227 break;
228 case AMDGPU_UCODE_ID_SDMA1:
229 if (adev->smu.fw_flags & AMDGPU_SDMA1_UCODE_LOADED)
230 return 0;
231 break;
232 case AMDGPU_UCODE_ID_CP_CE:
233 if (adev->smu.fw_flags & AMDGPU_CPCE_UCODE_LOADED)
234 return 0;
235 break;
236 case AMDGPU_UCODE_ID_CP_PFP:
237 if (adev->smu.fw_flags & AMDGPU_CPPFP_UCODE_LOADED)
238 return 0;
239 case AMDGPU_UCODE_ID_CP_ME:
240 if (adev->smu.fw_flags & AMDGPU_CPME_UCODE_LOADED)
241 return 0;
242 break;
243 case AMDGPU_UCODE_ID_CP_MEC1:
244 if (adev->smu.fw_flags & AMDGPU_CPMEC1_UCODE_LOADED)
245 return 0;
246 break;
247 case AMDGPU_UCODE_ID_CP_MEC2:
248 if (adev->smu.fw_flags & AMDGPU_CPMEC2_UCODE_LOADED)
249 return 0;
250 break;
251 case AMDGPU_UCODE_ID_RLC_G:
252 if (adev->smu.fw_flags & AMDGPU_CPRLC_UCODE_LOADED)
253 return 0;
254 break;
255 case AMDGPU_UCODE_ID_MAXIMUM:
256 default:
257 break;
258 }
259
260 return 1;
261}
262
263static int cz_load_mec_firmware(struct amdgpu_device *adev)
264{
265 struct amdgpu_firmware_info *ucode =
266 &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
267 uint32_t reg_data;
268 uint32_t tmp;
269
270 if (ucode->fw == NULL)
271 return -EINVAL;
272
273 /* Disable MEC parsing/prefetching */
274 tmp = RREG32(mmCP_MEC_CNTL);
275 tmp = REG_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME1_HALT, 1);
276 tmp = REG_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME2_HALT, 1);
277 WREG32(mmCP_MEC_CNTL, tmp);
278
279 tmp = RREG32(mmCP_CPC_IC_BASE_CNTL);
280 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
281 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ATC, 0);
282 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
283 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, MTYPE, 1);
284 WREG32(mmCP_CPC_IC_BASE_CNTL, tmp);
285
286 reg_data = lower_32_bits(ucode->mc_addr) &
287 REG_FIELD_MASK(CP_CPC_IC_BASE_LO, IC_BASE_LO);
288 WREG32(mmCP_CPC_IC_BASE_LO, reg_data);
289
290 reg_data = upper_32_bits(ucode->mc_addr) &
291 REG_FIELD_MASK(CP_CPC_IC_BASE_HI, IC_BASE_HI);
292 WREG32(mmCP_CPC_IC_BASE_HI, reg_data);
293
294 return 0;
295}
296
297int cz_smu_start(struct amdgpu_device *adev)
298{
299 int ret = 0;
300
301 uint32_t fw_to_check = UCODE_ID_RLC_G_MASK |
302 UCODE_ID_SDMA0_MASK |
303 UCODE_ID_SDMA1_MASK |
304 UCODE_ID_CP_CE_MASK |
305 UCODE_ID_CP_ME_MASK |
306 UCODE_ID_CP_PFP_MASK |
307 UCODE_ID_CP_MEC_JT1_MASK |
308 UCODE_ID_CP_MEC_JT2_MASK;
309
310 if (adev->asic_type == CHIP_STONEY)
311 fw_to_check &= ~(UCODE_ID_SDMA1_MASK | UCODE_ID_CP_MEC_JT2_MASK);
312
313 cz_smu_request_load_fw(adev);
314 ret = cz_smu_check_fw_load_finish(adev, fw_to_check);
315 if (ret)
316 return ret;
317
318 /* manually load MEC firmware for CZ */
319 if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY) {
320 ret = cz_load_mec_firmware(adev);
321 if (ret) {
322 dev_err(adev->dev, "(%d) Mec Firmware load failed\n", ret);
323 return ret;
324 }
325 }
326
327 /* setup fw load flag */
328 adev->smu.fw_flags = AMDGPU_SDMA0_UCODE_LOADED |
329 AMDGPU_SDMA1_UCODE_LOADED |
330 AMDGPU_CPCE_UCODE_LOADED |
331 AMDGPU_CPPFP_UCODE_LOADED |
332 AMDGPU_CPME_UCODE_LOADED |
333 AMDGPU_CPMEC1_UCODE_LOADED |
334 AMDGPU_CPMEC2_UCODE_LOADED |
335 AMDGPU_CPRLC_UCODE_LOADED;
336
337 if (adev->asic_type == CHIP_STONEY)
338 adev->smu.fw_flags &= ~(AMDGPU_SDMA1_UCODE_LOADED | AMDGPU_CPMEC2_UCODE_LOADED);
339
340 return ret;
341}
342
343static uint32_t cz_convert_fw_type(uint32_t fw_type)
344{
345 enum AMDGPU_UCODE_ID result = AMDGPU_UCODE_ID_MAXIMUM;
346
347 switch (fw_type) {
348 case UCODE_ID_SDMA0:
349 result = AMDGPU_UCODE_ID_SDMA0;
350 break;
351 case UCODE_ID_SDMA1:
352 result = AMDGPU_UCODE_ID_SDMA1;
353 break;
354 case UCODE_ID_CP_CE:
355 result = AMDGPU_UCODE_ID_CP_CE;
356 break;
357 case UCODE_ID_CP_PFP:
358 result = AMDGPU_UCODE_ID_CP_PFP;
359 break;
360 case UCODE_ID_CP_ME:
361 result = AMDGPU_UCODE_ID_CP_ME;
362 break;
363 case UCODE_ID_CP_MEC_JT1:
364 case UCODE_ID_CP_MEC_JT2:
365 result = AMDGPU_UCODE_ID_CP_MEC1;
366 break;
367 case UCODE_ID_RLC_G:
368 result = AMDGPU_UCODE_ID_RLC_G;
369 break;
370 default:
371 DRM_ERROR("UCode type is out of range!");
372 }
373
374 return result;
375}
376
377static uint8_t cz_smu_translate_firmware_enum_to_arg(
378 enum cz_scratch_entry firmware_enum)
379{
380 uint8_t ret = 0;
381
382 switch (firmware_enum) {
383 case CZ_SCRATCH_ENTRY_UCODE_ID_SDMA0:
384 ret = UCODE_ID_SDMA0;
385 break;
386 case CZ_SCRATCH_ENTRY_UCODE_ID_SDMA1:
387 ret = UCODE_ID_SDMA1;
388 break;
389 case CZ_SCRATCH_ENTRY_UCODE_ID_CP_CE:
390 ret = UCODE_ID_CP_CE;
391 break;
392 case CZ_SCRATCH_ENTRY_UCODE_ID_CP_PFP:
393 ret = UCODE_ID_CP_PFP;
394 break;
395 case CZ_SCRATCH_ENTRY_UCODE_ID_CP_ME:
396 ret = UCODE_ID_CP_ME;
397 break;
398 case CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1:
399 ret = UCODE_ID_CP_MEC_JT1;
400 break;
401 case CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2:
402 ret = UCODE_ID_CP_MEC_JT2;
403 break;
404 case CZ_SCRATCH_ENTRY_UCODE_ID_GMCON_RENG:
405 ret = UCODE_ID_GMCON_RENG;
406 break;
407 case CZ_SCRATCH_ENTRY_UCODE_ID_RLC_G:
408 ret = UCODE_ID_RLC_G;
409 break;
410 case CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SCRATCH:
411 ret = UCODE_ID_RLC_SCRATCH;
412 break;
413 case CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_ARAM:
414 ret = UCODE_ID_RLC_SRM_ARAM;
415 break;
416 case CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_DRAM:
417 ret = UCODE_ID_RLC_SRM_DRAM;
418 break;
419 case CZ_SCRATCH_ENTRY_UCODE_ID_DMCU_ERAM:
420 ret = UCODE_ID_DMCU_ERAM;
421 break;
422 case CZ_SCRATCH_ENTRY_UCODE_ID_DMCU_IRAM:
423 ret = UCODE_ID_DMCU_IRAM;
424 break;
425 case CZ_SCRATCH_ENTRY_UCODE_ID_POWER_PROFILING:
426 ret = TASK_ARG_INIT_MM_PWR_LOG;
427 break;
428 case CZ_SCRATCH_ENTRY_DATA_ID_SDMA_HALT:
429 case CZ_SCRATCH_ENTRY_DATA_ID_SYS_CLOCKGATING:
430 case CZ_SCRATCH_ENTRY_DATA_ID_SDMA_RING_REGS:
431 case CZ_SCRATCH_ENTRY_DATA_ID_NONGFX_REINIT:
432 case CZ_SCRATCH_ENTRY_DATA_ID_SDMA_START:
433 case CZ_SCRATCH_ENTRY_DATA_ID_IH_REGISTERS:
434 ret = TASK_ARG_REG_MMIO;
435 break;
436 case CZ_SCRATCH_ENTRY_SMU8_FUSION_CLKTABLE:
437 ret = TASK_ARG_INIT_CLK_TABLE;
438 break;
439 }
440
441 return ret;
442}
443
444static int cz_smu_populate_single_firmware_entry(struct amdgpu_device *adev,
445 enum cz_scratch_entry firmware_enum,
446 struct cz_buffer_entry *entry)
447{
448 uint64_t gpu_addr;
449 uint32_t data_size;
450 uint8_t ucode_id = cz_smu_translate_firmware_enum_to_arg(firmware_enum);
451 enum AMDGPU_UCODE_ID id = cz_convert_fw_type(ucode_id);
452 struct amdgpu_firmware_info *ucode = &adev->firmware.ucode[id];
453 const struct gfx_firmware_header_v1_0 *header;
454
455 if (ucode->fw == NULL)
456 return -EINVAL;
457
458 gpu_addr = ucode->mc_addr;
459 header = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
460 data_size = le32_to_cpu(header->header.ucode_size_bytes);
461
462 if ((firmware_enum == CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1) ||
463 (firmware_enum == CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2)) {
464 gpu_addr += le32_to_cpu(header->jt_offset) << 2;
465 data_size = le32_to_cpu(header->jt_size) << 2;
466 }
467
468 entry->mc_addr_low = lower_32_bits(gpu_addr);
469 entry->mc_addr_high = upper_32_bits(gpu_addr);
470 entry->data_size = data_size;
471 entry->firmware_ID = firmware_enum;
472
473 return 0;
474}
475
476static int cz_smu_populate_single_scratch_entry(struct amdgpu_device *adev,
477 enum cz_scratch_entry scratch_type,
478 uint32_t size_in_byte,
479 struct cz_buffer_entry *entry)
480{
481 struct cz_smu_private_data *priv = cz_smu_get_priv(adev);
482 uint64_t mc_addr = (((uint64_t) priv->smu_buffer.mc_addr_high) << 32) |
483 priv->smu_buffer.mc_addr_low;
484 mc_addr += size_in_byte;
485
486 priv->smu_buffer_used_bytes += size_in_byte;
487 entry->data_size = size_in_byte;
488 entry->kaddr = priv->smu_buffer.kaddr + priv->smu_buffer_used_bytes;
489 entry->mc_addr_low = lower_32_bits(mc_addr);
490 entry->mc_addr_high = upper_32_bits(mc_addr);
491 entry->firmware_ID = scratch_type;
492
493 return 0;
494}
495
496static int cz_smu_populate_single_ucode_load_task(struct amdgpu_device *adev,
497 enum cz_scratch_entry firmware_enum,
498 bool is_last)
499{
500 uint8_t i;
501 struct cz_smu_private_data *priv = cz_smu_get_priv(adev);
502 struct TOC *toc = (struct TOC *)priv->toc_buffer.kaddr;
503 struct SMU_Task *task = &toc->tasks[priv->toc_entry_used_count++];
504
505 task->type = TASK_TYPE_UCODE_LOAD;
506 task->arg = cz_smu_translate_firmware_enum_to_arg(firmware_enum);
507 task->next = is_last ? END_OF_TASK_LIST : priv->toc_entry_used_count;
508
509 for (i = 0; i < priv->driver_buffer_length; i++)
510 if (priv->driver_buffer[i].firmware_ID == firmware_enum)
511 break;
512
513 if (i >= priv->driver_buffer_length) {
514 dev_err(adev->dev, "Invalid Firmware Type\n");
515 return -EINVAL;
516 }
517
518 task->addr.low = priv->driver_buffer[i].mc_addr_low;
519 task->addr.high = priv->driver_buffer[i].mc_addr_high;
520 task->size_bytes = priv->driver_buffer[i].data_size;
521
522 return 0;
523}
524
525static int cz_smu_populate_single_scratch_task(struct amdgpu_device *adev,
526 enum cz_scratch_entry firmware_enum,
527 uint8_t type, bool is_last)
528{
529 uint8_t i;
530 struct cz_smu_private_data *priv = cz_smu_get_priv(adev);
531 struct TOC *toc = (struct TOC *)priv->toc_buffer.kaddr;
532 struct SMU_Task *task = &toc->tasks[priv->toc_entry_used_count++];
533
534 task->type = type;
535 task->arg = cz_smu_translate_firmware_enum_to_arg(firmware_enum);
536 task->next = is_last ? END_OF_TASK_LIST : priv->toc_entry_used_count;
537
538 for (i = 0; i < priv->scratch_buffer_length; i++)
539 if (priv->scratch_buffer[i].firmware_ID == firmware_enum)
540 break;
541
542 if (i >= priv->scratch_buffer_length) {
543 dev_err(adev->dev, "Invalid Firmware Type\n");
544 return -EINVAL;
545 }
546
547 task->addr.low = priv->scratch_buffer[i].mc_addr_low;
548 task->addr.high = priv->scratch_buffer[i].mc_addr_high;
549 task->size_bytes = priv->scratch_buffer[i].data_size;
550
551 if (CZ_SCRATCH_ENTRY_DATA_ID_IH_REGISTERS == firmware_enum) {
552 struct cz_ih_meta_data *pIHReg_restore =
553 (struct cz_ih_meta_data *)priv->scratch_buffer[i].kaddr;
554 pIHReg_restore->command =
555 METADATA_CMD_MODE0 | METADATA_PERFORM_ON_LOAD;
556 }
557
558 return 0;
559}
560
561static int cz_smu_construct_toc_for_rlc_aram_save(struct amdgpu_device *adev)
562{
563 struct cz_smu_private_data *priv = cz_smu_get_priv(adev);
564 priv->toc_entry_aram = priv->toc_entry_used_count;
565 cz_smu_populate_single_scratch_task(adev,
566 CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_ARAM,
567 TASK_TYPE_UCODE_SAVE, true);
568
569 return 0;
570}
571
572static int cz_smu_construct_toc_for_vddgfx_enter(struct amdgpu_device *adev)
573{
574 struct cz_smu_private_data *priv = cz_smu_get_priv(adev);
575 struct TOC *toc = (struct TOC *)priv->toc_buffer.kaddr;
576
577 toc->JobList[JOB_GFX_SAVE] = (uint8_t)priv->toc_entry_used_count;
578 cz_smu_populate_single_scratch_task(adev,
579 CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SCRATCH,
580 TASK_TYPE_UCODE_SAVE, false);
581 cz_smu_populate_single_scratch_task(adev,
582 CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_DRAM,
583 TASK_TYPE_UCODE_SAVE, true);
584
585 return 0;
586}
587
588static int cz_smu_construct_toc_for_vddgfx_exit(struct amdgpu_device *adev)
589{
590 struct cz_smu_private_data *priv = cz_smu_get_priv(adev);
591 struct TOC *toc = (struct TOC *)priv->toc_buffer.kaddr;
592
593 toc->JobList[JOB_GFX_RESTORE] = (uint8_t)priv->toc_entry_used_count;
594
595 /* populate ucode */
596 if (adev->firmware.smu_load) {
597 cz_smu_populate_single_ucode_load_task(adev,
598 CZ_SCRATCH_ENTRY_UCODE_ID_CP_CE, false);
599 cz_smu_populate_single_ucode_load_task(adev,
600 CZ_SCRATCH_ENTRY_UCODE_ID_CP_PFP, false);
601 cz_smu_populate_single_ucode_load_task(adev,
602 CZ_SCRATCH_ENTRY_UCODE_ID_CP_ME, false);
603 cz_smu_populate_single_ucode_load_task(adev,
604 CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, false);
605 if (adev->asic_type == CHIP_STONEY) {
606 cz_smu_populate_single_ucode_load_task(adev,
607 CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, false);
608 } else {
609 cz_smu_populate_single_ucode_load_task(adev,
610 CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2, false);
611 }
612 cz_smu_populate_single_ucode_load_task(adev,
613 CZ_SCRATCH_ENTRY_UCODE_ID_RLC_G, false);
614 }
615
616 /* populate scratch */
617 cz_smu_populate_single_scratch_task(adev,
618 CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SCRATCH,
619 TASK_TYPE_UCODE_LOAD, false);
620 cz_smu_populate_single_scratch_task(adev,
621 CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_ARAM,
622 TASK_TYPE_UCODE_LOAD, false);
623 cz_smu_populate_single_scratch_task(adev,
624 CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_DRAM,
625 TASK_TYPE_UCODE_LOAD, true);
626
627 return 0;
628}
629
630static int cz_smu_construct_toc_for_power_profiling(struct amdgpu_device *adev)
631{
632 struct cz_smu_private_data *priv = cz_smu_get_priv(adev);
633
634 priv->toc_entry_power_profiling_index = priv->toc_entry_used_count;
635
636 cz_smu_populate_single_scratch_task(adev,
637 CZ_SCRATCH_ENTRY_UCODE_ID_POWER_PROFILING,
638 TASK_TYPE_INITIALIZE, true);
639 return 0;
640}
641
642static int cz_smu_construct_toc_for_bootup(struct amdgpu_device *adev)
643{
644 struct cz_smu_private_data *priv = cz_smu_get_priv(adev);
645
646 priv->toc_entry_initialize_index = priv->toc_entry_used_count;
647
648 if (adev->firmware.smu_load) {
649 cz_smu_populate_single_ucode_load_task(adev,
650 CZ_SCRATCH_ENTRY_UCODE_ID_SDMA0, false);
651 if (adev->asic_type == CHIP_STONEY) {
652 cz_smu_populate_single_ucode_load_task(adev,
653 CZ_SCRATCH_ENTRY_UCODE_ID_SDMA0, false);
654 } else {
655 cz_smu_populate_single_ucode_load_task(adev,
656 CZ_SCRATCH_ENTRY_UCODE_ID_SDMA1, false);
657 }
658 cz_smu_populate_single_ucode_load_task(adev,
659 CZ_SCRATCH_ENTRY_UCODE_ID_CP_CE, false);
660 cz_smu_populate_single_ucode_load_task(adev,
661 CZ_SCRATCH_ENTRY_UCODE_ID_CP_PFP, false);
662 cz_smu_populate_single_ucode_load_task(adev,
663 CZ_SCRATCH_ENTRY_UCODE_ID_CP_ME, false);
664 cz_smu_populate_single_ucode_load_task(adev,
665 CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, false);
666 if (adev->asic_type == CHIP_STONEY) {
667 cz_smu_populate_single_ucode_load_task(adev,
668 CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, false);
669 } else {
670 cz_smu_populate_single_ucode_load_task(adev,
671 CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2, false);
672 }
673 cz_smu_populate_single_ucode_load_task(adev,
674 CZ_SCRATCH_ENTRY_UCODE_ID_RLC_G, true);
675 }
676
677 return 0;
678}
679
680static int cz_smu_construct_toc_for_clock_table(struct amdgpu_device *adev)
681{
682 struct cz_smu_private_data *priv = cz_smu_get_priv(adev);
683
684 priv->toc_entry_clock_table = priv->toc_entry_used_count;
685
686 cz_smu_populate_single_scratch_task(adev,
687 CZ_SCRATCH_ENTRY_SMU8_FUSION_CLKTABLE,
688 TASK_TYPE_INITIALIZE, true);
689
690 return 0;
691}
692
693static int cz_smu_initialize_toc_empty_job_list(struct amdgpu_device *adev)
694{
695 int i;
696 struct cz_smu_private_data *priv = cz_smu_get_priv(adev);
697 struct TOC *toc = (struct TOC *)priv->toc_buffer.kaddr;
698
699 for (i = 0; i < NUM_JOBLIST_ENTRIES; i++)
700 toc->JobList[i] = (uint8_t)IGNORE_JOB;
701
702 return 0;
703}
704
705/*
706 * cz smu uninitialization
707 */
708int cz_smu_fini(struct amdgpu_device *adev)
709{
710 amdgpu_bo_unref(&adev->smu.toc_buf);
711 amdgpu_bo_unref(&adev->smu.smu_buf);
712 kfree(adev->smu.priv);
713 adev->smu.priv = NULL;
714 if (adev->firmware.smu_load)
715 amdgpu_ucode_fini_bo(adev);
716
717 return 0;
718}
719
720int cz_smu_download_pptable(struct amdgpu_device *adev, void **table)
721{
722 uint8_t i;
723 struct cz_smu_private_data *priv = cz_smu_get_priv(adev);
724
725 for (i = 0; i < priv->scratch_buffer_length; i++)
726 if (priv->scratch_buffer[i].firmware_ID ==
727 CZ_SCRATCH_ENTRY_SMU8_FUSION_CLKTABLE)
728 break;
729
730 if (i >= priv->scratch_buffer_length) {
731 dev_err(adev->dev, "Invalid Scratch Type\n");
732 return -EINVAL;
733 }
734
735 *table = (struct SMU8_Fusion_ClkTable *)priv->scratch_buffer[i].kaddr;
736
737 /* prepare buffer for pptable */
738 cz_send_msg_to_smc_with_parameter(adev,
739 PPSMC_MSG_SetClkTableAddrHi,
740 priv->scratch_buffer[i].mc_addr_high);
741 cz_send_msg_to_smc_with_parameter(adev,
742 PPSMC_MSG_SetClkTableAddrLo,
743 priv->scratch_buffer[i].mc_addr_low);
744 cz_send_msg_to_smc_with_parameter(adev,
745 PPSMC_MSG_ExecuteJob,
746 priv->toc_entry_clock_table);
747
748 /* actual downloading */
749 cz_send_msg_to_smc(adev, PPSMC_MSG_ClkTableXferToDram);
750
751 return 0;
752}
753
754int cz_smu_upload_pptable(struct amdgpu_device *adev)
755{
756 uint8_t i;
757 struct cz_smu_private_data *priv = cz_smu_get_priv(adev);
758
759 for (i = 0; i < priv->scratch_buffer_length; i++)
760 if (priv->scratch_buffer[i].firmware_ID ==
761 CZ_SCRATCH_ENTRY_SMU8_FUSION_CLKTABLE)
762 break;
763
764 if (i >= priv->scratch_buffer_length) {
765 dev_err(adev->dev, "Invalid Scratch Type\n");
766 return -EINVAL;
767 }
768
769 /* prepare SMU */
770 cz_send_msg_to_smc_with_parameter(adev,
771 PPSMC_MSG_SetClkTableAddrHi,
772 priv->scratch_buffer[i].mc_addr_high);
773 cz_send_msg_to_smc_with_parameter(adev,
774 PPSMC_MSG_SetClkTableAddrLo,
775 priv->scratch_buffer[i].mc_addr_low);
776 cz_send_msg_to_smc_with_parameter(adev,
777 PPSMC_MSG_ExecuteJob,
778 priv->toc_entry_clock_table);
779
780 /* actual uploading */
781 cz_send_msg_to_smc(adev, PPSMC_MSG_ClkTableXferToSmu);
782
783 return 0;
784}
785
786/*
787 * cz smumgr functions initialization
788 */
789static const struct amdgpu_smumgr_funcs cz_smumgr_funcs = {
790 .check_fw_load_finish = cz_smu_check_finished,
791 .request_smu_load_fw = NULL,
792 .request_smu_specific_fw = NULL,
793};
794
795/*
796 * cz smu initialization
797 */
798int cz_smu_init(struct amdgpu_device *adev)
799{
800 int ret = -EINVAL;
801 uint64_t mc_addr = 0;
802 struct amdgpu_bo **toc_buf = &adev->smu.toc_buf;
803 struct amdgpu_bo **smu_buf = &adev->smu.smu_buf;
804 void *toc_buf_ptr = NULL;
805 void *smu_buf_ptr = NULL;
806
807 struct cz_smu_private_data *priv =
808 kzalloc(sizeof(struct cz_smu_private_data), GFP_KERNEL);
809 if (priv == NULL)
810 return -ENOMEM;
811
812 /* allocate firmware buffers */
813 if (adev->firmware.smu_load)
814 amdgpu_ucode_init_bo(adev);
815
816 adev->smu.priv = priv;
817 adev->smu.fw_flags = 0;
818 priv->toc_buffer.data_size = 4096;
819
820 priv->smu_buffer.data_size =
821 ALIGN(UCODE_ID_RLC_SCRATCH_SIZE_BYTE, 32) +
822 ALIGN(UCODE_ID_RLC_SRM_ARAM_SIZE_BYTE, 32) +
823 ALIGN(UCODE_ID_RLC_SRM_DRAM_SIZE_BYTE, 32) +
824 ALIGN(sizeof(struct SMU8_MultimediaPowerLogData), 32) +
825 ALIGN(sizeof(struct SMU8_Fusion_ClkTable), 32);
826
827 /* prepare toc buffer and smu buffer:
828 * 1. create amdgpu_bo for toc buffer and smu buffer
829 * 2. pin mc address
830 * 3. map kernel virtual address
831 */
832 ret = amdgpu_bo_create(adev, priv->toc_buffer.data_size, PAGE_SIZE,
833 true, AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
834 toc_buf);
835
836 if (ret) {
837 dev_err(adev->dev, "(%d) SMC TOC buffer allocation failed\n", ret);
838 return ret;
839 }
840
841 ret = amdgpu_bo_create(adev, priv->smu_buffer.data_size, PAGE_SIZE,
842 true, AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
843 smu_buf);
844
845 if (ret) {
846 dev_err(adev->dev, "(%d) SMC Internal buffer allocation failed\n", ret);
847 return ret;
848 }
849
850 /* toc buffer reserve/pin/map */
851 ret = amdgpu_bo_reserve(adev->smu.toc_buf, false);
852 if (ret) {
853 amdgpu_bo_unref(&adev->smu.toc_buf);
854 dev_err(adev->dev, "(%d) SMC TOC buffer reserve failed\n", ret);
855 return ret;
856 }
857
858 ret = amdgpu_bo_pin(adev->smu.toc_buf, AMDGPU_GEM_DOMAIN_GTT, &mc_addr);
859 if (ret) {
860 amdgpu_bo_unreserve(adev->smu.toc_buf);
861 amdgpu_bo_unref(&adev->smu.toc_buf);
862 dev_err(adev->dev, "(%d) SMC TOC buffer pin failed\n", ret);
863 return ret;
864 }
865
866 ret = amdgpu_bo_kmap(*toc_buf, &toc_buf_ptr);
867 if (ret)
868 goto smu_init_failed;
869
870 amdgpu_bo_unreserve(adev->smu.toc_buf);
871
872 priv->toc_buffer.mc_addr_low = lower_32_bits(mc_addr);
873 priv->toc_buffer.mc_addr_high = upper_32_bits(mc_addr);
874 priv->toc_buffer.kaddr = toc_buf_ptr;
875
876 /* smu buffer reserve/pin/map */
877 ret = amdgpu_bo_reserve(adev->smu.smu_buf, false);
878 if (ret) {
879 amdgpu_bo_unref(&adev->smu.smu_buf);
880 dev_err(adev->dev, "(%d) SMC Internal buffer reserve failed\n", ret);
881 return ret;
882 }
883
884 ret = amdgpu_bo_pin(adev->smu.smu_buf, AMDGPU_GEM_DOMAIN_GTT, &mc_addr);
885 if (ret) {
886 amdgpu_bo_unreserve(adev->smu.smu_buf);
887 amdgpu_bo_unref(&adev->smu.smu_buf);
888 dev_err(adev->dev, "(%d) SMC Internal buffer pin failed\n", ret);
889 return ret;
890 }
891
892 ret = amdgpu_bo_kmap(*smu_buf, &smu_buf_ptr);
893 if (ret)
894 goto smu_init_failed;
895
896 amdgpu_bo_unreserve(adev->smu.smu_buf);
897
898 priv->smu_buffer.mc_addr_low = lower_32_bits(mc_addr);
899 priv->smu_buffer.mc_addr_high = upper_32_bits(mc_addr);
900 priv->smu_buffer.kaddr = smu_buf_ptr;
901
902 if (adev->firmware.smu_load) {
903 if (cz_smu_populate_single_firmware_entry(adev,
904 CZ_SCRATCH_ENTRY_UCODE_ID_SDMA0,
905 &priv->driver_buffer[priv->driver_buffer_length++]))
906 goto smu_init_failed;
907
908 if (adev->asic_type == CHIP_STONEY) {
909 if (cz_smu_populate_single_firmware_entry(adev,
910 CZ_SCRATCH_ENTRY_UCODE_ID_SDMA0,
911 &priv->driver_buffer[priv->driver_buffer_length++]))
912 goto smu_init_failed;
913 } else {
914 if (cz_smu_populate_single_firmware_entry(adev,
915 CZ_SCRATCH_ENTRY_UCODE_ID_SDMA1,
916 &priv->driver_buffer[priv->driver_buffer_length++]))
917 goto smu_init_failed;
918 }
919 if (cz_smu_populate_single_firmware_entry(adev,
920 CZ_SCRATCH_ENTRY_UCODE_ID_CP_CE,
921 &priv->driver_buffer[priv->driver_buffer_length++]))
922 goto smu_init_failed;
923 if (cz_smu_populate_single_firmware_entry(adev,
924 CZ_SCRATCH_ENTRY_UCODE_ID_CP_PFP,
925 &priv->driver_buffer[priv->driver_buffer_length++]))
926 goto smu_init_failed;
927 if (cz_smu_populate_single_firmware_entry(adev,
928 CZ_SCRATCH_ENTRY_UCODE_ID_CP_ME,
929 &priv->driver_buffer[priv->driver_buffer_length++]))
930 goto smu_init_failed;
931 if (cz_smu_populate_single_firmware_entry(adev,
932 CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1,
933 &priv->driver_buffer[priv->driver_buffer_length++]))
934 goto smu_init_failed;
935 if (adev->asic_type == CHIP_STONEY) {
936 if (cz_smu_populate_single_firmware_entry(adev,
937 CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1,
938 &priv->driver_buffer[priv->driver_buffer_length++]))
939 goto smu_init_failed;
940 } else {
941 if (cz_smu_populate_single_firmware_entry(adev,
942 CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2,
943 &priv->driver_buffer[priv->driver_buffer_length++]))
944 goto smu_init_failed;
945 }
946 if (cz_smu_populate_single_firmware_entry(adev,
947 CZ_SCRATCH_ENTRY_UCODE_ID_RLC_G,
948 &priv->driver_buffer[priv->driver_buffer_length++]))
949 goto smu_init_failed;
950 }
951
952 if (cz_smu_populate_single_scratch_entry(adev,
953 CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SCRATCH,
954 UCODE_ID_RLC_SCRATCH_SIZE_BYTE,
955 &priv->scratch_buffer[priv->scratch_buffer_length++]))
956 goto smu_init_failed;
957 if (cz_smu_populate_single_scratch_entry(adev,
958 CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_ARAM,
959 UCODE_ID_RLC_SRM_ARAM_SIZE_BYTE,
960 &priv->scratch_buffer[priv->scratch_buffer_length++]))
961 goto smu_init_failed;
962 if (cz_smu_populate_single_scratch_entry(adev,
963 CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_DRAM,
964 UCODE_ID_RLC_SRM_DRAM_SIZE_BYTE,
965 &priv->scratch_buffer[priv->scratch_buffer_length++]))
966 goto smu_init_failed;
967 if (cz_smu_populate_single_scratch_entry(adev,
968 CZ_SCRATCH_ENTRY_UCODE_ID_POWER_PROFILING,
969 sizeof(struct SMU8_MultimediaPowerLogData),
970 &priv->scratch_buffer[priv->scratch_buffer_length++]))
971 goto smu_init_failed;
972 if (cz_smu_populate_single_scratch_entry(adev,
973 CZ_SCRATCH_ENTRY_SMU8_FUSION_CLKTABLE,
974 sizeof(struct SMU8_Fusion_ClkTable),
975 &priv->scratch_buffer[priv->scratch_buffer_length++]))
976 goto smu_init_failed;
977
978 cz_smu_initialize_toc_empty_job_list(adev);
979 cz_smu_construct_toc_for_rlc_aram_save(adev);
980 cz_smu_construct_toc_for_vddgfx_enter(adev);
981 cz_smu_construct_toc_for_vddgfx_exit(adev);
982 cz_smu_construct_toc_for_power_profiling(adev);
983 cz_smu_construct_toc_for_bootup(adev);
984 cz_smu_construct_toc_for_clock_table(adev);
985 /* init the smumgr functions */
986 adev->smu.smumgr_funcs = &cz_smumgr_funcs;
987
988 return 0;
989
990smu_init_failed:
991 amdgpu_bo_unref(toc_buf);
992 amdgpu_bo_unref(smu_buf);
993
994 return ret;
995}
diff --git a/drivers/gpu/drm/amd/amdgpu/cz_smumgr.h b/drivers/gpu/drm/amd/amdgpu/cz_smumgr.h
deleted file mode 100644
index 026342fcf0f3..000000000000
--- a/drivers/gpu/drm/amd/amdgpu/cz_smumgr.h
+++ /dev/null
@@ -1,94 +0,0 @@
1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#ifndef __CZ_SMC_H__
24#define __CZ_SMC_H__
25
26#define MAX_NUM_FIRMWARE 8
27#define MAX_NUM_SCRATCH 11
28#define CZ_SCRATCH_SIZE_NONGFX_CLOCKGATING 1024
29#define CZ_SCRATCH_SIZE_NONGFX_GOLDENSETTING 2048
30#define CZ_SCRATCH_SIZE_SDMA_METADATA 1024
31#define CZ_SCRATCH_SIZE_IH ((2*256+1)*4)
32
33enum cz_scratch_entry {
34 CZ_SCRATCH_ENTRY_UCODE_ID_SDMA0 = 0,
35 CZ_SCRATCH_ENTRY_UCODE_ID_SDMA1,
36 CZ_SCRATCH_ENTRY_UCODE_ID_CP_CE,
37 CZ_SCRATCH_ENTRY_UCODE_ID_CP_PFP,
38 CZ_SCRATCH_ENTRY_UCODE_ID_CP_ME,
39 CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1,
40 CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2,
41 CZ_SCRATCH_ENTRY_UCODE_ID_GMCON_RENG,
42 CZ_SCRATCH_ENTRY_UCODE_ID_RLC_G,
43 CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SCRATCH,
44 CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_ARAM,
45 CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_DRAM,
46 CZ_SCRATCH_ENTRY_UCODE_ID_DMCU_ERAM,
47 CZ_SCRATCH_ENTRY_UCODE_ID_DMCU_IRAM,
48 CZ_SCRATCH_ENTRY_UCODE_ID_POWER_PROFILING,
49 CZ_SCRATCH_ENTRY_DATA_ID_SDMA_HALT,
50 CZ_SCRATCH_ENTRY_DATA_ID_SYS_CLOCKGATING,
51 CZ_SCRATCH_ENTRY_DATA_ID_SDMA_RING_REGS,
52 CZ_SCRATCH_ENTRY_DATA_ID_NONGFX_REINIT,
53 CZ_SCRATCH_ENTRY_DATA_ID_SDMA_START,
54 CZ_SCRATCH_ENTRY_DATA_ID_IH_REGISTERS,
55 CZ_SCRATCH_ENTRY_SMU8_FUSION_CLKTABLE
56};
57
58struct cz_buffer_entry {
59 uint32_t data_size;
60 uint32_t mc_addr_low;
61 uint32_t mc_addr_high;
62 void *kaddr;
63 enum cz_scratch_entry firmware_ID;
64};
65
66struct cz_register_index_data_pair {
67 uint32_t offset;
68 uint32_t value;
69};
70
71struct cz_ih_meta_data {
72 uint32_t command;
73 struct cz_register_index_data_pair register_index_value_pair[1];
74};
75
76struct cz_smu_private_data {
77 uint8_t driver_buffer_length;
78 uint8_t scratch_buffer_length;
79 uint16_t toc_entry_used_count;
80 uint16_t toc_entry_initialize_index;
81 uint16_t toc_entry_power_profiling_index;
82 uint16_t toc_entry_aram;
83 uint16_t toc_entry_ih_register_restore_task_index;
84 uint16_t toc_entry_clock_table;
85 uint16_t ih_register_restore_task_size;
86 uint16_t smu_buffer_used_bytes;
87
88 struct cz_buffer_entry toc_buffer;
89 struct cz_buffer_entry smu_buffer;
90 struct cz_buffer_entry driver_buffer[MAX_NUM_FIRMWARE];
91 struct cz_buffer_entry scratch_buffer[MAX_NUM_SCRATCH];
92};
93
94#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-29 10:09:43 -0400