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authorHuang Rui <ray.huang@amd.com>2016-12-26 02:09:33 -0500
committerAlex Deucher <alexander.deucher@amd.com>2017-01-27 11:12:51 -0500
commit634a24d8af026d7e7df9b8c3a5efe3802de1299c (patch)
tree8d50e504db5e5d9cdfa382530c85b9df0d487d14
parentb5c11b8e37aa032773886c10bfc67179d7862070 (diff)
drm/amd/powerplay: update all printk to pr_* on smumgr
Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat
-rw-r--r--drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c28
-rw-r--r--drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c4
-rw-r--r--drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c8
-rw-r--r--drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c8
-rw-r--r--drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c2
-rw-r--r--drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c4
-rw-r--r--drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c8
-rw-r--r--drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c12
-rw-r--r--drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.c14
-rw-r--r--drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c2
10 files changed, 45 insertions, 45 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c
index 5a44485526d2..46052306d0f5 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c
@@ -70,7 +70,7 @@ static int cz_send_msg_to_smc_async(struct pp_smumgr *smumgr,
70 result = SMUM_WAIT_FIELD_UNEQUAL(smumgr, 70 result = SMUM_WAIT_FIELD_UNEQUAL(smumgr,
71 SMU_MP1_SRBM2P_RESP_0, CONTENT, 0); 71 SMU_MP1_SRBM2P_RESP_0, CONTENT, 0);
72 if (result != 0) { 72 if (result != 0) {
73 printk(KERN_ERR "[ powerplay ] cz_send_msg_to_smc_async failed\n"); 73 pr_err("cz_send_msg_to_smc_async failed\n");
74 return result; 74 return result;
75 } 75 }
76 76
@@ -100,12 +100,12 @@ static int cz_set_smc_sram_address(struct pp_smumgr *smumgr,
100 return -EINVAL; 100 return -EINVAL;
101 101
102 if (0 != (3 & smc_address)) { 102 if (0 != (3 & smc_address)) {
103 printk(KERN_ERR "[ powerplay ] SMC address must be 4 byte aligned\n"); 103 pr_err("SMC address must be 4 byte aligned\n");
104 return -EINVAL; 104 return -EINVAL;
105 } 105 }
106 106
107 if (limit <= (smc_address + 3)) { 107 if (limit <= (smc_address + 3)) {
108 printk(KERN_ERR "[ powerplay ] SMC address beyond the SMC RAM area\n"); 108 pr_err("SMC address beyond the SMC RAM area\n");
109 return -EINVAL; 109 return -EINVAL;
110 } 110 }
111 111
@@ -147,7 +147,7 @@ static int cz_request_smu_load_fw(struct pp_smumgr *smumgr)
147 uint32_t smc_address; 147 uint32_t smc_address;
148 148
149 if (!smumgr->reload_fw) { 149 if (!smumgr->reload_fw) {
150 printk(KERN_INFO "[ powerplay ] skip reloading...\n"); 150 pr_info("skip reloading...\n");
151 return 0; 151 return 0;
152 } 152 }
153 153
@@ -198,7 +198,7 @@ static int cz_check_fw_load_finish(struct pp_smumgr *smumgr,
198 } 198 }
199 199
200 if (i >= smumgr->usec_timeout) { 200 if (i >= smumgr->usec_timeout) {
201 printk(KERN_ERR "[ powerplay ] SMU check loaded firmware failed.\n"); 201 pr_err("SMU check loaded firmware failed.\n");
202 return -EINVAL; 202 return -EINVAL;
203 } 203 }
204 204
@@ -267,13 +267,13 @@ static int cz_start_smu(struct pp_smumgr *smumgr)
267 267
268 ret = cz_request_smu_load_fw(smumgr); 268 ret = cz_request_smu_load_fw(smumgr);
269 if (ret) 269 if (ret)
270 printk(KERN_ERR "[ powerplay] SMU firmware load failed\n"); 270 pr_err("SMU firmware load failed\n");
271 271
272 cz_check_fw_load_finish(smumgr, fw_to_check); 272 cz_check_fw_load_finish(smumgr, fw_to_check);
273 273
274 ret = cz_load_mec_firmware(smumgr); 274 ret = cz_load_mec_firmware(smumgr);
275 if (ret) 275 if (ret)
276 printk(KERN_ERR "[ powerplay ] Mec Firmware load failed\n"); 276 pr_err("Mec Firmware load failed\n");
277 277
278 return ret; 278 return ret;
279} 279}
@@ -406,7 +406,7 @@ static int cz_smu_populate_single_scratch_task(
406 break; 406 break;
407 407
408 if (i >= cz_smu->scratch_buffer_length) { 408 if (i >= cz_smu->scratch_buffer_length) {
409 printk(KERN_ERR "[ powerplay ] Invalid Firmware Type\n"); 409 pr_err("Invalid Firmware Type\n");
410 return -EINVAL; 410 return -EINVAL;
411 } 411 }
412 412
@@ -443,7 +443,7 @@ static int cz_smu_populate_single_ucode_load_task(
443 break; 443 break;
444 444
445 if (i >= cz_smu->driver_buffer_length) { 445 if (i >= cz_smu->driver_buffer_length) {
446 printk(KERN_ERR "[ powerplay ] Invalid Firmware Type\n"); 446 pr_err("Invalid Firmware Type\n");
447 return -EINVAL; 447 return -EINVAL;
448 } 448 }
449 449
@@ -774,7 +774,7 @@ static int cz_smu_init(struct pp_smumgr *smumgr)
774 CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SCRATCH, 774 CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SCRATCH,
775 UCODE_ID_RLC_SCRATCH_SIZE_BYTE, 775 UCODE_ID_RLC_SCRATCH_SIZE_BYTE,
776 &cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) { 776 &cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) {
777 printk(KERN_ERR "[ powerplay ] Error when Populate Firmware Entry.\n"); 777 pr_err("Error when Populate Firmware Entry.\n");
778 return -1; 778 return -1;
779 } 779 }
780 780
@@ -782,14 +782,14 @@ static int cz_smu_init(struct pp_smumgr *smumgr)
782 CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_ARAM, 782 CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_ARAM,
783 UCODE_ID_RLC_SRM_ARAM_SIZE_BYTE, 783 UCODE_ID_RLC_SRM_ARAM_SIZE_BYTE,
784 &cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) { 784 &cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) {
785 printk(KERN_ERR "[ powerplay ] Error when Populate Firmware Entry.\n"); 785 pr_err("Error when Populate Firmware Entry.\n");
786 return -1; 786 return -1;
787 } 787 }
788 if (0 != cz_smu_populate_single_scratch_entry(smumgr, 788 if (0 != cz_smu_populate_single_scratch_entry(smumgr,
789 CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_DRAM, 789 CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_DRAM,
790 UCODE_ID_RLC_SRM_DRAM_SIZE_BYTE, 790 UCODE_ID_RLC_SRM_DRAM_SIZE_BYTE,
791 &cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) { 791 &cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) {
792 printk(KERN_ERR "[ powerplay ] Error when Populate Firmware Entry.\n"); 792 pr_err("Error when Populate Firmware Entry.\n");
793 return -1; 793 return -1;
794 } 794 }
795 795
@@ -797,7 +797,7 @@ static int cz_smu_init(struct pp_smumgr *smumgr)
797 CZ_SCRATCH_ENTRY_UCODE_ID_POWER_PROFILING, 797 CZ_SCRATCH_ENTRY_UCODE_ID_POWER_PROFILING,
798 sizeof(struct SMU8_MultimediaPowerLogData), 798 sizeof(struct SMU8_MultimediaPowerLogData),
799 &cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) { 799 &cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) {
800 printk(KERN_ERR "[ powerplay ] Error when Populate Firmware Entry.\n"); 800 pr_err("Error when Populate Firmware Entry.\n");
801 return -1; 801 return -1;
802 } 802 }
803 803
@@ -805,7 +805,7 @@ static int cz_smu_init(struct pp_smumgr *smumgr)
805 CZ_SCRATCH_ENTRY_SMU8_FUSION_CLKTABLE, 805 CZ_SCRATCH_ENTRY_SMU8_FUSION_CLKTABLE,
806 sizeof(struct SMU8_Fusion_ClkTable), 806 sizeof(struct SMU8_Fusion_ClkTable),
807 &cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) { 807 &cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) {
808 printk(KERN_ERR "[ powerplay ] Error when Populate Firmware Entry.\n"); 808 pr_err("Error when Populate Firmware Entry.\n");
809 return -1; 809 return -1;
810 } 810 }
811 cz_smu_construct_toc(smumgr); 811 cz_smu_construct_toc(smumgr);
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c
index 5d5b8a0b4f19..0f7a77b7312e 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c
@@ -2131,7 +2131,7 @@ uint32_t fiji_get_offsetof(uint32_t type, uint32_t member)
2131 return offsetof(SMU73_Discrete_DpmTable, LowSclkInterruptThreshold); 2131 return offsetof(SMU73_Discrete_DpmTable, LowSclkInterruptThreshold);
2132 } 2132 }
2133 } 2133 }
2134 printk(KERN_WARNING "can't get the offset of type %x member %x\n", type, member); 2134 pr_warning("can't get the offset of type %x member %x\n", type, member);
2135 return 0; 2135 return 0;
2136} 2136}
2137 2137
@@ -2156,7 +2156,7 @@ uint32_t fiji_get_mac_definition(uint32_t value)
2156 return SMU73_MAX_LEVELS_MVDD; 2156 return SMU73_MAX_LEVELS_MVDD;
2157 } 2157 }
2158 2158
2159 printk(KERN_WARNING "can't get the mac of %x\n", value); 2159 pr_warning("can't get the mac of %x\n", value);
2160 return 0; 2160 return 0;
2161} 2161}
2162 2162
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
index 7a87e5a0451a..71ff0bc09bb2 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
@@ -179,7 +179,7 @@ static int fiji_setup_pwr_virus(struct pp_smumgr *smumgr)
179 result = 0; 179 result = 0;
180 break; 180 break;
181 default: 181 default:
182 printk(KERN_ERR "Table Exit with Invalid Command!"); 182 pr_err("Table Exit with Invalid Command!");
183 priv->avfs.AvfsBtcStatus = AVFS_BTC_VIRUS_FAIL; 183 priv->avfs.AvfsBtcStatus = AVFS_BTC_VIRUS_FAIL;
184 result = -1; 184 result = -1;
185 break; 185 break;
@@ -202,13 +202,13 @@ static int fiji_start_avfs_btc(struct pp_smumgr *smumgr)
202 priv->avfs.AvfsBtcStatus = AVFS_BTC_COMPLETED_UNSAVED; 202 priv->avfs.AvfsBtcStatus = AVFS_BTC_COMPLETED_UNSAVED;
203 result = 0; 203 result = 0;
204 } else { 204 } else {
205 printk(KERN_ERR "[AVFS][fiji_start_avfs_btc] Attempt" 205 pr_err("[AVFS][fiji_start_avfs_btc] Attempt"
206 " to Enable AVFS Failed!"); 206 " to Enable AVFS Failed!");
207 smum_send_msg_to_smc(smumgr, PPSMC_MSG_DisableAvfs); 207 smum_send_msg_to_smc(smumgr, PPSMC_MSG_DisableAvfs);
208 result = -1; 208 result = -1;
209 } 209 }
210 } else { 210 } else {
211 printk(KERN_ERR "[AVFS][fiji_start_avfs_btc] " 211 pr_err("[AVFS][fiji_start_avfs_btc] "
212 "PerformBTC SMU msg failed"); 212 "PerformBTC SMU msg failed");
213 result = -1; 213 result = -1;
214 } 214 }
@@ -384,7 +384,7 @@ static int fiji_avfs_event_mgr(struct pp_smumgr *smumgr, bool smu_started)
384 case AVFS_BTC_NOTSUPPORTED: /* Do nothing */ 384 case AVFS_BTC_NOTSUPPORTED: /* Do nothing */
385 break; 385 break;
386 default: 386 default:
387 printk(KERN_ERR "[AVFS] Something is broken. See log!"); 387 pr_err("[AVFS] Something is broken. See log!");
388 break; 388 break;
389 } 389 }
390 return 0; 390 return 0;
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c
index ef435f1b61d7..ad82161df831 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c
@@ -1545,7 +1545,7 @@ static int iceland_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
1545 1545
1546 if (0 != result) { 1546 if (0 != result) {
1547 smu_data->smc_state_table.GraphicsBootLevel = 0; 1547 smu_data->smc_state_table.GraphicsBootLevel = 0;
1548 printk(KERN_ERR "[ powerplay ] VBIOS did not find boot engine clock value \ 1548 pr_err("VBIOS did not find boot engine clock value \
1549 in dependency table. Using Graphics DPM level 0!"); 1549 in dependency table. Using Graphics DPM level 0!");
1550 result = 0; 1550 result = 0;
1551 } 1551 }
@@ -1556,7 +1556,7 @@ static int iceland_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
1556 1556
1557 if (0 != result) { 1557 if (0 != result) {
1558 smu_data->smc_state_table.MemoryBootLevel = 0; 1558 smu_data->smc_state_table.MemoryBootLevel = 0;
1559 printk(KERN_ERR "[ powerplay ] VBIOS did not find boot engine clock value \ 1559 pr_err("VBIOS did not find boot engine clock value \
1560 in dependency table. Using Memory DPM level 0!"); 1560 in dependency table. Using Memory DPM level 0!");
1561 result = 0; 1561 result = 0;
1562 } 1562 }
@@ -2146,7 +2146,7 @@ uint32_t iceland_get_offsetof(uint32_t type, uint32_t member)
2146 return offsetof(SMU71_Discrete_DpmTable, LowSclkInterruptThreshold); 2146 return offsetof(SMU71_Discrete_DpmTable, LowSclkInterruptThreshold);
2147 } 2147 }
2148 } 2148 }
2149 printk(KERN_WARNING "can't get the offset of type %x member %x\n", type, member); 2149 pr_warning("can't get the offset of type %x member %x\n", type, member);
2150 return 0; 2150 return 0;
2151} 2151}
2152 2152
@@ -2169,7 +2169,7 @@ uint32_t iceland_get_mac_definition(uint32_t value)
2169 return SMU71_MAX_LEVELS_MVDD; 2169 return SMU71_MAX_LEVELS_MVDD;
2170 } 2170 }
2171 2171
2172 printk(KERN_WARNING "can't get the mac of %x\n", value); 2172 pr_warning("can't get the mac of %x\n", value);
2173 return 0; 2173 return 0;
2174} 2174}
2175 2175
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
index 1fde30d20c8d..c830ea363575 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
@@ -176,7 +176,7 @@ static int iceland_start_smu(struct pp_smumgr *smumgr)
176 return result; 176 return result;
177 177
178 if (!smu7_is_smc_ram_running(smumgr)) { 178 if (!smu7_is_smc_ram_running(smumgr)) {
179 printk("smu not running, upload firmware again \n"); 179 pr_info("smu not running, upload firmware again \n");
180 result = iceland_smu_upload_firmware_image(smumgr); 180 result = iceland_smu_upload_firmware_image(smumgr);
181 if (result) 181 if (result)
182 return result; 182 return result;
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c
index c2889b574618..0e26900e459e 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c
@@ -2180,7 +2180,7 @@ uint32_t polaris10_get_offsetof(uint32_t type, uint32_t member)
2180 return offsetof(SMU74_Discrete_DpmTable, LowSclkInterruptThreshold); 2180 return offsetof(SMU74_Discrete_DpmTable, LowSclkInterruptThreshold);
2181 } 2181 }
2182 } 2182 }
2183 printk(KERN_WARNING "can't get the offset of type %x member %x\n", type, member); 2183 pr_warning("can't get the offset of type %x member %x\n", type, member);
2184 return 0; 2184 return 0;
2185} 2185}
2186 2186
@@ -2207,7 +2207,7 @@ uint32_t polaris10_get_mac_definition(uint32_t value)
2207 return SMU7_UVD_MCLK_HANDSHAKE_DISABLE; 2207 return SMU7_UVD_MCLK_HANDSHAKE_DISABLE;
2208 } 2208 }
2209 2209
2210 printk(KERN_WARNING "can't get the mac of %x\n", value); 2210 pr_warning("can't get the mac of %x\n", value);
2211 return 0; 2211 return 0;
2212} 2212}
2213 2213
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
index 7e1e330fa2af..8d6d9143f711 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
@@ -84,7 +84,7 @@ static int polaris10_setup_pwr_virus(struct pp_smumgr *smumgr)
84 break; 84 break;
85 85
86 default: 86 default:
87 printk("Table Exit with Invalid Command!"); 87 pr_info("Table Exit with Invalid Command!");
88 smu_data->avfs.avfs_btc_status = AVFS_BTC_VIRUS_FAIL; 88 smu_data->avfs.avfs_btc_status = AVFS_BTC_VIRUS_FAIL;
89 result = -1; 89 result = -1;
90 break; 90 break;
@@ -102,7 +102,7 @@ static int polaris10_perform_btc(struct pp_smumgr *smumgr)
102 102
103 if (0 != smu_data->avfs.avfs_btc_param) { 103 if (0 != smu_data->avfs.avfs_btc_param) {
104 if (0 != smu7_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_PerformBtc, smu_data->avfs.avfs_btc_param)) { 104 if (0 != smu7_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_PerformBtc, smu_data->avfs.avfs_btc_param)) {
105 printk("[AVFS][SmuPolaris10_PerformBtc] PerformBTC SMU msg failed"); 105 pr_info("[AVFS][SmuPolaris10_PerformBtc] PerformBTC SMU msg failed");
106 result = -1; 106 result = -1;
107 } 107 }
108 } 108 }
@@ -189,7 +189,7 @@ polaris10_avfs_event_mgr(struct pp_smumgr *smumgr, bool SMU_VFT_INTACT)
189 return -1); 189 return -1);
190 190
191 if (smu_data->avfs.avfs_btc_param > 1) { 191 if (smu_data->avfs.avfs_btc_param > 1) {
192 printk("[AVFS][Polaris10_AVFSEventMgr] AC BTC has not been successfully verified on Fiji. There may be in this setting."); 192 pr_info("[AVFS][Polaris10_AVFSEventMgr] AC BTC has not been successfully verified on Fiji. There may be in this setting.");
193 smu_data->avfs.avfs_btc_status = AVFS_BTC_VIRUS_FAIL; 193 smu_data->avfs.avfs_btc_status = AVFS_BTC_VIRUS_FAIL;
194 PP_ASSERT_WITH_CODE(-1 == polaris10_setup_pwr_virus(smumgr), 194 PP_ASSERT_WITH_CODE(-1 == polaris10_setup_pwr_virus(smumgr),
195 "[AVFS][Polaris10_AVFSEventMgr] Could not setup Pwr Virus for AVFS ", 195 "[AVFS][Polaris10_AVFSEventMgr] Could not setup Pwr Virus for AVFS ",
@@ -208,7 +208,7 @@ polaris10_avfs_event_mgr(struct pp_smumgr *smumgr, bool SMU_VFT_INTACT)
208 break; 208 break;
209 209
210 default: 210 default:
211 printk("[AVFS] Something is broken. See log!"); 211 pr_info("[AVFS] Something is broken. See log!");
212 break; 212 break;
213 } 213 }
214 214
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
index d0a77be0c02b..6749fbe26c74 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
@@ -175,7 +175,7 @@ int smu7_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg)
175 ret = SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP); 175 ret = SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP);
176 176
177 if (ret != 1) 177 if (ret != 1)
178 printk("\n failed to send pre message %x ret is %d \n", msg, ret); 178 pr_info("\n failed to send pre message %x ret is %d \n", msg, ret);
179 179
180 cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, msg); 180 cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, msg);
181 181
@@ -184,7 +184,7 @@ int smu7_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg)
184 ret = SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP); 184 ret = SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP);
185 185
186 if (ret != 1) 186 if (ret != 1)
187 printk("\n failed to send message %x ret is %d \n", msg, ret); 187 pr_info("\n failed to send message %x ret is %d \n", msg, ret);
188 188
189 return 0; 189 return 0;
190} 190}
@@ -225,7 +225,7 @@ int smu7_send_msg_to_smc_offset(struct pp_smumgr *smumgr)
225 SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0); 225 SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
226 226
227 if (1 != SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP)) 227 if (1 != SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP))
228 printk("Failed to send Message.\n"); 228 pr_info("Failed to send Message.\n");
229 229
230 return 0; 230 return 0;
231} 231}
@@ -347,7 +347,7 @@ static uint32_t smu7_get_mask_for_firmware_type(uint32_t fw_type)
347 result = UCODE_ID_RLC_G_MASK; 347 result = UCODE_ID_RLC_G_MASK;
348 break; 348 break;
349 default: 349 default:
350 printk("UCode type is out of range! \n"); 350 pr_info("UCode type is out of range! \n");
351 result = 0; 351 result = 0;
352 } 352 }
353 353
@@ -396,7 +396,7 @@ int smu7_request_smu_load_fw(struct pp_smumgr *smumgr)
396 struct SMU_DRAMData_TOC *toc; 396 struct SMU_DRAMData_TOC *toc;
397 397
398 if (!smumgr->reload_fw) { 398 if (!smumgr->reload_fw) {
399 printk(KERN_INFO "[ powerplay ] skip reloading...\n"); 399 pr_info("skip reloading...\n");
400 return 0; 400 return 0;
401 } 401 }
402 402
@@ -474,7 +474,7 @@ int smu7_request_smu_load_fw(struct pp_smumgr *smumgr)
474 smu7_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_DRV_DRAM_ADDR_LO, smu_data->header_buffer.mc_addr_low); 474 smu7_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_DRV_DRAM_ADDR_LO, smu_data->header_buffer.mc_addr_low);
475 475
476 if (smu7_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_LoadUcodes, fw_to_load)) 476 if (smu7_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_LoadUcodes, fw_to_load))
477 printk(KERN_ERR "Fail to Request SMU Load uCode"); 477 pr_err("Fail to Request SMU Load uCode");
478 478
479 return result; 479 return result;
480} 480}
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.c b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.c
index 93bfb196e242..331b0aba4a13 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.c
@@ -656,7 +656,7 @@ int tonga_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
656 } 656 }
657 } else { 657 } else {
658 if (0 == data->dpm_level_enable_mask.pcie_dpm_enable_mask) 658 if (0 == data->dpm_level_enable_mask.pcie_dpm_enable_mask)
659 printk(KERN_ERR "[ powerplay ] Pcie Dpm Enablemask is 0 !"); 659 pr_err("Pcie Dpm Enablemask is 0 !");
660 660
661 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask && 661 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
662 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & 662 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
@@ -1503,7 +1503,7 @@ static int tonga_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
1503 1503
1504 if (result != 0) { 1504 if (result != 0) {
1505 smu_data->smc_state_table.GraphicsBootLevel = 0; 1505 smu_data->smc_state_table.GraphicsBootLevel = 0;
1506 printk(KERN_ERR "[powerplay] VBIOS did not find boot engine " 1506 pr_err("[powerplay] VBIOS did not find boot engine "
1507 "clock value in dependency table. " 1507 "clock value in dependency table. "
1508 "Using Graphics DPM level 0 !"); 1508 "Using Graphics DPM level 0 !");
1509 result = 0; 1509 result = 0;
@@ -1515,7 +1515,7 @@ static int tonga_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
1515 1515
1516 if (result != 0) { 1516 if (result != 0) {
1517 smu_data->smc_state_table.MemoryBootLevel = 0; 1517 smu_data->smc_state_table.MemoryBootLevel = 0;
1518 printk(KERN_ERR "[powerplay] VBIOS did not find boot " 1518 pr_err("[powerplay] VBIOS did not find boot "
1519 "engine clock value in dependency table." 1519 "engine clock value in dependency table."
1520 "Using Memory DPM level 0 !"); 1520 "Using Memory DPM level 0 !");
1521 result = 0; 1521 result = 0;
@@ -1739,7 +1739,7 @@ static int tonga_populate_vr_config(struct pp_hwmgr *hwmgr,
1739 config = VR_SVI2_PLANE_2; 1739 config = VR_SVI2_PLANE_2;
1740 table->VRConfig |= config; 1740 table->VRConfig |= config;
1741 } else { 1741 } else {
1742 printk(KERN_ERR "[ powerplay ] VDDC and VDDGFX should " 1742 pr_err("VDDC and VDDGFX should "
1743 "be both on SVI2 control in splitted mode !\n"); 1743 "be both on SVI2 control in splitted mode !\n");
1744 } 1744 }
1745 } else { 1745 } else {
@@ -1752,7 +1752,7 @@ static int tonga_populate_vr_config(struct pp_hwmgr *hwmgr,
1752 config = VR_SVI2_PLANE_1; 1752 config = VR_SVI2_PLANE_1;
1753 table->VRConfig |= config; 1753 table->VRConfig |= config;
1754 } else { 1754 } else {
1755 printk(KERN_ERR "[ powerplay ] VDDC should be on " 1755 pr_err("VDDC should be on "
1756 "SVI2 control in merged mode !\n"); 1756 "SVI2 control in merged mode !\n");
1757 } 1757 }
1758 } 1758 }
@@ -2657,7 +2657,7 @@ uint32_t tonga_get_offsetof(uint32_t type, uint32_t member)
2657 return offsetof(SMU72_Discrete_DpmTable, LowSclkInterruptThreshold); 2657 return offsetof(SMU72_Discrete_DpmTable, LowSclkInterruptThreshold);
2658 } 2658 }
2659 } 2659 }
2660 printk(KERN_WARNING "can't get the offset of type %x member %x\n", type, member); 2660 pr_warning("can't get the offset of type %x member %x\n", type, member);
2661 return 0; 2661 return 0;
2662} 2662}
2663 2663
@@ -2681,7 +2681,7 @@ uint32_t tonga_get_mac_definition(uint32_t value)
2681 case SMU_MAX_LEVELS_MVDD: 2681 case SMU_MAX_LEVELS_MVDD:
2682 return SMU72_MAX_LEVELS_MVDD; 2682 return SMU72_MAX_LEVELS_MVDD;
2683 } 2683 }
2684 printk(KERN_WARNING "can't get the mac value %x\n", value); 2684 pr_warning("can't get the mac value %x\n", value);
2685 2685
2686 return 0; 2686 return 0;
2687} 2687}
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
index d0aef72eb8e6..858568b8c980 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
@@ -84,7 +84,7 @@ static int tonga_start_in_protection_mode(struct pp_smumgr *smumgr)
84 /* Check pass/failed indicator */ 84 /* Check pass/failed indicator */
85 if (1 != SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, 85 if (1 != SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device,
86 CGS_IND_REG__SMC, SMU_STATUS, SMU_PASS)) { 86 CGS_IND_REG__SMC, SMU_STATUS, SMU_PASS)) {
87 printk(KERN_ERR "[ powerplay ] SMU Firmware start failed\n"); 87 pr_err("SMU Firmware start failed\n");
88 return -EINVAL; 88 return -EINVAL;
89 } 89 }
90 90
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-26 20:13:37 -0400