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authorArnd Bergmann <arnd@arndb.de>2016-09-14 11:42:12 -0400
committerArnd Bergmann <arnd@arndb.de>2016-09-14 11:42:12 -0400
commitda9070b35ca82465d6fce0f82cf5969f1ec66d6c (patch)
tree8cd71ad699edab6a0a529fb8c067741a093e6be5
parente08644b0c74ce9bc6e79291f6ef52aa0eb6bb139 (diff)
parentfa765e5ef49d57834ee66690ba8ed5932edb7968 (diff)
Merge tag 'renesas-arm64-dt-for-v4.9' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/late
Pull "Renesas ARM64 Based SoC DT Updates for v4.9" from Simon Horman: Clean up: * Remove unnecessary cap-mmc-highspeed property from SDHI nodes on r8a7795 SoC * Add SoC-specific compatible property to audio-dmac nodes on r8a7795 SoC New Board: * Add r8a7794/h3ulcb board Enablement: * Add PFC and GPIO to r8a7796 SoC * Enable DU and USB 2.0 on r8a7795/salvator-x board * Add VTP, FCPV, FCPF and FDP1 to r8a7795 SoC * Set maximum frequency for SDHI clocks on r8a7795 SoC * tag 'renesas-arm64-dt-for-v4.9' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (43 commits) arm64: dts: r8a7796: Add GPIO device nodes arm64: dts: r8a7796: salvator-x: add serial console pins arm64: dts: r8a7796: Add pinctrl device node arm64: dts: r8a7795: salvator-x: Configure pins for the DU RGB output arm64: dts: h3ulcb: enable GPIO leds arm64: dts: h3ulcb: Sound SSI support arm64: dts: h3ulcb: enable SDHI0 arm64: dts: h3ulcb: enable GPIO keys arm64: dts: r8a7795: remove unnecessary cap-mmc-highspeed property arm64: dts: h3ulcb: enable USB2.0 Host channel 1 arm64: dts: h3ulcb: enable USB2 PHY of channel 1 arm64: dts: h3ulcb: enable WDT arm64: dts: h3ulcb: enable EXTALR clk arm64: dts: h3ulcb: enable I2C2 arm64: dts: h3ulcb: enable EthernetAVB arm64: dts: h3ulcb: enable SCIF clk and pins arm64: dts: h3ulcb: initial device tree arm64: dts: h3ulcb: add H3ULCB board DT bindings arm64: dts: r8a7795: Add SoC-specific compatible property to audio-dmac nodes arm64: dts: r8a7795: renesas: salvator-x: Enable DU ...
Diffstat
-rw-r--r--Documentation/devicetree/bindings/arm/shmobile.txt2
-rw-r--r--Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt2
-rw-r--r--arch/arm64/boot/dts/renesas/Makefile2
-rw-r--r--arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts328
-rw-r--r--arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts87
-rw-r--r--arch/arm64/boot/dts/renesas/r8a7795.dtsi276
-rw-r--r--arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts16
-rw-r--r--arch/arm64/boot/dts/renesas/r8a7796.dtsi117
-rw-r--r--drivers/pinctrl/sh-pfc/Kconfig10
-rw-r--r--drivers/pinctrl/sh-pfc/Makefile2
-rw-r--r--drivers/pinctrl/sh-pfc/core.c12
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7792.c2624
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7795.c356
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7796.c2647
-rw-r--r--drivers/pinctrl/sh-pfc/sh_pfc.h109
15 files changed, 6532 insertions, 58 deletions
diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt
index 1df32d339da5..69e42466d9cc 100644
--- a/Documentation/devicetree/bindings/arm/shmobile.txt
+++ b/Documentation/devicetree/bindings/arm/shmobile.txt
@@ -49,6 +49,8 @@ Boards:
49 compatible = "renesas,genmai", "renesas,r7s72100" 49 compatible = "renesas,genmai", "renesas,r7s72100"
50 - Gose 50 - Gose
51 compatible = "renesas,gose", "renesas,r8a7793" 51 compatible = "renesas,gose", "renesas,r8a7793"
52 - H3ULCB (RTP0RC7795SKB00010S)
53 compatible = "renesas,h3ulcb", "renesas,r8a7795";
52 - Henninger 54 - Henninger
53 compatible = "renesas,henninger", "renesas,r8a7791" 55 compatible = "renesas,henninger", "renesas,r8a7791"
54 - Koelsch (RTP0RC7791SEB00010S) 56 - Koelsch (RTP0RC7791SEB00010S)
diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
index e4cf022c992e..13df9498311a 100644
--- a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
@@ -17,9 +17,11 @@ Required Properties:
17 - "renesas,pfc-r8a7779": for R8A7779 (R-Car H1) compatible pin-controller. 17 - "renesas,pfc-r8a7779": for R8A7779 (R-Car H1) compatible pin-controller.
18 - "renesas,pfc-r8a7790": for R8A7790 (R-Car H2) compatible pin-controller. 18 - "renesas,pfc-r8a7790": for R8A7790 (R-Car H2) compatible pin-controller.
19 - "renesas,pfc-r8a7791": for R8A7791 (R-Car M2-W) compatible pin-controller. 19 - "renesas,pfc-r8a7791": for R8A7791 (R-Car M2-W) compatible pin-controller.
20 - "renesas,pfc-r8a7792": for R8A7792 (R-Car V2H) compatible pin-controller.
20 - "renesas,pfc-r8a7793": for R8A7793 (R-Car M2-N) compatible pin-controller. 21 - "renesas,pfc-r8a7793": for R8A7793 (R-Car M2-N) compatible pin-controller.
21 - "renesas,pfc-r8a7794": for R8A7794 (R-Car E2) compatible pin-controller. 22 - "renesas,pfc-r8a7794": for R8A7794 (R-Car E2) compatible pin-controller.
22 - "renesas,pfc-r8a7795": for R8A7795 (R-Car H3) compatible pin-controller. 23 - "renesas,pfc-r8a7795": for R8A7795 (R-Car H3) compatible pin-controller.
24 - "renesas,pfc-r8a7796": for R8A7796 (R-Car M3-W) compatible pin-controller.
23 - "renesas,pfc-sh73a0": for SH73A0 (SH-Mobile AG5) compatible pin-controller. 25 - "renesas,pfc-sh73a0": for SH73A0 (SH-Mobile AG5) compatible pin-controller.
24 26
25 - reg: Base address and length of each memory resource used by the pin 27 - reg: Base address and length of each memory resource used by the pin
diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
index 17139f7003a6..eb72830ec9eb 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -1,4 +1,4 @@
1dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-salvator-x.dtb 1dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-salvator-x.dtb r8a7795-h3ulcb.dtb
2dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-x.dtb 2dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-x.dtb
3 3
4always := $(dtb-y) 4always := $(dtb-y)
diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
new file mode 100644
index 000000000000..bcb11a868343
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
@@ -0,0 +1,328 @@
1/*
2 * Device Tree Source for the H3ULCB board
3 *
4 * Copyright (C) 2016 Renesas Electronics Corp.
5 * Copyright (C) 2016 Cogent Embedded, Inc.
6 *
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
10 */
11
12/dts-v1/;
13#include "r8a7795.dtsi"
14#include <dt-bindings/gpio/gpio.h>
15#include <dt-bindings/input/input.h>
16
17/ {
18 model = "Renesas H3ULCB board based on r8a7795";
19 compatible = "renesas,h3ulcb", "renesas,r8a7795";
20
21 aliases {
22 serial0 = &scif2;
23 ethernet0 = &avb;
24 };
25
26 chosen {
27 stdout-path = "serial0:115200n8";
28 };
29
30 memory@48000000 {
31 device_type = "memory";
32 /* first 128MB is reserved for secure area. */
33 reg = <0x0 0x48000000 0x0 0x38000000>;
34 };
35
36 leds {
37 compatible = "gpio-leds";
38
39 led5 {
40 gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>;
41 };
42 led6 {
43 gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>;
44 };
45 };
46
47 keyboard {
48 compatible = "gpio-keys";
49
50 key-1 {
51 linux,code = <KEY_1>;
52 label = "SW3";
53 wakeup-source;
54 debounce-interval = <20>;
55 gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
56 };
57 };
58
59 x12_clk: x12 {
60 compatible = "fixed-clock";
61 #clock-cells = <0>;
62 clock-frequency = <24576000>;
63 };
64
65 vcc_sdhi0: regulator-vcc-sdhi0 {
66 compatible = "regulator-fixed";
67
68 regulator-name = "SDHI0 Vcc";
69 regulator-min-microvolt = <3300000>;
70 regulator-max-microvolt = <3300000>;
71
72 gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
73 enable-active-high;
74 };
75
76 vccq_sdhi0: regulator-vccq-sdhi0 {
77 compatible = "regulator-gpio";
78
79 regulator-name = "SDHI0 VccQ";
80 regulator-min-microvolt = <1800000>;
81 regulator-max-microvolt = <3300000>;
82
83 gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
84 gpios-states = <1>;
85 states = <3300000 1
86 1800000 0>;
87 };
88
89 audio_clkout: audio-clkout {
90 /*
91 * This is same as <&rcar_sound 0>
92 * but needed to avoid cs2000/rcar_sound probe dead-lock
93 */
94 compatible = "fixed-clock";
95 #clock-cells = <0>;
96 clock-frequency = <11289600>;
97 };
98
99 rsnd_ak4613: sound {
100 compatible = "simple-audio-card";
101
102 simple-audio-card,format = "left_j";
103 simple-audio-card,bitclock-master = <&sndcpu>;
104 simple-audio-card,frame-master = <&sndcpu>;
105
106 sndcpu: simple-audio-card,cpu {
107 sound-dai = <&rcar_sound>;
108 };
109
110 sndcodec: simple-audio-card,codec {
111 sound-dai = <&ak4613>;
112 };
113 };
114};
115
116&extal_clk {
117 clock-frequency = <16666666>;
118};
119
120&extalr_clk {
121 clock-frequency = <32768>;
122};
123
124&pfc {
125 pinctrl-0 = <&scif_clk_pins>;
126 pinctrl-names = "default";
127
128 scif2_pins: scif2 {
129 groups = "scif2_data_a";
130 function = "scif2";
131 };
132
133 scif_clk_pins: scif_clk {
134 groups = "scif_clk_a";
135 function = "scif_clk";
136 };
137
138 i2c2_pins: i2c2 {
139 groups = "i2c2_a";
140 function = "i2c2";
141 };
142
143 avb_pins: avb {
144 groups = "avb_mdc";
145 function = "avb";
146 };
147
148 sdhi0_pins_3v3: sd0_3v3 {
149 groups = "sdhi0_data4", "sdhi0_ctrl";
150 function = "sdhi0";
151 power-source = <3300>;
152 };
153
154 sdhi0_pins_1v8: sd0_1v8 {
155 groups = "sdhi0_data4", "sdhi0_ctrl";
156 function = "sdhi0";
157 power-source = <1800>;
158 };
159
160 sound_pins: sound {
161 groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a";
162 function = "ssi";
163 };
164
165 sound_clk_pins: sound-clk {
166 groups = "audio_clk_a_a", "audio_clk_b_a", "audio_clk_c_a",
167 "audio_clkout_a", "audio_clkout3_a";
168 function = "audio_clk";
169 };
170
171 usb1_pins: usb1 {
172 groups = "usb1";
173 function = "usb1";
174 };
175};
176
177&scif2 {
178 pinctrl-0 = <&scif2_pins>;
179 pinctrl-names = "default";
180
181 status = "okay";
182};
183
184&scif_clk {
185 clock-frequency = <14745600>;
186 status = "okay";
187};
188
189&i2c2 {
190 pinctrl-0 = <&i2c2_pins>;
191 pinctrl-names = "default";
192
193 status = "okay";
194
195 clock-frequency = <100000>;
196
197 ak4613: codec@10 {
198 compatible = "asahi-kasei,ak4613";
199 #sound-dai-cells = <0>;
200 reg = <0x10>;
201 clocks = <&rcar_sound 3>;
202
203 asahi-kasei,in1-single-end;
204 asahi-kasei,in2-single-end;
205 asahi-kasei,out1-single-end;
206 asahi-kasei,out2-single-end;
207 asahi-kasei,out3-single-end;
208 asahi-kasei,out4-single-end;
209 asahi-kasei,out5-single-end;
210 asahi-kasei,out6-single-end;
211 };
212
213 cs2000: clk-multiplier@4f {
214 #clock-cells = <0>;
215 compatible = "cirrus,cs2000-cp";
216 reg = <0x4f>;
217 clocks = <&audio_clkout>, <&x12_clk>;
218 clock-names = "clk_in", "ref_clk";
219
220 assigned-clocks = <&cs2000>;
221 assigned-clock-rates = <24576000>; /* 1/1 divide */
222 };
223};
224
225&rcar_sound {
226 pinctrl-0 = <&sound_pins &sound_clk_pins>;
227 pinctrl-names = "default";
228
229 /* Single DAI */
230 #sound-dai-cells = <0>;
231
232 /* audio_clkout0/1/2/3 */
233 #clock-cells = <1>;
234 clock-frequency = <11289600>;
235
236 status = "okay";
237
238 /* update <audio_clk_b> to <cs2000> */
239 clocks = <&cpg CPG_MOD 1005>,
240 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
241 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
242 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
243 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
244 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
245 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
246 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
247 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
248 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
249 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
250 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
251 <&audio_clk_a>, <&cs2000>,
252 <&audio_clk_c>,
253 <&cpg CPG_CORE R8A7795_CLK_S0D4>;
254
255 rcar_sound,dai {
256 dai0 {
257 playback = <&ssi0 &src0 &dvc0>;
258 capture = <&ssi1 &src1 &dvc1>;
259 };
260 };
261};
262
263&sdhi0 {
264 pinctrl-0 = <&sdhi0_pins_3v3>;
265 pinctrl-1 = <&sdhi0_pins_1v8>;
266 pinctrl-names = "default", "state_uhs";
267
268 vmmc-supply = <&vcc_sdhi0>;
269 vqmmc-supply = <&vccq_sdhi0>;
270 cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
271 bus-width = <4>;
272 sd-uhs-sdr50;
273 status = "okay";
274};
275
276&ssi1 {
277 shared-pin;
278};
279
280&wdt0 {
281 timeout-sec = <60>;
282 status = "okay";
283};
284
285&audio_clk_a {
286 clock-frequency = <22579200>;
287};
288
289&avb {
290 pinctrl-0 = <&avb_pins>;
291 pinctrl-names = "default";
292 renesas,no-ether-link;
293 phy-handle = <&phy0>;
294 status = "okay";
295
296 phy0: ethernet-phy@0 {
297 rxc-skew-ps = <900>;
298 rxdv-skew-ps = <0>;
299 rxd0-skew-ps = <0>;
300 rxd1-skew-ps = <0>;
301 rxd2-skew-ps = <0>;
302 rxd3-skew-ps = <0>;
303 txc-skew-ps = <900>;
304 txen-skew-ps = <0>;
305 txd0-skew-ps = <0>;
306 txd1-skew-ps = <0>;
307 txd2-skew-ps = <0>;
308 txd3-skew-ps = <0>;
309 reg = <0>;
310 interrupt-parent = <&gpio2>;
311 interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
312 };
313};
314
315&usb2_phy1 {
316 pinctrl-0 = <&usb1_pins>;
317 pinctrl-names = "default";
318
319 status = "okay";
320};
321
322&ehci1 {
323 status = "okay";
324};
325
326&ohci1 {
327 status = "okay";
328};
diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
index 98f02631a0f0..b1eab6876f8c 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
@@ -110,6 +110,17 @@
110 1800000 0>; 110 1800000 0>;
111 }; 111 };
112 112
113 vbus0_usb2: regulator-vbus0-usb2 {
114 compatible = "regulator-fixed";
115
116 regulator-name = "USB20_VBUS0";
117 regulator-min-microvolt = <5000000>;
118 regulator-max-microvolt = <5000000>;
119
120 gpio = <&gpio6 16 GPIO_ACTIVE_HIGH>;
121 enable-active-high;
122 };
123
113 audio_clkout: audio_clkout { 124 audio_clkout: audio_clkout {
114 /* 125 /*
115 * This is same as <&rcar_sound 0> 126 * This is same as <&rcar_sound 0>
@@ -135,6 +146,52 @@
135 sound-dai = <&ak4613>; 146 sound-dai = <&ak4613>;
136 }; 147 };
137 }; 148 };
149
150 vga-encoder {
151 compatible = "adi,adv7123";
152
153 ports {
154 #address-cells = <1>;
155 #size-cells = <0>;
156
157 port@0 {
158 reg = <0>;
159 adv7123_in: endpoint {
160 remote-endpoint = <&du_out_rgb>;
161 };
162 };
163 port@1 {
164 reg = <1>;
165 adv7123_out: endpoint {
166 remote-endpoint = <&vga_in>;
167 };
168 };
169 };
170 };
171
172 vga {
173 compatible = "vga-connector";
174
175 port {
176 vga_in: endpoint {
177 remote-endpoint = <&adv7123_out>;
178 };
179 };
180 };
181};
182
183&du {
184 pinctrl-0 = <&du_pins>;
185 pinctrl-names = "default";
186 status = "okay";
187
188 ports {
189 port@0 {
190 endpoint {
191 remote-endpoint = <&adv7123_in>;
192 };
193 };
194 };
138}; 195};
139 196
140&extal_clk { 197&extal_clk {
@@ -172,6 +229,11 @@
172 function = "avb"; 229 function = "avb";
173 }; 230 };
174 231
232 du_pins: du {
233 groups = "du_rgb888", "du_sync", "du_oddf", "du_clk_out_0";
234 function = "du";
235 };
236
175 sdhi0_pins: sd0 { 237 sdhi0_pins: sd0 {
176 groups = "sdhi0_data4", "sdhi0_ctrl"; 238 groups = "sdhi0_data4", "sdhi0_ctrl";
177 function = "sdhi0"; 239 function = "sdhi0";
@@ -193,6 +255,11 @@
193 function = "audio_clk"; 255 function = "audio_clk";
194 }; 256 };
195 257
258 usb0_pins: usb0 {
259 groups = "usb0";
260 function = "usb0";
261 };
262
196 usb1_pins: usb1 { 263 usb1_pins: usb1 {
197 groups = "usb1"; 264 groups = "usb1";
198 function = "usb1"; 265 function = "usb1";
@@ -369,6 +436,14 @@
369 status = "okay"; 436 status = "okay";
370}; 437};
371 438
439&usb2_phy0 {
440 pinctrl-0 = <&usb0_pins>;
441 pinctrl-names = "default";
442
443 vbus-supply = <&vbus0_usb2>;
444 status = "okay";
445};
446
372&usb2_phy1 { 447&usb2_phy1 {
373 pinctrl-0 = <&usb1_pins>; 448 pinctrl-0 = <&usb1_pins>;
374 pinctrl-names = "default"; 449 pinctrl-names = "default";
@@ -383,6 +458,10 @@
383 status = "okay"; 458 status = "okay";
384}; 459};
385 460
461&ehci0 {
462 status = "okay";
463};
464
386&ehci1 { 465&ehci1 {
387 status = "okay"; 466 status = "okay";
388}; 467};
@@ -391,6 +470,10 @@
391 status = "okay"; 470 status = "okay";
392}; 471};
393 472
473&ohci0 {
474 status = "okay";
475};
476
394&ohci1 { 477&ohci1 {
395 status = "okay"; 478 status = "okay";
396}; 479};
@@ -399,6 +482,10 @@
399 status = "okay"; 482 status = "okay";
400}; 483};
401 484
485&hsusb {
486 status = "okay";
487};
488
402&pcie_bus_clk { 489&pcie_bus_clk {
403 clock-frequency = <100000000>; 490 clock-frequency = <100000000>;
404 status = "okay"; 491 status = "okay";
diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index b902356873c2..8c15040f2540 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -328,7 +328,8 @@
328 }; 328 };
329 329
330 audma0: dma-controller@ec700000 { 330 audma0: dma-controller@ec700000 {
331 compatible = "renesas,rcar-dmac"; 331 compatible = "renesas,dmac-r8a7795",
332 "renesas,rcar-dmac";
332 reg = <0 0xec700000 0 0x10000>; 333 reg = <0 0xec700000 0 0x10000>;
333 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH 334 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH
334 GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 335 GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
@@ -360,7 +361,8 @@
360 }; 361 };
361 362
362 audma1: dma-controller@ec720000 { 363 audma1: dma-controller@ec720000 {
363 compatible = "renesas,rcar-dmac"; 364 compatible = "renesas,dmac-r8a7795",
365 "renesas,rcar-dmac";
364 reg = <0 0xec720000 0 0x10000>; 366 reg = <0 0xec720000 0 0x10000>;
365 interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH 367 interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH
366 GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH 368 GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
@@ -1098,6 +1100,7 @@
1098 reg = <0 0xee100000 0 0x2000>; 1100 reg = <0 0xee100000 0 0x2000>;
1099 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 1101 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
1100 clocks = <&cpg CPG_MOD 314>; 1102 clocks = <&cpg CPG_MOD 314>;
1103 max-frequency = <200000000>;
1101 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1104 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1102 status = "disabled"; 1105 status = "disabled";
1103 }; 1106 };
@@ -1107,6 +1110,7 @@
1107 reg = <0 0xee120000 0 0x2000>; 1110 reg = <0 0xee120000 0 0x2000>;
1108 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1111 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
1109 clocks = <&cpg CPG_MOD 313>; 1112 clocks = <&cpg CPG_MOD 313>;
1113 max-frequency = <200000000>;
1110 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1114 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1111 status = "disabled"; 1115 status = "disabled";
1112 }; 1116 };
@@ -1116,8 +1120,8 @@
1116 reg = <0 0xee140000 0 0x2000>; 1120 reg = <0 0xee140000 0 0x2000>;
1117 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 1121 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
1118 clocks = <&cpg CPG_MOD 312>; 1122 clocks = <&cpg CPG_MOD 312>;
1123 max-frequency = <200000000>;
1119 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1124 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1120 cap-mmc-highspeed;
1121 status = "disabled"; 1125 status = "disabled";
1122 }; 1126 };
1123 1127
@@ -1126,8 +1130,8 @@
1126 reg = <0 0xee160000 0 0x2000>; 1130 reg = <0 0xee160000 0 0x2000>;
1127 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 1131 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
1128 clocks = <&cpg CPG_MOD 311>; 1132 clocks = <&cpg CPG_MOD 311>;
1133 max-frequency = <200000000>;
1129 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1134 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1130 cap-mmc-highspeed;
1131 status = "disabled"; 1135 status = "disabled";
1132 }; 1136 };
1133 1137
@@ -1224,6 +1228,23 @@
1224 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1228 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1225 status = "disabled"; 1229 status = "disabled";
1226 }; 1230 };
1231
1232 hsusb: usb@e6590000 {
1233 compatible = "renesas,usbhs-r8a7795",
1234 "renesas,rcar-gen3-usbhs";
1235 reg = <0 0xe6590000 0 0x100>;
1236 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1237 clocks = <&cpg CPG_MOD 704>;
1238 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
1239 <&usb_dmac1 0>, <&usb_dmac1 1>;
1240 dma-names = "ch0", "ch1", "ch2", "ch3";
1241 renesas,buswait = <11>;
1242 phys = <&usb2_phy0>;
1243 phy-names = "usb";
1244 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1245 status = "disabled";
1246 };
1247
1227 pciec0: pcie@fe000000 { 1248 pciec0: pcie@fe000000 {
1228 compatible = "renesas,pcie-r8a7795"; 1249 compatible = "renesas,pcie-r8a7795";
1229 reg = <0 0xfe000000 0 0x80000>; 1250 reg = <0 0xfe000000 0 0x80000>;
@@ -1273,5 +1294,252 @@
1273 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1294 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1274 status = "disabled"; 1295 status = "disabled";
1275 }; 1296 };
1297
1298 vspbc: vsp@fe920000 {
1299 compatible = "renesas,vsp2";
1300 reg = <0 0xfe920000 0 0x8000>;
1301 interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;
1302 clocks = <&cpg CPG_MOD 624>;
1303 power-domains = <&sysc R8A7795_PD_A3VP>;
1304
1305 renesas,fcp = <&fcpvb1>;
1306 };
1307
1308 fcpvb1: fcp@fe92f000 {
1309 compatible = "renesas,r8a7795-fcpv", "renesas,fcpv";
1310 reg = <0 0xfe92f000 0 0x200>;
1311 clocks = <&cpg CPG_MOD 606>;
1312 power-domains = <&sysc R8A7795_PD_A3VP>;
1313 };
1314
1315 fcpf0: fcp@fe950000 {
1316 compatible = "renesas,r8a7795-fcpf", "renesas,fcpf";
1317 reg = <0 0xfe950000 0 0x200>;
1318 clocks = <&cpg CPG_MOD 615>;
1319 power-domains = <&sysc R8A7795_PD_A3VP>;
1320 };
1321
1322 fcpf1: fcp@fe951000 {
1323 compatible = "renesas,r8a7795-fcpf", "renesas,fcpf";
1324 reg = <0 0xfe951000 0 0x200>;
1325 clocks = <&cpg CPG_MOD 614>;
1326 power-domains = <&sysc R8A7795_PD_A3VP>;
1327 };
1328
1329 fcpf2: fcp@fe952000 {
1330 compatible = "renesas,r8a7795-fcpf", "renesas,fcpf";
1331 reg = <0 0xfe952000 0 0x200>;
1332 clocks = <&cpg CPG_MOD 613>;
1333 power-domains = <&sysc R8A7795_PD_A3VP>;
1334 };
1335
1336 vspbd: vsp@fe960000 {
1337 compatible = "renesas,vsp2";
1338 reg = <0 0xfe960000 0 0x8000>;
1339 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
1340 clocks = <&cpg CPG_MOD 626>;
1341 power-domains = <&sysc R8A7795_PD_A3VP>;
1342
1343 renesas,fcp = <&fcpvb0>;
1344 };
1345
1346 fcpvb0: fcp@fe96f000 {
1347 compatible = "renesas,r8a7795-fcpv", "renesas,fcpv";
1348 reg = <0 0xfe96f000 0 0x200>;
1349 clocks = <&cpg CPG_MOD 607>;
1350 power-domains = <&sysc R8A7795_PD_A3VP>;
1351 };
1352
1353 vspi0: vsp@fe9a0000 {
1354 compatible = "renesas,vsp2";
1355 reg = <0 0xfe9a0000 0 0x8000>;
1356 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
1357 clocks = <&cpg CPG_MOD 631>;
1358 power-domains = <&sysc R8A7795_PD_A3VP>;
1359
1360 renesas,fcp = <&fcpvi0>;
1361 };
1362
1363 fcpvi0: fcp@fe9af000 {
1364 compatible = "renesas,r8a7795-fcpv", "renesas,fcpv";
1365 reg = <0 0xfe9af000 0 0x200>;
1366 clocks = <&cpg CPG_MOD 611>;
1367 power-domains = <&sysc R8A7795_PD_A3VP>;
1368 };
1369
1370 vspi1: vsp@fe9b0000 {
1371 compatible = "renesas,vsp2";
1372 reg = <0 0xfe9b0000 0 0x8000>;
1373 interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
1374 clocks = <&cpg CPG_MOD 630>;
1375 power-domains = <&sysc R8A7795_PD_A3VP>;
1376
1377 renesas,fcp = <&fcpvi1>;
1378 };
1379
1380 fcpvi1: fcp@fe9bf000 {
1381 compatible = "renesas,r8a7795-fcpv", "renesas,fcpv";
1382 reg = <0 0xfe9bf000 0 0x200>;
1383 clocks = <&cpg CPG_MOD 610>;
1384 power-domains = <&sysc R8A7795_PD_A3VP>;
1385 };
1386
1387 vspi2: vsp@fe9c0000 {
1388 compatible = "renesas,vsp2";
1389 reg = <0 0xfe9c0000 0 0x8000>;
1390 interrupts = <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>;
1391 clocks = <&cpg CPG_MOD 629>;
1392 power-domains = <&sysc R8A7795_PD_A3VP>;
1393
1394 renesas,fcp = <&fcpvi2>;
1395 };
1396
1397 fcpvi2: fcp@fe9cf000 {
1398 compatible = "renesas,r8a7795-fcpv", "renesas,fcpv";
1399 reg = <0 0xfe9cf000 0 0x200>;
1400 clocks = <&cpg CPG_MOD 609>;
1401 power-domains = <&sysc R8A7795_PD_A3VP>;
1402 };
1403
1404 vspd0: vsp@fea20000 {
1405 compatible = "renesas,vsp2";
1406 reg = <0 0xfea20000 0 0x4000>;
1407 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
1408 clocks = <&cpg CPG_MOD 623>;
1409 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1410
1411 renesas,fcp = <&fcpvd0>;
1412 };
1413
1414 fcpvd0: fcp@fea27000 {
1415 compatible = "renesas,r8a7795-fcpv", "renesas,fcpv";
1416 reg = <0 0xfea27000 0 0x200>;
1417 clocks = <&cpg CPG_MOD 603>;
1418 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1419 };
1420
1421 vspd1: vsp@fea28000 {
1422 compatible = "renesas,vsp2";
1423 reg = <0 0xfea28000 0 0x4000>;
1424 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
1425 clocks = <&cpg CPG_MOD 622>;
1426 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1427
1428 renesas,fcp = <&fcpvd1>;
1429 };
1430
1431 fcpvd1: fcp@fea2f000 {
1432 compatible = "renesas,r8a7795-fcpv", "renesas,fcpv";
1433 reg = <0 0xfea2f000 0 0x200>;
1434 clocks = <&cpg CPG_MOD 602>;
1435 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1436 };
1437
1438 vspd2: vsp@fea30000 {
1439 compatible = "renesas,vsp2";
1440 reg = <0 0xfea30000 0 0x4000>;
1441 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;
1442 clocks = <&cpg CPG_MOD 621>;
1443 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1444
1445 renesas,fcp = <&fcpvd2>;
1446 };
1447
1448 fcpvd2: fcp@fea37000 {
1449 compatible = "renesas,r8a7795-fcpv", "renesas,fcpv";
1450 reg = <0 0xfea37000 0 0x200>;
1451 clocks = <&cpg CPG_MOD 601>;
1452 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1453 };
1454
1455 vspd3: vsp@fea38000 {
1456 compatible = "renesas,vsp2";
1457 reg = <0 0xfea38000 0 0x4000>;
1458 interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
1459 clocks = <&cpg CPG_MOD 620>;
1460 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1461
1462 renesas,fcp = <&fcpvd3>;
1463 };
1464
1465 fcpvd3: fcp@fea3f000 {
1466 compatible = "renesas,r8a7795-fcpv", "renesas,fcpv";
1467 reg = <0 0xfea3f000 0 0x200>;
1468 clocks = <&cpg CPG_MOD 600>;
1469 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1470 };
1471
1472 fdp1@fe940000 {
1473 compatible = "renesas,fdp1";
1474 reg = <0 0xfe940000 0 0x2400>;
1475 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
1476 clocks = <&cpg CPG_MOD 119>;
1477 power-domains = <&sysc R8A7795_PD_A3VP>;
1478 renesas,fcp = <&fcpf0>;
1479 };
1480
1481 fdp1@fe944000 {
1482 compatible = "renesas,fdp1";
1483 reg = <0 0xfe944000 0 0x2400>;
1484 interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
1485 clocks = <&cpg CPG_MOD 118>;
1486 power-domains = <&sysc R8A7795_PD_A3VP>;
1487 renesas,fcp = <&fcpf1>;
1488 };
1489
1490 fdp1@fe948000 {
1491 compatible = "renesas,fdp1";
1492 reg = <0 0xfe948000 0 0x2400>;
1493 interrupts = <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
1494 clocks = <&cpg CPG_MOD 117>;
1495 power-domains = <&sysc R8A7795_PD_A3VP>;
1496 renesas,fcp = <&fcpf2>;
1497 };
1498
1499 du: display@feb00000 {
1500 compatible = "renesas,du-r8a7795";
1501 reg = <0 0xfeb00000 0 0x80000>,
1502 <0 0xfeb90000 0 0x14>;
1503 reg-names = "du", "lvds.0";
1504 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
1505 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
1506 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
1507 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
1508 clocks = <&cpg CPG_MOD 724>,
1509 <&cpg CPG_MOD 723>,
1510 <&cpg CPG_MOD 722>,
1511 <&cpg CPG_MOD 721>,
1512 <&cpg CPG_MOD 727>;
1513 clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0";
1514 status = "disabled";
1515
1516 vsps = <&vspd0 &vspd1 &vspd2 &vspd3>;
1517
1518 ports {
1519 #address-cells = <1>;
1520 #size-cells = <0>;
1521
1522 port@0 {
1523 reg = <0>;
1524 du_out_rgb: endpoint {
1525 };
1526 };
1527 port@1 {
1528 reg = <1>;
1529 du_out_hdmi0: endpoint {
1530 };
1531 };
1532 port@2 {
1533 reg = <2>;
1534 du_out_hdmi1: endpoint {
1535 };
1536 };
1537 port@3 {
1538 reg = <3>;
1539 du_out_lvds0: endpoint {
1540 };
1541 };
1542 };
1543 };
1276 }; 1544 };
1277}; 1545};
diff --git a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts
index e72be3856d79..13db7d61c26c 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts
@@ -31,11 +31,27 @@
31 }; 31 };
32}; 32};
33 33
34&pfc {
35 pinctrl-0 = <&scif_clk_pins>;
36 pinctrl-names = "default";
37
38 scif2_pins: scif2 {
39 groups = "scif2_data_a";
40 function = "scif2";
41 };
42 scif_clk_pins: scif_clk {
43 groups = "scif_clk_a";
44 function = "scif_clk";
45 };
46};
47
34&extal_clk { 48&extal_clk {
35 clock-frequency = <16666666>; 49 clock-frequency = <16666666>;
36}; 50};
37 51
38&scif2 { 52&scif2 {
53 pinctrl-0 = <&scif2_pins>;
54 pinctrl-names = "default";
39 status = "okay"; 55 status = "okay";
40}; 56};
41 57
diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
index 1edf82440d78..9217da983525 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
@@ -107,6 +107,123 @@
107 status = "disabled"; 107 status = "disabled";
108 }; 108 };
109 109
110 gpio0: gpio@e6050000 {
111 compatible = "renesas,gpio-r8a7796",
112 "renesas,gpio-rcar";
113 reg = <0 0xe6050000 0 0x50>;
114 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
115 #gpio-cells = <2>;
116 gpio-controller;
117 gpio-ranges = <&pfc 0 0 16>;
118 #interrupt-cells = <2>;
119 interrupt-controller;
120 clocks = <&cpg CPG_MOD 912>;
121 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
122 };
123
124 gpio1: gpio@e6051000 {
125 compatible = "renesas,gpio-r8a7796",
126 "renesas,gpio-rcar";
127 reg = <0 0xe6051000 0 0x50>;
128 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
129 #gpio-cells = <2>;
130 gpio-controller;
131 gpio-ranges = <&pfc 0 32 29>;
132 #interrupt-cells = <2>;
133 interrupt-controller;
134 clocks = <&cpg CPG_MOD 911>;
135 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
136 };
137
138 gpio2: gpio@e6052000 {
139 compatible = "renesas,gpio-r8a7796",
140 "renesas,gpio-rcar";
141 reg = <0 0xe6052000 0 0x50>;
142 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
143 #gpio-cells = <2>;
144 gpio-controller;
145 gpio-ranges = <&pfc 0 64 15>;
146 #interrupt-cells = <2>;
147 interrupt-controller;
148 clocks = <&cpg CPG_MOD 910>;
149 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
150 };
151
152 gpio3: gpio@e6053000 {
153 compatible = "renesas,gpio-r8a7796",
154 "renesas,gpio-rcar";
155 reg = <0 0xe6053000 0 0x50>;
156 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
157 #gpio-cells = <2>;
158 gpio-controller;
159 gpio-ranges = <&pfc 0 96 16>;
160 #interrupt-cells = <2>;
161 interrupt-controller;
162 clocks = <&cpg CPG_MOD 909>;
163 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
164 };
165
166 gpio4: gpio@e6054000 {
167 compatible = "renesas,gpio-r8a7796",
168 "renesas,gpio-rcar";
169 reg = <0 0xe6054000 0 0x50>;
170 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
171 #gpio-cells = <2>;
172 gpio-controller;
173 gpio-ranges = <&pfc 0 128 18>;
174 #interrupt-cells = <2>;
175 interrupt-controller;
176 clocks = <&cpg CPG_MOD 908>;
177 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
178 };
179
180 gpio5: gpio@e6055000 {
181 compatible = "renesas,gpio-r8a7796",
182 "renesas,gpio-rcar";
183 reg = <0 0xe6055000 0 0x50>;
184 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
185 #gpio-cells = <2>;
186 gpio-controller;
187 gpio-ranges = <&pfc 0 160 26>;
188 #interrupt-cells = <2>;
189 interrupt-controller;
190 clocks = <&cpg CPG_MOD 907>;
191 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
192 };
193
194 gpio6: gpio@e6055400 {
195 compatible = "renesas,gpio-r8a7796",
196 "renesas,gpio-rcar";
197 reg = <0 0xe6055400 0 0x50>;
198 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
199 #gpio-cells = <2>;
200 gpio-controller;
201 gpio-ranges = <&pfc 0 192 32>;
202 #interrupt-cells = <2>;
203 interrupt-controller;
204 clocks = <&cpg CPG_MOD 906>;
205 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
206 };
207
208 gpio7: gpio@e6055800 {
209 compatible = "renesas,gpio-r8a7796",
210 "renesas,gpio-rcar";
211 reg = <0 0xe6055800 0 0x50>;
212 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
213 #gpio-cells = <2>;
214 gpio-controller;
215 gpio-ranges = <&pfc 0 224 4>;
216 #interrupt-cells = <2>;
217 interrupt-controller;
218 clocks = <&cpg CPG_MOD 905>;
219 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
220 };
221
222 pfc: pin-controller@e6060000 {
223 compatible = "renesas,pfc-r8a7796";
224 reg = <0 0xe6060000 0 0x50c>;
225 };
226
110 cpg: clock-controller@e6150000 { 227 cpg: clock-controller@e6150000 {
111 compatible = "renesas,r8a7796-cpg-mssr"; 228 compatible = "renesas,r8a7796-cpg-mssr";
112 reg = <0 0xe6150000 0 0x1000>; 229 reg = <0 0xe6150000 0 0x1000>;
diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig
index 415dd8023063..07eca54bdc1c 100644
--- a/drivers/pinctrl/sh-pfc/Kconfig
+++ b/drivers/pinctrl/sh-pfc/Kconfig
@@ -54,6 +54,11 @@ config PINCTRL_PFC_R8A7791
54 depends on ARCH_R8A7791 54 depends on ARCH_R8A7791
55 select PINCTRL_SH_PFC 55 select PINCTRL_SH_PFC
56 56
57config PINCTRL_PFC_R8A7792
58 def_bool y
59 depends on ARCH_R8A7792
60 select PINCTRL_SH_PFC
61
57config PINCTRL_PFC_R8A7793 62config PINCTRL_PFC_R8A7793
58 def_bool y 63 def_bool y
59 depends on ARCH_R8A7793 64 depends on ARCH_R8A7793
@@ -69,6 +74,11 @@ config PINCTRL_PFC_R8A7795
69 depends on ARCH_R8A7795 74 depends on ARCH_R8A7795
70 select PINCTRL_SH_PFC 75 select PINCTRL_SH_PFC
71 76
77config PINCTRL_PFC_R8A7796
78 def_bool y
79 depends on ARCH_R8A7796
80 select PINCTRL_SH_PFC
81
72config PINCTRL_PFC_SH7203 82config PINCTRL_PFC_SH7203
73 def_bool y 83 def_bool y
74 depends on CPU_SUBTYPE_SH7203 84 depends on CPU_SUBTYPE_SH7203
diff --git a/drivers/pinctrl/sh-pfc/Makefile b/drivers/pinctrl/sh-pfc/Makefile
index 8a2c8710fc93..2dda8c63f3cf 100644
--- a/drivers/pinctrl/sh-pfc/Makefile
+++ b/drivers/pinctrl/sh-pfc/Makefile
@@ -7,9 +7,11 @@ obj-$(CONFIG_PINCTRL_PFC_R8A7778) += pfc-r8a7778.o
7obj-$(CONFIG_PINCTRL_PFC_R8A7779) += pfc-r8a7779.o 7obj-$(CONFIG_PINCTRL_PFC_R8A7779) += pfc-r8a7779.o
8obj-$(CONFIG_PINCTRL_PFC_R8A7790) += pfc-r8a7790.o 8obj-$(CONFIG_PINCTRL_PFC_R8A7790) += pfc-r8a7790.o
9obj-$(CONFIG_PINCTRL_PFC_R8A7791) += pfc-r8a7791.o 9obj-$(CONFIG_PINCTRL_PFC_R8A7791) += pfc-r8a7791.o
10obj-$(CONFIG_PINCTRL_PFC_R8A7792) += pfc-r8a7792.o
10obj-$(CONFIG_PINCTRL_PFC_R8A7793) += pfc-r8a7791.o 11obj-$(CONFIG_PINCTRL_PFC_R8A7793) += pfc-r8a7791.o
11obj-$(CONFIG_PINCTRL_PFC_R8A7794) += pfc-r8a7794.o 12obj-$(CONFIG_PINCTRL_PFC_R8A7794) += pfc-r8a7794.o
12obj-$(CONFIG_PINCTRL_PFC_R8A7795) += pfc-r8a7795.o 13obj-$(CONFIG_PINCTRL_PFC_R8A7795) += pfc-r8a7795.o
14obj-$(CONFIG_PINCTRL_PFC_R8A7796) += pfc-r8a7796.o
13obj-$(CONFIG_PINCTRL_PFC_SH7203) += pfc-sh7203.o 15obj-$(CONFIG_PINCTRL_PFC_SH7203) += pfc-sh7203.o
14obj-$(CONFIG_PINCTRL_PFC_SH7264) += pfc-sh7264.o 16obj-$(CONFIG_PINCTRL_PFC_SH7264) += pfc-sh7264.o
15obj-$(CONFIG_PINCTRL_PFC_SH7269) += pfc-sh7269.o 17obj-$(CONFIG_PINCTRL_PFC_SH7269) += pfc-sh7269.o
diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
index a3b82041b6a2..f3a8897d4e8f 100644
--- a/drivers/pinctrl/sh-pfc/core.c
+++ b/drivers/pinctrl/sh-pfc/core.c
@@ -494,6 +494,12 @@ static const struct of_device_id sh_pfc_of_table[] = {
494 .data = &r8a7791_pinmux_info, 494 .data = &r8a7791_pinmux_info,
495 }, 495 },
496#endif 496#endif
497#ifdef CONFIG_PINCTRL_PFC_R8A7792
498 {
499 .compatible = "renesas,pfc-r8a7792",
500 .data = &r8a7792_pinmux_info,
501 },
502#endif
497#ifdef CONFIG_PINCTRL_PFC_R8A7793 503#ifdef CONFIG_PINCTRL_PFC_R8A7793
498 { 504 {
499 .compatible = "renesas,pfc-r8a7793", 505 .compatible = "renesas,pfc-r8a7793",
@@ -512,6 +518,12 @@ static const struct of_device_id sh_pfc_of_table[] = {
512 .data = &r8a7795_pinmux_info, 518 .data = &r8a7795_pinmux_info,
513 }, 519 },
514#endif 520#endif
521#ifdef CONFIG_PINCTRL_PFC_R8A7796
522 {
523 .compatible = "renesas,pfc-r8a7796",
524 .data = &r8a7796_pinmux_info,
525 },
526#endif
515#ifdef CONFIG_PINCTRL_PFC_SH73A0 527#ifdef CONFIG_PINCTRL_PFC_SH73A0
516 { 528 {
517 .compatible = "renesas,pfc-sh73a0", 529 .compatible = "renesas,pfc-sh73a0",
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7792.c b/drivers/pinctrl/sh-pfc/pfc-r8a7792.c
new file mode 100644
index 000000000000..92c670992b3d
--- /dev/null
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7792.c
@@ -0,0 +1,2624 @@
1/*
2 * r8a7792 processor support - PFC hardware block.
3 *
4 * Copyright (C) 2013-2014 Renesas Electronics Corporation
5 * Copyright (C) 2016 Cogent Embedded, Inc., <source@cogentembedded.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2
9 * as published by the Free Software Foundation.
10 */
11
12#include <linux/kernel.h>
13
14#include "core.h"
15#include "sh_pfc.h"
16
17#define CPU_ALL_PORT(fn, sfx) \
18 PORT_GP_29(0, fn, sfx), \
19 PORT_GP_23(1, fn, sfx), \
20 PORT_GP_32(2, fn, sfx), \
21 PORT_GP_28(3, fn, sfx), \
22 PORT_GP_17(4, fn, sfx), \
23 PORT_GP_17(5, fn, sfx), \
24 PORT_GP_17(6, fn, sfx), \
25 PORT_GP_17(7, fn, sfx), \
26 PORT_GP_17(8, fn, sfx), \
27 PORT_GP_17(9, fn, sfx), \
28 PORT_GP_32(10, fn, sfx), \
29 PORT_GP_30(11, fn, sfx)
30
31enum {
32 PINMUX_RESERVED = 0,
33
34 PINMUX_DATA_BEGIN,
35 GP_ALL(DATA),
36 PINMUX_DATA_END,
37
38 PINMUX_FUNCTION_BEGIN,
39 GP_ALL(FN),
40
41 /* GPSR0 */
42 FN_IP0_0, FN_IP0_1, FN_IP0_2, FN_IP0_3, FN_IP0_4, FN_IP0_5,
43 FN_IP0_6, FN_IP0_7, FN_IP0_8, FN_IP0_9, FN_IP0_10, FN_IP0_11,
44 FN_IP0_12, FN_IP0_13, FN_IP0_14, FN_IP0_15, FN_IP0_16,
45 FN_IP0_17, FN_IP0_18, FN_IP0_19, FN_IP0_20, FN_IP0_21,
46 FN_IP0_22, FN_IP0_23, FN_IP1_0, FN_IP1_1, FN_IP1_2,
47 FN_IP1_3, FN_IP1_4,
48
49 /* GPSR1 */
50 FN_IP1_5, FN_IP1_6, FN_IP1_7, FN_IP1_8, FN_IP1_9, FN_IP1_10,
51 FN_IP1_11, FN_IP1_12, FN_IP1_13, FN_IP1_14, FN_IP1_15, FN_IP1_16,
52 FN_DU1_DB2_C0_DATA12, FN_DU1_DB3_C1_DATA13, FN_DU1_DB4_C2_DATA14,
53 FN_DU1_DB5_C3_DATA15, FN_DU1_DB6_C4, FN_DU1_DB7_C5,
54 FN_DU1_EXHSYNC_DU1_HSYNC, FN_DU1_EXVSYNC_DU1_VSYNC,
55 FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_DU1_DISP, FN_DU1_CDE,
56
57 /* GPSR2 */
58 FN_D0, FN_D1, FN_D2, FN_D3, FN_D4, FN_D5, FN_D6, FN_D7,
59 FN_D8, FN_D9, FN_D10, FN_D11, FN_D12, FN_D13, FN_D14, FN_D15,
60 FN_A0, FN_A1, FN_A2, FN_A3, FN_A4, FN_A5, FN_A6, FN_A7,
61 FN_A8, FN_A9, FN_A10, FN_A11, FN_A12, FN_A13, FN_A14, FN_A15,
62
63 /* GPSR3 */
64 FN_A16, FN_A17, FN_A18, FN_A19, FN_IP1_17, FN_IP1_18,
65 FN_CS1_N_A26, FN_EX_CS0_N, FN_EX_CS1_N, FN_EX_CS2_N, FN_EX_CS3_N,
66 FN_EX_CS4_N, FN_EX_CS5_N, FN_BS_N, FN_RD_N, FN_RD_WR_N,
67 FN_WE0_N, FN_WE1_N, FN_EX_WAIT0, FN_IRQ0, FN_IRQ1, FN_IRQ2, FN_IRQ3,
68 FN_IP1_19, FN_IP1_20, FN_IP1_21, FN_IP1_22, FN_CS0_N,
69
70 /* GPSR4 */
71 FN_VI0_CLK, FN_VI0_CLKENB, FN_VI0_HSYNC_N, FN_VI0_VSYNC_N,
72 FN_VI0_D0_B0_C0, FN_VI0_D1_B1_C1, FN_VI0_D2_B2_C2, FN_VI0_D3_B3_C3,
73 FN_VI0_D4_B4_C4, FN_VI0_D5_B5_C5, FN_VI0_D6_B6_C6, FN_VI0_D7_B7_C7,
74 FN_VI0_D8_G0_Y0, FN_VI0_D9_G1_Y1, FN_VI0_D10_G2_Y2, FN_VI0_D11_G3_Y3,
75 FN_VI0_FIELD,
76
77 /* GPSR5 */
78 FN_VI1_CLK, FN_VI1_CLKENB, FN_VI1_HSYNC_N, FN_VI1_VSYNC_N,
79 FN_VI1_D0_B0_C0, FN_VI1_D1_B1_C1, FN_VI1_D2_B2_C2, FN_VI1_D3_B3_C3,
80 FN_VI1_D4_B4_C4, FN_VI1_D5_B5_C5, FN_VI1_D6_B6_C6, FN_VI1_D7_B7_C7,
81 FN_VI1_D8_G0_Y0, FN_VI1_D9_G1_Y1, FN_VI1_D10_G2_Y2, FN_VI1_D11_G3_Y3,
82 FN_VI1_FIELD,
83
84 /* GPSR6 */
85 FN_IP2_0, FN_IP2_1, FN_IP2_2, FN_IP2_3, FN_IP2_4, FN_IP2_5, FN_IP2_6,
86 FN_IP2_7, FN_IP2_8, FN_IP2_9, FN_IP2_10, FN_IP2_11, FN_IP2_12,
87 FN_IP2_13, FN_IP2_14, FN_IP2_15, FN_IP2_16,
88
89 /* GPSR7 */
90 FN_IP3_0, FN_IP3_1, FN_IP3_2, FN_IP3_3, FN_IP3_4, FN_IP3_5, FN_IP3_6,
91 FN_IP3_7, FN_IP3_8, FN_IP3_9, FN_IP3_10, FN_IP3_11, FN_IP3_12,
92 FN_IP3_13, FN_VI3_D10_Y2, FN_IP3_14, FN_VI3_FIELD,
93
94 /* GPSR8 */
95 FN_VI4_CLK, FN_IP4_0, FN_IP4_1, FN_IP4_3_2, FN_IP4_4, FN_IP4_6_5,
96 FN_IP4_8_7, FN_IP4_10_9, FN_IP4_12_11, FN_IP4_14_13, FN_IP4_16_15,
97 FN_IP4_18_17, FN_IP4_20_19, FN_IP4_21, FN_IP4_22, FN_IP4_23, FN_IP4_24,
98
99 /* GPSR9 */
100 FN_VI5_CLK, FN_IP5_0, FN_IP5_1, FN_IP5_2, FN_IP5_3, FN_IP5_4, FN_IP5_5,
101 FN_IP5_6, FN_IP5_7, FN_IP5_8, FN_IP5_9, FN_IP5_10, FN_IP5_11,
102 FN_VI5_D9_Y1, FN_VI5_D10_Y2, FN_VI5_D11_Y3, FN_VI5_FIELD,
103
104 /* GPSR10 */
105 FN_IP6_0, FN_IP6_1, FN_HRTS0_N, FN_IP6_2, FN_IP6_3, FN_IP6_4, FN_IP6_5,
106 FN_HCTS1_N, FN_IP6_6, FN_IP6_7, FN_SCK0, FN_CTS0_N, FN_RTS0_N,
107 FN_TX0, FN_RX0, FN_SCK1, FN_CTS1_N, FN_RTS1_N, FN_TX1, FN_RX1,
108 FN_IP6_9_8, FN_IP6_11_10, FN_IP6_13_12, FN_IP6_15_14, FN_IP6_16,
109 FN_IP6_18_17, FN_SCIF_CLK, FN_CAN0_TX, FN_CAN0_RX, FN_CAN_CLK,
110 FN_CAN1_TX, FN_CAN1_RX,
111
112 /* GPSR11 */
113 FN_IP7_1_0, FN_IP7_3_2, FN_IP7_5_4, FN_IP7_6, FN_IP7_7, FN_SD0_CLK,
114 FN_SD0_CMD, FN_SD0_DAT0, FN_SD0_DAT1, FN_SD0_DAT2, FN_SD0_DAT3,
115 FN_SD0_CD, FN_SD0_WP, FN_IP7_9_8, FN_IP7_11_10, FN_IP7_13_12,
116 FN_IP7_15_14, FN_IP7_16, FN_IP7_17, FN_IP7_18, FN_IP7_19, FN_IP7_20,
117 FN_ADICLK, FN_ADICS_SAMP, FN_ADIDATA, FN_ADICHS0, FN_ADICHS1,
118 FN_ADICHS2, FN_AVS1, FN_AVS2,
119
120 /* IPSR0 */
121 FN_DU0_DR0_DATA0, FN_DU0_DR1_DATA1, FN_DU0_DR2_Y4_DATA2,
122 FN_DU0_DR3_Y5_DATA3, FN_DU0_DR4_Y6_DATA4, FN_DU0_DR5_Y7_DATA5,
123 FN_DU0_DR6_Y8_DATA6, FN_DU0_DR7_Y9_DATA7, FN_DU0_DG0_DATA8,
124 FN_DU0_DG1_DATA9, FN_DU0_DG2_C6_DATA10, FN_DU0_DG3_C7_DATA11,
125 FN_DU0_DG4_Y0_DATA12, FN_DU0_DG5_Y1_DATA13, FN_DU0_DG6_Y2_DATA14,
126 FN_DU0_DG7_Y3_DATA15, FN_DU0_DB0, FN_DU0_DB1, FN_DU0_DB2_C0,
127 FN_DU0_DB3_C1, FN_DU0_DB4_C2, FN_DU0_DB5_C3, FN_DU0_DB6_C4,
128 FN_DU0_DB7_C5,
129
130 /* IPSR1 */
131 FN_DU0_EXHSYNC_DU0_HSYNC, FN_DU0_EXVSYNC_DU0_VSYNC,
132 FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_DU0_DISP, FN_DU0_CDE,
133 FN_DU1_DR2_Y4_DATA0, FN_DU1_DR3_Y5_DATA1, FN_DU1_DR4_Y6_DATA2,
134 FN_DU1_DR5_Y7_DATA3, FN_DU1_DR6_DATA4, FN_DU1_DR7_DATA5,
135 FN_DU1_DG2_C6_DATA6, FN_DU1_DG3_C7_DATA7, FN_DU1_DG4_Y0_DATA8,
136 FN_DU1_DG5_Y1_DATA9, FN_DU1_DG6_Y2_DATA10, FN_DU1_DG7_Y3_DATA11,
137 FN_A20, FN_MOSI_IO0, FN_A21, FN_MISO_IO1, FN_A22, FN_IO2,
138 FN_A23, FN_IO3, FN_A24, FN_SPCLK, FN_A25, FN_SSL,
139
140 /* IPSR2 */
141 FN_VI2_CLK, FN_AVB_RX_CLK, FN_VI2_CLKENB, FN_AVB_RX_DV,
142 FN_VI2_HSYNC_N, FN_AVB_RXD0, FN_VI2_VSYNC_N, FN_AVB_RXD1,
143 FN_VI2_D0_C0, FN_AVB_RXD2, FN_VI2_D1_C1, FN_AVB_RXD3,
144 FN_VI2_D2_C2, FN_AVB_RXD4, FN_VI2_D3_C3, FN_AVB_RXD5,
145 FN_VI2_D4_C4, FN_AVB_RXD6, FN_VI2_D5_C5, FN_AVB_RXD7,
146 FN_VI2_D6_C6, FN_AVB_RX_ER, FN_VI2_D7_C7, FN_AVB_COL,
147 FN_VI2_D8_Y0, FN_AVB_TXD3, FN_VI2_D9_Y1, FN_AVB_TX_EN,
148 FN_VI2_D10_Y2, FN_AVB_TXD0, FN_VI2_D11_Y3, FN_AVB_TXD1,
149 FN_VI2_FIELD, FN_AVB_TXD2,
150
151 /* IPSR3 */
152 FN_VI3_CLK, FN_AVB_TX_CLK, FN_VI3_CLKENB, FN_AVB_TXD4,
153 FN_VI3_HSYNC_N, FN_AVB_TXD5, FN_VI3_VSYNC_N, FN_AVB_TXD6,
154 FN_VI3_D0_C0, FN_AVB_TXD7, FN_VI3_D1_C1, FN_AVB_TX_ER,
155 FN_VI3_D2_C2, FN_AVB_GTX_CLK, FN_VI3_D3_C3, FN_AVB_MDC,
156 FN_VI3_D4_C4, FN_AVB_MDIO, FN_VI3_D5_C5, FN_AVB_LINK,
157 FN_VI3_D6_C6, FN_AVB_MAGIC, FN_VI3_D7_C7, FN_AVB_PHY_INT,
158 FN_VI3_D8_Y0, FN_AVB_CRS, FN_VI3_D9_Y1, FN_AVB_GTXREFCLK,
159 FN_VI3_D11_Y3, FN_AVB_AVTP_MATCH,
160
161 /* IPSR4 */
162 FN_VI4_CLKENB, FN_VI0_D12_G4_Y4, FN_VI4_HSYNC_N, FN_VI0_D13_G5_Y5,
163 FN_VI4_VSYNC_N, FN_VI0_D14_G6_Y6, FN_RDR_CLKOUT,
164 FN_VI4_D0_C0, FN_VI0_D15_G7_Y7,
165 FN_VI4_D1_C1, FN_VI0_D16_R0, FN_VI1_D12_G4_Y4,
166 FN_VI4_D2_C2, FN_VI0_D17_R1, FN_VI1_D13_G5_Y5,
167 FN_VI4_D3_C3, FN_VI0_D18_R2, FN_VI1_D14_G6_Y6,
168 FN_VI4_D4_C4, FN_VI0_D19_R3, FN_VI1_D15_G7_Y7,
169 FN_VI4_D5_C5, FN_VI0_D20_R4, FN_VI2_D12_Y4,
170 FN_VI4_D6_C6, FN_VI0_D21_R5, FN_VI2_D13_Y5,
171 FN_VI4_D7_C7, FN_VI0_D22_R6, FN_VI2_D14_Y6,
172 FN_VI4_D8_Y0, FN_VI0_D23_R7, FN_VI2_D15_Y7,
173 FN_VI4_D9_Y1, FN_VI3_D12_Y4, FN_VI4_D10_Y2, FN_VI3_D13_Y5,
174 FN_VI4_D11_Y3, FN_VI3_D14_Y6, FN_VI4_FIELD, FN_VI3_D15_Y7,
175
176 /* IPSR5 */
177 FN_VI5_CLKENB, FN_VI1_D12_G4_Y4_B, FN_VI5_HSYNC_N, FN_VI1_D13_G5_Y5_B,
178 FN_VI5_VSYNC_N, FN_VI1_D14_G6_Y6_B, FN_VI5_D0_C0, FN_VI1_D15_G7_Y7_B,
179 FN_VI5_D1_C1, FN_VI1_D16_R0, FN_VI5_D2_C2, FN_VI1_D17_R1,
180 FN_VI5_D3_C3, FN_VI1_D18_R2, FN_VI5_D4_C4, FN_VI1_D19_R3,
181 FN_VI5_D5_C5, FN_VI1_D20_R4, FN_VI5_D6_C6, FN_VI1_D21_R5,
182 FN_VI5_D7_C7, FN_VI1_D22_R6, FN_VI5_D8_Y0, FN_VI1_D23_R7,
183
184 /* IPSR6 */
185 FN_MSIOF0_SCK, FN_HSCK0, FN_MSIOF0_SYNC, FN_HCTS0_N,
186 FN_MSIOF0_TXD, FN_HTX0, FN_MSIOF0_RXD, FN_HRX0,
187 FN_MSIOF1_SCK, FN_HSCK1, FN_MSIOF1_SYNC, FN_HRTS1_N,
188 FN_MSIOF1_TXD, FN_HTX1, FN_MSIOF1_RXD, FN_HRX1,
189 FN_DRACK0, FN_SCK2, FN_DACK0, FN_TX2, FN_DREQ0_N, FN_RX2,
190 FN_DACK1, FN_SCK3, FN_TX3, FN_DREQ1_N, FN_RX3,
191
192 /* IPSR7 */
193 FN_PWM0, FN_TCLK1, FN_FSO_CFE_0, FN_PWM1, FN_TCLK2, FN_FSO_CFE_1,
194 FN_PWM2, FN_TCLK3, FN_FSO_TOE, FN_PWM3, FN_PWM4,
195 FN_SSI_SCK34, FN_TPU0TO0, FN_SSI_WS34, FN_TPU0TO1,
196 FN_SSI_SDATA3, FN_TPU0TO2, FN_SSI_SCK4, FN_TPU0TO3,
197 FN_SSI_WS4, FN_SSI_SDATA4, FN_AUDIO_CLKOUT,
198 FN_AUDIO_CLKA, FN_AUDIO_CLKB,
199
200 /* MOD_SEL */
201 FN_SEL_VI1_0, FN_SEL_VI1_1,
202 PINMUX_FUNCTION_END,
203
204 PINMUX_MARK_BEGIN,
205 DU1_DB2_C0_DATA12_MARK, DU1_DB3_C1_DATA13_MARK,
206 DU1_DB4_C2_DATA14_MARK, DU1_DB5_C3_DATA15_MARK,
207 DU1_DB6_C4_MARK, DU1_DB7_C5_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
208 DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
209 DU1_DISP_MARK, DU1_CDE_MARK,
210
211 D0_MARK, D1_MARK, D2_MARK, D3_MARK, D4_MARK, D5_MARK, D6_MARK,
212 D7_MARK, D8_MARK, D9_MARK, D10_MARK, D11_MARK, D12_MARK, D13_MARK,
213 D14_MARK, D15_MARK, A0_MARK, A1_MARK, A2_MARK, A3_MARK, A4_MARK,
214 A5_MARK, A6_MARK, A7_MARK, A8_MARK, A9_MARK, A10_MARK, A11_MARK,
215 A12_MARK, A13_MARK, A14_MARK, A15_MARK,
216
217 A16_MARK, A17_MARK, A18_MARK, A19_MARK, CS1_N_A26_MARK,
218 EX_CS0_N_MARK, EX_CS1_N_MARK, EX_CS2_N_MARK, EX_CS3_N_MARK,
219 EX_CS4_N_MARK, EX_CS5_N_MARK, BS_N_MARK, RD_N_MARK, RD_WR_N_MARK,
220 WE0_N_MARK, WE1_N_MARK, EX_WAIT0_MARK,
221 IRQ0_MARK, IRQ1_MARK, IRQ2_MARK, IRQ3_MARK, CS0_N_MARK,
222
223 VI0_CLK_MARK, VI0_CLKENB_MARK, VI0_HSYNC_N_MARK, VI0_VSYNC_N_MARK,
224 VI0_D0_B0_C0_MARK, VI0_D1_B1_C1_MARK, VI0_D2_B2_C2_MARK,
225 VI0_D3_B3_C3_MARK, VI0_D4_B4_C4_MARK, VI0_D5_B5_C5_MARK,
226 VI0_D6_B6_C6_MARK, VI0_D7_B7_C7_MARK, VI0_D8_G0_Y0_MARK,
227 VI0_D9_G1_Y1_MARK, VI0_D10_G2_Y2_MARK, VI0_D11_G3_Y3_MARK,
228 VI0_FIELD_MARK,
229
230 VI1_CLK_MARK, VI1_CLKENB_MARK, VI1_HSYNC_N_MARK, VI1_VSYNC_N_MARK,
231 VI1_D0_B0_C0_MARK, VI1_D1_B1_C1_MARK, VI1_D2_B2_C2_MARK,
232 VI1_D3_B3_C3_MARK, VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
233 VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK, VI1_D8_G0_Y0_MARK,
234 VI1_D9_G1_Y1_MARK, VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
235 VI1_FIELD_MARK,
236
237 VI3_D10_Y2_MARK, VI3_FIELD_MARK,
238
239 VI4_CLK_MARK,
240
241 VI5_CLK_MARK, VI5_D9_Y1_MARK, VI5_D10_Y2_MARK, VI5_D11_Y3_MARK,
242 VI5_FIELD_MARK,
243
244 HRTS0_N_MARK, HCTS1_N_MARK, SCK0_MARK, CTS0_N_MARK, RTS0_N_MARK,
245 TX0_MARK, RX0_MARK, SCK1_MARK, CTS1_N_MARK, RTS1_N_MARK,
246 TX1_MARK, RX1_MARK, SCIF_CLK_MARK, CAN0_TX_MARK, CAN0_RX_MARK,
247 CAN_CLK_MARK, CAN1_TX_MARK, CAN1_RX_MARK,
248
249 SD0_CLK_MARK, SD0_CMD_MARK, SD0_DAT0_MARK, SD0_DAT1_MARK,
250 SD0_DAT2_MARK, SD0_DAT3_MARK, SD0_CD_MARK, SD0_WP_MARK,
251 ADICLK_MARK, ADICS_SAMP_MARK, ADIDATA_MARK, ADICHS0_MARK,
252 ADICHS1_MARK, ADICHS2_MARK, AVS1_MARK, AVS2_MARK,
253
254 /* IPSR0 */
255 DU0_DR0_DATA0_MARK, DU0_DR1_DATA1_MARK, DU0_DR2_Y4_DATA2_MARK,
256 DU0_DR3_Y5_DATA3_MARK, DU0_DR4_Y6_DATA4_MARK, DU0_DR5_Y7_DATA5_MARK,
257 DU0_DR6_Y8_DATA6_MARK, DU0_DR7_Y9_DATA7_MARK, DU0_DG0_DATA8_MARK,
258 DU0_DG1_DATA9_MARK, DU0_DG2_C6_DATA10_MARK, DU0_DG3_C7_DATA11_MARK,
259 DU0_DG4_Y0_DATA12_MARK, DU0_DG5_Y1_DATA13_MARK, DU0_DG6_Y2_DATA14_MARK,
260 DU0_DG7_Y3_DATA15_MARK, DU0_DB0_MARK, DU0_DB1_MARK,
261 DU0_DB2_C0_MARK, DU0_DB3_C1_MARK, DU0_DB4_C2_MARK, DU0_DB5_C3_MARK,
262 DU0_DB6_C4_MARK, DU0_DB7_C5_MARK,
263
264 /* IPSR1 */
265 DU0_EXHSYNC_DU0_HSYNC_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK,
266 DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, DU0_DISP_MARK, DU0_CDE_MARK,
267 DU1_DR2_Y4_DATA0_MARK, DU1_DR3_Y5_DATA1_MARK, DU1_DR4_Y6_DATA2_MARK,
268 DU1_DR5_Y7_DATA3_MARK, DU1_DR6_DATA4_MARK, DU1_DR7_DATA5_MARK,
269 DU1_DG2_C6_DATA6_MARK, DU1_DG3_C7_DATA7_MARK, DU1_DG4_Y0_DATA8_MARK,
270 DU1_DG5_Y1_DATA9_MARK, DU1_DG6_Y2_DATA10_MARK, DU1_DG7_Y3_DATA11_MARK,
271 A20_MARK, MOSI_IO0_MARK, A21_MARK, MISO_IO1_MARK, A22_MARK, IO2_MARK,
272 A23_MARK, IO3_MARK, A24_MARK, SPCLK_MARK, A25_MARK, SSL_MARK,
273
274 /* IPSR2 */
275 VI2_CLK_MARK, AVB_RX_CLK_MARK, VI2_CLKENB_MARK, AVB_RX_DV_MARK,
276 VI2_HSYNC_N_MARK, AVB_RXD0_MARK, VI2_VSYNC_N_MARK, AVB_RXD1_MARK,
277 VI2_D0_C0_MARK, AVB_RXD2_MARK, VI2_D1_C1_MARK, AVB_TX_CLK_MARK,
278 VI2_D2_C2_MARK, AVB_RXD4_MARK, VI2_D3_C3_MARK, AVB_RXD5_MARK,
279 VI2_D4_C4_MARK, AVB_RXD6_MARK, VI2_D5_C5_MARK, AVB_RXD7_MARK,
280 VI2_D6_C6_MARK, AVB_RX_ER_MARK, VI2_D7_C7_MARK, AVB_COL_MARK,
281 VI2_D8_Y0_MARK, AVB_RXD3_MARK, VI2_D9_Y1_MARK, AVB_TX_EN_MARK,
282 VI2_D10_Y2_MARK, AVB_TXD0_MARK,
283 VI2_D11_Y3_MARK, AVB_TXD1_MARK, VI2_FIELD_MARK, AVB_TXD2_MARK,
284
285 /* IPSR3 */
286 VI3_CLK_MARK, AVB_TXD3_MARK, VI3_CLKENB_MARK, AVB_TXD4_MARK,
287 VI3_HSYNC_N_MARK, AVB_TXD5_MARK, VI3_VSYNC_N_MARK, AVB_TXD6_MARK,
288 VI3_D0_C0_MARK, AVB_TXD7_MARK, VI3_D1_C1_MARK, AVB_TX_ER_MARK,
289 VI3_D2_C2_MARK, AVB_GTX_CLK_MARK, VI3_D3_C3_MARK, AVB_MDC_MARK,
290 VI3_D4_C4_MARK, AVB_MDIO_MARK, VI3_D5_C5_MARK, AVB_LINK_MARK,
291 VI3_D6_C6_MARK, AVB_MAGIC_MARK, VI3_D7_C7_MARK, AVB_PHY_INT_MARK,
292 VI3_D8_Y0_MARK, AVB_CRS_MARK, VI3_D9_Y1_MARK, AVB_GTXREFCLK_MARK,
293 VI3_D11_Y3_MARK, AVB_AVTP_MATCH_MARK,
294
295 /* IPSR4 */
296 VI4_CLKENB_MARK, VI0_D12_G4_Y4_MARK, VI4_HSYNC_N_MARK,
297 VI0_D13_G5_Y5_MARK, VI4_VSYNC_N_MARK, VI0_D14_G6_Y6_MARK,
298 RDR_CLKOUT_MARK, VI4_D0_C0_MARK, VI0_D15_G7_Y7_MARK, VI4_D1_C1_MARK,
299 VI0_D16_R0_MARK, VI1_D12_G4_Y4_MARK, VI4_D2_C2_MARK, VI0_D17_R1_MARK,
300 VI1_D13_G5_Y5_MARK, VI4_D3_C3_MARK, VI0_D18_R2_MARK, VI1_D14_G6_Y6_MARK,
301 VI4_D4_C4_MARK, VI0_D19_R3_MARK, VI1_D15_G7_Y7_MARK, VI4_D5_C5_MARK,
302 VI0_D20_R4_MARK, VI2_D12_Y4_MARK, VI4_D6_C6_MARK, VI0_D21_R5_MARK,
303 VI2_D13_Y5_MARK, VI4_D7_C7_MARK, VI0_D22_R6_MARK, VI2_D14_Y6_MARK,
304 VI4_D8_Y0_MARK, VI0_D23_R7_MARK, VI2_D15_Y7_MARK, VI4_D9_Y1_MARK,
305 VI3_D12_Y4_MARK, VI4_D10_Y2_MARK, VI3_D13_Y5_MARK, VI4_D11_Y3_MARK,
306 VI3_D14_Y6_MARK, VI4_FIELD_MARK, VI3_D15_Y7_MARK,
307
308 /* IPSR5 */
309 VI5_CLKENB_MARK, VI1_D12_G4_Y4_B_MARK, VI5_HSYNC_N_MARK,
310 VI1_D13_G5_Y5_B_MARK, VI5_VSYNC_N_MARK, VI1_D14_G6_Y6_B_MARK,
311 VI5_D0_C0_MARK, VI1_D15_G7_Y7_B_MARK, VI5_D1_C1_MARK, VI1_D16_R0_MARK,
312 VI5_D2_C2_MARK, VI1_D17_R1_MARK, VI5_D3_C3_MARK, VI1_D18_R2_MARK,
313 VI5_D4_C4_MARK, VI1_D19_R3_MARK, VI5_D5_C5_MARK, VI1_D20_R4_MARK,
314 VI5_D6_C6_MARK, VI1_D21_R5_MARK, VI5_D7_C7_MARK, VI1_D22_R6_MARK,
315 VI5_D8_Y0_MARK, VI1_D23_R7_MARK,
316
317 /* IPSR6 */
318 MSIOF0_SCK_MARK, HSCK0_MARK, MSIOF0_SYNC_MARK, HCTS0_N_MARK,
319 MSIOF0_TXD_MARK, HTX0_MARK, MSIOF0_RXD_MARK, HRX0_MARK,
320 MSIOF1_SCK_MARK, HSCK1_MARK, MSIOF1_SYNC_MARK, HRTS1_N_MARK,
321 MSIOF1_TXD_MARK, HTX1_MARK, MSIOF1_RXD_MARK, HRX1_MARK,
322 DRACK0_MARK, SCK2_MARK, DACK0_MARK, TX2_MARK, DREQ0_N_MARK,
323 RX2_MARK, DACK1_MARK, SCK3_MARK, TX3_MARK, DREQ1_N_MARK,
324 RX3_MARK,
325
326 /* IPSR7 */
327 PWM0_MARK, TCLK1_MARK, FSO_CFE_0_MARK, PWM1_MARK, TCLK2_MARK,
328 FSO_CFE_1_MARK, PWM2_MARK, TCLK3_MARK, FSO_TOE_MARK, PWM3_MARK,
329 PWM4_MARK, SSI_SCK34_MARK, TPU0TO0_MARK, SSI_WS34_MARK, TPU0TO1_MARK,
330 SSI_SDATA3_MARK, TPU0TO2_MARK, SSI_SCK4_MARK, TPU0TO3_MARK,
331 SSI_WS4_MARK, SSI_SDATA4_MARK, AUDIO_CLKOUT_MARK, AUDIO_CLKA_MARK,
332 AUDIO_CLKB_MARK,
333 PINMUX_MARK_END,
334};
335
336static const u16 pinmux_data[] = {
337 PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
338
339 PINMUX_SINGLE(DU1_DB2_C0_DATA12),
340 PINMUX_SINGLE(DU1_DB3_C1_DATA13),
341 PINMUX_SINGLE(DU1_DB4_C2_DATA14),
342 PINMUX_SINGLE(DU1_DB5_C3_DATA15),
343 PINMUX_SINGLE(DU1_DB6_C4),
344 PINMUX_SINGLE(DU1_DB7_C5),
345 PINMUX_SINGLE(DU1_EXHSYNC_DU1_HSYNC),
346 PINMUX_SINGLE(DU1_EXVSYNC_DU1_VSYNC),
347 PINMUX_SINGLE(DU1_EXODDF_DU1_ODDF_DISP_CDE),
348 PINMUX_SINGLE(DU1_DISP),
349 PINMUX_SINGLE(DU1_CDE),
350 PINMUX_SINGLE(D0),
351 PINMUX_SINGLE(D1),
352 PINMUX_SINGLE(D2),
353 PINMUX_SINGLE(D3),
354 PINMUX_SINGLE(D4),
355 PINMUX_SINGLE(D5),
356 PINMUX_SINGLE(D6),
357 PINMUX_SINGLE(D7),
358 PINMUX_SINGLE(D8),
359 PINMUX_SINGLE(D9),
360 PINMUX_SINGLE(D10),
361 PINMUX_SINGLE(D11),
362 PINMUX_SINGLE(D12),
363 PINMUX_SINGLE(D13),
364 PINMUX_SINGLE(D14),
365 PINMUX_SINGLE(D15),
366 PINMUX_SINGLE(A0),
367 PINMUX_SINGLE(A1),
368 PINMUX_SINGLE(A2),
369 PINMUX_SINGLE(A3),
370 PINMUX_SINGLE(A4),
371 PINMUX_SINGLE(A5),
372 PINMUX_SINGLE(A6),
373 PINMUX_SINGLE(A7),
374 PINMUX_SINGLE(A8),
375 PINMUX_SINGLE(A9),
376 PINMUX_SINGLE(A10),
377 PINMUX_SINGLE(A11),
378 PINMUX_SINGLE(A12),
379 PINMUX_SINGLE(A13),
380 PINMUX_SINGLE(A14),
381 PINMUX_SINGLE(A15),
382 PINMUX_SINGLE(A16),
383 PINMUX_SINGLE(A17),
384 PINMUX_SINGLE(A18),
385 PINMUX_SINGLE(A19),
386 PINMUX_SINGLE(CS1_N_A26),
387 PINMUX_SINGLE(EX_CS0_N),
388 PINMUX_SINGLE(EX_CS1_N),
389 PINMUX_SINGLE(EX_CS2_N),
390 PINMUX_SINGLE(EX_CS3_N),
391 PINMUX_SINGLE(EX_CS4_N),
392 PINMUX_SINGLE(EX_CS5_N),
393 PINMUX_SINGLE(BS_N),
394 PINMUX_SINGLE(RD_N),
395 PINMUX_SINGLE(RD_WR_N),
396 PINMUX_SINGLE(WE0_N),
397 PINMUX_SINGLE(WE1_N),
398 PINMUX_SINGLE(EX_WAIT0),
399 PINMUX_SINGLE(IRQ0),
400 PINMUX_SINGLE(IRQ1),
401 PINMUX_SINGLE(IRQ2),
402 PINMUX_SINGLE(IRQ3),
403 PINMUX_SINGLE(CS0_N),
404 PINMUX_SINGLE(VI0_CLK),
405 PINMUX_SINGLE(VI0_CLKENB),
406 PINMUX_SINGLE(VI0_HSYNC_N),
407 PINMUX_SINGLE(VI0_VSYNC_N),
408 PINMUX_SINGLE(VI0_D0_B0_C0),
409 PINMUX_SINGLE(VI0_D1_B1_C1),
410 PINMUX_SINGLE(VI0_D2_B2_C2),
411 PINMUX_SINGLE(VI0_D3_B3_C3),
412 PINMUX_SINGLE(VI0_D4_B4_C4),
413 PINMUX_SINGLE(VI0_D5_B5_C5),
414 PINMUX_SINGLE(VI0_D6_B6_C6),
415 PINMUX_SINGLE(VI0_D7_B7_C7),
416 PINMUX_SINGLE(VI0_D8_G0_Y0),
417 PINMUX_SINGLE(VI0_D9_G1_Y1),
418 PINMUX_SINGLE(VI0_D10_G2_Y2),
419 PINMUX_SINGLE(VI0_D11_G3_Y3),
420 PINMUX_SINGLE(VI0_FIELD),
421 PINMUX_SINGLE(VI1_CLK),
422 PINMUX_SINGLE(VI1_CLKENB),
423 PINMUX_SINGLE(VI1_HSYNC_N),
424 PINMUX_SINGLE(VI1_VSYNC_N),
425 PINMUX_SINGLE(VI1_D0_B0_C0),
426 PINMUX_SINGLE(VI1_D1_B1_C1),
427 PINMUX_SINGLE(VI1_D2_B2_C2),
428 PINMUX_SINGLE(VI1_D3_B3_C3),
429 PINMUX_SINGLE(VI1_D4_B4_C4),
430 PINMUX_SINGLE(VI1_D5_B5_C5),
431 PINMUX_SINGLE(VI1_D6_B6_C6),
432 PINMUX_SINGLE(VI1_D7_B7_C7),
433 PINMUX_SINGLE(VI1_D8_G0_Y0),
434 PINMUX_SINGLE(VI1_D9_G1_Y1),
435 PINMUX_SINGLE(VI1_D10_G2_Y2),
436 PINMUX_SINGLE(VI1_D11_G3_Y3),
437 PINMUX_SINGLE(VI1_FIELD),
438 PINMUX_SINGLE(VI3_D10_Y2),
439 PINMUX_SINGLE(VI3_FIELD),
440 PINMUX_SINGLE(VI4_CLK),
441 PINMUX_SINGLE(VI5_CLK),
442 PINMUX_SINGLE(VI5_D9_Y1),
443 PINMUX_SINGLE(VI5_D10_Y2),
444 PINMUX_SINGLE(VI5_D11_Y3),
445 PINMUX_SINGLE(VI5_FIELD),
446 PINMUX_SINGLE(HRTS0_N),
447 PINMUX_SINGLE(HCTS1_N),
448 PINMUX_SINGLE(SCK0),
449 PINMUX_SINGLE(CTS0_N),
450 PINMUX_SINGLE(RTS0_N),
451 PINMUX_SINGLE(TX0),
452 PINMUX_SINGLE(RX0),
453 PINMUX_SINGLE(SCK1),
454 PINMUX_SINGLE(CTS1_N),
455 PINMUX_SINGLE(RTS1_N),
456 PINMUX_SINGLE(TX1),
457 PINMUX_SINGLE(RX1),
458 PINMUX_SINGLE(SCIF_CLK),
459 PINMUX_SINGLE(CAN0_TX),
460 PINMUX_SINGLE(CAN0_RX),
461 PINMUX_SINGLE(CAN_CLK),
462 PINMUX_SINGLE(CAN1_TX),
463 PINMUX_SINGLE(CAN1_RX),
464 PINMUX_SINGLE(SD0_CLK),
465 PINMUX_SINGLE(SD0_CMD),
466 PINMUX_SINGLE(SD0_DAT0),
467 PINMUX_SINGLE(SD0_DAT1),
468 PINMUX_SINGLE(SD0_DAT2),
469 PINMUX_SINGLE(SD0_DAT3),
470 PINMUX_SINGLE(SD0_CD),
471 PINMUX_SINGLE(SD0_WP),
472 PINMUX_SINGLE(ADICLK),
473 PINMUX_SINGLE(ADICS_SAMP),
474 PINMUX_SINGLE(ADIDATA),
475 PINMUX_SINGLE(ADICHS0),
476 PINMUX_SINGLE(ADICHS1),
477 PINMUX_SINGLE(ADICHS2),
478 PINMUX_SINGLE(AVS1),
479 PINMUX_SINGLE(AVS2),
480
481 /* IPSR0 */
482 PINMUX_IPSR_GPSR(IP0_0, DU0_DR0_DATA0),
483 PINMUX_IPSR_GPSR(IP0_1, DU0_DR1_DATA1),
484 PINMUX_IPSR_GPSR(IP0_2, DU0_DR2_Y4_DATA2),
485 PINMUX_IPSR_GPSR(IP0_3, DU0_DR3_Y5_DATA3),
486 PINMUX_IPSR_GPSR(IP0_4, DU0_DR4_Y6_DATA4),
487 PINMUX_IPSR_GPSR(IP0_5, DU0_DR5_Y7_DATA5),
488 PINMUX_IPSR_GPSR(IP0_6, DU0_DR6_Y8_DATA6),
489 PINMUX_IPSR_GPSR(IP0_7, DU0_DR7_Y9_DATA7),
490 PINMUX_IPSR_GPSR(IP0_8, DU0_DG0_DATA8),
491 PINMUX_IPSR_GPSR(IP0_9, DU0_DG1_DATA9),
492 PINMUX_IPSR_GPSR(IP0_10, DU0_DG2_C6_DATA10),
493 PINMUX_IPSR_GPSR(IP0_11, DU0_DG3_C7_DATA11),
494 PINMUX_IPSR_GPSR(IP0_12, DU0_DG4_Y0_DATA12),
495 PINMUX_IPSR_GPSR(IP0_13, DU0_DG5_Y1_DATA13),
496 PINMUX_IPSR_GPSR(IP0_14, DU0_DG6_Y2_DATA14),
497 PINMUX_IPSR_GPSR(IP0_15, DU0_DG7_Y3_DATA15),
498 PINMUX_IPSR_GPSR(IP0_16, DU0_DB0),
499 PINMUX_IPSR_GPSR(IP0_17, DU0_DB1),
500 PINMUX_IPSR_GPSR(IP0_18, DU0_DB2_C0),
501 PINMUX_IPSR_GPSR(IP0_19, DU0_DB3_C1),
502 PINMUX_IPSR_GPSR(IP0_20, DU0_DB4_C2),
503 PINMUX_IPSR_GPSR(IP0_21, DU0_DB5_C3),
504 PINMUX_IPSR_GPSR(IP0_22, DU0_DB6_C4),
505 PINMUX_IPSR_GPSR(IP0_23, DU0_DB7_C5),
506
507 /* IPSR1 */
508 PINMUX_IPSR_GPSR(IP1_0, DU0_EXHSYNC_DU0_HSYNC),
509 PINMUX_IPSR_GPSR(IP1_1, DU0_EXVSYNC_DU0_VSYNC),
510 PINMUX_IPSR_GPSR(IP1_2, DU0_EXODDF_DU0_ODDF_DISP_CDE),
511 PINMUX_IPSR_GPSR(IP1_3, DU0_DISP),
512 PINMUX_IPSR_GPSR(IP1_4, DU0_CDE),
513 PINMUX_IPSR_GPSR(IP1_5, DU1_DR2_Y4_DATA0),
514 PINMUX_IPSR_GPSR(IP1_6, DU1_DR3_Y5_DATA1),
515 PINMUX_IPSR_GPSR(IP1_7, DU1_DR4_Y6_DATA2),
516 PINMUX_IPSR_GPSR(IP1_8, DU1_DR5_Y7_DATA3),
517 PINMUX_IPSR_GPSR(IP1_9, DU1_DR6_DATA4),
518 PINMUX_IPSR_GPSR(IP1_10, DU1_DR7_DATA5),
519 PINMUX_IPSR_GPSR(IP1_11, DU1_DG2_C6_DATA6),
520 PINMUX_IPSR_GPSR(IP1_12, DU1_DG3_C7_DATA7),
521 PINMUX_IPSR_GPSR(IP1_13, DU1_DG4_Y0_DATA8),
522 PINMUX_IPSR_GPSR(IP1_14, DU1_DG5_Y1_DATA9),
523 PINMUX_IPSR_GPSR(IP1_15, DU1_DG6_Y2_DATA10),
524 PINMUX_IPSR_GPSR(IP1_16, DU1_DG7_Y3_DATA11),
525 PINMUX_IPSR_GPSR(IP1_17, A20),
526 PINMUX_IPSR_GPSR(IP1_17, MOSI_IO0),
527 PINMUX_IPSR_GPSR(IP1_18, A21),
528 PINMUX_IPSR_GPSR(IP1_18, MISO_IO1),
529 PINMUX_IPSR_GPSR(IP1_19, A22),
530 PINMUX_IPSR_GPSR(IP1_19, IO2),
531 PINMUX_IPSR_GPSR(IP1_20, A23),
532 PINMUX_IPSR_GPSR(IP1_20, IO3),
533 PINMUX_IPSR_GPSR(IP1_21, A24),
534 PINMUX_IPSR_GPSR(IP1_21, SPCLK),
535 PINMUX_IPSR_GPSR(IP1_22, A25),
536 PINMUX_IPSR_GPSR(IP1_22, SSL),
537
538 /* IPSR2 */
539 PINMUX_IPSR_GPSR(IP2_0, VI2_CLK),
540 PINMUX_IPSR_GPSR(IP2_0, AVB_RX_CLK),
541 PINMUX_IPSR_GPSR(IP2_1, VI2_CLKENB),
542 PINMUX_IPSR_GPSR(IP2_1, AVB_RX_DV),
543 PINMUX_IPSR_GPSR(IP2_2, VI2_HSYNC_N),
544 PINMUX_IPSR_GPSR(IP2_2, AVB_RXD0),
545 PINMUX_IPSR_GPSR(IP2_3, VI2_VSYNC_N),
546 PINMUX_IPSR_GPSR(IP2_3, AVB_RXD1),
547 PINMUX_IPSR_GPSR(IP2_4, VI2_D0_C0),
548 PINMUX_IPSR_GPSR(IP2_4, AVB_RXD2),
549 PINMUX_IPSR_GPSR(IP2_5, VI2_D1_C1),
550 PINMUX_IPSR_GPSR(IP2_5, AVB_RXD3),
551 PINMUX_IPSR_GPSR(IP2_6, VI2_D2_C2),
552 PINMUX_IPSR_GPSR(IP2_6, AVB_RXD4),
553 PINMUX_IPSR_GPSR(IP2_7, VI2_D3_C3),
554 PINMUX_IPSR_GPSR(IP2_7, AVB_RXD5),
555 PINMUX_IPSR_GPSR(IP2_8, VI2_D4_C4),
556 PINMUX_IPSR_GPSR(IP2_8, AVB_RXD6),
557 PINMUX_IPSR_GPSR(IP2_9, VI2_D5_C5),
558 PINMUX_IPSR_GPSR(IP2_9, AVB_RXD7),
559 PINMUX_IPSR_GPSR(IP2_10, VI2_D6_C6),
560 PINMUX_IPSR_GPSR(IP2_10, AVB_RX_ER),
561 PINMUX_IPSR_GPSR(IP2_11, VI2_D7_C7),
562 PINMUX_IPSR_GPSR(IP2_11, AVB_COL),
563 PINMUX_IPSR_GPSR(IP2_12, VI2_D8_Y0),
564 PINMUX_IPSR_GPSR(IP2_12, AVB_TXD3),
565 PINMUX_IPSR_GPSR(IP2_13, VI2_D9_Y1),
566 PINMUX_IPSR_GPSR(IP2_13, AVB_TX_EN),
567 PINMUX_IPSR_GPSR(IP2_14, VI2_D10_Y2),
568 PINMUX_IPSR_GPSR(IP2_14, AVB_TXD0),
569 PINMUX_IPSR_GPSR(IP2_15, VI2_D11_Y3),
570 PINMUX_IPSR_GPSR(IP2_15, AVB_TXD1),
571 PINMUX_IPSR_GPSR(IP2_16, VI2_FIELD),
572 PINMUX_IPSR_GPSR(IP2_16, AVB_TXD2),
573
574 /* IPSR3 */
575 PINMUX_IPSR_GPSR(IP3_0, VI3_CLK),
576 PINMUX_IPSR_GPSR(IP3_0, AVB_TX_CLK),
577 PINMUX_IPSR_GPSR(IP3_1, VI3_CLKENB),
578 PINMUX_IPSR_GPSR(IP3_1, AVB_TXD4),
579 PINMUX_IPSR_GPSR(IP3_2, VI3_HSYNC_N),
580 PINMUX_IPSR_GPSR(IP3_2, AVB_TXD5),
581 PINMUX_IPSR_GPSR(IP3_3, VI3_VSYNC_N),
582 PINMUX_IPSR_GPSR(IP3_3, AVB_TXD6),
583 PINMUX_IPSR_GPSR(IP3_4, VI3_D0_C0),
584 PINMUX_IPSR_GPSR(IP3_4, AVB_TXD7),
585 PINMUX_IPSR_GPSR(IP3_5, VI3_D1_C1),
586 PINMUX_IPSR_GPSR(IP3_5, AVB_TX_ER),
587 PINMUX_IPSR_GPSR(IP3_6, VI3_D2_C2),
588 PINMUX_IPSR_GPSR(IP3_6, AVB_GTX_CLK),
589 PINMUX_IPSR_GPSR(IP3_7, VI3_D3_C3),
590 PINMUX_IPSR_GPSR(IP3_7, AVB_MDC),
591 PINMUX_IPSR_GPSR(IP3_8, VI3_D4_C4),
592 PINMUX_IPSR_GPSR(IP3_8, AVB_MDIO),
593 PINMUX_IPSR_GPSR(IP3_9, VI3_D5_C5),
594 PINMUX_IPSR_GPSR(IP3_9, AVB_LINK),
595 PINMUX_IPSR_GPSR(IP3_10, VI3_D6_C6),
596 PINMUX_IPSR_GPSR(IP3_10, AVB_MAGIC),
597 PINMUX_IPSR_GPSR(IP3_11, VI3_D7_C7),
598 PINMUX_IPSR_GPSR(IP3_11, AVB_PHY_INT),
599 PINMUX_IPSR_GPSR(IP3_12, VI3_D8_Y0),
600 PINMUX_IPSR_GPSR(IP3_12, AVB_CRS),
601 PINMUX_IPSR_GPSR(IP3_13, VI3_D9_Y1),
602 PINMUX_IPSR_GPSR(IP3_13, AVB_GTXREFCLK),
603 PINMUX_IPSR_GPSR(IP3_14, VI3_D11_Y3),
604 PINMUX_IPSR_GPSR(IP3_14, AVB_AVTP_MATCH),
605
606 /* IPSR4 */
607 PINMUX_IPSR_GPSR(IP4_0, VI4_CLKENB),
608 PINMUX_IPSR_GPSR(IP4_0, VI0_D12_G4_Y4),
609 PINMUX_IPSR_GPSR(IP4_1, VI4_HSYNC_N),
610 PINMUX_IPSR_GPSR(IP4_1, VI0_D13_G5_Y5),
611 PINMUX_IPSR_GPSR(IP4_3_2, VI4_VSYNC_N),
612 PINMUX_IPSR_GPSR(IP4_3_2, VI0_D14_G6_Y6),
613 PINMUX_IPSR_GPSR(IP4_4, VI4_D0_C0),
614 PINMUX_IPSR_GPSR(IP4_4, VI0_D15_G7_Y7),
615 PINMUX_IPSR_GPSR(IP4_6_5, VI4_D1_C1),
616 PINMUX_IPSR_GPSR(IP4_6_5, VI0_D16_R0),
617 PINMUX_IPSR_MSEL(IP4_6_5, VI1_D12_G4_Y4, SEL_VI1_0),
618 PINMUX_IPSR_GPSR(IP4_8_7, VI4_D2_C2),
619 PINMUX_IPSR_GPSR(IP4_8_7, VI0_D17_R1),
620 PINMUX_IPSR_MSEL(IP4_8_7, VI1_D13_G5_Y5, SEL_VI1_0),
621 PINMUX_IPSR_GPSR(IP4_10_9, VI4_D3_C3),
622 PINMUX_IPSR_GPSR(IP4_10_9, VI0_D18_R2),
623 PINMUX_IPSR_MSEL(IP4_10_9, VI1_D14_G6_Y6, SEL_VI1_0),
624 PINMUX_IPSR_GPSR(IP4_12_11, VI4_D4_C4),
625 PINMUX_IPSR_GPSR(IP4_12_11, VI0_D19_R3),
626 PINMUX_IPSR_MSEL(IP4_12_11, VI1_D15_G7_Y7, SEL_VI1_0),
627 PINMUX_IPSR_GPSR(IP4_14_13, VI4_D5_C5),
628 PINMUX_IPSR_GPSR(IP4_14_13, VI0_D20_R4),
629 PINMUX_IPSR_GPSR(IP4_14_13, VI2_D12_Y4),
630 PINMUX_IPSR_GPSR(IP4_16_15, VI4_D6_C6),
631 PINMUX_IPSR_GPSR(IP4_16_15, VI0_D21_R5),
632 PINMUX_IPSR_GPSR(IP4_16_15, VI2_D13_Y5),
633 PINMUX_IPSR_GPSR(IP4_18_17, VI4_D7_C7),
634 PINMUX_IPSR_GPSR(IP4_18_17, VI0_D22_R6),
635 PINMUX_IPSR_GPSR(IP4_18_17, VI2_D14_Y6),
636 PINMUX_IPSR_GPSR(IP4_20_19, VI4_D8_Y0),
637 PINMUX_IPSR_GPSR(IP4_20_19, VI0_D23_R7),
638 PINMUX_IPSR_GPSR(IP4_20_19, VI2_D15_Y7),
639 PINMUX_IPSR_GPSR(IP4_21, VI4_D9_Y1),
640 PINMUX_IPSR_GPSR(IP4_21, VI3_D12_Y4),
641 PINMUX_IPSR_GPSR(IP4_22, VI4_D10_Y2),
642 PINMUX_IPSR_GPSR(IP4_22, VI3_D13_Y5),
643 PINMUX_IPSR_GPSR(IP4_23, VI4_D11_Y3),
644 PINMUX_IPSR_GPSR(IP4_23, VI3_D14_Y6),
645 PINMUX_IPSR_GPSR(IP4_24, VI4_FIELD),
646 PINMUX_IPSR_GPSR(IP4_24, VI3_D15_Y7),
647
648 /* IPSR5 */
649 PINMUX_IPSR_GPSR(IP5_0, VI5_CLKENB),
650 PINMUX_IPSR_MSEL(IP5_0, VI1_D12_G4_Y4_B, SEL_VI1_1),
651 PINMUX_IPSR_GPSR(IP5_1, VI5_HSYNC_N),
652 PINMUX_IPSR_MSEL(IP5_1, VI1_D13_G5_Y5_B, SEL_VI1_1),
653 PINMUX_IPSR_GPSR(IP5_2, VI5_VSYNC_N),
654 PINMUX_IPSR_MSEL(IP5_2, VI1_D14_G6_Y6_B, SEL_VI1_1),
655 PINMUX_IPSR_GPSR(IP5_3, VI5_D0_C0),
656 PINMUX_IPSR_MSEL(IP5_3, VI1_D15_G7_Y7_B, SEL_VI1_1),
657 PINMUX_IPSR_GPSR(IP5_4, VI5_D1_C1),
658 PINMUX_IPSR_GPSR(IP5_4, VI1_D16_R0),
659 PINMUX_IPSR_GPSR(IP5_5, VI5_D2_C2),
660 PINMUX_IPSR_GPSR(IP5_5, VI1_D17_R1),
661 PINMUX_IPSR_GPSR(IP5_6, VI5_D3_C3),
662 PINMUX_IPSR_GPSR(IP5_6, VI1_D18_R2),
663 PINMUX_IPSR_GPSR(IP5_7, VI5_D4_C4),
664 PINMUX_IPSR_GPSR(IP5_7, VI1_D19_R3),
665 PINMUX_IPSR_GPSR(IP5_8, VI5_D5_C5),
666 PINMUX_IPSR_GPSR(IP5_8, VI1_D20_R4),
667 PINMUX_IPSR_GPSR(IP5_9, VI5_D6_C6),
668 PINMUX_IPSR_GPSR(IP5_9, VI1_D21_R5),
669 PINMUX_IPSR_GPSR(IP5_10, VI5_D7_C7),
670 PINMUX_IPSR_GPSR(IP5_10, VI1_D22_R6),
671 PINMUX_IPSR_GPSR(IP5_11, VI5_D8_Y0),
672 PINMUX_IPSR_GPSR(IP5_11, VI1_D23_R7),
673
674 /* IPSR6 */
675 PINMUX_IPSR_GPSR(IP6_0, MSIOF0_SCK),
676 PINMUX_IPSR_GPSR(IP6_0, HSCK0),
677 PINMUX_IPSR_GPSR(IP6_1, MSIOF0_SYNC),
678 PINMUX_IPSR_GPSR(IP6_1, HCTS0_N),
679 PINMUX_IPSR_GPSR(IP6_2, MSIOF0_TXD),
680 PINMUX_IPSR_GPSR(IP6_2, HTX0),
681 PINMUX_IPSR_GPSR(IP6_3, MSIOF0_RXD),
682 PINMUX_IPSR_GPSR(IP6_3, HRX0),
683 PINMUX_IPSR_GPSR(IP6_4, MSIOF1_SCK),
684 PINMUX_IPSR_GPSR(IP6_4, HSCK1),
685 PINMUX_IPSR_GPSR(IP6_5, MSIOF1_SYNC),
686 PINMUX_IPSR_GPSR(IP6_5, HRTS1_N),
687 PINMUX_IPSR_GPSR(IP6_6, MSIOF1_TXD),
688 PINMUX_IPSR_GPSR(IP6_6, HTX1),
689 PINMUX_IPSR_GPSR(IP6_7, MSIOF1_RXD),
690 PINMUX_IPSR_GPSR(IP6_7, HRX1),
691 PINMUX_IPSR_GPSR(IP6_9_8, DRACK0),
692 PINMUX_IPSR_GPSR(IP6_9_8, SCK2),
693 PINMUX_IPSR_GPSR(IP6_11_10, DACK0),
694 PINMUX_IPSR_GPSR(IP6_11_10, TX2),
695 PINMUX_IPSR_GPSR(IP6_13_12, DREQ0_N),
696 PINMUX_IPSR_GPSR(IP6_13_12, RX2),
697 PINMUX_IPSR_GPSR(IP6_15_14, DACK1),
698 PINMUX_IPSR_GPSR(IP6_15_14, SCK3),
699 PINMUX_IPSR_GPSR(IP6_16, TX3),
700 PINMUX_IPSR_GPSR(IP6_18_17, DREQ1_N),
701 PINMUX_IPSR_GPSR(IP6_18_17, RX3),
702
703 /* IPSR7 */
704 PINMUX_IPSR_GPSR(IP7_1_0, PWM0),
705 PINMUX_IPSR_GPSR(IP7_1_0, TCLK1),
706 PINMUX_IPSR_GPSR(IP7_1_0, FSO_CFE_0),
707 PINMUX_IPSR_GPSR(IP7_3_2, PWM1),
708 PINMUX_IPSR_GPSR(IP7_3_2, TCLK2),
709 PINMUX_IPSR_GPSR(IP7_3_2, FSO_CFE_1),
710 PINMUX_IPSR_GPSR(IP7_5_4, PWM2),
711 PINMUX_IPSR_GPSR(IP7_5_4, TCLK3),
712 PINMUX_IPSR_GPSR(IP7_5_4, FSO_TOE),
713 PINMUX_IPSR_GPSR(IP7_6, PWM3),
714 PINMUX_IPSR_GPSR(IP7_7, PWM4),
715 PINMUX_IPSR_GPSR(IP7_9_8, SSI_SCK34),
716 PINMUX_IPSR_GPSR(IP7_9_8, TPU0TO0),
717 PINMUX_IPSR_GPSR(IP7_11_10, SSI_WS34),
718 PINMUX_IPSR_GPSR(IP7_11_10, TPU0TO1),
719 PINMUX_IPSR_GPSR(IP7_13_12, SSI_SDATA3),
720 PINMUX_IPSR_GPSR(IP7_13_12, TPU0TO2),
721 PINMUX_IPSR_GPSR(IP7_15_14, SSI_SCK4),
722 PINMUX_IPSR_GPSR(IP7_15_14, TPU0TO3),
723 PINMUX_IPSR_GPSR(IP7_16, SSI_WS4),
724 PINMUX_IPSR_GPSR(IP7_17, SSI_SDATA4),
725 PINMUX_IPSR_GPSR(IP7_18, AUDIO_CLKOUT),
726 PINMUX_IPSR_GPSR(IP7_19, AUDIO_CLKA),
727 PINMUX_IPSR_GPSR(IP7_20, AUDIO_CLKB),
728};
729
730static const struct sh_pfc_pin pinmux_pins[] = {
731 PINMUX_GPIO_GP_ALL(),
732};
733
734/* - AVB -------------------------------------------------------------------- */
735static const unsigned int avb_link_pins[] = {
736 RCAR_GP_PIN(7, 9),
737};
738static const unsigned int avb_link_mux[] = {
739 AVB_LINK_MARK,
740};
741static const unsigned int avb_magic_pins[] = {
742 RCAR_GP_PIN(7, 10),
743};
744static const unsigned int avb_magic_mux[] = {
745 AVB_MAGIC_MARK,
746};
747static const unsigned int avb_phy_int_pins[] = {
748 RCAR_GP_PIN(7, 11),
749};
750static const unsigned int avb_phy_int_mux[] = {
751 AVB_PHY_INT_MARK,
752};
753static const unsigned int avb_mdio_pins[] = {
754 RCAR_GP_PIN(7, 7), RCAR_GP_PIN(7, 8),
755};
756static const unsigned int avb_mdio_mux[] = {
757 AVB_MDC_MARK, AVB_MDIO_MARK,
758};
759static const unsigned int avb_mii_pins[] = {
760 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15), RCAR_GP_PIN(6, 16),
761 RCAR_GP_PIN(6, 12),
762
763 RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3), RCAR_GP_PIN(6, 4),
764 RCAR_GP_PIN(6, 5),
765
766 RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
767 RCAR_GP_PIN(7, 12), RCAR_GP_PIN(6, 13), RCAR_GP_PIN(7, 5),
768 RCAR_GP_PIN(7, 0), RCAR_GP_PIN(6, 11),
769};
770static const unsigned int avb_mii_mux[] = {
771 AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
772 AVB_TXD3_MARK,
773
774 AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
775 AVB_RXD3_MARK,
776
777 AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
778 AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_ER_MARK,
779 AVB_TX_CLK_MARK, AVB_COL_MARK,
780};
781static const unsigned int avb_gmii_pins[] = {
782 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15), RCAR_GP_PIN(6, 16),
783 RCAR_GP_PIN(6, 12), RCAR_GP_PIN(7, 1), RCAR_GP_PIN(7, 2),
784 RCAR_GP_PIN(7, 3), RCAR_GP_PIN(7, 4),
785
786 RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3), RCAR_GP_PIN(6, 4),
787 RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7),
788 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
789
790 RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
791 RCAR_GP_PIN(7, 12), RCAR_GP_PIN(7, 6), RCAR_GP_PIN(7, 13),
792 RCAR_GP_PIN(6, 13), RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 0),
793 RCAR_GP_PIN(6, 11),
794};
795static const unsigned int avb_gmii_mux[] = {
796 AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
797 AVB_TXD3_MARK, AVB_TXD4_MARK, AVB_TXD5_MARK,
798 AVB_TXD6_MARK, AVB_TXD7_MARK,
799
800 AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
801 AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK,
802 AVB_RXD6_MARK, AVB_RXD7_MARK,
803
804 AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
805 AVB_CRS_MARK, AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK,
806 AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK,
807 AVB_COL_MARK,
808};
809static const unsigned int avb_avtp_match_pins[] = {
810 RCAR_GP_PIN(7, 15),
811};
812static const unsigned int avb_avtp_match_mux[] = {
813 AVB_AVTP_MATCH_MARK,
814};
815/* - CAN -------------------------------------------------------------------- */
816static const unsigned int can0_data_pins[] = {
817 /* TX, RX */
818 RCAR_GP_PIN(10, 27), RCAR_GP_PIN(10, 28),
819};
820static const unsigned int can0_data_mux[] = {
821 CAN0_TX_MARK, CAN0_RX_MARK,
822};
823static const unsigned int can1_data_pins[] = {
824 /* TX, RX */
825 RCAR_GP_PIN(10, 30), RCAR_GP_PIN(10, 31),
826};
827static const unsigned int can1_data_mux[] = {
828 CAN1_TX_MARK, CAN1_RX_MARK,
829};
830static const unsigned int can_clk_pins[] = {
831 /* CAN_CLK */
832 RCAR_GP_PIN(10, 29),
833};
834static const unsigned int can_clk_mux[] = {
835 CAN_CLK_MARK,
836};
837/* - DU --------------------------------------------------------------------- */
838static const unsigned int du0_rgb666_pins[] = {
839 /* R[7:2], G[7:2], B[7:2] */
840 RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 5),
841 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 2),
842 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
843 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
844 RCAR_GP_PIN(0, 23), RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 21),
845 RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 18),
846};
847static const unsigned int du0_rgb666_mux[] = {
848 DU0_DR7_Y9_DATA7_MARK, DU0_DR6_Y8_DATA6_MARK, DU0_DR5_Y7_DATA5_MARK,
849 DU0_DR4_Y6_DATA4_MARK, DU0_DR3_Y5_DATA3_MARK, DU0_DR2_Y4_DATA2_MARK,
850 DU0_DG7_Y3_DATA15_MARK, DU0_DG6_Y2_DATA14_MARK, DU0_DG5_Y1_DATA13_MARK,
851 DU0_DG4_Y0_DATA12_MARK, DU0_DG3_C7_DATA11_MARK, DU0_DG2_C6_DATA10_MARK,
852 DU0_DB7_C5_MARK, DU0_DB6_C4_MARK, DU0_DB5_C3_MARK,
853 DU0_DB4_C2_MARK, DU0_DB3_C1_MARK, DU0_DB2_C0_MARK,
854};
855static const unsigned int du0_rgb888_pins[] = {
856 /* R[7:0], G[7:0], B[7:0] */
857 RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 5),
858 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 2),
859 RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
860 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
861 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
862 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
863 RCAR_GP_PIN(0, 23), RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 21),
864 RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 18),
865 RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16),
866};
867static const unsigned int du0_rgb888_mux[] = {
868 DU0_DR7_Y9_DATA7_MARK, DU0_DR6_Y8_DATA6_MARK, DU0_DR5_Y7_DATA5_MARK,
869 DU0_DR4_Y6_DATA4_MARK, DU0_DR3_Y5_DATA3_MARK, DU0_DR2_Y4_DATA2_MARK,
870 DU0_DR1_DATA1_MARK, DU0_DR0_DATA0_MARK,
871 DU0_DG7_Y3_DATA15_MARK, DU0_DG6_Y2_DATA14_MARK, DU0_DG5_Y1_DATA13_MARK,
872 DU0_DG4_Y0_DATA12_MARK, DU0_DG3_C7_DATA11_MARK, DU0_DG2_C6_DATA10_MARK,
873 DU0_DG1_DATA9_MARK, DU0_DG0_DATA8_MARK,
874 DU0_DB7_C5_MARK, DU0_DB6_C4_MARK, DU0_DB5_C3_MARK,
875 DU0_DB4_C2_MARK, DU0_DB3_C1_MARK, DU0_DB2_C0_MARK,
876 DU0_DB1_MARK, DU0_DB0_MARK,
877};
878static const unsigned int du0_sync_pins[] = {
879 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
880 RCAR_GP_PIN(0, 25), RCAR_GP_PIN(0, 24),
881};
882static const unsigned int du0_sync_mux[] = {
883 DU0_EXVSYNC_DU0_VSYNC_MARK, DU0_EXHSYNC_DU0_HSYNC_MARK,
884};
885static const unsigned int du0_oddf_pins[] = {
886 /* EXODDF/ODDF/DISP/CDE */
887 RCAR_GP_PIN(0, 26),
888};
889static const unsigned int du0_oddf_mux[] = {
890 DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK
891};
892static const unsigned int du0_disp_pins[] = {
893 /* DISP */
894 RCAR_GP_PIN(0, 27),
895};
896static const unsigned int du0_disp_mux[] = {
897 DU0_DISP_MARK,
898};
899static const unsigned int du0_cde_pins[] = {
900 /* CDE */
901 RCAR_GP_PIN(0, 28),
902};
903static const unsigned int du0_cde_mux[] = {
904 DU0_CDE_MARK,
905};
906static const unsigned int du1_rgb666_pins[] = {
907 /* R[7:2], G[7:2], B[7:2] */
908 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3),
909 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
910 RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
911 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
912 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 15),
913 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 12),
914};
915static const unsigned int du1_rgb666_mux[] = {
916 DU1_DR7_DATA5_MARK, DU1_DR6_DATA4_MARK, DU1_DR5_Y7_DATA3_MARK,
917 DU1_DR4_Y6_DATA2_MARK, DU1_DR3_Y5_DATA1_MARK, DU1_DR2_Y4_DATA0_MARK,
918 DU1_DG7_Y3_DATA11_MARK, DU1_DG6_Y2_DATA10_MARK, DU1_DG5_Y1_DATA9_MARK,
919 DU1_DG4_Y0_DATA8_MARK, DU1_DG3_C7_DATA7_MARK, DU1_DG2_C6_DATA6_MARK,
920 DU1_DB7_C5_MARK, DU1_DB6_C4_MARK, DU1_DB5_C3_DATA15_MARK,
921 DU1_DB4_C2_DATA14_MARK, DU1_DB3_C1_DATA13_MARK, DU1_DB2_C0_DATA12_MARK,
922};
923static const unsigned int du1_sync_pins[] = {
924 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
925 RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
926};
927static const unsigned int du1_sync_mux[] = {
928 DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
929};
930static const unsigned int du1_oddf_pins[] = {
931 /* EXODDF/ODDF/DISP/CDE */
932 RCAR_GP_PIN(1, 20),
933};
934static const unsigned int du1_oddf_mux[] = {
935 DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK
936};
937static const unsigned int du1_disp_pins[] = {
938 /* DISP */
939 RCAR_GP_PIN(1, 21),
940};
941static const unsigned int du1_disp_mux[] = {
942 DU1_DISP_MARK,
943};
944static const unsigned int du1_cde_pins[] = {
945 /* CDE */
946 RCAR_GP_PIN(1, 22),
947};
948static const unsigned int du1_cde_mux[] = {
949 DU1_CDE_MARK,
950};
951/* - INTC ------------------------------------------------------------------- */
952static const unsigned int intc_irq0_pins[] = {
953 /* IRQ0 */
954 RCAR_GP_PIN(3, 19),
955};
956static const unsigned int intc_irq0_mux[] = {
957 IRQ0_MARK,
958};
959static const unsigned int intc_irq1_pins[] = {
960 /* IRQ1 */
961 RCAR_GP_PIN(3, 20),
962};
963static const unsigned int intc_irq1_mux[] = {
964 IRQ1_MARK,
965};
966static const unsigned int intc_irq2_pins[] = {
967 /* IRQ2 */
968 RCAR_GP_PIN(3, 21),
969};
970static const unsigned int intc_irq2_mux[] = {
971 IRQ2_MARK,
972};
973static const unsigned int intc_irq3_pins[] = {
974 /* IRQ3 */
975 RCAR_GP_PIN(3, 22),
976};
977static const unsigned int intc_irq3_mux[] = {
978 IRQ3_MARK,
979};
980/* - LBSC ------------------------------------------------------------------- */
981static const unsigned int lbsc_cs0_pins[] = {
982 /* CS0# */
983 RCAR_GP_PIN(3, 27),
984};
985static const unsigned int lbsc_cs0_mux[] = {
986 CS0_N_MARK,
987};
988static const unsigned int lbsc_cs1_pins[] = {
989 /* CS1#_A26 */
990 RCAR_GP_PIN(3, 6),
991};
992static const unsigned int lbsc_cs1_mux[] = {
993 CS1_N_A26_MARK,
994};
995static const unsigned int lbsc_ex_cs0_pins[] = {
996 /* EX_CS0# */
997 RCAR_GP_PIN(3, 7),
998};
999static const unsigned int lbsc_ex_cs0_mux[] = {
1000 EX_CS0_N_MARK,
1001};
1002static const unsigned int lbsc_ex_cs1_pins[] = {
1003 /* EX_CS1# */
1004 RCAR_GP_PIN(3, 8),
1005};
1006static const unsigned int lbsc_ex_cs1_mux[] = {
1007 EX_CS1_N_MARK,
1008};
1009static const unsigned int lbsc_ex_cs2_pins[] = {
1010 /* EX_CS2# */
1011 RCAR_GP_PIN(3, 9),
1012};
1013static const unsigned int lbsc_ex_cs2_mux[] = {
1014 EX_CS2_N_MARK,
1015};
1016static const unsigned int lbsc_ex_cs3_pins[] = {
1017 /* EX_CS3# */
1018 RCAR_GP_PIN(3, 10),
1019};
1020static const unsigned int lbsc_ex_cs3_mux[] = {
1021 EX_CS3_N_MARK,
1022};
1023static const unsigned int lbsc_ex_cs4_pins[] = {
1024 /* EX_CS4# */
1025 RCAR_GP_PIN(3, 11),
1026};
1027static const unsigned int lbsc_ex_cs4_mux[] = {
1028 EX_CS4_N_MARK,
1029};
1030static const unsigned int lbsc_ex_cs5_pins[] = {
1031 /* EX_CS5# */
1032 RCAR_GP_PIN(3, 12),
1033};
1034static const unsigned int lbsc_ex_cs5_mux[] = {
1035 EX_CS5_N_MARK,
1036};
1037/* - SCIF0 ------------------------------------------------------------------ */
1038static const unsigned int scif0_data_pins[] = {
1039 /* RX, TX */
1040 RCAR_GP_PIN(10, 14), RCAR_GP_PIN(10, 13),
1041};
1042static const unsigned int scif0_data_mux[] = {
1043 RX0_MARK, TX0_MARK,
1044};
1045static const unsigned int scif0_clk_pins[] = {
1046 /* SCK */
1047 RCAR_GP_PIN(10, 10),
1048};
1049static const unsigned int scif0_clk_mux[] = {
1050 SCK0_MARK,
1051};
1052static const unsigned int scif0_ctrl_pins[] = {
1053 /* RTS, CTS */
1054 RCAR_GP_PIN(10, 12), RCAR_GP_PIN(10, 11),
1055};
1056static const unsigned int scif0_ctrl_mux[] = {
1057 RTS0_N_MARK, CTS0_N_MARK,
1058};
1059/* - SCIF3 ------------------------------------------------------------------ */
1060static const unsigned int scif3_data_pins[] = {
1061 /* RX, TX */
1062 RCAR_GP_PIN(10, 25), RCAR_GP_PIN(10, 24),
1063};
1064static const unsigned int scif3_data_mux[] = {
1065 RX3_MARK, TX3_MARK,
1066};
1067static const unsigned int scif3_clk_pins[] = {
1068 /* SCK */
1069 RCAR_GP_PIN(10, 23),
1070};
1071static const unsigned int scif3_clk_mux[] = {
1072 SCK3_MARK,
1073};
1074/* - SDHI0 ------------------------------------------------------------------ */
1075static const unsigned int sdhi0_data1_pins[] = {
1076 /* DAT0 */
1077 RCAR_GP_PIN(11, 7),
1078};
1079static const unsigned int sdhi0_data1_mux[] = {
1080 SD0_DAT0_MARK,
1081};
1082static const unsigned int sdhi0_data4_pins[] = {
1083 /* DAT[0-3] */
1084 RCAR_GP_PIN(11, 7), RCAR_GP_PIN(11, 8),
1085 RCAR_GP_PIN(11, 9), RCAR_GP_PIN(11, 10),
1086};
1087static const unsigned int sdhi0_data4_mux[] = {
1088 SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
1089};
1090static const unsigned int sdhi0_ctrl_pins[] = {
1091 /* CLK, CMD */
1092 RCAR_GP_PIN(11, 5), RCAR_GP_PIN(11, 6),
1093};
1094static const unsigned int sdhi0_ctrl_mux[] = {
1095 SD0_CLK_MARK, SD0_CMD_MARK,
1096};
1097static const unsigned int sdhi0_cd_pins[] = {
1098 /* CD */
1099 RCAR_GP_PIN(11, 11),
1100};
1101static const unsigned int sdhi0_cd_mux[] = {
1102 SD0_CD_MARK,
1103};
1104static const unsigned int sdhi0_wp_pins[] = {
1105 /* WP */
1106 RCAR_GP_PIN(11, 12),
1107};
1108static const unsigned int sdhi0_wp_mux[] = {
1109 SD0_WP_MARK,
1110};
1111/* - VIN0 ------------------------------------------------------------------- */
1112static const union vin_data vin0_data_pins = {
1113 .data24 = {
1114 /* B */
1115 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
1116 RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
1117 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
1118 RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
1119 /* G */
1120 RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 13),
1121 RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
1122 RCAR_GP_PIN(8, 1), RCAR_GP_PIN(8, 2),
1123 RCAR_GP_PIN(8, 3), RCAR_GP_PIN(8, 4),
1124 /* R */
1125 RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 6),
1126 RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8),
1127 RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 10),
1128 RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 12),
1129 },
1130};
1131static const union vin_data vin0_data_mux = {
1132 .data24 = {
1133 /* B */
1134 VI0_D0_B0_C0_MARK, VI0_D1_B1_C1_MARK,
1135 VI0_D2_B2_C2_MARK, VI0_D3_B3_C3_MARK,
1136 VI0_D4_B4_C4_MARK, VI0_D5_B5_C5_MARK,
1137 VI0_D6_B6_C6_MARK, VI0_D7_B7_C7_MARK,
1138 /* G */
1139 VI0_D8_G0_Y0_MARK, VI0_D9_G1_Y1_MARK,
1140 VI0_D10_G2_Y2_MARK, VI0_D11_G3_Y3_MARK,
1141 VI0_D12_G4_Y4_MARK, VI0_D13_G5_Y5_MARK,
1142 VI0_D14_G6_Y6_MARK, VI0_D15_G7_Y7_MARK,
1143 /* R */
1144 VI0_D16_R0_MARK, VI0_D17_R1_MARK,
1145 VI0_D18_R2_MARK, VI0_D19_R3_MARK,
1146 VI0_D20_R4_MARK, VI0_D21_R5_MARK,
1147 VI0_D22_R6_MARK, VI0_D23_R7_MARK,
1148 },
1149};
1150static const unsigned int vin0_data18_pins[] = {
1151 /* B */
1152 RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
1153 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
1154 RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
1155 /* G */
1156 RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
1157 RCAR_GP_PIN(8, 1), RCAR_GP_PIN(8, 2),
1158 RCAR_GP_PIN(8, 3), RCAR_GP_PIN(8, 4),
1159 /* R */
1160 RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8),
1161 RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 10),
1162 RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 12),
1163};
1164static const unsigned int vin0_data18_mux[] = {
1165 /* B */
1166 VI0_D2_B2_C2_MARK, VI0_D3_B3_C3_MARK,
1167 VI0_D4_B4_C4_MARK, VI0_D5_B5_C5_MARK,
1168 VI0_D6_B6_C6_MARK, VI0_D7_B7_C7_MARK,
1169 /* G */
1170 VI0_D10_G2_Y2_MARK, VI0_D11_G3_Y3_MARK,
1171 VI0_D12_G4_Y4_MARK, VI0_D13_G5_Y5_MARK,
1172 VI0_D14_G6_Y6_MARK, VI0_D15_G7_Y7_MARK,
1173 /* R */
1174 VI0_D18_R2_MARK, VI0_D19_R3_MARK,
1175 VI0_D20_R4_MARK, VI0_D21_R5_MARK,
1176 VI0_D22_R6_MARK, VI0_D23_R7_MARK,
1177};
1178static const unsigned int vin0_sync_pins[] = {
1179 /* HSYNC#, VSYNC# */
1180 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
1181};
1182static const unsigned int vin0_sync_mux[] = {
1183 VI0_HSYNC_N_MARK, VI0_VSYNC_N_MARK,
1184};
1185static const unsigned int vin0_field_pins[] = {
1186 RCAR_GP_PIN(4, 16),
1187};
1188static const unsigned int vin0_field_mux[] = {
1189 VI0_FIELD_MARK,
1190};
1191static const unsigned int vin0_clkenb_pins[] = {
1192 RCAR_GP_PIN(4, 1),
1193};
1194static const unsigned int vin0_clkenb_mux[] = {
1195 VI0_CLKENB_MARK,
1196};
1197static const unsigned int vin0_clk_pins[] = {
1198 RCAR_GP_PIN(4, 0),
1199};
1200static const unsigned int vin0_clk_mux[] = {
1201 VI0_CLK_MARK,
1202};
1203/* - VIN1 ------------------------------------------------------------------- */
1204static const union vin_data vin1_data_pins = {
1205 .data24 = {
1206 /* B */
1207 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
1208 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
1209 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
1210 RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
1211 /* G */
1212 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),
1213 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
1214 RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 6),
1215 RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8),
1216 /* R */
1217 RCAR_GP_PIN(9, 5), RCAR_GP_PIN(9, 6),
1218 RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8),
1219 RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10),
1220 RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12),
1221 },
1222};
1223static const union vin_data vin1_data_mux = {
1224 .data24 = {
1225 /* B */
1226 VI1_D0_B0_C0_MARK, VI1_D1_B1_C1_MARK,
1227 VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK,
1228 VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
1229 VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK,
1230 /* G */
1231 VI1_D8_G0_Y0_MARK, VI1_D9_G1_Y1_MARK,
1232 VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
1233 VI1_D12_G4_Y4_MARK, VI1_D13_G5_Y5_MARK,
1234 VI1_D14_G6_Y6_MARK, VI1_D15_G7_Y7_MARK,
1235 /* R */
1236 VI1_D16_R0_MARK, VI1_D17_R1_MARK,
1237 VI1_D18_R2_MARK, VI1_D19_R3_MARK,
1238 VI1_D20_R4_MARK, VI1_D21_R5_MARK,
1239 VI1_D22_R6_MARK, VI1_D23_R7_MARK,
1240 },
1241};
1242static const unsigned int vin1_data18_pins[] = {
1243 /* B */
1244 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
1245 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
1246 RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
1247 /* G */
1248 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
1249 RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 6),
1250 RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8),
1251 /* R */
1252 RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8),
1253 RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10),
1254 RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12),
1255};
1256static const unsigned int vin1_data18_mux[] = {
1257 /* B */
1258 VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK,
1259 VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
1260 VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK,
1261 /* G */
1262 VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
1263 VI1_D12_G4_Y4_MARK, VI1_D13_G5_Y5_MARK,
1264 VI1_D14_G6_Y6_MARK, VI1_D15_G7_Y7_MARK,
1265 /* R */
1266 VI1_D18_R2_MARK, VI1_D19_R3_MARK,
1267 VI1_D20_R4_MARK, VI1_D21_R5_MARK,
1268 VI1_D22_R6_MARK, VI1_D23_R7_MARK,
1269};
1270static const union vin_data vin1_data_b_pins = {
1271 .data24 = {
1272 /* B */
1273 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
1274 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
1275 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
1276 RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
1277 /* G */
1278 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),
1279 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
1280 RCAR_GP_PIN(9, 1), RCAR_GP_PIN(9, 2),
1281 RCAR_GP_PIN(9, 3), RCAR_GP_PIN(9, 4),
1282 /* R */
1283 RCAR_GP_PIN(9, 5), RCAR_GP_PIN(9, 6),
1284 RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8),
1285 RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10),
1286 RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12),
1287 },
1288};
1289static const union vin_data vin1_data_b_mux = {
1290 .data24 = {
1291 /* B */
1292 VI1_D0_B0_C0_MARK, VI1_D1_B1_C1_MARK,
1293 VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK,
1294 VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
1295 VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK,
1296 /* G */
1297 VI1_D8_G0_Y0_MARK, VI1_D9_G1_Y1_MARK,
1298 VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
1299 VI1_D12_G4_Y4_B_MARK, VI1_D13_G5_Y5_B_MARK,
1300 VI1_D14_G6_Y6_B_MARK, VI1_D15_G7_Y7_B_MARK,
1301 /* R */
1302 VI1_D16_R0_MARK, VI1_D17_R1_MARK,
1303 VI1_D18_R2_MARK, VI1_D19_R3_MARK,
1304 VI1_D20_R4_MARK, VI1_D21_R5_MARK,
1305 VI1_D22_R6_MARK, VI1_D23_R7_MARK,
1306 },
1307};
1308static const unsigned int vin1_data18_b_pins[] = {
1309 /* B */
1310 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
1311 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
1312 RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
1313 /* G */
1314 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
1315 RCAR_GP_PIN(9, 1), RCAR_GP_PIN(9, 2),
1316 RCAR_GP_PIN(9, 3), RCAR_GP_PIN(9, 4),
1317 /* R */
1318 RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8),
1319 RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10),
1320 RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12),
1321};
1322static const unsigned int vin1_data18_b_mux[] = {
1323 /* B */
1324 VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK,
1325 VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
1326 VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK,
1327 /* G */
1328 VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
1329 VI1_D12_G4_Y4_B_MARK, VI1_D13_G5_Y5_B_MARK,
1330 VI1_D14_G6_Y6_B_MARK, VI1_D15_G7_Y7_B_MARK,
1331 /* R */
1332 VI1_D18_R2_MARK, VI1_D19_R3_MARK,
1333 VI1_D20_R4_MARK, VI1_D21_R5_MARK,
1334 VI1_D22_R6_MARK, VI1_D23_R7_MARK,
1335};
1336static const unsigned int vin1_sync_pins[] = {
1337 /* HSYNC#, VSYNC# */
1338 RCAR_GP_PIN(5, 2), RCAR_GP_PIN(5, 3),
1339};
1340static const unsigned int vin1_sync_mux[] = {
1341 VI1_HSYNC_N_MARK, VI1_VSYNC_N_MARK,
1342};
1343static const unsigned int vin1_field_pins[] = {
1344 RCAR_GP_PIN(5, 16),
1345};
1346static const unsigned int vin1_field_mux[] = {
1347 VI1_FIELD_MARK,
1348};
1349static const unsigned int vin1_clkenb_pins[] = {
1350 RCAR_GP_PIN(5, 1),
1351};
1352static const unsigned int vin1_clkenb_mux[] = {
1353 VI1_CLKENB_MARK,
1354};
1355static const unsigned int vin1_clk_pins[] = {
1356 RCAR_GP_PIN(5, 0),
1357};
1358static const unsigned int vin1_clk_mux[] = {
1359 VI1_CLK_MARK,
1360};
1361/* - VIN2 ------------------------------------------------------------------- */
1362static const union vin_data vin2_data_pins = {
1363 .data16 = {
1364 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
1365 RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7),
1366 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1367 RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11),
1368 RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13),
1369 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
1370 RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 10),
1371 RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 12),
1372 },
1373};
1374static const union vin_data vin2_data_mux = {
1375 .data16 = {
1376 VI2_D0_C0_MARK, VI2_D1_C1_MARK,
1377 VI2_D2_C2_MARK, VI2_D3_C3_MARK,
1378 VI2_D4_C4_MARK, VI2_D5_C5_MARK,
1379 VI2_D6_C6_MARK, VI2_D7_C7_MARK,
1380 VI2_D8_Y0_MARK, VI2_D9_Y1_MARK,
1381 VI2_D10_Y2_MARK, VI2_D11_Y3_MARK,
1382 VI2_D12_Y4_MARK, VI2_D13_Y5_MARK,
1383 VI2_D14_Y6_MARK, VI2_D15_Y7_MARK,
1384 },
1385};
1386static const unsigned int vin2_sync_pins[] = {
1387 /* HSYNC#, VSYNC# */
1388 RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
1389};
1390static const unsigned int vin2_sync_mux[] = {
1391 VI2_HSYNC_N_MARK, VI2_VSYNC_N_MARK,
1392};
1393static const unsigned int vin2_field_pins[] = {
1394 RCAR_GP_PIN(6, 16),
1395};
1396static const unsigned int vin2_field_mux[] = {
1397 VI2_FIELD_MARK,
1398};
1399static const unsigned int vin2_clkenb_pins[] = {
1400 RCAR_GP_PIN(6, 1),
1401};
1402static const unsigned int vin2_clkenb_mux[] = {
1403 VI2_CLKENB_MARK,
1404};
1405static const unsigned int vin2_clk_pins[] = {
1406 RCAR_GP_PIN(6, 0),
1407};
1408static const unsigned int vin2_clk_mux[] = {
1409 VI2_CLK_MARK,
1410};
1411/* - VIN3 ------------------------------------------------------------------- */
1412static const union vin_data vin3_data_pins = {
1413 .data16 = {
1414 RCAR_GP_PIN(7, 4), RCAR_GP_PIN(7, 5),
1415 RCAR_GP_PIN(7, 6), RCAR_GP_PIN(7, 7),
1416 RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9),
1417 RCAR_GP_PIN(7, 10), RCAR_GP_PIN(7, 11),
1418 RCAR_GP_PIN(7, 12), RCAR_GP_PIN(7, 13),
1419 RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15),
1420 RCAR_GP_PIN(8, 13), RCAR_GP_PIN(8, 14),
1421 RCAR_GP_PIN(8, 15), RCAR_GP_PIN(8, 16),
1422 },
1423};
1424static const union vin_data vin3_data_mux = {
1425 .data16 = {
1426 VI3_D0_C0_MARK, VI3_D1_C1_MARK,
1427 VI3_D2_C2_MARK, VI3_D3_C3_MARK,
1428 VI3_D4_C4_MARK, VI3_D5_C5_MARK,
1429 VI3_D6_C6_MARK, VI3_D7_C7_MARK,
1430 VI3_D8_Y0_MARK, VI3_D9_Y1_MARK,
1431 VI3_D10_Y2_MARK, VI3_D11_Y3_MARK,
1432 VI3_D12_Y4_MARK, VI3_D13_Y5_MARK,
1433 VI3_D14_Y6_MARK, VI3_D15_Y7_MARK,
1434 },
1435};
1436static const unsigned int vin3_sync_pins[] = {
1437 /* HSYNC#, VSYNC# */
1438 RCAR_GP_PIN(7, 2), RCAR_GP_PIN(7, 3),
1439};
1440static const unsigned int vin3_sync_mux[] = {
1441 VI3_HSYNC_N_MARK, VI3_VSYNC_N_MARK,
1442};
1443static const unsigned int vin3_field_pins[] = {
1444 RCAR_GP_PIN(7, 16),
1445};
1446static const unsigned int vin3_field_mux[] = {
1447 VI3_FIELD_MARK,
1448};
1449static const unsigned int vin3_clkenb_pins[] = {
1450 RCAR_GP_PIN(7, 1),
1451};
1452static const unsigned int vin3_clkenb_mux[] = {
1453 VI3_CLKENB_MARK,
1454};
1455static const unsigned int vin3_clk_pins[] = {
1456 RCAR_GP_PIN(7, 0),
1457};
1458static const unsigned int vin3_clk_mux[] = {
1459 VI3_CLK_MARK,
1460};
1461/* - VIN4 ------------------------------------------------------------------- */
1462static const union vin_data vin4_data_pins = {
1463 .data12 = {
1464 RCAR_GP_PIN(8, 4), RCAR_GP_PIN(8, 5),
1465 RCAR_GP_PIN(8, 6), RCAR_GP_PIN(8, 7),
1466 RCAR_GP_PIN(8, 8), RCAR_GP_PIN(8, 9),
1467 RCAR_GP_PIN(8, 10), RCAR_GP_PIN(8, 11),
1468 RCAR_GP_PIN(8, 12), RCAR_GP_PIN(8, 13),
1469 RCAR_GP_PIN(8, 14), RCAR_GP_PIN(8, 15),
1470 },
1471};
1472static const union vin_data vin4_data_mux = {
1473 .data12 = {
1474 VI4_D0_C0_MARK, VI4_D1_C1_MARK,
1475 VI4_D2_C2_MARK, VI4_D3_C3_MARK,
1476 VI4_D4_C4_MARK, VI4_D5_C5_MARK,
1477 VI4_D6_C6_MARK, VI4_D7_C7_MARK,
1478 VI4_D8_Y0_MARK, VI4_D9_Y1_MARK,
1479 VI4_D10_Y2_MARK, VI4_D11_Y3_MARK,
1480 },
1481};
1482static const unsigned int vin4_sync_pins[] = {
1483 /* HSYNC#, VSYNC# */
1484 RCAR_GP_PIN(8, 2), RCAR_GP_PIN(8, 3),
1485};
1486static const unsigned int vin4_sync_mux[] = {
1487 VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
1488};
1489static const unsigned int vin4_field_pins[] = {
1490 RCAR_GP_PIN(8, 16),
1491};
1492static const unsigned int vin4_field_mux[] = {
1493 VI4_FIELD_MARK,
1494};
1495static const unsigned int vin4_clkenb_pins[] = {
1496 RCAR_GP_PIN(8, 1),
1497};
1498static const unsigned int vin4_clkenb_mux[] = {
1499 VI4_CLKENB_MARK,
1500};
1501static const unsigned int vin4_clk_pins[] = {
1502 RCAR_GP_PIN(8, 0),
1503};
1504static const unsigned int vin4_clk_mux[] = {
1505 VI4_CLK_MARK,
1506};
1507/* - VIN5 ------------------------------------------------------------------- */
1508static const union vin_data vin5_data_pins = {
1509 .data12 = {
1510 RCAR_GP_PIN(9, 4), RCAR_GP_PIN(9, 5),
1511 RCAR_GP_PIN(9, 6), RCAR_GP_PIN(9, 7),
1512 RCAR_GP_PIN(9, 8), RCAR_GP_PIN(9, 9),
1513 RCAR_GP_PIN(9, 10), RCAR_GP_PIN(9, 11),
1514 RCAR_GP_PIN(9, 12), RCAR_GP_PIN(9, 13),
1515 RCAR_GP_PIN(9, 14), RCAR_GP_PIN(9, 15),
1516 },
1517};
1518static const union vin_data vin5_data_mux = {
1519 .data12 = {
1520 VI5_D0_C0_MARK, VI5_D1_C1_MARK,
1521 VI5_D2_C2_MARK, VI5_D3_C3_MARK,
1522 VI5_D4_C4_MARK, VI5_D5_C5_MARK,
1523 VI5_D6_C6_MARK, VI5_D7_C7_MARK,
1524 VI5_D8_Y0_MARK, VI5_D9_Y1_MARK,
1525 VI5_D10_Y2_MARK, VI5_D11_Y3_MARK,
1526 },
1527};
1528static const unsigned int vin5_sync_pins[] = {
1529 /* HSYNC#, VSYNC# */
1530 RCAR_GP_PIN(9, 2), RCAR_GP_PIN(9, 3),
1531};
1532static const unsigned int vin5_sync_mux[] = {
1533 VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK,
1534};
1535static const unsigned int vin5_field_pins[] = {
1536 RCAR_GP_PIN(9, 16),
1537};
1538static const unsigned int vin5_field_mux[] = {
1539 VI5_FIELD_MARK,
1540};
1541static const unsigned int vin5_clkenb_pins[] = {
1542 RCAR_GP_PIN(9, 1),
1543};
1544static const unsigned int vin5_clkenb_mux[] = {
1545 VI5_CLKENB_MARK,
1546};
1547static const unsigned int vin5_clk_pins[] = {
1548 RCAR_GP_PIN(9, 0),
1549};
1550static const unsigned int vin5_clk_mux[] = {
1551 VI5_CLK_MARK,
1552};
1553
1554static const struct sh_pfc_pin_group pinmux_groups[] = {
1555 SH_PFC_PIN_GROUP(avb_link),
1556 SH_PFC_PIN_GROUP(avb_magic),
1557 SH_PFC_PIN_GROUP(avb_phy_int),
1558 SH_PFC_PIN_GROUP(avb_mdio),
1559 SH_PFC_PIN_GROUP(avb_mii),
1560 SH_PFC_PIN_GROUP(avb_gmii),
1561 SH_PFC_PIN_GROUP(avb_avtp_match),
1562 SH_PFC_PIN_GROUP(can0_data),
1563 SH_PFC_PIN_GROUP(can1_data),
1564 SH_PFC_PIN_GROUP(can_clk),
1565 SH_PFC_PIN_GROUP(du0_rgb666),
1566 SH_PFC_PIN_GROUP(du0_rgb888),
1567 SH_PFC_PIN_GROUP(du0_sync),
1568 SH_PFC_PIN_GROUP(du0_oddf),
1569 SH_PFC_PIN_GROUP(du0_disp),
1570 SH_PFC_PIN_GROUP(du0_cde),
1571 SH_PFC_PIN_GROUP(du1_rgb666),
1572 SH_PFC_PIN_GROUP(du1_sync),
1573 SH_PFC_PIN_GROUP(du1_oddf),
1574 SH_PFC_PIN_GROUP(du1_disp),
1575 SH_PFC_PIN_GROUP(du1_cde),
1576 SH_PFC_PIN_GROUP(intc_irq0),
1577 SH_PFC_PIN_GROUP(intc_irq1),
1578 SH_PFC_PIN_GROUP(intc_irq2),
1579 SH_PFC_PIN_GROUP(intc_irq3),
1580 SH_PFC_PIN_GROUP(lbsc_cs0),
1581 SH_PFC_PIN_GROUP(lbsc_cs1),
1582 SH_PFC_PIN_GROUP(lbsc_ex_cs0),
1583 SH_PFC_PIN_GROUP(lbsc_ex_cs1),
1584 SH_PFC_PIN_GROUP(lbsc_ex_cs2),
1585 SH_PFC_PIN_GROUP(lbsc_ex_cs3),
1586 SH_PFC_PIN_GROUP(lbsc_ex_cs4),
1587 SH_PFC_PIN_GROUP(lbsc_ex_cs5),
1588 SH_PFC_PIN_GROUP(scif0_data),
1589 SH_PFC_PIN_GROUP(scif0_clk),
1590 SH_PFC_PIN_GROUP(scif0_ctrl),
1591 SH_PFC_PIN_GROUP(scif3_data),
1592 SH_PFC_PIN_GROUP(scif3_clk),
1593 SH_PFC_PIN_GROUP(sdhi0_data1),
1594 SH_PFC_PIN_GROUP(sdhi0_data4),
1595 SH_PFC_PIN_GROUP(sdhi0_ctrl),
1596 SH_PFC_PIN_GROUP(sdhi0_cd),
1597 SH_PFC_PIN_GROUP(sdhi0_wp),
1598 VIN_DATA_PIN_GROUP(vin0_data, 24),
1599 VIN_DATA_PIN_GROUP(vin0_data, 20),
1600 SH_PFC_PIN_GROUP(vin0_data18),
1601 VIN_DATA_PIN_GROUP(vin0_data, 16),
1602 VIN_DATA_PIN_GROUP(vin0_data, 12),
1603 VIN_DATA_PIN_GROUP(vin0_data, 10),
1604 VIN_DATA_PIN_GROUP(vin0_data, 8),
1605 SH_PFC_PIN_GROUP(vin0_sync),
1606 SH_PFC_PIN_GROUP(vin0_field),
1607 SH_PFC_PIN_GROUP(vin0_clkenb),
1608 SH_PFC_PIN_GROUP(vin0_clk),
1609 VIN_DATA_PIN_GROUP(vin1_data, 24),
1610 VIN_DATA_PIN_GROUP(vin1_data, 20),
1611 SH_PFC_PIN_GROUP(vin1_data18),
1612 VIN_DATA_PIN_GROUP(vin1_data, 16),
1613 VIN_DATA_PIN_GROUP(vin1_data, 12),
1614 VIN_DATA_PIN_GROUP(vin1_data, 10),
1615 VIN_DATA_PIN_GROUP(vin1_data, 8),
1616 VIN_DATA_PIN_GROUP(vin1_data_b, 24),
1617 VIN_DATA_PIN_GROUP(vin1_data_b, 20),
1618 SH_PFC_PIN_GROUP(vin1_data18_b),
1619 VIN_DATA_PIN_GROUP(vin1_data_b, 16),
1620 SH_PFC_PIN_GROUP(vin1_sync),
1621 SH_PFC_PIN_GROUP(vin1_field),
1622 SH_PFC_PIN_GROUP(vin1_clkenb),
1623 SH_PFC_PIN_GROUP(vin1_clk),
1624 VIN_DATA_PIN_GROUP(vin2_data, 16),
1625 VIN_DATA_PIN_GROUP(vin2_data, 12),
1626 VIN_DATA_PIN_GROUP(vin2_data, 10),
1627 VIN_DATA_PIN_GROUP(vin2_data, 8),
1628 SH_PFC_PIN_GROUP(vin2_sync),
1629 SH_PFC_PIN_GROUP(vin2_field),
1630 SH_PFC_PIN_GROUP(vin2_clkenb),
1631 SH_PFC_PIN_GROUP(vin2_clk),
1632 VIN_DATA_PIN_GROUP(vin3_data, 16),
1633 VIN_DATA_PIN_GROUP(vin3_data, 12),
1634 VIN_DATA_PIN_GROUP(vin3_data, 10),
1635 VIN_DATA_PIN_GROUP(vin3_data, 8),
1636 SH_PFC_PIN_GROUP(vin3_sync),
1637 SH_PFC_PIN_GROUP(vin3_field),
1638 SH_PFC_PIN_GROUP(vin3_clkenb),
1639 SH_PFC_PIN_GROUP(vin3_clk),
1640 VIN_DATA_PIN_GROUP(vin4_data, 12),
1641 VIN_DATA_PIN_GROUP(vin4_data, 10),
1642 VIN_DATA_PIN_GROUP(vin4_data, 8),
1643 SH_PFC_PIN_GROUP(vin4_sync),
1644 SH_PFC_PIN_GROUP(vin4_field),
1645 SH_PFC_PIN_GROUP(vin4_clkenb),
1646 SH_PFC_PIN_GROUP(vin4_clk),
1647 VIN_DATA_PIN_GROUP(vin5_data, 12),
1648 VIN_DATA_PIN_GROUP(vin5_data, 10),
1649 VIN_DATA_PIN_GROUP(vin5_data, 8),
1650 SH_PFC_PIN_GROUP(vin5_sync),
1651 SH_PFC_PIN_GROUP(vin5_field),
1652 SH_PFC_PIN_GROUP(vin5_clkenb),
1653 SH_PFC_PIN_GROUP(vin5_clk),
1654};
1655
1656static const char * const avb_groups[] = {
1657 "avb_link",
1658 "avb_magic",
1659 "avb_phy_int",
1660 "avb_mdio",
1661 "avb_mii",
1662 "avb_gmii",
1663 "avb_avtp_match",
1664};
1665
1666static const char * const can0_groups[] = {
1667 "can0_data",
1668 "can_clk",
1669};
1670
1671static const char * const can1_groups[] = {
1672 "can1_data",
1673 "can_clk",
1674};
1675
1676static const char * const du0_groups[] = {
1677 "du0_rgb666",
1678 "du0_rgb888",
1679 "du0_sync",
1680 "du0_oddf",
1681 "du0_disp",
1682 "du0_cde",
1683};
1684
1685static const char * const du1_groups[] = {
1686 "du1_rgb666",
1687 "du1_sync",
1688 "du1_oddf",
1689 "du1_disp",
1690 "du1_cde",
1691};
1692
1693static const char * const intc_groups[] = {
1694 "intc_irq0",
1695 "intc_irq1",
1696 "intc_irq2",
1697 "intc_irq3",
1698};
1699
1700static const char * const lbsc_groups[] = {
1701 "lbsc_cs0",
1702 "lbsc_cs1",
1703 "lbsc_ex_cs0",
1704 "lbsc_ex_cs1",
1705 "lbsc_ex_cs2",
1706 "lbsc_ex_cs3",
1707 "lbsc_ex_cs4",
1708 "lbsc_ex_cs5",
1709};
1710
1711static const char * const scif0_groups[] = {
1712 "scif0_data",
1713 "scif0_clk",
1714 "scif0_ctrl",
1715};
1716
1717static const char * const scif3_groups[] = {
1718 "scif3_data",
1719 "scif3_clk",
1720};
1721
1722static const char * const sdhi0_groups[] = {
1723 "sdhi0_data1",
1724 "sdhi0_data4",
1725 "sdhi0_ctrl",
1726 "sdhi0_cd",
1727 "sdhi0_wp",
1728};
1729
1730static const char * const vin0_groups[] = {
1731 "vin0_data24",
1732 "vin0_data20",
1733 "vin0_data18",
1734 "vin0_data16",
1735 "vin0_data12",
1736 "vin0_data10",
1737 "vin0_data8",
1738 "vin0_sync",
1739 "vin0_field",
1740 "vin0_clkenb",
1741 "vin0_clk",
1742};
1743
1744static const char * const vin1_groups[] = {
1745 "vin1_data24",
1746 "vin1_data20",
1747 "vin1_data18",
1748 "vin1_data16",
1749 "vin1_data12",
1750 "vin1_data10",
1751 "vin1_data8",
1752 "vin1_data24_b",
1753 "vin1_data20_b",
1754 "vin1_data16_b",
1755 "vin1_sync",
1756 "vin1_field",
1757 "vin1_clkenb",
1758 "vin1_clk",
1759};
1760
1761static const char * const vin2_groups[] = {
1762 "vin2_data16",
1763 "vin2_data12",
1764 "vin2_data10",
1765 "vin2_data8",
1766 "vin2_sync",
1767 "vin2_field",
1768 "vin2_clkenb",
1769 "vin2_clk",
1770};
1771
1772static const char * const vin3_groups[] = {
1773 "vin3_data16",
1774 "vin3_data12",
1775 "vin3_data10",
1776 "vin3_data8",
1777 "vin3_sync",
1778 "vin3_field",
1779 "vin3_clkenb",
1780 "vin3_clk",
1781};
1782
1783static const char * const vin4_groups[] = {
1784 "vin4_data12",
1785 "vin4_data10",
1786 "vin4_data8",
1787 "vin4_sync",
1788 "vin4_field",
1789 "vin4_clkenb",
1790 "vin4_clk",
1791};
1792
1793static const char * const vin5_groups[] = {
1794 "vin5_data12",
1795 "vin5_data10",
1796 "vin5_data8",
1797 "vin5_sync",
1798 "vin5_field",
1799 "vin5_clkenb",
1800 "vin5_clk",
1801};
1802
1803static const struct sh_pfc_function pinmux_functions[] = {
1804 SH_PFC_FUNCTION(avb),
1805 SH_PFC_FUNCTION(can0),
1806 SH_PFC_FUNCTION(can1),
1807 SH_PFC_FUNCTION(du0),
1808 SH_PFC_FUNCTION(du1),
1809 SH_PFC_FUNCTION(intc),
1810 SH_PFC_FUNCTION(lbsc),
1811 SH_PFC_FUNCTION(scif0),
1812 SH_PFC_FUNCTION(scif3),
1813 SH_PFC_FUNCTION(sdhi0),
1814 SH_PFC_FUNCTION(vin0),
1815 SH_PFC_FUNCTION(vin1),
1816 SH_PFC_FUNCTION(vin2),
1817 SH_PFC_FUNCTION(vin3),
1818 SH_PFC_FUNCTION(vin4),
1819 SH_PFC_FUNCTION(vin5),
1820};
1821
1822static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1823 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
1824 0, 0,
1825 0, 0,
1826 0, 0,
1827 GP_0_28_FN, FN_IP1_4,
1828 GP_0_27_FN, FN_IP1_3,
1829 GP_0_26_FN, FN_IP1_2,
1830 GP_0_25_FN, FN_IP1_1,
1831 GP_0_24_FN, FN_IP1_0,
1832 GP_0_23_FN, FN_IP0_23,
1833 GP_0_22_FN, FN_IP0_22,
1834 GP_0_21_FN, FN_IP0_21,
1835 GP_0_20_FN, FN_IP0_20,
1836 GP_0_19_FN, FN_IP0_19,
1837 GP_0_18_FN, FN_IP0_18,
1838 GP_0_17_FN, FN_IP0_17,
1839 GP_0_16_FN, FN_IP0_16,
1840 GP_0_15_FN, FN_IP0_15,
1841 GP_0_14_FN, FN_IP0_14,
1842 GP_0_13_FN, FN_IP0_13,
1843 GP_0_12_FN, FN_IP0_12,
1844 GP_0_11_FN, FN_IP0_11,
1845 GP_0_10_FN, FN_IP0_10,
1846 GP_0_9_FN, FN_IP0_9,
1847 GP_0_8_FN, FN_IP0_8,
1848 GP_0_7_FN, FN_IP0_7,
1849 GP_0_6_FN, FN_IP0_6,
1850 GP_0_5_FN, FN_IP0_5,
1851 GP_0_4_FN, FN_IP0_4,
1852 GP_0_3_FN, FN_IP0_3,
1853 GP_0_2_FN, FN_IP0_2,
1854 GP_0_1_FN, FN_IP0_1,
1855 GP_0_0_FN, FN_IP0_0 }
1856 },
1857 { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
1858 0, 0,
1859 0, 0,
1860 0, 0,
1861 0, 0,
1862 0, 0,
1863 0, 0,
1864 0, 0,
1865 0, 0,
1866 0, 0,
1867 GP_1_22_FN, FN_DU1_CDE,
1868 GP_1_21_FN, FN_DU1_DISP,
1869 GP_1_20_FN, FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,
1870 GP_1_19_FN, FN_DU1_EXVSYNC_DU1_VSYNC,
1871 GP_1_18_FN, FN_DU1_EXHSYNC_DU1_HSYNC,
1872 GP_1_17_FN, FN_DU1_DB7_C5,
1873 GP_1_16_FN, FN_DU1_DB6_C4,
1874 GP_1_15_FN, FN_DU1_DB5_C3_DATA15,
1875 GP_1_14_FN, FN_DU1_DB4_C2_DATA14,
1876 GP_1_13_FN, FN_DU1_DB3_C1_DATA13,
1877 GP_1_12_FN, FN_DU1_DB2_C0_DATA12,
1878 GP_1_11_FN, FN_IP1_16,
1879 GP_1_10_FN, FN_IP1_15,
1880 GP_1_9_FN, FN_IP1_14,
1881 GP_1_8_FN, FN_IP1_13,
1882 GP_1_7_FN, FN_IP1_12,
1883 GP_1_6_FN, FN_IP1_11,
1884 GP_1_5_FN, FN_IP1_10,
1885 GP_1_4_FN, FN_IP1_9,
1886 GP_1_3_FN, FN_IP1_8,
1887 GP_1_2_FN, FN_IP1_7,
1888 GP_1_1_FN, FN_IP1_6,
1889 GP_1_0_FN, FN_IP1_5, }
1890 },
1891 { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
1892 GP_2_31_FN, FN_A15,
1893 GP_2_30_FN, FN_A14,
1894 GP_2_29_FN, FN_A13,
1895 GP_2_28_FN, FN_A12,
1896 GP_2_27_FN, FN_A11,
1897 GP_2_26_FN, FN_A10,
1898 GP_2_25_FN, FN_A9,
1899 GP_2_24_FN, FN_A8,
1900 GP_2_23_FN, FN_A7,
1901 GP_2_22_FN, FN_A6,
1902 GP_2_21_FN, FN_A5,
1903 GP_2_20_FN, FN_A4,
1904 GP_2_19_FN, FN_A3,
1905 GP_2_18_FN, FN_A2,
1906 GP_2_17_FN, FN_A1,
1907 GP_2_16_FN, FN_A0,
1908 GP_2_15_FN, FN_D15,
1909 GP_2_14_FN, FN_D14,
1910 GP_2_13_FN, FN_D13,
1911 GP_2_12_FN, FN_D12,
1912 GP_2_11_FN, FN_D11,
1913 GP_2_10_FN, FN_D10,
1914 GP_2_9_FN, FN_D9,
1915 GP_2_8_FN, FN_D8,
1916 GP_2_7_FN, FN_D7,
1917 GP_2_6_FN, FN_D6,
1918 GP_2_5_FN, FN_D5,
1919 GP_2_4_FN, FN_D4,
1920 GP_2_3_FN, FN_D3,
1921 GP_2_2_FN, FN_D2,
1922 GP_2_1_FN, FN_D1,
1923 GP_2_0_FN, FN_D0 }
1924 },
1925 { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
1926 0, 0,
1927 0, 0,
1928 0, 0,
1929 0, 0,
1930 GP_3_27_FN, FN_CS0_N,
1931 GP_3_26_FN, FN_IP1_22,
1932 GP_3_25_FN, FN_IP1_21,
1933 GP_3_24_FN, FN_IP1_20,
1934 GP_3_23_FN, FN_IP1_19,
1935 GP_3_22_FN, FN_IRQ3,
1936 GP_3_21_FN, FN_IRQ2,
1937 GP_3_20_FN, FN_IRQ1,
1938 GP_3_19_FN, FN_IRQ0,
1939 GP_3_18_FN, FN_EX_WAIT0,
1940 GP_3_17_FN, FN_WE1_N,
1941 GP_3_16_FN, FN_WE0_N,
1942 GP_3_15_FN, FN_RD_WR_N,
1943 GP_3_14_FN, FN_RD_N,
1944 GP_3_13_FN, FN_BS_N,
1945 GP_3_12_FN, FN_EX_CS5_N,
1946 GP_3_11_FN, FN_EX_CS4_N,
1947 GP_3_10_FN, FN_EX_CS3_N,
1948 GP_3_9_FN, FN_EX_CS2_N,
1949 GP_3_8_FN, FN_EX_CS1_N,
1950 GP_3_7_FN, FN_EX_CS0_N,
1951 GP_3_6_FN, FN_CS1_N_A26,
1952 GP_3_5_FN, FN_IP1_18,
1953 GP_3_4_FN, FN_IP1_17,
1954 GP_3_3_FN, FN_A19,
1955 GP_3_2_FN, FN_A18,
1956 GP_3_1_FN, FN_A17,
1957 GP_3_0_FN, FN_A16 }
1958 },
1959 { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
1960 0, 0,
1961 0, 0,
1962 0, 0,
1963 0, 0,
1964 0, 0,
1965 0, 0,
1966 0, 0,
1967 0, 0,
1968 0, 0,
1969 0, 0,
1970 0, 0,
1971 0, 0,
1972 0, 0,
1973 0, 0,
1974 0, 0,
1975 GP_4_16_FN, FN_VI0_FIELD,
1976 GP_4_15_FN, FN_VI0_D11_G3_Y3,
1977 GP_4_14_FN, FN_VI0_D10_G2_Y2,
1978 GP_4_13_FN, FN_VI0_D9_G1_Y1,
1979 GP_4_12_FN, FN_VI0_D8_G0_Y0,
1980 GP_4_11_FN, FN_VI0_D7_B7_C7,
1981 GP_4_10_FN, FN_VI0_D6_B6_C6,
1982 GP_4_9_FN, FN_VI0_D5_B5_C5,
1983 GP_4_8_FN, FN_VI0_D4_B4_C4,
1984 GP_4_7_FN, FN_VI0_D3_B3_C3,
1985 GP_4_6_FN, FN_VI0_D2_B2_C2,
1986 GP_4_5_FN, FN_VI0_D1_B1_C1,
1987 GP_4_4_FN, FN_VI0_D0_B0_C0,
1988 GP_4_3_FN, FN_VI0_VSYNC_N,
1989 GP_4_2_FN, FN_VI0_HSYNC_N,
1990 GP_4_1_FN, FN_VI0_CLKENB,
1991 GP_4_0_FN, FN_VI0_CLK }
1992 },
1993 { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
1994 0, 0,
1995 0, 0,
1996 0, 0,
1997 0, 0,
1998 0, 0,
1999 0, 0,
2000 0, 0,
2001 0, 0,
2002 0, 0,
2003 0, 0,
2004 0, 0,
2005 0, 0,
2006 0, 0,
2007 0, 0,
2008 0, 0,
2009 GP_5_16_FN, FN_VI1_FIELD,
2010 GP_5_15_FN, FN_VI1_D11_G3_Y3,
2011 GP_5_14_FN, FN_VI1_D10_G2_Y2,
2012 GP_5_13_FN, FN_VI1_D9_G1_Y1,
2013 GP_5_12_FN, FN_VI1_D8_G0_Y0,
2014 GP_5_11_FN, FN_VI1_D7_B7_C7,
2015 GP_5_10_FN, FN_VI1_D6_B6_C6,
2016 GP_5_9_FN, FN_VI1_D5_B5_C5,
2017 GP_5_8_FN, FN_VI1_D4_B4_C4,
2018 GP_5_7_FN, FN_VI1_D3_B3_C3,
2019 GP_5_6_FN, FN_VI1_D2_B2_C2,
2020 GP_5_5_FN, FN_VI1_D1_B1_C1,
2021 GP_5_4_FN, FN_VI1_D0_B0_C0,
2022 GP_5_3_FN, FN_VI1_VSYNC_N,
2023 GP_5_2_FN, FN_VI1_HSYNC_N,
2024 GP_5_1_FN, FN_VI1_CLKENB,
2025 GP_5_0_FN, FN_VI1_CLK }
2026 },
2027 { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) {
2028 0, 0,
2029 0, 0,
2030 0, 0,
2031 0, 0,
2032 0, 0,
2033 0, 0,
2034 0, 0,
2035 0, 0,
2036 0, 0,
2037 0, 0,
2038 0, 0,
2039 0, 0,
2040 0, 0,
2041 0, 0,
2042 0, 0,
2043 GP_6_16_FN, FN_IP2_16,
2044 GP_6_15_FN, FN_IP2_15,
2045 GP_6_14_FN, FN_IP2_14,
2046 GP_6_13_FN, FN_IP2_13,
2047 GP_6_12_FN, FN_IP2_12,
2048 GP_6_11_FN, FN_IP2_11,
2049 GP_6_10_FN, FN_IP2_10,
2050 GP_6_9_FN, FN_IP2_9,
2051 GP_6_8_FN, FN_IP2_8,
2052 GP_6_7_FN, FN_IP2_7,
2053 GP_6_6_FN, FN_IP2_6,
2054 GP_6_5_FN, FN_IP2_5,
2055 GP_6_4_FN, FN_IP2_4,
2056 GP_6_3_FN, FN_IP2_3,
2057 GP_6_2_FN, FN_IP2_2,
2058 GP_6_1_FN, FN_IP2_1,
2059 GP_6_0_FN, FN_IP2_0 }
2060 },
2061 { PINMUX_CFG_REG("GPSR7", 0xE6060020, 32, 1) {
2062 0, 0,
2063 0, 0,
2064 0, 0,
2065 0, 0,
2066 0, 0,
2067 0, 0,
2068 0, 0,
2069 0, 0,
2070 0, 0,
2071 0, 0,
2072 0, 0,
2073 0, 0,
2074 0, 0,
2075 0, 0,
2076 0, 0,
2077 GP_7_16_FN, FN_VI3_FIELD,
2078 GP_7_15_FN, FN_IP3_14,
2079 GP_7_14_FN, FN_VI3_D10_Y2,
2080 GP_7_13_FN, FN_IP3_13,
2081 GP_7_12_FN, FN_IP3_12,
2082 GP_7_11_FN, FN_IP3_11,
2083 GP_7_10_FN, FN_IP3_10,
2084 GP_7_9_FN, FN_IP3_9,
2085 GP_7_8_FN, FN_IP3_8,
2086 GP_7_7_FN, FN_IP3_7,
2087 GP_7_6_FN, FN_IP3_6,
2088 GP_7_5_FN, FN_IP3_5,
2089 GP_7_4_FN, FN_IP3_4,
2090 GP_7_3_FN, FN_IP3_3,
2091 GP_7_2_FN, FN_IP3_2,
2092 GP_7_1_FN, FN_IP3_1,
2093 GP_7_0_FN, FN_IP3_0 }
2094 },
2095 { PINMUX_CFG_REG("GPSR8", 0xE6060024, 32, 1) {
2096 0, 0,
2097 0, 0,
2098 0, 0,
2099 0, 0,
2100 0, 0,
2101 0, 0,
2102 0, 0,
2103 0, 0,
2104 0, 0,
2105 0, 0,
2106 0, 0,
2107 0, 0,
2108 0, 0,
2109 0, 0,
2110 0, 0,
2111 GP_8_16_FN, FN_IP4_24,
2112 GP_8_15_FN, FN_IP4_23,
2113 GP_8_14_FN, FN_IP4_22,
2114 GP_8_13_FN, FN_IP4_21,
2115 GP_8_12_FN, FN_IP4_20_19,
2116 GP_8_11_FN, FN_IP4_18_17,
2117 GP_8_10_FN, FN_IP4_16_15,
2118 GP_8_9_FN, FN_IP4_14_13,
2119 GP_8_8_FN, FN_IP4_12_11,
2120 GP_8_7_FN, FN_IP4_10_9,
2121 GP_8_6_FN, FN_IP4_8_7,
2122 GP_8_5_FN, FN_IP4_6_5,
2123 GP_8_4_FN, FN_IP4_4,
2124 GP_8_3_FN, FN_IP4_3_2,
2125 GP_8_2_FN, FN_IP4_1,
2126 GP_8_1_FN, FN_IP4_0,
2127 GP_8_0_FN, FN_VI4_CLK }
2128 },
2129 { PINMUX_CFG_REG("GPSR9", 0xE6060028, 32, 1) {
2130 0, 0,
2131 0, 0,
2132 0, 0,
2133 0, 0,
2134 0, 0,
2135 0, 0,
2136 0, 0,
2137 0, 0,
2138 0, 0,
2139 0, 0,
2140 0, 0,
2141 0, 0,
2142 0, 0,
2143 0, 0,
2144 0, 0,
2145 GP_9_16_FN, FN_VI5_FIELD,
2146 GP_9_15_FN, FN_VI5_D11_Y3,
2147 GP_9_14_FN, FN_VI5_D10_Y2,
2148 GP_9_13_FN, FN_VI5_D9_Y1,
2149 GP_9_12_FN, FN_IP5_11,
2150 GP_9_11_FN, FN_IP5_10,
2151 GP_9_10_FN, FN_IP5_9,
2152 GP_9_9_FN, FN_IP5_8,
2153 GP_9_8_FN, FN_IP5_7,
2154 GP_9_7_FN, FN_IP5_6,
2155 GP_9_6_FN, FN_IP5_5,
2156 GP_9_5_FN, FN_IP5_4,
2157 GP_9_4_FN, FN_IP5_3,
2158 GP_9_3_FN, FN_IP5_2,
2159 GP_9_2_FN, FN_IP5_1,
2160 GP_9_1_FN, FN_IP5_0,
2161 GP_9_0_FN, FN_VI5_CLK }
2162 },
2163 { PINMUX_CFG_REG("GPSR10", 0xE606002C, 32, 1) {
2164 GP_10_31_FN, FN_CAN1_RX,
2165 GP_10_30_FN, FN_CAN1_TX,
2166 GP_10_29_FN, FN_CAN_CLK,
2167 GP_10_28_FN, FN_CAN0_RX,
2168 GP_10_27_FN, FN_CAN0_TX,
2169 GP_10_26_FN, FN_SCIF_CLK,
2170 GP_10_25_FN, FN_IP6_18_17,
2171 GP_10_24_FN, FN_IP6_16,
2172 GP_10_23_FN, FN_IP6_15_14,
2173 GP_10_22_FN, FN_IP6_13_12,
2174 GP_10_21_FN, FN_IP6_11_10,
2175 GP_10_20_FN, FN_IP6_9_8,
2176 GP_10_19_FN, FN_RX1,
2177 GP_10_18_FN, FN_TX1,
2178 GP_10_17_FN, FN_RTS1_N,
2179 GP_10_16_FN, FN_CTS1_N,
2180 GP_10_15_FN, FN_SCK1,
2181 GP_10_14_FN, FN_RX0,
2182 GP_10_13_FN, FN_TX0,
2183 GP_10_12_FN, FN_RTS0_N,
2184 GP_10_11_FN, FN_CTS0_N,
2185 GP_10_10_FN, FN_SCK0,
2186 GP_10_9_FN, FN_IP6_7,
2187 GP_10_8_FN, FN_IP6_6,
2188 GP_10_7_FN, FN_HCTS1_N,
2189 GP_10_6_FN, FN_IP6_5,
2190 GP_10_5_FN, FN_IP6_4,
2191 GP_10_4_FN, FN_IP6_3,
2192 GP_10_3_FN, FN_IP6_2,
2193 GP_10_2_FN, FN_HRTS0_N,
2194 GP_10_1_FN, FN_IP6_1,
2195 GP_10_0_FN, FN_IP6_0 }
2196 },
2197 { PINMUX_CFG_REG("GPSR11", 0xE6060030, 32, 1) {
2198 0, 0,
2199 0, 0,
2200 GP_11_29_FN, FN_AVS2,
2201 GP_11_28_FN, FN_AVS1,
2202 GP_11_27_FN, FN_ADICHS2,
2203 GP_11_26_FN, FN_ADICHS1,
2204 GP_11_25_FN, FN_ADICHS0,
2205 GP_11_24_FN, FN_ADIDATA,
2206 GP_11_23_FN, FN_ADICS_SAMP,
2207 GP_11_22_FN, FN_ADICLK,
2208 GP_11_21_FN, FN_IP7_20,
2209 GP_11_20_FN, FN_IP7_19,
2210 GP_11_19_FN, FN_IP7_18,
2211 GP_11_18_FN, FN_IP7_17,
2212 GP_11_17_FN, FN_IP7_16,
2213 GP_11_16_FN, FN_IP7_15_14,
2214 GP_11_15_FN, FN_IP7_13_12,
2215 GP_11_14_FN, FN_IP7_11_10,
2216 GP_11_13_FN, FN_IP7_9_8,
2217 GP_11_12_FN, FN_SD0_WP,
2218 GP_11_11_FN, FN_SD0_CD,
2219 GP_11_10_FN, FN_SD0_DAT3,
2220 GP_11_9_FN, FN_SD0_DAT2,
2221 GP_11_8_FN, FN_SD0_DAT1,
2222 GP_11_7_FN, FN_SD0_DAT0,
2223 GP_11_6_FN, FN_SD0_CMD,
2224 GP_11_5_FN, FN_SD0_CLK,
2225 GP_11_4_FN, FN_IP7_7,
2226 GP_11_3_FN, FN_IP7_6,
2227 GP_11_2_FN, FN_IP7_5_4,
2228 GP_11_1_FN, FN_IP7_3_2,
2229 GP_11_0_FN, FN_IP7_1_0 }
2230 },
2231 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060040, 32,
2232 4, 4,
2233 1, 1, 1, 1, 1, 1, 1, 1,
2234 1, 1, 1, 1, 1, 1, 1, 1,
2235 1, 1, 1, 1, 1, 1, 1, 1) {
2236 /* IP0_31_28 [4] */
2237 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2238 /* IP0_27_24 [4] */
2239 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2240 /* IP0_23 [1] */
2241 FN_DU0_DB7_C5, 0,
2242 /* IP0_22 [1] */
2243 FN_DU0_DB6_C4, 0,
2244 /* IP0_21 [1] */
2245 FN_DU0_DB5_C3, 0,
2246 /* IP0_20 [1] */
2247 FN_DU0_DB4_C2, 0,
2248 /* IP0_19 [1] */
2249 FN_DU0_DB3_C1, 0,
2250 /* IP0_18 [1] */
2251 FN_DU0_DB2_C0, 0,
2252 /* IP0_17 [1] */
2253 FN_DU0_DB1, 0,
2254 /* IP0_16 [1] */
2255 FN_DU0_DB0, 0,
2256 /* IP0_15 [1] */
2257 FN_DU0_DG7_Y3_DATA15, 0,
2258 /* IP0_14 [1] */
2259 FN_DU0_DG6_Y2_DATA14, 0,
2260 /* IP0_13 [1] */
2261 FN_DU0_DG5_Y1_DATA13, 0,
2262 /* IP0_12 [1] */
2263 FN_DU0_DG4_Y0_DATA12, 0,
2264 /* IP0_11 [1] */
2265 FN_DU0_DG3_C7_DATA11, 0,
2266 /* IP0_10 [1] */
2267 FN_DU0_DG2_C6_DATA10, 0,
2268 /* IP0_9 [1] */
2269 FN_DU0_DG1_DATA9, 0,
2270 /* IP0_8 [1] */
2271 FN_DU0_DG0_DATA8, 0,
2272 /* IP0_7 [1] */
2273 FN_DU0_DR7_Y9_DATA7, 0,
2274 /* IP0_6 [1] */
2275 FN_DU0_DR6_Y8_DATA6, 0,
2276 /* IP0_5 [1] */
2277 FN_DU0_DR5_Y7_DATA5, 0,
2278 /* IP0_4 [1] */
2279 FN_DU0_DR4_Y6_DATA4, 0,
2280 /* IP0_3 [1] */
2281 FN_DU0_DR3_Y5_DATA3, 0,
2282 /* IP0_2 [1] */
2283 FN_DU0_DR2_Y4_DATA2, 0,
2284 /* IP0_1 [1] */
2285 FN_DU0_DR1_DATA1, 0,
2286 /* IP0_0 [1] */
2287 FN_DU0_DR0_DATA0, 0 }
2288 },
2289 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060044, 32,
2290 4, 4,
2291 1, 1, 1, 1, 1, 1, 1, 1,
2292 1, 1, 1, 1, 1, 1, 1, 1,
2293 1, 1, 1, 1, 1, 1, 1, 1) {
2294 /* IP1_31_28 [4] */
2295 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2296 /* IP1_27_24 [4] */
2297 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2298 /* IP1_23 [1] */
2299 0, 0,
2300 /* IP1_22 [1] */
2301 FN_A25, FN_SSL,
2302 /* IP1_21 [1] */
2303 FN_A24, FN_SPCLK,
2304 /* IP1_20 [1] */
2305 FN_A23, FN_IO3,
2306 /* IP1_19 [1] */
2307 FN_A22, FN_IO2,
2308 /* IP1_18 [1] */
2309 FN_A21, FN_MISO_IO1,
2310 /* IP1_17 [1] */
2311 FN_A20, FN_MOSI_IO0,
2312 /* IP1_16 [1] */
2313 FN_DU1_DG7_Y3_DATA11, 0,
2314 /* IP1_15 [1] */
2315 FN_DU1_DG6_Y2_DATA10, 0,
2316 /* IP1_14 [1] */
2317 FN_DU1_DG5_Y1_DATA9, 0,
2318 /* IP1_13 [1] */
2319 FN_DU1_DG4_Y0_DATA8, 0,
2320 /* IP1_12 [1] */
2321 FN_DU1_DG3_C7_DATA7, 0,
2322 /* IP1_11 [1] */
2323 FN_DU1_DG2_C6_DATA6, 0,
2324 /* IP1_10 [1] */
2325 FN_DU1_DR7_DATA5, 0,
2326 /* IP1_9 [1] */
2327 FN_DU1_DR6_DATA4, 0,
2328 /* IP1_8 [1] */
2329 FN_DU1_DR5_Y7_DATA3, 0,
2330 /* IP1_7 [1] */
2331 FN_DU1_DR4_Y6_DATA2, 0,
2332 /* IP1_6 [1] */
2333 FN_DU1_DR3_Y5_DATA1, 0,
2334 /* IP1_5 [1] */
2335 FN_DU1_DR2_Y4_DATA0, 0,
2336 /* IP1_4 [1] */
2337 FN_DU0_CDE, 0,
2338 /* IP1_3 [1] */
2339 FN_DU0_DISP, 0,
2340 /* IP1_2 [1] */
2341 FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, 0,
2342 /* IP1_1 [1] */
2343 FN_DU0_EXVSYNC_DU0_VSYNC, 0,
2344 /* IP1_0 [1] */
2345 FN_DU0_EXHSYNC_DU0_HSYNC, 0 }
2346 },
2347 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060048, 32,
2348 4, 4,
2349 4, 3, 1,
2350 1, 1, 1, 1, 1, 1, 1, 1,
2351 1, 1, 1, 1, 1, 1, 1, 1) {
2352 /* IP2_31_28 [4] */
2353 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2354 /* IP2_27_24 [4] */
2355 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2356 /* IP2_23_20 [4] */
2357 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2358 /* IP2_19_17 [3] */
2359 0, 0, 0, 0, 0, 0, 0, 0,
2360 /* IP2_16 [1] */
2361 FN_VI2_FIELD, FN_AVB_TXD2,
2362 /* IP2_15 [1] */
2363 FN_VI2_D11_Y3, FN_AVB_TXD1,
2364 /* IP2_14 [1] */
2365 FN_VI2_D10_Y2, FN_AVB_TXD0,
2366 /* IP2_13 [1] */
2367 FN_VI2_D9_Y1, FN_AVB_TX_EN,
2368 /* IP2_12 [1] */
2369 FN_VI2_D8_Y0, FN_AVB_TXD3,
2370 /* IP2_11 [1] */
2371 FN_VI2_D7_C7, FN_AVB_COL,
2372 /* IP2_10 [1] */
2373 FN_VI2_D6_C6, FN_AVB_RX_ER,
2374 /* IP2_9 [1] */
2375 FN_VI2_D5_C5, FN_AVB_RXD7,
2376 /* IP2_8 [1] */
2377 FN_VI2_D4_C4, FN_AVB_RXD6,
2378 /* IP2_7 [1] */
2379 FN_VI2_D3_C3, FN_AVB_RXD5,
2380 /* IP2_6 [1] */
2381 FN_VI2_D2_C2, FN_AVB_RXD4,
2382 /* IP2_5 [1] */
2383 FN_VI2_D1_C1, FN_AVB_RXD3,
2384 /* IP2_4 [1] */
2385 FN_VI2_D0_C0, FN_AVB_RXD2,
2386 /* IP2_3 [1] */
2387 FN_VI2_VSYNC_N, FN_AVB_RXD1,
2388 /* IP2_2 [1] */
2389 FN_VI2_HSYNC_N, FN_AVB_RXD0,
2390 /* IP2_1 [1] */
2391 FN_VI2_CLKENB, FN_AVB_RX_DV,
2392 /* IP2_0 [1] */
2393 FN_VI2_CLK, FN_AVB_RX_CLK }
2394 },
2395 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606004C, 32,
2396 4, 4,
2397 4, 4,
2398 1, 1, 1, 1, 1, 1, 1, 1,
2399 1, 1, 1, 1, 1, 1, 1, 1) {
2400 /* IP3_31_28 [4] */
2401 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2402 /* IP3_27_24 [4] */
2403 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2404 /* IP3_23_20 [4] */
2405 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2406 /* IP3_19_16 [4] */
2407 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2408 /* IP3_15 [1] */
2409 0, 0,
2410 /* IP3_14 [1] */
2411 FN_VI3_D11_Y3, FN_AVB_AVTP_MATCH,
2412 /* IP3_13 [1] */
2413 FN_VI3_D9_Y1, FN_AVB_GTXREFCLK,
2414 /* IP3_12 [1] */
2415 FN_VI3_D8_Y0, FN_AVB_CRS,
2416 /* IP3_11 [1] */
2417 FN_VI3_D7_C7, FN_AVB_PHY_INT,
2418 /* IP3_10 [1] */
2419 FN_VI3_D6_C6, FN_AVB_MAGIC,
2420 /* IP3_9 [1] */
2421 FN_VI3_D5_C5, FN_AVB_LINK,
2422 /* IP3_8 [1] */
2423 FN_VI3_D4_C4, FN_AVB_MDIO,
2424 /* IP3_7 [1] */
2425 FN_VI3_D3_C3, FN_AVB_MDC,
2426 /* IP3_6 [1] */
2427 FN_VI3_D2_C2, FN_AVB_GTX_CLK,
2428 /* IP3_5 [1] */
2429 FN_VI3_D1_C1, FN_AVB_TX_ER,
2430 /* IP3_4 [1] */
2431 FN_VI3_D0_C0, FN_AVB_TXD7,
2432 /* IP3_3 [1] */
2433 FN_VI3_VSYNC_N, FN_AVB_TXD6,
2434 /* IP3_2 [1] */
2435 FN_VI3_HSYNC_N, FN_AVB_TXD5,
2436 /* IP3_1 [1] */
2437 FN_VI3_CLKENB, FN_AVB_TXD4,
2438 /* IP3_0 [1] */
2439 FN_VI3_CLK, FN_AVB_TX_CLK }
2440 },
2441 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060050, 32,
2442 4, 3, 1,
2443 1, 1, 1, 2, 2, 2,
2444 2, 2, 2, 2, 2, 1, 2, 1, 1) {
2445 /* IP4_31_28 [4] */
2446 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2447 /* IP4_27_25 [3] */
2448 0, 0, 0, 0, 0, 0, 0, 0,
2449 /* IP4_24 [1] */
2450 FN_VI4_FIELD, FN_VI3_D15_Y7,
2451 /* IP4_23 [1] */
2452 FN_VI4_D11_Y3, FN_VI3_D14_Y6,
2453 /* IP4_22 [1] */
2454 FN_VI4_D10_Y2, FN_VI3_D13_Y5,
2455 /* IP4_21 [1] */
2456 FN_VI4_D9_Y1, FN_VI3_D12_Y4,
2457 /* IP4_20_19 [2] */
2458 FN_VI4_D8_Y0, FN_VI0_D23_R7, FN_VI2_D15_Y7, 0,
2459 /* IP4_18_17 [2] */
2460 FN_VI4_D7_C7, FN_VI0_D22_R6, FN_VI2_D14_Y6, 0,
2461 /* IP4_16_15 [2] */
2462 FN_VI4_D6_C6, FN_VI0_D21_R5, FN_VI2_D13_Y5, 0,
2463 /* IP4_14_13 [2] */
2464 FN_VI4_D5_C5, FN_VI0_D20_R4, FN_VI2_D12_Y4, 0,
2465 /* IP4_12_11 [2] */
2466 FN_VI4_D4_C4, FN_VI0_D19_R3, FN_VI1_D15_G7_Y7, 0,
2467 /* IP4_10_9 [2] */
2468 FN_VI4_D3_C3, FN_VI0_D18_R2, FN_VI1_D14_G6_Y6, 0,
2469 /* IP4_8_7 [2] */
2470 FN_VI4_D2_C2, 0, FN_VI0_D17_R1, FN_VI1_D13_G5_Y5,
2471 /* IP4_6_5 [2] */
2472 FN_VI4_D1_C1, FN_VI0_D16_R0, FN_VI1_D12_G4_Y4, 0,
2473 /* IP4_4 [1] */
2474 FN_VI4_D0_C0, FN_VI0_D15_G7_Y7,
2475 /* IP4_3_2 [2] */
2476 FN_VI4_VSYNC_N, FN_VI0_D14_G6_Y6, 0, 0,
2477 /* IP4_1 [1] */
2478 FN_VI4_HSYNC_N, FN_VI0_D13_G5_Y5,
2479 /* IP4_0 [1] */
2480 FN_VI4_CLKENB, FN_VI0_D12_G4_Y4 }
2481 },
2482 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060054, 32,
2483 4, 4,
2484 4, 4,
2485 4, 1, 1, 1, 1,
2486 1, 1, 1, 1, 1, 1, 1, 1) {
2487 /* IP5_31_28 [4] */
2488 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2489 /* IP5_27_24 [4] */
2490 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2491 /* IP5_23_20 [4] */
2492 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2493 /* IP5_19_16 [4] */
2494 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2495 /* IP5_15_12 [4] */
2496 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2497 /* IP5_11 [1] */
2498 FN_VI5_D8_Y0, FN_VI1_D23_R7,
2499 /* IP5_10 [1] */
2500 FN_VI5_D7_C7, FN_VI1_D22_R6,
2501 /* IP5_9 [1] */
2502 FN_VI5_D6_C6, FN_VI1_D21_R5,
2503 /* IP5_8 [1] */
2504 FN_VI5_D5_C5, FN_VI1_D20_R4,
2505 /* IP5_7 [1] */
2506 FN_VI5_D4_C4, FN_VI1_D19_R3,
2507 /* IP5_6 [1] */
2508 FN_VI5_D3_C3, FN_VI1_D18_R2,
2509 /* IP5_5 [1] */
2510 FN_VI5_D2_C2, FN_VI1_D17_R1,
2511 /* IP5_4 [1] */
2512 FN_VI5_D1_C1, FN_VI1_D16_R0,
2513 /* IP5_3 [1] */
2514 FN_VI5_D0_C0, FN_VI1_D15_G7_Y7_B,
2515 /* IP5_2 [1] */
2516 FN_VI5_VSYNC_N, FN_VI1_D14_G6_Y6_B,
2517 /* IP5_1 [1] */
2518 FN_VI5_HSYNC_N, FN_VI1_D13_G5_Y5_B,
2519 /* IP5_0 [1] */
2520 FN_VI5_CLKENB, FN_VI1_D12_G4_Y4_B }
2521 },
2522 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060058, 32,
2523 4, 4,
2524 4, 1, 2, 1,
2525 2, 2, 2, 2,
2526 1, 1, 1, 1, 1, 1, 1, 1) {
2527 /* IP6_31_28 [4] */
2528 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2529 /* IP6_27_24 [4] */
2530 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2531 /* IP6_23_20 [4] */
2532 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2533 /* IP6_19 [1] */
2534 0, 0,
2535 /* IP6_18_17 [2] */
2536 FN_DREQ1_N, FN_RX3, 0, 0,
2537 /* IP6_16 [1] */
2538 FN_TX3, 0,
2539 /* IP6_15_14 [2] */
2540 FN_DACK1, FN_SCK3, 0, 0,
2541 /* IP6_13_12 [2] */
2542 FN_DREQ0_N, FN_RX2, 0, 0,
2543 /* IP6_11_10 [2] */
2544 FN_DACK0, FN_TX2, 0, 0,
2545 /* IP6_9_8 [2] */
2546 FN_DRACK0, FN_SCK2, 0, 0,
2547 /* IP6_7 [1] */
2548 FN_MSIOF1_RXD, FN_HRX1,
2549 /* IP6_6 [1] */
2550 FN_MSIOF1_TXD, FN_HTX1,
2551 /* IP6_5 [1] */
2552 FN_MSIOF1_SYNC, FN_HRTS1_N,
2553 /* IP6_4 [1] */
2554 FN_MSIOF1_SCK, FN_HSCK1,
2555 /* IP6_3 [1] */
2556 FN_MSIOF0_RXD, FN_HRX0,
2557 /* IP6_2 [1] */
2558 FN_MSIOF0_TXD, FN_HTX0,
2559 /* IP6_1 [1] */
2560 FN_MSIOF0_SYNC, FN_HCTS0_N,
2561 /* IP6_0 [1] */
2562 FN_MSIOF0_SCK, FN_HSCK0 }
2563 },
2564 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606005C, 32,
2565 4, 4,
2566 3, 1, 1, 1, 1, 1,
2567 2, 2, 2, 2,
2568 1, 1, 2, 2, 2) {
2569 /* IP7_31_28 [4] */
2570 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2571 /* IP7_27_24 [4] */
2572 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2573 /* IP7_23_21 [3] */
2574 0, 0, 0, 0, 0, 0, 0, 0,
2575 /* IP7_20 [1] */
2576 FN_AUDIO_CLKB, 0,
2577 /* IP7_19 [1] */
2578 FN_AUDIO_CLKA, 0,
2579 /* IP7_18 [1] */
2580 FN_AUDIO_CLKOUT, 0,
2581 /* IP7_17 [1] */
2582 FN_SSI_SDATA4, 0,
2583 /* IP7_16 [1] */
2584 FN_SSI_WS4, 0,
2585 /* IP7_15_14 [2] */
2586 FN_SSI_SCK4, FN_TPU0TO3, 0, 0,
2587 /* IP7_13_12 [2] */
2588 FN_SSI_SDATA3, FN_TPU0TO2, 0, 0,
2589 /* IP7_11_10 [2] */
2590 FN_SSI_WS34, FN_TPU0TO1, 0, 0,
2591 /* IP7_9_8 [2] */
2592 FN_SSI_SCK34, FN_TPU0TO0, 0, 0,
2593 /* IP7_7 [1] */
2594 FN_PWM4, 0,
2595 /* IP7_6 [1] */
2596 FN_PWM3, 0,
2597 /* IP7_5_4 [2] */
2598 FN_PWM2, FN_TCLK3, FN_FSO_TOE, 0,
2599 /* IP7_3_2 [2] */
2600 FN_PWM1, FN_TCLK2, FN_FSO_CFE_1, 0,
2601 /* IP7_1_0 [2] */
2602 FN_PWM0, FN_TCLK1, FN_FSO_CFE_0, 0 }
2603 },
2604 { },
2605};
2606
2607const struct sh_pfc_soc_info r8a7792_pinmux_info = {
2608 .name = "r8a77920_pfc",
2609 .unlock_reg = 0xe6060000, /* PMMR */
2610
2611 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2612
2613 .pins = pinmux_pins,
2614 .nr_pins = ARRAY_SIZE(pinmux_pins),
2615 .groups = pinmux_groups,
2616 .nr_groups = ARRAY_SIZE(pinmux_groups),
2617 .functions = pinmux_functions,
2618 .nr_functions = ARRAY_SIZE(pinmux_functions),
2619
2620 .cfg_regs = pinmux_config_regs,
2621
2622 .pinmux_data = pinmux_data,
2623 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
2624};
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
index b74cdd310d83..2e8cc2adbed7 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * R-Car Gen3 processor support - PFC hardware block. 2 * R8A7795 processor support - PFC hardware block.
3 * 3 *
4 * Copyright (C) 2015 Renesas Electronics Corporation 4 * Copyright (C) 2015 Renesas Electronics Corporation
5 * 5 *
@@ -13,19 +13,23 @@
13#include "core.h" 13#include "core.h"
14#include "sh_pfc.h" 14#include "sh_pfc.h"
15 15
16#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \
17 SH_PFC_PIN_CFG_PULL_UP | \
18 SH_PFC_PIN_CFG_PULL_DOWN)
19
16#define CPU_ALL_PORT(fn, sfx) \ 20#define CPU_ALL_PORT(fn, sfx) \
17 PORT_GP_CFG_16(0, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \ 21 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
18 PORT_GP_CFG_28(1, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \ 22 PORT_GP_CFG_28(1, fn, sfx, CFG_FLAGS), \
19 PORT_GP_CFG_15(2, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \ 23 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
20 PORT_GP_CFG_12(3, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_IO_VOLTAGE), \ 24 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
21 PORT_GP_CFG_1(3, 12, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \ 25 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
22 PORT_GP_CFG_1(3, 13, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \ 26 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
23 PORT_GP_CFG_1(3, 14, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \ 27 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
24 PORT_GP_CFG_1(3, 15, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \ 28 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
25 PORT_GP_CFG_18(4, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_IO_VOLTAGE), \ 29 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
26 PORT_GP_CFG_26(5, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \ 30 PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
27 PORT_GP_CFG_32(6, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \ 31 PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
28 PORT_GP_CFG_4(7, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH) 32 PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
29/* 33/*
30 * F_() : just information 34 * F_() : just information
31 * FM() : macro for FN_xxx / xxx_MARK 35 * FM() : macro for FN_xxx / xxx_MARK
@@ -1871,6 +1875,86 @@ static const unsigned int drif3_data1_b_mux[] = {
1871 RIF3_D1_B_MARK, 1875 RIF3_D1_B_MARK,
1872}; 1876};
1873 1877
1878/* - DU --------------------------------------------------------------------- */
1879static const unsigned int du_rgb666_pins[] = {
1880 /* R[7:2], G[7:2], B[7:2] */
1881 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
1882 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
1883 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
1884 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
1885 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
1886 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
1887};
1888static const unsigned int du_rgb666_mux[] = {
1889 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
1890 DU_DR3_MARK, DU_DR2_MARK,
1891 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
1892 DU_DG3_MARK, DU_DG2_MARK,
1893 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
1894 DU_DB3_MARK, DU_DB2_MARK,
1895};
1896static const unsigned int du_rgb888_pins[] = {
1897 /* R[7:0], G[7:0], B[7:0] */
1898 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
1899 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
1900 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
1901 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
1902 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
1903 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
1904 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
1905 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
1906 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
1907};
1908static const unsigned int du_rgb888_mux[] = {
1909 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
1910 DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
1911 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
1912 DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
1913 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
1914 DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
1915};
1916static const unsigned int du_clk_out_0_pins[] = {
1917 /* CLKOUT */
1918 RCAR_GP_PIN(1, 27),
1919};
1920static const unsigned int du_clk_out_0_mux[] = {
1921 DU_DOTCLKOUT0_MARK
1922};
1923static const unsigned int du_clk_out_1_pins[] = {
1924 /* CLKOUT */
1925 RCAR_GP_PIN(2, 3),
1926};
1927static const unsigned int du_clk_out_1_mux[] = {
1928 DU_DOTCLKOUT1_MARK
1929};
1930static const unsigned int du_sync_pins[] = {
1931 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
1932 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
1933};
1934static const unsigned int du_sync_mux[] = {
1935 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
1936};
1937static const unsigned int du_oddf_pins[] = {
1938 /* EXDISP/EXODDF/EXCDE */
1939 RCAR_GP_PIN(2, 2),
1940};
1941static const unsigned int du_oddf_mux[] = {
1942 DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
1943};
1944static const unsigned int du_cde_pins[] = {
1945 /* CDE */
1946 RCAR_GP_PIN(2, 0),
1947};
1948static const unsigned int du_cde_mux[] = {
1949 DU_CDE_MARK,
1950};
1951static const unsigned int du_disp_pins[] = {
1952 /* DISP */
1953 RCAR_GP_PIN(2, 1),
1954};
1955static const unsigned int du_disp_mux[] = {
1956 DU_DISP_MARK,
1957};
1874/* - HSCIF0 ----------------------------------------------------------------- */ 1958/* - HSCIF0 ----------------------------------------------------------------- */
1875static const unsigned int hscif0_data_pins[] = { 1959static const unsigned int hscif0_data_pins[] = {
1876 /* RX, TX */ 1960 /* RX, TX */
@@ -3593,6 +3677,14 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
3593 SH_PFC_PIN_GROUP(drif3_ctrl_b), 3677 SH_PFC_PIN_GROUP(drif3_ctrl_b),
3594 SH_PFC_PIN_GROUP(drif3_data0_b), 3678 SH_PFC_PIN_GROUP(drif3_data0_b),
3595 SH_PFC_PIN_GROUP(drif3_data1_b), 3679 SH_PFC_PIN_GROUP(drif3_data1_b),
3680 SH_PFC_PIN_GROUP(du_rgb666),
3681 SH_PFC_PIN_GROUP(du_rgb888),
3682 SH_PFC_PIN_GROUP(du_clk_out_0),
3683 SH_PFC_PIN_GROUP(du_clk_out_1),
3684 SH_PFC_PIN_GROUP(du_sync),
3685 SH_PFC_PIN_GROUP(du_oddf),
3686 SH_PFC_PIN_GROUP(du_cde),
3687 SH_PFC_PIN_GROUP(du_disp),
3596 SH_PFC_PIN_GROUP(hscif0_data), 3688 SH_PFC_PIN_GROUP(hscif0_data),
3597 SH_PFC_PIN_GROUP(hscif0_clk), 3689 SH_PFC_PIN_GROUP(hscif0_clk),
3598 SH_PFC_PIN_GROUP(hscif0_ctrl), 3690 SH_PFC_PIN_GROUP(hscif0_ctrl),
@@ -3918,6 +4010,17 @@ static const char * const drif3_groups[] = {
3918 "drif3_data1_b", 4010 "drif3_data1_b",
3919}; 4011};
3920 4012
4013static const char * const du_groups[] = {
4014 "du_rgb666",
4015 "du_rgb888",
4016 "du_clk_out_0",
4017 "du_clk_out_1",
4018 "du_sync",
4019 "du_oddf",
4020 "du_cde",
4021 "du_disp",
4022};
4023
3921static const char * const hscif0_groups[] = { 4024static const char * const hscif0_groups[] = {
3922 "hscif0_data", 4025 "hscif0_data",
3923 "hscif0_clk", 4026 "hscif0_clk",
@@ -4265,6 +4368,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
4265 SH_PFC_FUNCTION(drif1), 4368 SH_PFC_FUNCTION(drif1),
4266 SH_PFC_FUNCTION(drif2), 4369 SH_PFC_FUNCTION(drif2),
4267 SH_PFC_FUNCTION(drif3), 4370 SH_PFC_FUNCTION(drif3),
4371 SH_PFC_FUNCTION(du),
4268 SH_PFC_FUNCTION(hscif0), 4372 SH_PFC_FUNCTION(hscif0),
4269 SH_PFC_FUNCTION(hscif1), 4373 SH_PFC_FUNCTION(hscif1),
4270 SH_PFC_FUNCTION(hscif2), 4374 SH_PFC_FUNCTION(hscif2),
@@ -5073,8 +5177,234 @@ static int r8a7795_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *poc
5073 return bit; 5177 return bit;
5074} 5178}
5075 5179
5180#define PUEN 0xe6060400
5181#define PUD 0xe6060440
5182
5183#define PU0 0x00
5184#define PU1 0x04
5185#define PU2 0x08
5186#define PU3 0x0c
5187#define PU4 0x10
5188#define PU5 0x14
5189#define PU6 0x18
5190
5191static const struct {
5192 u16 reg : 11;
5193 u16 bit : 5;
5194} pullups[] = {
5195 [RCAR_GP_PIN(2, 11)] = { PU0, 31 }, /* AVB_PHY_INT */
5196 [RCAR_GP_PIN(2, 10)] = { PU0, 30 }, /* AVB_MAGIC */
5197 [RCAR_GP_PIN(2, 9)] = { PU0, 29 }, /* AVB_MDC */
5198
5199 [RCAR_GP_PIN(1, 19)] = { PU1, 31 }, /* A19 */
5200 [RCAR_GP_PIN(1, 18)] = { PU1, 30 }, /* A18 */
5201 [RCAR_GP_PIN(1, 17)] = { PU1, 29 }, /* A17 */
5202 [RCAR_GP_PIN(1, 16)] = { PU1, 28 }, /* A16 */
5203 [RCAR_GP_PIN(1, 15)] = { PU1, 27 }, /* A15 */
5204 [RCAR_GP_PIN(1, 14)] = { PU1, 26 }, /* A14 */
5205 [RCAR_GP_PIN(1, 13)] = { PU1, 25 }, /* A13 */
5206 [RCAR_GP_PIN(1, 12)] = { PU1, 24 }, /* A12 */
5207 [RCAR_GP_PIN(1, 11)] = { PU1, 23 }, /* A11 */
5208 [RCAR_GP_PIN(1, 10)] = { PU1, 22 }, /* A10 */
5209 [RCAR_GP_PIN(1, 9)] = { PU1, 21 }, /* A9 */
5210 [RCAR_GP_PIN(1, 8)] = { PU1, 20 }, /* A8 */
5211 [RCAR_GP_PIN(1, 7)] = { PU1, 19 }, /* A7 */
5212 [RCAR_GP_PIN(1, 6)] = { PU1, 18 }, /* A6 */
5213 [RCAR_GP_PIN(1, 5)] = { PU1, 17 }, /* A5 */
5214 [RCAR_GP_PIN(1, 4)] = { PU1, 16 }, /* A4 */
5215 [RCAR_GP_PIN(1, 3)] = { PU1, 15 }, /* A3 */
5216 [RCAR_GP_PIN(1, 2)] = { PU1, 14 }, /* A2 */
5217 [RCAR_GP_PIN(1, 1)] = { PU1, 13 }, /* A1 */
5218 [RCAR_GP_PIN(1, 0)] = { PU1, 12 }, /* A0 */
5219 [RCAR_GP_PIN(2, 8)] = { PU1, 11 }, /* PWM2_A */
5220 [RCAR_GP_PIN(2, 7)] = { PU1, 10 }, /* PWM1_A */
5221 [RCAR_GP_PIN(2, 6)] = { PU1, 9 }, /* PWM0 */
5222 [RCAR_GP_PIN(2, 5)] = { PU1, 8 }, /* IRQ5 */
5223 [RCAR_GP_PIN(2, 4)] = { PU1, 7 }, /* IRQ4 */
5224 [RCAR_GP_PIN(2, 3)] = { PU1, 6 }, /* IRQ3 */
5225 [RCAR_GP_PIN(2, 2)] = { PU1, 5 }, /* IRQ2 */
5226 [RCAR_GP_PIN(2, 1)] = { PU1, 4 }, /* IRQ1 */
5227 [RCAR_GP_PIN(2, 0)] = { PU1, 3 }, /* IRQ0 */
5228 [RCAR_GP_PIN(2, 14)] = { PU1, 2 }, /* AVB_AVTP_CAPTURE_A */
5229 [RCAR_GP_PIN(2, 13)] = { PU1, 1 }, /* AVB_AVTP_MATCH_A */
5230 [RCAR_GP_PIN(2, 12)] = { PU1, 0 }, /* AVB_LINK */
5231
5232 [RCAR_GP_PIN(7, 3)] = { PU2, 29 }, /* HDMI1_CEC */
5233 [RCAR_GP_PIN(7, 2)] = { PU2, 28 }, /* HDMI0_CEC */
5234 [RCAR_GP_PIN(7, 1)] = { PU2, 27 }, /* AVS2 */
5235 [RCAR_GP_PIN(7, 0)] = { PU2, 26 }, /* AVS1 */
5236 [RCAR_GP_PIN(0, 15)] = { PU2, 25 }, /* D15 */
5237 [RCAR_GP_PIN(0, 14)] = { PU2, 24 }, /* D14 */
5238 [RCAR_GP_PIN(0, 13)] = { PU2, 23 }, /* D13 */
5239 [RCAR_GP_PIN(0, 12)] = { PU2, 22 }, /* D12 */
5240 [RCAR_GP_PIN(0, 11)] = { PU2, 21 }, /* D11 */
5241 [RCAR_GP_PIN(0, 10)] = { PU2, 20 }, /* D10 */
5242 [RCAR_GP_PIN(0, 9)] = { PU2, 19 }, /* D9 */
5243 [RCAR_GP_PIN(0, 8)] = { PU2, 18 }, /* D8 */
5244 [RCAR_GP_PIN(0, 7)] = { PU2, 17 }, /* D7 */
5245 [RCAR_GP_PIN(0, 6)] = { PU2, 16 }, /* D6 */
5246 [RCAR_GP_PIN(0, 5)] = { PU2, 15 }, /* D5 */
5247 [RCAR_GP_PIN(0, 4)] = { PU2, 14 }, /* D4 */
5248 [RCAR_GP_PIN(0, 3)] = { PU2, 13 }, /* D3 */
5249 [RCAR_GP_PIN(0, 2)] = { PU2, 12 }, /* D2 */
5250 [RCAR_GP_PIN(0, 1)] = { PU2, 11 }, /* D1 */
5251 [RCAR_GP_PIN(0, 0)] = { PU2, 10 }, /* D0 */
5252 [RCAR_GP_PIN(1, 27)] = { PU2, 8 }, /* EX_WAIT0_A */
5253 [RCAR_GP_PIN(1, 26)] = { PU2, 7 }, /* WE1_N */
5254 [RCAR_GP_PIN(1, 25)] = { PU2, 6 }, /* WE0_N */
5255 [RCAR_GP_PIN(1, 24)] = { PU2, 5 }, /* RD_WR_N */
5256 [RCAR_GP_PIN(1, 23)] = { PU2, 4 }, /* RD_N */
5257 [RCAR_GP_PIN(1, 22)] = { PU2, 3 }, /* BS_N */
5258 [RCAR_GP_PIN(1, 21)] = { PU2, 2 }, /* CS1_N_A26 */
5259 [RCAR_GP_PIN(1, 20)] = { PU2, 1 }, /* CS0_N */
5260
5261 [RCAR_GP_PIN(4, 9)] = { PU3, 31 }, /* SD3_DAT0 */
5262 [RCAR_GP_PIN(4, 8)] = { PU3, 30 }, /* SD3_CMD */
5263 [RCAR_GP_PIN(4, 7)] = { PU3, 29 }, /* SD3_CLK */
5264 [RCAR_GP_PIN(4, 6)] = { PU3, 28 }, /* SD2_DS */
5265 [RCAR_GP_PIN(4, 5)] = { PU3, 27 }, /* SD2_DAT3 */
5266 [RCAR_GP_PIN(4, 4)] = { PU3, 26 }, /* SD2_DAT2 */
5267 [RCAR_GP_PIN(4, 3)] = { PU3, 25 }, /* SD2_DAT1 */
5268 [RCAR_GP_PIN(4, 2)] = { PU3, 24 }, /* SD2_DAT0 */
5269 [RCAR_GP_PIN(4, 1)] = { PU3, 23 }, /* SD2_CMD */
5270 [RCAR_GP_PIN(4, 0)] = { PU3, 22 }, /* SD2_CLK */
5271 [RCAR_GP_PIN(3, 11)] = { PU3, 21 }, /* SD1_DAT3 */
5272 [RCAR_GP_PIN(3, 10)] = { PU3, 20 }, /* SD1_DAT2 */
5273 [RCAR_GP_PIN(3, 9)] = { PU3, 19 }, /* SD1_DAT1 */
5274 [RCAR_GP_PIN(3, 8)] = { PU3, 18 }, /* SD1_DAT0 */
5275 [RCAR_GP_PIN(3, 7)] = { PU3, 17 }, /* SD1_CMD */
5276 [RCAR_GP_PIN(3, 6)] = { PU3, 16 }, /* SD1_CLK */
5277 [RCAR_GP_PIN(3, 5)] = { PU3, 15 }, /* SD0_DAT3 */
5278 [RCAR_GP_PIN(3, 4)] = { PU3, 14 }, /* SD0_DAT2 */
5279 [RCAR_GP_PIN(3, 3)] = { PU3, 13 }, /* SD0_DAT1 */
5280 [RCAR_GP_PIN(3, 2)] = { PU3, 12 }, /* SD0_DAT0 */
5281 [RCAR_GP_PIN(3, 1)] = { PU3, 11 }, /* SD0_CMD */
5282 [RCAR_GP_PIN(3, 0)] = { PU3, 10 }, /* SD0_CLK */
5283
5284 [RCAR_GP_PIN(5, 19)] = { PU4, 31 }, /* MSIOF0_SS1 */
5285 [RCAR_GP_PIN(5, 18)] = { PU4, 30 }, /* MSIOF0_SYNC */
5286 [RCAR_GP_PIN(5, 17)] = { PU4, 29 }, /* MSIOF0_SCK */
5287 [RCAR_GP_PIN(5, 16)] = { PU4, 28 }, /* HRTS0_N */
5288 [RCAR_GP_PIN(5, 15)] = { PU4, 27 }, /* HCTS0_N */
5289 [RCAR_GP_PIN(5, 14)] = { PU4, 26 }, /* HTX0 */
5290 [RCAR_GP_PIN(5, 13)] = { PU4, 25 }, /* HRX0 */
5291 [RCAR_GP_PIN(5, 12)] = { PU4, 24 }, /* HSCK0 */
5292 [RCAR_GP_PIN(5, 11)] = { PU4, 23 }, /* RX2_A */
5293 [RCAR_GP_PIN(5, 10)] = { PU4, 22 }, /* TX2_A */
5294 [RCAR_GP_PIN(5, 9)] = { PU4, 21 }, /* SCK2 */
5295 [RCAR_GP_PIN(5, 8)] = { PU4, 20 }, /* RTS1_N_TANS */
5296 [RCAR_GP_PIN(5, 7)] = { PU4, 19 }, /* CTS1_N */
5297 [RCAR_GP_PIN(5, 6)] = { PU4, 18 }, /* TX1_A */
5298 [RCAR_GP_PIN(5, 5)] = { PU4, 17 }, /* RX1_A */
5299 [RCAR_GP_PIN(5, 4)] = { PU4, 16 }, /* RTS0_N_TANS */
5300 [RCAR_GP_PIN(5, 3)] = { PU4, 15 }, /* CTS0_N */
5301 [RCAR_GP_PIN(5, 2)] = { PU4, 14 }, /* TX0 */
5302 [RCAR_GP_PIN(5, 1)] = { PU4, 13 }, /* RX0 */
5303 [RCAR_GP_PIN(5, 0)] = { PU4, 12 }, /* SCK0 */
5304 [RCAR_GP_PIN(3, 15)] = { PU4, 11 }, /* SD1_WP */
5305 [RCAR_GP_PIN(3, 14)] = { PU4, 10 }, /* SD1_CD */
5306 [RCAR_GP_PIN(3, 13)] = { PU4, 9 }, /* SD0_WP */
5307 [RCAR_GP_PIN(3, 12)] = { PU4, 8 }, /* SD0_CD */
5308 [RCAR_GP_PIN(4, 17)] = { PU4, 7 }, /* SD3_DS */
5309 [RCAR_GP_PIN(4, 16)] = { PU4, 6 }, /* SD3_DAT7 */
5310 [RCAR_GP_PIN(4, 15)] = { PU4, 5 }, /* SD3_DAT6 */
5311 [RCAR_GP_PIN(4, 14)] = { PU4, 4 }, /* SD3_DAT5 */
5312 [RCAR_GP_PIN(4, 13)] = { PU4, 3 }, /* SD3_DAT4 */
5313 [RCAR_GP_PIN(4, 12)] = { PU4, 2 }, /* SD3_DAT3 */
5314 [RCAR_GP_PIN(4, 11)] = { PU4, 1 }, /* SD3_DAT2 */
5315 [RCAR_GP_PIN(4, 10)] = { PU4, 0 }, /* SD3_DAT1 */
5316
5317 [RCAR_GP_PIN(6, 24)] = { PU5, 31 }, /* USB0_PWEN */
5318 [RCAR_GP_PIN(6, 23)] = { PU5, 30 }, /* AUDIO_CLKB_B */
5319 [RCAR_GP_PIN(6, 22)] = { PU5, 29 }, /* AUDIO_CLKA_A */
5320 [RCAR_GP_PIN(6, 21)] = { PU5, 28 }, /* SSI_SDATA9_A */
5321 [RCAR_GP_PIN(6, 20)] = { PU5, 27 }, /* SSI_SDATA8 */
5322 [RCAR_GP_PIN(6, 19)] = { PU5, 26 }, /* SSI_SDATA7 */
5323 [RCAR_GP_PIN(6, 18)] = { PU5, 25 }, /* SSI_WS78 */
5324 [RCAR_GP_PIN(6, 17)] = { PU5, 24 }, /* SSI_SCK78 */
5325 [RCAR_GP_PIN(6, 16)] = { PU5, 23 }, /* SSI_SDATA6 */
5326 [RCAR_GP_PIN(6, 15)] = { PU5, 22 }, /* SSI_WS6 */
5327 [RCAR_GP_PIN(6, 14)] = { PU5, 21 }, /* SSI_SCK6 */
5328 [RCAR_GP_PIN(6, 13)] = { PU5, 20 }, /* SSI_SDATA5 */
5329 [RCAR_GP_PIN(6, 12)] = { PU5, 19 }, /* SSI_WS5 */
5330 [RCAR_GP_PIN(6, 11)] = { PU5, 18 }, /* SSI_SCK5 */
5331 [RCAR_GP_PIN(6, 10)] = { PU5, 17 }, /* SSI_SDATA4 */
5332 [RCAR_GP_PIN(6, 9)] = { PU5, 16 }, /* SSI_WS4 */
5333 [RCAR_GP_PIN(6, 8)] = { PU5, 15 }, /* SSI_SCK4 */
5334 [RCAR_GP_PIN(6, 7)] = { PU5, 14 }, /* SSI_SDATA3 */
5335 [RCAR_GP_PIN(6, 6)] = { PU5, 13 }, /* SSI_WS34 */
5336 [RCAR_GP_PIN(6, 5)] = { PU5, 12 }, /* SSI_SCK34 */
5337 [RCAR_GP_PIN(6, 4)] = { PU5, 11 }, /* SSI_SDATA2_A */
5338 [RCAR_GP_PIN(6, 3)] = { PU5, 10 }, /* SSI_SDATA1_A */
5339 [RCAR_GP_PIN(6, 2)] = { PU5, 9 }, /* SSI_SDATA0 */
5340 [RCAR_GP_PIN(6, 1)] = { PU5, 8 }, /* SSI_WS01239 */
5341 [RCAR_GP_PIN(6, 0)] = { PU5, 7 }, /* SSI_SCK01239 */
5342 [RCAR_GP_PIN(5, 25)] = { PU5, 5 }, /* MLB_DAT */
5343 [RCAR_GP_PIN(5, 24)] = { PU5, 4 }, /* MLB_SIG */
5344 [RCAR_GP_PIN(5, 23)] = { PU5, 3 }, /* MLB_CLK */
5345 [RCAR_GP_PIN(5, 22)] = { PU5, 2 }, /* MSIOF0_RXD */
5346 [RCAR_GP_PIN(5, 21)] = { PU5, 1 }, /* MSIOF0_SS2 */
5347 [RCAR_GP_PIN(5, 20)] = { PU5, 0 }, /* MSIOF0_TXD */
5348
5349 [RCAR_GP_PIN(6, 31)] = { PU6, 6 }, /* USB31_OVC */
5350 [RCAR_GP_PIN(6, 30)] = { PU6, 5 }, /* USB31_PWEN */
5351 [RCAR_GP_PIN(6, 29)] = { PU6, 4 }, /* USB30_OVC */
5352 [RCAR_GP_PIN(6, 28)] = { PU6, 3 }, /* USB30_PWEN */
5353 [RCAR_GP_PIN(6, 27)] = { PU6, 2 }, /* USB1_OVC */
5354 [RCAR_GP_PIN(6, 26)] = { PU6, 1 }, /* USB1_PWEN */
5355 [RCAR_GP_PIN(6, 25)] = { PU6, 0 }, /* USB0_OVC */
5356};
5357
5358static unsigned int r8a7795_pinmux_get_bias(struct sh_pfc *pfc,
5359 unsigned int pin)
5360{
5361 u32 reg;
5362 u32 bit;
5363
5364 if (WARN_ON_ONCE(!pullups[pin].reg))
5365 return PIN_CONFIG_BIAS_DISABLE;
5366
5367 reg = pullups[pin].reg;
5368 bit = BIT(pullups[pin].bit);
5369
5370 if (sh_pfc_read_reg(pfc, PUEN + reg, 32) & bit) {
5371 if (sh_pfc_read_reg(pfc, PUD + reg, 32) & bit)
5372 return PIN_CONFIG_BIAS_PULL_UP;
5373 else
5374 return PIN_CONFIG_BIAS_PULL_DOWN;
5375 } else
5376 return PIN_CONFIG_BIAS_DISABLE;
5377}
5378
5379static void r8a7795_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
5380 unsigned int bias)
5381{
5382 u32 enable, updown;
5383 u32 reg;
5384 u32 bit;
5385
5386 if (WARN_ON_ONCE(!pullups[pin].reg))
5387 return;
5388
5389 reg = pullups[pin].reg;
5390 bit = BIT(pullups[pin].bit);
5391
5392 enable = sh_pfc_read_reg(pfc, PUEN + reg, 32) & ~bit;
5393 if (bias != PIN_CONFIG_BIAS_DISABLE)
5394 enable |= bit;
5395
5396 updown = sh_pfc_read_reg(pfc, PUD + reg, 32) & ~bit;
5397 if (bias == PIN_CONFIG_BIAS_PULL_UP)
5398 updown |= bit;
5399
5400 sh_pfc_write_reg(pfc, PUD + reg, 32, updown);
5401 sh_pfc_write_reg(pfc, PUEN + reg, 32, enable);
5402}
5403
5076static const struct sh_pfc_soc_operations r8a7795_pinmux_ops = { 5404static const struct sh_pfc_soc_operations r8a7795_pinmux_ops = {
5077 .pin_to_pocctrl = r8a7795_pin_to_pocctrl, 5405 .pin_to_pocctrl = r8a7795_pin_to_pocctrl,
5406 .get_bias = r8a7795_pinmux_get_bias,
5407 .set_bias = r8a7795_pinmux_set_bias,
5078}; 5408};
5079 5409
5080const struct sh_pfc_soc_info r8a7795_pinmux_info = { 5410const struct sh_pfc_soc_info r8a7795_pinmux_info = {
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
new file mode 100644
index 000000000000..f8ab74dd0506
--- /dev/null
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
@@ -0,0 +1,2647 @@
1/*
2 * R8A7796 processor support - PFC hardware block.
3 *
4 * Copyright (C) 2016 Renesas Electronics Corp.
5 *
6 * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c
7 *
8 * R-Car Gen3 processor support - PFC hardware block.
9 *
10 * Copyright (C) 2015 Renesas Electronics Corporation
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; version 2 of the License.
15 */
16
17#include <linux/kernel.h>
18
19#include "core.h"
20#include "sh_pfc.h"
21
22#define CPU_ALL_PORT(fn, sfx) \
23 PORT_GP_16(0, fn, sfx), \
24 PORT_GP_29(1, fn, sfx), \
25 PORT_GP_15(2, fn, sfx), \
26 PORT_GP_16(3, fn, sfx), \
27 PORT_GP_18(4, fn, sfx), \
28 PORT_GP_26(5, fn, sfx), \
29 PORT_GP_32(6, fn, sfx), \
30 PORT_GP_4(7, fn, sfx)
31/*
32 * F_() : just information
33 * FM() : macro for FN_xxx / xxx_MARK
34 */
35
36/* GPSR0 */
37#define GPSR0_15 F_(D15, IP7_11_8)
38#define GPSR0_14 F_(D14, IP7_7_4)
39#define GPSR0_13 F_(D13, IP7_3_0)
40#define GPSR0_12 F_(D12, IP6_31_28)
41#define GPSR0_11 F_(D11, IP6_27_24)
42#define GPSR0_10 F_(D10, IP6_23_20)
43#define GPSR0_9 F_(D9, IP6_19_16)
44#define GPSR0_8 F_(D8, IP6_15_12)
45#define GPSR0_7 F_(D7, IP6_11_8)
46#define GPSR0_6 F_(D6, IP6_7_4)
47#define GPSR0_5 F_(D5, IP6_3_0)
48#define GPSR0_4 F_(D4, IP5_31_28)
49#define GPSR0_3 F_(D3, IP5_27_24)
50#define GPSR0_2 F_(D2, IP5_23_20)
51#define GPSR0_1 F_(D1, IP5_19_16)
52#define GPSR0_0 F_(D0, IP5_15_12)
53
54/* GPSR1 */
55#define GPSR1_28 FM(CLKOUT)
56#define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
57#define GPSR1_26 F_(WE1_N, IP5_7_4)
58#define GPSR1_25 F_(WE0_N, IP5_3_0)
59#define GPSR1_24 F_(RD_WR_N, IP4_31_28)
60#define GPSR1_23 F_(RD_N, IP4_27_24)
61#define GPSR1_22 F_(BS_N, IP4_23_20)
62#define GPSR1_21 F_(CS1_N_A26, IP4_19_16)
63#define GPSR1_20 F_(CS0_N, IP4_15_12)
64#define GPSR1_19 F_(A19, IP4_11_8)
65#define GPSR1_18 F_(A18, IP4_7_4)
66#define GPSR1_17 F_(A17, IP4_3_0)
67#define GPSR1_16 F_(A16, IP3_31_28)
68#define GPSR1_15 F_(A15, IP3_27_24)
69#define GPSR1_14 F_(A14, IP3_23_20)
70#define GPSR1_13 F_(A13, IP3_19_16)
71#define GPSR1_12 F_(A12, IP3_15_12)
72#define GPSR1_11 F_(A11, IP3_11_8)
73#define GPSR1_10 F_(A10, IP3_7_4)
74#define GPSR1_9 F_(A9, IP3_3_0)
75#define GPSR1_8 F_(A8, IP2_31_28)
76#define GPSR1_7 F_(A7, IP2_27_24)
77#define GPSR1_6 F_(A6, IP2_23_20)
78#define GPSR1_5 F_(A5, IP2_19_16)
79#define GPSR1_4 F_(A4, IP2_15_12)
80#define GPSR1_3 F_(A3, IP2_11_8)
81#define GPSR1_2 F_(A2, IP2_7_4)
82#define GPSR1_1 F_(A1, IP2_3_0)
83#define GPSR1_0 F_(A0, IP1_31_28)
84
85/* GPSR2 */
86#define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
87#define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
88#define GPSR2_12 F_(AVB_LINK, IP0_15_12)
89#define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
90#define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
91#define GPSR2_9 F_(AVB_MDC, IP0_3_0)
92#define GPSR2_8 F_(PWM2_A, IP1_27_24)
93#define GPSR2_7 F_(PWM1_A, IP1_23_20)
94#define GPSR2_6 F_(PWM0, IP1_19_16)
95#define GPSR2_5 F_(IRQ5, IP1_15_12)
96#define GPSR2_4 F_(IRQ4, IP1_11_8)
97#define GPSR2_3 F_(IRQ3, IP1_7_4)
98#define GPSR2_2 F_(IRQ2, IP1_3_0)
99#define GPSR2_1 F_(IRQ1, IP0_31_28)
100#define GPSR2_0 F_(IRQ0, IP0_27_24)
101
102/* GPSR3 */
103#define GPSR3_15 F_(SD1_WP, IP11_23_20)
104#define GPSR3_14 F_(SD1_CD, IP11_19_16)
105#define GPSR3_13 F_(SD0_WP, IP11_15_12)
106#define GPSR3_12 F_(SD0_CD, IP11_11_8)
107#define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
108#define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
109#define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
110#define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
111#define GPSR3_7 F_(SD1_CMD, IP8_15_12)
112#define GPSR3_6 F_(SD1_CLK, IP8_11_8)
113#define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
114#define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
115#define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
116#define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
117#define GPSR3_1 F_(SD0_CMD, IP7_23_20)
118#define GPSR3_0 F_(SD0_CLK, IP7_19_16)
119
120/* GPSR4 */
121#define GPSR4_17 F_(SD3_DS, IP11_11_8)
122#define GPSR4_16 F_(SD3_DAT7, IP10_7_4)
123#define GPSR4_15 F_(SD3_DAT6, IP10_3_0)
124#define GPSR4_14 F_(SD3_DAT5, IP9_31_28)
125#define GPSR4_13 F_(SD3_DAT4, IP9_27_24)
126#define GPSR4_12 F_(SD3_DAT3, IP10_19_16)
127#define GPSR4_11 F_(SD3_DAT2, IP10_15_12)
128#define GPSR4_10 F_(SD3_DAT1, IP10_11_8)
129#define GPSR4_9 F_(SD3_DAT0, IP10_7_4)
130#define GPSR4_8 F_(SD3_CMD, IP10_3_0)
131#define GPSR4_7 F_(SD3_CLK, IP9_31_28)
132#define GPSR4_6 F_(SD2_DS, IP9_23_20)
133#define GPSR4_5 F_(SD2_DAT3, IP9_19_16)
134#define GPSR4_4 F_(SD2_DAT2, IP9_15_12)
135#define GPSR4_3 F_(SD2_DAT1, IP9_11_8)
136#define GPSR4_2 F_(SD2_DAT0, IP9_7_4)
137#define GPSR4_1 F_(SD2_CMD, IP9_7_4)
138#define GPSR4_0 F_(SD2_CLK, IP9_3_0)
139
140/* GPSR5 */
141#define GPSR5_25 F_(MLB_DAT, IP14_19_16)
142#define GPSR5_24 F_(MLB_SIG, IP14_15_12)
143#define GPSR5_23 F_(MLB_CLK, IP14_11_8)
144#define GPSR5_22 FM(MSIOF0_RXD)
145#define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4)
146#define GPSR5_20 FM(MSIOF0_TXD)
147#define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0)
148#define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28)
149#define GPSR5_17 FM(MSIOF0_SCK)
150#define GPSR5_16 F_(HRTS0_N, IP13_27_24)
151#define GPSR5_15 F_(HCTS0_N, IP13_23_20)
152#define GPSR5_14 F_(HTX0, IP13_19_16)
153#define GPSR5_13 F_(HRX0, IP13_15_12)
154#define GPSR5_12 F_(HSCK0, IP13_11_8)
155#define GPSR5_11 F_(RX2_A, IP13_7_4)
156#define GPSR5_10 F_(TX2_A, IP13_3_0)
157#define GPSR5_9 F_(SCK2, IP12_31_28)
158#define GPSR5_8 F_(RTS1_N_TANS, IP12_27_24)
159#define GPSR5_7 F_(CTS1_N, IP12_23_20)
160#define GPSR5_6 F_(TX1_A, IP12_19_16)
161#define GPSR5_5 F_(RX1_A, IP12_15_12)
162#define GPSR5_4 F_(RTS0_N_TANS, IP12_11_8)
163#define GPSR5_3 F_(CTS0_N, IP12_7_4)
164#define GPSR5_2 F_(TX0, IP12_3_0)
165#define GPSR5_1 F_(RX0, IP11_31_28)
166#define GPSR5_0 F_(SCK0, IP11_27_24)
167
168/* GPSR6 */
169#define GPSR6_31 F_(GP6_31, IP18_7_4)
170#define GPSR6_30 F_(GP6_30, IP18_3_0)
171#define GPSR6_29 F_(USB30_OVC, IP17_31_28)
172#define GPSR6_28 F_(USB30_PWEN, IP17_27_24)
173#define GPSR6_27 F_(USB1_OVC, IP17_23_20)
174#define GPSR6_26 F_(USB1_PWEN, IP17_19_16)
175#define GPSR6_25 F_(USB0_OVC, IP17_15_12)
176#define GPSR6_24 F_(USB0_PWEN, IP17_11_8)
177#define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4)
178#define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0)
179#define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28)
180#define GPSR6_20 F_(SSI_SDATA8, IP16_27_24)
181#define GPSR6_19 F_(SSI_SDATA7, IP16_23_20)
182#define GPSR6_18 F_(SSI_WS78, IP16_19_16)
183#define GPSR6_17 F_(SSI_SCK78, IP16_15_12)
184#define GPSR6_16 F_(SSI_SDATA6, IP16_11_8)
185#define GPSR6_15 F_(SSI_WS6, IP16_7_4)
186#define GPSR6_14 F_(SSI_SCK6, IP16_3_0)
187#define GPSR6_13 FM(SSI_SDATA5)
188#define GPSR6_12 FM(SSI_WS5)
189#define GPSR6_11 FM(SSI_SCK5)
190#define GPSR6_10 F_(SSI_SDATA4, IP15_31_28)
191#define GPSR6_9 F_(SSI_WS4, IP15_27_24)
192#define GPSR6_8 F_(SSI_SCK4, IP15_23_20)
193#define GPSR6_7 F_(SSI_SDATA3, IP15_19_16)
194#define GPSR6_6 F_(SSI_WS34, IP15_15_12)
195#define GPSR6_5 F_(SSI_SCK34, IP15_11_8)
196#define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4)
197#define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0)
198#define GPSR6_2 F_(SSI_SDATA0, IP14_31_28)
199#define GPSR6_1 F_(SSI_WS0129, IP14_27_24)
200#define GPSR6_0 F_(SSI_SCK0129, IP14_23_20)
201
202/* GPSR7 */
203#define GPSR7_3 FM(GP7_03)
204#define GPSR7_2 FM(HDMI0_CEC)
205#define GPSR7_1 FM(AVS2)
206#define GPSR7_0 FM(AVS1)
207
208
209/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
210#define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
211#define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
212#define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
213#define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
214#define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
215#define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_TANS_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
216#define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
217#define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
218#define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
219#define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) FM(A25) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
220#define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) FM(A24) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
221#define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) FM(A23) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) F_(0, 0) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222#define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)FM(A22) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
223#define IP1_23_20 FM(PWM1_A) F_(0, 0) FM(A21) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
224#define IP1_27_24 FM(PWM2_A) F_(0, 0) FM(A20) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225#define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
226#define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
227#define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
228#define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
229#define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
230#define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
231#define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
232#define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
233#define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
234#define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
235#define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_TANS_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
236#define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
237
238/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
239#define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
240#define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
241#define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
242#define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
243#define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
244#define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
245#define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
246#define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
247#define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
248#define IP4_19_16 FM(CS1_N_A26) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
249#define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
250#define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
251#define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
252#define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
253#define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N_TANS) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
254#define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
255#define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
256#define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257#define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258#define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259#define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260#define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261#define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262#define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263#define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264#define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265#define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266#define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_TANS_C)FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267#define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268
269/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
270#define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271#define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272#define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273#define IP7_15_12 FM(FSCLKST) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274#define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
275#define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
276#define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
277#define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278#define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279#define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280#define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281#define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282#define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283#define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284#define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285#define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286#define IP9_3_0 FM(SD2_CLK) F_(0, 0) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287#define IP9_7_4 FM(SD2_CMD) F_(0, 0) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288#define IP9_11_8 FM(SD2_DAT0) F_(0, 0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289#define IP9_15_12 FM(SD2_DAT1) F_(0, 0) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290#define IP9_19_16 FM(SD2_DAT2) F_(0, 0) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291#define IP9_23_20 FM(SD2_DAT3) F_(0, 0) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292#define IP9_27_24 FM(SD2_DS) F_(0, 0) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293#define IP9_31_28 FM(SD3_CLK) F_(0, 0) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294#define IP10_3_0 FM(SD3_CMD) F_(0, 0) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295#define IP10_7_4 FM(SD3_DAT0) F_(0, 0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296#define IP10_11_8 FM(SD3_DAT1) F_(0, 0) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297#define IP10_15_12 FM(SD3_DAT2) F_(0, 0) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298#define IP10_19_16 FM(SD3_DAT3) F_(0, 0) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299#define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) F_(0, 0) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300#define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) F_(0, 0) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301#define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) F_(0, 0) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302#define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) F_(0, 0) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303#define IP11_7_4 FM(SD3_DS) F_(0, 0) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304#define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305
306/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
307#define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308#define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309#define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310#define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311#define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312#define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313#define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314#define IP12_11_8 FM(RTS0_N_TANS) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) FM(FSO_TOE_A) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315#define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316#define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317#define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
318#define IP12_27_24 FM(RTS1_N_TANS) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
319#define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320#define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321#define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322#define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323#define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324#define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325#define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326#define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327#define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
328#define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
329#define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
330#define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331#define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332#define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
333#define IP14_23_20 FM(SSI_SCK0129) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334#define IP14_27_24 FM(SSI_WS0129) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335
336/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
337#define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
338#define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
339#define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
340#define IP15_11_8 FM(SSI_SCK34) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
341#define IP15_15_12 FM(SSI_WS34) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
342#define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343#define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
344#define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345#define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346#define IP16_3_0 FM(SSI_SCK6) F_(0, 0) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347#define IP16_7_4 FM(SSI_WS6) F_(0, 0) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348#define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349#define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
350#define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
351#define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
352#define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
353#define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
354#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
355#define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
356#define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
357#define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
358#define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
359#define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
360#define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
361#define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_B) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
362#define IP18_3_0 FM(GP6_30) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) FM(FSO_CFE_0_A) FM(TPU0TO2) F_(0, 0) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0)
363#define IP18_7_4 FM(GP6_31) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) FM(FSO_CFE_1_A) FM(TPU0TO3) F_(0, 0) FM(FMIN_C) FM(FMIN_D) F_(0, 0)
364
365#define PINMUX_GPSR \
366\
367 GPSR6_31 \
368 GPSR6_30 \
369 GPSR6_29 \
370 GPSR1_28 GPSR6_28 \
371 GPSR1_27 GPSR6_27 \
372 GPSR1_26 GPSR6_26 \
373 GPSR1_25 GPSR5_25 GPSR6_25 \
374 GPSR1_24 GPSR5_24 GPSR6_24 \
375 GPSR1_23 GPSR5_23 GPSR6_23 \
376 GPSR1_22 GPSR5_22 GPSR6_22 \
377 GPSR1_21 GPSR5_21 GPSR6_21 \
378 GPSR1_20 GPSR5_20 GPSR6_20 \
379 GPSR1_19 GPSR5_19 GPSR6_19 \
380 GPSR1_18 GPSR5_18 GPSR6_18 \
381 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
382 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
383GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
384GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
385GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
386GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
387GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
388GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
389GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
390GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
391GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
392GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
393GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
394GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
395GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
396GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
397GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
398GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
399
400#define PINMUX_IPSR \
401\
402FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
403FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
404FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
405FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
406FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
407FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
408FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
409FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
410\
411FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
412FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
413FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
414FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \
415FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
416FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
417FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
418FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
419\
420FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
421FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
422FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
423FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
424FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
425FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
426FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
427FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
428\
429FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
430FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
431FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
432FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
433FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
434FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
435FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
436FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
437\
438FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \
439FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \
440FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \
441FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \
442FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \
443FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \
444FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \
445FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
446
447/* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
448#define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0)
449#define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
450#define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
451#define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
452#define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
453#define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
454#define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
455#define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
456#define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
457#define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
458#define MOD_SEL0_15 FM(SEL_FSO_0) FM(SEL_FSO_1)
459#define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0)
460#define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
461#define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
462#define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
463#define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
464#define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
465#define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
466#define MOD_SEL0_4_3 FM(SEL_ADG_A_0) FM(SEL_ADG_A_1) FM(SEL_ADG_A_2) FM(SEL_ADG_A_3)
467#define MOD_SEL0_2 FM(SEL_5LINE_0) FM(SEL_5LINE_1)
468
469/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
470#define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
471#define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
472#define MOD_SEL1_26 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
473#define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
474#define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
475#define MOD_SEL1_20 FM(SEL_SSI_0) FM(SEL_SSI_1)
476#define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
477#define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
478#define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
479#define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
480#define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
481#define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
482#define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
483#define MOD_SEL1_10 FM(SEL_SATA_0) FM(SEL_SATA_1)
484#define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
485#define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
486#define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
487#define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
488#define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
489#define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
490#define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
491#define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
492
493/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
494#define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
495#define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
496#define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
497#define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
498#define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
499#define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
500#define MOD_SEL2_22 FM(SEL_NDF_0) FM(SEL_NDF_1)
501#define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
502#define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
503#define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
504#define MOD_SEL2_18 FM(SEL_ADG_B_0) FM(SEL_ADG_B_1)
505#define MOD_SEL2_17 FM(SEL_ADG_C_0) FM(SEL_ADG_C_1)
506#define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
507
508#define PINMUX_MOD_SELS \
509\
510MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \
511 MOD_SEL2_30 \
512 MOD_SEL1_29_28_27 MOD_SEL2_29 \
513MOD_SEL0_28_27 MOD_SEL2_28_27 \
514MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \
515 MOD_SEL1_25_24 MOD_SEL2_25_24_23 \
516MOD_SEL0_23 MOD_SEL1_23_22_21 \
517MOD_SEL0_22 MOD_SEL2_22 \
518MOD_SEL0_21 MOD_SEL2_21 \
519MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \
520MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \
521MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \
522 MOD_SEL2_17 \
523MOD_SEL0_16 MOD_SEL1_16 \
524MOD_SEL0_15 MOD_SEL1_15_14 \
525MOD_SEL0_14_13 \
526 MOD_SEL1_13 \
527MOD_SEL0_12 MOD_SEL1_12 \
528MOD_SEL0_11 MOD_SEL1_11 \
529MOD_SEL0_10 MOD_SEL1_10 \
530MOD_SEL0_9_8 MOD_SEL1_9 \
531MOD_SEL0_7_6 \
532 MOD_SEL1_6 \
533MOD_SEL0_5 MOD_SEL1_5 \
534MOD_SEL0_4_3 MOD_SEL1_4 \
535 MOD_SEL1_3 \
536MOD_SEL0_2 MOD_SEL1_2 \
537 MOD_SEL1_1 \
538 MOD_SEL1_0 MOD_SEL2_0
539
540enum {
541 PINMUX_RESERVED = 0,
542
543 PINMUX_DATA_BEGIN,
544 GP_ALL(DATA),
545 PINMUX_DATA_END,
546
547#define F_(x, y)
548#define FM(x) FN_##x,
549 PINMUX_FUNCTION_BEGIN,
550 GP_ALL(FN),
551 PINMUX_GPSR
552 PINMUX_IPSR
553 PINMUX_MOD_SELS
554 PINMUX_FUNCTION_END,
555#undef F_
556#undef FM
557
558#define F_(x, y)
559#define FM(x) x##_MARK,
560 PINMUX_MARK_BEGIN,
561 PINMUX_GPSR
562 PINMUX_IPSR
563 PINMUX_MOD_SELS
564 PINMUX_MARK_END,
565#undef F_
566#undef FM
567};
568
569static const u16 pinmux_data[] = {
570 PINMUX_DATA_GP_ALL(),
571
572 PINMUX_SINGLE(AVS1),
573 PINMUX_SINGLE(AVS2),
574 PINMUX_SINGLE(CLKOUT),
575 PINMUX_SINGLE(GP7_03),
576 PINMUX_SINGLE(HDMI0_CEC),
577 PINMUX_SINGLE(MSIOF0_RXD),
578 PINMUX_SINGLE(MSIOF0_SCK),
579 PINMUX_SINGLE(MSIOF0_TXD),
580 PINMUX_SINGLE(SSI_SCK5),
581 PINMUX_SINGLE(SSI_SDATA5),
582 PINMUX_SINGLE(SSI_WS5),
583
584 /* IPSR0 */
585 PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC),
586 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2),
587
588 PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC),
589 PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2),
590 PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0),
591
592 PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT),
593 PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2),
594 PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0),
595
596 PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK),
597 PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
598 PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
599
600 PINMUX_IPSR_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, SEL_ETHERAVB_0),
601 PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_RXD_C, SEL_MSIOF2_2),
602 PINMUX_IPSR_MSEL(IP0_19_16, CTS4_N_A, SEL_SCIF4_0),
603
604 PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0),
605 PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_2),
606 PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_TANS_A, SEL_SCIF4_0),
607
608 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
609 PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
610 PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE),
611 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1),
612 PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1),
613 PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1),
614 PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS2_E, SEL_MSIOF3_4),
615
616 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
617 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
618 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
619 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
620 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
621 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
622 PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS1_E, SEL_MSIOF3_4),
623
624 /* IPSR1 */
625 PINMUX_IPSR_GPSR(IP1_3_0, IRQ2),
626 PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE),
627 PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE),
628 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1),
629 PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1),
630 PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_SYNC_E, SEL_MSIOF3_4),
631
632 PINMUX_IPSR_GPSR(IP1_7_4, IRQ3),
633 PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE),
634 PINMUX_IPSR_GPSR(IP1_7_4, A25),
635 PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1),
636 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1),
637 PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1),
638 PINMUX_IPSR_MSEL(IP1_7_4, MSIOF3_SCK_E, SEL_MSIOF3_4),
639
640 PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
641 PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS),
642 PINMUX_IPSR_GPSR(IP1_11_8, A24),
643 PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC),
644 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1),
645 PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1),
646 PINMUX_IPSR_MSEL(IP1_11_8, MSIOF3_RXD_E, SEL_MSIOF3_4),
647
648 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
649 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
650 PINMUX_IPSR_GPSR(IP1_15_12, A23),
651 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
652 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
653 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
654 PINMUX_IPSR_MSEL(IP1_15_12, MSIOF3_TXD_E, SEL_MSIOF3_4),
655
656 PINMUX_IPSR_GPSR(IP1_19_16, PWM0),
657 PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS),
658 PINMUX_IPSR_GPSR(IP1_19_16, A22),
659 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
660 PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
661
662 PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0),
663 PINMUX_IPSR_GPSR(IP1_23_20, A21),
664 PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3),
665 PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B, SEL_VIN4_1),
666 PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1),
667
668 PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0),
669 PINMUX_IPSR_GPSR(IP1_27_24, A20),
670 PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3),
671 PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1),
672
673 PINMUX_IPSR_GPSR(IP1_31_28, A0),
674 PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
675 PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1),
676 PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8),
677 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0),
678 PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0),
679
680 /* IPSR2 */
681 PINMUX_IPSR_GPSR(IP2_3_0, A1),
682 PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17),
683 PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1),
684 PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9),
685 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1),
686 PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0),
687
688 PINMUX_IPSR_GPSR(IP2_7_4, A2),
689 PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18),
690 PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1),
691 PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10),
692 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2),
693 PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0),
694
695 PINMUX_IPSR_GPSR(IP2_11_8, A3),
696 PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19),
697 PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1),
698 PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11),
699 PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3),
700 PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0),
701
702 PINMUX_IPSR_GPSR(IP2_15_12, A4),
703 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20),
704 PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1),
705 PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12),
706 PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12),
707 PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4),
708
709 PINMUX_IPSR_GPSR(IP2_19_16, A5),
710 PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21),
711 PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1),
712 PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1),
713 PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13),
714 PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13),
715 PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5),
716
717 PINMUX_IPSR_GPSR(IP2_23_20, A6),
718 PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22),
719 PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0),
720 PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1),
721 PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14),
722 PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14),
723 PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6),
724
725 PINMUX_IPSR_GPSR(IP2_27_24, A7),
726 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23),
727 PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0),
728 PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1),
729 PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15),
730 PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15),
731 PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7),
732
733 PINMUX_IPSR_GPSR(IP2_31_28, A8),
734 PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1),
735 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0),
736 PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1),
737 PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0),
738 PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1),
739 PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1),
740
741 /* IPSR3 */
742 PINMUX_IPSR_GPSR(IP3_3_0, A9),
743 PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0),
744 PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1),
745 PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N),
746
747 PINMUX_IPSR_GPSR(IP3_7_4, A10),
748 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
749 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_TANS_B, SEL_SCIF4_1),
750 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
751
752 PINMUX_IPSR_GPSR(IP3_11_8, A11),
753 PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1),
754 PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0),
755 PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1),
756 PINMUX_IPSR_GPSR(IP3_11_8, HSCK4),
757 PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD),
758 PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0),
759 PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
760 PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1),
761
762 PINMUX_IPSR_GPSR(IP3_15_12, A12),
763 PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12),
764 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2),
765 PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0),
766 PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8),
767 PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4),
768
769 PINMUX_IPSR_GPSR(IP3_19_16, A13),
770 PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13),
771 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2),
772 PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0),
773 PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9),
774 PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5),
775
776 PINMUX_IPSR_GPSR(IP3_23_20, A14),
777 PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14),
778 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2),
779 PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N),
780 PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10),
781 PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6),
782
783 PINMUX_IPSR_GPSR(IP3_27_24, A15),
784 PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15),
785 PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2),
786 PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N),
787 PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11),
788 PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7),
789
790 PINMUX_IPSR_GPSR(IP3_31_28, A16),
791 PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8),
792 PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD),
793 PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0),
794
795 /* IPSR4 */
796 PINMUX_IPSR_GPSR(IP4_3_0, A17),
797 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9),
798 PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N),
799 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1),
800
801 PINMUX_IPSR_GPSR(IP4_7_4, A18),
802 PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10),
803 PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N),
804 PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2),
805
806 PINMUX_IPSR_GPSR(IP4_11_8, A19),
807 PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11),
808 PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB),
809 PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3),
810
811 PINMUX_IPSR_GPSR(IP4_15_12, CS0_N),
812 PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB),
813
814 PINMUX_IPSR_GPSR(IP4_19_16, CS1_N_A26),
815 PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK),
816 PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1),
817
818 PINMUX_IPSR_GPSR(IP4_23_20, BS_N),
819 PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS),
820 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3),
821 PINMUX_IPSR_GPSR(IP4_23_20, SCK3),
822 PINMUX_IPSR_GPSR(IP4_23_20, HSCK3),
823 PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX),
824 PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX),
825 PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0),
826
827 PINMUX_IPSR_GPSR(IP4_27_24, RD_N),
828 PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3),
829 PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0),
830 PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0),
831 PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0),
832 PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0),
833
834 PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N),
835 PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3),
836 PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0),
837 PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0),
838 PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0),
839 PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0),
840
841 /* IPSR5 */
842 PINMUX_IPSR_GPSR(IP5_3_0, WE0_N),
843 PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3),
844 PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N),
845 PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N),
846 PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1),
847 PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK),
848 PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0),
849
850 PINMUX_IPSR_GPSR(IP5_7_4, WE1_N),
851 PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3),
852 PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N_TANS),
853 PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N),
854 PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1),
855 PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX),
856 PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX),
857 PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0),
858
859 PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0),
860 PINMUX_IPSR_GPSR(IP5_11_8, QCLK),
861 PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK),
862 PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0),
863
864 PINMUX_IPSR_GPSR(IP5_15_12, D0),
865 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1),
866 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0),
867 PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16),
868 PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0),
869
870 PINMUX_IPSR_GPSR(IP5_19_16, D1),
871 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1),
872 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0),
873 PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17),
874 PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1),
875
876 PINMUX_IPSR_GPSR(IP5_23_20, D2),
877 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0),
878 PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18),
879 PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2),
880
881 PINMUX_IPSR_GPSR(IP5_27_24, D3),
882 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
883 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19),
884 PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3),
885
886 PINMUX_IPSR_GPSR(IP5_31_28, D4),
887 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1),
888 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20),
889 PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4),
890
891 /* IPSR6 */
892 PINMUX_IPSR_GPSR(IP6_3_0, D5),
893 PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
894 PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21),
895 PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5),
896
897 PINMUX_IPSR_GPSR(IP6_7_4, D6),
898 PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1),
899 PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22),
900 PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6),
901
902 PINMUX_IPSR_GPSR(IP6_11_8, D7),
903 PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1),
904 PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23),
905 PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7),
906
907 PINMUX_IPSR_GPSR(IP6_15_12, D8),
908 PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0),
909 PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3),
910 PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2),
911 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0),
912 PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0),
913
914 PINMUX_IPSR_GPSR(IP6_19_16, D9),
915 PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1),
916 PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3),
917 PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0),
918 PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1),
919
920 PINMUX_IPSR_GPSR(IP6_23_20, D10),
921 PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2),
922 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3),
923 PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1),
924 PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0),
925 PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2),
926 PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2),
927
928 PINMUX_IPSR_GPSR(IP6_27_24, D11),
929 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3),
930 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3),
931 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1),
932 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0),
933 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_TANS_C, SEL_SCIF4_2),
934 PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3),
935
936 PINMUX_IPSR_GPSR(IP6_31_28, D12),
937 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4),
938 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3),
939 PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2),
940 PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0),
941 PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4),
942
943 /* IPSR7 */
944 PINMUX_IPSR_GPSR(IP7_3_0, D13),
945 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5),
946 PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3),
947 PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2),
948 PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0),
949 PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5),
950
951 PINMUX_IPSR_GPSR(IP7_7_4, D14),
952 PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6),
953 PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0),
954 PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2),
955 PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0),
956 PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6),
957 PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2),
958
959 PINMUX_IPSR_GPSR(IP7_11_8, D15),
960 PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7),
961 PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0),
962 PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2),
963 PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0),
964 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7),
965 PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2),
966
967 PINMUX_IPSR_GPSR(IP7_15_12, FSCLKST),
968
969 PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK),
970 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4),
971 PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1),
972
973 PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD),
974 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4),
975 PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1),
976
977 PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0),
978 PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4),
979 PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1),
980 PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1),
981
982 PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1),
983 PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4),
984 PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1),
985 PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1),
986
987 /* IPSR8 */
988 PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2),
989 PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4),
990 PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1),
991 PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1),
992
993 PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3),
994 PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4),
995 PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1),
996 PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1),
997
998 PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK),
999 PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6),
1000 PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0),
1001
1002 PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
1003 PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
1004 PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDF_1),
1005 PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
1006 PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
1007
1008 PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
1009 PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
1010 PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
1011 PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDF_1),
1012 PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
1013 PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
1014
1015 PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
1016 PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
1017 PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
1018 PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1),
1019 PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
1020 PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
1021
1022 PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
1023 PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
1024 PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
1025 PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1),
1026 PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
1027 PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
1028
1029 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
1030 PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
1031 PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
1032 PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDF_1),
1033 PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
1034 PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
1035
1036 /* IPSR9 */
1037 PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK),
1038 PINMUX_IPSR_GPSR(IP9_3_0, NFDATA8),
1039
1040 PINMUX_IPSR_GPSR(IP9_7_4, SD2_CMD),
1041 PINMUX_IPSR_GPSR(IP9_7_4, NFDATA9),
1042
1043 PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT0),
1044 PINMUX_IPSR_GPSR(IP9_11_8, NFDATA10),
1045
1046 PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT1),
1047 PINMUX_IPSR_GPSR(IP9_15_12, NFDATA11),
1048
1049 PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT2),
1050 PINMUX_IPSR_GPSR(IP9_19_16, NFDATA12),
1051
1052 PINMUX_IPSR_GPSR(IP9_23_20, SD2_DAT3),
1053 PINMUX_IPSR_GPSR(IP9_23_20, NFDATA13),
1054
1055 PINMUX_IPSR_GPSR(IP9_27_24, SD2_DS),
1056 PINMUX_IPSR_GPSR(IP9_27_24, NFALE),
1057
1058 PINMUX_IPSR_GPSR(IP9_31_28, SD3_CLK),
1059 PINMUX_IPSR_GPSR(IP9_31_28, NFWE_N),
1060
1061 /* IPSR10 */
1062 PINMUX_IPSR_GPSR(IP10_3_0, SD3_CMD),
1063 PINMUX_IPSR_GPSR(IP10_3_0, NFRE_N),
1064
1065 PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT0),
1066 PINMUX_IPSR_GPSR(IP10_7_4, NFDATA0),
1067
1068 PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT1),
1069 PINMUX_IPSR_GPSR(IP10_11_8, NFDATA1),
1070
1071 PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT2),
1072 PINMUX_IPSR_GPSR(IP10_15_12, NFDATA2),
1073
1074 PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT3),
1075 PINMUX_IPSR_GPSR(IP10_19_16, NFDATA3),
1076
1077 PINMUX_IPSR_GPSR(IP10_23_20, SD3_DAT4),
1078 PINMUX_IPSR_MSEL(IP10_23_20, SD2_CD_A, SEL_SDHI2_0),
1079 PINMUX_IPSR_GPSR(IP10_23_20, NFDATA4),
1080
1081 PINMUX_IPSR_GPSR(IP10_27_24, SD3_DAT5),
1082 PINMUX_IPSR_MSEL(IP10_27_24, SD2_WP_A, SEL_SDHI2_0),
1083 PINMUX_IPSR_GPSR(IP10_27_24, NFDATA5),
1084
1085 PINMUX_IPSR_GPSR(IP10_31_28, SD3_DAT6),
1086 PINMUX_IPSR_GPSR(IP10_31_28, SD3_CD),
1087 PINMUX_IPSR_GPSR(IP10_31_28, NFDATA6),
1088
1089 /* IPSR11 */
1090 PINMUX_IPSR_GPSR(IP11_3_0, SD3_DAT7),
1091 PINMUX_IPSR_GPSR(IP11_3_0, SD3_WP),
1092 PINMUX_IPSR_GPSR(IP11_3_0, NFDATA7),
1093
1094 PINMUX_IPSR_GPSR(IP11_7_4, SD3_DS),
1095 PINMUX_IPSR_GPSR(IP11_7_4, NFCLE),
1096
1097 PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD),
1098 PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1),
1099 PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0),
1100
1101 PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP),
1102 PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),
1103
1104 PINMUX_IPSR_GPSR(IP11_19_16, SD1_CD),
1105 PINMUX_IPSR_MSEL(IP11_19_16, SIM0_CLK_B, SEL_SIMCARD_1),
1106
1107 PINMUX_IPSR_GPSR(IP11_23_20, SD1_WP),
1108 PINMUX_IPSR_MSEL(IP11_23_20, SIM0_D_B, SEL_SIMCARD_1),
1109
1110 PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
1111 PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1),
1112 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
1113 PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADG_C_1),
1114 PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
1115 PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1),
1116 PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
1117 PINMUX_IPSR_MSEL(IP11_27_24, RIF0_CLK_B, SEL_DRIF0_1),
1118 PINMUX_IPSR_GPSR(IP11_27_24, ADICHS2),
1119 PINMUX_IPSR_MSEL(IP11_27_24, SCK5_B, SEL_SCIF5_1),
1120
1121 PINMUX_IPSR_GPSR(IP11_31_28, RX0),
1122 PINMUX_IPSR_MSEL(IP11_31_28, HRX1_B, SEL_HSCIF1_1),
1123 PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK0_C, SEL_TSIF0_2),
1124 PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2),
1125 PINMUX_IPSR_MSEL(IP11_31_28, RIF0_D0_B, SEL_DRIF0_1),
1126
1127 /* IPSR12 */
1128 PINMUX_IPSR_GPSR(IP12_3_0, TX0),
1129 PINMUX_IPSR_MSEL(IP12_3_0, HTX1_B, SEL_HSCIF1_1),
1130 PINMUX_IPSR_MSEL(IP12_3_0, TS_SPSYNC0_C, SEL_TSIF0_2),
1131 PINMUX_IPSR_MSEL(IP12_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2),
1132 PINMUX_IPSR_MSEL(IP12_3_0, RIF0_D1_B, SEL_DRIF0_1),
1133
1134 PINMUX_IPSR_GPSR(IP12_7_4, CTS0_N),
1135 PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_B, SEL_HSCIF1_1),
1136 PINMUX_IPSR_MSEL(IP12_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1),
1137 PINMUX_IPSR_MSEL(IP12_7_4, TS_SPSYNC1_C, SEL_TSIF1_2),
1138 PINMUX_IPSR_MSEL(IP12_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2),
1139 PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_B, SEL_DRIF1_1),
1140 PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C),
1141 PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP),
1142
1143 PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N_TANS),
1144 PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1),
1145 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
1146 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADG_A_1),
1147 PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0),
1148 PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
1149 PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
1150 PINMUX_IPSR_MSEL(IP12_11_8, FSO_TOE_A, SEL_FSO_0),
1151 PINMUX_IPSR_GPSR(IP12_11_8, ADICHS1),
1152
1153 PINMUX_IPSR_MSEL(IP12_15_12, RX1_A, SEL_SCIF1_0),
1154 PINMUX_IPSR_MSEL(IP12_15_12, HRX1_A, SEL_HSCIF1_0),
1155 PINMUX_IPSR_MSEL(IP12_15_12, TS_SDAT0_C, SEL_TSIF0_2),
1156 PINMUX_IPSR_MSEL(IP12_15_12, STP_ISD_0_C, SEL_SSP1_0_2),
1157 PINMUX_IPSR_MSEL(IP12_15_12, RIF1_CLK_C, SEL_DRIF1_2),
1158
1159 PINMUX_IPSR_MSEL(IP12_19_16, TX1_A, SEL_SCIF1_0),
1160 PINMUX_IPSR_MSEL(IP12_19_16, HTX1_A, SEL_HSCIF1_0),
1161 PINMUX_IPSR_MSEL(IP12_19_16, TS_SDEN0_C, SEL_TSIF0_2),
1162 PINMUX_IPSR_MSEL(IP12_19_16, STP_ISEN_0_C, SEL_SSP1_0_2),
1163 PINMUX_IPSR_MSEL(IP12_19_16, RIF1_D0_C, SEL_DRIF1_2),
1164
1165 PINMUX_IPSR_GPSR(IP12_23_20, CTS1_N),
1166 PINMUX_IPSR_MSEL(IP12_23_20, HCTS1_N_A, SEL_HSCIF1_0),
1167 PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1),
1168 PINMUX_IPSR_MSEL(IP12_23_20, TS_SDEN1_C, SEL_TSIF1_2),
1169 PINMUX_IPSR_MSEL(IP12_23_20, STP_ISEN_1_C, SEL_SSP1_1_2),
1170 PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1),
1171 PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA),
1172
1173 PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N_TANS),
1174 PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0),
1175 PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1),
1176 PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2),
1177 PINMUX_IPSR_MSEL(IP12_27_24, STP_ISD_1_C, SEL_SSP1_1_2),
1178 PINMUX_IPSR_MSEL(IP12_27_24, RIF1_D1_B, SEL_DRIF1_1),
1179 PINMUX_IPSR_GPSR(IP12_27_24, ADICHS0),
1180
1181 PINMUX_IPSR_GPSR(IP12_31_28, SCK2),
1182 PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF1_1),
1183 PINMUX_IPSR_MSEL(IP12_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1),
1184 PINMUX_IPSR_MSEL(IP12_31_28, TS_SCK1_C, SEL_TSIF1_2),
1185 PINMUX_IPSR_MSEL(IP12_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2),
1186 PINMUX_IPSR_MSEL(IP12_31_28, RIF1_CLK_B, SEL_DRIF1_1),
1187 PINMUX_IPSR_GPSR(IP12_31_28, ADICLK),
1188
1189 /* IPSR13 */
1190 PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0),
1191 PINMUX_IPSR_MSEL(IP13_3_0, SD2_CD_B, SEL_SDHI2_1),
1192 PINMUX_IPSR_MSEL(IP13_3_0, SCL1_A, SEL_I2C1_0),
1193 PINMUX_IPSR_MSEL(IP13_3_0, FMCLK_A, SEL_FM_0),
1194 PINMUX_IPSR_MSEL(IP13_3_0, RIF1_D1_C, SEL_DRIF1_2),
1195 PINMUX_IPSR_MSEL(IP13_3_0, FSO_CFE_0_B, SEL_FSO_1),
1196
1197 PINMUX_IPSR_MSEL(IP13_7_4, RX2_A, SEL_SCIF2_0),
1198 PINMUX_IPSR_MSEL(IP13_7_4, SD2_WP_B, SEL_SDHI2_1),
1199 PINMUX_IPSR_MSEL(IP13_7_4, SDA1_A, SEL_I2C1_0),
1200 PINMUX_IPSR_MSEL(IP13_7_4, FMIN_A, SEL_FM_0),
1201 PINMUX_IPSR_MSEL(IP13_7_4, RIF1_SYNC_C, SEL_DRIF1_2),
1202 PINMUX_IPSR_MSEL(IP13_7_4, FSO_CFE_1_B, SEL_FSO_1),
1203
1204 PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
1205 PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
1206 PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADG_B_0),
1207 PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI_1),
1208 PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3),
1209 PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
1210 PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2),
1211 PINMUX_IPSR_MSEL(IP13_11_8, RX5_B, SEL_SCIF5_1),
1212
1213 PINMUX_IPSR_GPSR(IP13_15_12, HRX0),
1214 PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3),
1215 PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI_1),
1216 PINMUX_IPSR_MSEL(IP13_15_12, TS_SDEN0_D, SEL_TSIF0_3),
1217 PINMUX_IPSR_MSEL(IP13_15_12, STP_ISEN_0_D, SEL_SSP1_0_3),
1218 PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_C, SEL_DRIF0_2),
1219
1220 PINMUX_IPSR_GPSR(IP13_19_16, HTX0),
1221 PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3),
1222 PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI_1),
1223 PINMUX_IPSR_MSEL(IP13_19_16, TS_SDAT0_D, SEL_TSIF0_3),
1224 PINMUX_IPSR_MSEL(IP13_19_16, STP_ISD_0_D, SEL_SSP1_0_3),
1225 PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_C, SEL_DRIF0_2),
1226
1227 PINMUX_IPSR_GPSR(IP13_23_20, HCTS0_N),
1228 PINMUX_IPSR_MSEL(IP13_23_20, RX2_B, SEL_SCIF2_1),
1229 PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3),
1230 PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI_0),
1231 PINMUX_IPSR_MSEL(IP13_23_20, TS_SPSYNC0_D, SEL_TSIF0_3),
1232 PINMUX_IPSR_MSEL(IP13_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3),
1233 PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_C, SEL_DRIF0_2),
1234 PINMUX_IPSR_GPSR(IP13_23_20, AUDIO_CLKOUT1_A),
1235
1236 PINMUX_IPSR_GPSR(IP13_27_24, HRTS0_N),
1237 PINMUX_IPSR_MSEL(IP13_27_24, TX2_B, SEL_SCIF2_1),
1238 PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3),
1239 PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI_0),
1240 PINMUX_IPSR_MSEL(IP13_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3),
1241 PINMUX_IPSR_MSEL(IP13_27_24, BPFCLK_A, SEL_FM_0),
1242 PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT2_A),
1243
1244 PINMUX_IPSR_GPSR(IP13_31_28, MSIOF0_SYNC),
1245 PINMUX_IPSR_GPSR(IP13_31_28, AUDIO_CLKOUT_A),
1246 PINMUX_IPSR_MSEL(IP13_31_28, TX5_B, SEL_SCIF5_1),
1247 PINMUX_IPSR_MSEL(IP13_31_28, BPFCLK_D, SEL_FM_3),
1248
1249 /* IPSR14 */
1250 PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
1251 PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
1252 PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDF_0),
1253 PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADG_A_2),
1254 PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI_0),
1255 PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
1256 PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A),
1257 PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU_1),
1258
1259 PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2),
1260 PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0),
1261 PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
1262 PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADG_C_0),
1263 PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI_0),
1264 PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
1265 PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D),
1266 PINMUX_IPSR_MSEL(IP14_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1),
1267
1268 PINMUX_IPSR_GPSR(IP14_11_8, MLB_CLK),
1269 PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5),
1270 PINMUX_IPSR_MSEL(IP14_11_8, SCL1_B, SEL_I2C1_1),
1271
1272 PINMUX_IPSR_GPSR(IP14_15_12, MLB_SIG),
1273 PINMUX_IPSR_MSEL(IP14_15_12, RX1_B, SEL_SCIF1_1),
1274 PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5),
1275 PINMUX_IPSR_MSEL(IP14_15_12, SDA1_B, SEL_I2C1_1),
1276
1277 PINMUX_IPSR_GPSR(IP14_19_16, MLB_DAT),
1278 PINMUX_IPSR_MSEL(IP14_19_16, TX1_B, SEL_SCIF1_1),
1279 PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5),
1280
1281 PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK0129),
1282 PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5),
1283
1284 PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS0129),
1285 PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5),
1286
1287 PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA0),
1288 PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5),
1289
1290 /* IPSR15 */
1291 PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI_0),
1292
1293 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI_0),
1294 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI_1),
1295
1296 PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK34),
1297 PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
1298 PINMUX_IPSR_MSEL(IP15_11_8, STP_OPWM_0_A, SEL_SSP1_0_0),
1299
1300 PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS34),
1301 PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0),
1302 PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0),
1303 PINMUX_IPSR_MSEL(IP15_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0),
1304
1305 PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA3),
1306 PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0),
1307 PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0),
1308 PINMUX_IPSR_MSEL(IP15_19_16, TS_SCK0_A, SEL_TSIF0_0),
1309 PINMUX_IPSR_MSEL(IP15_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0),
1310 PINMUX_IPSR_MSEL(IP15_19_16, RIF0_D1_A, SEL_DRIF0_0),
1311 PINMUX_IPSR_MSEL(IP15_19_16, RIF2_D0_A, SEL_DRIF2_0),
1312
1313 PINMUX_IPSR_GPSR(IP15_23_20, SSI_SCK4),
1314 PINMUX_IPSR_MSEL(IP15_23_20, HRX2_A, SEL_HSCIF2_0),
1315 PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0),
1316 PINMUX_IPSR_MSEL(IP15_23_20, TS_SDAT0_A, SEL_TSIF0_0),
1317 PINMUX_IPSR_MSEL(IP15_23_20, STP_ISD_0_A, SEL_SSP1_0_0),
1318 PINMUX_IPSR_MSEL(IP15_23_20, RIF0_CLK_A, SEL_DRIF0_0),
1319 PINMUX_IPSR_MSEL(IP15_23_20, RIF2_CLK_A, SEL_DRIF2_0),
1320
1321 PINMUX_IPSR_GPSR(IP15_27_24, SSI_WS4),
1322 PINMUX_IPSR_MSEL(IP15_27_24, HTX2_A, SEL_HSCIF2_0),
1323 PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0),
1324 PINMUX_IPSR_MSEL(IP15_27_24, TS_SDEN0_A, SEL_TSIF0_0),
1325 PINMUX_IPSR_MSEL(IP15_27_24, STP_ISEN_0_A, SEL_SSP1_0_0),
1326 PINMUX_IPSR_MSEL(IP15_27_24, RIF0_SYNC_A, SEL_DRIF0_0),
1327 PINMUX_IPSR_MSEL(IP15_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
1328
1329 PINMUX_IPSR_GPSR(IP15_31_28, SSI_SDATA4),
1330 PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_A, SEL_HSCIF2_0),
1331 PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0),
1332 PINMUX_IPSR_MSEL(IP15_31_28, TS_SPSYNC0_A, SEL_TSIF0_0),
1333 PINMUX_IPSR_MSEL(IP15_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0),
1334 PINMUX_IPSR_MSEL(IP15_31_28, RIF0_D0_A, SEL_DRIF0_0),
1335 PINMUX_IPSR_MSEL(IP15_31_28, RIF2_D1_A, SEL_DRIF2_0),
1336
1337 /* IPSR16 */
1338 PINMUX_IPSR_GPSR(IP16_3_0, SSI_SCK6),
1339 PINMUX_IPSR_MSEL(IP16_3_0, SIM0_RST_D, SEL_SIMCARD_3),
1340
1341 PINMUX_IPSR_GPSR(IP16_7_4, SSI_WS6),
1342 PINMUX_IPSR_MSEL(IP16_7_4, SIM0_D_D, SEL_SIMCARD_3),
1343
1344 PINMUX_IPSR_GPSR(IP16_11_8, SSI_SDATA6),
1345 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_CLK_D, SEL_SIMCARD_3),
1346
1347 PINMUX_IPSR_GPSR(IP16_15_12, SSI_SCK78),
1348 PINMUX_IPSR_MSEL(IP16_15_12, HRX2_B, SEL_HSCIF2_1),
1349 PINMUX_IPSR_MSEL(IP16_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2),
1350 PINMUX_IPSR_MSEL(IP16_15_12, TS_SCK1_A, SEL_TSIF1_0),
1351 PINMUX_IPSR_MSEL(IP16_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0),
1352 PINMUX_IPSR_MSEL(IP16_15_12, RIF1_CLK_A, SEL_DRIF1_0),
1353 PINMUX_IPSR_MSEL(IP16_15_12, RIF3_CLK_A, SEL_DRIF3_0),
1354
1355 PINMUX_IPSR_GPSR(IP16_19_16, SSI_WS78),
1356 PINMUX_IPSR_MSEL(IP16_19_16, HTX2_B, SEL_HSCIF2_1),
1357 PINMUX_IPSR_MSEL(IP16_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2),
1358 PINMUX_IPSR_MSEL(IP16_19_16, TS_SDAT1_A, SEL_TSIF1_0),
1359 PINMUX_IPSR_MSEL(IP16_19_16, STP_ISD_1_A, SEL_SSP1_1_0),
1360 PINMUX_IPSR_MSEL(IP16_19_16, RIF1_SYNC_A, SEL_DRIF1_0),
1361 PINMUX_IPSR_MSEL(IP16_19_16, RIF3_SYNC_A, SEL_DRIF3_0),
1362
1363 PINMUX_IPSR_GPSR(IP16_23_20, SSI_SDATA7),
1364 PINMUX_IPSR_MSEL(IP16_23_20, HCTS2_N_B, SEL_HSCIF2_1),
1365 PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2),
1366 PINMUX_IPSR_MSEL(IP16_23_20, TS_SDEN1_A, SEL_TSIF1_0),
1367 PINMUX_IPSR_MSEL(IP16_23_20, STP_ISEN_1_A, SEL_SSP1_1_0),
1368 PINMUX_IPSR_MSEL(IP16_23_20, RIF1_D0_A, SEL_DRIF1_0),
1369 PINMUX_IPSR_MSEL(IP16_23_20, RIF3_D0_A, SEL_DRIF3_0),
1370 PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU_0),
1371
1372 PINMUX_IPSR_GPSR(IP16_27_24, SSI_SDATA8),
1373 PINMUX_IPSR_MSEL(IP16_27_24, HRTS2_N_B, SEL_HSCIF2_1),
1374 PINMUX_IPSR_MSEL(IP16_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2),
1375 PINMUX_IPSR_MSEL(IP16_27_24, TS_SPSYNC1_A, SEL_TSIF1_0),
1376 PINMUX_IPSR_MSEL(IP16_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0),
1377 PINMUX_IPSR_MSEL(IP16_27_24, RIF1_D1_A, SEL_DRIF1_0),
1378 PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D1_A, SEL_DRIF3_0),
1379
1380 PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI_0),
1381 PINMUX_IPSR_MSEL(IP16_31_28, HSCK2_B, SEL_HSCIF2_1),
1382 PINMUX_IPSR_MSEL(IP16_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2),
1383 PINMUX_IPSR_MSEL(IP16_31_28, HSCK1_A, SEL_HSCIF1_0),
1384 PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI_1),
1385 PINMUX_IPSR_GPSR(IP16_31_28, SCK1),
1386 PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
1387 PINMUX_IPSR_GPSR(IP16_31_28, SCK5_A),
1388
1389 /* IPSR17 */
1390 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADG_A_0),
1391 PINMUX_IPSR_GPSR(IP17_3_0, CC5_OSCOUT),
1392
1393 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADG_B_1),
1394 PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF1_0),
1395 PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
1396 PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0),
1397 PINMUX_IPSR_MSEL(IP17_7_4, TCLK1_A, SEL_TIMER_TMU_0),
1398
1399 PINMUX_IPSR_GPSR(IP17_11_8, USB0_PWEN),
1400 PINMUX_IPSR_MSEL(IP17_11_8, SIM0_RST_C, SEL_SIMCARD_2),
1401 PINMUX_IPSR_MSEL(IP17_11_8, TS_SCK1_D, SEL_TSIF1_3),
1402 PINMUX_IPSR_MSEL(IP17_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3),
1403 PINMUX_IPSR_MSEL(IP17_11_8, BPFCLK_B, SEL_FM_1),
1404 PINMUX_IPSR_MSEL(IP17_11_8, RIF3_CLK_B, SEL_DRIF3_1),
1405 PINMUX_IPSR_MSEL(IP17_11_8, HSCK2_C, SEL_HSCIF2_2),
1406
1407 PINMUX_IPSR_GPSR(IP17_15_12, USB0_OVC),
1408 PINMUX_IPSR_MSEL(IP17_15_12, SIM0_D_C, SEL_SIMCARD_2),
1409 PINMUX_IPSR_MSEL(IP17_15_12, TS_SDAT1_D, SEL_TSIF1_3),
1410 PINMUX_IPSR_MSEL(IP17_15_12, STP_ISD_1_D, SEL_SSP1_1_3),
1411 PINMUX_IPSR_MSEL(IP17_15_12, RIF3_SYNC_B, SEL_DRIF3_1),
1412 PINMUX_IPSR_MSEL(IP17_15_12, HRX2_C, SEL_HSCIF2_2),
1413
1414 PINMUX_IPSR_GPSR(IP17_19_16, USB1_PWEN),
1415 PINMUX_IPSR_MSEL(IP17_19_16, SIM0_CLK_C, SEL_SIMCARD_2),
1416 PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI_0),
1417 PINMUX_IPSR_MSEL(IP17_19_16, TS_SCK0_E, SEL_TSIF0_4),
1418 PINMUX_IPSR_MSEL(IP17_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4),
1419 PINMUX_IPSR_MSEL(IP17_19_16, FMCLK_B, SEL_FM_1),
1420 PINMUX_IPSR_MSEL(IP17_19_16, RIF2_CLK_B, SEL_DRIF2_1),
1421 PINMUX_IPSR_MSEL(IP17_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0),
1422 PINMUX_IPSR_MSEL(IP17_19_16, HTX2_C, SEL_HSCIF2_2),
1423
1424 PINMUX_IPSR_GPSR(IP17_23_20, USB1_OVC),
1425 PINMUX_IPSR_MSEL(IP17_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2),
1426 PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI_0),
1427 PINMUX_IPSR_MSEL(IP17_23_20, TS_SDAT0_E, SEL_TSIF0_4),
1428 PINMUX_IPSR_MSEL(IP17_23_20, STP_ISD_0_E, SEL_SSP1_0_4),
1429 PINMUX_IPSR_MSEL(IP17_23_20, FMIN_B, SEL_FM_1),
1430 PINMUX_IPSR_MSEL(IP17_23_20, RIF2_SYNC_B, SEL_DRIF2_1),
1431 PINMUX_IPSR_MSEL(IP17_23_20, REMOCON_B, SEL_REMOCON_1),
1432 PINMUX_IPSR_MSEL(IP17_23_20, HCTS2_N_C, SEL_HSCIF2_2),
1433
1434 PINMUX_IPSR_GPSR(IP17_27_24, USB30_PWEN),
1435 PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B),
1436 PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI_1),
1437 PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3),
1438 PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_2),
1439 PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
1440 PINMUX_IPSR_MSEL(IP17_27_24, RIF3_D0_B, SEL_DRIF3_1),
1441 PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU_1),
1442 PINMUX_IPSR_GPSR(IP17_27_24, TPU0TO0),
1443 PINMUX_IPSR_MSEL(IP17_27_24, BPFCLK_C, SEL_FM_2),
1444 PINMUX_IPSR_MSEL(IP17_27_24, HRTS2_N_C, SEL_HSCIF2_2),
1445
1446 PINMUX_IPSR_GPSR(IP17_31_28, USB30_OVC),
1447 PINMUX_IPSR_GPSR(IP17_31_28, AUDIO_CLKOUT1_B),
1448 PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI_1),
1449 PINMUX_IPSR_MSEL(IP17_31_28, TS_SPSYNC1_D, SEL_TSIF1_3),
1450 PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3),
1451 PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4),
1452 PINMUX_IPSR_MSEL(IP17_31_28, RIF3_D1_B, SEL_DRIF3_1),
1453 PINMUX_IPSR_MSEL(IP17_31_28, FSO_TOE_B, SEL_FSO_1),
1454 PINMUX_IPSR_GPSR(IP17_31_28, TPU0TO1),
1455
1456 /* IPSR18 */
1457 PINMUX_IPSR_GPSR(IP18_3_0, GP6_30),
1458 PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B),
1459 PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI_1),
1460 PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4),
1461 PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4),
1462 PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1),
1463 PINMUX_IPSR_GPSR(IP18_3_0, TPU0TO2),
1464 PINMUX_IPSR_MSEL(IP18_3_0, FSO_CFE_0_A, SEL_FSO_0),
1465 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_C, SEL_FM_2),
1466 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_D, SEL_FM_3),
1467
1468 PINMUX_IPSR_GPSR(IP18_7_4, GP6_31),
1469 PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B),
1470 PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI_1),
1471 PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4),
1472 PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
1473 PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1),
1474 PINMUX_IPSR_GPSR(IP18_7_4, TPU0TO3),
1475 PINMUX_IPSR_MSEL(IP18_7_4, FSO_CFE_1_A, SEL_FSO_0),
1476 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2),
1477 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3),
1478
1479 /* I2C */
1480 PINMUX_IPSR_NOGP(0, I2C_SEL_0_1),
1481 PINMUX_IPSR_NOGP(0, I2C_SEL_3_1),
1482 PINMUX_IPSR_NOGP(0, I2C_SEL_5_1),
1483};
1484
1485static const struct sh_pfc_pin pinmux_pins[] = {
1486 PINMUX_GPIO_GP_ALL(),
1487};
1488
1489/* - SCIF0 ------------------------------------------------------------------ */
1490static const unsigned int scif0_data_pins[] = {
1491 /* RX, TX */
1492 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1493};
1494static const unsigned int scif0_data_mux[] = {
1495 RX0_MARK, TX0_MARK,
1496};
1497static const unsigned int scif0_clk_pins[] = {
1498 /* SCK */
1499 RCAR_GP_PIN(5, 0),
1500};
1501static const unsigned int scif0_clk_mux[] = {
1502 SCK0_MARK,
1503};
1504static const unsigned int scif0_ctrl_pins[] = {
1505 /* RTS, CTS */
1506 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
1507};
1508static const unsigned int scif0_ctrl_mux[] = {
1509 RTS0_N_TANS_MARK, CTS0_N_MARK,
1510};
1511/* - SCIF1 ------------------------------------------------------------------ */
1512static const unsigned int scif1_data_a_pins[] = {
1513 /* RX, TX */
1514 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
1515};
1516static const unsigned int scif1_data_a_mux[] = {
1517 RX1_A_MARK, TX1_A_MARK,
1518};
1519static const unsigned int scif1_clk_pins[] = {
1520 /* SCK */
1521 RCAR_GP_PIN(6, 21),
1522};
1523static const unsigned int scif1_clk_mux[] = {
1524 SCK1_MARK,
1525};
1526static const unsigned int scif1_ctrl_pins[] = {
1527 /* RTS, CTS */
1528 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
1529};
1530static const unsigned int scif1_ctrl_mux[] = {
1531 RTS1_N_TANS_MARK, CTS1_N_MARK,
1532};
1533
1534static const unsigned int scif1_data_b_pins[] = {
1535 /* RX, TX */
1536 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
1537};
1538static const unsigned int scif1_data_b_mux[] = {
1539 RX1_B_MARK, TX1_B_MARK,
1540};
1541/* - SCIF2 ------------------------------------------------------------------ */
1542static const unsigned int scif2_data_a_pins[] = {
1543 /* RX, TX */
1544 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
1545};
1546static const unsigned int scif2_data_a_mux[] = {
1547 RX2_A_MARK, TX2_A_MARK,
1548};
1549static const unsigned int scif2_clk_pins[] = {
1550 /* SCK */
1551 RCAR_GP_PIN(5, 9),
1552};
1553static const unsigned int scif2_clk_mux[] = {
1554 SCK2_MARK,
1555};
1556static const unsigned int scif2_data_b_pins[] = {
1557 /* RX, TX */
1558 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
1559};
1560static const unsigned int scif2_data_b_mux[] = {
1561 RX2_B_MARK, TX2_B_MARK,
1562};
1563/* - SCIF3 ------------------------------------------------------------------ */
1564static const unsigned int scif3_data_a_pins[] = {
1565 /* RX, TX */
1566 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1567};
1568static const unsigned int scif3_data_a_mux[] = {
1569 RX3_A_MARK, TX3_A_MARK,
1570};
1571static const unsigned int scif3_clk_pins[] = {
1572 /* SCK */
1573 RCAR_GP_PIN(1, 22),
1574};
1575static const unsigned int scif3_clk_mux[] = {
1576 SCK3_MARK,
1577};
1578static const unsigned int scif3_ctrl_pins[] = {
1579 /* RTS, CTS */
1580 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
1581};
1582static const unsigned int scif3_ctrl_mux[] = {
1583 RTS3_N_TANS_MARK, CTS3_N_MARK,
1584};
1585static const unsigned int scif3_data_b_pins[] = {
1586 /* RX, TX */
1587 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
1588};
1589static const unsigned int scif3_data_b_mux[] = {
1590 RX3_B_MARK, TX3_B_MARK,
1591};
1592/* - SCIF4 ------------------------------------------------------------------ */
1593static const unsigned int scif4_data_a_pins[] = {
1594 /* RX, TX */
1595 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
1596};
1597static const unsigned int scif4_data_a_mux[] = {
1598 RX4_A_MARK, TX4_A_MARK,
1599};
1600static const unsigned int scif4_clk_a_pins[] = {
1601 /* SCK */
1602 RCAR_GP_PIN(2, 10),
1603};
1604static const unsigned int scif4_clk_a_mux[] = {
1605 SCK4_A_MARK,
1606};
1607static const unsigned int scif4_ctrl_a_pins[] = {
1608 /* RTS, CTS */
1609 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
1610};
1611static const unsigned int scif4_ctrl_a_mux[] = {
1612 RTS4_N_TANS_A_MARK, CTS4_N_A_MARK,
1613};
1614static const unsigned int scif4_data_b_pins[] = {
1615 /* RX, TX */
1616 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
1617};
1618static const unsigned int scif4_data_b_mux[] = {
1619 RX4_B_MARK, TX4_B_MARK,
1620};
1621static const unsigned int scif4_clk_b_pins[] = {
1622 /* SCK */
1623 RCAR_GP_PIN(1, 5),
1624};
1625static const unsigned int scif4_clk_b_mux[] = {
1626 SCK4_B_MARK,
1627};
1628static const unsigned int scif4_ctrl_b_pins[] = {
1629 /* RTS, CTS */
1630 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
1631};
1632static const unsigned int scif4_ctrl_b_mux[] = {
1633 RTS4_N_TANS_B_MARK, CTS4_N_B_MARK,
1634};
1635static const unsigned int scif4_data_c_pins[] = {
1636 /* RX, TX */
1637 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
1638};
1639static const unsigned int scif4_data_c_mux[] = {
1640 RX4_C_MARK, TX4_C_MARK,
1641};
1642static const unsigned int scif4_clk_c_pins[] = {
1643 /* SCK */
1644 RCAR_GP_PIN(0, 8),
1645};
1646static const unsigned int scif4_clk_c_mux[] = {
1647 SCK4_C_MARK,
1648};
1649static const unsigned int scif4_ctrl_c_pins[] = {
1650 /* RTS, CTS */
1651 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
1652};
1653static const unsigned int scif4_ctrl_c_mux[] = {
1654 RTS4_N_TANS_C_MARK, CTS4_N_C_MARK,
1655};
1656/* - SCIF5 ------------------------------------------------------------------ */
1657static const unsigned int scif5_data_a_pins[] = {
1658 /* RX, TX */
1659 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
1660};
1661static const unsigned int scif5_data_a_mux[] = {
1662 RX5_A_MARK, TX5_A_MARK,
1663};
1664static const unsigned int scif5_clk_a_pins[] = {
1665 /* SCK */
1666 RCAR_GP_PIN(6, 21),
1667};
1668static const unsigned int scif5_clk_a_mux[] = {
1669 SCK5_A_MARK,
1670};
1671
1672static const unsigned int scif5_data_b_pins[] = {
1673 /* RX, TX */
1674 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),
1675};
1676static const unsigned int scif5_data_b_mux[] = {
1677 RX5_B_MARK, TX5_B_MARK,
1678};
1679static const unsigned int scif5_clk_b_pins[] = {
1680 /* SCK */
1681 RCAR_GP_PIN(5, 0),
1682};
1683static const unsigned int scif5_clk_b_mux[] = {
1684 SCK5_B_MARK,
1685};
1686
1687/* - SCIF Clock ------------------------------------------------------------- */
1688static const unsigned int scif_clk_a_pins[] = {
1689 /* SCIF_CLK */
1690 RCAR_GP_PIN(6, 23),
1691};
1692static const unsigned int scif_clk_a_mux[] = {
1693 SCIF_CLK_A_MARK,
1694};
1695static const unsigned int scif_clk_b_pins[] = {
1696 /* SCIF_CLK */
1697 RCAR_GP_PIN(5, 9),
1698};
1699static const unsigned int scif_clk_b_mux[] = {
1700 SCIF_CLK_B_MARK,
1701};
1702
1703/* - SDHI0 ------------------------------------------------------------------ */
1704static const unsigned int sdhi0_data1_pins[] = {
1705 /* D0 */
1706 RCAR_GP_PIN(3, 2),
1707};
1708static const unsigned int sdhi0_data1_mux[] = {
1709 SD0_DAT0_MARK,
1710};
1711static const unsigned int sdhi0_data4_pins[] = {
1712 /* D[0:3] */
1713 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
1714 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
1715};
1716static const unsigned int sdhi0_data4_mux[] = {
1717 SD0_DAT0_MARK, SD0_DAT1_MARK,
1718 SD0_DAT2_MARK, SD0_DAT3_MARK,
1719};
1720static const unsigned int sdhi0_ctrl_pins[] = {
1721 /* CLK, CMD */
1722 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
1723};
1724static const unsigned int sdhi0_ctrl_mux[] = {
1725 SD0_CLK_MARK, SD0_CMD_MARK,
1726};
1727static const unsigned int sdhi0_cd_pins[] = {
1728 /* CD */
1729 RCAR_GP_PIN(3, 12),
1730};
1731static const unsigned int sdhi0_cd_mux[] = {
1732 SD0_CD_MARK,
1733};
1734static const unsigned int sdhi0_wp_pins[] = {
1735 /* WP */
1736 RCAR_GP_PIN(3, 13),
1737};
1738static const unsigned int sdhi0_wp_mux[] = {
1739 SD0_WP_MARK,
1740};
1741/* - SDHI1 ------------------------------------------------------------------ */
1742static const unsigned int sdhi1_data1_pins[] = {
1743 /* D0 */
1744 RCAR_GP_PIN(3, 8),
1745};
1746static const unsigned int sdhi1_data1_mux[] = {
1747 SD1_DAT0_MARK,
1748};
1749static const unsigned int sdhi1_data4_pins[] = {
1750 /* D[0:3] */
1751 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1752 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
1753};
1754static const unsigned int sdhi1_data4_mux[] = {
1755 SD1_DAT0_MARK, SD1_DAT1_MARK,
1756 SD1_DAT2_MARK, SD1_DAT3_MARK,
1757};
1758static const unsigned int sdhi1_ctrl_pins[] = {
1759 /* CLK, CMD */
1760 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1761};
1762static const unsigned int sdhi1_ctrl_mux[] = {
1763 SD1_CLK_MARK, SD1_CMD_MARK,
1764};
1765static const unsigned int sdhi1_cd_pins[] = {
1766 /* CD */
1767 RCAR_GP_PIN(3, 14),
1768};
1769static const unsigned int sdhi1_cd_mux[] = {
1770 SD1_CD_MARK,
1771};
1772static const unsigned int sdhi1_wp_pins[] = {
1773 /* WP */
1774 RCAR_GP_PIN(3, 15),
1775};
1776static const unsigned int sdhi1_wp_mux[] = {
1777 SD1_WP_MARK,
1778};
1779/* - SDHI2 ------------------------------------------------------------------ */
1780static const unsigned int sdhi2_data1_pins[] = {
1781 /* D0 */
1782 RCAR_GP_PIN(4, 2),
1783};
1784static const unsigned int sdhi2_data1_mux[] = {
1785 SD2_DAT0_MARK,
1786};
1787static const unsigned int sdhi2_data4_pins[] = {
1788 /* D[0:3] */
1789 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
1790 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
1791};
1792static const unsigned int sdhi2_data4_mux[] = {
1793 SD2_DAT0_MARK, SD2_DAT1_MARK,
1794 SD2_DAT2_MARK, SD2_DAT3_MARK,
1795};
1796static const unsigned int sdhi2_data8_pins[] = {
1797 /* D[0:7] */
1798 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
1799 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
1800 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1801 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
1802};
1803static const unsigned int sdhi2_data8_mux[] = {
1804 SD2_DAT0_MARK, SD2_DAT1_MARK,
1805 SD2_DAT2_MARK, SD2_DAT3_MARK,
1806 SD2_DAT4_MARK, SD2_DAT5_MARK,
1807 SD2_DAT6_MARK, SD2_DAT7_MARK,
1808};
1809static const unsigned int sdhi2_ctrl_pins[] = {
1810 /* CLK, CMD */
1811 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
1812};
1813static const unsigned int sdhi2_ctrl_mux[] = {
1814 SD2_CLK_MARK, SD2_CMD_MARK,
1815};
1816static const unsigned int sdhi2_cd_a_pins[] = {
1817 /* CD */
1818 RCAR_GP_PIN(4, 13),
1819};
1820static const unsigned int sdhi2_cd_a_mux[] = {
1821 SD2_CD_A_MARK,
1822};
1823static const unsigned int sdhi2_cd_b_pins[] = {
1824 /* CD */
1825 RCAR_GP_PIN(5, 10),
1826};
1827static const unsigned int sdhi2_cd_b_mux[] = {
1828 SD2_CD_B_MARK,
1829};
1830static const unsigned int sdhi2_wp_a_pins[] = {
1831 /* WP */
1832 RCAR_GP_PIN(4, 14),
1833};
1834static const unsigned int sdhi2_wp_a_mux[] = {
1835 SD2_WP_A_MARK,
1836};
1837static const unsigned int sdhi2_wp_b_pins[] = {
1838 /* WP */
1839 RCAR_GP_PIN(5, 11),
1840};
1841static const unsigned int sdhi2_wp_b_mux[] = {
1842 SD2_WP_B_MARK,
1843};
1844static const unsigned int sdhi2_ds_pins[] = {
1845 /* DS */
1846 RCAR_GP_PIN(4, 6),
1847};
1848static const unsigned int sdhi2_ds_mux[] = {
1849 SD2_DS_MARK,
1850};
1851/* - SDHI3 ------------------------------------------------------------------ */
1852static const unsigned int sdhi3_data1_pins[] = {
1853 /* D0 */
1854 RCAR_GP_PIN(4, 9),
1855};
1856static const unsigned int sdhi3_data1_mux[] = {
1857 SD3_DAT0_MARK,
1858};
1859static const unsigned int sdhi3_data4_pins[] = {
1860 /* D[0:3] */
1861 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
1862 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
1863};
1864static const unsigned int sdhi3_data4_mux[] = {
1865 SD3_DAT0_MARK, SD3_DAT1_MARK,
1866 SD3_DAT2_MARK, SD3_DAT3_MARK,
1867};
1868static const unsigned int sdhi3_data8_pins[] = {
1869 /* D[0:7] */
1870 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
1871 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
1872 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
1873 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
1874};
1875static const unsigned int sdhi3_data8_mux[] = {
1876 SD3_DAT0_MARK, SD3_DAT1_MARK,
1877 SD3_DAT2_MARK, SD3_DAT3_MARK,
1878 SD3_DAT4_MARK, SD3_DAT5_MARK,
1879 SD3_DAT6_MARK, SD3_DAT7_MARK,
1880};
1881static const unsigned int sdhi3_ctrl_pins[] = {
1882 /* CLK, CMD */
1883 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
1884};
1885static const unsigned int sdhi3_ctrl_mux[] = {
1886 SD3_CLK_MARK, SD3_CMD_MARK,
1887};
1888static const unsigned int sdhi3_cd_pins[] = {
1889 /* CD */
1890 RCAR_GP_PIN(4, 15),
1891};
1892static const unsigned int sdhi3_cd_mux[] = {
1893 SD3_CD_MARK,
1894};
1895static const unsigned int sdhi3_wp_pins[] = {
1896 /* WP */
1897 RCAR_GP_PIN(4, 16),
1898};
1899static const unsigned int sdhi3_wp_mux[] = {
1900 SD3_WP_MARK,
1901};
1902static const unsigned int sdhi3_ds_pins[] = {
1903 /* DS */
1904 RCAR_GP_PIN(4, 17),
1905};
1906static const unsigned int sdhi3_ds_mux[] = {
1907 SD3_DS_MARK,
1908};
1909
1910static const struct sh_pfc_pin_group pinmux_groups[] = {
1911 SH_PFC_PIN_GROUP(scif0_data),
1912 SH_PFC_PIN_GROUP(scif0_clk),
1913 SH_PFC_PIN_GROUP(scif0_ctrl),
1914 SH_PFC_PIN_GROUP(scif1_data_a),
1915 SH_PFC_PIN_GROUP(scif1_clk),
1916 SH_PFC_PIN_GROUP(scif1_ctrl),
1917 SH_PFC_PIN_GROUP(scif1_data_b),
1918 SH_PFC_PIN_GROUP(scif2_data_a),
1919 SH_PFC_PIN_GROUP(scif2_clk),
1920 SH_PFC_PIN_GROUP(scif2_data_b),
1921 SH_PFC_PIN_GROUP(scif3_data_a),
1922 SH_PFC_PIN_GROUP(scif3_clk),
1923 SH_PFC_PIN_GROUP(scif3_ctrl),
1924 SH_PFC_PIN_GROUP(scif3_data_b),
1925 SH_PFC_PIN_GROUP(scif4_data_a),
1926 SH_PFC_PIN_GROUP(scif4_clk_a),
1927 SH_PFC_PIN_GROUP(scif4_ctrl_a),
1928 SH_PFC_PIN_GROUP(scif4_data_b),
1929 SH_PFC_PIN_GROUP(scif4_clk_b),
1930 SH_PFC_PIN_GROUP(scif4_ctrl_b),
1931 SH_PFC_PIN_GROUP(scif4_data_c),
1932 SH_PFC_PIN_GROUP(scif4_clk_c),
1933 SH_PFC_PIN_GROUP(scif4_ctrl_c),
1934 SH_PFC_PIN_GROUP(scif5_data_a),
1935 SH_PFC_PIN_GROUP(scif5_clk_a),
1936 SH_PFC_PIN_GROUP(scif5_data_b),
1937 SH_PFC_PIN_GROUP(scif5_clk_b),
1938 SH_PFC_PIN_GROUP(scif_clk_a),
1939 SH_PFC_PIN_GROUP(scif_clk_b),
1940 SH_PFC_PIN_GROUP(sdhi0_data1),
1941 SH_PFC_PIN_GROUP(sdhi0_data4),
1942 SH_PFC_PIN_GROUP(sdhi0_ctrl),
1943 SH_PFC_PIN_GROUP(sdhi0_cd),
1944 SH_PFC_PIN_GROUP(sdhi0_wp),
1945 SH_PFC_PIN_GROUP(sdhi1_data1),
1946 SH_PFC_PIN_GROUP(sdhi1_data4),
1947 SH_PFC_PIN_GROUP(sdhi1_ctrl),
1948 SH_PFC_PIN_GROUP(sdhi1_cd),
1949 SH_PFC_PIN_GROUP(sdhi1_wp),
1950 SH_PFC_PIN_GROUP(sdhi2_data1),
1951 SH_PFC_PIN_GROUP(sdhi2_data4),
1952 SH_PFC_PIN_GROUP(sdhi2_data8),
1953 SH_PFC_PIN_GROUP(sdhi2_ctrl),
1954 SH_PFC_PIN_GROUP(sdhi2_cd_a),
1955 SH_PFC_PIN_GROUP(sdhi2_wp_a),
1956 SH_PFC_PIN_GROUP(sdhi2_cd_b),
1957 SH_PFC_PIN_GROUP(sdhi2_wp_b),
1958 SH_PFC_PIN_GROUP(sdhi2_ds),
1959 SH_PFC_PIN_GROUP(sdhi3_data1),
1960 SH_PFC_PIN_GROUP(sdhi3_data4),
1961 SH_PFC_PIN_GROUP(sdhi3_data8),
1962 SH_PFC_PIN_GROUP(sdhi3_ctrl),
1963 SH_PFC_PIN_GROUP(sdhi3_cd),
1964 SH_PFC_PIN_GROUP(sdhi3_wp),
1965 SH_PFC_PIN_GROUP(sdhi3_ds),
1966};
1967
1968static const char * const scif0_groups[] = {
1969 "scif0_data",
1970 "scif0_clk",
1971 "scif0_ctrl",
1972};
1973
1974static const char * const scif1_groups[] = {
1975 "scif1_data_a",
1976 "scif1_clk",
1977 "scif1_ctrl",
1978 "scif1_data_b",
1979};
1980
1981static const char * const scif2_groups[] = {
1982 "scif2_data_a",
1983 "scif2_clk",
1984 "scif2_data_b",
1985};
1986
1987static const char * const scif3_groups[] = {
1988 "scif3_data_a",
1989 "scif3_clk",
1990 "scif3_ctrl",
1991 "scif3_data_b",
1992};
1993
1994static const char * const scif4_groups[] = {
1995 "scif4_data_a",
1996 "scif4_clk_a",
1997 "scif4_ctrl_a",
1998 "scif4_data_b",
1999 "scif4_clk_b",
2000 "scif4_ctrl_b",
2001 "scif4_data_c",
2002 "scif4_clk_c",
2003 "scif4_ctrl_c",
2004};
2005
2006static const char * const scif5_groups[] = {
2007 "scif5_data_a",
2008 "scif5_clk_a",
2009 "scif5_data_b",
2010 "scif5_clk_b",
2011};
2012
2013static const char * const scif_clk_groups[] = {
2014 "scif_clk_a",
2015 "scif_clk_b",
2016};
2017
2018static const char * const sdhi0_groups[] = {
2019 "sdhi0_data1",
2020 "sdhi0_data4",
2021 "sdhi0_ctrl",
2022 "sdhi0_cd",
2023 "sdhi0_wp",
2024};
2025
2026static const char * const sdhi1_groups[] = {
2027 "sdhi1_data1",
2028 "sdhi1_data4",
2029 "sdhi1_ctrl",
2030 "sdhi1_cd",
2031 "sdhi1_wp",
2032};
2033
2034static const char * const sdhi2_groups[] = {
2035 "sdhi2_data1",
2036 "sdhi2_data4",
2037 "sdhi2_data8",
2038 "sdhi2_ctrl",
2039 "sdhi2_cd_a",
2040 "sdhi2_wp_a",
2041 "sdhi2_cd_b",
2042 "sdhi2_wp_b",
2043 "sdhi2_ds",
2044};
2045
2046static const char * const sdhi3_groups[] = {
2047 "sdhi3_data1",
2048 "sdhi3_data4",
2049 "sdhi3_data8",
2050 "sdhi3_ctrl",
2051 "sdhi3_cd",
2052 "sdhi3_wp",
2053 "sdhi3_ds",
2054};
2055
2056static const struct sh_pfc_function pinmux_functions[] = {
2057 SH_PFC_FUNCTION(scif0),
2058 SH_PFC_FUNCTION(scif1),
2059 SH_PFC_FUNCTION(scif2),
2060 SH_PFC_FUNCTION(scif3),
2061 SH_PFC_FUNCTION(scif4),
2062 SH_PFC_FUNCTION(scif5),
2063 SH_PFC_FUNCTION(scif_clk),
2064 SH_PFC_FUNCTION(sdhi0),
2065 SH_PFC_FUNCTION(sdhi1),
2066 SH_PFC_FUNCTION(sdhi2),
2067 SH_PFC_FUNCTION(sdhi3),
2068};
2069
2070static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2071#define F_(x, y) FN_##y
2072#define FM(x) FN_##x
2073 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
2074 0, 0,
2075 0, 0,
2076 0, 0,
2077 0, 0,
2078 0, 0,
2079 0, 0,
2080 0, 0,
2081 0, 0,
2082 0, 0,
2083 0, 0,
2084 0, 0,
2085 0, 0,
2086 0, 0,
2087 0, 0,
2088 0, 0,
2089 0, 0,
2090 GP_0_15_FN, GPSR0_15,
2091 GP_0_14_FN, GPSR0_14,
2092 GP_0_13_FN, GPSR0_13,
2093 GP_0_12_FN, GPSR0_12,
2094 GP_0_11_FN, GPSR0_11,
2095 GP_0_10_FN, GPSR0_10,
2096 GP_0_9_FN, GPSR0_9,
2097 GP_0_8_FN, GPSR0_8,
2098 GP_0_7_FN, GPSR0_7,
2099 GP_0_6_FN, GPSR0_6,
2100 GP_0_5_FN, GPSR0_5,
2101 GP_0_4_FN, GPSR0_4,
2102 GP_0_3_FN, GPSR0_3,
2103 GP_0_2_FN, GPSR0_2,
2104 GP_0_1_FN, GPSR0_1,
2105 GP_0_0_FN, GPSR0_0, }
2106 },
2107 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
2108 0, 0,
2109 0, 0,
2110 0, 0,
2111 GP_1_28_FN, GPSR1_28,
2112 GP_1_27_FN, GPSR1_27,
2113 GP_1_26_FN, GPSR1_26,
2114 GP_1_25_FN, GPSR1_25,
2115 GP_1_24_FN, GPSR1_24,
2116 GP_1_23_FN, GPSR1_23,
2117 GP_1_22_FN, GPSR1_22,
2118 GP_1_21_FN, GPSR1_21,
2119 GP_1_20_FN, GPSR1_20,
2120 GP_1_19_FN, GPSR1_19,
2121 GP_1_18_FN, GPSR1_18,
2122 GP_1_17_FN, GPSR1_17,
2123 GP_1_16_FN, GPSR1_16,
2124 GP_1_15_FN, GPSR1_15,
2125 GP_1_14_FN, GPSR1_14,
2126 GP_1_13_FN, GPSR1_13,
2127 GP_1_12_FN, GPSR1_12,
2128 GP_1_11_FN, GPSR1_11,
2129 GP_1_10_FN, GPSR1_10,
2130 GP_1_9_FN, GPSR1_9,
2131 GP_1_8_FN, GPSR1_8,
2132 GP_1_7_FN, GPSR1_7,
2133 GP_1_6_FN, GPSR1_6,
2134 GP_1_5_FN, GPSR1_5,
2135 GP_1_4_FN, GPSR1_4,
2136 GP_1_3_FN, GPSR1_3,
2137 GP_1_2_FN, GPSR1_2,
2138 GP_1_1_FN, GPSR1_1,
2139 GP_1_0_FN, GPSR1_0, }
2140 },
2141 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
2142 0, 0,
2143 0, 0,
2144 0, 0,
2145 0, 0,
2146 0, 0,
2147 0, 0,
2148 0, 0,
2149 0, 0,
2150 0, 0,
2151 0, 0,
2152 0, 0,
2153 0, 0,
2154 0, 0,
2155 0, 0,
2156 0, 0,
2157 0, 0,
2158 0, 0,
2159 GP_2_14_FN, GPSR2_14,
2160 GP_2_13_FN, GPSR2_13,
2161 GP_2_12_FN, GPSR2_12,
2162 GP_2_11_FN, GPSR2_11,
2163 GP_2_10_FN, GPSR2_10,
2164 GP_2_9_FN, GPSR2_9,
2165 GP_2_8_FN, GPSR2_8,
2166 GP_2_7_FN, GPSR2_7,
2167 GP_2_6_FN, GPSR2_6,
2168 GP_2_5_FN, GPSR2_5,
2169 GP_2_4_FN, GPSR2_4,
2170 GP_2_3_FN, GPSR2_3,
2171 GP_2_2_FN, GPSR2_2,
2172 GP_2_1_FN, GPSR2_1,
2173 GP_2_0_FN, GPSR2_0, }
2174 },
2175 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
2176 0, 0,
2177 0, 0,
2178 0, 0,
2179 0, 0,
2180 0, 0,
2181 0, 0,
2182 0, 0,
2183 0, 0,
2184 0, 0,
2185 0, 0,
2186 0, 0,
2187 0, 0,
2188 0, 0,
2189 0, 0,
2190 0, 0,
2191 0, 0,
2192 GP_3_15_FN, GPSR3_15,
2193 GP_3_14_FN, GPSR3_14,
2194 GP_3_13_FN, GPSR3_13,
2195 GP_3_12_FN, GPSR3_12,
2196 GP_3_11_FN, GPSR3_11,
2197 GP_3_10_FN, GPSR3_10,
2198 GP_3_9_FN, GPSR3_9,
2199 GP_3_8_FN, GPSR3_8,
2200 GP_3_7_FN, GPSR3_7,
2201 GP_3_6_FN, GPSR3_6,
2202 GP_3_5_FN, GPSR3_5,
2203 GP_3_4_FN, GPSR3_4,
2204 GP_3_3_FN, GPSR3_3,
2205 GP_3_2_FN, GPSR3_2,
2206 GP_3_1_FN, GPSR3_1,
2207 GP_3_0_FN, GPSR3_0, }
2208 },
2209 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
2210 0, 0,
2211 0, 0,
2212 0, 0,
2213 0, 0,
2214 0, 0,
2215 0, 0,
2216 0, 0,
2217 0, 0,
2218 0, 0,
2219 0, 0,
2220 0, 0,
2221 0, 0,
2222 0, 0,
2223 0, 0,
2224 GP_4_17_FN, GPSR4_17,
2225 GP_4_16_FN, GPSR4_16,
2226 GP_4_15_FN, GPSR4_15,
2227 GP_4_14_FN, GPSR4_14,
2228 GP_4_13_FN, GPSR4_13,
2229 GP_4_12_FN, GPSR4_12,
2230 GP_4_11_FN, GPSR4_11,
2231 GP_4_10_FN, GPSR4_10,
2232 GP_4_9_FN, GPSR4_9,
2233 GP_4_8_FN, GPSR4_8,
2234 GP_4_7_FN, GPSR4_7,
2235 GP_4_6_FN, GPSR4_6,
2236 GP_4_5_FN, GPSR4_5,
2237 GP_4_4_FN, GPSR4_4,
2238 GP_4_3_FN, GPSR4_3,
2239 GP_4_2_FN, GPSR4_2,
2240 GP_4_1_FN, GPSR4_1,
2241 GP_4_0_FN, GPSR4_0, }
2242 },
2243 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
2244 0, 0,
2245 0, 0,
2246 0, 0,
2247 0, 0,
2248 0, 0,
2249 0, 0,
2250 GP_5_25_FN, GPSR5_25,
2251 GP_5_24_FN, GPSR5_24,
2252 GP_5_23_FN, GPSR5_23,
2253 GP_5_22_FN, GPSR5_22,
2254 GP_5_21_FN, GPSR5_21,
2255 GP_5_20_FN, GPSR5_20,
2256 GP_5_19_FN, GPSR5_19,
2257 GP_5_18_FN, GPSR5_18,
2258 GP_5_17_FN, GPSR5_17,
2259 GP_5_16_FN, GPSR5_16,
2260 GP_5_15_FN, GPSR5_15,
2261 GP_5_14_FN, GPSR5_14,
2262 GP_5_13_FN, GPSR5_13,
2263 GP_5_12_FN, GPSR5_12,
2264 GP_5_11_FN, GPSR5_11,
2265 GP_5_10_FN, GPSR5_10,
2266 GP_5_9_FN, GPSR5_9,
2267 GP_5_8_FN, GPSR5_8,
2268 GP_5_7_FN, GPSR5_7,
2269 GP_5_6_FN, GPSR5_6,
2270 GP_5_5_FN, GPSR5_5,
2271 GP_5_4_FN, GPSR5_4,
2272 GP_5_3_FN, GPSR5_3,
2273 GP_5_2_FN, GPSR5_2,
2274 GP_5_1_FN, GPSR5_1,
2275 GP_5_0_FN, GPSR5_0, }
2276 },
2277 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
2278 GP_6_31_FN, GPSR6_31,
2279 GP_6_30_FN, GPSR6_30,
2280 GP_6_29_FN, GPSR6_29,
2281 GP_6_28_FN, GPSR6_28,
2282 GP_6_27_FN, GPSR6_27,
2283 GP_6_26_FN, GPSR6_26,
2284 GP_6_25_FN, GPSR6_25,
2285 GP_6_24_FN, GPSR6_24,
2286 GP_6_23_FN, GPSR6_23,
2287 GP_6_22_FN, GPSR6_22,
2288 GP_6_21_FN, GPSR6_21,
2289 GP_6_20_FN, GPSR6_20,
2290 GP_6_19_FN, GPSR6_19,
2291 GP_6_18_FN, GPSR6_18,
2292 GP_6_17_FN, GPSR6_17,
2293 GP_6_16_FN, GPSR6_16,
2294 GP_6_15_FN, GPSR6_15,
2295 GP_6_14_FN, GPSR6_14,
2296 GP_6_13_FN, GPSR6_13,
2297 GP_6_12_FN, GPSR6_12,
2298 GP_6_11_FN, GPSR6_11,
2299 GP_6_10_FN, GPSR6_10,
2300 GP_6_9_FN, GPSR6_9,
2301 GP_6_8_FN, GPSR6_8,
2302 GP_6_7_FN, GPSR6_7,
2303 GP_6_6_FN, GPSR6_6,
2304 GP_6_5_FN, GPSR6_5,
2305 GP_6_4_FN, GPSR6_4,
2306 GP_6_3_FN, GPSR6_3,
2307 GP_6_2_FN, GPSR6_2,
2308 GP_6_1_FN, GPSR6_1,
2309 GP_6_0_FN, GPSR6_0, }
2310 },
2311 { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) {
2312 0, 0,
2313 0, 0,
2314 0, 0,
2315 0, 0,
2316 0, 0,
2317 0, 0,
2318 0, 0,
2319 0, 0,
2320 0, 0,
2321 0, 0,
2322 0, 0,
2323 0, 0,
2324 0, 0,
2325 0, 0,
2326 0, 0,
2327 0, 0,
2328 0, 0,
2329 0, 0,
2330 0, 0,
2331 0, 0,
2332 0, 0,
2333 0, 0,
2334 0, 0,
2335 0, 0,
2336 0, 0,
2337 0, 0,
2338 0, 0,
2339 0, 0,
2340 GP_7_3_FN, GPSR7_3,
2341 GP_7_2_FN, GPSR7_2,
2342 GP_7_1_FN, GPSR7_1,
2343 GP_7_0_FN, GPSR7_0, }
2344 },
2345#undef F_
2346#undef FM
2347
2348#define F_(x, y) x,
2349#define FM(x) FN_##x,
2350 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
2351 IP0_31_28
2352 IP0_27_24
2353 IP0_23_20
2354 IP0_19_16
2355 IP0_15_12
2356 IP0_11_8
2357 IP0_7_4
2358 IP0_3_0 }
2359 },
2360 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
2361 IP1_31_28
2362 IP1_27_24
2363 IP1_23_20
2364 IP1_19_16
2365 IP1_15_12
2366 IP1_11_8
2367 IP1_7_4
2368 IP1_3_0 }
2369 },
2370 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
2371 IP2_31_28
2372 IP2_27_24
2373 IP2_23_20
2374 IP2_19_16
2375 IP2_15_12
2376 IP2_11_8
2377 IP2_7_4
2378 IP2_3_0 }
2379 },
2380 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
2381 IP3_31_28
2382 IP3_27_24
2383 IP3_23_20
2384 IP3_19_16
2385 IP3_15_12
2386 IP3_11_8
2387 IP3_7_4
2388 IP3_3_0 }
2389 },
2390 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
2391 IP4_31_28
2392 IP4_27_24
2393 IP4_23_20
2394 IP4_19_16
2395 IP4_15_12
2396 IP4_11_8
2397 IP4_7_4
2398 IP4_3_0 }
2399 },
2400 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
2401 IP5_31_28
2402 IP5_27_24
2403 IP5_23_20
2404 IP5_19_16
2405 IP5_15_12
2406 IP5_11_8
2407 IP5_7_4
2408 IP5_3_0 }
2409 },
2410 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
2411 IP6_31_28
2412 IP6_27_24
2413 IP6_23_20
2414 IP6_19_16
2415 IP6_15_12
2416 IP6_11_8
2417 IP6_7_4
2418 IP6_3_0 }
2419 },
2420 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
2421 IP7_31_28
2422 IP7_27_24
2423 IP7_23_20
2424 IP7_19_16
2425 IP7_15_12
2426 IP7_11_8
2427 IP7_7_4
2428 IP7_3_0 }
2429 },
2430 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
2431 IP8_31_28
2432 IP8_27_24
2433 IP8_23_20
2434 IP8_19_16
2435 IP8_15_12
2436 IP8_11_8
2437 IP8_7_4
2438 IP8_3_0 }
2439 },
2440 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
2441 IP9_31_28
2442 IP9_27_24
2443 IP9_23_20
2444 IP9_19_16
2445 IP9_15_12
2446 IP9_11_8
2447 IP9_7_4
2448 IP9_3_0 }
2449 },
2450 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
2451 IP10_31_28
2452 IP10_27_24
2453 IP10_23_20
2454 IP10_19_16
2455 IP10_15_12
2456 IP10_11_8
2457 IP10_7_4
2458 IP10_3_0 }
2459 },
2460 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
2461 IP11_31_28
2462 IP11_27_24
2463 IP11_23_20
2464 IP11_19_16
2465 IP11_15_12
2466 IP11_11_8
2467 IP11_7_4
2468 IP11_3_0 }
2469 },
2470 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
2471 IP12_31_28
2472 IP12_27_24
2473 IP12_23_20
2474 IP12_19_16
2475 IP12_15_12
2476 IP12_11_8
2477 IP12_7_4
2478 IP12_3_0 }
2479 },
2480 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
2481 IP13_31_28
2482 IP13_27_24
2483 IP13_23_20
2484 IP13_19_16
2485 IP13_15_12
2486 IP13_11_8
2487 IP13_7_4
2488 IP13_3_0 }
2489 },
2490 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) {
2491 IP14_31_28
2492 IP14_27_24
2493 IP14_23_20
2494 IP14_19_16
2495 IP14_15_12
2496 IP14_11_8
2497 IP14_7_4
2498 IP14_3_0 }
2499 },
2500 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) {
2501 IP15_31_28
2502 IP15_27_24
2503 IP15_23_20
2504 IP15_19_16
2505 IP15_15_12
2506 IP15_11_8
2507 IP15_7_4
2508 IP15_3_0 }
2509 },
2510 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) {
2511 IP16_31_28
2512 IP16_27_24
2513 IP16_23_20
2514 IP16_19_16
2515 IP16_15_12
2516 IP16_11_8
2517 IP16_7_4
2518 IP16_3_0 }
2519 },
2520 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) {
2521 IP17_31_28
2522 IP17_27_24
2523 IP17_23_20
2524 IP17_19_16
2525 IP17_15_12
2526 IP17_11_8
2527 IP17_7_4
2528 IP17_3_0 }
2529 },
2530 { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4) {
2531 /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2532 /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2533 /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2534 /* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2535 /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2536 /* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2537 IP18_7_4
2538 IP18_3_0 }
2539 },
2540#undef F_
2541#undef FM
2542
2543#define F_(x, y) x,
2544#define FM(x) FN_##x,
2545 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
2546 3, 2, 3, 1, 1, 1, 1, 1, 2, 1,
2547 1, 2, 1, 1, 1, 2, 2, 1, 2, 3) {
2548 MOD_SEL0_31_30_29
2549 MOD_SEL0_28_27
2550 MOD_SEL0_26_25_24
2551 MOD_SEL0_23
2552 MOD_SEL0_22
2553 MOD_SEL0_21
2554 MOD_SEL0_20
2555 MOD_SEL0_19
2556 MOD_SEL0_18_17
2557 MOD_SEL0_16
2558 MOD_SEL0_15
2559 MOD_SEL0_14_13
2560 MOD_SEL0_12
2561 MOD_SEL0_11
2562 MOD_SEL0_10
2563 MOD_SEL0_9_8
2564 MOD_SEL0_7_6
2565 MOD_SEL0_5
2566 MOD_SEL0_4_3
2567 /* RESERVED 2, 1, 0 */
2568 0, 0, 0, 0, 0, 0, 0, 0 }
2569 },
2570 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
2571 2, 3, 1, 2, 3, 1, 1, 2, 1,
2572 2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) {
2573 MOD_SEL1_31_30
2574 MOD_SEL1_29_28_27
2575 MOD_SEL1_26
2576 MOD_SEL1_25_24
2577 MOD_SEL1_23_22_21
2578 MOD_SEL1_20
2579 MOD_SEL1_19
2580 MOD_SEL1_18_17
2581 MOD_SEL1_16
2582 MOD_SEL1_15_14
2583 MOD_SEL1_13
2584 MOD_SEL1_12
2585 MOD_SEL1_11
2586 MOD_SEL1_10
2587 MOD_SEL1_9
2588 0, 0, 0, 0, /* RESERVED 8, 7 */
2589 MOD_SEL1_6
2590 MOD_SEL1_5
2591 MOD_SEL1_4
2592 MOD_SEL1_3
2593 MOD_SEL1_2
2594 MOD_SEL1_1
2595 MOD_SEL1_0 }
2596 },
2597 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
2598 1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 1,
2599 4, 4, 4, 3, 1) {
2600 MOD_SEL2_31
2601 MOD_SEL2_30
2602 MOD_SEL2_29
2603 MOD_SEL2_28_27
2604 MOD_SEL2_26
2605 MOD_SEL2_25_24_23
2606 MOD_SEL2_22
2607 MOD_SEL2_21
2608 MOD_SEL2_20
2609 MOD_SEL2_19
2610 MOD_SEL2_18
2611 MOD_SEL2_17
2612 /* RESERVED 16 */
2613 0, 0,
2614 /* RESERVED 15, 14, 13, 12 */
2615 0, 0, 0, 0, 0, 0, 0, 0,
2616 0, 0, 0, 0, 0, 0, 0, 0,
2617 /* RESERVED 11, 10, 9, 8 */
2618 0, 0, 0, 0, 0, 0, 0, 0,
2619 0, 0, 0, 0, 0, 0, 0, 0,
2620 /* RESERVED 7, 6, 5, 4 */
2621 0, 0, 0, 0, 0, 0, 0, 0,
2622 0, 0, 0, 0, 0, 0, 0, 0,
2623 /* RESERVED 3, 2, 1 */
2624 0, 0, 0, 0, 0, 0, 0, 0,
2625 MOD_SEL2_0 }
2626 },
2627 { },
2628};
2629
2630const struct sh_pfc_soc_info r8a7796_pinmux_info = {
2631 .name = "r8a77960_pfc",
2632 .unlock_reg = 0xe6060000, /* PMMR */
2633
2634 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2635
2636 .pins = pinmux_pins,
2637 .nr_pins = ARRAY_SIZE(pinmux_pins),
2638 .groups = pinmux_groups,
2639 .nr_groups = ARRAY_SIZE(pinmux_groups),
2640 .functions = pinmux_functions,
2641 .nr_functions = ARRAY_SIZE(pinmux_functions),
2642
2643 .cfg_regs = pinmux_config_regs,
2644
2645 .pinmux_data = pinmux_data,
2646 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
2647};
diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h
index 5e966c09434d..c24067edcec4 100644
--- a/drivers/pinctrl/sh-pfc/sh_pfc.h
+++ b/drivers/pinctrl/sh-pfc/sh_pfc.h
@@ -257,9 +257,11 @@ extern const struct sh_pfc_soc_info r8a7778_pinmux_info;
257extern const struct sh_pfc_soc_info r8a7779_pinmux_info; 257extern const struct sh_pfc_soc_info r8a7779_pinmux_info;
258extern const struct sh_pfc_soc_info r8a7790_pinmux_info; 258extern const struct sh_pfc_soc_info r8a7790_pinmux_info;
259extern const struct sh_pfc_soc_info r8a7791_pinmux_info; 259extern const struct sh_pfc_soc_info r8a7791_pinmux_info;
260extern const struct sh_pfc_soc_info r8a7792_pinmux_info;
260extern const struct sh_pfc_soc_info r8a7793_pinmux_info; 261extern const struct sh_pfc_soc_info r8a7793_pinmux_info;
261extern const struct sh_pfc_soc_info r8a7794_pinmux_info; 262extern const struct sh_pfc_soc_info r8a7794_pinmux_info;
262extern const struct sh_pfc_soc_info r8a7795_pinmux_info; 263extern const struct sh_pfc_soc_info r8a7795_pinmux_info;
264extern const struct sh_pfc_soc_info r8a7796_pinmux_info;
263extern const struct sh_pfc_soc_info sh7203_pinmux_info; 265extern const struct sh_pfc_soc_info sh7203_pinmux_info;
264extern const struct sh_pfc_soc_info sh7264_pinmux_info; 266extern const struct sh_pfc_soc_info sh7264_pinmux_info;
265extern const struct sh_pfc_soc_info sh7269_pinmux_info; 267extern const struct sh_pfc_soc_info sh7269_pinmux_info;
@@ -354,72 +356,99 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info;
354 * GP port style (32 ports banks) 356 * GP port style (32 ports banks)
355 */ 357 */
356 358
357#define PORT_GP_CFG_1(bank, pin, fn, sfx, cfg) fn(bank, pin, GP_##bank##_##pin, sfx, cfg) 359#define PORT_GP_CFG_1(bank, pin, fn, sfx, cfg) \
360 fn(bank, pin, GP_##bank##_##pin, sfx, cfg)
358#define PORT_GP_1(bank, pin, fn, sfx) PORT_GP_CFG_1(bank, pin, fn, sfx, 0) 361#define PORT_GP_1(bank, pin, fn, sfx) PORT_GP_CFG_1(bank, pin, fn, sfx, 0)
359 362
360#define PORT_GP_CFG_4(bank, fn, sfx, cfg) \ 363#define PORT_GP_CFG_4(bank, fn, sfx, cfg) \
361 PORT_GP_CFG_1(bank, 0, fn, sfx, cfg), PORT_GP_CFG_1(bank, 1, fn, sfx, cfg), \ 364 PORT_GP_CFG_1(bank, 0, fn, sfx, cfg), \
362 PORT_GP_CFG_1(bank, 2, fn, sfx, cfg), PORT_GP_CFG_1(bank, 3, fn, sfx, cfg) 365 PORT_GP_CFG_1(bank, 1, fn, sfx, cfg), \
366 PORT_GP_CFG_1(bank, 2, fn, sfx, cfg), \
367 PORT_GP_CFG_1(bank, 3, fn, sfx, cfg)
363#define PORT_GP_4(bank, fn, sfx) PORT_GP_CFG_4(bank, fn, sfx, 0) 368#define PORT_GP_4(bank, fn, sfx) PORT_GP_CFG_4(bank, fn, sfx, 0)
364 369
365#define PORT_GP_CFG_8(bank, fn, sfx, cfg) \ 370#define PORT_GP_CFG_8(bank, fn, sfx, cfg) \
366 PORT_GP_CFG_4(bank, fn, sfx, cfg), \ 371 PORT_GP_CFG_4(bank, fn, sfx, cfg), \
367 PORT_GP_CFG_1(bank, 4, fn, sfx, cfg), PORT_GP_CFG_1(bank, 5, fn, sfx, cfg), \ 372 PORT_GP_CFG_1(bank, 4, fn, sfx, cfg), \
368 PORT_GP_CFG_1(bank, 6, fn, sfx, cfg), PORT_GP_CFG_1(bank, 7, fn, sfx, cfg) 373 PORT_GP_CFG_1(bank, 5, fn, sfx, cfg), \
374 PORT_GP_CFG_1(bank, 6, fn, sfx, cfg), \
375 PORT_GP_CFG_1(bank, 7, fn, sfx, cfg)
369#define PORT_GP_8(bank, fn, sfx) PORT_GP_CFG_8(bank, fn, sfx, 0) 376#define PORT_GP_8(bank, fn, sfx) PORT_GP_CFG_8(bank, fn, sfx, 0)
370 377
371#define PORT_GP_CFG_9(bank, fn, sfx, cfg) \ 378#define PORT_GP_CFG_9(bank, fn, sfx, cfg) \
372 PORT_GP_CFG_8(bank, fn, sfx, cfg), \ 379 PORT_GP_CFG_8(bank, fn, sfx, cfg), \
373 PORT_GP_CFG_1(bank, 8, fn, sfx, cfg) 380 PORT_GP_CFG_1(bank, 8, fn, sfx, cfg)
374#define PORT_GP_9(bank, fn, sfx) PORT_GP_CFG_9(bank, fn, sfx, 0) 381#define PORT_GP_9(bank, fn, sfx) PORT_GP_CFG_9(bank, fn, sfx, 0)
375 382
376#define PORT_GP_CFG_12(bank, fn, sfx, cfg) \ 383#define PORT_GP_CFG_12(bank, fn, sfx, cfg) \
377 PORT_GP_CFG_8(bank, fn, sfx, cfg), \ 384 PORT_GP_CFG_9(bank, fn, sfx, cfg), \
378 PORT_GP_CFG_1(bank, 8, fn, sfx, cfg), PORT_GP_CFG_1(bank, 9, fn, sfx, cfg), \ 385 PORT_GP_CFG_1(bank, 9, fn, sfx, cfg), \
379 PORT_GP_CFG_1(bank, 10, fn, sfx, cfg), PORT_GP_CFG_1(bank, 11, fn, sfx, cfg) 386 PORT_GP_CFG_1(bank, 10, fn, sfx, cfg), \
387 PORT_GP_CFG_1(bank, 11, fn, sfx, cfg)
380#define PORT_GP_12(bank, fn, sfx) PORT_GP_CFG_12(bank, fn, sfx, 0) 388#define PORT_GP_12(bank, fn, sfx) PORT_GP_CFG_12(bank, fn, sfx, 0)
381 389
382#define PORT_GP_CFG_14(bank, fn, sfx, cfg) \ 390#define PORT_GP_CFG_14(bank, fn, sfx, cfg) \
383 PORT_GP_CFG_12(bank, fn, sfx, cfg), \ 391 PORT_GP_CFG_12(bank, fn, sfx, cfg), \
384 PORT_GP_CFG_1(bank, 12, fn, sfx, cfg), PORT_GP_CFG_1(bank, 13, fn, sfx, cfg) 392 PORT_GP_CFG_1(bank, 12, fn, sfx, cfg), \
393 PORT_GP_CFG_1(bank, 13, fn, sfx, cfg)
385#define PORT_GP_14(bank, fn, sfx) PORT_GP_CFG_14(bank, fn, sfx, 0) 394#define PORT_GP_14(bank, fn, sfx) PORT_GP_CFG_14(bank, fn, sfx, 0)
386 395
387#define PORT_GP_CFG_15(bank, fn, sfx, cfg) \ 396#define PORT_GP_CFG_15(bank, fn, sfx, cfg) \
388 PORT_GP_CFG_14(bank, fn, sfx, cfg), \ 397 PORT_GP_CFG_14(bank, fn, sfx, cfg), \
389 PORT_GP_CFG_1(bank, 14, fn, sfx, cfg) 398 PORT_GP_CFG_1(bank, 14, fn, sfx, cfg)
390#define PORT_GP_15(bank, fn, sfx) PORT_GP_CFG_15(bank, fn, sfx, 0) 399#define PORT_GP_15(bank, fn, sfx) PORT_GP_CFG_15(bank, fn, sfx, 0)
391 400
392#define PORT_GP_CFG_16(bank, fn, sfx, cfg) \ 401#define PORT_GP_CFG_16(bank, fn, sfx, cfg) \
393 PORT_GP_CFG_14(bank, fn, sfx, cfg), \ 402 PORT_GP_CFG_15(bank, fn, sfx, cfg), \
394 PORT_GP_CFG_1(bank, 14, fn, sfx, cfg), PORT_GP_CFG_1(bank, 15, fn, sfx, cfg) 403 PORT_GP_CFG_1(bank, 15, fn, sfx, cfg)
395#define PORT_GP_16(bank, fn, sfx) PORT_GP_CFG_16(bank, fn, sfx, 0) 404#define PORT_GP_16(bank, fn, sfx) PORT_GP_CFG_16(bank, fn, sfx, 0)
396 405
397#define PORT_GP_CFG_18(bank, fn, sfx, cfg) \ 406#define PORT_GP_CFG_17(bank, fn, sfx, cfg) \
398 PORT_GP_CFG_16(bank, fn, sfx, cfg), \ 407 PORT_GP_CFG_16(bank, fn, sfx, cfg), \
399 PORT_GP_CFG_1(bank, 16, fn, sfx, cfg), PORT_GP_CFG_1(bank, 17, fn, sfx, cfg) 408 PORT_GP_CFG_1(bank, 16, fn, sfx, cfg)
409#define PORT_GP_17(bank, fn, sfx) PORT_GP_CFG_17(bank, fn, sfx, 0)
410
411#define PORT_GP_CFG_18(bank, fn, sfx, cfg) \
412 PORT_GP_CFG_17(bank, fn, sfx, cfg), \
413 PORT_GP_CFG_1(bank, 17, fn, sfx, cfg)
400#define PORT_GP_18(bank, fn, sfx) PORT_GP_CFG_18(bank, fn, sfx, 0) 414#define PORT_GP_18(bank, fn, sfx) PORT_GP_CFG_18(bank, fn, sfx, 0)
401 415
402#define PORT_GP_CFG_26(bank, fn, sfx, cfg) \ 416#define PORT_GP_CFG_23(bank, fn, sfx, cfg) \
403 PORT_GP_CFG_18(bank, fn, sfx, cfg), \ 417 PORT_GP_CFG_18(bank, fn, sfx, cfg), \
404 PORT_GP_CFG_1(bank, 18, fn, sfx, cfg), PORT_GP_CFG_1(bank, 19, fn, sfx, cfg), \ 418 PORT_GP_CFG_1(bank, 18, fn, sfx, cfg), \
405 PORT_GP_CFG_1(bank, 20, fn, sfx, cfg), PORT_GP_CFG_1(bank, 21, fn, sfx, cfg), \ 419 PORT_GP_CFG_1(bank, 19, fn, sfx, cfg), \
406 PORT_GP_CFG_1(bank, 22, fn, sfx, cfg), PORT_GP_CFG_1(bank, 23, fn, sfx, cfg), \ 420 PORT_GP_CFG_1(bank, 20, fn, sfx, cfg), \
407 PORT_GP_CFG_1(bank, 24, fn, sfx, cfg), PORT_GP_CFG_1(bank, 25, fn, sfx, cfg) 421 PORT_GP_CFG_1(bank, 21, fn, sfx, cfg), \
422 PORT_GP_CFG_1(bank, 22, fn, sfx, cfg)
423#define PORT_GP_23(bank, fn, sfx) PORT_GP_CFG_23(bank, fn, sfx, 0)
424
425#define PORT_GP_CFG_26(bank, fn, sfx, cfg) \
426 PORT_GP_CFG_23(bank, fn, sfx, cfg), \
427 PORT_GP_CFG_1(bank, 23, fn, sfx, cfg), \
428 PORT_GP_CFG_1(bank, 24, fn, sfx, cfg), \
429 PORT_GP_CFG_1(bank, 25, fn, sfx, cfg)
408#define PORT_GP_26(bank, fn, sfx) PORT_GP_CFG_26(bank, fn, sfx, 0) 430#define PORT_GP_26(bank, fn, sfx) PORT_GP_CFG_26(bank, fn, sfx, 0)
409 431
410#define PORT_GP_CFG_28(bank, fn, sfx, cfg) \ 432#define PORT_GP_CFG_28(bank, fn, sfx, cfg) \
411 PORT_GP_CFG_26(bank, fn, sfx, cfg), \ 433 PORT_GP_CFG_26(bank, fn, sfx, cfg), \
412 PORT_GP_CFG_1(bank, 26, fn, sfx, cfg), PORT_GP_CFG_1(bank, 27, fn, sfx, cfg) 434 PORT_GP_CFG_1(bank, 26, fn, sfx, cfg), \
435 PORT_GP_CFG_1(bank, 27, fn, sfx, cfg)
413#define PORT_GP_28(bank, fn, sfx) PORT_GP_CFG_28(bank, fn, sfx, 0) 436#define PORT_GP_28(bank, fn, sfx) PORT_GP_CFG_28(bank, fn, sfx, 0)
414 437
415#define PORT_GP_CFG_30(bank, fn, sfx, cfg) \ 438#define PORT_GP_CFG_29(bank, fn, sfx, cfg) \
416 PORT_GP_CFG_28(bank, fn, sfx, cfg), \ 439 PORT_GP_CFG_28(bank, fn, sfx, cfg), \
417 PORT_GP_CFG_1(bank, 28, fn, sfx, cfg), PORT_GP_CFG_1(bank, 29, fn, sfx, cfg) 440 PORT_GP_CFG_1(bank, 28, fn, sfx, cfg)
441#define PORT_GP_29(bank, fn, sfx) PORT_GP_CFG_29(bank, fn, sfx, 0)
442
443#define PORT_GP_CFG_30(bank, fn, sfx, cfg) \
444 PORT_GP_CFG_29(bank, fn, sfx, cfg), \
445 PORT_GP_CFG_1(bank, 29, fn, sfx, cfg)
418#define PORT_GP_30(bank, fn, sfx) PORT_GP_CFG_30(bank, fn, sfx, 0) 446#define PORT_GP_30(bank, fn, sfx) PORT_GP_CFG_30(bank, fn, sfx, 0)
419 447
420#define PORT_GP_CFG_32(bank, fn, sfx, cfg) \ 448#define PORT_GP_CFG_32(bank, fn, sfx, cfg) \
421 PORT_GP_CFG_30(bank, fn, sfx, cfg), \ 449 PORT_GP_CFG_30(bank, fn, sfx, cfg), \
422 PORT_GP_CFG_1(bank, 30, fn, sfx, cfg), PORT_GP_CFG_1(bank, 31, fn, sfx, cfg) 450 PORT_GP_CFG_1(bank, 30, fn, sfx, cfg), \
451 PORT_GP_CFG_1(bank, 31, fn, sfx, cfg)
423#define PORT_GP_32(bank, fn, sfx) PORT_GP_CFG_32(bank, fn, sfx, 0) 452#define PORT_GP_32(bank, fn, sfx) PORT_GP_CFG_32(bank, fn, sfx, 0)
424 453
425#define PORT_GP_32_REV(bank, fn, sfx) \ 454#define PORT_GP_32_REV(bank, fn, sfx) \
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-22 14:44:13 -0400