Merge tag 'amlogic-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into next/late

Pull "Amlogic 64-bit DT changes for v4.9" from Kevin Hilman:

- add watchdog, reset, IR remote, PWM
- add secure monitor and eFuse
- add always-on (AO) domain clock and reset

* tag 'amlogic-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic:
  ARM64: dts: amlogic: gxbb: Enable NVMEM
  documentation: Add nvmem bindings documentation
  ARM64: dts: amlogic: gxbb: Enable secure monitor
  documentation: Add secure monitor bindings documentation
  ARM64: dts: meson-gxbb: Add PWM pinctrl nodes
  ARM64: dts: meson-gxbb: Enable the the IR decoder on supported boards
  ARM64: dts: meson-gxbb: Add Infrared Remote Controller decoder
  dt-bindings: media: meson-ir: Add Meson8b and GXBB compatible strings
  ARM64: dts: amlogic: add the input pin for the IR remote
  ARM64: dts: meson-gxbb: Add GXBB AO Clock and Reset node
  clk: meson: Fix invalid use of sizeof in gxbb_aoclkc_probe()
  clk: meson: Add GXBB AO Clock and Reset controller driver
  dt-bindings: clock: reset: Add GXBB AO Clock and Reset Bindings
  ARM64: DTS: meson-gxbb: switch ethernet to real clock
  ARM64: dts: amlogic: meson-gxbb: Add watchdog node

12 files changed, 575 insertions, 3 deletions

diff --git a/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt b/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt
new file mode 100644
index 000000000000..a55d31b48d6e
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt
@@ -0,0 +1,45 @@
+* Amlogic GXBB AO Clock and Reset Unit
+
+The Amlogic GXBB AO clock controller generates and supplies clock to various
+controllers within the Always-On part of the SoC.
+
+Required Properties:
+
+- compatible: should be "amlogic,gxbb-aoclkc"
+- reg: physical base address of the clock controller and length of memory
+       mapped region.
+
+- #clock-cells: should be 1.
+
+Each clock is assigned an identifier and client nodes can use this identifier
+to specify the clock which they consume. All available clocks are defined as
+preprocessor macros in the dt-bindings/clock/gxbb-aoclkc.h header and can be
+used in device tree sources.
+
+- #reset-cells: should be 1.
+
+Each reset is assigned an identifier and client nodes can use this identifier
+to specify the reset which they consume. All available resets are defined as
+preprocessor macros in the dt-bindings/reset/gxbb-aoclkc.h header and can be
+used in device tree sources.
+
+Example: AO Clock controller node:
+
+        clkc_AO: clock-controller@040 {
+                compatible = "amlogic,gxbb-aoclkc";
+                reg = <0x0 0x040 0x0 0x4>;
+                #clock-cells = <1>;
+                #reset-cells = <1>;
+        };
+
+Example: UART controller node that consumes the clock and reset generated
+  by the clock controller:
+
+        uart_AO: serial@4c0 {
+                compatible = "amlogic,meson-uart";
+                reg = <0x4c0 0x14>;
+                interrupts = <0 90 1>;
+                clocks = <&clkc_AO CLKID_AO_UART1>;
+                resets = <&clkc_AO RESET_AO_UART1>;
+                status = "disabled";
+        };
diff --git a/Documentation/devicetree/bindings/firmware/meson/meson_sm.txt b/Documentation/devicetree/bindings/firmware/meson/meson_sm.txt
new file mode 100644
index 000000000000..c248cd44f727
--- /dev/null
+++ b/Documentation/devicetree/bindings/firmware/meson/meson_sm.txt
@@ -0,0 +1,15 @@
+* Amlogic Secure Monitor
+
+In the Amlogic SoCs the Secure Monitor code is used to provide access to the
+NVMEM, enable JTAG, set USB boot, etc...
+
+Required properties for the secure monitor node:
+- compatible: Should be "amlogic,meson-gxbb-sm"
+
+Example:
+
+        firmware {
+                sm: secure-monitor {
+                        compatible = "amlogic,meson-gxbb-sm";
+                };
+        };
diff --git a/Documentation/devicetree/bindings/media/meson-ir.txt b/Documentation/devicetree/bindings/media/meson-ir.txt
index 407848e85f31..e7e3f3c4fc8f 100644
--- a/Documentation/devicetree/bindings/media/meson-ir.txt
+++ b/Documentation/devicetree/bindings/media/meson-ir.txt
@@ -1,7 +1,10 @@
 * Amlogic Meson IR remote control receiver
 
 Required properties:
- - compatible   : should be "amlogic,meson6-ir"
+ - compatible   : depending on the platform this should be one of:
+                  - "amlogic,meson6-ir"
+                  - "amlogic,meson8b-ir"
+                  - "amlogic,meson-gxbb-ir"
  - reg          : physical base address and length of the device registers
  - interrupts   : a single specifier for the interrupt from the device
 
diff --git a/Documentation/devicetree/bindings/nvmem/amlogic-efuse.txt b/Documentation/devicetree/bindings/nvmem/amlogic-efuse.txt
new file mode 100644
index 000000000000..fafd85bd67a6
--- /dev/null
+++ b/Documentation/devicetree/bindings/nvmem/amlogic-efuse.txt
@@ -0,0 +1,39 @@
+= Amlogic eFuse device tree bindings =
+
+Required properties:
+- compatible: should be "amlogic,meson-gxbb-efuse"
+
+= Data cells =
+Are child nodes of eFuse, bindings of which as described in
+bindings/nvmem/nvmem.txt
+
+Example:
+
+        efuse: efuse {
+                compatible = "amlogic,meson-gxbb-efuse";
+                #address-cells = <1>;
+                #size-cells = <1>;
+
+                sn: sn@14 {
+                        reg = <0x14 0x10>;
+                };
+
+                eth_mac: eth_mac@34 {
+                        reg = <0x34 0x10>;
+                };
+
+                bid: bid@46 {
+                        reg = <0x46 0x30>;
+                };
+        };
+
+= Data consumers =
+Are device nodes which consume nvmem data cells.
+
+For example:
+
+        eth_mac {
+                ...
+                nvmem-cells = <&eth_mac>;
+                nvmem-cell-names = "eth_mac";
+        };
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
index 90a84c514d3d..233703529201 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
@@ -87,3 +87,8 @@
         pinctrl-names = "default";
 };
 
+&ir {
+        status = "okay";
+        pinctrl-0 = <&remote_input_ao_pins>;
+        pinctrl-names = "default";
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi
index f4f30f674b4c..0eaca7277cfd 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi
@@ -72,3 +72,8 @@
         pinctrl-names = "default";
 };
 
+&ir {
+        status = "okay";
+        pinctrl-0 = <&remote_input_ao_pins>;
+        pinctrl-names = "default";
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi
index 54bb7c739089..560770e6c648 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi
@@ -60,3 +60,9 @@
         pinctrl-names = "default";
 
 };
+
+&ir {
+        status = "okay";
+        pinctrl-0 = <&remote_input_ao_pins>;
+        pinctrl-names = "default";
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
index e502c24b0ac7..762f3681a49c 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
@@ -45,6 +45,9 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/gpio/meson-gxbb-gpio.h>
 #include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
+#include <dt-bindings/clock/gxbb-clkc.h>
+#include <dt-bindings/clock/gxbb-aoclkc.h>
+#include <dt-bindings/reset/gxbb-aoclkc.h>
 
 / {
         compatible = "amlogic,meson-gxbb";
@@ -99,6 +102,30 @@
                 method = "smc";
         };
 
+        firmware {
+                sm: secure-monitor {
+                        compatible = "amlogic,meson-gxbb-sm";
+                };
+        };
+
+        efuse: efuse {
+                compatible = "amlogic,meson-gxbb-efuse";
+                #address-cells = <1>;
+                #size-cells = <1>;
+
+                sn: sn@14 {
+                        reg = <0x14 0x10>;
+                };
+
+                eth_mac: eth_mac@34 {
+                        reg = <0x34 0x10>;
+                };
+
+                bid: bid@46 {
+                        reg = <0x46 0x30>;
+                };
+        };
+
         timer {
                 compatible = "arm,armv8-timer";
                 interrupts = <GIC_PPI 13
@@ -160,6 +187,12 @@
                                 clocks = <&xtal>;
                                 status = "disabled";
                         };
+
+                        watchdog@98d0 {
+                                compatible = "amlogic,meson-gxbb-wdt";
+                                reg = <0x0 0x098d0 0x0 0x10>;
+                                clocks = <&xtal>;
+                        };
                 };
 
                 gic: interrupt-controller@c4301000 {
@@ -203,6 +236,48 @@
                                                 function = "uart_ao";
                                         };
                                 };
+
+                                remote_input_ao_pins: remote_input_ao {
+                                        mux {
+                                                groups = "remote_input_ao";
+                                                function = "remote_input_ao";
+                                        };
+                                };
+
+                                pwm_ao_a_3_pins: pwm_ao_a_3 {
+                                        mux {
+                                                groups = "pwm_ao_a_3";
+                                                function = "pwm_ao_a_3";
+                                        };
+                                };
+
+                                pwm_ao_a_6_pins: pwm_ao_a_6 {
+                                        mux {
+                                                groups = "pwm_ao_a_6";
+                                                function = "pwm_ao_a_6";
+                                        };
+                                };
+
+                                pwm_ao_a_12_pins: pwm_ao_a_12 {
+                                        mux {
+                                                groups = "pwm_ao_a_12";
+                                                function = "pwm_ao_a_12";
+                                        };
+                                };
+
+                                pwm_ao_b_pins: pwm_ao_b {
+                                        mux {
+                                                groups = "pwm_ao_b";
+                                                function = "pwm_ao_b";
+                                        };
+                                };
+                        };
+
+                        clkc_AO: clock-controller@040 {
+                                compatible = "amlogic,gxbb-aoclkc";
+                                reg = <0x0 0x00040 0x0 0x4>;
+                                #clock-cells = <1>;
+                                #reset-cells = <1>;
                         };
 
                         uart_AO: serial@4c0 {
@@ -212,6 +287,13 @@
                                 clocks = <&xtal>;
                                 status = "disabled";
                         };
+
+                        ir: ir@580 {
+                                compatible = "amlogic,meson-gxbb-ir";
+                                reg = <0x0 0x00580 0x0 0x40>;
+                                interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
+                                status = "disabled";
+                        };
                 };
 
                 periphs: periphs@c8834000 {
@@ -306,6 +388,55 @@
                                                 function = "eth";
                                         };
                                 };
+
+                                pwm_a_x_pins: pwm_a_x {
+                                        mux {
+                                                groups = "pwm_a_x";
+                                                function = "pwm_a_x";
+                                        };
+                                };
+
+                                pwm_a_y_pins: pwm_a_y {
+                                        mux {
+                                                groups = "pwm_a_y";
+                                                function = "pwm_a_y";
+                                        };
+                                };
+
+                                pwm_b_pins: pwm_b {
+                                        mux {
+                                                groups = "pwm_b";
+                                                function = "pwm_b";
+                                        };
+                                };
+
+                                pwm_d_pins: pwm_d {
+                                        mux {
+                                                groups = "pwm_d";
+                                                function = "pwm_d";
+                                        };
+                                };
+
+                                pwm_e_pins: pwm_e {
+                                        mux {
+                                                groups = "pwm_e";
+                                                function = "pwm_e";
+                                        };
+                                };
+
+                                pwm_f_x_pins: pwm_f_x {
+                                        mux {
+                                                groups = "pwm_f_x";
+                                                function = "pwm_f_x";
+                                        };
+                                };
+
+                                pwm_f_y_pins: pwm_f_y {
+                                        mux {
+                                                groups = "pwm_f_y";
+                                                function = "pwm_f_y";
+                                        };
+                                };
                         };
                 };
 
@@ -337,7 +468,7 @@
                                0x0 0xc8834540 0x0 0x4>;
                         interrupts = <0 8 1>;
                         interrupt-names = "macirq";
-                        clocks = <&xtal>;
+                        clocks = <&clkc CLKID_ETH>;
                         clock-names = "stmmaceth";
                         phy-mode = "rgmii";
                         status = "disabled";
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index 197e40175166..d4cd4a35d74e 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -4,4 +4,4 @@
 
 obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-cpu.o clk-mpll.o
 obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b-clkc.o
-obj-$(CONFIG_COMMON_CLK_GXBB)    += gxbb.o
+obj-$(CONFIG_COMMON_CLK_GXBB)    += gxbb.o gxbb-aoclk.o
diff --git a/drivers/clk/meson/gxbb-aoclk.c b/drivers/clk/meson/gxbb-aoclk.c
new file mode 100644
index 000000000000..b45c5fba7e35
--- /dev/null
+++ b/drivers/clk/meson/gxbb-aoclk.c
@@ -0,0 +1,191 @@
+/*
+ * This file is provided under a dual BSD/GPLv2 license.  When using or
+ * redistributing this file, you may do so under either license.
+ *
+ * GPL LICENSE SUMMARY
+ *
+ * Copyright (c) 2016 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
+ * The full GNU General Public License is included in this distribution
+ * in the file called COPYING.
+ *
+ * BSD LICENSE
+ *
+ * Copyright (c) 2016 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *   * Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in
+ *     the documentation and/or other materials provided with the
+ *     distribution.
+ *   * Neither the name of Intel Corporation nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include <linux/clk-provider.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/reset-controller.h>
+#include <linux/init.h>
+#include <dt-bindings/clock/gxbb-aoclkc.h>
+#include <dt-bindings/reset/gxbb-aoclkc.h>
+
+static DEFINE_SPINLOCK(gxbb_aoclk_lock);
+
+struct gxbb_aoclk_reset_controller {
+        struct reset_controller_dev reset;
+        unsigned int *data;
+        void __iomem *base;
+};
+
+static int gxbb_aoclk_do_reset(struct reset_controller_dev *rcdev,
+                               unsigned long id)
+{
+        struct gxbb_aoclk_reset_controller *reset =
+                container_of(rcdev, struct gxbb_aoclk_reset_controller, reset);
+
+        writel(BIT(reset->data[id]), reset->base);
+
+        return 0;
+}
+
+static const struct reset_control_ops gxbb_aoclk_reset_ops = {
+        .reset = gxbb_aoclk_do_reset,
+};
+
+#define GXBB_AO_GATE(_name, _bit)                                       \
+static struct clk_gate _name##_ao = {                                   \
+        .reg = (void __iomem *)0,                                       \
+        .bit_idx = (_bit),                                              \
+        .lock = &gxbb_aoclk_lock,                                       \
+        .hw.init = &(struct clk_init_data) {                            \
+                .name = #_name "_ao",                                   \
+                .ops = &clk_gate_ops,                                   \
+                .parent_names = (const char *[]){ "clk81" },            \
+                .num_parents = 1,                                       \
+                .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED),     \
+        },                                                              \
+}
+
+GXBB_AO_GATE(remote, 0);
+GXBB_AO_GATE(i2c_master, 1);
+GXBB_AO_GATE(i2c_slave, 2);
+GXBB_AO_GATE(uart1, 3);
+GXBB_AO_GATE(uart2, 5);
+GXBB_AO_GATE(ir_blaster, 6);
+
+static unsigned int gxbb_aoclk_reset[] = {
+        [RESET_AO_REMOTE] = 16,
+        [RESET_AO_I2C_MASTER] = 18,
+        [RESET_AO_I2C_SLAVE] = 19,
+        [RESET_AO_UART1] = 17,
+        [RESET_AO_UART2] = 22,
+        [RESET_AO_IR_BLASTER] = 23,
+};
+
+static struct clk_gate *gxbb_aoclk_gate[] = {
+        [CLKID_AO_REMOTE] = &remote_ao,
+        [CLKID_AO_I2C_MASTER] = &i2c_master_ao,
+        [CLKID_AO_I2C_SLAVE] = &i2c_slave_ao,
+        [CLKID_AO_UART1] = &uart1_ao,
+        [CLKID_AO_UART2] = &uart2_ao,
+        [CLKID_AO_IR_BLASTER] = &ir_blaster_ao,
+};
+
+static struct clk_hw_onecell_data gxbb_aoclk_onecell_data = {
+        .hws = {
+                [CLKID_AO_REMOTE] = &remote_ao.hw,
+                [CLKID_AO_I2C_MASTER] = &i2c_master_ao.hw,
+                [CLKID_AO_I2C_SLAVE] = &i2c_slave_ao.hw,
+                [CLKID_AO_UART1] = &uart1_ao.hw,
+                [CLKID_AO_UART2] = &uart2_ao.hw,
+                [CLKID_AO_IR_BLASTER] = &ir_blaster_ao.hw,
+        },
+        .num = ARRAY_SIZE(gxbb_aoclk_gate),
+};
+
+static int gxbb_aoclkc_probe(struct platform_device *pdev)
+{
+        struct resource *res;
+        void __iomem *base;
+        int ret, clkid;
+        struct device *dev = &pdev->dev;
+        struct gxbb_aoclk_reset_controller *rstc;
+
+        rstc = devm_kzalloc(dev, sizeof(*rstc), GFP_KERNEL);
+        if (!rstc)
+                return -ENOMEM;
+
+        /* Generic clocks */
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        base = devm_ioremap_resource(dev, res);
+        if (IS_ERR(base))
+                return PTR_ERR(base);
+
+        /* Reset Controller */
+        rstc->base = base;
+        rstc->data = gxbb_aoclk_reset;
+        rstc->reset.ops = &gxbb_aoclk_reset_ops;
+        rstc->reset.nr_resets = ARRAY_SIZE(gxbb_aoclk_reset);
+        rstc->reset.of_node = dev->of_node;
+        ret = devm_reset_controller_register(dev, &rstc->reset);
+
+        /*
+         * Populate base address and register all clks
+         */
+        for (clkid = 0; clkid < gxbb_aoclk_onecell_data.num; clkid++) {
+                gxbb_aoclk_gate[clkid]->reg = base;
+
+                ret = devm_clk_hw_register(dev,
+                                        gxbb_aoclk_onecell_data.hws[clkid]);
+                if (ret)
+                        return ret;
+        }
+
+        return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
+                        &gxbb_aoclk_onecell_data);
+}
+
+static const struct of_device_id gxbb_aoclkc_match_table[] = {
+        { .compatible = "amlogic,gxbb-aoclkc" },
+        { }
+};
+
+static struct platform_driver gxbb_aoclkc_driver = {
+        .probe          = gxbb_aoclkc_probe,
+        .driver         = {
+                .name   = "gxbb-aoclkc",
+                .of_match_table = gxbb_aoclkc_match_table,
+        },
+};
+builtin_platform_driver(gxbb_aoclkc_driver);
diff --git a/include/dt-bindings/clock/gxbb-aoclkc.h b/include/dt-bindings/clock/gxbb-aoclkc.h
new file mode 100644
index 000000000000..31751482d13c
--- /dev/null
+++ b/include/dt-bindings/clock/gxbb-aoclkc.h
@@ -0,0 +1,66 @@
+/*
+ * This file is provided under a dual BSD/GPLv2 license.  When using or
+ * redistributing this file, you may do so under either license.
+ *
+ * GPL LICENSE SUMMARY
+ *
+ * Copyright (c) 2016 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
+ * The full GNU General Public License is included in this distribution
+ * in the file called COPYING.
+ *
+ * BSD LICENSE
+ *
+ * Copyright (c) 2016 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *   * Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in
+ *     the documentation and/or other materials provided with the
+ *     distribution.
+ *   * Neither the name of Intel Corporation nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef DT_BINDINGS_CLOCK_AMLOGIC_MESON_GXBB_AOCLK
+#define DT_BINDINGS_CLOCK_AMLOGIC_MESON_GXBB_AOCLK
+
+#define CLKID_AO_REMOTE         0
+#define CLKID_AO_I2C_MASTER     1
+#define CLKID_AO_I2C_SLAVE      2
+#define CLKID_AO_UART1          3
+#define CLKID_AO_UART2          4
+#define CLKID_AO_IR_BLASTER     5
+
+#endif
diff --git a/include/dt-bindings/reset/gxbb-aoclkc.h b/include/dt-bindings/reset/gxbb-aoclkc.h
new file mode 100644
index 000000000000..9e3fd60c309c
--- /dev/null
+++ b/include/dt-bindings/reset/gxbb-aoclkc.h
@@ -0,0 +1,66 @@
+/*
+ * This file is provided under a dual BSD/GPLv2 license.  When using or
+ * redistributing this file, you may do so under either license.
+ *
+ * GPL LICENSE SUMMARY
+ *
+ * Copyright (c) 2016 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
+ * The full GNU General Public License is included in this distribution
+ * in the file called COPYING.
+ *
+ * BSD LICENSE
+ *
+ * Copyright (c) 2016 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *   * Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in
+ *     the documentation and/or other materials provided with the
+ *     distribution.
+ *   * Neither the name of Intel Corporation nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef DT_BINDINGS_RESET_AMLOGIC_MESON_GXBB_AOCLK
+#define DT_BINDINGS_RESET_AMLOGIC_MESON_GXBB_AOCLK
+
+#define RESET_AO_REMOTE         0
+#define RESET_AO_I2C_MASTER     1
+#define RESET_AO_I2C_SLAVE      2
+#define RESET_AO_UART1          3
+#define RESET_AO_UART2          4
+#define RESET_AO_IR_BLASTER     5
+
+#endif