diff options
| author | Eric Engestrom <eric@engestrom.ch> | 2016-04-24 20:24:04 -0400 |
|---|---|---|
| committer | Vineet Gupta <vgupta@synopsys.com> | 2016-04-25 04:51:09 -0400 |
| commit | da67e68c0e4601e87612918496fd8c7d72795e50 (patch) | |
| tree | 5a762aa6da6b2d19383f29db7a50798366d57125 | |
| parent | d9676fa152c83b82137af950b1d4f629045d90c9 (diff) | |
Documentation: dt: arc: fix spelling mistakes
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
| -rw-r--r-- | Documentation/devicetree/bindings/arc/archs-pct.txt | 2 | ||||
| -rw-r--r-- | Documentation/devicetree/bindings/arc/pct.txt | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/arc/archs-pct.txt b/Documentation/devicetree/bindings/arc/archs-pct.txt index 1ae98b87c640..e4b9dcee6d41 100644 --- a/Documentation/devicetree/bindings/arc/archs-pct.txt +++ b/Documentation/devicetree/bindings/arc/archs-pct.txt | |||
| @@ -2,7 +2,7 @@ | |||
| 2 | 2 | ||
| 3 | The ARC HS can be configured with a pipeline performance monitor for counting | 3 | The ARC HS can be configured with a pipeline performance monitor for counting |
| 4 | CPU and cache events like cache misses and hits. Like conventional PCT there | 4 | CPU and cache events like cache misses and hits. Like conventional PCT there |
| 5 | are 100+ hardware conditions dynamically mapped to upto 32 counters. | 5 | are 100+ hardware conditions dynamically mapped to up to 32 counters. |
| 6 | It also supports overflow interrupts. | 6 | It also supports overflow interrupts. |
| 7 | 7 | ||
| 8 | Required properties: | 8 | Required properties: |
diff --git a/Documentation/devicetree/bindings/arc/pct.txt b/Documentation/devicetree/bindings/arc/pct.txt index 7b9588444f20..4e874d9a38a6 100644 --- a/Documentation/devicetree/bindings/arc/pct.txt +++ b/Documentation/devicetree/bindings/arc/pct.txt | |||
| @@ -2,7 +2,7 @@ | |||
| 2 | 2 | ||
| 3 | The ARC700 can be configured with a pipeline performance monitor for counting | 3 | The ARC700 can be configured with a pipeline performance monitor for counting |
| 4 | CPU and cache events like cache misses and hits. Like conventional PCT there | 4 | CPU and cache events like cache misses and hits. Like conventional PCT there |
| 5 | are 100+ hardware conditions dynamically mapped to upto 32 counters | 5 | are 100+ hardware conditions dynamically mapped to up to 32 counters |
| 6 | 6 | ||
| 7 | Note that: | 7 | Note that: |
| 8 | * The ARC 700 PCT does not support interrupts; although HW events may be | 8 | * The ARC 700 PCT does not support interrupts; although HW events may be |