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authorArnd Bergmann <arnd@arndb.de>2018-09-28 11:32:55 -0400
committerArnd Bergmann <arnd@arndb.de>2018-09-28 11:39:58 -0400
commitd4db2b19eb0ce4f95f75ea64d1efbec0fbc908f0 (patch)
tree1a0eac788dfe2d80571ec4c64e2d5b14d1dc82ee
parentfb5c84ce00d9321433b5709c205e32049201fa62 (diff)
parentebea2a43fdafdbce918bd7e200b709d6c33b9f3b (diff)
Merge tag 'tegra-for-4.20-arm-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/dt
ARM: tegra: Device tree changes for v4.20-rc1 This contains a massive amount of changes from Marcel Ziswiler for various boards by Toradex. * tag 'tegra-for-4.20-arm-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: (129 commits) ARM: dts: paz00: fix wakeup gpio keycode ARM: tegra: tegra20: Fix mixed tabs-spaces indentation ARM: tegra: colibri_t20: add eval board device tree ARM: tegra: colibri_t20: rename ac97 label to tegra_ac97 ARM: tegra: colibri_t20: get rid of fake clocks simple bus ARM: tegra: colibri_t20: rename tps6586x@34 and drop unused pmic label ARM: tegra: colibri_t20: iris: drop unused i2c_ddc label ARM: tegra: colibri_t20: rename i2c_ddc to hdmi_ddc ARM: tegra: colibri_t20: drop module level model and compatible ARM: tegra: colibri_t20: iris: add colibri ssp support ARM: tegra: colibri_t20: iris: simplify model and compatible properties ARM: tegra: colibri_t20: simplify model and compatible properties ARM: tegra: colibri_t20: add compatibility comment ARM: tegra: colibri_t20: annotate/move sd card detect ARM: tegra: colibri_t20: add gpio hogs for gmi_wr_n buffers ARM: tegra: colibri_t20: add gpio hog to unreset usb ethernet chip ARM: tegra: colibri_t20: add i2c-thermtrip ARM: tegra: colibri_t20: annotate/rename lm95245 temperature sensor ARM: tegra: colibri_t20: iris: add dr_mode property ARM: tegra: colibri_t20: iris: add gpio wakeup key ... Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat
-rw-r--r--Documentation/devicetree/bindings/arm/tegra.txt9
-rw-r--r--Documentation/devicetree/bindings/vendor-prefixes.txt1
-rw-r--r--arch/arm/boot/dts/Makefile2
-rw-r--r--arch/arm/boot/dts/tegra124-apalis-eval.dts40
-rw-r--r--arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts43
-rw-r--r--arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi452
-rw-r--r--arch/arm/boot/dts/tegra124-apalis.dtsi451
-rw-r--r--arch/arm/boot/dts/tegra20-colibri-eval-v3.dts262
-rw-r--r--arch/arm/boot/dts/tegra20-colibri-iris.dts200
-rw-r--r--arch/arm/boot/dts/tegra20-colibri.dtsi657
-rw-r--r--arch/arm/boot/dts/tegra20-paz00.dts12
-rw-r--r--arch/arm/boot/dts/tegra20.dtsi28
-rw-r--r--arch/arm/boot/dts/tegra30-apalis-eval.dts148
-rw-r--r--arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts266
-rw-r--r--arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi1189
-rw-r--r--arch/arm/boot/dts/tegra30-apalis.dtsi705
-rw-r--r--arch/arm/boot/dts/tegra30-colibri-eval-v3.dts130
-rw-r--r--arch/arm/boot/dts/tegra30-colibri.dtsi780
-rw-r--r--arch/arm/boot/dts/tegra30.dtsi10
19 files changed, 4173 insertions, 1212 deletions
diff --git a/Documentation/devicetree/bindings/arm/tegra.txt b/Documentation/devicetree/bindings/arm/tegra.txt
index 32f62bb7006d..c59b15f64346 100644
--- a/Documentation/devicetree/bindings/arm/tegra.txt
+++ b/Documentation/devicetree/bindings/arm/tegra.txt
@@ -47,12 +47,17 @@ board-specific compatible values:
47 nvidia,ventana 47 nvidia,ventana
48 toradex,apalis_t30 48 toradex,apalis_t30
49 toradex,apalis_t30-eval 49 toradex,apalis_t30-eval
50 toradex,apalis_t30-v1.1
51 toradex,apalis_t30-v1.1-eval
50 toradex,apalis-tk1 52 toradex,apalis-tk1
51 toradex,apalis-tk1-eval 53 toradex,apalis-tk1-eval
52 toradex,colibri_t20-512 54 toradex,apalis-tk1-v1.2
55 toradex,apalis-tk1-v1.2-eval
56 toradex,colibri_t20
57 toradex,colibri_t20-eval-v3
58 toradex,colibri_t20-iris
53 toradex,colibri_t30 59 toradex,colibri_t30
54 toradex,colibri_t30-eval-v3 60 toradex,colibri_t30-eval-v3
55 toradex,iris
56 61
57Trusted Foundations 62Trusted Foundations
58------------------------------------------- 63-------------------------------------------
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 1c63d2c2d48f..b84a705c5c14 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -298,6 +298,7 @@ pine64 Pine64
298pixcir PIXCIR MICROELECTRONICS Co., Ltd 298pixcir PIXCIR MICROELECTRONICS Co., Ltd
299plathome Plat'Home Co., Ltd. 299plathome Plat'Home Co., Ltd.
300plda PLDA 300plda PLDA
301plx Broadcom Corporation (formerly PLX Technology)
301portwell Portwell Inc. 302portwell Portwell Inc.
302poslab Poslab Technology Co., Ltd. 303poslab Poslab Technology Co., Ltd.
303powervr PowerVR (deprecated, use img) 304powervr PowerVR (deprecated, use img)
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index dbf198b95377..626e73186685 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1063,6 +1063,7 @@ dtb-$(CONFIG_ARCH_TANGO) += \
1063 tango4-vantage-1172.dtb 1063 tango4-vantage-1172.dtb
1064dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \ 1064dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \
1065 tegra20-harmony.dtb \ 1065 tegra20-harmony.dtb \
1066 tegra20-colibri-eval-v3.dtb \
1066 tegra20-colibri-iris.dtb \ 1067 tegra20-colibri-iris.dtb \
1067 tegra20-medcom-wide.dtb \ 1068 tegra20-medcom-wide.dtb \
1068 tegra20-paz00.dtb \ 1069 tegra20-paz00.dtb \
@@ -1073,6 +1074,7 @@ dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \
1073 tegra20-ventana.dtb 1074 tegra20-ventana.dtb
1074dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += \ 1075dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += \
1075 tegra30-apalis-eval.dtb \ 1076 tegra30-apalis-eval.dtb \
1077 tegra30-apalis-v1.1-eval.dtb \
1076 tegra30-beaver.dtb \ 1078 tegra30-beaver.dtb \
1077 tegra30-cardhu-a02.dtb \ 1079 tegra30-cardhu-a02.dtb \
1078 tegra30-cardhu-a04.dtb \ 1080 tegra30-cardhu-a04.dtb \
diff --git a/arch/arm/boot/dts/tegra124-apalis-eval.dts b/arch/arm/boot/dts/tegra124-apalis-eval.dts
index a6ad759dddb4..eaee10ef6512 100644
--- a/arch/arm/boot/dts/tegra124-apalis-eval.dts
+++ b/arch/arm/boot/dts/tegra124-apalis-eval.dts
@@ -72,6 +72,7 @@
72 host1x@50000000 { 72 host1x@50000000 {
73 hdmi@54280000 { 73 hdmi@54280000 {
74 status = "okay"; 74 status = "okay";
75 hdmi-supply = <&reg_5v0>;
75 }; 76 };
76 }; 77 };
77 78
@@ -122,7 +123,7 @@
122 /* 123 /*
123 * GEN2_I2C: I2C2_SDA/SCL (DDC) on MXM3 pin 205/207 (e.g. display EDID) 124 * GEN2_I2C: I2C2_SDA/SCL (DDC) on MXM3 pin 205/207 (e.g. display EDID)
124 */ 125 */
125 hdmi_ddc: i2c@7000c400 { 126 i2c@7000c400 {
126 status = "okay"; 127 status = "okay";
127 }; 128 };
128 129
@@ -141,29 +142,19 @@
141 spi@7000d400 { 142 spi@7000d400 {
142 status = "okay"; 143 status = "okay";
143 spi-max-frequency = <50000000>; 144 spi-max-frequency = <50000000>;
144
145 spidev0: spidev@0 {
146 compatible = "spidev";
147 reg = <0>;
148 spi-max-frequency = <50000000>;
149 };
150 }; 145 };
151 146
152 /* SPI4: Apalis SPI2 */ 147 /* SPI4: Apalis SPI2 */
153 spi@7000da00 { 148 spi@7000da00 {
154 status = "okay"; 149 status = "okay";
155 spi-max-frequency = <50000000>; 150 spi-max-frequency = <50000000>;
156
157 spidev1: spidev@0 {
158 compatible = "spidev";
159 reg = <0>;
160 spi-max-frequency = <50000000>;
161 };
162 }; 151 };
163 152
164 /* Apalis Serial ATA */ 153 /* Apalis Serial ATA */
165 sata@70020000 { 154 sata@70020000 {
166 status = "okay"; 155 status = "okay";
156 target-5v-supply = <&reg_5v0>;
157 target-12v-supply = <&reg_12v0>;
167 }; 158 };
168 159
169 hda@70030000 { 160 hda@70030000 {
@@ -177,18 +168,18 @@
177 /* Apalis MMC1 */ 168 /* Apalis MMC1 */
178 sdhci@700b0000 { 169 sdhci@700b0000 {
179 status = "okay"; 170 status = "okay";
171 bus-width = <4>;
180 /* MMC1_CD# */ 172 /* MMC1_CD# */
181 cd-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>; 173 cd-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>;
182 bus-width = <4>;
183 vqmmc-supply = <&vddio_sdmmc1>; 174 vqmmc-supply = <&vddio_sdmmc1>;
184 }; 175 };
185 176
186 /* Apalis SD1 */ 177 /* Apalis SD1 */
187 sdhci@700b0400 { 178 sdhci@700b0400 {
188 status = "okay"; 179 status = "okay";
180 bus-width = <4>;
189 /* SD1_CD# */ 181 /* SD1_CD# */
190 cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; 182 cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
191 bus-width = <4>;
192 vqmmc-supply = <&vddio_sdmmc3>; 183 vqmmc-supply = <&vddio_sdmmc3>;
193 }; 184 };
194 185
@@ -225,11 +216,12 @@
225 216
226 backlight: backlight { 217 backlight: backlight {
227 compatible = "pwm-backlight"; 218 compatible = "pwm-backlight";
228 pwms = <&pwm 3 5000000>; /* BKL1_PWM */
229 brightness-levels = <255 231 223 207 191 159 127 0>; 219 brightness-levels = <255 231 223 207 191 159 127 0>;
230 default-brightness-level = <6>; 220 default-brightness-level = <6>;
231 /* BKL1_ON */ 221 /* BKL1_ON */
232 enable-gpios = <&gpio TEGRA_GPIO(BB, 5) GPIO_ACTIVE_HIGH>; 222 enable-gpios = <&gpio TEGRA_GPIO(BB, 5) GPIO_ACTIVE_HIGH>;
223 power-supply = <&reg_3v3>;
224 pwms = <&pwm 3 5000000>; /* BKL1_PWM */
233 }; 225 };
234 226
235 gpio-keys { 227 gpio-keys {
@@ -244,6 +236,13 @@
244 }; 236 };
245 }; 237 };
246 238
239 reg_3v3: regulator-3v3 {
240 compatible = "regulator-fixed";
241 regulator-name = "3.3V_SW";
242 regulator-min-microvolt = <3300000>;
243 regulator-max-microvolt = <3300000>;
244 };
245
247 reg_5v0: regulator-5v0 { 246 reg_5v0: regulator-5v0 {
248 compatible = "regulator-fixed"; 247 compatible = "regulator-fixed";
249 regulator-name = "5V_SW"; 248 regulator-name = "5V_SW";
@@ -251,6 +250,13 @@
251 regulator-max-microvolt = <5000000>; 250 regulator-max-microvolt = <5000000>;
252 }; 251 };
253 252
253 reg_12v0: regulator-12v0 {
254 compatible = "regulator-fixed";
255 regulator-name = "12V_SW";
256 regulator-min-microvolt = <12000000>;
257 regulator-max-microvolt = <12000000>;
258 };
259
254 /* USBO1_EN */ 260 /* USBO1_EN */
255 reg_usbo1_vbus: regulator-usbo1-vbus { 261 reg_usbo1_vbus: regulator-usbo1-vbus {
256 compatible = "regulator-fixed"; 262 compatible = "regulator-fixed";
@@ -276,7 +282,7 @@
276 282
277&gpio { 283&gpio {
278 /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */ 284 /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */
279 pex_perst_n { 285 pex-perst-n {
280 gpio-hog; 286 gpio-hog;
281 gpios = <TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>; 287 gpios = <TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>;
282 output-high; 288 output-high;
diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts b/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts
index 8a8d5fa0ecd1..7961eb4bd803 100644
--- a/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts
+++ b/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts
@@ -11,7 +11,8 @@
11/ { 11/ {
12 model = "Toradex Apalis TK1 on Apalis Evaluation Board"; 12 model = "Toradex Apalis TK1 on Apalis Evaluation Board";
13 compatible = "toradex,apalis-tk1-v1.2-eval", "toradex,apalis-tk1-eval", 13 compatible = "toradex,apalis-tk1-v1.2-eval", "toradex,apalis-tk1-eval",
14 "toradex,apalis-tk1", "nvidia,tegra124"; 14 "toradex,apalis-tk1-v1.2", "toradex,apalis-tk1",
15 "nvidia,tegra124";
15 16
16 aliases { 17 aliases {
17 rtc0 = "/i2c@7000c000/rtc@68"; 18 rtc0 = "/i2c@7000c000/rtc@68";
@@ -36,6 +37,7 @@
36 host1x@50000000 { 37 host1x@50000000 {
37 hdmi@54280000 { 38 hdmi@54280000 {
38 status = "okay"; 39 status = "okay";
40 hdmi-supply = <&reg_5v0>;
39 }; 41 };
40 }; 42 };
41 43
@@ -98,7 +100,7 @@
98 * I2C4 (DDC): I2C4_SDA/SCL (DDC) on MXM3 pin 205/207 100 * I2C4 (DDC): I2C4_SDA/SCL (DDC) on MXM3 pin 205/207
99 * (e.g. display EDID) 101 * (e.g. display EDID)
100 */ 102 */
101 hdmi_ddc: i2c@7000c700 { 103 i2c@7000c700 {
102 status = "okay"; 104 status = "okay";
103 }; 105 };
104 106
@@ -106,29 +108,19 @@
106 spi@7000d400 { 108 spi@7000d400 {
107 status = "okay"; 109 status = "okay";
108 spi-max-frequency = <50000000>; 110 spi-max-frequency = <50000000>;
109
110 spidev0: spidev@0 {
111 compatible = "spidev";
112 reg = <0>;
113 spi-max-frequency = <50000000>;
114 };
115 }; 111 };
116 112
117 /* SPI4: Apalis SPI2 */ 113 /* SPI4: Apalis SPI2 */
118 spi@7000da00 { 114 spi@7000da00 {
119 status = "okay"; 115 status = "okay";
120 spi-max-frequency = <50000000>; 116 spi-max-frequency = <50000000>;
121
122 spidev1: spidev@0 {
123 compatible = "spidev";
124 reg = <0>;
125 spi-max-frequency = <50000000>;
126 };
127 }; 117 };
128 118
129 /* Apalis Serial ATA */ 119 /* Apalis Serial ATA */
130 sata@70020000 { 120 sata@70020000 {
131 status = "okay"; 121 status = "okay";
122 target-5v-supply = <&reg_5v0>;
123 target-12v-supply = <&reg_12v0>;
132 }; 124 };
133 125
134 hda@70030000 { 126 hda@70030000 {
@@ -142,18 +134,18 @@
142 /* Apalis MMC1 */ 134 /* Apalis MMC1 */
143 sdhci@700b0000 { 135 sdhci@700b0000 {
144 status = "okay"; 136 status = "okay";
137 bus-width = <4>;
145 /* MMC1_CD# */ 138 /* MMC1_CD# */
146 cd-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>; 139 cd-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>;
147 bus-width = <4>;
148 vqmmc-supply = <&vddio_sdmmc1>; 140 vqmmc-supply = <&vddio_sdmmc1>;
149 }; 141 };
150 142
151 /* Apalis SD1 */ 143 /* Apalis SD1 */
152 sdhci@700b0400 { 144 sdhci@700b0400 {
153 status = "okay"; 145 status = "okay";
146 bus-width = <4>;
154 /* SD1_CD# */ 147 /* SD1_CD# */
155 cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; 148 cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
156 bus-width = <4>;
157 vqmmc-supply = <&vddio_sdmmc3>; 149 vqmmc-supply = <&vddio_sdmmc3>;
158 }; 150 };
159 151
@@ -190,11 +182,12 @@
190 182
191 backlight: backlight { 183 backlight: backlight {
192 compatible = "pwm-backlight"; 184 compatible = "pwm-backlight";
193 pwms = <&pwm 3 5000000>; /* BKL1_PWM */
194 brightness-levels = <255 231 223 207 191 159 127 0>; 185 brightness-levels = <255 231 223 207 191 159 127 0>;
195 default-brightness-level = <6>; 186 default-brightness-level = <6>;
196 /* BKL1_ON */ 187 /* BKL1_ON */
197 enable-gpios = <&gpio TEGRA_GPIO(BB, 5) GPIO_ACTIVE_HIGH>; 188 enable-gpios = <&gpio TEGRA_GPIO(BB, 5) GPIO_ACTIVE_HIGH>;
189 power-supply = <&reg_3v3>;
190 pwms = <&pwm 3 5000000>; /* BKL1_PWM */
198 }; 191 };
199 192
200 gpio-keys { 193 gpio-keys {
@@ -209,6 +202,13 @@
209 }; 202 };
210 }; 203 };
211 204
205 reg_3v3: regulator-3v3 {
206 compatible = "regulator-fixed";
207 regulator-name = "3.3V_SW";
208 regulator-min-microvolt = <3300000>;
209 regulator-max-microvolt = <3300000>;
210 };
211
212 reg_5v0: regulator-5v0 { 212 reg_5v0: regulator-5v0 {
213 compatible = "regulator-fixed"; 213 compatible = "regulator-fixed";
214 regulator-name = "5V_SW"; 214 regulator-name = "5V_SW";
@@ -216,6 +216,13 @@
216 regulator-max-microvolt = <5000000>; 216 regulator-max-microvolt = <5000000>;
217 }; 217 };
218 218
219 reg_12v0: regulator-12v0 {
220 compatible = "regulator-fixed";
221 regulator-name = "12V_SW";
222 regulator-min-microvolt = <12000000>;
223 regulator-max-microvolt = <12000000>;
224 };
225
219 /* USBO1_EN */ 226 /* USBO1_EN */
220 reg_usbo1_vbus: regulator-usbo1-vbus { 227 reg_usbo1_vbus: regulator-usbo1-vbus {
221 compatible = "regulator-fixed"; 228 compatible = "regulator-fixed";
@@ -241,7 +248,7 @@
241 248
242&gpio { 249&gpio {
243 /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */ 250 /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */
244 pex_perst_n { 251 pex-perst-n {
245 gpio-hog; 252 gpio-hog;
246 gpios = <TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>; 253 gpios = <TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>;
247 output-high; 254 output-high;
diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi
index 573aaa50fff1..367eb8c86098 100644
--- a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi
+++ b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi
@@ -11,23 +11,19 @@
11 * Compatible for Revisions 2GB: V1.2A 11 * Compatible for Revisions 2GB: V1.2A
12 */ 12 */
13/ { 13/ {
14 model = "Toradex Apalis TK1";
15 compatible = "toradex,apalis-tk1-v1.2", "toradex,apalis-tk1",
16 "nvidia,tegra124";
17
18 memory@80000000 { 14 memory@80000000 {
19 reg = <0x0 0x80000000 0x0 0x80000000>; 15 reg = <0x0 0x80000000 0x0 0x80000000>;
20 }; 16 };
21 17
22 pcie@1003000 { 18 pcie@1003000 {
23 status = "okay"; 19 status = "okay";
24 avddio-pex-supply = <&vdd_1v05>; 20 avddio-pex-supply = <&reg_1v05_vdd>;
25 avdd-pex-pll-supply = <&vdd_1v05>; 21 avdd-pex-pll-supply = <&reg_1v05_vdd>;
26 avdd-pll-erefe-supply = <&avdd_1v05>; 22 avdd-pll-erefe-supply = <&reg_1v05_avdd>;
27 dvddio-pex-supply = <&vdd_1v05>; 23 dvddio-pex-supply = <&reg_1v05_vdd>;
28 hvdd-pex-pll-e-supply = <&reg_3v3>; 24 hvdd-pex-pll-e-supply = <&reg_module_3v3>;
29 hvdd-pex-supply = <&reg_3v3>; 25 hvdd-pex-supply = <&reg_module_3v3>;
30 vddio-pex-ctl-supply = <&reg_3v3>; 26 vddio-pex-ctl-supply = <&reg_module_3v3>;
31 27
32 /* Apalis PCIe (additional lane Apalis type specific) */ 28 /* Apalis PCIe (additional lane Apalis type specific) */
33 pci@1,0 { 29 pci@1,0 {
@@ -42,16 +38,21 @@
42 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>; 38 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>;
43 phy-names = "pcie-0"; 39 phy-names = "pcie-0";
44 status = "okay"; 40 status = "okay";
41
42 pcie@0 {
43 reg = <0 0 0 0 0>;
44 local-mac-address = [00 00 00 00 00 00];
45 };
45 }; 46 };
46 }; 47 };
47 48
48 host1x@50000000 { 49 host1x@50000000 {
49 hdmi@54280000 { 50 hdmi@54280000 {
50 pll-supply = <&reg_1v05_avdd_hdmi_pll>;
51 vdd-supply = <&reg_3v3_avdd_hdmi>;
52 nvidia,ddc-i2c-bus = <&hdmi_ddc>; 51 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
53 nvidia,hpd-gpio = 52 nvidia,hpd-gpio =
54 <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; 53 <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
54 pll-supply = <&reg_1v05_avdd_hdmi_pll>;
55 vdd-supply = <&reg_3v3_avdd_hdmi>;
55 }; 56 };
56 }; 57 };
57 58
@@ -60,44 +61,44 @@
60 * Node left disabled on purpose - the bootloader will enable 61 * Node left disabled on purpose - the bootloader will enable
61 * it after having set the VPR up 62 * it after having set the VPR up
62 */ 63 */
63 vdd-supply = <&vdd_gpu>; 64 vdd-supply = <&reg_vdd_gpu>;
64 }; 65 };
65 66
66 pinmux: pinmux@70000868 { 67 pinmux@70000868 {
67 pinctrl-names = "default"; 68 pinctrl-names = "default";
68 pinctrl-0 = <&state_default>; 69 pinctrl-0 = <&state_default>;
69 70
70 state_default: pinmux { 71 state_default: pinmux {
71 /* Analogue Audio (On-module) */ 72 /* Analogue Audio (On-module) */
72 dap3_fs_pp0 { 73 dap3-fs-pp0 {
73 nvidia,pins = "dap3_fs_pp0"; 74 nvidia,pins = "dap3_fs_pp0";
74 nvidia,function = "i2s2"; 75 nvidia,function = "i2s2";
75 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 76 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
76 nvidia,tristate = <TEGRA_PIN_DISABLE>; 77 nvidia,tristate = <TEGRA_PIN_DISABLE>;
77 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 78 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
78 }; 79 };
79 dap3_din_pp1 { 80 dap3-din-pp1 {
80 nvidia,pins = "dap3_din_pp1"; 81 nvidia,pins = "dap3_din_pp1";
81 nvidia,function = "i2s2"; 82 nvidia,function = "i2s2";
82 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 83 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
83 nvidia,tristate = <TEGRA_PIN_ENABLE>; 84 nvidia,tristate = <TEGRA_PIN_ENABLE>;
84 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 85 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
85 }; 86 };
86 dap3_dout_pp2 { 87 dap3-dout-pp2 {
87 nvidia,pins = "dap3_dout_pp2"; 88 nvidia,pins = "dap3_dout_pp2";
88 nvidia,function = "i2s2"; 89 nvidia,function = "i2s2";
89 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 90 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
90 nvidia,tristate = <TEGRA_PIN_DISABLE>; 91 nvidia,tristate = <TEGRA_PIN_DISABLE>;
91 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 92 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
92 }; 93 };
93 dap3_sclk_pp3 { 94 dap3-sclk-pp3 {
94 nvidia,pins = "dap3_sclk_pp3"; 95 nvidia,pins = "dap3_sclk_pp3";
95 nvidia,function = "i2s2"; 96 nvidia,function = "i2s2";
96 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 97 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
97 nvidia,tristate = <TEGRA_PIN_DISABLE>; 98 nvidia,tristate = <TEGRA_PIN_DISABLE>;
98 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 99 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
99 }; 100 };
100 dap_mclk1_pw4 { 101 dap-mclk1-pw4 {
101 nvidia,pins = "dap_mclk1_pw4"; 102 nvidia,pins = "dap_mclk1_pw4";
102 nvidia,function = "extperiph1"; 103 nvidia,function = "extperiph1";
103 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 104 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -124,7 +125,7 @@
124 }; 125 };
125 126
126 /* Apalis CAM1_MCLK */ 127 /* Apalis CAM1_MCLK */
127 cam_mclk_pcc0 { 128 cam-mclk-pcc0 {
128 nvidia,pins = "cam_mclk_pcc0"; 129 nvidia,pins = "cam_mclk_pcc0";
129 nvidia,function = "vi_alt3"; 130 nvidia,function = "vi_alt3";
130 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 131 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -133,28 +134,28 @@
133 }; 134 };
134 135
135 /* Apalis Digital Audio */ 136 /* Apalis Digital Audio */
136 dap2_fs_pa2 { 137 dap2-fs-pa2 {
137 nvidia,pins = "dap2_fs_pa2"; 138 nvidia,pins = "dap2_fs_pa2";
138 nvidia,function = "hda"; 139 nvidia,function = "hda";
139 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 140 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
140 nvidia,tristate = <TEGRA_PIN_DISABLE>; 141 nvidia,tristate = <TEGRA_PIN_DISABLE>;
141 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 142 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
142 }; 143 };
143 dap2_sclk_pa3 { 144 dap2-sclk-pa3 {
144 nvidia,pins = "dap2_sclk_pa3"; 145 nvidia,pins = "dap2_sclk_pa3";
145 nvidia,function = "hda"; 146 nvidia,function = "hda";
146 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 147 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
147 nvidia,tristate = <TEGRA_PIN_DISABLE>; 148 nvidia,tristate = <TEGRA_PIN_DISABLE>;
148 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 149 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
149 }; 150 };
150 dap2_din_pa4 { 151 dap2-din-pa4 {
151 nvidia,pins = "dap2_din_pa4"; 152 nvidia,pins = "dap2_din_pa4";
152 nvidia,function = "hda"; 153 nvidia,function = "hda";
153 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 154 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
154 nvidia,tristate = <TEGRA_PIN_ENABLE>; 155 nvidia,tristate = <TEGRA_PIN_ENABLE>;
155 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 156 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
156 }; 157 };
157 dap2_dout_pa5 { 158 dap2-dout-pa5 {
158 nvidia,pins = "dap2_dout_pa5"; 159 nvidia,pins = "dap2_dout_pa5";
159 nvidia,function = "hda"; 160 nvidia,function = "hda";
160 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 161 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -167,7 +168,7 @@
167 nvidia,tristate = <TEGRA_PIN_DISABLE>; 168 nvidia,tristate = <TEGRA_PIN_DISABLE>;
168 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 169 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
169 }; 170 };
170 clk3_out_pee0 { 171 clk3-out-pee0 {
171 nvidia,pins = "clk3_out_pee0"; 172 nvidia,pins = "clk3_out_pee0";
172 nvidia,function = "extperiph3"; 173 nvidia,function = "extperiph3";
173 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 174 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -176,7 +177,7 @@
176 }; 177 };
177 178
178 /* Apalis GPIO */ 179 /* Apalis GPIO */
179 usb_vbus_en0_pn4 { 180 usb-vbus-en0-pn4 {
180 nvidia,pins = "usb_vbus_en0_pn4"; 181 nvidia,pins = "usb_vbus_en0_pn4";
181 nvidia,function = "rsvd2"; 182 nvidia,function = "rsvd2";
182 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 183 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -184,7 +185,7 @@
184 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 185 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
185 nvidia,open-drain = <TEGRA_PIN_DISABLE>; 186 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
186 }; 187 };
187 usb_vbus_en1_pn5 { 188 usb-vbus-en1-pn5 {
188 nvidia,pins = "usb_vbus_en1_pn5"; 189 nvidia,pins = "usb_vbus_en1_pn5";
189 nvidia,function = "rsvd2"; 190 nvidia,function = "rsvd2";
190 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 191 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -192,35 +193,35 @@
192 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 193 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
193 nvidia,open-drain = <TEGRA_PIN_DISABLE>; 194 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
194 }; 195 };
195 pex_l0_rst_n_pdd1 { 196 pex-l0-rst-n-pdd1 {
196 nvidia,pins = "pex_l0_rst_n_pdd1"; 197 nvidia,pins = "pex_l0_rst_n_pdd1";
197 nvidia,function = "rsvd2"; 198 nvidia,function = "rsvd2";
198 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 199 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
199 nvidia,tristate = <TEGRA_PIN_DISABLE>; 200 nvidia,tristate = <TEGRA_PIN_DISABLE>;
200 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 201 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
201 }; 202 };
202 pex_l0_clkreq_n_pdd2 { 203 pex-l0-clkreq-n-pdd2 {
203 nvidia,pins = "pex_l0_clkreq_n_pdd2"; 204 nvidia,pins = "pex_l0_clkreq_n_pdd2";
204 nvidia,function = "rsvd2"; 205 nvidia,function = "rsvd2";
205 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 206 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
206 nvidia,tristate = <TEGRA_PIN_DISABLE>; 207 nvidia,tristate = <TEGRA_PIN_DISABLE>;
207 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 208 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
208 }; 209 };
209 pex_l1_rst_n_pdd5 { 210 pex-l1-rst-n-pdd5 {
210 nvidia,pins = "pex_l1_rst_n_pdd5"; 211 nvidia,pins = "pex_l1_rst_n_pdd5";
211 nvidia,function = "rsvd2"; 212 nvidia,function = "rsvd2";
212 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 213 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
213 nvidia,tristate = <TEGRA_PIN_DISABLE>; 214 nvidia,tristate = <TEGRA_PIN_DISABLE>;
214 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 215 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
215 }; 216 };
216 pex_l1_clkreq_n_pdd6 { 217 pex-l1-clkreq-n-pdd6 {
217 nvidia,pins = "pex_l1_clkreq_n_pdd6"; 218 nvidia,pins = "pex_l1_clkreq_n_pdd6";
218 nvidia,function = "rsvd2"; 219 nvidia,function = "rsvd2";
219 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 220 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
220 nvidia,tristate = <TEGRA_PIN_DISABLE>; 221 nvidia,tristate = <TEGRA_PIN_DISABLE>;
221 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 222 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
222 }; 223 };
223 dp_hpd_pff0 { 224 dp-hpd-pff0 {
224 nvidia,pins = "dp_hpd_pff0"; 225 nvidia,pins = "dp_hpd_pff0";
225 nvidia,function = "dp"; 226 nvidia,function = "dp";
226 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 227 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -244,7 +245,7 @@
244 }; 245 };
245 246
246 /* Apalis HDMI1_CEC */ 247 /* Apalis HDMI1_CEC */
247 hdmi_cec_pee3 { 248 hdmi-cec-pee3 {
248 nvidia,pins = "hdmi_cec_pee3"; 249 nvidia,pins = "hdmi_cec_pee3";
249 nvidia,function = "cec"; 250 nvidia,function = "cec";
250 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 251 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -254,7 +255,7 @@
254 }; 255 };
255 256
256 /* Apalis HDMI1_HPD */ 257 /* Apalis HDMI1_HPD */
257 hdmi_int_pn7 { 258 hdmi-int-pn7 {
258 nvidia,pins = "hdmi_int_pn7"; 259 nvidia,pins = "hdmi_int_pn7";
259 nvidia,function = "rsvd1"; 260 nvidia,function = "rsvd1";
260 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 261 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
@@ -264,7 +265,7 @@
264 }; 265 };
265 266
266 /* Apalis I2C1 */ 267 /* Apalis I2C1 */
267 gen1_i2c_scl_pc4 { 268 gen1-i2c-scl-pc4 {
268 nvidia,pins = "gen1_i2c_scl_pc4"; 269 nvidia,pins = "gen1_i2c_scl_pc4";
269 nvidia,function = "i2c1"; 270 nvidia,function = "i2c1";
270 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 271 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -272,7 +273,7 @@
272 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 273 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
273 nvidia,open-drain = <TEGRA_PIN_ENABLE>; 274 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
274 }; 275 };
275 gen1_i2c_sda_pc5 { 276 gen1-i2c-sda-pc5 {
276 nvidia,pins = "gen1_i2c_sda_pc5"; 277 nvidia,pins = "gen1_i2c_sda_pc5";
277 nvidia,function = "i2c1"; 278 nvidia,function = "i2c1";
278 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 279 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -282,7 +283,7 @@
282 }; 283 };
283 284
284 /* Apalis I2C3 (CAM) */ 285 /* Apalis I2C3 (CAM) */
285 cam_i2c_scl_pbb1 { 286 cam-i2c-scl-pbb1 {
286 nvidia,pins = "cam_i2c_scl_pbb1"; 287 nvidia,pins = "cam_i2c_scl_pbb1";
287 nvidia,function = "i2c3"; 288 nvidia,function = "i2c3";
288 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 289 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -290,7 +291,7 @@
290 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 291 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
291 nvidia,open-drain = <TEGRA_PIN_ENABLE>; 292 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
292 }; 293 };
293 cam_i2c_sda_pbb2 { 294 cam-i2c-sda-pbb2 {
294 nvidia,pins = "cam_i2c_sda_pbb2"; 295 nvidia,pins = "cam_i2c_sda_pbb2";
295 nvidia,function = "i2c3"; 296 nvidia,function = "i2c3";
296 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 297 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -300,7 +301,7 @@
300 }; 301 };
301 302
302 /* Apalis I2C4 (DDC) */ 303 /* Apalis I2C4 (DDC) */
303 ddc_scl_pv4 { 304 ddc-scl-pv4 {
304 nvidia,pins = "ddc_scl_pv4"; 305 nvidia,pins = "ddc_scl_pv4";
305 nvidia,function = "i2c4"; 306 nvidia,function = "i2c4";
306 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 307 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -308,7 +309,7 @@
308 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 309 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
309 nvidia,rcv-sel = <TEGRA_PIN_ENABLE>; 310 nvidia,rcv-sel = <TEGRA_PIN_ENABLE>;
310 }; 311 };
311 ddc_sda_pv5 { 312 ddc-sda-pv5 {
312 nvidia,pins = "ddc_sda_pv5"; 313 nvidia,pins = "ddc_sda_pv5";
313 nvidia,function = "i2c4"; 314 nvidia,function = "i2c4";
314 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 315 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -318,77 +319,77 @@
318 }; 319 };
319 320
320 /* Apalis MMC1 */ 321 /* Apalis MMC1 */
321 sdmmc1_cd_n_pv3 { /* CD# GPIO */ 322 sdmmc1-cd-n-pv3 { /* CD# GPIO */
322 nvidia,pins = "sdmmc1_wp_n_pv3"; 323 nvidia,pins = "sdmmc1_wp_n_pv3";
323 nvidia,function = "sdmmc1"; 324 nvidia,function = "sdmmc1";
324 nvidia,pull = <TEGRA_PIN_PULL_UP>; 325 nvidia,pull = <TEGRA_PIN_PULL_UP>;
325 nvidia,tristate = <TEGRA_PIN_ENABLE>; 326 nvidia,tristate = <TEGRA_PIN_ENABLE>;
326 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 327 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
327 }; 328 };
328 clk2_out_pw5 { /* D5 GPIO */ 329 clk2-out-pw5 { /* D5 GPIO */
329 nvidia,pins = "clk2_out_pw5"; 330 nvidia,pins = "clk2_out_pw5";
330 nvidia,function = "rsvd2"; 331 nvidia,function = "rsvd2";
331 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 332 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
332 nvidia,tristate = <TEGRA_PIN_DISABLE>; 333 nvidia,tristate = <TEGRA_PIN_DISABLE>;
333 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 334 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
334 }; 335 };
335 sdmmc1_dat3_py4 { 336 sdmmc1-dat3-py4 {
336 nvidia,pins = "sdmmc1_dat3_py4"; 337 nvidia,pins = "sdmmc1_dat3_py4";
337 nvidia,function = "sdmmc1"; 338 nvidia,function = "sdmmc1";
338 nvidia,pull = <TEGRA_PIN_PULL_UP>; 339 nvidia,pull = <TEGRA_PIN_PULL_UP>;
339 nvidia,tristate = <TEGRA_PIN_DISABLE>; 340 nvidia,tristate = <TEGRA_PIN_DISABLE>;
340 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 341 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
341 }; 342 };
342 sdmmc1_dat2_py5 { 343 sdmmc1-dat2-py5 {
343 nvidia,pins = "sdmmc1_dat2_py5"; 344 nvidia,pins = "sdmmc1_dat2_py5";
344 nvidia,function = "sdmmc1"; 345 nvidia,function = "sdmmc1";
345 nvidia,pull = <TEGRA_PIN_PULL_UP>; 346 nvidia,pull = <TEGRA_PIN_PULL_UP>;
346 nvidia,tristate = <TEGRA_PIN_DISABLE>; 347 nvidia,tristate = <TEGRA_PIN_DISABLE>;
347 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 348 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
348 }; 349 };
349 sdmmc1_dat1_py6 { 350 sdmmc1-dat1-py6 {
350 nvidia,pins = "sdmmc1_dat1_py6"; 351 nvidia,pins = "sdmmc1_dat1_py6";
351 nvidia,function = "sdmmc1"; 352 nvidia,function = "sdmmc1";
352 nvidia,pull = <TEGRA_PIN_PULL_UP>; 353 nvidia,pull = <TEGRA_PIN_PULL_UP>;
353 nvidia,tristate = <TEGRA_PIN_DISABLE>; 354 nvidia,tristate = <TEGRA_PIN_DISABLE>;
354 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 355 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
355 }; 356 };
356 sdmmc1_dat0_py7 { 357 sdmmc1-dat0-py7 {
357 nvidia,pins = "sdmmc1_dat0_py7"; 358 nvidia,pins = "sdmmc1_dat0_py7";
358 nvidia,function = "sdmmc1"; 359 nvidia,function = "sdmmc1";
359 nvidia,pull = <TEGRA_PIN_PULL_UP>; 360 nvidia,pull = <TEGRA_PIN_PULL_UP>;
360 nvidia,tristate = <TEGRA_PIN_DISABLE>; 361 nvidia,tristate = <TEGRA_PIN_DISABLE>;
361 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 362 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
362 }; 363 };
363 sdmmc1_clk_pz0 { 364 sdmmc1-clk-pz0 {
364 nvidia,pins = "sdmmc1_clk_pz0"; 365 nvidia,pins = "sdmmc1_clk_pz0";
365 nvidia,function = "sdmmc1"; 366 nvidia,function = "sdmmc1";
366 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 367 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
367 nvidia,tristate = <TEGRA_PIN_DISABLE>; 368 nvidia,tristate = <TEGRA_PIN_DISABLE>;
368 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 369 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
369 }; 370 };
370 sdmmc1_cmd_pz1 { 371 sdmmc1-cmd-pz1 {
371 nvidia,pins = "sdmmc1_cmd_pz1"; 372 nvidia,pins = "sdmmc1_cmd_pz1";
372 nvidia,function = "sdmmc1"; 373 nvidia,function = "sdmmc1";
373 nvidia,pull = <TEGRA_PIN_PULL_UP>; 374 nvidia,pull = <TEGRA_PIN_PULL_UP>;
374 nvidia,tristate = <TEGRA_PIN_DISABLE>; 375 nvidia,tristate = <TEGRA_PIN_DISABLE>;
375 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 376 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
376 }; 377 };
377 clk2_req_pcc5 { /* D4 GPIO */ 378 clk2-req-pcc5 { /* D4 GPIO */
378 nvidia,pins = "clk2_req_pcc5"; 379 nvidia,pins = "clk2_req_pcc5";
379 nvidia,function = "rsvd2"; 380 nvidia,function = "rsvd2";
380 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 381 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
381 nvidia,tristate = <TEGRA_PIN_DISABLE>; 382 nvidia,tristate = <TEGRA_PIN_DISABLE>;
382 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 383 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
383 }; 384 };
384 sdmmc3_clk_lb_in_pee5 { /* D6 GPIO */ 385 sdmmc3-clk-lb-in-pee5 { /* D6 GPIO */
385 nvidia,pins = "sdmmc3_clk_lb_in_pee5"; 386 nvidia,pins = "sdmmc3_clk_lb_in_pee5";
386 nvidia,function = "rsvd2"; 387 nvidia,function = "rsvd2";
387 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 388 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
388 nvidia,tristate = <TEGRA_PIN_DISABLE>; 389 nvidia,tristate = <TEGRA_PIN_DISABLE>;
389 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 390 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
390 }; 391 };
391 usb_vbus_en2_pff1 { /* D7 GPIO */ 392 usb-vbus-en2-pff1 { /* D7 GPIO */
392 nvidia,pins = "usb_vbus_en2_pff1"; 393 nvidia,pins = "usb_vbus_en2_pff1";
393 nvidia,function = "rsvd2"; 394 nvidia,function = "rsvd2";
394 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 395 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -428,7 +429,7 @@
428 }; 429 };
429 430
430 /* Apalis SATA1_ACT# */ 431 /* Apalis SATA1_ACT# */
431 dap1_dout_pn2 { 432 dap1-dout-pn2 {
432 nvidia,pins = "dap1_dout_pn2"; 433 nvidia,pins = "dap1_dout_pn2";
433 nvidia,function = "gmi"; 434 nvidia,function = "gmi";
434 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 435 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -437,49 +438,49 @@
437 }; 438 };
438 439
439 /* Apalis SD1 */ 440 /* Apalis SD1 */
440 sdmmc3_clk_pa6 { 441 sdmmc3-clk-pa6 {
441 nvidia,pins = "sdmmc3_clk_pa6"; 442 nvidia,pins = "sdmmc3_clk_pa6";
442 nvidia,function = "sdmmc3"; 443 nvidia,function = "sdmmc3";
443 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 444 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
444 nvidia,tristate = <TEGRA_PIN_DISABLE>; 445 nvidia,tristate = <TEGRA_PIN_DISABLE>;
445 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 446 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
446 }; 447 };
447 sdmmc3_cmd_pa7 { 448 sdmmc3-cmd-pa7 {
448 nvidia,pins = "sdmmc3_cmd_pa7"; 449 nvidia,pins = "sdmmc3_cmd_pa7";
449 nvidia,function = "sdmmc3"; 450 nvidia,function = "sdmmc3";
450 nvidia,pull = <TEGRA_PIN_PULL_UP>; 451 nvidia,pull = <TEGRA_PIN_PULL_UP>;
451 nvidia,tristate = <TEGRA_PIN_DISABLE>; 452 nvidia,tristate = <TEGRA_PIN_DISABLE>;
452 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 453 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
453 }; 454 };
454 sdmmc3_dat3_pb4 { 455 sdmmc3-dat3-pb4 {
455 nvidia,pins = "sdmmc3_dat3_pb4"; 456 nvidia,pins = "sdmmc3_dat3_pb4";
456 nvidia,function = "sdmmc3"; 457 nvidia,function = "sdmmc3";
457 nvidia,pull = <TEGRA_PIN_PULL_UP>; 458 nvidia,pull = <TEGRA_PIN_PULL_UP>;
458 nvidia,tristate = <TEGRA_PIN_DISABLE>; 459 nvidia,tristate = <TEGRA_PIN_DISABLE>;
459 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 460 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
460 }; 461 };
461 sdmmc3_dat2_pb5 { 462 sdmmc3-dat2-pb5 {
462 nvidia,pins = "sdmmc3_dat2_pb5"; 463 nvidia,pins = "sdmmc3_dat2_pb5";
463 nvidia,function = "sdmmc3"; 464 nvidia,function = "sdmmc3";
464 nvidia,pull = <TEGRA_PIN_PULL_UP>; 465 nvidia,pull = <TEGRA_PIN_PULL_UP>;
465 nvidia,tristate = <TEGRA_PIN_DISABLE>; 466 nvidia,tristate = <TEGRA_PIN_DISABLE>;
466 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 467 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
467 }; 468 };
468 sdmmc3_dat1_pb6 { 469 sdmmc3-dat1-pb6 {
469 nvidia,pins = "sdmmc3_dat1_pb6"; 470 nvidia,pins = "sdmmc3_dat1_pb6";
470 nvidia,function = "sdmmc3"; 471 nvidia,function = "sdmmc3";
471 nvidia,pull = <TEGRA_PIN_PULL_UP>; 472 nvidia,pull = <TEGRA_PIN_PULL_UP>;
472 nvidia,tristate = <TEGRA_PIN_DISABLE>; 473 nvidia,tristate = <TEGRA_PIN_DISABLE>;
473 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 474 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
474 }; 475 };
475 sdmmc3_dat0_pb7 { 476 sdmmc3-dat0-pb7 {
476 nvidia,pins = "sdmmc3_dat0_pb7"; 477 nvidia,pins = "sdmmc3_dat0_pb7";
477 nvidia,function = "sdmmc3"; 478 nvidia,function = "sdmmc3";
478 nvidia,pull = <TEGRA_PIN_PULL_UP>; 479 nvidia,pull = <TEGRA_PIN_PULL_UP>;
479 nvidia,tristate = <TEGRA_PIN_DISABLE>; 480 nvidia,tristate = <TEGRA_PIN_DISABLE>;
480 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 481 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
481 }; 482 };
482 sdmmc3_cd_n_pv2 { /* CD# GPIO */ 483 sdmmc3-cd-n-pv2 { /* CD# GPIO */
483 nvidia,pins = "sdmmc3_cd_n_pv2"; 484 nvidia,pins = "sdmmc3_cd_n_pv2";
484 nvidia,function = "rsvd3"; 485 nvidia,function = "rsvd3";
485 nvidia,pull = <TEGRA_PIN_PULL_UP>; 486 nvidia,pull = <TEGRA_PIN_PULL_UP>;
@@ -488,14 +489,14 @@
488 }; 489 };
489 490
490 /* Apalis SPDIF */ 491 /* Apalis SPDIF */
491 spdif_out_pk5 { 492 spdif-out-pk5 {
492 nvidia,pins = "spdif_out_pk5"; 493 nvidia,pins = "spdif_out_pk5";
493 nvidia,function = "spdif"; 494 nvidia,function = "spdif";
494 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 495 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
495 nvidia,tristate = <TEGRA_PIN_DISABLE>; 496 nvidia,tristate = <TEGRA_PIN_DISABLE>;
496 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 497 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
497 }; 498 };
498 spdif_in_pk6 { 499 spdif-in-pk6 {
499 nvidia,pins = "spdif_in_pk6"; 500 nvidia,pins = "spdif_in_pk6";
500 nvidia,function = "spdif"; 501 nvidia,function = "spdif";
501 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 502 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -504,28 +505,28 @@
504 }; 505 };
505 506
506 /* Apalis SPI1 */ 507 /* Apalis SPI1 */
507 ulpi_clk_py0 { 508 ulpi-clk-py0 {
508 nvidia,pins = "ulpi_clk_py0"; 509 nvidia,pins = "ulpi_clk_py0";
509 nvidia,function = "spi1"; 510 nvidia,function = "spi1";
510 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 511 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
511 nvidia,tristate = <TEGRA_PIN_DISABLE>; 512 nvidia,tristate = <TEGRA_PIN_DISABLE>;
512 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 513 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
513 }; 514 };
514 ulpi_dir_py1 { 515 ulpi-dir-py1 {
515 nvidia,pins = "ulpi_dir_py1"; 516 nvidia,pins = "ulpi_dir_py1";
516 nvidia,function = "spi1"; 517 nvidia,function = "spi1";
517 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 518 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
518 nvidia,tristate = <TEGRA_PIN_ENABLE>; 519 nvidia,tristate = <TEGRA_PIN_ENABLE>;
519 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 520 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
520 }; 521 };
521 ulpi_nxt_py2 { 522 ulpi-nxt-py2 {
522 nvidia,pins = "ulpi_nxt_py2"; 523 nvidia,pins = "ulpi_nxt_py2";
523 nvidia,function = "spi1"; 524 nvidia,function = "spi1";
524 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 525 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
525 nvidia,tristate = <TEGRA_PIN_DISABLE>; 526 nvidia,tristate = <TEGRA_PIN_DISABLE>;
526 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 527 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
527 }; 528 };
528 ulpi_stp_py3 { 529 ulpi-stp-py3 {
529 nvidia,pins = "ulpi_stp_py3"; 530 nvidia,pins = "ulpi_stp_py3";
530 nvidia,function = "spi1"; 531 nvidia,function = "spi1";
531 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 532 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -578,42 +579,42 @@
578 nvidia,tristate = <TEGRA_PIN_ENABLE>; 579 nvidia,tristate = <TEGRA_PIN_ENABLE>;
579 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 580 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
580 }; 581 };
581 uart1_txd_pu0 { 582 uart1-txd-pu0 {
582 nvidia,pins = "pu0"; 583 nvidia,pins = "pu0";
583 nvidia,function = "uarta"; 584 nvidia,function = "uarta";
584 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 585 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
585 nvidia,tristate = <TEGRA_PIN_DISABLE>; 586 nvidia,tristate = <TEGRA_PIN_DISABLE>;
586 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 587 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
587 }; 588 };
588 uart1_rxd_pu1 { 589 uart1-rxd-pu1 {
589 nvidia,pins = "pu1"; 590 nvidia,pins = "pu1";
590 nvidia,function = "uarta"; 591 nvidia,function = "uarta";
591 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 592 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
592 nvidia,tristate = <TEGRA_PIN_ENABLE>; 593 nvidia,tristate = <TEGRA_PIN_ENABLE>;
593 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 594 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
594 }; 595 };
595 uart1_cts_n_pu2 { 596 uart1-cts-n-pu2 {
596 nvidia,pins = "pu2"; 597 nvidia,pins = "pu2";
597 nvidia,function = "uarta"; 598 nvidia,function = "uarta";
598 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 599 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
599 nvidia,tristate = <TEGRA_PIN_ENABLE>; 600 nvidia,tristate = <TEGRA_PIN_ENABLE>;
600 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 601 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
601 }; 602 };
602 uart1_rts_n_pu3 { 603 uart1-rts-n-pu3 {
603 nvidia,pins = "pu3"; 604 nvidia,pins = "pu3";
604 nvidia,function = "uarta"; 605 nvidia,function = "uarta";
605 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 606 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
606 nvidia,tristate = <TEGRA_PIN_DISABLE>; 607 nvidia,tristate = <TEGRA_PIN_DISABLE>;
607 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 608 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
608 }; 609 };
609 uart3_cts_n_pa1 { /* DSR GPIO */ 610 uart3-cts-n-pa1 { /* DSR GPIO */
610 nvidia,pins = "uart3_cts_n_pa1"; 611 nvidia,pins = "uart3_cts_n_pa1";
611 nvidia,function = "gmi"; 612 nvidia,function = "gmi";
612 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 613 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
613 nvidia,tristate = <TEGRA_PIN_ENABLE>; 614 nvidia,tristate = <TEGRA_PIN_ENABLE>;
614 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 615 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
615 }; 616 };
616 uart3_rts_n_pc0 { /* DTR GPIO */ 617 uart3-rts-n-pc0 { /* DTR GPIO */
617 nvidia,pins = "uart3_rts_n_pc0"; 618 nvidia,pins = "uart3_rts_n_pc0";
618 nvidia,function = "gmi"; 619 nvidia,function = "gmi";
619 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 620 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -622,28 +623,28 @@
622 }; 623 };
623 624
624 /* Apalis UART2 */ 625 /* Apalis UART2 */
625 uart2_txd_pc2 { 626 uart2-txd-pc2 {
626 nvidia,pins = "uart2_txd_pc2"; 627 nvidia,pins = "uart2_txd_pc2";
627 nvidia,function = "irda"; 628 nvidia,function = "irda";
628 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 629 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
629 nvidia,tristate = <TEGRA_PIN_DISABLE>; 630 nvidia,tristate = <TEGRA_PIN_DISABLE>;
630 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 631 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
631 }; 632 };
632 uart2_rxd_pc3 { 633 uart2-rxd-pc3 {
633 nvidia,pins = "uart2_rxd_pc3"; 634 nvidia,pins = "uart2_rxd_pc3";
634 nvidia,function = "irda"; 635 nvidia,function = "irda";
635 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 636 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
636 nvidia,tristate = <TEGRA_PIN_ENABLE>; 637 nvidia,tristate = <TEGRA_PIN_ENABLE>;
637 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 638 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
638 }; 639 };
639 uart2_cts_n_pj5 { 640 uart2-cts-n-pj5 {
640 nvidia,pins = "uart2_cts_n_pj5"; 641 nvidia,pins = "uart2_cts_n_pj5";
641 nvidia,function = "uartb"; 642 nvidia,function = "uartb";
642 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 643 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
643 nvidia,tristate = <TEGRA_PIN_ENABLE>; 644 nvidia,tristate = <TEGRA_PIN_ENABLE>;
644 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 645 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
645 }; 646 };
646 uart2_rts_n_pj6 { 647 uart2-rts-n-pj6 {
647 nvidia,pins = "uart2_rts_n_pj6"; 648 nvidia,pins = "uart2_rts_n_pj6";
648 nvidia,function = "uartb"; 649 nvidia,function = "uartb";
649 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 650 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -652,14 +653,14 @@
652 }; 653 };
653 654
654 /* Apalis UART3 */ 655 /* Apalis UART3 */
655 uart3_txd_pw6 { 656 uart3-txd-pw6 {
656 nvidia,pins = "uart3_txd_pw6"; 657 nvidia,pins = "uart3_txd_pw6";
657 nvidia,function = "uartc"; 658 nvidia,function = "uartc";
658 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 659 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
659 nvidia,tristate = <TEGRA_PIN_DISABLE>; 660 nvidia,tristate = <TEGRA_PIN_DISABLE>;
660 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 661 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
661 }; 662 };
662 uart3_rxd_pw7 { 663 uart3-rxd-pw7 {
663 nvidia,pins = "uart3_rxd_pw7"; 664 nvidia,pins = "uart3_rxd_pw7";
664 nvidia,function = "uartc"; 665 nvidia,function = "uartc";
665 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 666 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -668,14 +669,14 @@
668 }; 669 };
669 670
670 /* Apalis UART4 */ 671 /* Apalis UART4 */
671 uart4_rxd_pb0 { 672 uart4-rxd-pb0 {
672 nvidia,pins = "pb0"; 673 nvidia,pins = "pb0";
673 nvidia,function = "uartd"; 674 nvidia,function = "uartd";
674 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 675 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
675 nvidia,tristate = <TEGRA_PIN_ENABLE>; 676 nvidia,tristate = <TEGRA_PIN_ENABLE>;
676 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 677 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
677 }; 678 };
678 uart4_txd_pj7 { 679 uart4-txd-pj7 {
679 nvidia,pins = "pj7"; 680 nvidia,pins = "pj7";
680 nvidia,function = "uartd"; 681 nvidia,function = "uartd";
681 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 682 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -684,7 +685,7 @@
684 }; 685 };
685 686
686 /* Apalis USBH_EN */ 687 /* Apalis USBH_EN */
687 gen2_i2c_sda_pt6 { 688 gen2-i2c-sda-pt6 {
688 nvidia,pins = "gen2_i2c_sda_pt6"; 689 nvidia,pins = "gen2_i2c_sda_pt6";
689 nvidia,function = "rsvd2"; 690 nvidia,function = "rsvd2";
690 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 691 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -703,7 +704,7 @@
703 }; 704 };
704 705
705 /* Apalis USBO1_EN */ 706 /* Apalis USBO1_EN */
706 gen2_i2c_scl_pt5 { 707 gen2-i2c-scl-pt5 {
707 nvidia,pins = "gen2_i2c_scl_pt5"; 708 nvidia,pins = "gen2_i2c_scl_pt5";
708 nvidia,function = "rsvd2"; 709 nvidia,function = "rsvd2";
709 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 710 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -722,7 +723,7 @@
722 }; 723 };
723 724
724 /* Apalis WAKE1_MICO */ 725 /* Apalis WAKE1_MICO */
725 pex_wake_n_pdd3 { 726 pex-wake-n-pdd3 {
726 nvidia,pins = "pex_wake_n_pdd3"; 727 nvidia,pins = "pex_wake_n_pdd3";
727 nvidia,function = "rsvd2"; 728 nvidia,function = "rsvd2";
728 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 729 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -731,7 +732,7 @@
731 }; 732 };
732 733
733 /* CORE_PWR_REQ */ 734 /* CORE_PWR_REQ */
734 core_pwr_req { 735 core-pwr-req {
735 nvidia,pins = "core_pwr_req"; 736 nvidia,pins = "core_pwr_req";
736 nvidia,function = "pwron"; 737 nvidia,function = "pwron";
737 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 738 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -740,7 +741,7 @@
740 }; 741 };
741 742
742 /* CPU_PWR_REQ */ 743 /* CPU_PWR_REQ */
743 cpu_pwr_req { 744 cpu-pwr-req {
744 nvidia,pins = "cpu_pwr_req"; 745 nvidia,pins = "cpu_pwr_req";
745 nvidia,function = "cpu"; 746 nvidia,function = "cpu";
746 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 747 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -749,14 +750,14 @@
749 }; 750 };
750 751
751 /* DVFS */ 752 /* DVFS */
752 dvfs_pwm_px0 { 753 dvfs-pwm-px0 {
753 nvidia,pins = "dvfs_pwm_px0"; 754 nvidia,pins = "dvfs_pwm_px0";
754 nvidia,function = "cldvfs"; 755 nvidia,function = "cldvfs";
755 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 756 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
756 nvidia,tristate = <TEGRA_PIN_DISABLE>; 757 nvidia,tristate = <TEGRA_PIN_DISABLE>;
757 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 758 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
758 }; 759 };
759 dvfs_clk_px2 { 760 dvfs-clk-px2 {
760 nvidia,pins = "dvfs_clk_px2"; 761 nvidia,pins = "dvfs_clk_px2";
761 nvidia,function = "cldvfs"; 762 nvidia,function = "cldvfs";
762 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 763 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -765,70 +766,70 @@
765 }; 766 };
766 767
767 /* eMMC */ 768 /* eMMC */
768 sdmmc4_dat0_paa0 { 769 sdmmc4-dat0-paa0 {
769 nvidia,pins = "sdmmc4_dat0_paa0"; 770 nvidia,pins = "sdmmc4_dat0_paa0";
770 nvidia,function = "sdmmc4"; 771 nvidia,function = "sdmmc4";
771 nvidia,pull = <TEGRA_PIN_PULL_UP>; 772 nvidia,pull = <TEGRA_PIN_PULL_UP>;
772 nvidia,tristate = <TEGRA_PIN_DISABLE>; 773 nvidia,tristate = <TEGRA_PIN_DISABLE>;
773 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 774 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
774 }; 775 };
775 sdmmc4_dat1_paa1 { 776 sdmmc4-dat1-paa1 {
776 nvidia,pins = "sdmmc4_dat1_paa1"; 777 nvidia,pins = "sdmmc4_dat1_paa1";
777 nvidia,function = "sdmmc4"; 778 nvidia,function = "sdmmc4";
778 nvidia,pull = <TEGRA_PIN_PULL_UP>; 779 nvidia,pull = <TEGRA_PIN_PULL_UP>;
779 nvidia,tristate = <TEGRA_PIN_DISABLE>; 780 nvidia,tristate = <TEGRA_PIN_DISABLE>;
780 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 781 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
781 }; 782 };
782 sdmmc4_dat2_paa2 { 783 sdmmc4-dat2-paa2 {
783 nvidia,pins = "sdmmc4_dat2_paa2"; 784 nvidia,pins = "sdmmc4_dat2_paa2";
784 nvidia,function = "sdmmc4"; 785 nvidia,function = "sdmmc4";
785 nvidia,pull = <TEGRA_PIN_PULL_UP>; 786 nvidia,pull = <TEGRA_PIN_PULL_UP>;
786 nvidia,tristate = <TEGRA_PIN_DISABLE>; 787 nvidia,tristate = <TEGRA_PIN_DISABLE>;
787 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 788 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
788 }; 789 };
789 sdmmc4_dat3_paa3 { 790 sdmmc4-dat3-paa3 {
790 nvidia,pins = "sdmmc4_dat3_paa3"; 791 nvidia,pins = "sdmmc4_dat3_paa3";
791 nvidia,function = "sdmmc4"; 792 nvidia,function = "sdmmc4";
792 nvidia,pull = <TEGRA_PIN_PULL_UP>; 793 nvidia,pull = <TEGRA_PIN_PULL_UP>;
793 nvidia,tristate = <TEGRA_PIN_DISABLE>; 794 nvidia,tristate = <TEGRA_PIN_DISABLE>;
794 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 795 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
795 }; 796 };
796 sdmmc4_dat4_paa4 { 797 sdmmc4-dat4-paa4 {
797 nvidia,pins = "sdmmc4_dat4_paa4"; 798 nvidia,pins = "sdmmc4_dat4_paa4";
798 nvidia,function = "sdmmc4"; 799 nvidia,function = "sdmmc4";
799 nvidia,pull = <TEGRA_PIN_PULL_UP>; 800 nvidia,pull = <TEGRA_PIN_PULL_UP>;
800 nvidia,tristate = <TEGRA_PIN_DISABLE>; 801 nvidia,tristate = <TEGRA_PIN_DISABLE>;
801 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 802 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
802 }; 803 };
803 sdmmc4_dat5_paa5 { 804 sdmmc4-dat5-paa5 {
804 nvidia,pins = "sdmmc4_dat5_paa5"; 805 nvidia,pins = "sdmmc4_dat5_paa5";
805 nvidia,function = "sdmmc4"; 806 nvidia,function = "sdmmc4";
806 nvidia,pull = <TEGRA_PIN_PULL_UP>; 807 nvidia,pull = <TEGRA_PIN_PULL_UP>;
807 nvidia,tristate = <TEGRA_PIN_DISABLE>; 808 nvidia,tristate = <TEGRA_PIN_DISABLE>;
808 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 809 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
809 }; 810 };
810 sdmmc4_dat6_paa6 { 811 sdmmc4-dat6-paa6 {
811 nvidia,pins = "sdmmc4_dat6_paa6"; 812 nvidia,pins = "sdmmc4_dat6_paa6";
812 nvidia,function = "sdmmc4"; 813 nvidia,function = "sdmmc4";
813 nvidia,pull = <TEGRA_PIN_PULL_UP>; 814 nvidia,pull = <TEGRA_PIN_PULL_UP>;
814 nvidia,tristate = <TEGRA_PIN_DISABLE>; 815 nvidia,tristate = <TEGRA_PIN_DISABLE>;
815 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 816 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
816 }; 817 };
817 sdmmc4_dat7_paa7 { 818 sdmmc4-dat7-paa7 {
818 nvidia,pins = "sdmmc4_dat7_paa7"; 819 nvidia,pins = "sdmmc4_dat7_paa7";
819 nvidia,function = "sdmmc4"; 820 nvidia,function = "sdmmc4";
820 nvidia,pull = <TEGRA_PIN_PULL_UP>; 821 nvidia,pull = <TEGRA_PIN_PULL_UP>;
821 nvidia,tristate = <TEGRA_PIN_DISABLE>; 822 nvidia,tristate = <TEGRA_PIN_DISABLE>;
822 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 823 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
823 }; 824 };
824 sdmmc4_clk_pcc4 { 825 sdmmc4-clk-pcc4 {
825 nvidia,pins = "sdmmc4_clk_pcc4"; 826 nvidia,pins = "sdmmc4_clk_pcc4";
826 nvidia,function = "sdmmc4"; 827 nvidia,function = "sdmmc4";
827 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 828 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
828 nvidia,tristate = <TEGRA_PIN_DISABLE>; 829 nvidia,tristate = <TEGRA_PIN_DISABLE>;
829 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 830 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
830 }; 831 };
831 sdmmc4_cmd_pt7 { 832 sdmmc4-cmd-pt7 {
832 nvidia,pins = "sdmmc4_cmd_pt7"; 833 nvidia,pins = "sdmmc4_cmd_pt7";
833 nvidia,function = "sdmmc4"; 834 nvidia,function = "sdmmc4";
834 nvidia,pull = <TEGRA_PIN_PULL_UP>; 835 nvidia,pull = <TEGRA_PIN_PULL_UP>;
@@ -837,7 +838,7 @@
837 }; 838 };
838 839
839 /* JTAG_RTCK */ 840 /* JTAG_RTCK */
840 jtag_rtck { 841 jtag-rtck {
841 nvidia,pins = "jtag_rtck"; 842 nvidia,pins = "jtag_rtck";
842 nvidia,function = "rtck"; 843 nvidia,function = "rtck";
843 nvidia,pull = <TEGRA_PIN_PULL_UP>; 844 nvidia,pull = <TEGRA_PIN_PULL_UP>;
@@ -846,7 +847,7 @@
846 }; 847 };
847 848
848 /* LAN_DEV_OFF# */ 849 /* LAN_DEV_OFF# */
849 ulpi_data5_po6 { 850 ulpi-data5-po6 {
850 nvidia,pins = "ulpi_data5_po6"; 851 nvidia,pins = "ulpi_data5_po6";
851 nvidia,function = "ulpi"; 852 nvidia,function = "ulpi";
852 nvidia,pull = <TEGRA_PIN_PULL_UP>; 853 nvidia,pull = <TEGRA_PIN_PULL_UP>;
@@ -855,7 +856,7 @@
855 }; 856 };
856 857
857 /* LAN_RESET# */ 858 /* LAN_RESET# */
858 kb_row10_ps2 { 859 kb-row10-ps2 {
859 nvidia,pins = "kb_row10_ps2"; 860 nvidia,pins = "kb_row10_ps2";
860 nvidia,function = "rsvd2"; 861 nvidia,function = "rsvd2";
861 nvidia,pull = <TEGRA_PIN_PULL_UP>; 862 nvidia,pull = <TEGRA_PIN_PULL_UP>;
@@ -864,7 +865,7 @@
864 }; 865 };
865 866
866 /* LAN_WAKE# */ 867 /* LAN_WAKE# */
867 ulpi_data4_po5 { 868 ulpi-data4-po5 {
868 nvidia,pins = "ulpi_data4_po5"; 869 nvidia,pins = "ulpi_data4_po5";
869 nvidia,function = "ulpi"; 870 nvidia,function = "ulpi";
870 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 871 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -918,35 +919,35 @@
918 }; 919 };
919 920
920 /* MCU SPI */ 921 /* MCU SPI */
921 gpio_x4_aud_px4 { 922 gpio-x4-aud-px4 {
922 nvidia,pins = "gpio_x4_aud_px4"; 923 nvidia,pins = "gpio_x4_aud_px4";
923 nvidia,function = "spi2"; 924 nvidia,function = "spi2";
924 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 925 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
925 nvidia,tristate = <TEGRA_PIN_DISABLE>; 926 nvidia,tristate = <TEGRA_PIN_DISABLE>;
926 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 927 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
927 }; 928 };
928 gpio_x5_aud_px5 { 929 gpio-x5-aud-px5 {
929 nvidia,pins = "gpio_x5_aud_px5"; 930 nvidia,pins = "gpio_x5_aud_px5";
930 nvidia,function = "spi2"; 931 nvidia,function = "spi2";
931 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 932 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
932 nvidia,tristate = <TEGRA_PIN_DISABLE>; 933 nvidia,tristate = <TEGRA_PIN_DISABLE>;
933 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 934 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
934 }; 935 };
935 gpio_x6_aud_px6 { /* MCU_CS */ 936 gpio-x6-aud-px6 { /* MCU_CS */
936 nvidia,pins = "gpio_x6_aud_px6"; 937 nvidia,pins = "gpio_x6_aud_px6";
937 nvidia,function = "spi2"; 938 nvidia,function = "spi2";
938 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 939 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
939 nvidia,tristate = <TEGRA_PIN_DISABLE>; 940 nvidia,tristate = <TEGRA_PIN_DISABLE>;
940 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 941 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
941 }; 942 };
942 gpio_x7_aud_px7 { 943 gpio-x7-aud-px7 {
943 nvidia,pins = "gpio_x7_aud_px7"; 944 nvidia,pins = "gpio_x7_aud_px7";
944 nvidia,function = "spi2"; 945 nvidia,function = "spi2";
945 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 946 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
946 nvidia,tristate = <TEGRA_PIN_ENABLE>; 947 nvidia,tristate = <TEGRA_PIN_ENABLE>;
947 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 948 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
948 }; 949 };
949 gpio_w2_aud_pw2 { /* MCU_CSEZP */ 950 gpio-w2-aud-pw2 { /* MCU_CSEZP */
950 nvidia,pins = "gpio_w2_aud_pw2"; 951 nvidia,pins = "gpio_w2_aud_pw2";
951 nvidia,function = "spi2"; 952 nvidia,function = "spi2";
952 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 953 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -955,7 +956,7 @@
955 }; 956 };
956 957
957 /* PMIC_CLK_32K */ 958 /* PMIC_CLK_32K */
958 clk_32k_in { 959 clk-32k-in {
959 nvidia,pins = "clk_32k_in"; 960 nvidia,pins = "clk_32k_in";
960 nvidia,function = "clk"; 961 nvidia,function = "clk";
961 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 962 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -964,7 +965,7 @@
964 }; 965 };
965 966
966 /* PMIC_CPU_OC_INT */ 967 /* PMIC_CPU_OC_INT */
967 clk_32k_out_pa0 { 968 clk-32k-out-pa0 {
968 nvidia,pins = "clk_32k_out_pa0"; 969 nvidia,pins = "clk_32k_out_pa0";
969 nvidia,function = "soc"; 970 nvidia,function = "soc";
970 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 971 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -973,7 +974,7 @@
973 }; 974 };
974 975
975 /* PWR_I2C */ 976 /* PWR_I2C */
976 pwr_i2c_scl_pz6 { 977 pwr-i2c-scl-pz6 {
977 nvidia,pins = "pwr_i2c_scl_pz6"; 978 nvidia,pins = "pwr_i2c_scl_pz6";
978 nvidia,function = "i2cpwr"; 979 nvidia,function = "i2cpwr";
979 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 980 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -981,7 +982,7 @@
981 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 982 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
982 nvidia,open-drain = <TEGRA_PIN_ENABLE>; 983 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
983 }; 984 };
984 pwr_i2c_sda_pz7 { 985 pwr-i2c-sda-pz7 {
985 nvidia,pins = "pwr_i2c_sda_pz7"; 986 nvidia,pins = "pwr_i2c_sda_pz7";
986 nvidia,function = "i2cpwr"; 987 nvidia,function = "i2cpwr";
987 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 988 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -991,7 +992,7 @@
991 }; 992 };
992 993
993 /* PWR_INT_N */ 994 /* PWR_INT_N */
994 pwr_int_n { 995 pwr-int-n {
995 nvidia,pins = "pwr_int_n"; 996 nvidia,pins = "pwr_int_n";
996 nvidia,function = "pmi"; 997 nvidia,function = "pmi";
997 nvidia,pull = <TEGRA_PIN_PULL_UP>; 998 nvidia,pull = <TEGRA_PIN_PULL_UP>;
@@ -1009,7 +1010,7 @@
1009 }; 1010 };
1010 1011
1011 /* RESET_OUT_N */ 1012 /* RESET_OUT_N */
1012 reset_out_n { 1013 reset-out-n {
1013 nvidia,pins = "reset_out_n"; 1014 nvidia,pins = "reset_out_n";
1014 nvidia,function = "reset_out_n"; 1015 nvidia,function = "reset_out_n";
1015 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1016 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -1018,14 +1019,14 @@
1018 }; 1019 };
1019 1020
1020 /* SHIFT_CTRL_DIR_IN */ 1021 /* SHIFT_CTRL_DIR_IN */
1021 kb_row0_pr0 { 1022 kb-row0-pr0 {
1022 nvidia,pins = "kb_row0_pr0"; 1023 nvidia,pins = "kb_row0_pr0";
1023 nvidia,function = "rsvd2"; 1024 nvidia,function = "rsvd2";
1024 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1025 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1025 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1026 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1026 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1027 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1027 }; 1028 };
1028 kb_row1_pr1 { 1029 kb-row1-pr1 {
1029 nvidia,pins = "kb_row1_pr1"; 1030 nvidia,pins = "kb_row1_pr1";
1030 nvidia,function = "rsvd2"; 1031 nvidia,function = "rsvd2";
1031 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1032 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
@@ -1034,7 +1035,7 @@
1034 }; 1035 };
1035 1036
1036 /* Configure level-shifter as output for HDA */ 1037 /* Configure level-shifter as output for HDA */
1037 kb_row11_ps3 { 1038 kb-row11-ps3 {
1038 nvidia,pins = "kb_row11_ps3"; 1039 nvidia,pins = "kb_row11_ps3";
1039 nvidia,function = "rsvd2"; 1040 nvidia,function = "rsvd2";
1040 nvidia,pull = <TEGRA_PIN_PULL_UP>; 1041 nvidia,pull = <TEGRA_PIN_PULL_UP>;
@@ -1043,21 +1044,21 @@
1043 }; 1044 };
1044 1045
1045 /* SHIFT_CTRL_DIR_OUT */ 1046 /* SHIFT_CTRL_DIR_OUT */
1046 kb_col5_pq5 { 1047 kb-col5-pq5 {
1047 nvidia,pins = "kb_col5_pq5"; 1048 nvidia,pins = "kb_col5_pq5";
1048 nvidia,function = "rsvd2"; 1049 nvidia,function = "rsvd2";
1049 nvidia,pull = <TEGRA_PIN_PULL_UP>; 1050 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1050 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1051 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1051 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1052 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1052 }; 1053 };
1053 kb_col6_pq6 { 1054 kb-col6-pq6 {
1054 nvidia,pins = "kb_col6_pq6"; 1055 nvidia,pins = "kb_col6_pq6";
1055 nvidia,function = "rsvd2"; 1056 nvidia,function = "rsvd2";
1056 nvidia,pull = <TEGRA_PIN_PULL_UP>; 1057 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1057 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1058 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1058 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1059 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1059 }; 1060 };
1060 kb_col7_pq7 { 1061 kb-col7-pq7 {
1061 nvidia,pins = "kb_col7_pq7"; 1062 nvidia,pins = "kb_col7_pq7";
1062 nvidia,function = "rsvd2"; 1063 nvidia,function = "rsvd2";
1063 nvidia,pull = <TEGRA_PIN_PULL_UP>; 1064 nvidia,pull = <TEGRA_PIN_PULL_UP>;
@@ -1066,35 +1067,35 @@
1066 }; 1067 };
1067 1068
1068 /* SHIFT_CTRL_OE */ 1069 /* SHIFT_CTRL_OE */
1069 kb_col0_pq0 { 1070 kb-col0-pq0 {
1070 nvidia,pins = "kb_col0_pq0"; 1071 nvidia,pins = "kb_col0_pq0";
1071 nvidia,function = "rsvd2"; 1072 nvidia,function = "rsvd2";
1072 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1073 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1073 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1074 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1074 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1075 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1075 }; 1076 };
1076 kb_col1_pq1 { 1077 kb-col1-pq1 {
1077 nvidia,pins = "kb_col1_pq1"; 1078 nvidia,pins = "kb_col1_pq1";
1078 nvidia,function = "rsvd2"; 1079 nvidia,function = "rsvd2";
1079 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1080 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1080 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1081 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1081 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1082 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1082 }; 1083 };
1083 kb_col2_pq2 { 1084 kb-col2-pq2 {
1084 nvidia,pins = "kb_col2_pq2"; 1085 nvidia,pins = "kb_col2_pq2";
1085 nvidia,function = "rsvd2"; 1086 nvidia,function = "rsvd2";
1086 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1087 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1087 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1088 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1088 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1089 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1089 }; 1090 };
1090 kb_col4_pq4 { 1091 kb-col4-pq4 {
1091 nvidia,pins = "kb_col4_pq4"; 1092 nvidia,pins = "kb_col4_pq4";
1092 nvidia,function = "kbc"; 1093 nvidia,function = "kbc";
1093 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1094 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1094 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1095 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1095 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1096 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1096 }; 1097 };
1097 kb_row2_pr2 { 1098 kb-row2-pr2 {
1098 nvidia,pins = "kb_row2_pr2"; 1099 nvidia,pins = "kb_row2_pr2";
1099 nvidia,function = "rsvd2"; 1100 nvidia,function = "rsvd2";
1100 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1101 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
@@ -1112,7 +1113,7 @@
1112 }; 1113 };
1113 1114
1114 /* TOUCH_INT */ 1115 /* TOUCH_INT */
1115 gpio_w3_aud_pw3 { 1116 gpio-w3-aud-pw3 {
1116 nvidia,pins = "gpio_w3_aud_pw3"; 1117 nvidia,pins = "gpio_w3_aud_pw3";
1117 nvidia,function = "spi6"; 1118 nvidia,function = "spi6";
1118 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1119 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -1253,189 +1254,189 @@
1253 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1254 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1254 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1255 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1255 }; 1256 };
1256 dap1_fs_pn0 { /* NC */ 1257 dap1-fs-pn0 { /* NC */
1257 nvidia,pins = "dap1_fs_pn0"; 1258 nvidia,pins = "dap1_fs_pn0";
1258 nvidia,function = "rsvd4"; 1259 nvidia,function = "rsvd4";
1259 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1260 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1260 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1261 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1261 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1262 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1262 }; 1263 };
1263 dap1_din_pn1 { /* NC */ 1264 dap1-din-pn1 { /* NC */
1264 nvidia,pins = "dap1_din_pn1"; 1265 nvidia,pins = "dap1_din_pn1";
1265 nvidia,function = "rsvd4"; 1266 nvidia,function = "rsvd4";
1266 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1267 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1267 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1268 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1268 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1269 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1269 }; 1270 };
1270 dap1_sclk_pn3 { /* NC */ 1271 dap1-sclk-pn3 { /* NC */
1271 nvidia,pins = "dap1_sclk_pn3"; 1272 nvidia,pins = "dap1_sclk_pn3";
1272 nvidia,function = "rsvd4"; 1273 nvidia,function = "rsvd4";
1273 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1274 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1274 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1275 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1275 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1276 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1276 }; 1277 };
1277 ulpi_data7_po0 { /* NC */ 1278 ulpi-data7-po0 { /* NC */
1278 nvidia,pins = "ulpi_data7_po0"; 1279 nvidia,pins = "ulpi_data7_po0";
1279 nvidia,function = "ulpi"; 1280 nvidia,function = "ulpi";
1280 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1281 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1281 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1282 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1282 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1283 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1283 }; 1284 };
1284 ulpi_data0_po1 { /* NC */ 1285 ulpi-data0-po1 { /* NC */
1285 nvidia,pins = "ulpi_data0_po1"; 1286 nvidia,pins = "ulpi_data0_po1";
1286 nvidia,function = "ulpi"; 1287 nvidia,function = "ulpi";
1287 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1288 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1288 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1289 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1289 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1290 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1290 }; 1291 };
1291 ulpi_data1_po2 { /* NC */ 1292 ulpi-data1-po2 { /* NC */
1292 nvidia,pins = "ulpi_data1_po2"; 1293 nvidia,pins = "ulpi_data1_po2";
1293 nvidia,function = "ulpi"; 1294 nvidia,function = "ulpi";
1294 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1295 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1295 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1296 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1296 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1297 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1297 }; 1298 };
1298 ulpi_data2_po3 { /* NC */ 1299 ulpi-data2-po3 { /* NC */
1299 nvidia,pins = "ulpi_data2_po3"; 1300 nvidia,pins = "ulpi_data2_po3";
1300 nvidia,function = "ulpi"; 1301 nvidia,function = "ulpi";
1301 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1302 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1302 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1303 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1303 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1304 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1304 }; 1305 };
1305 ulpi_data3_po4 { /* NC */ 1306 ulpi-data3-po4 { /* NC */
1306 nvidia,pins = "ulpi_data3_po4"; 1307 nvidia,pins = "ulpi_data3_po4";
1307 nvidia,function = "ulpi"; 1308 nvidia,function = "ulpi";
1308 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1309 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1309 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1310 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1310 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1311 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1311 }; 1312 };
1312 ulpi_data6_po7 { /* NC */ 1313 ulpi-data6-po7 { /* NC */
1313 nvidia,pins = "ulpi_data6_po7"; 1314 nvidia,pins = "ulpi_data6_po7";
1314 nvidia,function = "ulpi"; 1315 nvidia,function = "ulpi";
1315 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1316 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1316 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1317 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1317 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1318 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1318 }; 1319 };
1319 dap4_fs_pp4 { /* NC */ 1320 dap4-fs-pp4 { /* NC */
1320 nvidia,pins = "dap4_fs_pp4"; 1321 nvidia,pins = "dap4_fs_pp4";
1321 nvidia,function = "rsvd4"; 1322 nvidia,function = "rsvd4";
1322 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1323 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1323 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1324 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1324 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1325 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1325 }; 1326 };
1326 dap4_din_pp5 { /* NC */ 1327 dap4-din-pp5 { /* NC */
1327 nvidia,pins = "dap4_din_pp5"; 1328 nvidia,pins = "dap4_din_pp5";
1328 nvidia,function = "rsvd3"; 1329 nvidia,function = "rsvd3";
1329 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1330 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1330 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1331 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1331 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1332 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1332 }; 1333 };
1333 dap4_dout_pp6 { /* NC */ 1334 dap4-dout-pp6 { /* NC */
1334 nvidia,pins = "dap4_dout_pp6"; 1335 nvidia,pins = "dap4_dout_pp6";
1335 nvidia,function = "rsvd4"; 1336 nvidia,function = "rsvd4";
1336 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1337 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1337 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1338 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1338 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1339 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1339 }; 1340 };
1340 dap4_sclk_pp7 { /* NC */ 1341 dap4-sclk-pp7 { /* NC */
1341 nvidia,pins = "dap4_sclk_pp7"; 1342 nvidia,pins = "dap4_sclk_pp7";
1342 nvidia,function = "rsvd3"; 1343 nvidia,function = "rsvd3";
1343 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1344 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1344 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1345 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1345 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1346 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1346 }; 1347 };
1347 kb_col3_pq3 { /* NC */ 1348 kb-col3-pq3 { /* NC */
1348 nvidia,pins = "kb_col3_pq3"; 1349 nvidia,pins = "kb_col3_pq3";
1349 nvidia,function = "kbc"; 1350 nvidia,function = "kbc";
1350 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1351 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1351 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1352 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1352 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1353 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1353 }; 1354 };
1354 kb_row3_pr3 { /* NC */ 1355 kb-row3-pr3 { /* NC */
1355 nvidia,pins = "kb_row3_pr3"; 1356 nvidia,pins = "kb_row3_pr3";
1356 nvidia,function = "kbc"; 1357 nvidia,function = "kbc";
1357 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1358 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1358 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1359 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1359 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1360 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1360 }; 1361 };
1361 kb_row4_pr4 { /* NC */ 1362 kb-row4-pr4 { /* NC */
1362 nvidia,pins = "kb_row4_pr4"; 1363 nvidia,pins = "kb_row4_pr4";
1363 nvidia,function = "rsvd3"; 1364 nvidia,function = "rsvd3";
1364 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1365 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1365 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1366 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1366 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1367 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1367 }; 1368 };
1368 kb_row5_pr5 { /* NC */ 1369 kb-row5-pr5 { /* NC */
1369 nvidia,pins = "kb_row5_pr5"; 1370 nvidia,pins = "kb_row5_pr5";
1370 nvidia,function = "rsvd3"; 1371 nvidia,function = "rsvd3";
1371 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1372 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1372 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1373 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1373 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1374 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1374 }; 1375 };
1375 kb_row6_pr6 { /* NC */ 1376 kb-row6-pr6 { /* NC */
1376 nvidia,pins = "kb_row6_pr6"; 1377 nvidia,pins = "kb_row6_pr6";
1377 nvidia,function = "kbc"; 1378 nvidia,function = "kbc";
1378 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1379 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1379 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1380 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1380 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1381 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1381 }; 1382 };
1382 kb_row7_pr7 { /* NC */ 1383 kb-row7-pr7 { /* NC */
1383 nvidia,pins = "kb_row7_pr7"; 1384 nvidia,pins = "kb_row7_pr7";
1384 nvidia,function = "rsvd2"; 1385 nvidia,function = "rsvd2";
1385 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1386 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1386 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1387 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1387 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1388 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1388 }; 1389 };
1389 kb_row8_ps0 { /* NC */ 1390 kb-row8-ps0 { /* NC */
1390 nvidia,pins = "kb_row8_ps0"; 1391 nvidia,pins = "kb_row8_ps0";
1391 nvidia,function = "rsvd2"; 1392 nvidia,function = "rsvd2";
1392 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1393 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1393 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1394 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1394 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1395 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1395 }; 1396 };
1396 kb_row9_ps1 { /* NC */ 1397 kb-row9-ps1 { /* NC */
1397 nvidia,pins = "kb_row9_ps1"; 1398 nvidia,pins = "kb_row9_ps1";
1398 nvidia,function = "rsvd2"; 1399 nvidia,function = "rsvd2";
1399 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1400 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1400 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1401 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1401 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1402 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1402 }; 1403 };
1403 kb_row12_ps4 { /* NC */ 1404 kb-row12-ps4 { /* NC */
1404 nvidia,pins = "kb_row12_ps4"; 1405 nvidia,pins = "kb_row12_ps4";
1405 nvidia,function = "rsvd2"; 1406 nvidia,function = "rsvd2";
1406 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1407 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1407 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1408 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1408 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1409 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1409 }; 1410 };
1410 kb_row13_ps5 { /* NC */ 1411 kb-row13-ps5 { /* NC */
1411 nvidia,pins = "kb_row13_ps5"; 1412 nvidia,pins = "kb_row13_ps5";
1412 nvidia,function = "rsvd2"; 1413 nvidia,function = "rsvd2";
1413 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1414 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1414 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1415 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1415 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1416 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1416 }; 1417 };
1417 kb_row14_ps6 { /* NC */ 1418 kb-row14-ps6 { /* NC */
1418 nvidia,pins = "kb_row14_ps6"; 1419 nvidia,pins = "kb_row14_ps6";
1419 nvidia,function = "rsvd2"; 1420 nvidia,function = "rsvd2";
1420 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1421 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1421 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1422 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1422 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1423 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1423 }; 1424 };
1424 kb_row15_ps7 { /* NC */ 1425 kb-row15-ps7 { /* NC */
1425 nvidia,pins = "kb_row15_ps7"; 1426 nvidia,pins = "kb_row15_ps7";
1426 nvidia,function = "rsvd3"; 1427 nvidia,function = "rsvd3";
1427 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1428 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1428 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1429 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1429 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1430 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1430 }; 1431 };
1431 kb_row16_pt0 { /* NC */ 1432 kb-row16-pt0 { /* NC */
1432 nvidia,pins = "kb_row16_pt0"; 1433 nvidia,pins = "kb_row16_pt0";
1433 nvidia,function = "rsvd2"; 1434 nvidia,function = "rsvd2";
1434 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1435 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1435 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1436 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1436 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1437 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1437 }; 1438 };
1438 kb_row17_pt1 { /* NC */ 1439 kb-row17-pt1 { /* NC */
1439 nvidia,pins = "kb_row17_pt1"; 1440 nvidia,pins = "kb_row17_pt1";
1440 nvidia,function = "rsvd2"; 1441 nvidia,function = "rsvd2";
1441 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1442 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
@@ -1467,14 +1468,14 @@
1467 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1468 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1468 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1469 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1469 }; 1470 };
1470 gpio_x1_aud_px1 { /* NC */ 1471 gpio-x1-aud-px1 { /* NC */
1471 nvidia,pins = "gpio_x1_aud_px1"; 1472 nvidia,pins = "gpio_x1_aud_px1";
1472 nvidia,function = "rsvd2"; 1473 nvidia,function = "rsvd2";
1473 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1474 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1474 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1475 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1475 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1476 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1476 }; 1477 };
1477 gpio_x3_aud_px3 { /* NC */ 1478 gpio-x3-aud-px3 { /* NC */
1478 nvidia,pins = "gpio_x3_aud_px3"; 1479 nvidia,pins = "gpio_x3_aud_px3";
1479 nvidia,function = "rsvd4"; 1480 nvidia,function = "rsvd4";
1480 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1481 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
@@ -1502,14 +1503,14 @@
1502 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1503 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1503 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1504 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1504 }; 1505 };
1505 clk3_req_pee1 { /* NC */ 1506 clk3-req-pee1 { /* NC */
1506 nvidia,pins = "clk3_req_pee1"; 1507 nvidia,pins = "clk3_req_pee1";
1507 nvidia,function = "rsvd2"; 1508 nvidia,function = "rsvd2";
1508 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1509 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1509 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1510 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1510 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1511 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1511 }; 1512 };
1512 dap_mclk1_req_pee2 { /* NC */ 1513 dap-mclk1-req-pee2 { /* NC */
1513 nvidia,pins = "dap_mclk1_req_pee2"; 1514 nvidia,pins = "dap_mclk1_req_pee2";
1514 nvidia,function = "rsvd4"; 1515 nvidia,function = "rsvd4";
1515 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1516 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
@@ -1525,7 +1526,7 @@
1525 * SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1 1526 * SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1
1526 * bits being set to 0xfffd according to the TRM! 1527 * bits being set to 0xfffd according to the TRM!
1527 */ 1528 */
1528 sdmmc3_clk_lb_out_pee4 { /* NC */ 1529 sdmmc3-clk-lb-out-pee4 { /* NC */
1529 nvidia,pins = "sdmmc3_clk_lb_out_pee4"; 1530 nvidia,pins = "sdmmc3_clk_lb_out_pee4";
1530 nvidia,function = "sdmmc3"; 1531 nvidia,function = "sdmmc3";
1531 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1532 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -1560,8 +1561,9 @@
1560 sgtl5000: codec@a { 1561 sgtl5000: codec@a {
1561 compatible = "fsl,sgtl5000"; 1562 compatible = "fsl,sgtl5000";
1562 reg = <0x0a>; 1563 reg = <0x0a>;
1563 VDDA-supply = <&reg_3v3>; 1564 VDDA-supply = <&reg_module_3v3_audio>;
1564 VDDIO-supply = <&vddio_1v8>; 1565 VDDD-supply = <&reg_1v8_vddio>;
1566 VDDIO-supply = <&reg_1v8_vddio>;
1565 clocks = <&tegra_car TEGRA124_CLK_EXTERN1>; 1567 clocks = <&tegra_car TEGRA124_CLK_EXTERN1>;
1566 }; 1568 };
1567 1569
@@ -1578,14 +1580,14 @@
1578 pinctrl-0 = <&as3722_default>; 1580 pinctrl-0 = <&as3722_default>;
1579 1581
1580 as3722_default: pinmux { 1582 as3722_default: pinmux {
1581 gpio2_7 { 1583 gpio2-7 {
1582 pins = "gpio2", /* PWR_EN_+V3.3 */ 1584 pins = "gpio2", /* PWR_EN_+V3.3 */
1583 "gpio7"; /* +V1.6_LPO */ 1585 "gpio7"; /* +V1.6_LPO */
1584 function = "gpio"; 1586 function = "gpio";
1585 bias-pull-up; 1587 bias-pull-up;
1586 }; 1588 };
1587 1589
1588 gpio0_1_3_4_5_6 { 1590 gpio0-1-3-4-5-6 {
1589 pins = "gpio0", "gpio1", "gpio3", 1591 pins = "gpio0", "gpio1", "gpio3",
1590 "gpio4", "gpio5", "gpio6"; 1592 "gpio4", "gpio5", "gpio6";
1591 bias-high-impedance; 1593 bias-high-impedance;
@@ -1593,18 +1595,18 @@
1593 }; 1595 };
1594 1596
1595 regulators { 1597 regulators {
1596 vsup-sd2-supply = <&reg_3v3>; 1598 vsup-sd2-supply = <&reg_module_3v3>;
1597 vsup-sd3-supply = <&reg_3v3>; 1599 vsup-sd3-supply = <&reg_module_3v3>;
1598 vsup-sd4-supply = <&reg_3v3>; 1600 vsup-sd4-supply = <&reg_module_3v3>;
1599 vsup-sd5-supply = <&reg_3v3>; 1601 vsup-sd5-supply = <&reg_module_3v3>;
1600 vin-ldo0-supply = <&vddio_ddr_1v35>; 1602 vin-ldo0-supply = <&reg_1v35_vddio_ddr>;
1601 vin-ldo1-6-supply = <&reg_3v3>; 1603 vin-ldo1-6-supply = <&reg_module_3v3>;
1602 vin-ldo2-5-7-supply = <&vddio_1v8>; 1604 vin-ldo2-5-7-supply = <&reg_1v8_vddio>;
1603 vin-ldo3-4-supply = <&reg_3v3>; 1605 vin-ldo3-4-supply = <&reg_module_3v3>;
1604 vin-ldo9-10-supply = <&reg_3v3>; 1606 vin-ldo9-10-supply = <&reg_module_3v3>;
1605 vin-ldo11-supply = <&reg_3v3>; 1607 vin-ldo11-supply = <&reg_module_3v3>;
1606 1608
1607 vdd_cpu: sd0 { 1609 reg_vdd_cpu: sd0 {
1608 regulator-name = "+VDD_CPU_AP"; 1610 regulator-name = "+VDD_CPU_AP";
1609 regulator-min-microvolt = <700000>; 1611 regulator-min-microvolt = <700000>;
1610 regulator-max-microvolt = <1400000>; 1612 regulator-max-microvolt = <1400000>;
@@ -1626,7 +1628,7 @@
1626 ams,ext-control = <1>; 1628 ams,ext-control = <1>;
1627 }; 1629 };
1628 1630
1629 vddio_ddr_1v35: sd2 { 1631 reg_1v35_vddio_ddr: sd2 {
1630 regulator-name = 1632 regulator-name =
1631 "+V1.35_VDDIO_DDR(sd2)"; 1633 "+V1.35_VDDIO_DDR(sd2)";
1632 regulator-min-microvolt = <1350000>; 1634 regulator-min-microvolt = <1350000>;
@@ -1644,13 +1646,13 @@
1644 regulator-boot-on; 1646 regulator-boot-on;
1645 }; 1647 };
1646 1648
1647 vdd_1v05: sd4 { 1649 reg_1v05_vdd: sd4 {
1648 regulator-name = "+V1.05"; 1650 regulator-name = "+V1.05";
1649 regulator-min-microvolt = <1050000>; 1651 regulator-min-microvolt = <1050000>;
1650 regulator-max-microvolt = <1050000>; 1652 regulator-max-microvolt = <1050000>;
1651 }; 1653 };
1652 1654
1653 vddio_1v8: sd5 { 1655 reg_1v8_vddio: sd5 {
1654 regulator-name = "+V1.8"; 1656 regulator-name = "+V1.8";
1655 regulator-min-microvolt = <1800000>; 1657 regulator-min-microvolt = <1800000>;
1656 regulator-max-microvolt = <1800000>; 1658 regulator-max-microvolt = <1800000>;
@@ -1658,7 +1660,7 @@
1658 regulator-always-on; 1660 regulator-always-on;
1659 }; 1661 };
1660 1662
1661 vdd_gpu: sd6 { 1663 reg_vdd_gpu: sd6 {
1662 regulator-name = "+VDD_GPU_AP"; 1664 regulator-name = "+VDD_GPU_AP";
1663 regulator-min-microvolt = <650000>; 1665 regulator-min-microvolt = <650000>;
1664 regulator-max-microvolt = <1200000>; 1666 regulator-max-microvolt = <1200000>;
@@ -1668,7 +1670,7 @@
1668 regulator-always-on; 1670 regulator-always-on;
1669 }; 1671 };
1670 1672
1671 avdd_1v05: ldo0 { 1673 reg_1v05_avdd: ldo0 {
1672 regulator-name = "+V1.05_AVDD"; 1674 regulator-name = "+V1.05_AVDD";
1673 regulator-min-microvolt = <1050000>; 1675 regulator-min-microvolt = <1050000>;
1674 regulator-max-microvolt = <1050000>; 1676 regulator-max-microvolt = <1050000>;
@@ -1743,12 +1745,13 @@
1743 * TMP451 temperature sensor 1745 * TMP451 temperature sensor
1744 * Note: THERM_N directly connected to AS3722 PMIC THERM 1746 * Note: THERM_N directly connected to AS3722 PMIC THERM
1745 */ 1747 */
1746 temperature-sensor@4c { 1748 temp-sensor@4c {
1747 compatible = "ti,tmp451"; 1749 compatible = "ti,tmp451";
1748 reg = <0x4c>; 1750 reg = <0x4c>;
1749 interrupt-parent = <&gpio>; 1751 interrupt-parent = <&gpio>;
1750 interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_LEVEL_LOW>; 1752 interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_LEVEL_LOW>;
1751 #thermal-sensor-cells = <1>; 1753 #thermal-sensor-cells = <1>;
1754 vcc-supply = <&reg_module_3v3>;
1752 }; 1755 };
1753 }; 1756 };
1754 1757
@@ -1780,9 +1783,9 @@
1780 sata@70020000 { 1783 sata@70020000 {
1781 phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>; 1784 phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>;
1782 phy-names = "sata-0"; 1785 phy-names = "sata-0";
1783 avdd-supply = <&vdd_1v05>; 1786 avdd-supply = <&reg_1v05_vdd>;
1784 hvdd-supply = <&reg_3v3>; 1787 hvdd-supply = <&reg_module_3v3>;
1785 vddio-supply = <&vdd_1v05>; 1788 vddio-supply = <&reg_1v05_vdd>;
1786 }; 1789 };
1787 1790
1788 usb@70090000 { 1791 usb@70090000 {
@@ -1793,14 +1796,14 @@
1793 <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, 1796 <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>,
1794 <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>; 1797 <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>;
1795 phy-names = "usb2-0", "usb3-1", "usb2-1", "usb2-2", "usb3-0"; 1798 phy-names = "usb2-0", "usb3-1", "usb2-1", "usb2-2", "usb3-0";
1796 avddio-pex-supply = <&vdd_1v05>; 1799 avddio-pex-supply = <&reg_1v05_vdd>;
1797 avdd-pll-erefe-supply = <&avdd_1v05>; 1800 avdd-pll-erefe-supply = <&reg_1v05_avdd>;
1798 avdd-pll-utmip-supply = <&vddio_1v8>; 1801 avdd-pll-utmip-supply = <&reg_1v8_vddio>;
1799 avdd-usb-ss-pll-supply = <&vdd_1v05>; 1802 avdd-usb-ss-pll-supply = <&reg_1v05_vdd>;
1800 avdd-usb-supply = <&reg_3v3>; 1803 avdd-usb-supply = <&reg_module_3v3>;
1801 dvddio-pex-supply = <&vdd_1v05>; 1804 dvddio-pex-supply = <&reg_1v05_vdd>;
1802 hvdd-usb-ss-pll-e-supply = <&reg_3v3>; 1805 hvdd-usb-ss-pll-e-supply = <&reg_module_3v3>;
1803 hvdd-usb-ss-supply = <&reg_3v3>; 1806 hvdd-usb-ss-supply = <&reg_module_3v3>;
1804 }; 1807 };
1805 1808
1806 padctl@7009f000 { 1809 padctl@7009f000 {
@@ -1810,18 +1813,18 @@
1810 1813
1811 lanes { 1814 lanes {
1812 usb2-0 { 1815 usb2-0 {
1813 nvidia,function = "xusb";
1814 status = "okay"; 1816 status = "okay";
1817 nvidia,function = "xusb";
1815 }; 1818 };
1816 1819
1817 usb2-1 { 1820 usb2-1 {
1818 nvidia,function = "xusb";
1819 status = "okay"; 1821 status = "okay";
1822 nvidia,function = "xusb";
1820 }; 1823 };
1821 1824
1822 usb2-2 { 1825 usb2-2 {
1823 nvidia,function = "xusb";
1824 status = "okay"; 1826 status = "okay";
1827 nvidia,function = "xusb";
1825 }; 1828 };
1826 }; 1829 };
1827 }; 1830 };
@@ -1831,28 +1834,28 @@
1831 1834
1832 lanes { 1835 lanes {
1833 pcie-0 { 1836 pcie-0 {
1834 nvidia,function = "usb3-ss";
1835 status = "okay"; 1837 status = "okay";
1838 nvidia,function = "usb3-ss";
1836 }; 1839 };
1837 1840
1838 pcie-1 { 1841 pcie-1 {
1839 nvidia,function = "usb3-ss";
1840 status = "okay"; 1842 status = "okay";
1843 nvidia,function = "usb3-ss";
1841 }; 1844 };
1842 1845
1843 pcie-2 { 1846 pcie-2 {
1844 nvidia,function = "pcie";
1845 status = "okay"; 1847 status = "okay";
1848 nvidia,function = "pcie";
1846 }; 1849 };
1847 1850
1848 pcie-3 { 1851 pcie-3 {
1849 nvidia,function = "pcie";
1850 status = "okay"; 1852 status = "okay";
1853 nvidia,function = "pcie";
1851 }; 1854 };
1852 1855
1853 pcie-4 { 1856 pcie-4 {
1854 nvidia,function = "pcie";
1855 status = "okay"; 1857 status = "okay";
1858 nvidia,function = "pcie";
1856 }; 1859 };
1857 }; 1860 };
1858 }; 1861 };
@@ -1862,8 +1865,8 @@
1862 1865
1863 lanes { 1866 lanes {
1864 sata-0 { 1867 sata-0 {
1865 nvidia,function = "sata";
1866 status = "okay"; 1868 status = "okay";
1869 nvidia,function = "sata";
1867 }; 1870 };
1868 }; 1871 };
1869 }; 1872 };
@@ -1874,7 +1877,6 @@
1874 usb2-0 { 1877 usb2-0 {
1875 status = "okay"; 1878 status = "okay";
1876 mode = "otg"; 1879 mode = "otg";
1877
1878 vbus-supply = <&reg_usbo1_vbus>; 1880 vbus-supply = <&reg_usbo1_vbus>;
1879 }; 1881 };
1880 1882
@@ -1882,7 +1884,6 @@
1882 usb2-1 { 1884 usb2-1 {
1883 status = "okay"; 1885 status = "okay";
1884 mode = "host"; 1886 mode = "host";
1885
1886 vbus-supply = <&reg_usbh_vbus>; 1887 vbus-supply = <&reg_usbh_vbus>;
1887 }; 1888 };
1888 1889
@@ -1890,18 +1891,19 @@
1890 usb2-2 { 1891 usb2-2 {
1891 status = "okay"; 1892 status = "okay";
1892 mode = "host"; 1893 mode = "host";
1893
1894 vbus-supply = <&reg_usbh_vbus>; 1894 vbus-supply = <&reg_usbh_vbus>;
1895 }; 1895 };
1896 1896
1897 usb3-0 { 1897 usb3-0 {
1898 nvidia,usb2-companion = <2>;
1899 status = "okay"; 1898 status = "okay";
1899 nvidia,usb2-companion = <2>;
1900 vbus-supply = <&reg_usbh_vbus>;
1900 }; 1901 };
1901 1902
1902 usb3-1 { 1903 usb3-1 {
1903 nvidia,usb2-companion = <0>;
1904 status = "okay"; 1904 status = "okay";
1905 nvidia,usb2-companion = <0>;
1906 vbus-supply = <&reg_usbo1_vbus>;
1905 }; 1907 };
1906 }; 1908 };
1907 }; 1909 };
@@ -1911,13 +1913,16 @@
1911 status = "okay"; 1913 status = "okay";
1912 bus-width = <8>; 1914 bus-width = <8>;
1913 non-removable; 1915 non-removable;
1916 vmmc-supply = <&reg_module_3v3>; /* VCC */
1917 vqmmc-supply = <&reg_1v8_vddio>; /* VCCQ */
1918 mmc-ddr-1_8v;
1914 }; 1919 };
1915 1920
1916 /* CPU DFLL clock */ 1921 /* CPU DFLL clock */
1917 clock@70110000 { 1922 clock@70110000 {
1918 status = "okay"; 1923 status = "okay";
1919 vdd-cpu-supply = <&vdd_cpu>;
1920 nvidia,i2c-fs-rate = <400000>; 1924 nvidia,i2c-fs-rate = <400000>;
1925 vdd-cpu-supply = <&reg_vdd_cpu>;
1921 }; 1926 };
1922 1927
1923 ahub@70300000 { 1928 ahub@70300000 {
@@ -1926,22 +1931,15 @@
1926 }; 1931 };
1927 }; 1932 };
1928 1933
1929 clocks { 1934 clk32k_in: osc3 {
1930 compatible = "simple-bus"; 1935 compatible = "fixed-clock";
1931 #address-cells = <1>; 1936 #clock-cells = <0>;
1932 #size-cells = <0>; 1937 clock-frequency = <32768>;
1933
1934 clk32k_in: clock@0 {
1935 compatible = "fixed-clock";
1936 reg = <0>;
1937 #clock-cells = <0>;
1938 clock-frequency = <32768>;
1939 };
1940 }; 1938 };
1941 1939
1942 cpus { 1940 cpus {
1943 cpu@0 { 1941 cpu@0 {
1944 vdd-cpu-supply = <&vdd_cpu>; 1942 vdd-cpu-supply = <&reg_vdd_cpu>;
1945 }; 1943 };
1946 }; 1944 };
1947 1945
@@ -1951,7 +1949,7 @@
1951 regulator-min-microvolt = <1050000>; 1949 regulator-min-microvolt = <1050000>;
1952 regulator-max-microvolt = <1050000>; 1950 regulator-max-microvolt = <1050000>;
1953 gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; 1951 gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>;
1954 vin-supply = <&vdd_1v05>; 1952 vin-supply = <&reg_1v05_vdd>;
1955 }; 1953 };
1956 1954
1957 reg_3v3_mxm: regulator-3v3-mxm { 1955 reg_3v3_mxm: regulator-3v3-mxm {
@@ -1963,7 +1961,15 @@
1963 regulator-boot-on; 1961 regulator-boot-on;
1964 }; 1962 };
1965 1963
1966 reg_3v3: regulator-3v3 { 1964 reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi {
1965 compatible = "regulator-fixed";
1966 regulator-name = "+V3.3_AVDD_HDMI";
1967 regulator-min-microvolt = <3300000>;
1968 regulator-max-microvolt = <3300000>;
1969 vin-supply = <&reg_1v05_vdd>;
1970 };
1971
1972 reg_module_3v3: regulator-module-3v3 {
1967 compatible = "regulator-fixed"; 1973 compatible = "regulator-fixed";
1968 regulator-name = "+V3.3"; 1974 regulator-name = "+V3.3";
1969 regulator-min-microvolt = <3300000>; 1975 regulator-min-microvolt = <3300000>;
@@ -1976,12 +1982,12 @@
1976 vin-supply = <&reg_3v3_mxm>; 1982 vin-supply = <&reg_3v3_mxm>;
1977 }; 1983 };
1978 1984
1979 reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi { 1985 reg_module_3v3_audio: regulator-module-3v3-audio {
1980 compatible = "regulator-fixed"; 1986 compatible = "regulator-fixed";
1981 regulator-name = "+V3.3_AVDD_HDMI"; 1987 regulator-name = "+V3.3_AUDIO_AVDD_S";
1982 regulator-min-microvolt = <3300000>; 1988 regulator-min-microvolt = <3300000>;
1983 regulator-max-microvolt = <3300000>; 1989 regulator-max-microvolt = <3300000>;
1984 vin-supply = <&vdd_1v05>; 1990 regulator-always-on;
1985 }; 1991 };
1986 1992
1987 sound { 1993 sound {
@@ -2035,7 +2041,7 @@
2035 2041
2036&gpio { 2042&gpio {
2037 /* I210 Gigabit Ethernet Controller Reset */ 2043 /* I210 Gigabit Ethernet Controller Reset */
2038 lan_reset_n { 2044 lan-reset-n {
2039 gpio-hog; 2045 gpio-hog;
2040 gpios = <TEGRA_GPIO(S, 2) GPIO_ACTIVE_HIGH>; 2046 gpios = <TEGRA_GPIO(S, 2) GPIO_ACTIVE_HIGH>;
2041 output-high; 2047 output-high;
@@ -2043,7 +2049,7 @@
2043 }; 2049 };
2044 2050
2045 /* Control MXM3 pin 26 Reset Module Output Carrier Input */ 2051 /* Control MXM3 pin 26 Reset Module Output Carrier Input */
2046 reset_moci_ctrl { 2052 reset-moci-ctrl {
2047 gpio-hog; 2053 gpio-hog;
2048 gpios = <TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>; 2054 gpios = <TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>;
2049 output-high; 2055 output-high;
diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/tegra124-apalis.dtsi
index 0f0d4a4988b9..13c93cd507d8 100644
--- a/arch/arm/boot/dts/tegra124-apalis.dtsi
+++ b/arch/arm/boot/dts/tegra124-apalis.dtsi
@@ -47,22 +47,19 @@
47 * Compatible for Revisions 2GB: V1.0A, V1.0B, V1.1A 47 * Compatible for Revisions 2GB: V1.0A, V1.0B, V1.1A
48 */ 48 */
49/ { 49/ {
50 model = "Toradex Apalis TK1";
51 compatible = "toradex,apalis-tk1", "nvidia,tegra124";
52
53 memory@80000000 { 50 memory@80000000 {
54 reg = <0x0 0x80000000 0x0 0x80000000>; 51 reg = <0x0 0x80000000 0x0 0x80000000>;
55 }; 52 };
56 53
57 pcie@1003000 { 54 pcie@1003000 {
58 status = "okay"; 55 status = "okay";
59 avddio-pex-supply = <&vdd_1v05>; 56 avddio-pex-supply = <&reg_1v05_vdd>;
60 avdd-pex-pll-supply = <&vdd_1v05>; 57 avdd-pex-pll-supply = <&reg_1v05_vdd>;
61 avdd-pll-erefe-supply = <&avdd_1v05>; 58 avdd-pll-erefe-supply = <&reg_1v05_avdd>;
62 dvddio-pex-supply = <&vdd_1v05>; 59 dvddio-pex-supply = <&reg_1v05_vdd>;
63 hvdd-pex-pll-e-supply = <&reg_3v3>; 60 hvdd-pex-pll-e-supply = <&reg_module_3v3>;
64 hvdd-pex-supply = <&reg_3v3>; 61 hvdd-pex-supply = <&reg_module_3v3>;
65 vddio-pex-ctl-supply = <&reg_3v3>; 62 vddio-pex-ctl-supply = <&reg_module_3v3>;
66 63
67 /* Apalis PCIe (additional lane Apalis type specific) */ 64 /* Apalis PCIe (additional lane Apalis type specific) */
68 pci@1,0 { 65 pci@1,0 {
@@ -77,16 +74,21 @@
77 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>; 74 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>;
78 phy-names = "pcie-0"; 75 phy-names = "pcie-0";
79 status = "okay"; 76 status = "okay";
77
78 pcie@0 {
79 reg = <0 0 0 0 0>;
80 local-mac-address = [00 00 00 00 00 00];
81 };
80 }; 82 };
81 }; 83 };
82 84
83 host1x@50000000 { 85 host1x@50000000 {
84 hdmi@54280000 { 86 hdmi@54280000 {
85 pll-supply = <&reg_1v05_avdd_hdmi_pll>;
86 vdd-supply = <&reg_3v3_avdd_hdmi>;
87 nvidia,ddc-i2c-bus = <&hdmi_ddc>; 87 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
88 nvidia,hpd-gpio = 88 nvidia,hpd-gpio =
89 <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; 89 <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
90 pll-supply = <&reg_1v05_avdd_hdmi_pll>;
91 vdd-supply = <&reg_3v3_avdd_hdmi>;
90 }; 92 };
91 }; 93 };
92 94
@@ -95,44 +97,44 @@
95 * Node left disabled on purpose - the bootloader will enable 97 * Node left disabled on purpose - the bootloader will enable
96 * it after having set the VPR up 98 * it after having set the VPR up
97 */ 99 */
98 vdd-supply = <&vdd_gpu>; 100 vdd-supply = <&reg_vdd_gpu>;
99 }; 101 };
100 102
101 pinmux: pinmux@70000868 { 103 pinmux@70000868 {
102 pinctrl-names = "default"; 104 pinctrl-names = "default";
103 pinctrl-0 = <&state_default>; 105 pinctrl-0 = <&state_default>;
104 106
105 state_default: pinmux { 107 state_default: pinmux {
106 /* Analogue Audio (On-module) */ 108 /* Analogue Audio (On-module) */
107 dap3_fs_pp0 { 109 dap3-fs-pp0 {
108 nvidia,pins = "dap3_fs_pp0"; 110 nvidia,pins = "dap3_fs_pp0";
109 nvidia,function = "i2s2"; 111 nvidia,function = "i2s2";
110 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 112 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
111 nvidia,tristate = <TEGRA_PIN_DISABLE>; 113 nvidia,tristate = <TEGRA_PIN_DISABLE>;
112 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 114 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
113 }; 115 };
114 dap3_din_pp1 { 116 dap3-din-pp1 {
115 nvidia,pins = "dap3_din_pp1"; 117 nvidia,pins = "dap3_din_pp1";
116 nvidia,function = "i2s2"; 118 nvidia,function = "i2s2";
117 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 119 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
118 nvidia,tristate = <TEGRA_PIN_ENABLE>; 120 nvidia,tristate = <TEGRA_PIN_ENABLE>;
119 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 121 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
120 }; 122 };
121 dap3_dout_pp2 { 123 dap3-dout-pp2 {
122 nvidia,pins = "dap3_dout_pp2"; 124 nvidia,pins = "dap3_dout_pp2";
123 nvidia,function = "i2s2"; 125 nvidia,function = "i2s2";
124 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 126 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
125 nvidia,tristate = <TEGRA_PIN_DISABLE>; 127 nvidia,tristate = <TEGRA_PIN_DISABLE>;
126 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 128 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
127 }; 129 };
128 dap3_sclk_pp3 { 130 dap3-sclk-pp3 {
129 nvidia,pins = "dap3_sclk_pp3"; 131 nvidia,pins = "dap3_sclk_pp3";
130 nvidia,function = "i2s2"; 132 nvidia,function = "i2s2";
131 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 133 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
132 nvidia,tristate = <TEGRA_PIN_DISABLE>; 134 nvidia,tristate = <TEGRA_PIN_DISABLE>;
133 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 135 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
134 }; 136 };
135 dap_mclk1_pw4 { 137 dap-mclk1-pw4 {
136 nvidia,pins = "dap_mclk1_pw4"; 138 nvidia,pins = "dap_mclk1_pw4";
137 nvidia,function = "extperiph1"; 139 nvidia,function = "extperiph1";
138 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 140 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -159,7 +161,7 @@
159 }; 161 };
160 162
161 /* Apalis CAM1_MCLK */ 163 /* Apalis CAM1_MCLK */
162 cam_mclk_pcc0 { 164 cam-mclk-pcc0 {
163 nvidia,pins = "cam_mclk_pcc0"; 165 nvidia,pins = "cam_mclk_pcc0";
164 nvidia,function = "vi_alt3"; 166 nvidia,function = "vi_alt3";
165 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 167 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -168,28 +170,28 @@
168 }; 170 };
169 171
170 /* Apalis Digital Audio */ 172 /* Apalis Digital Audio */
171 dap2_fs_pa2 { 173 dap2-fs-pa2 {
172 nvidia,pins = "dap2_fs_pa2"; 174 nvidia,pins = "dap2_fs_pa2";
173 nvidia,function = "hda"; 175 nvidia,function = "hda";
174 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 176 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
175 nvidia,tristate = <TEGRA_PIN_DISABLE>; 177 nvidia,tristate = <TEGRA_PIN_DISABLE>;
176 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 178 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
177 }; 179 };
178 dap2_sclk_pa3 { 180 dap2-sclk-pa3 {
179 nvidia,pins = "dap2_sclk_pa3"; 181 nvidia,pins = "dap2_sclk_pa3";
180 nvidia,function = "hda"; 182 nvidia,function = "hda";
181 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 183 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
182 nvidia,tristate = <TEGRA_PIN_DISABLE>; 184 nvidia,tristate = <TEGRA_PIN_DISABLE>;
183 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 185 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
184 }; 186 };
185 dap2_din_pa4 { 187 dap2-din-pa4 {
186 nvidia,pins = "dap2_din_pa4"; 188 nvidia,pins = "dap2_din_pa4";
187 nvidia,function = "hda"; 189 nvidia,function = "hda";
188 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 190 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
189 nvidia,tristate = <TEGRA_PIN_ENABLE>; 191 nvidia,tristate = <TEGRA_PIN_ENABLE>;
190 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 192 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
191 }; 193 };
192 dap2_dout_pa5 { 194 dap2-dout-pa5 {
193 nvidia,pins = "dap2_dout_pa5"; 195 nvidia,pins = "dap2_dout_pa5";
194 nvidia,function = "hda"; 196 nvidia,function = "hda";
195 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 197 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -202,7 +204,7 @@
202 nvidia,tristate = <TEGRA_PIN_DISABLE>; 204 nvidia,tristate = <TEGRA_PIN_DISABLE>;
203 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 205 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
204 }; 206 };
205 clk3_out_pee0 { 207 clk3-out-pee0 {
206 nvidia,pins = "clk3_out_pee0"; 208 nvidia,pins = "clk3_out_pee0";
207 nvidia,function = "extperiph3"; 209 nvidia,function = "extperiph3";
208 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 210 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -211,49 +213,49 @@
211 }; 213 };
212 214
213 /* Apalis GPIO */ 215 /* Apalis GPIO */
214 ddc_scl_pv4 { 216 ddc-scl-pv4 {
215 nvidia,pins = "ddc_scl_pv4"; 217 nvidia,pins = "ddc_scl_pv4";
216 nvidia,function = "rsvd2"; 218 nvidia,function = "rsvd2";
217 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 219 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
218 nvidia,tristate = <TEGRA_PIN_DISABLE>; 220 nvidia,tristate = <TEGRA_PIN_DISABLE>;
219 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 221 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
220 }; 222 };
221 ddc_sda_pv5 { 223 ddc-sda-pv5 {
222 nvidia,pins = "ddc_sda_pv5"; 224 nvidia,pins = "ddc_sda_pv5";
223 nvidia,function = "rsvd2"; 225 nvidia,function = "rsvd2";
224 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 226 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
225 nvidia,tristate = <TEGRA_PIN_DISABLE>; 227 nvidia,tristate = <TEGRA_PIN_DISABLE>;
226 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 228 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
227 }; 229 };
228 pex_l0_rst_n_pdd1 { 230 pex-l0-rst-n-pdd1 {
229 nvidia,pins = "pex_l0_rst_n_pdd1"; 231 nvidia,pins = "pex_l0_rst_n_pdd1";
230 nvidia,function = "rsvd2"; 232 nvidia,function = "rsvd2";
231 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 233 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
232 nvidia,tristate = <TEGRA_PIN_DISABLE>; 234 nvidia,tristate = <TEGRA_PIN_DISABLE>;
233 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 235 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
234 }; 236 };
235 pex_l0_clkreq_n_pdd2 { 237 pex-l0-clkreq-n-pdd2 {
236 nvidia,pins = "pex_l0_clkreq_n_pdd2"; 238 nvidia,pins = "pex_l0_clkreq_n_pdd2";
237 nvidia,function = "rsvd2"; 239 nvidia,function = "rsvd2";
238 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 240 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
239 nvidia,tristate = <TEGRA_PIN_DISABLE>; 241 nvidia,tristate = <TEGRA_PIN_DISABLE>;
240 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 242 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
241 }; 243 };
242 pex_l1_rst_n_pdd5 { 244 pex-l1-rst-n-pdd5 {
243 nvidia,pins = "pex_l1_rst_n_pdd5"; 245 nvidia,pins = "pex_l1_rst_n_pdd5";
244 nvidia,function = "rsvd2"; 246 nvidia,function = "rsvd2";
245 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 247 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
246 nvidia,tristate = <TEGRA_PIN_DISABLE>; 248 nvidia,tristate = <TEGRA_PIN_DISABLE>;
247 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 249 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
248 }; 250 };
249 pex_l1_clkreq_n_pdd6 { 251 pex-l1-clkreq-n-pdd6 {
250 nvidia,pins = "pex_l1_clkreq_n_pdd6"; 252 nvidia,pins = "pex_l1_clkreq_n_pdd6";
251 nvidia,function = "rsvd2"; 253 nvidia,function = "rsvd2";
252 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 254 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
253 nvidia,tristate = <TEGRA_PIN_DISABLE>; 255 nvidia,tristate = <TEGRA_PIN_DISABLE>;
254 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 256 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
255 }; 257 };
256 dp_hpd_pff0 { 258 dp-hpd-pff0 {
257 nvidia,pins = "dp_hpd_pff0"; 259 nvidia,pins = "dp_hpd_pff0";
258 nvidia,function = "dp"; 260 nvidia,function = "dp";
259 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 261 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -277,7 +279,7 @@
277 }; 279 };
278 280
279 /* Apalis HDMI1_CEC */ 281 /* Apalis HDMI1_CEC */
280 hdmi_cec_pee3 { 282 hdmi-cec-pee3 {
281 nvidia,pins = "hdmi_cec_pee3"; 283 nvidia,pins = "hdmi_cec_pee3";
282 nvidia,function = "cec"; 284 nvidia,function = "cec";
283 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 285 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -287,7 +289,7 @@
287 }; 289 };
288 290
289 /* Apalis HDMI1_HPD */ 291 /* Apalis HDMI1_HPD */
290 hdmi_int_pn7 { 292 hdmi-int-pn7 {
291 nvidia,pins = "hdmi_int_pn7"; 293 nvidia,pins = "hdmi_int_pn7";
292 nvidia,function = "rsvd1"; 294 nvidia,function = "rsvd1";
293 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 295 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
@@ -297,7 +299,7 @@
297 }; 299 };
298 300
299 /* Apalis I2C1 */ 301 /* Apalis I2C1 */
300 gen1_i2c_scl_pc4 { 302 gen1-i2c-scl-pc4 {
301 nvidia,pins = "gen1_i2c_scl_pc4"; 303 nvidia,pins = "gen1_i2c_scl_pc4";
302 nvidia,function = "i2c1"; 304 nvidia,function = "i2c1";
303 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 305 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -305,7 +307,7 @@
305 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 307 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
306 nvidia,open-drain = <TEGRA_PIN_ENABLE>; 308 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
307 }; 309 };
308 gen1_i2c_sda_pc5 { 310 gen1-i2c-sda-pc5 {
309 nvidia,pins = "gen1_i2c_sda_pc5"; 311 nvidia,pins = "gen1_i2c_sda_pc5";
310 nvidia,function = "i2c1"; 312 nvidia,function = "i2c1";
311 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 313 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -315,7 +317,7 @@
315 }; 317 };
316 318
317 /* Apalis I2C2 (DDC) */ 319 /* Apalis I2C2 (DDC) */
318 gen2_i2c_scl_pt5 { 320 gen2-i2c-scl-pt5 {
319 nvidia,pins = "gen2_i2c_scl_pt5"; 321 nvidia,pins = "gen2_i2c_scl_pt5";
320 nvidia,function = "i2c2"; 322 nvidia,function = "i2c2";
321 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 323 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -323,7 +325,7 @@
323 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 325 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
324 nvidia,open-drain = <TEGRA_PIN_ENABLE>; 326 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
325 }; 327 };
326 gen2_i2c_sda_pt6 { 328 gen2-i2c-sda-pt6 {
327 nvidia,pins = "gen2_i2c_sda_pt6"; 329 nvidia,pins = "gen2_i2c_sda_pt6";
328 nvidia,function = "i2c2"; 330 nvidia,function = "i2c2";
329 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 331 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -333,7 +335,7 @@
333 }; 335 };
334 336
335 /* Apalis I2C3 (CAM) */ 337 /* Apalis I2C3 (CAM) */
336 cam_i2c_scl_pbb1 { 338 cam-i2c-scl-pbb1 {
337 nvidia,pins = "cam_i2c_scl_pbb1"; 339 nvidia,pins = "cam_i2c_scl_pbb1";
338 nvidia,function = "i2c3"; 340 nvidia,function = "i2c3";
339 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 341 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -341,7 +343,7 @@
341 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 343 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
342 nvidia,open-drain = <TEGRA_PIN_ENABLE>; 344 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
343 }; 345 };
344 cam_i2c_sda_pbb2 { 346 cam-i2c-sda-pbb2 {
345 nvidia,pins = "cam_i2c_sda_pbb2"; 347 nvidia,pins = "cam_i2c_sda_pbb2";
346 nvidia,function = "i2c3"; 348 nvidia,function = "i2c3";
347 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 349 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -351,77 +353,77 @@
351 }; 353 };
352 354
353 /* Apalis MMC1 */ 355 /* Apalis MMC1 */
354 sdmmc1_cd_n_pv3 { /* CD# GPIO */ 356 sdmmc1-cd-n-pv3 { /* CD# GPIO */
355 nvidia,pins = "sdmmc1_wp_n_pv3"; 357 nvidia,pins = "sdmmc1_wp_n_pv3";
356 nvidia,function = "sdmmc1"; 358 nvidia,function = "sdmmc1";
357 nvidia,pull = <TEGRA_PIN_PULL_UP>; 359 nvidia,pull = <TEGRA_PIN_PULL_UP>;
358 nvidia,tristate = <TEGRA_PIN_ENABLE>; 360 nvidia,tristate = <TEGRA_PIN_ENABLE>;
359 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 361 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
360 }; 362 };
361 clk2_out_pw5 { /* D5 GPIO */ 363 clk2-out-pw5 { /* D5 GPIO */
362 nvidia,pins = "clk2_out_pw5"; 364 nvidia,pins = "clk2_out_pw5";
363 nvidia,function = "rsvd2"; 365 nvidia,function = "rsvd2";
364 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 366 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
365 nvidia,tristate = <TEGRA_PIN_DISABLE>; 367 nvidia,tristate = <TEGRA_PIN_DISABLE>;
366 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 368 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
367 }; 369 };
368 sdmmc1_dat3_py4 { 370 sdmmc1-dat3-py4 {
369 nvidia,pins = "sdmmc1_dat3_py4"; 371 nvidia,pins = "sdmmc1_dat3_py4";
370 nvidia,function = "sdmmc1"; 372 nvidia,function = "sdmmc1";
371 nvidia,pull = <TEGRA_PIN_PULL_UP>; 373 nvidia,pull = <TEGRA_PIN_PULL_UP>;
372 nvidia,tristate = <TEGRA_PIN_DISABLE>; 374 nvidia,tristate = <TEGRA_PIN_DISABLE>;
373 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 375 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
374 }; 376 };
375 sdmmc1_dat2_py5 { 377 sdmmc1-dat2-py5 {
376 nvidia,pins = "sdmmc1_dat2_py5"; 378 nvidia,pins = "sdmmc1_dat2_py5";
377 nvidia,function = "sdmmc1"; 379 nvidia,function = "sdmmc1";
378 nvidia,pull = <TEGRA_PIN_PULL_UP>; 380 nvidia,pull = <TEGRA_PIN_PULL_UP>;
379 nvidia,tristate = <TEGRA_PIN_DISABLE>; 381 nvidia,tristate = <TEGRA_PIN_DISABLE>;
380 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 382 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
381 }; 383 };
382 sdmmc1_dat1_py6 { 384 sdmmc1-dat1-py6 {
383 nvidia,pins = "sdmmc1_dat1_py6"; 385 nvidia,pins = "sdmmc1_dat1_py6";
384 nvidia,function = "sdmmc1"; 386 nvidia,function = "sdmmc1";
385 nvidia,pull = <TEGRA_PIN_PULL_UP>; 387 nvidia,pull = <TEGRA_PIN_PULL_UP>;
386 nvidia,tristate = <TEGRA_PIN_DISABLE>; 388 nvidia,tristate = <TEGRA_PIN_DISABLE>;
387 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 389 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
388 }; 390 };
389 sdmmc1_dat0_py7 { 391 sdmmc1-dat0-py7 {
390 nvidia,pins = "sdmmc1_dat0_py7"; 392 nvidia,pins = "sdmmc1_dat0_py7";
391 nvidia,function = "sdmmc1"; 393 nvidia,function = "sdmmc1";
392 nvidia,pull = <TEGRA_PIN_PULL_UP>; 394 nvidia,pull = <TEGRA_PIN_PULL_UP>;
393 nvidia,tristate = <TEGRA_PIN_DISABLE>; 395 nvidia,tristate = <TEGRA_PIN_DISABLE>;
394 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 396 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
395 }; 397 };
396 sdmmc1_clk_pz0 { 398 sdmmc1-clk-pz0 {
397 nvidia,pins = "sdmmc1_clk_pz0"; 399 nvidia,pins = "sdmmc1_clk_pz0";
398 nvidia,function = "sdmmc1"; 400 nvidia,function = "sdmmc1";
399 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 401 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
400 nvidia,tristate = <TEGRA_PIN_DISABLE>; 402 nvidia,tristate = <TEGRA_PIN_DISABLE>;
401 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 403 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
402 }; 404 };
403 sdmmc1_cmd_pz1 { 405 sdmmc1-cmd-pz1 {
404 nvidia,pins = "sdmmc1_cmd_pz1"; 406 nvidia,pins = "sdmmc1_cmd_pz1";
405 nvidia,function = "sdmmc1"; 407 nvidia,function = "sdmmc1";
406 nvidia,pull = <TEGRA_PIN_PULL_UP>; 408 nvidia,pull = <TEGRA_PIN_PULL_UP>;
407 nvidia,tristate = <TEGRA_PIN_DISABLE>; 409 nvidia,tristate = <TEGRA_PIN_DISABLE>;
408 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 410 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
409 }; 411 };
410 clk2_req_pcc5 { /* D4 GPIO */ 412 clk2-req-pcc5 { /* D4 GPIO */
411 nvidia,pins = "clk2_req_pcc5"; 413 nvidia,pins = "clk2_req_pcc5";
412 nvidia,function = "rsvd2"; 414 nvidia,function = "rsvd2";
413 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 415 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
414 nvidia,tristate = <TEGRA_PIN_DISABLE>; 416 nvidia,tristate = <TEGRA_PIN_DISABLE>;
415 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 417 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
416 }; 418 };
417 sdmmc3_clk_lb_in_pee5 { /* D6 GPIO */ 419 sdmmc3-clk-lb-in-pee5 { /* D6 GPIO */
418 nvidia,pins = "sdmmc3_clk_lb_in_pee5"; 420 nvidia,pins = "sdmmc3_clk_lb_in_pee5";
419 nvidia,function = "rsvd2"; 421 nvidia,function = "rsvd2";
420 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 422 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
421 nvidia,tristate = <TEGRA_PIN_DISABLE>; 423 nvidia,tristate = <TEGRA_PIN_DISABLE>;
422 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 424 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
423 }; 425 };
424 usb_vbus_en2_pff1 { /* D7 GPIO */ 426 usb-vbus-en2-pff1 { /* D7 GPIO */
425 nvidia,pins = "usb_vbus_en2_pff1"; 427 nvidia,pins = "usb_vbus_en2_pff1";
426 nvidia,function = "rsvd2"; 428 nvidia,function = "rsvd2";
427 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 429 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -461,7 +463,7 @@
461 }; 463 };
462 464
463 /* Apalis SATA1_ACT# */ 465 /* Apalis SATA1_ACT# */
464 dap1_dout_pn2 { 466 dap1-dout-pn2 {
465 nvidia,pins = "dap1_dout_pn2"; 467 nvidia,pins = "dap1_dout_pn2";
466 nvidia,function = "gmi"; 468 nvidia,function = "gmi";
467 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 469 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -470,49 +472,49 @@
470 }; 472 };
471 473
472 /* Apalis SD1 */ 474 /* Apalis SD1 */
473 sdmmc3_clk_pa6 { 475 sdmmc3-clk-pa6 {
474 nvidia,pins = "sdmmc3_clk_pa6"; 476 nvidia,pins = "sdmmc3_clk_pa6";
475 nvidia,function = "sdmmc3"; 477 nvidia,function = "sdmmc3";
476 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 478 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
477 nvidia,tristate = <TEGRA_PIN_DISABLE>; 479 nvidia,tristate = <TEGRA_PIN_DISABLE>;
478 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 480 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
479 }; 481 };
480 sdmmc3_cmd_pa7 { 482 sdmmc3-cmd-pa7 {
481 nvidia,pins = "sdmmc3_cmd_pa7"; 483 nvidia,pins = "sdmmc3_cmd_pa7";
482 nvidia,function = "sdmmc3"; 484 nvidia,function = "sdmmc3";
483 nvidia,pull = <TEGRA_PIN_PULL_UP>; 485 nvidia,pull = <TEGRA_PIN_PULL_UP>;
484 nvidia,tristate = <TEGRA_PIN_DISABLE>; 486 nvidia,tristate = <TEGRA_PIN_DISABLE>;
485 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 487 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
486 }; 488 };
487 sdmmc3_dat3_pb4 { 489 sdmmc3-dat3-pb4 {
488 nvidia,pins = "sdmmc3_dat3_pb4"; 490 nvidia,pins = "sdmmc3_dat3_pb4";
489 nvidia,function = "sdmmc3"; 491 nvidia,function = "sdmmc3";
490 nvidia,pull = <TEGRA_PIN_PULL_UP>; 492 nvidia,pull = <TEGRA_PIN_PULL_UP>;
491 nvidia,tristate = <TEGRA_PIN_DISABLE>; 493 nvidia,tristate = <TEGRA_PIN_DISABLE>;
492 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 494 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
493 }; 495 };
494 sdmmc3_dat2_pb5 { 496 sdmmc3-dat2-pb5 {
495 nvidia,pins = "sdmmc3_dat2_pb5"; 497 nvidia,pins = "sdmmc3_dat2_pb5";
496 nvidia,function = "sdmmc3"; 498 nvidia,function = "sdmmc3";
497 nvidia,pull = <TEGRA_PIN_PULL_UP>; 499 nvidia,pull = <TEGRA_PIN_PULL_UP>;
498 nvidia,tristate = <TEGRA_PIN_DISABLE>; 500 nvidia,tristate = <TEGRA_PIN_DISABLE>;
499 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 501 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
500 }; 502 };
501 sdmmc3_dat1_pb6 { 503 sdmmc3-dat1-pb6 {
502 nvidia,pins = "sdmmc3_dat1_pb6"; 504 nvidia,pins = "sdmmc3_dat1_pb6";
503 nvidia,function = "sdmmc3"; 505 nvidia,function = "sdmmc3";
504 nvidia,pull = <TEGRA_PIN_PULL_UP>; 506 nvidia,pull = <TEGRA_PIN_PULL_UP>;
505 nvidia,tristate = <TEGRA_PIN_DISABLE>; 507 nvidia,tristate = <TEGRA_PIN_DISABLE>;
506 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 508 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
507 }; 509 };
508 sdmmc3_dat0_pb7 { 510 sdmmc3-dat0-pb7 {
509 nvidia,pins = "sdmmc3_dat0_pb7"; 511 nvidia,pins = "sdmmc3_dat0_pb7";
510 nvidia,function = "sdmmc3"; 512 nvidia,function = "sdmmc3";
511 nvidia,pull = <TEGRA_PIN_PULL_UP>; 513 nvidia,pull = <TEGRA_PIN_PULL_UP>;
512 nvidia,tristate = <TEGRA_PIN_DISABLE>; 514 nvidia,tristate = <TEGRA_PIN_DISABLE>;
513 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 515 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
514 }; 516 };
515 sdmmc3_cd_n_pv2 { /* CD# GPIO */ 517 sdmmc3-cd-n-pv2 { /* CD# GPIO */
516 nvidia,pins = "sdmmc3_cd_n_pv2"; 518 nvidia,pins = "sdmmc3_cd_n_pv2";
517 nvidia,function = "rsvd3"; 519 nvidia,function = "rsvd3";
518 nvidia,pull = <TEGRA_PIN_PULL_UP>; 520 nvidia,pull = <TEGRA_PIN_PULL_UP>;
@@ -521,14 +523,14 @@
521 }; 523 };
522 524
523 /* Apalis SPDIF */ 525 /* Apalis SPDIF */
524 spdif_out_pk5 { 526 spdif-out-pk5 {
525 nvidia,pins = "spdif_out_pk5"; 527 nvidia,pins = "spdif_out_pk5";
526 nvidia,function = "spdif"; 528 nvidia,function = "spdif";
527 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 529 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
528 nvidia,tristate = <TEGRA_PIN_DISABLE>; 530 nvidia,tristate = <TEGRA_PIN_DISABLE>;
529 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 531 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
530 }; 532 };
531 spdif_in_pk6 { 533 spdif-in-pk6 {
532 nvidia,pins = "spdif_in_pk6"; 534 nvidia,pins = "spdif_in_pk6";
533 nvidia,function = "spdif"; 535 nvidia,function = "spdif";
534 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 536 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -537,28 +539,28 @@
537 }; 539 };
538 540
539 /* Apalis SPI1 */ 541 /* Apalis SPI1 */
540 ulpi_clk_py0 { 542 ulpi-clk-py0 {
541 nvidia,pins = "ulpi_clk_py0"; 543 nvidia,pins = "ulpi_clk_py0";
542 nvidia,function = "spi1"; 544 nvidia,function = "spi1";
543 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 545 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
544 nvidia,tristate = <TEGRA_PIN_DISABLE>; 546 nvidia,tristate = <TEGRA_PIN_DISABLE>;
545 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 547 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
546 }; 548 };
547 ulpi_dir_py1 { 549 ulpi-dir-py1 {
548 nvidia,pins = "ulpi_dir_py1"; 550 nvidia,pins = "ulpi_dir_py1";
549 nvidia,function = "spi1"; 551 nvidia,function = "spi1";
550 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 552 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
551 nvidia,tristate = <TEGRA_PIN_ENABLE>; 553 nvidia,tristate = <TEGRA_PIN_ENABLE>;
552 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 554 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
553 }; 555 };
554 ulpi_nxt_py2 { 556 ulpi-nxt-py2 {
555 nvidia,pins = "ulpi_nxt_py2"; 557 nvidia,pins = "ulpi_nxt_py2";
556 nvidia,function = "spi1"; 558 nvidia,function = "spi1";
557 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 559 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
558 nvidia,tristate = <TEGRA_PIN_DISABLE>; 560 nvidia,tristate = <TEGRA_PIN_DISABLE>;
559 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 561 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
560 }; 562 };
561 ulpi_stp_py3 { 563 ulpi-stp-py3 {
562 nvidia,pins = "ulpi_stp_py3"; 564 nvidia,pins = "ulpi_stp_py3";
563 nvidia,function = "spi1"; 565 nvidia,function = "spi1";
564 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 566 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -611,42 +613,42 @@
611 nvidia,tristate = <TEGRA_PIN_ENABLE>; 613 nvidia,tristate = <TEGRA_PIN_ENABLE>;
612 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 614 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
613 }; 615 };
614 uart1_txd_pu0 { 616 uart1-txd-pu0 {
615 nvidia,pins = "pu0"; 617 nvidia,pins = "pu0";
616 nvidia,function = "uarta"; 618 nvidia,function = "uarta";
617 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 619 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
618 nvidia,tristate = <TEGRA_PIN_DISABLE>; 620 nvidia,tristate = <TEGRA_PIN_DISABLE>;
619 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 621 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
620 }; 622 };
621 uart1_rxd_pu1 { 623 uart1-rxd-pu1 {
622 nvidia,pins = "pu1"; 624 nvidia,pins = "pu1";
623 nvidia,function = "uarta"; 625 nvidia,function = "uarta";
624 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 626 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
625 nvidia,tristate = <TEGRA_PIN_ENABLE>; 627 nvidia,tristate = <TEGRA_PIN_ENABLE>;
626 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 628 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
627 }; 629 };
628 uart1_cts_n_pu2 { 630 uart1-cts-n-pu2 {
629 nvidia,pins = "pu2"; 631 nvidia,pins = "pu2";
630 nvidia,function = "uarta"; 632 nvidia,function = "uarta";
631 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 633 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
632 nvidia,tristate = <TEGRA_PIN_ENABLE>; 634 nvidia,tristate = <TEGRA_PIN_ENABLE>;
633 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 635 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
634 }; 636 };
635 uart1_rts_n_pu3 { 637 uart1-rts-n-pu3 {
636 nvidia,pins = "pu3"; 638 nvidia,pins = "pu3";
637 nvidia,function = "uarta"; 639 nvidia,function = "uarta";
638 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 640 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
639 nvidia,tristate = <TEGRA_PIN_DISABLE>; 641 nvidia,tristate = <TEGRA_PIN_DISABLE>;
640 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 642 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
641 }; 643 };
642 uart3_cts_n_pa1 { /* DSR GPIO */ 644 uart3-cts-n-pa1 { /* DSR GPIO */
643 nvidia,pins = "uart3_cts_n_pa1"; 645 nvidia,pins = "uart3_cts_n_pa1";
644 nvidia,function = "gmi"; 646 nvidia,function = "gmi";
645 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 647 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
646 nvidia,tristate = <TEGRA_PIN_ENABLE>; 648 nvidia,tristate = <TEGRA_PIN_ENABLE>;
647 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 649 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
648 }; 650 };
649 uart3_rts_n_pc0 { /* DTR GPIO */ 651 uart3-rts-n-pc0 { /* DTR GPIO */
650 nvidia,pins = "uart3_rts_n_pc0"; 652 nvidia,pins = "uart3_rts_n_pc0";
651 nvidia,function = "gmi"; 653 nvidia,function = "gmi";
652 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 654 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -655,28 +657,28 @@
655 }; 657 };
656 658
657 /* Apalis UART2 */ 659 /* Apalis UART2 */
658 uart2_txd_pc2 { 660 uart2-txd-pc2 {
659 nvidia,pins = "uart2_txd_pc2"; 661 nvidia,pins = "uart2_txd_pc2";
660 nvidia,function = "irda"; 662 nvidia,function = "irda";
661 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 663 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
662 nvidia,tristate = <TEGRA_PIN_DISABLE>; 664 nvidia,tristate = <TEGRA_PIN_DISABLE>;
663 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 665 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
664 }; 666 };
665 uart2_rxd_pc3 { 667 uart2-rxd-pc3 {
666 nvidia,pins = "uart2_rxd_pc3"; 668 nvidia,pins = "uart2_rxd_pc3";
667 nvidia,function = "irda"; 669 nvidia,function = "irda";
668 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 670 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
669 nvidia,tristate = <TEGRA_PIN_ENABLE>; 671 nvidia,tristate = <TEGRA_PIN_ENABLE>;
670 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 672 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
671 }; 673 };
672 uart2_cts_n_pj5 { 674 uart2-cts-n-pj5 {
673 nvidia,pins = "uart2_cts_n_pj5"; 675 nvidia,pins = "uart2_cts_n_pj5";
674 nvidia,function = "uartb"; 676 nvidia,function = "uartb";
675 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 677 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
676 nvidia,tristate = <TEGRA_PIN_ENABLE>; 678 nvidia,tristate = <TEGRA_PIN_ENABLE>;
677 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 679 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
678 }; 680 };
679 uart2_rts_n_pj6 { 681 uart2-rts-n-pj6 {
680 nvidia,pins = "uart2_rts_n_pj6"; 682 nvidia,pins = "uart2_rts_n_pj6";
681 nvidia,function = "uartb"; 683 nvidia,function = "uartb";
682 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 684 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -685,14 +687,14 @@
685 }; 687 };
686 688
687 /* Apalis UART3 */ 689 /* Apalis UART3 */
688 uart3_txd_pw6 { 690 uart3-txd-pw6 {
689 nvidia,pins = "uart3_txd_pw6"; 691 nvidia,pins = "uart3_txd_pw6";
690 nvidia,function = "uartc"; 692 nvidia,function = "uartc";
691 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 693 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
692 nvidia,tristate = <TEGRA_PIN_DISABLE>; 694 nvidia,tristate = <TEGRA_PIN_DISABLE>;
693 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 695 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
694 }; 696 };
695 uart3_rxd_pw7 { 697 uart3-rxd-pw7 {
696 nvidia,pins = "uart3_rxd_pw7"; 698 nvidia,pins = "uart3_rxd_pw7";
697 nvidia,function = "uartc"; 699 nvidia,function = "uartc";
698 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 700 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -701,14 +703,14 @@
701 }; 703 };
702 704
703 /* Apalis UART4 */ 705 /* Apalis UART4 */
704 uart4_rxd_pb0 { 706 uart4-rxd-pb0 {
705 nvidia,pins = "pb0"; 707 nvidia,pins = "pb0";
706 nvidia,function = "uartd"; 708 nvidia,function = "uartd";
707 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 709 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
708 nvidia,tristate = <TEGRA_PIN_ENABLE>; 710 nvidia,tristate = <TEGRA_PIN_ENABLE>;
709 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 711 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
710 }; 712 };
711 uart4_txd_pj7 { 713 uart4-txd-pj7 {
712 nvidia,pins = "pj7"; 714 nvidia,pins = "pj7";
713 nvidia,function = "uartd"; 715 nvidia,function = "uartd";
714 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 716 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -717,7 +719,7 @@
717 }; 719 };
718 720
719 /* Apalis USBH_EN */ 721 /* Apalis USBH_EN */
720 usb_vbus_en1_pn5 { 722 usb-vbus-en1-pn5 {
721 nvidia,pins = "usb_vbus_en1_pn5"; 723 nvidia,pins = "usb_vbus_en1_pn5";
722 nvidia,function = "rsvd2"; 724 nvidia,function = "rsvd2";
723 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 725 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -736,7 +738,7 @@
736 }; 738 };
737 739
738 /* Apalis USBO1_EN */ 740 /* Apalis USBO1_EN */
739 usb_vbus_en0_pn4 { 741 usb-vbus-en0-pn4 {
740 nvidia,pins = "usb_vbus_en0_pn4"; 742 nvidia,pins = "usb_vbus_en0_pn4";
741 nvidia,function = "rsvd2"; 743 nvidia,function = "rsvd2";
742 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 744 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -755,7 +757,7 @@
755 }; 757 };
756 758
757 /* Apalis WAKE1_MICO */ 759 /* Apalis WAKE1_MICO */
758 pex_wake_n_pdd3 { 760 pex-wake-n-pdd3 {
759 nvidia,pins = "pex_wake_n_pdd3"; 761 nvidia,pins = "pex_wake_n_pdd3";
760 nvidia,function = "rsvd2"; 762 nvidia,function = "rsvd2";
761 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 763 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -764,7 +766,7 @@
764 }; 766 };
765 767
766 /* CORE_PWR_REQ */ 768 /* CORE_PWR_REQ */
767 core_pwr_req { 769 core-pwr-req {
768 nvidia,pins = "core_pwr_req"; 770 nvidia,pins = "core_pwr_req";
769 nvidia,function = "pwron"; 771 nvidia,function = "pwron";
770 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 772 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -773,7 +775,7 @@
773 }; 775 };
774 776
775 /* CPU_PWR_REQ */ 777 /* CPU_PWR_REQ */
776 cpu_pwr_req { 778 cpu-pwr-req {
777 nvidia,pins = "cpu_pwr_req"; 779 nvidia,pins = "cpu_pwr_req";
778 nvidia,function = "cpu"; 780 nvidia,function = "cpu";
779 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 781 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -782,14 +784,14 @@
782 }; 784 };
783 785
784 /* DVFS */ 786 /* DVFS */
785 dvfs_pwm_px0 { 787 dvfs-pwm-px0 {
786 nvidia,pins = "dvfs_pwm_px0"; 788 nvidia,pins = "dvfs_pwm_px0";
787 nvidia,function = "cldvfs"; 789 nvidia,function = "cldvfs";
788 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 790 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
789 nvidia,tristate = <TEGRA_PIN_DISABLE>; 791 nvidia,tristate = <TEGRA_PIN_DISABLE>;
790 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 792 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
791 }; 793 };
792 dvfs_clk_px2 { 794 dvfs-clk-px2 {
793 nvidia,pins = "dvfs_clk_px2"; 795 nvidia,pins = "dvfs_clk_px2";
794 nvidia,function = "cldvfs"; 796 nvidia,function = "cldvfs";
795 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 797 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -798,70 +800,70 @@
798 }; 800 };
799 801
800 /* eMMC */ 802 /* eMMC */
801 sdmmc4_dat0_paa0 { 803 sdmmc4-dat0-paa0 {
802 nvidia,pins = "sdmmc4_dat0_paa0"; 804 nvidia,pins = "sdmmc4_dat0_paa0";
803 nvidia,function = "sdmmc4"; 805 nvidia,function = "sdmmc4";
804 nvidia,pull = <TEGRA_PIN_PULL_UP>; 806 nvidia,pull = <TEGRA_PIN_PULL_UP>;
805 nvidia,tristate = <TEGRA_PIN_DISABLE>; 807 nvidia,tristate = <TEGRA_PIN_DISABLE>;
806 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 808 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
807 }; 809 };
808 sdmmc4_dat1_paa1 { 810 sdmmc4-dat1-paa1 {
809 nvidia,pins = "sdmmc4_dat1_paa1"; 811 nvidia,pins = "sdmmc4_dat1_paa1";
810 nvidia,function = "sdmmc4"; 812 nvidia,function = "sdmmc4";
811 nvidia,pull = <TEGRA_PIN_PULL_UP>; 813 nvidia,pull = <TEGRA_PIN_PULL_UP>;
812 nvidia,tristate = <TEGRA_PIN_DISABLE>; 814 nvidia,tristate = <TEGRA_PIN_DISABLE>;
813 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 815 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
814 }; 816 };
815 sdmmc4_dat2_paa2 { 817 sdmmc4-dat2-paa2 {
816 nvidia,pins = "sdmmc4_dat2_paa2"; 818 nvidia,pins = "sdmmc4_dat2_paa2";
817 nvidia,function = "sdmmc4"; 819 nvidia,function = "sdmmc4";
818 nvidia,pull = <TEGRA_PIN_PULL_UP>; 820 nvidia,pull = <TEGRA_PIN_PULL_UP>;
819 nvidia,tristate = <TEGRA_PIN_DISABLE>; 821 nvidia,tristate = <TEGRA_PIN_DISABLE>;
820 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 822 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
821 }; 823 };
822 sdmmc4_dat3_paa3 { 824 sdmmc4-dat3-paa3 {
823 nvidia,pins = "sdmmc4_dat3_paa3"; 825 nvidia,pins = "sdmmc4_dat3_paa3";
824 nvidia,function = "sdmmc4"; 826 nvidia,function = "sdmmc4";
825 nvidia,pull = <TEGRA_PIN_PULL_UP>; 827 nvidia,pull = <TEGRA_PIN_PULL_UP>;
826 nvidia,tristate = <TEGRA_PIN_DISABLE>; 828 nvidia,tristate = <TEGRA_PIN_DISABLE>;
827 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 829 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
828 }; 830 };
829 sdmmc4_dat4_paa4 { 831 sdmmc4-dat4-paa4 {
830 nvidia,pins = "sdmmc4_dat4_paa4"; 832 nvidia,pins = "sdmmc4_dat4_paa4";
831 nvidia,function = "sdmmc4"; 833 nvidia,function = "sdmmc4";
832 nvidia,pull = <TEGRA_PIN_PULL_UP>; 834 nvidia,pull = <TEGRA_PIN_PULL_UP>;
833 nvidia,tristate = <TEGRA_PIN_DISABLE>; 835 nvidia,tristate = <TEGRA_PIN_DISABLE>;
834 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 836 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
835 }; 837 };
836 sdmmc4_dat5_paa5 { 838 sdmmc4-dat5-paa5 {
837 nvidia,pins = "sdmmc4_dat5_paa5"; 839 nvidia,pins = "sdmmc4_dat5_paa5";
838 nvidia,function = "sdmmc4"; 840 nvidia,function = "sdmmc4";
839 nvidia,pull = <TEGRA_PIN_PULL_UP>; 841 nvidia,pull = <TEGRA_PIN_PULL_UP>;
840 nvidia,tristate = <TEGRA_PIN_DISABLE>; 842 nvidia,tristate = <TEGRA_PIN_DISABLE>;
841 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 843 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
842 }; 844 };
843 sdmmc4_dat6_paa6 { 845 sdmmc4-dat6-paa6 {
844 nvidia,pins = "sdmmc4_dat6_paa6"; 846 nvidia,pins = "sdmmc4_dat6_paa6";
845 nvidia,function = "sdmmc4"; 847 nvidia,function = "sdmmc4";
846 nvidia,pull = <TEGRA_PIN_PULL_UP>; 848 nvidia,pull = <TEGRA_PIN_PULL_UP>;
847 nvidia,tristate = <TEGRA_PIN_DISABLE>; 849 nvidia,tristate = <TEGRA_PIN_DISABLE>;
848 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 850 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
849 }; 851 };
850 sdmmc4_dat7_paa7 { 852 sdmmc4-dat7-paa7 {
851 nvidia,pins = "sdmmc4_dat7_paa7"; 853 nvidia,pins = "sdmmc4_dat7_paa7";
852 nvidia,function = "sdmmc4"; 854 nvidia,function = "sdmmc4";
853 nvidia,pull = <TEGRA_PIN_PULL_UP>; 855 nvidia,pull = <TEGRA_PIN_PULL_UP>;
854 nvidia,tristate = <TEGRA_PIN_DISABLE>; 856 nvidia,tristate = <TEGRA_PIN_DISABLE>;
855 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 857 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
856 }; 858 };
857 sdmmc4_clk_pcc4 { 859 sdmmc4-clk-pcc4 {
858 nvidia,pins = "sdmmc4_clk_pcc4"; 860 nvidia,pins = "sdmmc4_clk_pcc4";
859 nvidia,function = "sdmmc4"; 861 nvidia,function = "sdmmc4";
860 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 862 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
861 nvidia,tristate = <TEGRA_PIN_DISABLE>; 863 nvidia,tristate = <TEGRA_PIN_DISABLE>;
862 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 864 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
863 }; 865 };
864 sdmmc4_cmd_pt7 { 866 sdmmc4-cmd-pt7 {
865 nvidia,pins = "sdmmc4_cmd_pt7"; 867 nvidia,pins = "sdmmc4_cmd_pt7";
866 nvidia,function = "sdmmc4"; 868 nvidia,function = "sdmmc4";
867 nvidia,pull = <TEGRA_PIN_PULL_UP>; 869 nvidia,pull = <TEGRA_PIN_PULL_UP>;
@@ -870,7 +872,7 @@
870 }; 872 };
871 873
872 /* JTAG_RTCK */ 874 /* JTAG_RTCK */
873 jtag_rtck { 875 jtag-rtck {
874 nvidia,pins = "jtag_rtck"; 876 nvidia,pins = "jtag_rtck";
875 nvidia,function = "rtck"; 877 nvidia,function = "rtck";
876 nvidia,pull = <TEGRA_PIN_PULL_UP>; 878 nvidia,pull = <TEGRA_PIN_PULL_UP>;
@@ -879,7 +881,7 @@
879 }; 881 };
880 882
881 /* LAN_DEV_OFF# */ 883 /* LAN_DEV_OFF# */
882 ulpi_data5_po6 { 884 ulpi-data5-po6 {
883 nvidia,pins = "ulpi_data5_po6"; 885 nvidia,pins = "ulpi_data5_po6";
884 nvidia,function = "ulpi"; 886 nvidia,function = "ulpi";
885 nvidia,pull = <TEGRA_PIN_PULL_UP>; 887 nvidia,pull = <TEGRA_PIN_PULL_UP>;
@@ -888,7 +890,7 @@
888 }; 890 };
889 891
890 /* LAN_RESET# */ 892 /* LAN_RESET# */
891 kb_row10_ps2 { 893 kb-row10-ps2 {
892 nvidia,pins = "kb_row10_ps2"; 894 nvidia,pins = "kb_row10_ps2";
893 nvidia,function = "rsvd2"; 895 nvidia,function = "rsvd2";
894 nvidia,pull = <TEGRA_PIN_PULL_UP>; 896 nvidia,pull = <TEGRA_PIN_PULL_UP>;
@@ -897,7 +899,7 @@
897 }; 899 };
898 900
899 /* LAN_WAKE# */ 901 /* LAN_WAKE# */
900 ulpi_data4_po5 { 902 ulpi-data4-po5 {
901 nvidia,pins = "ulpi_data4_po5"; 903 nvidia,pins = "ulpi_data4_po5";
902 nvidia,function = "ulpi"; 904 nvidia,function = "ulpi";
903 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 905 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -951,35 +953,35 @@
951 }; 953 };
952 954
953 /* MCU SPI */ 955 /* MCU SPI */
954 gpio_x4_aud_px4 { 956 gpio-x4-aud-px4 {
955 nvidia,pins = "gpio_x4_aud_px4"; 957 nvidia,pins = "gpio_x4_aud_px4";
956 nvidia,function = "spi2"; 958 nvidia,function = "spi2";
957 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 959 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
958 nvidia,tristate = <TEGRA_PIN_DISABLE>; 960 nvidia,tristate = <TEGRA_PIN_DISABLE>;
959 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 961 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
960 }; 962 };
961 gpio_x5_aud_px5 { 963 gpio-x5-aud-px5 {
962 nvidia,pins = "gpio_x5_aud_px5"; 964 nvidia,pins = "gpio_x5_aud_px5";
963 nvidia,function = "spi2"; 965 nvidia,function = "spi2";
964 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 966 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
965 nvidia,tristate = <TEGRA_PIN_DISABLE>; 967 nvidia,tristate = <TEGRA_PIN_DISABLE>;
966 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 968 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
967 }; 969 };
968 gpio_x6_aud_px6 { /* MCU_CS */ 970 gpio-x6-aud-px6 { /* MCU_CS */
969 nvidia,pins = "gpio_x6_aud_px6"; 971 nvidia,pins = "gpio_x6_aud_px6";
970 nvidia,function = "spi2"; 972 nvidia,function = "spi2";
971 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 973 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
972 nvidia,tristate = <TEGRA_PIN_DISABLE>; 974 nvidia,tristate = <TEGRA_PIN_DISABLE>;
973 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 975 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
974 }; 976 };
975 gpio_x7_aud_px7 { 977 gpio-x7-aud-px7 {
976 nvidia,pins = "gpio_x7_aud_px7"; 978 nvidia,pins = "gpio_x7_aud_px7";
977 nvidia,function = "spi2"; 979 nvidia,function = "spi2";
978 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 980 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
979 nvidia,tristate = <TEGRA_PIN_ENABLE>; 981 nvidia,tristate = <TEGRA_PIN_ENABLE>;
980 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 982 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
981 }; 983 };
982 gpio_w2_aud_pw2 { /* MCU_CSEZP */ 984 gpio-w2-aud-pw2 { /* MCU_CSEZP */
983 nvidia,pins = "gpio_w2_aud_pw2"; 985 nvidia,pins = "gpio_w2_aud_pw2";
984 nvidia,function = "spi2"; 986 nvidia,function = "spi2";
985 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 987 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -988,7 +990,7 @@
988 }; 990 };
989 991
990 /* PMIC_CLK_32K */ 992 /* PMIC_CLK_32K */
991 clk_32k_in { 993 clk-32k-in {
992 nvidia,pins = "clk_32k_in"; 994 nvidia,pins = "clk_32k_in";
993 nvidia,function = "clk"; 995 nvidia,function = "clk";
994 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 996 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -997,7 +999,7 @@
997 }; 999 };
998 1000
999 /* PMIC_CPU_OC_INT */ 1001 /* PMIC_CPU_OC_INT */
1000 clk_32k_out_pa0 { 1002 clk-32k-out-pa0 {
1001 nvidia,pins = "clk_32k_out_pa0"; 1003 nvidia,pins = "clk_32k_out_pa0";
1002 nvidia,function = "soc"; 1004 nvidia,function = "soc";
1003 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1005 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -1006,7 +1008,7 @@
1006 }; 1008 };
1007 1009
1008 /* PWR_I2C */ 1010 /* PWR_I2C */
1009 pwr_i2c_scl_pz6 { 1011 pwr-i2c-scl-pz6 {
1010 nvidia,pins = "pwr_i2c_scl_pz6"; 1012 nvidia,pins = "pwr_i2c_scl_pz6";
1011 nvidia,function = "i2cpwr"; 1013 nvidia,function = "i2cpwr";
1012 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1014 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -1014,7 +1016,7 @@
1014 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1016 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1015 nvidia,open-drain = <TEGRA_PIN_ENABLE>; 1017 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
1016 }; 1018 };
1017 pwr_i2c_sda_pz7 { 1019 pwr-i2c-sda-pz7 {
1018 nvidia,pins = "pwr_i2c_sda_pz7"; 1020 nvidia,pins = "pwr_i2c_sda_pz7";
1019 nvidia,function = "i2cpwr"; 1021 nvidia,function = "i2cpwr";
1020 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1022 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -1024,7 +1026,7 @@
1024 }; 1026 };
1025 1027
1026 /* PWR_INT_N */ 1028 /* PWR_INT_N */
1027 pwr_int_n { 1029 pwr-int-n {
1028 nvidia,pins = "pwr_int_n"; 1030 nvidia,pins = "pwr_int_n";
1029 nvidia,function = "pmi"; 1031 nvidia,function = "pmi";
1030 nvidia,pull = <TEGRA_PIN_PULL_UP>; 1032 nvidia,pull = <TEGRA_PIN_PULL_UP>;
@@ -1042,7 +1044,7 @@
1042 }; 1044 };
1043 1045
1044 /* RESET_OUT_N */ 1046 /* RESET_OUT_N */
1045 reset_out_n { 1047 reset-out-n {
1046 nvidia,pins = "reset_out_n"; 1048 nvidia,pins = "reset_out_n";
1047 nvidia,function = "reset_out_n"; 1049 nvidia,function = "reset_out_n";
1048 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1050 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -1051,14 +1053,14 @@
1051 }; 1053 };
1052 1054
1053 /* SHIFT_CTRL_DIR_IN */ 1055 /* SHIFT_CTRL_DIR_IN */
1054 kb_row0_pr0 { 1056 kb-row0-pr0 {
1055 nvidia,pins = "kb_row0_pr0"; 1057 nvidia,pins = "kb_row0_pr0";
1056 nvidia,function = "rsvd2"; 1058 nvidia,function = "rsvd2";
1057 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1059 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1058 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1060 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1059 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1061 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1060 }; 1062 };
1061 kb_row1_pr1 { 1063 kb-row1-pr1 {
1062 nvidia,pins = "kb_row1_pr1"; 1064 nvidia,pins = "kb_row1_pr1";
1063 nvidia,function = "rsvd2"; 1065 nvidia,function = "rsvd2";
1064 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1066 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
@@ -1067,7 +1069,7 @@
1067 }; 1069 };
1068 1070
1069 /* Configure level-shifter as output for HDA */ 1071 /* Configure level-shifter as output for HDA */
1070 kb_row11_ps3 { 1072 kb-row11-ps3 {
1071 nvidia,pins = "kb_row11_ps3"; 1073 nvidia,pins = "kb_row11_ps3";
1072 nvidia,function = "rsvd2"; 1074 nvidia,function = "rsvd2";
1073 nvidia,pull = <TEGRA_PIN_PULL_UP>; 1075 nvidia,pull = <TEGRA_PIN_PULL_UP>;
@@ -1076,21 +1078,21 @@
1076 }; 1078 };
1077 1079
1078 /* SHIFT_CTRL_DIR_OUT */ 1080 /* SHIFT_CTRL_DIR_OUT */
1079 kb_col5_pq5 { 1081 kb-col5-pq5 {
1080 nvidia,pins = "kb_col5_pq5"; 1082 nvidia,pins = "kb_col5_pq5";
1081 nvidia,function = "rsvd2"; 1083 nvidia,function = "rsvd2";
1082 nvidia,pull = <TEGRA_PIN_PULL_UP>; 1084 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1083 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1085 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1084 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1086 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1085 }; 1087 };
1086 kb_col6_pq6 { 1088 kb-col6-pq6 {
1087 nvidia,pins = "kb_col6_pq6"; 1089 nvidia,pins = "kb_col6_pq6";
1088 nvidia,function = "rsvd2"; 1090 nvidia,function = "rsvd2";
1089 nvidia,pull = <TEGRA_PIN_PULL_UP>; 1091 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1090 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1092 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1091 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1093 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1092 }; 1094 };
1093 kb_col7_pq7 { 1095 kb-col7-pq7 {
1094 nvidia,pins = "kb_col7_pq7"; 1096 nvidia,pins = "kb_col7_pq7";
1095 nvidia,function = "rsvd2"; 1097 nvidia,function = "rsvd2";
1096 nvidia,pull = <TEGRA_PIN_PULL_UP>; 1098 nvidia,pull = <TEGRA_PIN_PULL_UP>;
@@ -1099,35 +1101,35 @@
1099 }; 1101 };
1100 1102
1101 /* SHIFT_CTRL_OE */ 1103 /* SHIFT_CTRL_OE */
1102 kb_col0_pq0 { 1104 kb-col0-pq0 {
1103 nvidia,pins = "kb_col0_pq0"; 1105 nvidia,pins = "kb_col0_pq0";
1104 nvidia,function = "rsvd2"; 1106 nvidia,function = "rsvd2";
1105 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1107 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1106 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1108 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1107 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1109 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1108 }; 1110 };
1109 kb_col1_pq1 { 1111 kb-col1-pq1 {
1110 nvidia,pins = "kb_col1_pq1"; 1112 nvidia,pins = "kb_col1_pq1";
1111 nvidia,function = "rsvd2"; 1113 nvidia,function = "rsvd2";
1112 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1114 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1113 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1115 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1114 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1116 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1115 }; 1117 };
1116 kb_col2_pq2 { 1118 kb-col2-pq2 {
1117 nvidia,pins = "kb_col2_pq2"; 1119 nvidia,pins = "kb_col2_pq2";
1118 nvidia,function = "rsvd2"; 1120 nvidia,function = "rsvd2";
1119 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1121 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1120 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1122 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1121 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1123 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1122 }; 1124 };
1123 kb_col4_pq4 { 1125 kb-col4-pq4 {
1124 nvidia,pins = "kb_col4_pq4"; 1126 nvidia,pins = "kb_col4_pq4";
1125 nvidia,function = "kbc"; 1127 nvidia,function = "kbc";
1126 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1128 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1127 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1129 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1128 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1130 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1129 }; 1131 };
1130 kb_row2_pr2 { 1132 kb-row2-pr2 {
1131 nvidia,pins = "kb_row2_pr2"; 1133 nvidia,pins = "kb_row2_pr2";
1132 nvidia,function = "rsvd2"; 1134 nvidia,function = "rsvd2";
1133 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1135 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
@@ -1145,7 +1147,7 @@
1145 }; 1147 };
1146 1148
1147 /* TOUCH_INT */ 1149 /* TOUCH_INT */
1148 gpio_w3_aud_pw3 { 1150 gpio-w3-aud-pw3 {
1149 nvidia,pins = "gpio_w3_aud_pw3"; 1151 nvidia,pins = "gpio_w3_aud_pw3";
1150 nvidia,function = "spi6"; 1152 nvidia,function = "spi6";
1151 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1153 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -1286,189 +1288,189 @@
1286 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1288 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1287 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1289 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1288 }; 1290 };
1289 dap1_fs_pn0 { /* NC */ 1291 dap1-fs-pn0 { /* NC */
1290 nvidia,pins = "dap1_fs_pn0"; 1292 nvidia,pins = "dap1_fs_pn0";
1291 nvidia,function = "rsvd4"; 1293 nvidia,function = "rsvd4";
1292 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1294 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1293 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1295 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1294 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1296 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1295 }; 1297 };
1296 dap1_din_pn1 { /* NC */ 1298 dap1-din-pn1 { /* NC */
1297 nvidia,pins = "dap1_din_pn1"; 1299 nvidia,pins = "dap1_din_pn1";
1298 nvidia,function = "rsvd4"; 1300 nvidia,function = "rsvd4";
1299 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1301 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1300 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1302 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1301 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1303 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1302 }; 1304 };
1303 dap1_sclk_pn3 { /* NC */ 1305 dap1-sclk-pn3 { /* NC */
1304 nvidia,pins = "dap1_sclk_pn3"; 1306 nvidia,pins = "dap1_sclk_pn3";
1305 nvidia,function = "rsvd4"; 1307 nvidia,function = "rsvd4";
1306 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1308 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1307 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1309 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1308 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1310 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1309 }; 1311 };
1310 ulpi_data7_po0 { /* NC */ 1312 ulpi-data7-po0 { /* NC */
1311 nvidia,pins = "ulpi_data7_po0"; 1313 nvidia,pins = "ulpi_data7_po0";
1312 nvidia,function = "ulpi"; 1314 nvidia,function = "ulpi";
1313 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1315 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1314 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1316 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1315 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1317 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1316 }; 1318 };
1317 ulpi_data0_po1 { /* NC */ 1319 ulpi-data0-po1 { /* NC */
1318 nvidia,pins = "ulpi_data0_po1"; 1320 nvidia,pins = "ulpi_data0_po1";
1319 nvidia,function = "ulpi"; 1321 nvidia,function = "ulpi";
1320 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1322 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1321 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1323 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1322 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1324 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1323 }; 1325 };
1324 ulpi_data1_po2 { /* NC */ 1326 ulpi-data1-po2 { /* NC */
1325 nvidia,pins = "ulpi_data1_po2"; 1327 nvidia,pins = "ulpi_data1_po2";
1326 nvidia,function = "ulpi"; 1328 nvidia,function = "ulpi";
1327 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1329 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1328 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1330 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1329 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1331 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1330 }; 1332 };
1331 ulpi_data2_po3 { /* NC */ 1333 ulpi-data2-po3 { /* NC */
1332 nvidia,pins = "ulpi_data2_po3"; 1334 nvidia,pins = "ulpi_data2_po3";
1333 nvidia,function = "ulpi"; 1335 nvidia,function = "ulpi";
1334 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1336 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1335 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1337 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1336 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1338 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1337 }; 1339 };
1338 ulpi_data3_po4 { /* NC */ 1340 ulpi-data3-po4 { /* NC */
1339 nvidia,pins = "ulpi_data3_po4"; 1341 nvidia,pins = "ulpi_data3_po4";
1340 nvidia,function = "ulpi"; 1342 nvidia,function = "ulpi";
1341 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1343 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1342 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1344 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1343 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1345 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1344 }; 1346 };
1345 ulpi_data6_po7 { /* NC */ 1347 ulpi-data6-po7 { /* NC */
1346 nvidia,pins = "ulpi_data6_po7"; 1348 nvidia,pins = "ulpi_data6_po7";
1347 nvidia,function = "ulpi"; 1349 nvidia,function = "ulpi";
1348 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1350 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1349 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1351 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1350 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1352 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1351 }; 1353 };
1352 dap4_fs_pp4 { /* NC */ 1354 dap4-fs-pp4 { /* NC */
1353 nvidia,pins = "dap4_fs_pp4"; 1355 nvidia,pins = "dap4_fs_pp4";
1354 nvidia,function = "rsvd4"; 1356 nvidia,function = "rsvd4";
1355 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1357 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1356 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1358 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1357 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1359 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1358 }; 1360 };
1359 dap4_din_pp5 { /* NC */ 1361 dap4-din-pp5 { /* NC */
1360 nvidia,pins = "dap4_din_pp5"; 1362 nvidia,pins = "dap4_din_pp5";
1361 nvidia,function = "rsvd3"; 1363 nvidia,function = "rsvd3";
1362 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1364 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1363 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1365 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1364 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1366 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1365 }; 1367 };
1366 dap4_dout_pp6 { /* NC */ 1368 dap4-dout-pp6 { /* NC */
1367 nvidia,pins = "dap4_dout_pp6"; 1369 nvidia,pins = "dap4_dout_pp6";
1368 nvidia,function = "rsvd4"; 1370 nvidia,function = "rsvd4";
1369 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1371 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1370 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1372 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1371 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1373 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1372 }; 1374 };
1373 dap4_sclk_pp7 { /* NC */ 1375 dap4-sclk-pp7 { /* NC */
1374 nvidia,pins = "dap4_sclk_pp7"; 1376 nvidia,pins = "dap4_sclk_pp7";
1375 nvidia,function = "rsvd3"; 1377 nvidia,function = "rsvd3";
1376 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1378 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1377 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1379 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1378 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1380 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1379 }; 1381 };
1380 kb_col3_pq3 { /* NC */ 1382 kb-col3-pq3 { /* NC */
1381 nvidia,pins = "kb_col3_pq3"; 1383 nvidia,pins = "kb_col3_pq3";
1382 nvidia,function = "kbc"; 1384 nvidia,function = "kbc";
1383 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1385 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1384 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1386 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1385 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1387 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1386 }; 1388 };
1387 kb_row3_pr3 { /* NC */ 1389 kb-row3-pr3 { /* NC */
1388 nvidia,pins = "kb_row3_pr3"; 1390 nvidia,pins = "kb_row3_pr3";
1389 nvidia,function = "kbc"; 1391 nvidia,function = "kbc";
1390 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1392 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1391 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1393 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1392 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1394 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1393 }; 1395 };
1394 kb_row4_pr4 { /* NC */ 1396 kb-row4-pr4 { /* NC */
1395 nvidia,pins = "kb_row4_pr4"; 1397 nvidia,pins = "kb_row4_pr4";
1396 nvidia,function = "rsvd3"; 1398 nvidia,function = "rsvd3";
1397 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1399 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1398 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1400 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1399 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1401 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1400 }; 1402 };
1401 kb_row5_pr5 { /* NC */ 1403 kb-row5-pr5 { /* NC */
1402 nvidia,pins = "kb_row5_pr5"; 1404 nvidia,pins = "kb_row5_pr5";
1403 nvidia,function = "rsvd3"; 1405 nvidia,function = "rsvd3";
1404 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1406 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1405 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1407 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1406 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1408 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1407 }; 1409 };
1408 kb_row6_pr6 { /* NC */ 1410 kb-row6-pr6 { /* NC */
1409 nvidia,pins = "kb_row6_pr6"; 1411 nvidia,pins = "kb_row6_pr6";
1410 nvidia,function = "kbc"; 1412 nvidia,function = "kbc";
1411 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1413 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1412 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1414 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1413 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1415 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1414 }; 1416 };
1415 kb_row7_pr7 { /* NC */ 1417 kb-row7-pr7 { /* NC */
1416 nvidia,pins = "kb_row7_pr7"; 1418 nvidia,pins = "kb_row7_pr7";
1417 nvidia,function = "rsvd2"; 1419 nvidia,function = "rsvd2";
1418 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1420 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1419 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1421 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1420 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1422 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1421 }; 1423 };
1422 kb_row8_ps0 { /* NC */ 1424 kb-row8-ps0 { /* NC */
1423 nvidia,pins = "kb_row8_ps0"; 1425 nvidia,pins = "kb_row8_ps0";
1424 nvidia,function = "rsvd2"; 1426 nvidia,function = "rsvd2";
1425 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1427 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1426 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1428 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1427 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1429 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1428 }; 1430 };
1429 kb_row9_ps1 { /* NC */ 1431 kb-row9-ps1 { /* NC */
1430 nvidia,pins = "kb_row9_ps1"; 1432 nvidia,pins = "kb_row9_ps1";
1431 nvidia,function = "rsvd2"; 1433 nvidia,function = "rsvd2";
1432 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1434 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1433 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1435 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1434 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1436 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1435 }; 1437 };
1436 kb_row12_ps4 { /* NC */ 1438 kb-row12-ps4 { /* NC */
1437 nvidia,pins = "kb_row12_ps4"; 1439 nvidia,pins = "kb_row12_ps4";
1438 nvidia,function = "rsvd2"; 1440 nvidia,function = "rsvd2";
1439 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1441 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1440 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1442 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1441 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1443 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1442 }; 1444 };
1443 kb_row13_ps5 { /* NC */ 1445 kb-row13-ps5 { /* NC */
1444 nvidia,pins = "kb_row13_ps5"; 1446 nvidia,pins = "kb_row13_ps5";
1445 nvidia,function = "rsvd2"; 1447 nvidia,function = "rsvd2";
1446 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1448 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1447 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1449 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1448 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1450 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1449 }; 1451 };
1450 kb_row14_ps6 { /* NC */ 1452 kb-row14-ps6 { /* NC */
1451 nvidia,pins = "kb_row14_ps6"; 1453 nvidia,pins = "kb_row14_ps6";
1452 nvidia,function = "rsvd2"; 1454 nvidia,function = "rsvd2";
1453 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1455 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1454 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1456 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1455 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1457 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1456 }; 1458 };
1457 kb_row15_ps7 { /* NC */ 1459 kb-row15-ps7 { /* NC */
1458 nvidia,pins = "kb_row15_ps7"; 1460 nvidia,pins = "kb_row15_ps7";
1459 nvidia,function = "rsvd3"; 1461 nvidia,function = "rsvd3";
1460 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1462 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1461 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1463 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1462 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1464 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1463 }; 1465 };
1464 kb_row16_pt0 { /* NC */ 1466 kb-row16-pt0 { /* NC */
1465 nvidia,pins = "kb_row16_pt0"; 1467 nvidia,pins = "kb_row16_pt0";
1466 nvidia,function = "rsvd2"; 1468 nvidia,function = "rsvd2";
1467 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1469 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1468 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1470 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1469 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1471 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1470 }; 1472 };
1471 kb_row17_pt1 { /* NC */ 1473 kb-row17-pt1 { /* NC */
1472 nvidia,pins = "kb_row17_pt1"; 1474 nvidia,pins = "kb_row17_pt1";
1473 nvidia,function = "rsvd2"; 1475 nvidia,function = "rsvd2";
1474 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1476 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
@@ -1496,14 +1498,14 @@
1496 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1498 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1497 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1499 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1498 }; 1500 };
1499 gpio_x1_aud_px1 { /* NC */ 1501 gpio-x1-aud-px1 { /* NC */
1500 nvidia,pins = "gpio_x1_aud_px1"; 1502 nvidia,pins = "gpio_x1_aud_px1";
1501 nvidia,function = "rsvd2"; 1503 nvidia,function = "rsvd2";
1502 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1504 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1503 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1505 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1504 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1506 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1505 }; 1507 };
1506 gpio_x3_aud_px3 { /* NC */ 1508 gpio-x3-aud-px3 { /* NC */
1507 nvidia,pins = "gpio_x3_aud_px3"; 1509 nvidia,pins = "gpio_x3_aud_px3";
1508 nvidia,function = "rsvd4"; 1510 nvidia,function = "rsvd4";
1509 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1511 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
@@ -1531,14 +1533,14 @@
1531 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1533 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1532 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1534 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1533 }; 1535 };
1534 clk3_req_pee1 { /* NC */ 1536 clk3-req-pee1 { /* NC */
1535 nvidia,pins = "clk3_req_pee1"; 1537 nvidia,pins = "clk3_req_pee1";
1536 nvidia,function = "rsvd2"; 1538 nvidia,function = "rsvd2";
1537 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1539 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1538 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1540 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1539 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1541 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1540 }; 1542 };
1541 dap_mclk1_req_pee2 { /* NC */ 1543 dap-mclk1-req-pee2 { /* NC */
1542 nvidia,pins = "dap_mclk1_req_pee2"; 1544 nvidia,pins = "dap_mclk1_req_pee2";
1543 nvidia,function = "rsvd4"; 1545 nvidia,function = "rsvd4";
1544 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1546 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
@@ -1554,7 +1556,7 @@
1554 * SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1 1556 * SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1
1555 * bits being set to 0xfffd according to the TRM! 1557 * bits being set to 0xfffd according to the TRM!
1556 */ 1558 */
1557 sdmmc3_clk_lb_out_pee4 { /* NC */ 1559 sdmmc3-clk-lb-out-pee4 { /* NC */
1558 nvidia,pins = "sdmmc3_clk_lb_out_pee4"; 1560 nvidia,pins = "sdmmc3_clk_lb_out_pee4";
1559 nvidia,function = "sdmmc3"; 1561 nvidia,function = "sdmmc3";
1560 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1562 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -1589,8 +1591,9 @@
1589 sgtl5000: codec@a { 1591 sgtl5000: codec@a {
1590 compatible = "fsl,sgtl5000"; 1592 compatible = "fsl,sgtl5000";
1591 reg = <0x0a>; 1593 reg = <0x0a>;
1592 VDDA-supply = <&reg_3v3>; 1594 VDDA-supply = <&reg_module_3v3_audio>;
1593 VDDIO-supply = <&vddio_1v8>; 1595 VDDD-supply = <&reg_1v8_vddio>;
1596 VDDIO-supply = <&reg_1v8_vddio>;
1594 clocks = <&tegra_car TEGRA124_CLK_EXTERN1>; 1597 clocks = <&tegra_car TEGRA124_CLK_EXTERN1>;
1595 }; 1598 };
1596 1599
@@ -1607,14 +1610,14 @@
1607 pinctrl-0 = <&as3722_default>; 1610 pinctrl-0 = <&as3722_default>;
1608 1611
1609 as3722_default: pinmux { 1612 as3722_default: pinmux {
1610 gpio2_7 { 1613 gpio2-7 {
1611 pins = "gpio2", /* PWR_EN_+V3.3 */ 1614 pins = "gpio2", /* PWR_EN_+V3.3 */
1612 "gpio7"; /* +V1.6_LPO */ 1615 "gpio7"; /* +V1.6_LPO */
1613 function = "gpio"; 1616 function = "gpio";
1614 bias-pull-up; 1617 bias-pull-up;
1615 }; 1618 };
1616 1619
1617 gpio0_1_3_4_5_6 { 1620 gpio0-1-3-4-5-6 {
1618 pins = "gpio0", "gpio1", "gpio3", 1621 pins = "gpio0", "gpio1", "gpio3",
1619 "gpio4", "gpio5", "gpio6"; 1622 "gpio4", "gpio5", "gpio6";
1620 bias-high-impedance; 1623 bias-high-impedance;
@@ -1622,18 +1625,18 @@
1622 }; 1625 };
1623 1626
1624 regulators { 1627 regulators {
1625 vsup-sd2-supply = <&reg_3v3>; 1628 vsup-sd2-supply = <&reg_module_3v3>;
1626 vsup-sd3-supply = <&reg_3v3>; 1629 vsup-sd3-supply = <&reg_module_3v3>;
1627 vsup-sd4-supply = <&reg_3v3>; 1630 vsup-sd4-supply = <&reg_module_3v3>;
1628 vsup-sd5-supply = <&reg_3v3>; 1631 vsup-sd5-supply = <&reg_module_3v3>;
1629 vin-ldo0-supply = <&vddio_ddr_1v35>; 1632 vin-ldo0-supply = <&reg_1v35_vddio_ddr>;
1630 vin-ldo1-6-supply = <&reg_3v3>; 1633 vin-ldo1-6-supply = <&reg_module_3v3>;
1631 vin-ldo2-5-7-supply = <&vddio_1v8>; 1634 vin-ldo2-5-7-supply = <&reg_1v8_vddio>;
1632 vin-ldo3-4-supply = <&reg_3v3>; 1635 vin-ldo3-4-supply = <&reg_module_3v3>;
1633 vin-ldo9-10-supply = <&reg_3v3>; 1636 vin-ldo9-10-supply = <&reg_module_3v3>;
1634 vin-ldo11-supply = <&reg_3v3>; 1637 vin-ldo11-supply = <&reg_module_3v3>;
1635 1638
1636 vdd_cpu: sd0 { 1639 reg_vdd_cpu: sd0 {
1637 regulator-name = "+VDD_CPU_AP"; 1640 regulator-name = "+VDD_CPU_AP";
1638 regulator-min-microvolt = <700000>; 1641 regulator-min-microvolt = <700000>;
1639 regulator-max-microvolt = <1400000>; 1642 regulator-max-microvolt = <1400000>;
@@ -1655,7 +1658,7 @@
1655 ams,ext-control = <1>; 1658 ams,ext-control = <1>;
1656 }; 1659 };
1657 1660
1658 vddio_ddr_1v35: sd2 { 1661 reg_1v35_vddio_ddr: sd2 {
1659 regulator-name = 1662 regulator-name =
1660 "+V1.35_VDDIO_DDR(sd2)"; 1663 "+V1.35_VDDIO_DDR(sd2)";
1661 regulator-min-microvolt = <1350000>; 1664 regulator-min-microvolt = <1350000>;
@@ -1673,13 +1676,13 @@
1673 regulator-boot-on; 1676 regulator-boot-on;
1674 }; 1677 };
1675 1678
1676 vdd_1v05: sd4 { 1679 reg_1v05_vdd: sd4 {
1677 regulator-name = "+V1.05"; 1680 regulator-name = "+V1.05";
1678 regulator-min-microvolt = <1050000>; 1681 regulator-min-microvolt = <1050000>;
1679 regulator-max-microvolt = <1050000>; 1682 regulator-max-microvolt = <1050000>;
1680 }; 1683 };
1681 1684
1682 vddio_1v8: sd5 { 1685 reg_1v8_vddio: sd5 {
1683 regulator-name = "+V1.8"; 1686 regulator-name = "+V1.8";
1684 regulator-min-microvolt = <1800000>; 1687 regulator-min-microvolt = <1800000>;
1685 regulator-max-microvolt = <1800000>; 1688 regulator-max-microvolt = <1800000>;
@@ -1687,7 +1690,7 @@
1687 regulator-always-on; 1690 regulator-always-on;
1688 }; 1691 };
1689 1692
1690 vdd_gpu: sd6 { 1693 reg_vdd_gpu: sd6 {
1691 regulator-name = "+VDD_GPU_AP"; 1694 regulator-name = "+VDD_GPU_AP";
1692 regulator-min-microvolt = <650000>; 1695 regulator-min-microvolt = <650000>;
1693 regulator-max-microvolt = <1200000>; 1696 regulator-max-microvolt = <1200000>;
@@ -1697,7 +1700,7 @@
1697 regulator-always-on; 1700 regulator-always-on;
1698 }; 1701 };
1699 1702
1700 avdd_1v05: ldo0 { 1703 reg_1v05_avdd: ldo0 {
1701 regulator-name = "+V1.05_AVDD"; 1704 regulator-name = "+V1.05_AVDD";
1702 regulator-min-microvolt = <1050000>; 1705 regulator-min-microvolt = <1050000>;
1703 regulator-max-microvolt = <1050000>; 1706 regulator-max-microvolt = <1050000>;
@@ -1772,12 +1775,13 @@
1772 * TMP451 temperature sensor 1775 * TMP451 temperature sensor
1773 * Note: THERM_N directly connected to AS3722 PMIC THERM 1776 * Note: THERM_N directly connected to AS3722 PMIC THERM
1774 */ 1777 */
1775 temperature-sensor@4c { 1778 temp-sensor@4c {
1776 compatible = "ti,tmp451"; 1779 compatible = "ti,tmp451";
1777 reg = <0x4c>; 1780 reg = <0x4c>;
1778 interrupt-parent = <&gpio>; 1781 interrupt-parent = <&gpio>;
1779 interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_LEVEL_LOW>; 1782 interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_LEVEL_LOW>;
1780 #thermal-sensor-cells = <1>; 1783 #thermal-sensor-cells = <1>;
1784 vcc-supply = <&reg_module_3v3>;
1781 }; 1785 };
1782 }; 1786 };
1783 1787
@@ -1809,9 +1813,9 @@
1809 sata@70020000 { 1813 sata@70020000 {
1810 phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>; 1814 phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>;
1811 phy-names = "sata-0"; 1815 phy-names = "sata-0";
1812 avdd-supply = <&vdd_1v05>; 1816 avdd-supply = <&reg_1v05_vdd>;
1813 hvdd-supply = <&reg_3v3>; 1817 hvdd-supply = <&reg_module_3v3>;
1814 vddio-supply = <&vdd_1v05>; 1818 vddio-supply = <&reg_1v05_vdd>;
1815 }; 1819 };
1816 1820
1817 usb@70090000 { 1821 usb@70090000 {
@@ -1822,14 +1826,14 @@
1822 <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, 1826 <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>,
1823 <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>; 1827 <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>;
1824 phy-names = "usb2-0", "usb3-1", "usb2-1", "usb2-2", "usb3-0"; 1828 phy-names = "usb2-0", "usb3-1", "usb2-1", "usb2-2", "usb3-0";
1825 avddio-pex-supply = <&vdd_1v05>; 1829 avddio-pex-supply = <&reg_1v05_vdd>;
1826 avdd-pll-erefe-supply = <&avdd_1v05>; 1830 avdd-pll-erefe-supply = <&reg_1v05_avdd>;
1827 avdd-pll-utmip-supply = <&vddio_1v8>; 1831 avdd-pll-utmip-supply = <&reg_1v8_vddio>;
1828 avdd-usb-ss-pll-supply = <&vdd_1v05>; 1832 avdd-usb-ss-pll-supply = <&reg_1v05_vdd>;
1829 avdd-usb-supply = <&reg_3v3>; 1833 avdd-usb-supply = <&reg_module_3v3>;
1830 dvddio-pex-supply = <&vdd_1v05>; 1834 dvddio-pex-supply = <&reg_1v05_vdd>;
1831 hvdd-usb-ss-pll-e-supply = <&reg_3v3>; 1835 hvdd-usb-ss-pll-e-supply = <&reg_module_3v3>;
1832 hvdd-usb-ss-supply = <&reg_3v3>; 1836 hvdd-usb-ss-supply = <&reg_module_3v3>;
1833 }; 1837 };
1834 1838
1835 padctl@7009f000 { 1839 padctl@7009f000 {
@@ -1839,18 +1843,18 @@
1839 1843
1840 lanes { 1844 lanes {
1841 usb2-0 { 1845 usb2-0 {
1842 nvidia,function = "xusb";
1843 status = "okay"; 1846 status = "okay";
1847 nvidia,function = "xusb";
1844 }; 1848 };
1845 1849
1846 usb2-1 { 1850 usb2-1 {
1847 nvidia,function = "xusb";
1848 status = "okay"; 1851 status = "okay";
1852 nvidia,function = "xusb";
1849 }; 1853 };
1850 1854
1851 usb2-2 { 1855 usb2-2 {
1852 nvidia,function = "xusb";
1853 status = "okay"; 1856 status = "okay";
1857 nvidia,function = "xusb";
1854 }; 1858 };
1855 }; 1859 };
1856 }; 1860 };
@@ -1860,28 +1864,28 @@
1860 1864
1861 lanes { 1865 lanes {
1862 pcie-0 { 1866 pcie-0 {
1863 nvidia,function = "usb3-ss";
1864 status = "okay"; 1867 status = "okay";
1868 nvidia,function = "usb3-ss";
1865 }; 1869 };
1866 1870
1867 pcie-1 { 1871 pcie-1 {
1868 nvidia,function = "usb3-ss";
1869 status = "okay"; 1872 status = "okay";
1873 nvidia,function = "usb3-ss";
1870 }; 1874 };
1871 1875
1872 pcie-2 { 1876 pcie-2 {
1873 nvidia,function = "pcie";
1874 status = "okay"; 1877 status = "okay";
1878 nvidia,function = "pcie";
1875 }; 1879 };
1876 1880
1877 pcie-3 { 1881 pcie-3 {
1878 nvidia,function = "pcie";
1879 status = "okay"; 1882 status = "okay";
1883 nvidia,function = "pcie";
1880 }; 1884 };
1881 1885
1882 pcie-4 { 1886 pcie-4 {
1883 nvidia,function = "pcie";
1884 status = "okay"; 1887 status = "okay";
1888 nvidia,function = "pcie";
1885 }; 1889 };
1886 }; 1890 };
1887 }; 1891 };
@@ -1891,8 +1895,8 @@
1891 1895
1892 lanes { 1896 lanes {
1893 sata-0 { 1897 sata-0 {
1894 nvidia,function = "sata";
1895 status = "okay"; 1898 status = "okay";
1899 nvidia,function = "sata";
1896 }; 1900 };
1897 }; 1901 };
1898 }; 1902 };
@@ -1903,7 +1907,6 @@
1903 usb2-0 { 1907 usb2-0 {
1904 status = "okay"; 1908 status = "okay";
1905 mode = "otg"; 1909 mode = "otg";
1906
1907 vbus-supply = <&reg_usbo1_vbus>; 1910 vbus-supply = <&reg_usbo1_vbus>;
1908 }; 1911 };
1909 1912
@@ -1911,7 +1914,6 @@
1911 usb2-1 { 1914 usb2-1 {
1912 status = "okay"; 1915 status = "okay";
1913 mode = "host"; 1916 mode = "host";
1914
1915 vbus-supply = <&reg_usbh_vbus>; 1917 vbus-supply = <&reg_usbh_vbus>;
1916 }; 1918 };
1917 1919
@@ -1919,18 +1921,19 @@
1919 usb2-2 { 1921 usb2-2 {
1920 status = "okay"; 1922 status = "okay";
1921 mode = "host"; 1923 mode = "host";
1922
1923 vbus-supply = <&reg_usbh_vbus>; 1924 vbus-supply = <&reg_usbh_vbus>;
1924 }; 1925 };
1925 1926
1926 usb3-0 { 1927 usb3-0 {
1927 nvidia,usb2-companion = <2>;
1928 status = "okay"; 1928 status = "okay";
1929 nvidia,usb2-companion = <2>;
1930 vbus-supply = <&reg_usbh_vbus>;
1929 }; 1931 };
1930 1932
1931 usb3-1 { 1933 usb3-1 {
1932 nvidia,usb2-companion = <0>;
1933 status = "okay"; 1934 status = "okay";
1935 nvidia,usb2-companion = <0>;
1936 vbus-supply = <&reg_usbo1_vbus>;
1934 }; 1937 };
1935 }; 1938 };
1936 }; 1939 };
@@ -1940,13 +1943,16 @@
1940 status = "okay"; 1943 status = "okay";
1941 bus-width = <8>; 1944 bus-width = <8>;
1942 non-removable; 1945 non-removable;
1946 vmmc-supply = <&reg_module_3v3>; /* VCC */
1947 vqmmc-supply = <&reg_1v8_vddio>; /* VCCQ */
1948 mmc-ddr-1_8v;
1943 }; 1949 };
1944 1950
1945 /* CPU DFLL clock */ 1951 /* CPU DFLL clock */
1946 clock@70110000 { 1952 clock@70110000 {
1947 status = "okay"; 1953 status = "okay";
1948 vdd-cpu-supply = <&vdd_cpu>;
1949 nvidia,i2c-fs-rate = <400000>; 1954 nvidia,i2c-fs-rate = <400000>;
1955 vdd-cpu-supply = <&reg_vdd_cpu>;
1950 }; 1956 };
1951 1957
1952 ahub@70300000 { 1958 ahub@70300000 {
@@ -1955,22 +1961,15 @@
1955 }; 1961 };
1956 }; 1962 };
1957 1963
1958 clocks { 1964 clk32k_in: osc3 {
1959 compatible = "simple-bus"; 1965 compatible = "fixed-clock";
1960 #address-cells = <1>; 1966 #clock-cells = <0>;
1961 #size-cells = <0>; 1967 clock-frequency = <32768>;
1962
1963 clk32k_in: clock@0 {
1964 compatible = "fixed-clock";
1965 reg = <0>;
1966 #clock-cells = <0>;
1967 clock-frequency = <32768>;
1968 };
1969 }; 1968 };
1970 1969
1971 cpus { 1970 cpus {
1972 cpu@0 { 1971 cpu@0 {
1973 vdd-cpu-supply = <&vdd_cpu>; 1972 vdd-cpu-supply = <&reg_vdd_cpu>;
1974 }; 1973 };
1975 }; 1974 };
1976 1975
@@ -1980,7 +1979,7 @@
1980 regulator-min-microvolt = <1050000>; 1979 regulator-min-microvolt = <1050000>;
1981 regulator-max-microvolt = <1050000>; 1980 regulator-max-microvolt = <1050000>;
1982 gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; 1981 gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>;
1983 vin-supply = <&vdd_1v05>; 1982 vin-supply = <&reg_1v05_vdd>;
1984 }; 1983 };
1985 1984
1986 reg_3v3_mxm: regulator-3v3-mxm { 1985 reg_3v3_mxm: regulator-3v3-mxm {
@@ -1992,7 +1991,15 @@
1992 regulator-boot-on; 1991 regulator-boot-on;
1993 }; 1992 };
1994 1993
1995 reg_3v3: regulator-3v3 { 1994 reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi {
1995 compatible = "regulator-fixed";
1996 regulator-name = "+V3.3_AVDD_HDMI";
1997 regulator-min-microvolt = <3300000>;
1998 regulator-max-microvolt = <3300000>;
1999 vin-supply = <&reg_1v05_vdd>;
2000 };
2001
2002 reg_module_3v3: regulator-module-3v3 {
1996 compatible = "regulator-fixed"; 2003 compatible = "regulator-fixed";
1997 regulator-name = "+V3.3"; 2004 regulator-name = "+V3.3";
1998 regulator-min-microvolt = <3300000>; 2005 regulator-min-microvolt = <3300000>;
@@ -2005,12 +2012,12 @@
2005 vin-supply = <&reg_3v3_mxm>; 2012 vin-supply = <&reg_3v3_mxm>;
2006 }; 2013 };
2007 2014
2008 reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi { 2015 reg_module_3v3_audio: regulator-module-3v3-audio {
2009 compatible = "regulator-fixed"; 2016 compatible = "regulator-fixed";
2010 regulator-name = "+V3.3_AVDD_HDMI"; 2017 regulator-name = "+V3.3_AUDIO_AVDD_S";
2011 regulator-min-microvolt = <3300000>; 2018 regulator-min-microvolt = <3300000>;
2012 regulator-max-microvolt = <3300000>; 2019 regulator-max-microvolt = <3300000>;
2013 vin-supply = <&vdd_1v05>; 2020 regulator-always-on;
2014 }; 2021 };
2015 2022
2016 sound { 2023 sound {
@@ -2064,7 +2071,7 @@
2064 2071
2065&gpio { 2072&gpio {
2066 /* I210 Gigabit Ethernet Controller Reset */ 2073 /* I210 Gigabit Ethernet Controller Reset */
2067 lan_reset_n { 2074 lan-reset-n {
2068 gpio-hog; 2075 gpio-hog;
2069 gpios = <TEGRA_GPIO(S, 2) GPIO_ACTIVE_HIGH>; 2076 gpios = <TEGRA_GPIO(S, 2) GPIO_ACTIVE_HIGH>;
2070 output-high; 2077 output-high;
@@ -2072,7 +2079,7 @@
2072 }; 2079 };
2073 2080
2074 /* Control MXM3 pin 26 Reset Module Output Carrier Input */ 2081 /* Control MXM3 pin 26 Reset Module Output Carrier Input */
2075 reset_moci_ctrl { 2082 reset-moci-ctrl {
2076 gpio-hog; 2083 gpio-hog;
2077 gpios = <TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>; 2084 gpios = <TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>;
2078 output-high; 2085 output-high;
diff --git a/arch/arm/boot/dts/tegra20-colibri-eval-v3.dts b/arch/arm/boot/dts/tegra20-colibri-eval-v3.dts
new file mode 100644
index 000000000000..3c0f2681fcde
--- /dev/null
+++ b/arch/arm/boot/dts/tegra20-colibri-eval-v3.dts
@@ -0,0 +1,262 @@
1// SPDX-License-Identifier: GPL-2.0 OR MIT
2/dts-v1/;
3
4#include <dt-bindings/input/input.h>
5#include "tegra20-colibri.dtsi"
6
7/ {
8 model = "Toradex Colibri T20 on Colibri Evaluation Board";
9 compatible = "toradex,colibri_t20-eval-v3", "toradex,colibri_t20",
10 "nvidia,tegra20";
11
12 aliases {
13 rtc0 = "/i2c@7000c000/rtc@68";
14 rtc1 = "/i2c@7000d000/pmic@34";
15 rtc2 = "/rtc@7000e000";
16 serial0 = &uarta;
17 serial1 = &uartd;
18 serial2 = &uartb;
19 };
20
21 chosen {
22 stdout-path = "serial0:115200n8";
23 };
24
25 host1x@50000000 {
26 dc@54200000 {
27 rgb {
28 status = "okay";
29 nvidia,panel = <&panel>;
30 };
31 };
32
33 hdmi@54280000 {
34 status = "okay";
35 hdmi-supply = <&reg_5v0>;
36 };
37 };
38
39 pinmux@70000014 {
40 state_default: pinmux {
41 bl-on {
42 nvidia,tristate = <TEGRA_PIN_DISABLE>;
43 };
44
45 ddc {
46 nvidia,tristate = <TEGRA_PIN_DISABLE>;
47 };
48
49 hotplug-detect {
50 nvidia,tristate = <TEGRA_PIN_DISABLE>;
51 };
52
53 i2c {
54 nvidia,tristate = <TEGRA_PIN_DISABLE>;
55 };
56
57 lcd {
58 nvidia,tristate = <TEGRA_PIN_DISABLE>;
59 };
60
61 lm1 {
62 nvidia,tristate = <TEGRA_PIN_DISABLE>;
63 };
64
65 mmc {
66 nvidia,tristate = <TEGRA_PIN_DISABLE>;
67 };
68
69 mmccd {
70 nvidia,tristate = <TEGRA_PIN_DISABLE>;
71 };
72
73 pwm-a-b {
74 nvidia,tristate = <TEGRA_PIN_DISABLE>;
75 };
76
77 pwm-c-d {
78 nvidia,tristate = <TEGRA_PIN_DISABLE>;
79 };
80
81 ssp {
82 nvidia,tristate = <TEGRA_PIN_DISABLE>;
83 };
84
85 uart-a {
86 nvidia,tristate = <TEGRA_PIN_DISABLE>;
87 };
88
89 uart-b {
90 nvidia,tristate = <TEGRA_PIN_DISABLE>;
91 };
92
93 uart-c {
94 nvidia,tristate = <TEGRA_PIN_DISABLE>;
95 };
96
97 usbh-pen {
98 nvidia,tristate = <TEGRA_PIN_DISABLE>;
99 };
100 };
101 };
102
103 /* Colibri UART-A */
104 serial@70006000 {
105 status = "okay";
106 };
107
108 /* Colibri UART-C */
109 serial@70006040 {
110 status = "okay";
111 };
112
113 /* Colibri UART-B */
114 serial@70006300 {
115 status = "okay";
116 };
117
118 pwm@7000a000 {
119 status = "okay";
120 };
121
122 /*
123 * GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier
124 * board)
125 */
126 i2c@7000c000 {
127 status = "okay";
128 clock-frequency = <400000>;
129
130 /* M41T0M6 real time clock on carrier board */
131 rtc@68 {
132 compatible = "st,m41t0";
133 reg = <0x68>;
134 };
135 };
136
137 /* GEN2_I2C: unused */
138
139 /* CAM_I2C (I2C3): unused */
140
141 /* DDC_CLOCK/DATA on X3 pin 15/16 (e.g. display EDID) */
142 i2c@7000c400 {
143 status = "okay";
144 };
145
146 /* EHCI instance 0: USB1_DP/N -> USBC_P/N */
147 usb@c5000000 {
148 status = "okay";
149 dr_mode = "otg";
150 };
151
152 usb-phy@c5000000 {
153 status = "okay";
154 vbus-supply = <&reg_usbc_vbus>;
155 };
156
157 /* EHCI instance 2: USB3_DP/N -> USBH_P/N */
158 usb@c5008000 {
159 status = "okay";
160 };
161
162 usb-phy@c5008000 {
163 status = "okay";
164 vbus-supply = <&reg_usbh_vbus>;
165 };
166
167 /* SPI4: Colibri SSP */
168 spi@7000da00 {
169 status = "okay";
170 spi-max-frequency = <25000000>;
171
172 can@0 {
173 compatible = "microchip,mcp2515";
174 reg = <0>;
175 clocks = <&clk16m>;
176 interrupt-parent = <&gpio>;
177 /* CAN_INT */
178 interrupts = <TEGRA_GPIO(A, 0) IRQ_TYPE_EDGE_FALLING>;
179 spi-max-frequency = <10000000>;
180 vdd-supply = <&reg_3v3>;
181 xceiver-supply = <&reg_5v0>;
182 };
183 };
184
185 /* SD/MMC */
186 sdhci@c8000600 {
187 status = "okay";
188 bus-width = <4>;
189 cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>; /* MMCD */
190 no-1-8-v;
191 };
192
193 backlight: backlight {
194 compatible = "pwm-backlight";
195 brightness-levels = <255 128 64 32 16 8 4 0>;
196 default-brightness-level = <6>;
197 /* BL_ON */
198 enable-gpios = <&gpio TEGRA_GPIO(T, 4) GPIO_ACTIVE_HIGH>;
199 power-supply = <&reg_3v3>;
200 pwms = <&pwm 0 5000000>; /* PWM<A> */
201 };
202
203 clk16m: osc3 {
204 compatible = "fixed-clock";
205 #clock-cells = <0>;
206 clock-frequency = <16000000>;
207 };
208
209 gpio-keys {
210 compatible = "gpio-keys";
211
212 wakeup {
213 label = "SODIMM pin 45 wakeup";
214 gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>;
215 linux,code = <KEY_WAKEUP>;
216 debounce-interval = <10>;
217 wakeup-source;
218 };
219 };
220
221 panel: panel {
222 /*
223 * edt,et057090dhu: EDT 5.7" LCD TFT
224 * edt,et070080dh6: EDT 7.0" LCD TFT
225 */
226 compatible = "edt,et057090dhu", "simple-panel";
227 backlight = <&backlight>;
228 power-supply = <&reg_3v3>;
229 };
230
231 reg_3v3: regulator-3v3 {
232 compatible = "regulator-fixed";
233 regulator-name = "3.3V_SW";
234 regulator-min-microvolt = <3300000>;
235 regulator-max-microvolt = <3300000>;
236 };
237
238 reg_5v0: regulator-5v0 {
239 compatible = "regulator-fixed";
240 regulator-name = "5V_SW";
241 regulator-min-microvolt = <5000000>;
242 regulator-max-microvolt = <5000000>;
243 };
244
245 reg_usbc_vbus: regulator-usbc-vbus {
246 compatible = "regulator-fixed";
247 regulator-name = "VCC_USB5";
248 regulator-min-microvolt = <5000000>;
249 regulator-max-microvolt = <5000000>;
250 vin-supply = <&reg_5v0>;
251 };
252
253 /* USBH_PEN resp. USB_P_EN */
254 reg_usbh_vbus: regulator-usbh-vbus {
255 compatible = "regulator-fixed";
256 regulator-name = "VCC_USB[1-4]";
257 regulator-min-microvolt = <5000000>;
258 regulator-max-microvolt = <5000000>;
259 gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
260 vin-supply = <&reg_5v0>;
261 };
262};
diff --git a/arch/arm/boot/dts/tegra20-colibri-iris.dts b/arch/arm/boot/dts/tegra20-colibri-iris.dts
index 57f16c0e9917..d8004d68efa0 100644
--- a/arch/arm/boot/dts/tegra20-colibri-iris.dts
+++ b/arch/arm/boot/dts/tegra20-colibri-iris.dts
@@ -1,15 +1,21 @@
1// SPDX-License-Identifier: GPL-2.0 1// SPDX-License-Identifier: GPL-2.0
2/dts-v1/; 2/dts-v1/;
3 3
4#include <dt-bindings/input/input.h>
4#include "tegra20-colibri.dtsi" 5#include "tegra20-colibri.dtsi"
5 6
6/ { 7/ {
7 model = "Toradex Colibri T20 256/512 MB on Iris"; 8 model = "Toradex Colibri T20 on Iris";
8 compatible = "toradex,iris", "toradex,colibri_t20-512", "nvidia,tegra20"; 9 compatible = "toradex,colibri_t20-iris", "toradex,colibri_t20",
10 "nvidia,tegra20";
9 11
10 aliases { 12 aliases {
13 rtc0 = "/i2c@7000c000/rtc@68";
14 rtc1 = "/i2c@7000d000/pmic@34";
15 rtc2 = "/rtc@7000e000";
11 serial0 = &uarta; 16 serial0 = &uarta;
12 serial1 = &uartd; 17 serial1 = &uartd;
18 serial2 = &uartb;
13 }; 19 };
14 20
15 chosen { 21 chosen {
@@ -17,90 +23,222 @@
17 }; 23 };
18 24
19 host1x@50000000 { 25 host1x@50000000 {
26 dc@54200000 {
27 rgb {
28 status = "okay";
29 nvidia,panel = <&panel>;
30 };
31 };
32
20 hdmi@54280000 { 33 hdmi@54280000 {
21 status = "okay"; 34 status = "okay";
35 hdmi-supply = <&reg_5v0>;
22 }; 36 };
23 }; 37 };
24 38
25 pinmux@70000014 { 39 pinmux@70000014 {
26 state_default: pinmux { 40 state_default: pinmux {
27 hdint { 41 bl-on {
42 nvidia,tristate = <TEGRA_PIN_DISABLE>;
43 };
44
45 ddc {
46 nvidia,tristate = <TEGRA_PIN_DISABLE>;
47 };
48
49 hotplug-detect {
50 nvidia,tristate = <TEGRA_PIN_DISABLE>;
51 };
52
53 i2c {
54 nvidia,tristate = <TEGRA_PIN_DISABLE>;
55 };
56
57 lcd {
58 nvidia,tristate = <TEGRA_PIN_DISABLE>;
59 };
60
61 lm1 {
62 nvidia,tristate = <TEGRA_PIN_DISABLE>;
63 };
64
65 mmc {
66 nvidia,tristate = <TEGRA_PIN_DISABLE>;
67 };
68
69 mmccd {
70 nvidia,tristate = <TEGRA_PIN_DISABLE>;
71 };
72
73 pwm-a-b {
74 nvidia,tristate = <TEGRA_PIN_DISABLE>;
75 };
76
77 pwm-c-d {
78 nvidia,tristate = <TEGRA_PIN_DISABLE>;
79 };
80
81 ssp {
28 nvidia,tristate = <TEGRA_PIN_DISABLE>; 82 nvidia,tristate = <TEGRA_PIN_DISABLE>;
29 }; 83 };
30 84
31 i2cddc { 85 uart-a {
32 nvidia,tristate = <TEGRA_PIN_DISABLE>; 86 nvidia,tristate = <TEGRA_PIN_DISABLE>;
33 }; 87 };
34 88
35 sdio4 { 89 uart-b {
36 nvidia,tristate = <TEGRA_PIN_DISABLE>; 90 nvidia,tristate = <TEGRA_PIN_DISABLE>;
37 }; 91 };
38 92
39 uarta { 93 uart-c {
40 nvidia,tristate = <TEGRA_PIN_DISABLE>; 94 nvidia,tristate = <TEGRA_PIN_DISABLE>;
41 }; 95 };
42 96
43 uartd { 97 usbh-pen {
44 nvidia,tristate = <TEGRA_PIN_DISABLE>; 98 nvidia,tristate = <TEGRA_PIN_DISABLE>;
45 }; 99 };
46 }; 100 };
47 }; 101 };
48 102
103 /* Colibri UART-A */
49 serial@70006000 { 104 serial@70006000 {
50 status = "okay"; 105 status = "okay";
51 }; 106 };
52 107
108 /* Colibri UART-C */
109 serial@70006040 {
110 status = "okay";
111 };
112
113 /* Colibri UART-B */
53 serial@70006300 { 114 serial@70006300 {
54 status = "okay"; 115 status = "okay";
55 }; 116 };
56 117
57 i2c_ddc: i2c@7000c400 { 118 pwm@7000a000 {
119 status = "okay";
120 };
121
122 /*
123 * GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier
124 * board)
125 */
126 i2c@7000c000 {
127 status = "okay";
128 clock-frequency = <400000>;
129
130 /* M41T0M6 real time clock on carrier board */
131 rtc@68 {
132 compatible = "st,m41t0";
133 reg = <0x68>;
134 };
135 };
136
137 /* GEN2_I2C: unused */
138
139 /* CAM_I2C (I2C3): unused */
140
141 /* DDC_CLOCK/DATA on X3 pin 15/16 (e.g. display EDID) */
142 i2c@7000c400 {
58 status = "okay"; 143 status = "okay";
59 }; 144 };
60 145
146 /* EHCI instance 0: USB1_DP/N -> USBC_P/N */
61 usb@c5000000 { 147 usb@c5000000 {
62 status = "okay"; 148 status = "okay";
149 dr_mode = "otg";
63 }; 150 };
64 151
65 usb-phy@c5000000 { 152 usb-phy@c5000000 {
66 status = "okay"; 153 status = "okay";
154 vbus-supply = <&reg_usbc_vbus>;
67 }; 155 };
68 156
157 /* EHCI instance 2: USB3_DP/N -> USBH_P/N */
69 usb@c5008000 { 158 usb@c5008000 {
70 status = "okay"; 159 status = "okay";
71 }; 160 };
72 161
73 usb-phy@c5008000 { 162 usb-phy@c5008000 {
74 status = "okay"; 163 status = "okay";
164 vbus-supply = <&reg_usbh_vbus>;
165 };
166
167 /* SPI4: Colibri SSP */
168 spi@7000da00 {
169 status = "okay";
170 spi-max-frequency = <25000000>;
75 }; 171 };
76 172
173 /* SD/MMC */
77 sdhci@c8000600 { 174 sdhci@c8000600 {
78 status = "okay"; 175 status = "okay";
79 bus-width = <4>; 176 bus-width = <4>;
80 vmmc-supply = <&vcc_sd_reg>; 177 cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>; /* MMCD */
81 vqmmc-supply = <&vcc_sd_reg>; 178 no-1-8-v;
82 }; 179 };
83 180
84 regulators { 181 backlight: backlight {
85 regulator@0 { 182 compatible = "pwm-backlight";
86 compatible = "regulator-fixed"; 183 brightness-levels = <255 128 64 32 16 8 4 0>;
87 reg = <0>; 184 default-brightness-level = <6>;
88 regulator-name = "usb_host_vbus"; 185 /* BL_ON */
89 regulator-min-microvolt = <5000000>; 186 enable-gpios = <&gpio TEGRA_GPIO(T, 4) GPIO_ACTIVE_HIGH>;
90 regulator-max-microvolt = <5000000>; 187 power-supply = <&reg_3v3>;
91 regulator-boot-on; 188 pwms = <&pwm 0 5000000>; /* PWM<A> */
92 regulator-always-on; 189 };
93 gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>; 190
94 }; 191 gpio-keys {
192 compatible = "gpio-keys";
95 193
96 vcc_sd_reg: regulator@1 { 194 wakeup {
97 compatible = "regulator-fixed"; 195 label = "SODIMM pin 45 wakeup";
98 reg = <1>; 196 gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>;
99 regulator-name = "vcc_sd"; 197 linux,code = <KEY_WAKEUP>;
100 regulator-min-microvolt = <3300000>; 198 debounce-interval = <10>;
101 regulator-max-microvolt = <3300000>; 199 wakeup-source;
102 regulator-boot-on;
103 regulator-always-on;
104 }; 200 };
105 }; 201 };
202
203 panel: panel {
204 /*
205 * edt,et057090dhu: EDT 5.7" LCD TFT
206 * edt,et070080dh6: EDT 7.0" LCD TFT
207 */
208 compatible = "edt,et057090dhu", "simple-panel";
209 backlight = <&backlight>;
210 power-supply = <&reg_3v3>;
211 };
212
213 reg_3v3: regulator-3v3 {
214 compatible = "regulator-fixed";
215 regulator-name = "3.3V";
216 regulator-min-microvolt = <3300000>;
217 regulator-max-microvolt = <3300000>;
218 };
219
220 reg_5v0: regulator-5v0 {
221 compatible = "regulator-fixed";
222 regulator-name = "5V";
223 regulator-min-microvolt = <5000000>;
224 regulator-max-microvolt = <5000000>;
225 };
226
227 reg_usbc_vbus: regulator-usbc-vbus {
228 compatible = "regulator-fixed";
229 regulator-name = "VCC_USB2";
230 regulator-min-microvolt = <5000000>;
231 regulator-max-microvolt = <5000000>;
232 vin-supply = <&reg_5v0>;
233 };
234
235 /* USBH_PEN resp. USB_P_EN */
236 reg_usbh_vbus: regulator-usbh-vbus {
237 compatible = "regulator-fixed";
238 regulator-name = "VCC_USB1";
239 regulator-min-microvolt = <5000000>;
240 regulator-max-microvolt = <5000000>;
241 gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
242 vin-supply = <&reg_5v0>;
243 };
106}; 244};
diff --git a/arch/arm/boot/dts/tegra20-colibri.dtsi b/arch/arm/boot/dts/tegra20-colibri.dtsi
index e7b9ab09908a..6162d193e12c 100644
--- a/arch/arm/boot/dts/tegra20-colibri.dtsi
+++ b/arch/arm/boot/dts/tegra20-colibri.dtsi
@@ -1,15 +1,13 @@
1// SPDX-License-Identifier: GPL-2.0 1// SPDX-License-Identifier: GPL-2.0
2#include "tegra20.dtsi" 2#include "tegra20.dtsi"
3 3
4/*
5 * Toradex Colibri T20 Module Device Tree
6 * Compatible for Revisions Colibri T20 256MB V1.1B, V1.2A;
7 * Colibri T20 256MB IT V1.2A; Colibri T20 512MB V1.1C, V1.2A;
8 * Colibri T20 512MB IT V1.2A
9 */
4/ { 10/ {
5 model = "Toradex Colibri T20 256/512 MB";
6 compatible = "toradex,colibri_t20-512", "nvidia,tegra20";
7
8 aliases {
9 rtc0 = "/i2c@7000d000/tps6586x@34";
10 rtc1 = "/rtc@7000e000";
11 };
12
13 memory@0 { 11 memory@0 {
14 /* 12 /*
15 * Set memory to 256 MB to be safe as this could be used on 13 * Set memory to 256 MB to be safe as this could be used on
@@ -21,12 +19,11 @@
21 19
22 host1x@50000000 { 20 host1x@50000000 {
23 hdmi@54280000 { 21 hdmi@54280000 {
24 vdd-supply = <&hdmi_vdd_reg>; 22 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
25 pll-supply = <&hdmi_pll_reg>; 23 nvidia,hpd-gpio =
26 24 <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
27 nvidia,ddc-i2c-bus = <&i2c_ddc>; 25 pll-supply = <&reg_1v8_avdd_hdmi_pll>;
28 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) 26 vdd-supply = <&reg_3v3_avdd_hdmi>;
29 GPIO_ACTIVE_HIGH>;
30 }; 27 };
31 }; 28 };
32 29
@@ -35,187 +32,406 @@
35 pinctrl-0 = <&state_default>; 32 pinctrl-0 = <&state_default>;
36 33
37 state_default: pinmux { 34 state_default: pinmux {
38 audio_refclk { 35 /* Analogue Audio AC97 to WM9712 (On-module) */
36 audio-refclk {
39 nvidia,pins = "cdev1"; 37 nvidia,pins = "cdev1";
40 nvidia,function = "plla_out"; 38 nvidia,function = "plla_out";
41 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 39 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
42 nvidia,tristate = <TEGRA_PIN_DISABLE>; 40 nvidia,tristate = <TEGRA_PIN_DISABLE>;
43 }; 41 };
44 crt {
45 nvidia,pins = "crtp";
46 nvidia,function = "crt";
47 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
48 nvidia,tristate = <TEGRA_PIN_ENABLE>;
49 };
50 dap3 { 42 dap3 {
51 nvidia,pins = "dap3"; 43 nvidia,pins = "dap3";
52 nvidia,function = "dap3"; 44 nvidia,function = "dap3";
53 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 45 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
54 nvidia,tristate = <TEGRA_PIN_DISABLE>; 46 nvidia,tristate = <TEGRA_PIN_DISABLE>;
55 }; 47 };
56 displaya { 48
57 nvidia,pins = "ld0", "ld1", "ld2", "ld3", 49 /*
58 "ld4", "ld5", "ld6", "ld7", "ld8", 50 * AC97_RESET, ULPI_RESET, AC97_INT aka WM9712 GENIRQ
59 "ld9", "ld10", "ld11", "ld12", "ld13", 51 * (All on-module), SODIMM Pin 45 Wakeup
60 "ld14", "ld15", "ld16", "ld17", 52 */
61 "lhs", "lpw0", "lpw2", "lsc0", 53 gpio-uac {
62 "lsc1", "lsck", "lsda", "lspi", "lvs"; 54 nvidia,pins = "uac";
63 nvidia,function = "displaya"; 55 nvidia,function = "rsvd2";
64 nvidia,tristate = <TEGRA_PIN_ENABLE>;
65 };
66 gpio_dte {
67 nvidia,pins = "dte";
68 nvidia,function = "rsvd1";
69 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
70 nvidia,tristate = <TEGRA_PIN_DISABLE>;
71 };
72 gpio_gmi {
73 nvidia,pins = "ata", "atc", "atd", "ate",
74 "dap1", "dap2", "dap4", "gpu", "irrx",
75 "irtx", "spia", "spib", "spic";
76 nvidia,function = "gmi";
77 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 56 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
78 nvidia,tristate = <TEGRA_PIN_DISABLE>; 57 nvidia,tristate = <TEGRA_PIN_DISABLE>;
79 }; 58 };
80 gpio_pta { 59
60 /*
61 * Buffer Enables for nPWE and RDnWR (On-module,
62 * see GPIO hogging further down below)
63 */
64 gpio-pta {
81 nvidia,pins = "pta"; 65 nvidia,pins = "pta";
82 nvidia,function = "rsvd4"; 66 nvidia,function = "rsvd4";
83 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 67 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
84 nvidia,tristate = <TEGRA_PIN_DISABLE>; 68 nvidia,tristate = <TEGRA_PIN_DISABLE>;
85 }; 69 };
86 gpio_uac { 70
87 nvidia,pins = "uac"; 71 /*
88 nvidia,function = "rsvd2"; 72 * CLK_32K_OUT, CORE_PWR_REQ, CPU_PWR_REQ, PWR_INT_N,
89 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 73 * SYS_CLK_REQ (All on-module)
74 */
75 pmc {
76 nvidia,pins = "pmc";
77 nvidia,function = "pwr_on";
90 nvidia,tristate = <TEGRA_PIN_DISABLE>; 78 nvidia,tristate = <TEGRA_PIN_DISABLE>;
91 }; 79 };
92 hdint { 80
93 nvidia,pins = "hdint"; 81 /*
82 * Colibri Address/Data Bus (GMI)
83 * Note: spid and spie optionally used for SPI1
84 */
85 gmi {
86 nvidia,pins = "atc", "atd", "ate", "dap1",
87 "dap2", "dap4", "gmd", "gpu",
88 "irrx", "irtx", "spia", "spib",
89 "spic", "spid", "spie", "uca",
90 "ucb";
91 nvidia,function = "gmi";
92 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
93 nvidia,tristate = <TEGRA_PIN_ENABLE>;
94 };
95 /* Further pins may be used as GPIOs */
96 gmi-gpio1 {
97 nvidia,pins = "lpw0", "lsc1", "lsck", "lsda";
94 nvidia,function = "hdmi"; 98 nvidia,function = "hdmi";
95 nvidia,tristate = <TEGRA_PIN_ENABLE>; 99 nvidia,tristate = <TEGRA_PIN_ENABLE>;
96 }; 100 };
97 i2c1 { 101 gmi-gpio2 {
98 nvidia,pins = "rm"; 102 nvidia,pins = "lcsn", "ldc", "lm0", "lsdi";
99 nvidia,function = "i2c1"; 103 nvidia,function = "rsvd4";
100 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
101 nvidia,tristate = <TEGRA_PIN_ENABLE>; 104 nvidia,tristate = <TEGRA_PIN_ENABLE>;
102 }; 105 };
103 i2c3 { 106
104 nvidia,pins = "dtf"; 107 /* Colibri BL_ON */
105 nvidia,function = "i2c3"; 108 bl-on {
109 nvidia,pins = "dta";
110 nvidia,function = "rsvd1";
106 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 111 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
107 nvidia,tristate = <TEGRA_PIN_ENABLE>; 112 nvidia,tristate = <TEGRA_PIN_ENABLE>;
108 }; 113 };
109 i2cddc { 114
115 /* Colibri Backlight PWM<A>, PWM<B> */
116 pwm-a-b {
117 nvidia,pins = "sdc";
118 nvidia,function = "pwm";
119 nvidia,tristate = <TEGRA_PIN_ENABLE>;
120 };
121
122 /* Colibri DDC */
123 ddc {
110 nvidia,pins = "ddc"; 124 nvidia,pins = "ddc";
111 nvidia,function = "i2c2"; 125 nvidia,function = "i2c2";
112 nvidia,pull = <TEGRA_PIN_PULL_UP>; 126 nvidia,pull = <TEGRA_PIN_PULL_UP>;
113 nvidia,tristate = <TEGRA_PIN_ENABLE>; 127 nvidia,tristate = <TEGRA_PIN_ENABLE>;
114 }; 128 };
115 i2cp { 129
116 nvidia,pins = "i2cp"; 130 /*
117 nvidia,function = "i2cp"; 131 * Colibri EXT_IO*
132 * Note: dtf optionally used for I2C3
133 */
134 ext-io {
135 nvidia,pins = "dtf", "spdi";
136 nvidia,function = "rsvd2";
118 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 137 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
119 nvidia,tristate = <TEGRA_PIN_DISABLE>; 138 nvidia,tristate = <TEGRA_PIN_ENABLE>;
120 }; 139 };
121 irda { 140
122 nvidia,pins = "uad"; 141 /*
123 nvidia,function = "irda"; 142 * Colibri Ethernet (On-module)
143 * ULPI EHCI instance 1 USB2_DP/N -> AX88772B
144 */
145 ulpi {
146 nvidia,pins = "uaa", "uab", "uda";
147 nvidia,function = "ulpi";
124 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 148 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
125 nvidia,tristate = <TEGRA_PIN_ENABLE>; 149 nvidia,tristate = <TEGRA_PIN_DISABLE>;
126 }; 150 };
127 nand { 151 ulpi-refclk {
128 nvidia,pins = "kbca", "kbcc", "kbcd", 152 nvidia,pins = "cdev2";
129 "kbce", "kbcf"; 153 nvidia,function = "pllp_out4";
130 nvidia,function = "nand";
131 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 154 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
132 nvidia,tristate = <TEGRA_PIN_DISABLE>; 155 nvidia,tristate = <TEGRA_PIN_DISABLE>;
133 }; 156 };
134 owc { 157
135 nvidia,pins = "owc"; 158 /* Colibri HOTPLUG_DETECT (HDMI) */
136 nvidia,function = "owr"; 159 hotplug-detect {
160 nvidia,pins = "hdint";
161 nvidia,function = "hdmi";
162 nvidia,tristate = <TEGRA_PIN_ENABLE>;
163 };
164
165 /* Colibri I2C */
166 i2c {
167 nvidia,pins = "rm";
168 nvidia,function = "i2c1";
137 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 169 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
138 nvidia,tristate = <TEGRA_PIN_ENABLE>; 170 nvidia,tristate = <TEGRA_PIN_ENABLE>;
139 }; 171 };
140 pmc { 172
141 nvidia,pins = "pmc"; 173 /*
142 nvidia,function = "pwr_on"; 174 * Colibri L_BIAS, LCD_M1 is muxed with LCD_DE
143 nvidia,tristate = <TEGRA_PIN_DISABLE>; 175 * today's display need DE, disable LCD_M1
176 */
177 lm1 {
178 nvidia,pins = "lm1";
179 nvidia,function = "rsvd3";
180 nvidia,tristate = <TEGRA_PIN_ENABLE>;
144 }; 181 };
145 pwm { 182
146 nvidia,pins = "sdb", "sdc", "sdd"; 183 /* Colibri LCD (L_* resp. LDD<*>) */
147 nvidia,function = "pwm"; 184 lcd {
185 nvidia,pins = "ld0", "ld1", "ld2", "ld3",
186 "ld4", "ld5", "ld6", "ld7",
187 "ld8", "ld9", "ld10", "ld11",
188 "ld12", "ld13", "ld14", "ld15",
189 "ld16", "ld17", "lhs", "lsc0",
190 "lspi", "lvs";
191 nvidia,function = "displaya";
148 nvidia,tristate = <TEGRA_PIN_ENABLE>; 192 nvidia,tristate = <TEGRA_PIN_ENABLE>;
149 }; 193 };
150 sdio4 { 194 /* Colibri LCD (Optional 24 BPP Support) */
151 nvidia,pins = "atb", "gma", "gme"; 195 lcd-24 {
196 nvidia,pins = "ldi", "lhp0", "lhp1", "lhp2",
197 "lpp", "lvp1";
198 nvidia,function = "displaya";
199 nvidia,tristate = <TEGRA_PIN_ENABLE>;
200 };
201
202 /* Colibri MMC */
203 mmc {
204 nvidia,pins = "atb", "gma";
152 nvidia,function = "sdio4"; 205 nvidia,function = "sdio4";
153 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 206 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
154 nvidia,tristate = <TEGRA_PIN_ENABLE>; 207 nvidia,tristate = <TEGRA_PIN_ENABLE>;
155 }; 208 };
156 spi1 { 209
157 nvidia,pins = "spid", "spie", "spif"; 210 /* Colibri MMCCD */
158 nvidia,function = "spi1"; 211 mmccd {
212 nvidia,pins = "gmb";
213 nvidia,function = "gmi_int";
159 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 214 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
160 nvidia,tristate = <TEGRA_PIN_ENABLE>; 215 nvidia,tristate = <TEGRA_PIN_ENABLE>;
161 }; 216 };
162 spi4 { 217
218 /* Colibri MMC (Optional 8-bit) */
219 mmc-8bit {
220 nvidia,pins = "gme";
221 nvidia,function = "sdio4";
222 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
223 nvidia,tristate = <TEGRA_PIN_ENABLE>;
224 };
225
226 /*
227 * Colibri Parallel Camera (Optional)
228 * pins multiplexed with others and therefore disabled
229 * Note: dta used for BL_ON by default
230 */
231 cif-mclk {
232 nvidia,pins = "csus";
233 nvidia,function = "vi_sensor_clk";
234 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
235 nvidia,tristate = <TEGRA_PIN_ENABLE>;
236 };
237 cif {
238 nvidia,pins = "dtb", "dtc", "dtd";
239 nvidia,function = "vi";
240 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
241 nvidia,tristate = <TEGRA_PIN_ENABLE>;
242 };
243
244 /* Colibri PWM<C>, PWM<D> */
245 pwm-c-d {
246 nvidia,pins = "sdb", "sdd";
247 nvidia,function = "pwm";
248 nvidia,tristate = <TEGRA_PIN_ENABLE>;
249 };
250
251 /* Colibri SSP */
252 ssp {
163 nvidia,pins = "slxa", "slxc", "slxd", "slxk"; 253 nvidia,pins = "slxa", "slxc", "slxd", "slxk";
164 nvidia,function = "spi4"; 254 nvidia,function = "spi4";
165 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 255 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
166 nvidia,tristate = <TEGRA_PIN_ENABLE>; 256 nvidia,tristate = <TEGRA_PIN_ENABLE>;
167 }; 257 };
168 uarta { 258
259 /* Colibri UART-A */
260 uart-a {
169 nvidia,pins = "sdio1"; 261 nvidia,pins = "sdio1";
170 nvidia,function = "uarta"; 262 nvidia,function = "uarta";
171 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 263 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
172 nvidia,tristate = <TEGRA_PIN_ENABLE>; 264 nvidia,tristate = <TEGRA_PIN_ENABLE>;
173 }; 265 };
174 uartd { 266 uart-a-dsr {
267 nvidia,pins = "lpw1";
268 nvidia,function = "rsvd3";
269 nvidia,tristate = <TEGRA_PIN_ENABLE>;
270 };
271 uart-a-dcd {
272 nvidia,pins = "lpw2";
273 nvidia,function = "hdmi";
274 nvidia,tristate = <TEGRA_PIN_ENABLE>;
275 };
276
277 /* Colibri UART-B */
278 uart-b {
175 nvidia,pins = "gmc"; 279 nvidia,pins = "gmc";
176 nvidia,function = "uartd"; 280 nvidia,function = "uartd";
177 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 281 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
178 nvidia,tristate = <TEGRA_PIN_ENABLE>; 282 nvidia,tristate = <TEGRA_PIN_ENABLE>;
179 }; 283 };
180 ulpi { 284
181 nvidia,pins = "uaa", "uab", "uda"; 285 /* Colibri UART-C */
182 nvidia,function = "ulpi"; 286 uart-c {
287 nvidia,pins = "uad";
288 nvidia,function = "irda";
289 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
290 nvidia,tristate = <TEGRA_PIN_ENABLE>;
291 };
292
293 /* Colibri USB_CDET */
294 usb-cdet {
295 nvidia,pins = "spdo";
296 nvidia,function = "rsvd2";
297 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
298 nvidia,tristate = <TEGRA_PIN_ENABLE>;
299 };
300
301 /* Colibri USBH_OC */
302 usbh-oc {
303 nvidia,pins = "spih";
304 nvidia,function = "spi2_alt";
305 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
306 nvidia,tristate = <TEGRA_PIN_ENABLE>;
307 };
308
309 /* Colibri USBH_PEN */
310 usbh-pen {
311 nvidia,pins = "spig";
312 nvidia,function = "spi2_alt";
313 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
314 nvidia,tristate = <TEGRA_PIN_ENABLE>;
315 };
316
317 /* Colibri VGA not supported */
318 vga {
319 nvidia,pins = "crtp";
320 nvidia,function = "crt";
321 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
322 nvidia,tristate = <TEGRA_PIN_ENABLE>;
323 };
324
325 /* I2C3 (Optional) */
326 i2c3 {
327 nvidia,pins = "dtf";
328 nvidia,function = "i2c3";
329 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
330 nvidia,tristate = <TEGRA_PIN_ENABLE>;
331 };
332
333 /* JTAG_RTCK */
334 jtag-rtck {
335 nvidia,pins = "gpu7";
336 nvidia,function = "rtck";
337 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
338 nvidia,tristate = <TEGRA_PIN_ENABLE>;
339 };
340
341 /*
342 * LAN_RESET, LAN_EXT_WAKEUP and LAN_PME
343 * (All On-module)
344 */
345 gpio-gpv {
346 nvidia,pins = "gpv";
347 nvidia,function = "rsvd2";
183 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 348 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
184 nvidia,tristate = <TEGRA_PIN_DISABLE>; 349 nvidia,tristate = <TEGRA_PIN_DISABLE>;
185 }; 350 };
186 ulpi_refclk { 351
187 nvidia,pins = "cdev2"; 352 /*
188 nvidia,function = "pllp_out4"; 353 * LAN_V_BUS, VDD_FAULT, BATT_FAULT, WM9712 PENDOWN
354 * (All On-module); Colibri CAN_INT
355 */
356 gpio-dte {
357 nvidia,pins = "dte";
358 nvidia,function = "rsvd1";
189 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 359 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
190 nvidia,tristate = <TEGRA_PIN_DISABLE>; 360 nvidia,tristate = <TEGRA_PIN_DISABLE>;
191 }; 361 };
192 usb_gpio { 362
193 nvidia,pins = "spig", "spih"; 363 /* NAND (On-module) */
194 nvidia,function = "spi2_alt"; 364 nand {
365 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
366 "kbce", "kbcf";
367 nvidia,function = "nand";
195 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 368 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
196 nvidia,tristate = <TEGRA_PIN_DISABLE>; 369 nvidia,tristate = <TEGRA_PIN_DISABLE>;
197 }; 370 };
198 vi { 371
199 nvidia,pins = "dta", "dtb", "dtc", "dtd"; 372 /* Onewire (Optional) */
200 nvidia,function = "vi"; 373 owr {
374 nvidia,pins = "owc";
375 nvidia,function = "owr";
201 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 376 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
202 nvidia,tristate = <TEGRA_PIN_ENABLE>; 377 nvidia,tristate = <TEGRA_PIN_ENABLE>;
203 }; 378 };
204 vi_sc { 379
205 nvidia,pins = "csus"; 380 /* Power I2C (On-module) */
206 nvidia,function = "vi_sensor_clk"; 381 i2cp {
382 nvidia,pins = "i2cp";
383 nvidia,function = "i2cp";
384 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
385 nvidia,tristate = <TEGRA_PIN_DISABLE>;
386 };
387
388 /* RESET_OUT */
389 reset-out {
390 nvidia,pins = "ata";
391 nvidia,function = "gmi";
392 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
393 nvidia,tristate = <TEGRA_PIN_DISABLE>;
394 };
395
396 /*
397 * SPI1 (Optional)
398 * Note: spid and spie used for Colibri Address/Data
399 * Bus (GMI)
400 */
401 spi1 {
402 nvidia,pins = "spid", "spie", "spif";
403 nvidia,function = "spi1";
207 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 404 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
208 nvidia,tristate = <TEGRA_PIN_ENABLE>; 405 nvidia,tristate = <TEGRA_PIN_ENABLE>;
209 }; 406 };
407
408 /*
409 * THERMD_ALERT# (On-module), unlatched I2C address pin
410 * of LM95245 temperature sensor therefore requires
411 * disabling for now
412 */
413 lvp0 {
414 nvidia,pins = "lvp0";
415 nvidia,function = "rsvd3";
416 nvidia,tristate = <TEGRA_PIN_ENABLE>;
417 };
210 }; 418 };
211 }; 419 };
212 420
213 ac97: ac97@70002000 { 421 tegra_ac97: ac97@70002000 {
214 status = "okay"; 422 status = "okay";
215 nvidia,codec-reset-gpio = <&gpio TEGRA_GPIO(V, 0) 423 nvidia,codec-reset-gpio =
216 GPIO_ACTIVE_HIGH>; 424 <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_HIGH>;
217 nvidia,codec-sync-gpio = <&gpio TEGRA_GPIO(P, 0) 425 nvidia,codec-sync-gpio =
218 GPIO_ACTIVE_HIGH>; 426 <&gpio TEGRA_GPIO(P, 0) GPIO_ACTIVE_HIGH>;
427 };
428
429 serial@70006040 {
430 compatible = "nvidia,tegra20-hsuart";
431 };
432
433 serial@70006300 {
434 compatible = "nvidia,tegra20-hsuart";
219 }; 435 };
220 436
221 nand-controller@70008000 { 437 nand-controller@70008000 {
@@ -243,7 +459,7 @@
243 }; 459 };
244 460
245 /* DDC_SCL/SDA on X3 pin 15/16 (e.g. display EDID) */ 461 /* DDC_SCL/SDA on X3 pin 15/16 (e.g. display EDID) */
246 i2c_ddc: i2c@7000c400 { 462 hdmi_ddc: i2c@7000c400 {
247 clock-frequency = <10000>; 463 clock-frequency = <10000>;
248 }; 464 };
249 465
@@ -256,59 +472,45 @@
256 status = "okay"; 472 status = "okay";
257 clock-frequency = <100000>; 473 clock-frequency = <100000>;
258 474
259 pmic: tps6586x@34 { 475 pmic@34 {
260 compatible = "ti,tps6586x"; 476 compatible = "ti,tps6586x";
261 reg = <0x34>; 477 reg = <0x34>;
262 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 478 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
263
264 ti,system-power-controller; 479 ti,system-power-controller;
265
266 #gpio-cells = <2>; 480 #gpio-cells = <2>;
267 gpio-controller; 481 gpio-controller;
268 482 sys-supply = <&reg_module_3v3>;
269 sys-supply = <&vdd_3v3_reg>; 483 vin-sm0-supply = <&reg_3v3_vsys>;
270 vin-sm0-supply = <&sys_reg>; 484 vin-sm1-supply = <&reg_3v3_vsys>;
271 vin-sm1-supply = <&sys_reg>; 485 vin-sm2-supply = <&reg_3v3_vsys>;
272 vin-sm2-supply = <&sys_reg>; 486 vinldo01-supply = <&reg_1v8_vdd_ddr2>;
273 vinldo01-supply = <&sm2_reg>; 487 vinldo23-supply = <&reg_module_3v3>;
274 vinldo23-supply = <&vdd_3v3_reg>; 488 vinldo4-supply = <&reg_module_3v3>;
275 vinldo4-supply = <&vdd_3v3_reg>; 489 vinldo678-supply = <&reg_module_3v3>;
276 vinldo678-supply = <&vdd_3v3_reg>; 490 vinldo9-supply = <&reg_module_3v3>;
277 vinldo9-supply = <&vdd_3v3_reg>;
278 491
279 regulators { 492 regulators {
280 #address-cells = <1>; 493 reg_3v3_vsys: sys {
281 #size-cells = <0>; 494 regulator-name = "VSYS_3.3V";
282
283 sys_reg: regulator@0 {
284 reg = <0>;
285 regulator-compatible = "sys";
286 regulator-name = "vdd_sys";
287 regulator-always-on; 495 regulator-always-on;
288 }; 496 };
289 497
290 regulator@1 { 498 sm0 {
291 reg = <1>; 499 regulator-name = "VDD_CORE_1.2V";
292 regulator-compatible = "sm0";
293 regulator-name = "vdd_sm0,vdd_core";
294 regulator-min-microvolt = <1200000>; 500 regulator-min-microvolt = <1200000>;
295 regulator-max-microvolt = <1200000>; 501 regulator-max-microvolt = <1200000>;
296 regulator-always-on; 502 regulator-always-on;
297 }; 503 };
298 504
299 regulator@2 { 505 sm1 {
300 reg = <2>; 506 regulator-name = "VDD_CPU_1.0V";
301 regulator-compatible = "sm1";
302 regulator-name = "vdd_sm1,vdd_cpu";
303 regulator-min-microvolt = <1000000>; 507 regulator-min-microvolt = <1000000>;
304 regulator-max-microvolt = <1000000>; 508 regulator-max-microvolt = <1000000>;
305 regulator-always-on; 509 regulator-always-on;
306 }; 510 };
307 511
308 sm2_reg: regulator@3 { 512 reg_1v8_vdd_ddr2: sm2 {
309 reg = <3>; 513 regulator-name = "VDD_DDR2_1.8V";
310 regulator-compatible = "sm2";
311 regulator-name = "vdd_sm2,vin_ldo*";
312 regulator-min-microvolt = <1800000>; 514 regulator-min-microvolt = <1800000>;
313 regulator-max-microvolt = <1800000>; 515 regulator-max-microvolt = <1800000>;
314 regulator-always-on; 516 regulator-always-on;
@@ -316,80 +518,68 @@
316 518
317 /* LDO0 is not connected to anything */ 519 /* LDO0 is not connected to anything */
318 520
319 regulator@5 { 521 /*
320 reg = <5>; 522 * +3.3V_ENABLE_N switching via FET:
321 regulator-compatible = "ldo1"; 523 * AVDD_AUDIO_S and +3.3V
322 regulator-name = "vdd_ldo1,avdd_pll*"; 524 * see also +3.3V fixed supply
525 */
526 ldo1 {
527 regulator-name = "AVDD_PLL_1.1V";
323 regulator-min-microvolt = <1100000>; 528 regulator-min-microvolt = <1100000>;
324 regulator-max-microvolt = <1100000>; 529 regulator-max-microvolt = <1100000>;
325 regulator-always-on; 530 regulator-always-on;
326 }; 531 };
327 532
328 regulator@6 { 533 ldo2 {
329 reg = <6>; 534 regulator-name = "VDD_RTC_1.2V";
330 regulator-compatible = "ldo2";
331 regulator-name = "vdd_ldo2,vdd_rtc";
332 regulator-min-microvolt = <1200000>; 535 regulator-min-microvolt = <1200000>;
333 regulator-max-microvolt = <1200000>; 536 regulator-max-microvolt = <1200000>;
334 }; 537 };
335 538
336 /* LDO3 is not connected to anything */ 539 /* LDO3 is not connected to anything */
337 540
338 regulator@8 { 541 ldo4 {
339 reg = <8>; 542 regulator-name = "VDDIO_SYS_1.8V";
340 regulator-compatible = "ldo4";
341 regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
342 regulator-min-microvolt = <1800000>; 543 regulator-min-microvolt = <1800000>;
343 regulator-max-microvolt = <1800000>; 544 regulator-max-microvolt = <1800000>;
344 regulator-always-on; 545 regulator-always-on;
345 }; 546 };
346 547
347 ldo5_reg: regulator@9 { 548 /* Switched via FET from regular +3.3V */
348 reg = <9>; 549 ldo5 {
349 regulator-compatible = "ldo5"; 550 regulator-name = "+3.3V_USB";
350 regulator-name = "vdd_ldo5,vdd_fuse";
351 regulator-min-microvolt = <3300000>; 551 regulator-min-microvolt = <3300000>;
352 regulator-max-microvolt = <3300000>; 552 regulator-max-microvolt = <3300000>;
353 regulator-always-on; 553 regulator-always-on;
354 }; 554 };
355 555
356 regulator@10 { 556 ldo6 {
357 reg = <10>; 557 regulator-name = "AVDD_VDAC_2.85V";
358 regulator-compatible = "ldo6";
359 regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam";
360 regulator-min-microvolt = <2850000>; 558 regulator-min-microvolt = <2850000>;
361 regulator-max-microvolt = <2850000>; 559 regulator-max-microvolt = <2850000>;
362 }; 560 };
363 561
364 hdmi_vdd_reg: regulator@11 { 562 reg_3v3_avdd_hdmi: ldo7 {
365 reg = <11>; 563 regulator-name = "AVDD_HDMI_3.3V";
366 regulator-compatible = "ldo7";
367 regulator-name = "vdd_ldo7,avdd_hdmi";
368 regulator-min-microvolt = <3300000>; 564 regulator-min-microvolt = <3300000>;
369 regulator-max-microvolt = <3300000>; 565 regulator-max-microvolt = <3300000>;
370 }; 566 };
371 567
372 hdmi_pll_reg: regulator@12 { 568 reg_1v8_avdd_hdmi_pll: ldo8 {
373 reg = <12>; 569 regulator-name = "AVDD_HDMI_PLL_1.8V";
374 regulator-compatible = "ldo8";
375 regulator-name = "vdd_ldo8,avdd_hdmi_pll";
376 regulator-min-microvolt = <1800000>; 570 regulator-min-microvolt = <1800000>;
377 regulator-max-microvolt = <1800000>; 571 regulator-max-microvolt = <1800000>;
378 }; 572 };
379 573
380 regulator@13 { 574 ldo9 {
381 reg = <13>; 575 regulator-name = "VDDIO_RX_DDR_2.85V";
382 regulator-compatible = "ldo9";
383 regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
384 regulator-min-microvolt = <2850000>; 576 regulator-min-microvolt = <2850000>;
385 regulator-max-microvolt = <2850000>; 577 regulator-max-microvolt = <2850000>;
386 regulator-always-on; 578 regulator-always-on;
387 }; 579 };
388 580
389 regulator@14 { 581 ldo_rtc {
390 reg = <14>; 582 regulator-name = "VCC_BATT";
391 regulator-compatible = "ldo_rtc";
392 regulator-name = "vdd_rtc_out,vdd_cell";
393 regulator-min-microvolt = <3300000>; 583 regulator-min-microvolt = <3300000>;
394 regulator-max-microvolt = <3300000>; 584 regulator-max-microvolt = <3300000>;
395 regulator-always-on; 585 regulator-always-on;
@@ -397,7 +587,8 @@
397 }; 587 };
398 }; 588 };
399 589
400 temperature-sensor@4c { 590 /* LM95245 temperature sensor */
591 temp-sensor@4c {
401 compatible = "national,lm95245"; 592 compatible = "national,lm95245";
402 reg = <0x4c>; 593 reg = <0x4c>;
403 }; 594 };
@@ -410,6 +601,14 @@
410 nvidia,core-pwr-good-time = <3845 3845>; 601 nvidia,core-pwr-good-time = <3845 3845>;
411 nvidia,core-pwr-off-time = <3875>; 602 nvidia,core-pwr-off-time = <3875>;
412 nvidia,sys-clock-req-active-high; 603 nvidia,sys-clock-req-active-high;
604
605 /* Set SLEEP MODE bit in SUPPLYENE register of TPS658643 PMIC */
606 i2c-thermtrip {
607 nvidia,i2c-controller-id = <3>;
608 nvidia,bus-addr = <0x34>;
609 nvidia,reg-addr = <0x14>;
610 nvidia,reg-data = <0x8>;
611 };
413 }; 612 };
414 613
415 memory-controller@7000f400 { 614 memory-controller@7000f400 {
@@ -483,79 +682,87 @@
483 }; 682 };
484 }; 683 };
485 684
685 /* EHCI instance 1: ULPI PHY -> AX88772B (On-module) */
486 usb@c5004000 { 686 usb@c5004000 {
487 status = "okay"; 687 status = "okay";
488 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) 688 #address-cells = <1>;
489 GPIO_ACTIVE_LOW>; 689 #size-cells = <0>;
690
691 asix@1 {
692 reg = <1>;
693 local-mac-address = [00 00 00 00 00 00];
694 };
490 }; 695 };
491 696
492 usb-phy@c5004000 { 697 usb-phy@c5004000 {
493 status = "okay"; 698 status = "okay";
494 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) 699 nvidia,phy-reset-gpio =
495 GPIO_ACTIVE_LOW>; 700 <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_LOW>;
701 vbus-supply = <&reg_lan_v_bus>;
496 }; 702 };
497 703
498 sdhci@c8000600 { 704 clk32k_in: xtal3 {
499 cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>; 705 compatible = "fixed-clock";
706 #clock-cells = <0>;
707 clock-frequency = <32768>;
500 }; 708 };
501 709
502 clocks { 710 reg_lan_v_bus: regulator-lan-v-bus {
503 compatible = "simple-bus"; 711 compatible = "regulator-fixed";
504 #address-cells = <1>; 712 regulator-name = "LAN_V_BUS";
505 #size-cells = <0>; 713 regulator-min-microvolt = <5000000>;
506 714 regulator-max-microvolt = <5000000>;
507 clk32k_in: clock@0 { 715 enable-active-high;
508 compatible = "fixed-clock"; 716 gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>;
509 reg = <0>;
510 #clock-cells = <0>;
511 clock-frequency = <32768>;
512 };
513 }; 717 };
514 718
515 regulators { 719 reg_module_3v3: regulator-module-3v3 {
516 compatible = "simple-bus"; 720 compatible = "regulator-fixed";
517 #address-cells = <1>; 721 regulator-name = "+V3.3";
518 #size-cells = <0>; 722 regulator-min-microvolt = <3300000>;
519 723 regulator-max-microvolt = <3300000>;
520 vdd_3v3_reg: regulator@100 { 724 regulator-always-on;
521 compatible = "regulator-fixed";
522 reg = <100>;
523 regulator-name = "vdd_3v3";
524 regulator-min-microvolt = <3300000>;
525 regulator-max-microvolt = <3300000>;
526 regulator-always-on;
527 };
528
529 regulator@101 {
530 compatible = "regulator-fixed";
531 reg = <101>;
532 regulator-name = "internal_usb";
533 regulator-min-microvolt = <5000000>;
534 regulator-max-microvolt = <5000000>;
535 enable-active-high;
536 regulator-boot-on;
537 regulator-always-on;
538 gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>;
539 };
540 }; 725 };
541 726
542 sound { 727 sound {
543 compatible = "nvidia,tegra-audio-wm9712-colibri_t20", 728 compatible = "nvidia,tegra-audio-wm9712-colibri_t20",
544 "nvidia,tegra-audio-wm9712"; 729 "nvidia,tegra-audio-wm9712";
545 nvidia,model = "Colibri T20 AC97 Audio"; 730 nvidia,model = "Toradex Colibri T20";
546
547 nvidia,audio-routing = 731 nvidia,audio-routing =
548 "Headphone", "HPOUTL", 732 "Headphone", "HPOUTL",
549 "Headphone", "HPOUTR", 733 "Headphone", "HPOUTR",
550 "LineIn", "LINEINL", 734 "LineIn", "LINEINL",
551 "LineIn", "LINEINR", 735 "LineIn", "LINEINR",
552 "Mic", "MIC1"; 736 "Mic", "MIC1";
553 737 nvidia,ac97-controller = <&tegra_ac97>;
554 nvidia,ac97-controller = <&ac97>;
555
556 clocks = <&tegra_car TEGRA20_CLK_PLL_A>, 738 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
557 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, 739 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
558 <&tegra_car TEGRA20_CLK_CDEV1>; 740 <&tegra_car TEGRA20_CLK_CDEV1>;
559 clock-names = "pll_a", "pll_a_out0", "mclk"; 741 clock-names = "pll_a", "pll_a_out0", "mclk";
560 }; 742 };
561}; 743};
744
745&gpio {
746 lan-reset-n {
747 gpio-hog;
748 gpios = <TEGRA_GPIO(V, 4) GPIO_ACTIVE_HIGH>;
749 output-high;
750 line-name = "LAN_RESET#";
751 };
752
753 /* Tri-stating GMI_WR_N on SODIMM pin 99 nPWE */
754 npwe {
755 gpio-hog;
756 gpios = <TEGRA_GPIO(T, 5) GPIO_ACTIVE_HIGH>;
757 output-high;
758 line-name = "Tri-state nPWE";
759 };
760
761 /* Not tri-stating GMI_WR_N on SODIMM pin 93 RDnWR */
762 rdnwr {
763 gpio-hog;
764 gpios = <TEGRA_GPIO(T, 6) GPIO_ACTIVE_HIGH>;
765 output-low;
766 line-name = "Not tri-state RDnWR";
767 };
768};
diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts
index ef245291924f..8861e0976e37 100644
--- a/arch/arm/boot/dts/tegra20-paz00.dts
+++ b/arch/arm/boot/dts/tegra20-paz00.dts
@@ -303,7 +303,7 @@
303 request-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; 303 request-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
304 slave-addr = <138>; 304 slave-addr = <138>;
305 clocks = <&tegra_car TEGRA20_CLK_I2C3>, 305 clocks = <&tegra_car TEGRA20_CLK_I2C3>,
306 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; 306 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
307 clock-names = "div-clk", "fast-clk"; 307 clock-names = "div-clk", "fast-clk";
308 resets = <&tegra_car 67>; 308 resets = <&tegra_car 67>;
309 reset-names = "i2c"; 309 reset-names = "i2c";
@@ -524,10 +524,10 @@
524 gpio-keys { 524 gpio-keys {
525 compatible = "gpio-keys"; 525 compatible = "gpio-keys";
526 526
527 power { 527 wakeup {
528 label = "Power"; 528 label = "Wakeup";
529 gpios = <&gpio TEGRA_GPIO(J, 7) GPIO_ACTIVE_LOW>; 529 gpios = <&gpio TEGRA_GPIO(J, 7) GPIO_ACTIVE_LOW>;
530 linux,code = <KEY_POWER>; 530 linux,code = <KEY_WAKEUP>;
531 wakeup-source; 531 wakeup-source;
532 }; 532 };
533 }; 533 };
@@ -599,8 +599,8 @@
599 GPIO_ACTIVE_HIGH>; 599 GPIO_ACTIVE_HIGH>;
600 600
601 clocks = <&tegra_car TEGRA20_CLK_PLL_A>, 601 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
602 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, 602 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
603 <&tegra_car TEGRA20_CLK_CDEV1>; 603 <&tegra_car TEGRA20_CLK_CDEV1>;
604 clock-names = "pll_a", "pll_a_out0", "mclk"; 604 clock-names = "pll_a", "pll_a_out0", "mclk";
605 }; 605 };
606}; 606};
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 15b73bd377f0..20869757d32f 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -419,19 +419,6 @@
419 status = "disabled"; 419 status = "disabled";
420 }; 420 };
421 421
422 gmi@70009000 {
423 compatible = "nvidia,tegra20-gmi";
424 reg = <0x70009000 0x1000>;
425 #address-cells = <2>;
426 #size-cells = <1>;
427 ranges = <0 0 0xd0000000 0xfffffff>;
428 clocks = <&tegra_car TEGRA20_CLK_NOR>;
429 clock-names = "gmi";
430 resets = <&tegra_car 42>;
431 reset-names = "gmi";
432 status = "disabled";
433 };
434
435 nand-controller@70008000 { 422 nand-controller@70008000 {
436 compatible = "nvidia,tegra20-nand"; 423 compatible = "nvidia,tegra20-nand";
437 reg = <0x70008000 0x100>; 424 reg = <0x70008000 0x100>;
@@ -447,6 +434,19 @@
447 status = "disabled"; 434 status = "disabled";
448 }; 435 };
449 436
437 gmi@70009000 {
438 compatible = "nvidia,tegra20-gmi";
439 reg = <0x70009000 0x1000>;
440 #address-cells = <2>;
441 #size-cells = <1>;
442 ranges = <0 0 0xd0000000 0xfffffff>;
443 clocks = <&tegra_car TEGRA20_CLK_NOR>;
444 clock-names = "gmi";
445 resets = <&tegra_car 42>;
446 reset-names = "gmi";
447 status = "disabled";
448 };
449
450 pwm: pwm@7000a000 { 450 pwm: pwm@7000a000 {
451 compatible = "nvidia,tegra20-pwm"; 451 compatible = "nvidia,tegra20-pwm";
452 reg = <0x7000a000 0x100>; 452 reg = <0x7000a000 0x100>;
@@ -865,5 +865,7 @@
865 compatible = "arm,cortex-a9-pmu"; 865 compatible = "arm,cortex-a9-pmu";
866 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 866 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
867 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 867 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
868 interrupt-affinity = <&{/cpus/cpu@0}>,
869 <&{/cpus/cpu@1}>;
868 }; 870 };
869}; 871};
diff --git a/arch/arm/boot/dts/tegra30-apalis-eval.dts b/arch/arm/boot/dts/tegra30-apalis-eval.dts
index 0dc85a20bd45..749fc6d1ff70 100644
--- a/arch/arm/boot/dts/tegra30-apalis-eval.dts
+++ b/arch/arm/boot/dts/tegra30-apalis-eval.dts
@@ -6,11 +6,12 @@
6 6
7/ { 7/ {
8 model = "Toradex Apalis T30 on Apalis Evaluation Board"; 8 model = "Toradex Apalis T30 on Apalis Evaluation Board";
9 compatible = "toradex,apalis_t30-eval", "toradex,apalis_t30", "nvidia,tegra30"; 9 compatible = "toradex,apalis_t30-eval", "toradex,apalis_t30",
10 "nvidia,tegra30";
10 11
11 aliases { 12 aliases {
12 rtc0 = "/i2c@7000c000/rtc@68"; 13 rtc0 = "/i2c@7000c000/rtc@68";
13 rtc1 = "/i2c@7000d000/tps65911@2d"; 14 rtc1 = "/i2c@7000d000/pmic@2d";
14 rtc2 = "/rtc@7000e000"; 15 rtc2 = "/rtc@7000e000";
15 serial0 = &uarta; 16 serial0 = &uarta;
16 serial1 = &uartb; 17 serial1 = &uartb;
@@ -23,8 +24,6 @@
23 }; 24 };
24 25
25 pcie@3000 { 26 pcie@3000 {
26 status = "okay";
27
28 pci@1,0 { 27 pci@1,0 {
29 status = "okay"; 28 status = "okay";
30 }; 29 };
@@ -32,10 +31,6 @@
32 pci@2,0 { 31 pci@2,0 {
33 status = "okay"; 32 status = "okay";
34 }; 33 };
35
36 pci@3,0 {
37 status = "okay";
38 };
39 }; 34 };
40 35
41 host1x@50000000 { 36 host1x@50000000 {
@@ -45,27 +40,30 @@
45 nvidia,panel = <&panel>; 40 nvidia,panel = <&panel>;
46 }; 41 };
47 }; 42 };
43
48 hdmi@54280000 { 44 hdmi@54280000 {
49 status = "okay"; 45 status = "okay";
46 hdmi-supply = <&reg_5v0>;
50 }; 47 };
51 }; 48 };
52 49
50 /* Apalis UART1 */
53 serial@70006000 { 51 serial@70006000 {
54 status = "okay"; 52 status = "okay";
55 }; 53 };
56 54
55 /* Apalis UART2 */
57 serial@70006040 { 56 serial@70006040 {
58 compatible = "nvidia,tegra30-hsuart";
59 status = "okay"; 57 status = "okay";
60 }; 58 };
61 59
60 /* Apalis UART3 */
62 serial@70006200 { 61 serial@70006200 {
63 compatible = "nvidia,tegra30-hsuart";
64 status = "okay"; 62 status = "okay";
65 }; 63 };
66 64
65 /* Apalis UART4 */
67 serial@70006300 { 66 serial@70006300 {
68 compatible = "nvidia,tegra30-hsuart";
69 status = "okay"; 67 status = "okay";
70 }; 68 };
71 69
@@ -99,13 +97,13 @@
99 * CAM_I2C: I2C3_SDA/SCL on MXM3 pin 201/203 (e.g. camera sensor on 97 * CAM_I2C: I2C3_SDA/SCL on MXM3 pin 201/203 (e.g. camera sensor on
100 * carrier board) 98 * carrier board)
101 */ 99 */
102 cami2c: i2c@7000c500 { 100 i2c@7000c500 {
103 status = "okay"; 101 status = "okay";
104 clock-frequency = <400000>; 102 clock-frequency = <400000>;
105 }; 103 };
106 104
107 /* DDC: I2C2_SDA/SCL on MXM3 pin 205/207 (e.g. display EDID) */ 105 /* DDC: I2C2_SDA/SCL on MXM3 pin 205/207 (e.g. display EDID) */
108 hdmiddc: i2c@7000c700 { 106 i2c@7000c700 {
109 status = "okay"; 107 status = "okay";
110 }; 108 };
111 109
@@ -113,29 +111,16 @@
113 spi@7000d400 { 111 spi@7000d400 {
114 status = "okay"; 112 status = "okay";
115 spi-max-frequency = <25000000>; 113 spi-max-frequency = <25000000>;
116 spidev0: spidev@1 {
117 compatible = "spidev";
118 reg = <1>;
119 spi-max-frequency = <25000000>;
120 };
121 }; 114 };
122 115
123 /* SPI5: Apalis SPI2 */ 116 /* SPI5: Apalis SPI2 */
124 spi@7000dc00 { 117 spi@7000dc00 {
125 status = "okay"; 118 status = "okay";
126 spi-max-frequency = <25000000>; 119 spi-max-frequency = <25000000>;
127 spidev1: spidev@2 {
128 compatible = "spidev";
129 reg = <2>;
130 spi-max-frequency = <25000000>;
131 };
132 };
133
134 hda@70030000 {
135 status = "okay";
136 }; 120 };
137 121
138 sd1: sdhci@78000000 { 122 /* Apalis SD1 */
123 sdhci@78000000 {
139 status = "okay"; 124 status = "okay";
140 bus-width = <4>; 125 bus-width = <4>;
141 /* SD1_CD# */ 126 /* SD1_CD# */
@@ -143,7 +128,8 @@
143 no-1-8-v; 128 no-1-8-v;
144 }; 129 };
145 130
146 mmc1: sdhci@78000400 { 131 /* Apalis MMC1 */
132 sdhci@78000400 {
147 status = "okay"; 133 status = "okay";
148 bus-width = <8>; 134 bus-width = <8>;
149 /* MMC1_CD# */ 135 /* MMC1_CD# */
@@ -154,12 +140,12 @@
154 /* EHCI instance 0: USB1_DP/N -> USBO1_DP/N */ 140 /* EHCI instance 0: USB1_DP/N -> USBO1_DP/N */
155 usb@7d000000 { 141 usb@7d000000 {
156 status = "okay"; 142 status = "okay";
143 dr_mode = "otg";
157 }; 144 };
158 145
159 usb-phy@7d000000 { 146 usb-phy@7d000000 {
160 status = "okay"; 147 status = "okay";
161 dr_mode = "otg"; 148 vbus-supply = <&reg_usbo1_vbus>;
162 vbus-supply = <&usbo1_vbus_reg>;
163 }; 149 };
164 150
165 /* EHCI instance 1: USB2_DP/N -> USBH2_DP/N */ 151 /* EHCI instance 1: USB2_DP/N -> USBH2_DP/N */
@@ -169,7 +155,7 @@
169 155
170 usb-phy@7d004000 { 156 usb-phy@7d004000 {
171 status = "okay"; 157 status = "okay";
172 vbus-supply = <&usbh_vbus_reg>; 158 vbus-supply = <&reg_usbh_vbus>;
173 }; 159 };
174 160
175 /* EHCI instance 2: USB3_DP/N -> USBH3_DP/N */ 161 /* EHCI instance 2: USB3_DP/N -> USBH3_DP/N */
@@ -179,18 +165,17 @@
179 165
180 usb-phy@7d008000 { 166 usb-phy@7d008000 {
181 status = "okay"; 167 status = "okay";
182 vbus-supply = <&usbh_vbus_reg>; 168 vbus-supply = <&reg_usbh_vbus>;
183 }; 169 };
184 170
185 backlight: backlight { 171 backlight: backlight {
186 compatible = "pwm-backlight"; 172 compatible = "pwm-backlight";
187
188 /* PWM_BKL1 */
189 pwms = <&pwm 0 5000000>;
190 brightness-levels = <255 231 223 207 191 159 127 0>; 173 brightness-levels = <255 231 223 207 191 159 127 0>;
191 default-brightness-level = <6>; 174 default-brightness-level = <6>;
192 /* BKL1_ON */ 175 /* BKL1_ON */
193 enable-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; 176 enable-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
177 power-supply = <&reg_3v3>;
178 pwms = <&pwm 0 5000000>; /* BKL1_PWM */
194 }; 179 };
195 180
196 gpio-keys { 181 gpio-keys {
@@ -211,64 +196,53 @@
211 * edt,et070080dh6: EDT 7.0" LCD TFT 196 * edt,et070080dh6: EDT 7.0" LCD TFT
212 */ 197 */
213 compatible = "edt,et057090dhu", "simple-panel"; 198 compatible = "edt,et057090dhu", "simple-panel";
214
215 backlight = <&backlight>; 199 backlight = <&backlight>;
200 power-supply = <&reg_3v3>;
216 }; 201 };
217 202
218 pwmleds { 203 reg_3v3: regulator-3v3 {
219 compatible = "pwm-leds"; 204 compatible = "regulator-fixed";
220 205 regulator-name = "3.3V_SW";
221 pwm1 { 206 regulator-min-microvolt = <3300000>;
222 label = "PWM1"; 207 regulator-max-microvolt = <3300000>;
223 pwms = <&pwm 3 19600>; 208 };
224 max-brightness = <255>;
225 };
226
227 pwm2 {
228 label = "PWM2";
229 pwms = <&pwm 2 19600>;
230 max-brightness = <255>;
231 };
232 209
233 pwm3 { 210 reg_5v0: regulator-5v0 {
234 label = "PWM3"; 211 compatible = "regulator-fixed";
235 pwms = <&pwm 1 19600>; 212 regulator-name = "5V_SW";
236 max-brightness = <255>; 213 regulator-min-microvolt = <5000000>;
237 }; 214 regulator-max-microvolt = <5000000>;
238 }; 215 };
239 216
240 regulators { 217 /* USBO1_EN */
241 sys_5v0_reg: regulator@1 { 218 reg_usbo1_vbus: regulator-usbo1-vbus {
242 compatible = "regulator-fixed"; 219 compatible = "regulator-fixed";
243 reg = <1>; 220 regulator-name = "VCC_USBO1";
244 regulator-name = "5v0"; 221 regulator-min-microvolt = <5000000>;
245 regulator-min-microvolt = <5000000>; 222 regulator-max-microvolt = <5000000>;
246 regulator-max-microvolt = <5000000>; 223 gpio = <&gpio TEGRA_GPIO(T, 5) GPIO_ACTIVE_HIGH>;
247 regulator-always-on; 224 enable-active-high;
248 }; 225 vin-supply = <&reg_5v0>;
226 };
249 227
250 /* USBO1_EN */ 228 /* USBH_EN */
251 usbo1_vbus_reg: regulator@2 { 229 reg_usbh_vbus: regulator-usbh-vbus {
252 compatible = "regulator-fixed"; 230 compatible = "regulator-fixed";
253 reg = <2>; 231 regulator-name = "VCC_USBH(2A|2C|2D|3|4)";
254 regulator-name = "usbo1_vbus"; 232 regulator-min-microvolt = <5000000>;
255 regulator-min-microvolt = <5000000>; 233 regulator-max-microvolt = <5000000>;
256 regulator-max-microvolt = <5000000>; 234 gpio = <&gpio TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>;
257 gpio = <&gpio TEGRA_GPIO(T, 5) GPIO_ACTIVE_HIGH>; 235 enable-active-high;
258 enable-active-high; 236 vin-supply = <&reg_5v0>;
259 vin-supply = <&sys_5v0_reg>; 237 };
260 }; 238};
261 239
262 /* USBH_EN */ 240&gpio {
263 usbh_vbus_reg: regulator@3 { 241 /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */
264 compatible = "regulator-fixed"; 242 pex-perst-n {
265 reg = <3>; 243 gpio-hog;
266 regulator-name = "usbh_vbus"; 244 gpios = <TEGRA_GPIO(S, 7) GPIO_ACTIVE_HIGH>;
267 regulator-min-microvolt = <5000000>; 245 output-high;
268 regulator-max-microvolt = <5000000>; 246 line-name = "PEX_PERST_N";
269 gpio = <&gpio TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>;
270 enable-active-high;
271 vin-supply = <&sys_5v0_reg>;
272 };
273 }; 247 };
274}; 248};
diff --git a/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts b/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts
new file mode 100644
index 000000000000..0be50e881684
--- /dev/null
+++ b/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts
@@ -0,0 +1,266 @@
1// SPDX-License-Identifier: GPL-2.0 OR MIT
2/dts-v1/;
3
4#include <dt-bindings/input/input.h>
5#include "tegra30-apalis-v1.1.dtsi"
6
7/ {
8 model = "Toradex Apalis T30 on Apalis Evaluation Board";
9 compatible = "toradex,apalis_t30-v1.1-eval", "toradex,apalis_t30-eval",
10 "toradex,apalis_t30-v1.1", "toradex,apalis_t30",
11 "nvidia,tegra30";
12
13 aliases {
14 rtc0 = "/i2c@7000c000/rtc@68";
15 rtc1 = "/i2c@7000d000/pmic@2d";
16 rtc2 = "/rtc@7000e000";
17 serial0 = &uarta;
18 serial1 = &uartb;
19 serial2 = &uartc;
20 serial3 = &uartd;
21 };
22
23 chosen {
24 stdout-path = "serial0:115200n8";
25 };
26
27 pcie@3000 {
28 pci@1,0 {
29 status = "okay";
30 };
31
32 pci@2,0 {
33 status = "okay";
34 };
35 };
36
37 host1x@50000000 {
38 dc@54200000 {
39 rgb {
40 status = "okay";
41 nvidia,panel = <&panel>;
42 };
43 };
44
45 hdmi@54280000 {
46 status = "okay";
47 hdmi-supply = <&reg_5v0>;
48 };
49 };
50
51 /* Apalis UART1 */
52 serial@70006000 {
53 status = "okay";
54 };
55
56 /* Apalis UART2 */
57 serial@70006040 {
58 status = "okay";
59 };
60
61 /* Apalis UART3 */
62 serial@70006200 {
63 status = "okay";
64 };
65
66 /* Apalis UART4 */
67 serial@70006300 {
68 status = "okay";
69 };
70
71 pwm@7000a000 {
72 status = "okay";
73 };
74
75 /*
76 * GEN1_I2C: I2C1_SDA/SCL on MXM3 pin 209/211 (e.g. RTC on carrier
77 * board)
78 */
79 i2c@7000c000 {
80 status = "okay";
81 clock-frequency = <400000>;
82
83 pcie-switch@58 {
84 compatible = "plx,pex8605";
85 reg = <0x58>;
86 };
87
88 /* M41T0M6 real time clock on carrier board */
89 rtc@68 {
90 compatible = "st,m41t0";
91 reg = <0x68>;
92 };
93 };
94
95 /* GEN2_I2C: unused */
96
97 /*
98 * CAM_I2C: I2C3_SDA/SCL on MXM3 pin 201/203 (e.g. camera sensor on
99 * carrier board)
100 */
101 i2c@7000c500 {
102 status = "okay";
103 clock-frequency = <400000>;
104 };
105
106 /* DDC: I2C2_SDA/SCL on MXM3 pin 205/207 (e.g. display EDID) */
107 i2c@7000c700 {
108 status = "okay";
109 };
110
111 /* SPI1: Apalis SPI1 */
112 spi@7000d400 {
113 status = "okay";
114 spi-max-frequency = <25000000>;
115 };
116
117 /* SPI5: Apalis SPI2 */
118 spi@7000dc00 {
119 status = "okay";
120 spi-max-frequency = <25000000>;
121 };
122
123 /* Apalis SD1 */
124 sdhci@78000000 {
125 status = "okay";
126 bus-width = <4>;
127 /* SD1_CD# */
128 cd-gpios = <&gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_LOW>;
129 no-1-8-v;
130 };
131
132 /* Apalis MMC1 */
133 sdhci@78000400 {
134 status = "okay";
135 bus-width = <8>;
136 /* MMC1_CD# */
137 cd-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>;
138 vqmmc-supply = <&reg_vddio_sdmmc3>;
139 };
140
141 /* EHCI instance 0: USB1_DP/N -> USBO1_DP/N */
142 usb@7d000000 {
143 status = "okay";
144 dr_mode = "otg";
145 };
146
147 usb-phy@7d000000 {
148 status = "okay";
149 vbus-supply = <&reg_usbo1_vbus>;
150 };
151
152 /* EHCI instance 1: USB2_DP/N -> USBH2_DP/N */
153 usb@7d004000 {
154 status = "okay";
155 };
156
157 usb-phy@7d004000 {
158 status = "okay";
159 vbus-supply = <&reg_usbh_vbus>;
160 };
161
162 /* EHCI instance 2: USB3_DP/N -> USBH3_DP/N */
163 usb@7d008000 {
164 status = "okay";
165 };
166
167 usb-phy@7d008000 {
168 status = "okay";
169 vbus-supply = <&reg_usbh_vbus>;
170 };
171
172 backlight: backlight {
173 compatible = "pwm-backlight";
174 brightness-levels = <255 231 223 207 191 159 127 0>;
175 default-brightness-level = <6>;
176 /* BKL1_ON */
177 enable-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
178 power-supply = <&reg_3v3>;
179 pwms = <&pwm 0 5000000>; /* BKL1_PWM */
180 };
181
182 gpio-keys {
183 compatible = "gpio-keys";
184
185 wakeup {
186 label = "WAKE1_MICO";
187 gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_LOW>;
188 linux,code = <KEY_WAKEUP>;
189 debounce-interval = <10>;
190 wakeup-source;
191 };
192 };
193
194 panel: panel {
195 /*
196 * edt,et057090dhu: EDT 5.7" LCD TFT
197 * edt,et070080dh6: EDT 7.0" LCD TFT
198 */
199 compatible = "edt,et057090dhu", "simple-panel";
200 backlight = <&backlight>;
201 power-supply = <&reg_3v3>;
202 };
203
204 reg_3v3: regulator-3v3 {
205 compatible = "regulator-fixed";
206 regulator-name = "3.3V_SW";
207 regulator-min-microvolt = <3300000>;
208 regulator-max-microvolt = <3300000>;
209 };
210
211 reg_5v0: regulator-5v0 {
212 compatible = "regulator-fixed";
213 regulator-name = "5V_SW";
214 regulator-min-microvolt = <5000000>;
215 regulator-max-microvolt = <5000000>;
216 };
217
218 /* USBO1_EN */
219 reg_usbo1_vbus: regulator-usbo1-vbus {
220 compatible = "regulator-fixed";
221 regulator-name = "VCC_USBO1";
222 regulator-min-microvolt = <5000000>;
223 regulator-max-microvolt = <5000000>;
224 gpio = <&gpio TEGRA_GPIO(T, 5) GPIO_ACTIVE_HIGH>;
225 enable-active-high;
226 vin-supply = <&reg_5v0>;
227 };
228
229 /* USBH_EN */
230 reg_usbh_vbus: regulator-usbh-vbus {
231 compatible = "regulator-fixed";
232 regulator-name = "VCC_USBH(2A|2C|2D|3|4)";
233 regulator-min-microvolt = <5000000>;
234 regulator-max-microvolt = <5000000>;
235 gpio = <&gpio TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>;
236 enable-active-high;
237 vin-supply = <&reg_5v0>;
238 };
239
240 /*
241 * 1.8 volt resp. 3.3 volt VDDIO_SDMMC3 depending on
242 * EN_+3.3_SDMMC3 GPIO
243 */
244 reg_vddio_sdmmc3: regulator-vddio-sdmmc3 {
245 compatible = "regulator-gpio";
246 regulator-name = "VDDIO_SDMMC3";
247 regulator-min-microvolt = <1800000>;
248 regulator-max-microvolt = <3300000>;
249 regulator-type = "voltage";
250 gpios = <&gpio TEGRA_GPIO(J, 5) GPIO_ACTIVE_HIGH>;
251 states = <1800000 0x0
252 3300000 0x1>;
253 startup-delay-us = <100000>;
254 vin-supply = <&vddio_sdmmc_1v8_reg>;
255 };
256};
257
258&gpio {
259 /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */
260 pex-perst-n {
261 gpio-hog;
262 gpios = <TEGRA_GPIO(S, 7) GPIO_ACTIVE_HIGH>;
263 output-high;
264 line-name = "PEX_PERST_N";
265 };
266};
diff --git a/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi b/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi
new file mode 100644
index 000000000000..02f8126481a2
--- /dev/null
+++ b/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi
@@ -0,0 +1,1189 @@
1// SPDX-License-Identifier: GPL-2.0 OR MIT
2#include "tegra30.dtsi"
3
4/*
5 * Toradex Apalis T30 Module Device Tree
6 * Compatible for Revisions 1GB: V1.1A, V1.1B; 1GB IT: V1.1A, V1.1B;
7 * 2GB: V1.1A, V1.1B
8 */
9/ {
10 memory@80000000 {
11 reg = <0x80000000 0x40000000>;
12 };
13
14 pcie@3000 {
15 status = "okay";
16 avdd-pexa-supply = <&vdd2_reg>;
17 avdd-pexb-supply = <&vdd2_reg>;
18 avdd-pex-pll-supply = <&vdd2_reg>;
19 avdd-plle-supply = <&ldo6_reg>;
20 hvdd-pex-supply = <&reg_module_3v3>;
21 vddio-pex-ctl-supply = <&reg_module_3v3>;
22 vdd-pexa-supply = <&vdd2_reg>;
23 vdd-pexb-supply = <&vdd2_reg>;
24
25 /* Apalis type specific */
26 pci@1,0 {
27 nvidia,num-lanes = <4>;
28 };
29
30 /* Apalis PCIe */
31 pci@2,0 {
32 nvidia,num-lanes = <1>;
33 };
34
35 /* I210/I211 Gigabit Ethernet Controller (on-module) */
36 pci@3,0 {
37 status = "okay";
38 nvidia,num-lanes = <1>;
39
40 pcie@0 {
41 reg = <0 0 0 0 0>;
42 local-mac-address = [00 00 00 00 00 00];
43 };
44 };
45 };
46
47 host1x@50000000 {
48 hdmi@54280000 {
49 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
50 nvidia,hpd-gpio =
51 <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
52 pll-supply = <&reg_1v8_avdd_hdmi_pll>;
53 vdd-supply = <&reg_3v3_avdd_hdmi>;
54 };
55 };
56
57 pinmux@70000868 {
58 pinctrl-names = "default";
59 pinctrl-0 = <&state_default>;
60
61 state_default: pinmux {
62 /* Analogue Audio (On-module) */
63 clk1-out-pw4 {
64 nvidia,pins = "clk1_out_pw4";
65 nvidia,function = "extperiph1";
66 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
67 nvidia,tristate = <TEGRA_PIN_DISABLE>;
68 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
69 };
70 dap3-fs-pp0 {
71 nvidia,pins = "dap3_fs_pp0",
72 "dap3_sclk_pp3",
73 "dap3_din_pp1",
74 "dap3_dout_pp2";
75 nvidia,function = "i2s2";
76 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
77 nvidia,tristate = <TEGRA_PIN_DISABLE>;
78 };
79
80 /* Apalis BKL1_ON */
81 pv2 {
82 nvidia,pins = "pv2";
83 nvidia,function = "rsvd4";
84 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
85 nvidia,tristate = <TEGRA_PIN_DISABLE>;
86 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
87 };
88
89 /* Apalis BKL1_PWM */
90 uart3-rts-n-pc0 {
91 nvidia,pins = "uart3_rts_n_pc0";
92 nvidia,function = "pwm0";
93 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
94 nvidia,tristate = <TEGRA_PIN_DISABLE>;
95 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
96 };
97 /* BKL1_PWM_EN#, disable TPS65911 PMIC PWM backlight */
98 uart3-cts-n-pa1 {
99 nvidia,pins = "uart3_cts_n_pa1";
100 nvidia,function = "rsvd2";
101 nvidia,pull = <TEGRA_PIN_PULL_UP>;
102 nvidia,tristate = <TEGRA_PIN_DISABLE>;
103 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
104 };
105
106 /* Apalis CAN1 on SPI6 */
107 spi2-cs0-n-px3 {
108 nvidia,pins = "spi2_cs0_n_px3",
109 "spi2_miso_px1",
110 "spi2_mosi_px0",
111 "spi2_sck_px2";
112 nvidia,function = "spi6";
113 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
114 nvidia,tristate = <TEGRA_PIN_DISABLE>;
115 };
116 /* CAN_INT1 */
117 spi2-cs1-n-pw2 {
118 nvidia,pins = "spi2_cs1_n_pw2";
119 nvidia,function = "spi3";
120 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
121 nvidia,tristate = <TEGRA_PIN_DISABLE>;
122 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
123 };
124
125 /* Apalis CAN2 on SPI4 */
126 gmi-a16-pj7 {
127 nvidia,pins = "gmi_a16_pj7",
128 "gmi_a17_pb0",
129 "gmi_a18_pb1",
130 "gmi_a19_pk7";
131 nvidia,function = "spi4";
132 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
133 nvidia,tristate = <TEGRA_PIN_DISABLE>;
134 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
135 };
136 /* CAN_INT2 */
137 spi2-cs2-n-pw3 {
138 nvidia,pins = "spi2_cs2_n_pw3";
139 nvidia,function = "spi3";
140 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
141 nvidia,tristate = <TEGRA_PIN_DISABLE>;
142 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
143 };
144
145 /* Apalis Digital Audio */
146 clk1-req-pee2 {
147 nvidia,pins = "clk1_req_pee2";
148 nvidia,function = "hda";
149 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
150 nvidia,tristate = <TEGRA_PIN_DISABLE>;
151 };
152 clk2-out-pw5 {
153 nvidia,pins = "clk2_out_pw5";
154 nvidia,function = "extperiph2";
155 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
156 nvidia,tristate = <TEGRA_PIN_DISABLE>;
157 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
158 };
159 dap1-fs-pn0 {
160 nvidia,pins = "dap1_fs_pn0",
161 "dap1_din_pn1",
162 "dap1_dout_pn2",
163 "dap1_sclk_pn3";
164 nvidia,function = "hda";
165 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
166 nvidia,tristate = <TEGRA_PIN_DISABLE>;
167 };
168
169 /* Apalis GPIO */
170 kb-col0-pq0 {
171 nvidia,pins = "kb_col0_pq0",
172 "kb_col1_pq1",
173 "kb_row10_ps2",
174 "kb_row11_ps3",
175 "kb_row12_ps4",
176 "kb_row13_ps5",
177 "kb_row14_ps6",
178 "kb_row15_ps7";
179 nvidia,function = "kbc";
180 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
181 nvidia,tristate = <TEGRA_PIN_DISABLE>;
182 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
183 };
184 /* Multiplexed and therefore disabled */
185 owr {
186 nvidia,pins = "owr";
187 nvidia,function = "rsvd3";
188 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
189 nvidia,tristate = <TEGRA_PIN_ENABLE>;
190 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
191 };
192
193 /* Apalis HDMI1 */
194 hdmi-cec-pee3 {
195 nvidia,pins = "hdmi_cec_pee3";
196 nvidia,function = "cec";
197 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
198 nvidia,tristate = <TEGRA_PIN_DISABLE>;
199 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
200 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
201 };
202 hdmi-int-pn7 {
203 nvidia,pins = "hdmi_int_pn7";
204 nvidia,function = "hdmi";
205 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
206 nvidia,tristate = <TEGRA_PIN_ENABLE>;
207 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
208 };
209
210 /* Apalis I2C1 */
211 gen1-i2c-scl-pc4 {
212 nvidia,pins = "gen1_i2c_scl_pc4",
213 "gen1_i2c_sda_pc5";
214 nvidia,function = "i2c1";
215 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
216 nvidia,tristate = <TEGRA_PIN_DISABLE>;
217 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
218 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
219 };
220
221 /* Apalis I2C2 (DDC) */
222 ddc-scl-pv4 {
223 nvidia,pins = "ddc_scl_pv4",
224 "ddc_sda_pv5";
225 nvidia,function = "i2c4";
226 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
227 nvidia,tristate = <TEGRA_PIN_DISABLE>;
228 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
229 };
230
231 /* Apalis I2C3 (CAM) */
232 cam-i2c-scl-pbb1 {
233 nvidia,pins = "cam_i2c_scl_pbb1",
234 "cam_i2c_sda_pbb2";
235 nvidia,function = "i2c3";
236 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
237 nvidia,tristate = <TEGRA_PIN_DISABLE>;
238 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
239 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
240 };
241
242 /* Apalis LCD1 */
243 lcd-d0-pe0 {
244 nvidia,pins = "lcd_d0_pe0",
245 "lcd_d1_pe1",
246 "lcd_d2_pe2",
247 "lcd_d3_pe3",
248 "lcd_d4_pe4",
249 "lcd_d5_pe5",
250 "lcd_d6_pe6",
251 "lcd_d7_pe7",
252 "lcd_d8_pf0",
253 "lcd_d9_pf1",
254 "lcd_d10_pf2",
255 "lcd_d11_pf3",
256 "lcd_d12_pf4",
257 "lcd_d13_pf5",
258 "lcd_d14_pf6",
259 "lcd_d15_pf7",
260 "lcd_d16_pm0",
261 "lcd_d17_pm1",
262 "lcd_d18_pm2",
263 "lcd_d19_pm3",
264 "lcd_d20_pm4",
265 "lcd_d21_pm5",
266 "lcd_d22_pm6",
267 "lcd_d23_pm7",
268 "lcd_de_pj1",
269 "lcd_hsync_pj3",
270 "lcd_pclk_pb3",
271 "lcd_vsync_pj4";
272 nvidia,function = "displaya";
273 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
274 nvidia,tristate = <TEGRA_PIN_DISABLE>;
275 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
276 };
277
278 /* Apalis MMC1 */
279 sdmmc3-clk-pa6 {
280 nvidia,pins = "sdmmc3_clk_pa6";
281 nvidia,function = "sdmmc3";
282 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
283 nvidia,tristate = <TEGRA_PIN_DISABLE>;
284 };
285 sdmmc3-dat0-pb7 {
286 nvidia,pins = "sdmmc3_cmd_pa7",
287 "sdmmc3_dat0_pb7",
288 "sdmmc3_dat1_pb6",
289 "sdmmc3_dat2_pb5",
290 "sdmmc3_dat3_pb4",
291 "sdmmc3_dat4_pd1",
292 "sdmmc3_dat5_pd0",
293 "sdmmc3_dat6_pd3",
294 "sdmmc3_dat7_pd4";
295 nvidia,function = "sdmmc3";
296 nvidia,pull = <TEGRA_PIN_PULL_UP>;
297 nvidia,tristate = <TEGRA_PIN_DISABLE>;
298 };
299 /* Apalis MMC1_CD# */
300 pv3 {
301 nvidia,pins = "pv3";
302 nvidia,function = "rsvd2";
303 nvidia,pull = <TEGRA_PIN_PULL_UP>;
304 nvidia,tristate = <TEGRA_PIN_DISABLE>;
305 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
306 };
307
308 /* Apalis Parallel Camera */
309 cam-mclk-pcc0 {
310 nvidia,pins = "cam_mclk_pcc0";
311 nvidia,function = "vi_alt3";
312 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
313 nvidia,tristate = <TEGRA_PIN_DISABLE>;
314 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
315 };
316 vi-vsync-pd6 {
317 nvidia,pins = "vi_d0_pt4",
318 "vi_d1_pd5",
319 "vi_d2_pl0",
320 "vi_d3_pl1",
321 "vi_d4_pl2",
322 "vi_d5_pl3",
323 "vi_d6_pl4",
324 "vi_d7_pl5",
325 "vi_d8_pl6",
326 "vi_d9_pl7",
327 "vi_d10_pt2",
328 "vi_d11_pt3",
329 "vi_hsync_pd7",
330 "vi_pclk_pt0",
331 "vi_vsync_pd6";
332 nvidia,function = "vi";
333 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
334 nvidia,tristate = <TEGRA_PIN_DISABLE>;
335 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
336 };
337 /* Multiplexed and therefore disabled */
338 kb-col2-pq2 {
339 nvidia,pins = "kb_col2_pq2",
340 "kb_col3_pq3",
341 "kb_col4_pq4",
342 "kb_row4_pr4";
343 nvidia,function = "rsvd4";
344 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
345 nvidia,tristate = <TEGRA_PIN_ENABLE>;
346 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
347 };
348 kb-row0-pr0 {
349 nvidia,pins = "kb_row0_pr0",
350 "kb_row1_pr1",
351 "kb_row2_pr2",
352 "kb_row3_pr3";
353 nvidia,function = "rsvd3";
354 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
355 nvidia,tristate = <TEGRA_PIN_ENABLE>;
356 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
357 };
358 kb-row5-pr5 {
359 nvidia,pins = "kb_row5_pr5",
360 "kb_row6_pr6",
361 "kb_row7_pr7";
362 nvidia,function = "kbc";
363 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
364 nvidia,tristate = <TEGRA_PIN_ENABLE>;
365 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
366 };
367 /*
368 * VI level-shifter direction
369 * (pull-down => default direction input)
370 */
371 vi-mclk-pt1 {
372 nvidia,pins = "vi_mclk_pt1";
373 nvidia,function = "vi_alt3";
374 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
375 nvidia,tristate = <TEGRA_PIN_ENABLE>;
376 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
377 };
378
379 /* Apalis PWM1 */
380 pu6 {
381 nvidia,pins = "pu6";
382 nvidia,function = "pwm3";
383 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
384 nvidia,tristate = <TEGRA_PIN_DISABLE>;
385 };
386
387 /* Apalis PWM2 */
388 pu5 {
389 nvidia,pins = "pu5";
390 nvidia,function = "pwm2";
391 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
392 nvidia,tristate = <TEGRA_PIN_DISABLE>;
393 };
394
395 /* Apalis PWM3 */
396 pu4 {
397 nvidia,pins = "pu4";
398 nvidia,function = "pwm1";
399 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
400 nvidia,tristate = <TEGRA_PIN_DISABLE>;
401 };
402
403 /* Apalis PWM4 */
404 pu3 {
405 nvidia,pins = "pu3";
406 nvidia,function = "pwm0";
407 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
408 nvidia,tristate = <TEGRA_PIN_DISABLE>;
409 };
410
411 /* Apalis RESET_MOCI# */
412 gmi-rst-n-pi4 {
413 nvidia,pins = "gmi_rst_n_pi4";
414 nvidia,function = "gmi";
415 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
416 nvidia,tristate = <TEGRA_PIN_DISABLE>;
417 };
418
419 /* Apalis SATA1_ACT# */
420 pex-l0-prsnt-n-pdd0 {
421 nvidia,pins = "pex_l0_prsnt_n_pdd0";
422 nvidia,function = "rsvd3";
423 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
424 nvidia,tristate = <TEGRA_PIN_DISABLE>;
425 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
426 };
427
428 /* Apalis SD1 */
429 sdmmc1-clk-pz0 {
430 nvidia,pins = "sdmmc1_clk_pz0";
431 nvidia,function = "sdmmc1";
432 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
433 nvidia,tristate = <TEGRA_PIN_DISABLE>;
434 };
435 sdmmc1-cmd-pz1 {
436 nvidia,pins = "sdmmc1_cmd_pz1",
437 "sdmmc1_dat0_py7",
438 "sdmmc1_dat1_py6",
439 "sdmmc1_dat2_py5",
440 "sdmmc1_dat3_py4";
441 nvidia,function = "sdmmc1";
442 nvidia,pull = <TEGRA_PIN_PULL_UP>;
443 nvidia,tristate = <TEGRA_PIN_DISABLE>;
444 };
445 /* Apalis SD1_CD# */
446 clk2-req-pcc5 {
447 nvidia,pins = "clk2_req_pcc5";
448 nvidia,function = "rsvd2";
449 nvidia,pull = <TEGRA_PIN_PULL_UP>;
450 nvidia,tristate = <TEGRA_PIN_DISABLE>;
451 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
452 };
453
454 /* Apalis SPDIF1 */
455 spdif-out-pk5 {
456 nvidia,pins = "spdif_out_pk5",
457 "spdif_in_pk6";
458 nvidia,function = "spdif";
459 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
460 nvidia,tristate = <TEGRA_PIN_DISABLE>;
461 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
462 };
463
464 /* Apalis SPI1 */
465 spi1-sck-px5 {
466 nvidia,pins = "spi1_sck_px5",
467 "spi1_mosi_px4",
468 "spi1_miso_px7",
469 "spi1_cs0_n_px6";
470 nvidia,function = "spi1";
471 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
472 nvidia,tristate = <TEGRA_PIN_DISABLE>;
473 };
474
475 /* Apalis SPI2 */
476 lcd-sck-pz4 {
477 nvidia,pins = "lcd_sck_pz4",
478 "lcd_sdout_pn5",
479 "lcd_sdin_pz2",
480 "lcd_cs0_n_pn4";
481 nvidia,function = "spi5";
482 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
483 nvidia,tristate = <TEGRA_PIN_DISABLE>;
484 };
485
486 /*
487 * Apalis TS (Low-speed type specific)
488 * pins may be used as GPIOs
489 */
490 kb-col5-pq5 {
491 nvidia,pins = "kb_col5_pq5";
492 nvidia,function = "rsvd4";
493 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
494 nvidia,tristate = <TEGRA_PIN_DISABLE>;
495 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
496 };
497 kb-col6-pq6 {
498 nvidia,pins = "kb_col6_pq6",
499 "kb_col7_pq7",
500 "kb_row8_ps0",
501 "kb_row9_ps1";
502 nvidia,function = "kbc";
503 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
504 nvidia,tristate = <TEGRA_PIN_DISABLE>;
505 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
506 };
507
508 /* Apalis UART1 */
509 ulpi-data0 {
510 nvidia,pins = "ulpi_data0_po1",
511 "ulpi_data1_po2",
512 "ulpi_data2_po3",
513 "ulpi_data3_po4",
514 "ulpi_data4_po5",
515 "ulpi_data5_po6",
516 "ulpi_data6_po7",
517 "ulpi_data7_po0";
518 nvidia,function = "uarta";
519 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
520 nvidia,tristate = <TEGRA_PIN_DISABLE>;
521 };
522
523 /* Apalis UART2 */
524 ulpi-clk-py0 {
525 nvidia,pins = "ulpi_clk_py0",
526 "ulpi_dir_py1",
527 "ulpi_nxt_py2",
528 "ulpi_stp_py3";
529 nvidia,function = "uartd";
530 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
531 nvidia,tristate = <TEGRA_PIN_DISABLE>;
532 };
533
534 /* Apalis UART3 */
535 uart2-rxd-pc3 {
536 nvidia,pins = "uart2_rxd_pc3",
537 "uart2_txd_pc2";
538 nvidia,function = "uartb";
539 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
540 nvidia,tristate = <TEGRA_PIN_DISABLE>;
541 };
542
543 /* Apalis UART4 */
544 uart3-rxd-pw7 {
545 nvidia,pins = "uart3_rxd_pw7",
546 "uart3_txd_pw6";
547 nvidia,function = "uartc";
548 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
549 nvidia,tristate = <TEGRA_PIN_DISABLE>;
550 };
551
552 /* Apalis USBH_EN */
553 pex-l0-rst-n-pdd1 {
554 nvidia,pins = "pex_l0_rst_n_pdd1";
555 nvidia,function = "rsvd3";
556 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
557 nvidia,tristate = <TEGRA_PIN_DISABLE>;
558 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
559 };
560
561 /* Apalis USBH_OC# */
562 pex-l0-clkreq-n-pdd2 {
563 nvidia,pins = "pex_l0_clkreq_n_pdd2";
564 nvidia,function = "rsvd3";
565 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
566 nvidia,tristate = <TEGRA_PIN_DISABLE>;
567 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
568 };
569
570 /* Apalis USBO1_EN */
571 gen2-i2c-scl-pt5 {
572 nvidia,pins = "gen2_i2c_scl_pt5";
573 nvidia,function = "rsvd4";
574 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
575 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
576 nvidia,tristate = <TEGRA_PIN_DISABLE>;
577 };
578
579 /* Apalis USBO1_OC# */
580 gen2-i2c-sda-pt6 {
581 nvidia,pins = "gen2_i2c_sda_pt6";
582 nvidia,function = "rsvd4";
583 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
584 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
585 nvidia,tristate = <TEGRA_PIN_DISABLE>;
586 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
587 };
588
589 /* Apalis VGA1 not supported and therefore disabled */
590 crt-hsync-pv6 {
591 nvidia,pins = "crt_hsync_pv6",
592 "crt_vsync_pv7";
593 nvidia,function = "rsvd2";
594 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
595 nvidia,tristate = <TEGRA_PIN_ENABLE>;
596 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
597 };
598
599 /* Apalis WAKE1_MICO */
600 pv1 {
601 nvidia,pins = "pv1";
602 nvidia,function = "rsvd1";
603 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
604 nvidia,tristate = <TEGRA_PIN_DISABLE>;
605 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
606 };
607
608 /* eMMC (On-module) */
609 sdmmc4-clk-pcc4 {
610 nvidia,pins = "sdmmc4_clk_pcc4",
611 "sdmmc4_cmd_pt7",
612 "sdmmc4_rst_n_pcc3";
613 nvidia,function = "sdmmc4";
614 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
615 nvidia,tristate = <TEGRA_PIN_DISABLE>;
616 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
617 };
618 sdmmc4-dat0-paa0 {
619 nvidia,pins = "sdmmc4_dat0_paa0",
620 "sdmmc4_dat1_paa1",
621 "sdmmc4_dat2_paa2",
622 "sdmmc4_dat3_paa3",
623 "sdmmc4_dat4_paa4",
624 "sdmmc4_dat5_paa5",
625 "sdmmc4_dat6_paa6",
626 "sdmmc4_dat7_paa7";
627 nvidia,function = "sdmmc4";
628 nvidia,pull = <TEGRA_PIN_PULL_UP>;
629 nvidia,tristate = <TEGRA_PIN_DISABLE>;
630 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
631 };
632
633 /* EN_+3.3_SDMMC3 */
634 uart2-cts-n-pj5 {
635 nvidia,pins = "uart2_cts_n_pj5";
636 nvidia,function = "gmi";
637 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
638 nvidia,tristate = <TEGRA_PIN_DISABLE>;
639 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
640 };
641
642 /* LAN i210/i211 DEV_OFF_N, PE_RST_N (On-module) */
643 pex-l2-prsnt-n-pdd7 {
644 nvidia,pins = "pex_l2_prsnt_n_pdd7",
645 "pex_l2_rst_n_pcc6";
646 nvidia,function = "pcie";
647 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
648 nvidia,tristate = <TEGRA_PIN_DISABLE>;
649 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
650 };
651 /* LAN i210/i211 PE_WAKE_N, SDP3 (On-module) */
652 pex-wake-n-pdd3 {
653 nvidia,pins = "pex_wake_n_pdd3",
654 "pex_l2_clkreq_n_pcc7";
655 nvidia,function = "pcie";
656 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
657 nvidia,tristate = <TEGRA_PIN_DISABLE>;
658 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
659 };
660 /* LAN i210/i211 SMB_ALERT_N (On-module) */
661 sys-clk-req-pz5 {
662 nvidia,pins = "sys_clk_req_pz5";
663 nvidia,function = "rsvd2";
664 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
665 nvidia,tristate = <TEGRA_PIN_DISABLE>;
666 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
667 };
668
669 /* LVDS Transceiver Configuration */
670 pbb0 {
671 nvidia,pins = "pbb0",
672 "pbb7",
673 "pcc1",
674 "pcc2";
675 nvidia,function = "rsvd2";
676 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
677 nvidia,tristate = <TEGRA_PIN_DISABLE>;
678 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
679 };
680 pbb3 {
681 nvidia,pins = "pbb3",
682 "pbb4",
683 "pbb5",
684 "pbb6";
685 nvidia,function = "displayb";
686 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
687 nvidia,tristate = <TEGRA_PIN_DISABLE>;
688 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
689 };
690
691 /* Not connected and therefore disabled */
692 clk-32k-out-pa0 {
693 nvidia,pins = "clk3_out_pee0",
694 "clk3_req_pee1",
695 "clk_32k_out_pa0",
696 "dap4_din_pp5",
697 "dap4_dout_pp6",
698 "dap4_fs_pp4",
699 "dap4_sclk_pp7";
700 nvidia,function = "rsvd2";
701 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
702 nvidia,tristate = <TEGRA_PIN_ENABLE>;
703 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
704 };
705 dap2-fs-pa2 {
706 nvidia,pins = "dap2_fs_pa2",
707 "dap2_sclk_pa3",
708 "dap2_din_pa4",
709 "dap2_dout_pa5",
710 "lcd_dc0_pn6",
711 "lcd_m1_pw1",
712 "lcd_pwr1_pc1",
713 "pex_l1_clkreq_n_pdd6",
714 "pex_l1_prsnt_n_pdd4",
715 "pex_l1_rst_n_pdd5";
716 nvidia,function = "rsvd3";
717 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
718 nvidia,tristate = <TEGRA_PIN_ENABLE>;
719 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
720 };
721 gmi-ad0-pg0 {
722 nvidia,pins = "gmi_ad0_pg0",
723 "gmi_ad2_pg2",
724 "gmi_ad3_pg3",
725 "gmi_ad4_pg4",
726 "gmi_ad5_pg5",
727 "gmi_ad6_pg6",
728 "gmi_ad7_pg7",
729 "gmi_ad8_ph0",
730 "gmi_ad9_ph1",
731 "gmi_ad10_ph2",
732 "gmi_ad11_ph3",
733 "gmi_ad12_ph4",
734 "gmi_ad13_ph5",
735 "gmi_ad14_ph6",
736 "gmi_ad15_ph7",
737 "gmi_adv_n_pk0",
738 "gmi_clk_pk1",
739 "gmi_cs4_n_pk2",
740 "gmi_cs2_n_pk3",
741 "gmi_dqs_pi2",
742 "gmi_iordy_pi5",
743 "gmi_oe_n_pi1",
744 "gmi_wait_pi7",
745 "gmi_wr_n_pi0",
746 "lcd_cs1_n_pw0",
747 "pu0",
748 "pu1",
749 "pu2";
750 nvidia,function = "rsvd4";
751 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
752 nvidia,tristate = <TEGRA_PIN_ENABLE>;
753 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
754 };
755 gmi-cs0-n-pj0 {
756 nvidia,pins = "gmi_cs0_n_pj0",
757 "gmi_cs1_n_pj2",
758 "gmi_cs3_n_pk4";
759 nvidia,function = "rsvd1";
760 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
761 nvidia,tristate = <TEGRA_PIN_ENABLE>;
762 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
763 };
764 gmi-cs6-n-pi3 {
765 nvidia,pins = "gmi_cs6_n_pi3";
766 nvidia,function = "sata";
767 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
768 nvidia,tristate = <TEGRA_PIN_ENABLE>;
769 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
770 };
771 gmi-cs7-n-pi6 {
772 nvidia,pins = "gmi_cs7_n_pi6";
773 nvidia,function = "gmi_alt";
774 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
775 nvidia,tristate = <TEGRA_PIN_ENABLE>;
776 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
777 };
778 lcd-pwr0-pb2 {
779 nvidia,pins = "lcd_pwr0_pb2",
780 "lcd_pwr2_pc6",
781 "lcd_wr_n_pz3";
782 nvidia,function = "hdcp";
783 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
784 nvidia,tristate = <TEGRA_PIN_ENABLE>;
785 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
786 };
787 uart2-rts-n-pj6 {
788 nvidia,pins = "uart2_rts_n_pj6";
789 nvidia,function = "gmi";
790 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
791 nvidia,tristate = <TEGRA_PIN_ENABLE>;
792 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
793 };
794
795 /* Power I2C (On-module) */
796 pwr-i2c-scl-pz6 {
797 nvidia,pins = "pwr_i2c_scl_pz6",
798 "pwr_i2c_sda_pz7";
799 nvidia,function = "i2cpwr";
800 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
801 nvidia,tristate = <TEGRA_PIN_DISABLE>;
802 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
803 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
804 };
805
806 /*
807 * THERMD_ALERT#, unlatched I2C address pin of LM95245
808 * temperature sensor therefore requires disabling for
809 * now
810 */
811 lcd-dc1-pd2 {
812 nvidia,pins = "lcd_dc1_pd2";
813 nvidia,function = "rsvd3";
814 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
815 nvidia,tristate = <TEGRA_PIN_ENABLE>;
816 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
817 };
818
819 /* TOUCH_PEN_INT# (On-module) */
820 pv0 {
821 nvidia,pins = "pv0";
822 nvidia,function = "rsvd1";
823 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
824 nvidia,tristate = <TEGRA_PIN_DISABLE>;
825 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
826 };
827 };
828 };
829
830 serial@70006040 {
831 compatible = "nvidia,tegra30-hsuart";
832 };
833
834 serial@70006200 {
835 compatible = "nvidia,tegra30-hsuart";
836 };
837
838 serial@70006300 {
839 compatible = "nvidia,tegra30-hsuart";
840 };
841
842 hdmi_ddc: i2c@7000c700 {
843 clock-frequency = <10000>;
844 };
845
846 /*
847 * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
848 * touch screen controller
849 */
850 i2c@7000d000 {
851 status = "okay";
852 clock-frequency = <100000>;
853
854 /* SGTL5000 audio codec */
855 sgtl5000: codec@a {
856 compatible = "fsl,sgtl5000";
857 reg = <0x0a>;
858 VDDA-supply = <&reg_module_3v3_audio>;
859 VDDD-supply = <&reg_1v8_vio>;
860 VDDIO-supply = <&reg_module_3v3>;
861 clocks = <&tegra_car TEGRA30_CLK_EXTERN1>;
862 };
863
864 pmic: pmic@2d {
865 compatible = "ti,tps65911";
866 reg = <0x2d>;
867
868 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
869 #interrupt-cells = <2>;
870 interrupt-controller;
871
872 ti,system-power-controller;
873
874 #gpio-cells = <2>;
875 gpio-controller;
876
877 vcc1-supply = <&reg_module_3v3>;
878 vcc2-supply = <&reg_module_3v3>;
879 vcc3-supply = <&reg_1v8_vio>;
880 vcc4-supply = <&reg_module_3v3>;
881 vcc5-supply = <&reg_module_3v3>;
882 vcc6-supply = <&reg_1v8_vio>;
883 vcc7-supply = <&reg_5v0_charge_pump>;
884 vccio-supply = <&reg_module_3v3>;
885
886 regulators {
887 vdd1_reg: vdd1 {
888 regulator-name = "+V1.35_VDDIO_DDR";
889 regulator-min-microvolt = <1350000>;
890 regulator-max-microvolt = <1350000>;
891 regulator-always-on;
892 };
893
894 vdd2_reg: vdd2 {
895 regulator-name = "+V1.05";
896 regulator-min-microvolt = <1050000>;
897 regulator-max-microvolt = <1050000>;
898 };
899
900 vddctrl_reg: vddctrl {
901 regulator-name = "+V1.0_VDD_CPU";
902 regulator-min-microvolt = <1150000>;
903 regulator-max-microvolt = <1150000>;
904 regulator-always-on;
905 };
906
907 reg_1v8_vio: vio {
908 regulator-name = "+V1.8";
909 regulator-min-microvolt = <1800000>;
910 regulator-max-microvolt = <1800000>;
911 regulator-always-on;
912 };
913
914 /*
915 * 1.8 volt +VDDIO_SDMMC3 in case EN_+3.3_SDMMC3
916 * is off
917 */
918 vddio_sdmmc_1v8_reg: ldo1 {
919 regulator-name = "+VDDIO_SDMMC3_1V8";
920 regulator-min-microvolt = <1800000>;
921 regulator-max-microvolt = <1800000>;
922 regulator-always-on;
923 };
924
925 /*
926 * EN_+V3.3 switching via FET:
927 * +V3.3_AUDIO_AVDD_S, +V3.3
928 * see also +V3.3 fixed supply
929 */
930 ldo2_reg: ldo2 {
931 regulator-name = "EN_+V3.3";
932 regulator-min-microvolt = <3300000>;
933 regulator-max-microvolt = <3300000>;
934 regulator-always-on;
935 };
936
937 ldo3_reg: ldo3 {
938 regulator-name = "+V1.2_CSI";
939 regulator-min-microvolt = <1200000>;
940 regulator-max-microvolt = <1200000>;
941 };
942
943 ldo4_reg: ldo4 {
944 regulator-name = "+V1.2_VDD_RTC";
945 regulator-min-microvolt = <1200000>;
946 regulator-max-microvolt = <1200000>;
947 regulator-always-on;
948 };
949
950 /*
951 * +V2.8_AVDD_VDAC:
952 * only required for (unsupported) analog RGB
953 */
954 ldo5_reg: ldo5 {
955 regulator-name = "+V2.8_AVDD_VDAC";
956 regulator-min-microvolt = <2800000>;
957 regulator-max-microvolt = <2800000>;
958 regulator-always-on;
959 };
960
961 /*
962 * +V1.05_AVDD_PLLE: avdd_plle should be 1.05V
963 * but LDO6 can't set voltage in 50mV
964 * granularity
965 */
966 ldo6_reg: ldo6 {
967 regulator-name = "+V1.05_AVDD_PLLE";
968 regulator-min-microvolt = <1100000>;
969 regulator-max-microvolt = <1100000>;
970 };
971
972 ldo7_reg: ldo7 {
973 regulator-name = "+V1.2_AVDD_PLL";
974 regulator-min-microvolt = <1200000>;
975 regulator-max-microvolt = <1200000>;
976 regulator-always-on;
977 };
978
979 ldo8_reg: ldo8 {
980 regulator-name = "+V1.0_VDD_DDR_HS";
981 regulator-min-microvolt = <1000000>;
982 regulator-max-microvolt = <1000000>;
983 regulator-always-on;
984 };
985 };
986 };
987
988 /* STMPE811 touch screen controller */
989 touchscreen@41 {
990 compatible = "st,stmpe811";
991 reg = <0x41>;
992 irq-gpio = <&gpio TEGRA_GPIO(V, 0) IRQ_TYPE_LEVEL_LOW>;
993 interrupt-controller;
994 id = <0>;
995 blocks = <0x5>;
996 irq-trigger = <0x1>;
997
998 stmpe_touchscreen {
999 compatible = "st,stmpe-ts";
1000 /* 3.25 MHz ADC clock speed */
1001 st,adc-freq = <1>;
1002 /* 8 sample average control */
1003 st,ave-ctrl = <3>;
1004 /* 7 length fractional part in z */
1005 st,fraction-z = <7>;
1006 /*
1007 * 50 mA typical 80 mA max touchscreen drivers
1008 * current limit value
1009 */
1010 st,i-drive = <1>;
1011 /* 12-bit ADC */
1012 st,mod-12b = <1>;
1013 /* internal ADC reference */
1014 st,ref-sel = <0>;
1015 /* ADC converstion time: 80 clocks */
1016 st,sample-time = <4>;
1017 /* 1 ms panel driver settling time */
1018 st,settling = <3>;
1019 /* 5 ms touch detect interrupt delay */
1020 st,touch-det-delay = <5>;
1021 };
1022 };
1023
1024 /*
1025 * LM95245 temperature sensor
1026 * Note: OVERT1# directly connected to TPS65911 PMIC PWRDN
1027 */
1028 temp-sensor@4c {
1029 compatible = "national,lm95245";
1030 reg = <0x4c>;
1031 };
1032
1033 /* SW: +V1.2_VDD_CORE */
1034 regulator@60 {
1035 compatible = "ti,tps62362";
1036 reg = <0x60>;
1037
1038 regulator-name = "tps62362-vout";
1039 regulator-min-microvolt = <900000>;
1040 regulator-max-microvolt = <1400000>;
1041 regulator-boot-on;
1042 regulator-always-on;
1043 ti,vsel0-state-low;
1044 /* VSEL1: EN_CORE_DVFS_N low for DVFS */
1045 ti,vsel1-state-low;
1046 };
1047 };
1048
1049 /* SPI4: CAN2 */
1050 spi@7000da00 {
1051 status = "okay";
1052 spi-max-frequency = <10000000>;
1053
1054 can@1 {
1055 compatible = "microchip,mcp2515";
1056 reg = <1>;
1057 clocks = <&clk16m>;
1058 interrupt-parent = <&gpio>;
1059 interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_EDGE_FALLING>;
1060 spi-max-frequency = <10000000>;
1061 };
1062 };
1063
1064 /* SPI6: CAN1 */
1065 spi@7000de00 {
1066 status = "okay";
1067 spi-max-frequency = <10000000>;
1068
1069 can@0 {
1070 compatible = "microchip,mcp2515";
1071 reg = <0>;
1072 clocks = <&clk16m>;
1073 interrupt-parent = <&gpio>;
1074 interrupts = <TEGRA_GPIO(W, 2) IRQ_TYPE_EDGE_FALLING>;
1075 spi-max-frequency = <10000000>;
1076 };
1077 };
1078
1079 pmc@7000e400 {
1080 nvidia,invert-interrupt;
1081 nvidia,suspend-mode = <1>;
1082 nvidia,cpu-pwr-good-time = <5000>;
1083 nvidia,cpu-pwr-off-time = <5000>;
1084 nvidia,core-pwr-good-time = <3845 3845>;
1085 nvidia,core-pwr-off-time = <0>;
1086 nvidia,core-power-req-active-high;
1087 nvidia,sys-clock-req-active-high;
1088
1089 /* Set DEV_OFF bit in DCDC control register of TPS65911 PMIC */
1090 i2c-thermtrip {
1091 nvidia,i2c-controller-id = <4>;
1092 nvidia,bus-addr = <0x2d>;
1093 nvidia,reg-addr = <0x3f>;
1094 nvidia,reg-data = <0x1>;
1095 };
1096 };
1097
1098 hda@70030000 {
1099 status = "okay";
1100 };
1101
1102 ahub@70080000 {
1103 i2s@70080500 {
1104 status = "okay";
1105 };
1106 };
1107
1108 /* eMMC */
1109 sdhci@78000600 {
1110 status = "okay";
1111 bus-width = <8>;
1112 non-removable;
1113 vmmc-supply = <&reg_module_3v3>; /* VCC */
1114 vqmmc-supply = <&reg_1v8_vio>; /* VCCQ */
1115 mmc-ddr-1_8v;
1116 };
1117
1118 clk32k_in: xtal1 {
1119 compatible = "fixed-clock";
1120 #clock-cells = <0>;
1121 clock-frequency = <32768>;
1122 };
1123
1124 clk16m: osc4 {
1125 compatible = "fixed-clock";
1126 #clock-cells = <0>;
1127 clock-frequency = <16000000>;
1128 };
1129
1130 reg_1v8_avdd_hdmi_pll: regulator-1v8-avdd-hdmi-pll {
1131 compatible = "regulator-fixed";
1132 regulator-name = "+V1.8_AVDD_HDMI_PLL";
1133 regulator-min-microvolt = <1800000>;
1134 regulator-max-microvolt = <1800000>;
1135 enable-active-high;
1136 gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
1137 vin-supply = <&reg_1v8_vio>;
1138 };
1139
1140 reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi {
1141 compatible = "regulator-fixed";
1142 regulator-name = "+V3.3_AVDD_HDMI";
1143 regulator-min-microvolt = <3300000>;
1144 regulator-max-microvolt = <3300000>;
1145 enable-active-high;
1146 gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
1147 vin-supply = <&reg_module_3v3>;
1148 };
1149
1150 reg_5v0_charge_pump: regulator-5v0-charge-pump {
1151 compatible = "regulator-fixed";
1152 regulator-name = "+V5.0";
1153 regulator-min-microvolt = <5000000>;
1154 regulator-max-microvolt = <5000000>;
1155 regulator-always-on;
1156 };
1157
1158 reg_module_3v3: regulator-module-3v3 {
1159 compatible = "regulator-fixed";
1160 regulator-name = "+V3.3";
1161 regulator-min-microvolt = <3300000>;
1162 regulator-max-microvolt = <3300000>;
1163 regulator-always-on;
1164 };
1165
1166 reg_module_3v3_audio: regulator-module-3v3-audio {
1167 compatible = "regulator-fixed";
1168 regulator-name = "+V3.3_AUDIO_AVDD_S";
1169 regulator-min-microvolt = <3300000>;
1170 regulator-max-microvolt = <3300000>;
1171 regulator-always-on;
1172 };
1173
1174 sound {
1175 compatible = "toradex,tegra-audio-sgtl5000-apalis_t30",
1176 "nvidia,tegra-audio-sgtl5000";
1177 nvidia,model = "Toradex Apalis T30";
1178 nvidia,audio-routing =
1179 "Headphone Jack", "HP_OUT",
1180 "LINE_IN", "Line In Jack",
1181 "MIC_IN", "Mic Jack";
1182 nvidia,i2s-controller = <&tegra_i2s2>;
1183 nvidia,audio-codec = <&sgtl5000>;
1184 clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
1185 <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
1186 <&tegra_car TEGRA30_CLK_EXTERN1>;
1187 clock-names = "pll_a", "pll_a_out0", "mclk";
1188 };
1189};
diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi
index 2f807d40c1b7..7f112f192fe9 100644
--- a/arch/arm/boot/dts/tegra30-apalis.dtsi
+++ b/arch/arm/boot/dts/tegra30-apalis.dtsi
@@ -3,48 +3,53 @@
3 3
4/* 4/*
5 * Toradex Apalis T30 Module Device Tree 5 * Toradex Apalis T30 Module Device Tree
6 * Compatible for Revisions 1GB: V1.0A, V1.1A; 1GB IT: V1.1A; 6 * Compatible for Revisions 1GB: V1.0A; 2GB: V1.0B, V1.0C, V1.0E
7 * 2GB: V1.0B, V1.0C, V1.0E, V1.1A
8 */ 7 */
9/ { 8/ {
10 model = "Toradex Apalis T30";
11 compatible = "toradex,apalis_t30", "nvidia,tegra30";
12
13 memory@80000000 { 9 memory@80000000 {
14 reg = <0x80000000 0x40000000>; 10 reg = <0x80000000 0x40000000>;
15 }; 11 };
16 12
17 pcie@3000 { 13 pcie@3000 {
14 status = "okay";
18 avdd-pexa-supply = <&vdd2_reg>; 15 avdd-pexa-supply = <&vdd2_reg>;
19 vdd-pexa-supply = <&vdd2_reg>;
20 avdd-pexb-supply = <&vdd2_reg>; 16 avdd-pexb-supply = <&vdd2_reg>;
21 vdd-pexb-supply = <&vdd2_reg>;
22 avdd-pex-pll-supply = <&vdd2_reg>; 17 avdd-pex-pll-supply = <&vdd2_reg>;
23 avdd-plle-supply = <&ldo6_reg>; 18 avdd-plle-supply = <&ldo6_reg>;
24 vddio-pex-ctl-supply = <&sys_3v3_reg>; 19 hvdd-pex-supply = <&reg_module_3v3>;
25 hvdd-pex-supply = <&sys_3v3_reg>; 20 vddio-pex-ctl-supply = <&reg_module_3v3>;
21 vdd-pexa-supply = <&vdd2_reg>;
22 vdd-pexb-supply = <&vdd2_reg>;
26 23
24 /* Apalis type specific */
27 pci@1,0 { 25 pci@1,0 {
28 nvidia,num-lanes = <4>; 26 nvidia,num-lanes = <4>;
29 }; 27 };
30 28
29 /* Apalis PCIe */
31 pci@2,0 { 30 pci@2,0 {
32 nvidia,num-lanes = <1>; 31 nvidia,num-lanes = <1>;
33 }; 32 };
34 33
34 /* I210/I211 Gigabit Ethernet Controller (on-module) */
35 pci@3,0 { 35 pci@3,0 {
36 status = "okay";
36 nvidia,num-lanes = <1>; 37 nvidia,num-lanes = <1>;
38
39 pcie@0 {
40 reg = <0 0 0 0 0>;
41 local-mac-address = [00 00 00 00 00 00];
42 };
37 }; 43 };
38 }; 44 };
39 45
40 host1x@50000000 { 46 host1x@50000000 {
41 hdmi@54280000 { 47 hdmi@54280000 {
42 vdd-supply = <&avdd_hdmi_3v3_reg>; 48 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
43 pll-supply = <&avdd_hdmi_pll_1v8_reg>;
44
45 nvidia,hpd-gpio = 49 nvidia,hpd-gpio =
46 <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; 50 <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
47 nvidia,ddc-i2c-bus = <&hdmiddc>; 51 pll-supply = <&reg_1v8_avdd_hdmi_pll>;
52 vdd-supply = <&reg_3v3_avdd_hdmi>;
48 }; 53 };
49 }; 54 };
50 55
@@ -54,18 +59,18 @@
54 59
55 state_default: pinmux { 60 state_default: pinmux {
56 /* Analogue Audio (On-module) */ 61 /* Analogue Audio (On-module) */
57 clk1_out_pw4 { 62 clk1-out-pw4 {
58 nvidia,pins = "clk1_out_pw4"; 63 nvidia,pins = "clk1_out_pw4";
59 nvidia,function = "extperiph1"; 64 nvidia,function = "extperiph1";
60 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 65 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
61 nvidia,tristate = <TEGRA_PIN_DISABLE>; 66 nvidia,tristate = <TEGRA_PIN_DISABLE>;
62 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 67 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
63 }; 68 };
64 dap3_fs_pp0 { 69 dap3-fs-pp0 {
65 nvidia,pins = "dap3_fs_pp0", 70 nvidia,pins = "dap3_fs_pp0",
66 "dap3_sclk_pp3", 71 "dap3_sclk_pp3",
67 "dap3_din_pp1", 72 "dap3_din_pp1",
68 "dap3_dout_pp2"; 73 "dap3_dout_pp2";
69 nvidia,function = "i2s2"; 74 nvidia,function = "i2s2";
70 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 75 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
71 nvidia,tristate = <TEGRA_PIN_DISABLE>; 76 nvidia,tristate = <TEGRA_PIN_DISABLE>;
@@ -77,25 +82,28 @@
77 nvidia,function = "rsvd4"; 82 nvidia,function = "rsvd4";
78 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 83 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
79 nvidia,tristate = <TEGRA_PIN_DISABLE>; 84 nvidia,tristate = <TEGRA_PIN_DISABLE>;
85 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
80 }; 86 };
81 87
82 /* Apalis BKL1_PWM */ 88 /* Apalis BKL1_PWM */
83 uart3_rts_n_pc0 { 89 uart3-rts-n-pc0 {
84 nvidia,pins = "uart3_rts_n_pc0"; 90 nvidia,pins = "uart3_rts_n_pc0";
85 nvidia,function = "pwm0"; 91 nvidia,function = "pwm0";
86 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 92 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
87 nvidia,tristate = <TEGRA_PIN_DISABLE>; 93 nvidia,tristate = <TEGRA_PIN_DISABLE>;
94 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
88 }; 95 };
89 /* BKL1_PWM_EN#, disable TPS65911 PMIC PWM backlight */ 96 /* BKL1_PWM_EN#, disable TPS65911 PMIC PWM backlight */
90 uart3_cts_n_pa1 { 97 uart3-cts-n-pa1 {
91 nvidia,pins = "uart3_cts_n_pa1"; 98 nvidia,pins = "uart3_cts_n_pa1";
92 nvidia,function = "rsvd2"; 99 nvidia,function = "rsvd2";
93 nvidia,pull = <TEGRA_PIN_PULL_UP>; 100 nvidia,pull = <TEGRA_PIN_PULL_UP>;
94 nvidia,tristate = <TEGRA_PIN_DISABLE>; 101 nvidia,tristate = <TEGRA_PIN_DISABLE>;
102 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
95 }; 103 };
96 104
97 /* Apalis CAN1 on SPI6 */ 105 /* Apalis CAN1 on SPI6 */
98 spi2_cs0_n_px3 { 106 spi2-cs0-n-px3 {
99 nvidia,pins = "spi2_cs0_n_px3", 107 nvidia,pins = "spi2_cs0_n_px3",
100 "spi2_miso_px1", 108 "spi2_miso_px1",
101 "spi2_mosi_px0", 109 "spi2_mosi_px0",
@@ -105,7 +113,7 @@
105 nvidia,tristate = <TEGRA_PIN_DISABLE>; 113 nvidia,tristate = <TEGRA_PIN_DISABLE>;
106 }; 114 };
107 /* CAN_INT1 */ 115 /* CAN_INT1 */
108 spi2_cs1_n_pw2 { 116 spi2-cs1-n-pw2 {
109 nvidia,pins = "spi2_cs1_n_pw2"; 117 nvidia,pins = "spi2_cs1_n_pw2";
110 nvidia,function = "spi3"; 118 nvidia,function = "spi3";
111 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 119 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -114,7 +122,7 @@
114 }; 122 };
115 123
116 /* Apalis CAN2 on SPI4 */ 124 /* Apalis CAN2 on SPI4 */
117 gmi_a16_pj7 { 125 gmi-a16-pj7 {
118 nvidia,pins = "gmi_a16_pj7", 126 nvidia,pins = "gmi_a16_pj7",
119 "gmi_a17_pb0", 127 "gmi_a17_pb0",
120 "gmi_a18_pb1", 128 "gmi_a18_pb1",
@@ -125,7 +133,7 @@
125 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 133 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
126 }; 134 };
127 /* CAN_INT2 */ 135 /* CAN_INT2 */
128 spi2_cs2_n_pw3 { 136 spi2-cs2-n-pw3 {
129 nvidia,pins = "spi2_cs2_n_pw3"; 137 nvidia,pins = "spi2_cs2_n_pw3";
130 nvidia,function = "spi3"; 138 nvidia,function = "spi3";
131 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 139 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -134,20 +142,20 @@
134 }; 142 };
135 143
136 /* Apalis Digital Audio */ 144 /* Apalis Digital Audio */
137 clk1_req_pee2 { 145 clk1-req-pee2 {
138 nvidia,pins = "clk1_req_pee2"; 146 nvidia,pins = "clk1_req_pee2";
139 nvidia,function = "hda"; 147 nvidia,function = "hda";
140 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 148 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
141 nvidia,tristate = <TEGRA_PIN_DISABLE>; 149 nvidia,tristate = <TEGRA_PIN_DISABLE>;
142 }; 150 };
143 clk2_out_pw5 { 151 clk2-out-pw5 {
144 nvidia,pins = "clk2_out_pw5"; 152 nvidia,pins = "clk2_out_pw5";
145 nvidia,function = "extperiph2"; 153 nvidia,function = "extperiph2";
146 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 154 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
147 nvidia,tristate = <TEGRA_PIN_DISABLE>; 155 nvidia,tristate = <TEGRA_PIN_DISABLE>;
148 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 156 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
149 }; 157 };
150 dap1_fs_pn0 { 158 dap1-fs-pn0 {
151 nvidia,pins = "dap1_fs_pn0", 159 nvidia,pins = "dap1_fs_pn0",
152 "dap1_din_pn1", 160 "dap1_din_pn1",
153 "dap1_dout_pn2", 161 "dap1_dout_pn2",
@@ -157,28 +165,125 @@
157 nvidia,tristate = <TEGRA_PIN_DISABLE>; 165 nvidia,tristate = <TEGRA_PIN_DISABLE>;
158 }; 166 };
159 167
160 /* Apalis I2C3 */ 168 /* Apalis GPIO */
161 cam_i2c_scl_pbb1 { 169 kb-col0-pq0 {
170 nvidia,pins = "kb_col0_pq0",
171 "kb_col1_pq1",
172 "kb_row10_ps2",
173 "kb_row11_ps3",
174 "kb_row12_ps4",
175 "kb_row13_ps5",
176 "kb_row14_ps6",
177 "kb_row15_ps7";
178 nvidia,function = "kbc";
179 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
180 nvidia,tristate = <TEGRA_PIN_DISABLE>;
181 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
182 };
183 /* Multiplexed and therefore disabled */
184 owr {
185 nvidia,pins = "owr";
186 nvidia,function = "rsvd3";
187 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
188 nvidia,tristate = <TEGRA_PIN_ENABLE>;
189 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
190 };
191
192 /* Apalis HDMI1 */
193 hdmi-cec-pee3 {
194 nvidia,pins = "hdmi_cec_pee3";
195 nvidia,function = "cec";
196 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
197 nvidia,tristate = <TEGRA_PIN_DISABLE>;
198 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
199 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
200 };
201 hdmi-int-pn7 {
202 nvidia,pins = "hdmi_int_pn7";
203 nvidia,function = "hdmi";
204 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
205 nvidia,tristate = <TEGRA_PIN_ENABLE>;
206 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
207 };
208
209 /* Apalis I2C1 */
210 gen1-i2c-scl-pc4 {
211 nvidia,pins = "gen1_i2c_scl_pc4",
212 "gen1_i2c_sda_pc5";
213 nvidia,function = "i2c1";
214 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
215 nvidia,tristate = <TEGRA_PIN_DISABLE>;
216 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
217 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
218 };
219
220 /* Apalis I2C2 (DDC) */
221 ddc-scl-pv4 {
222 nvidia,pins = "ddc_scl_pv4",
223 "ddc_sda_pv5";
224 nvidia,function = "i2c4";
225 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
226 nvidia,tristate = <TEGRA_PIN_DISABLE>;
227 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
228 };
229
230 /* Apalis I2C3 (CAM) */
231 cam-i2c-scl-pbb1 {
162 nvidia,pins = "cam_i2c_scl_pbb1", 232 nvidia,pins = "cam_i2c_scl_pbb1",
163 "cam_i2c_sda_pbb2"; 233 "cam_i2c_sda_pbb2";
164 nvidia,function = "i2c3"; 234 nvidia,function = "i2c3";
165 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 235 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
166 nvidia,tristate = <TEGRA_PIN_DISABLE>; 236 nvidia,tristate = <TEGRA_PIN_DISABLE>;
167 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 237 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
168 nvidia,lock = <TEGRA_PIN_DISABLE>;
169 nvidia,open-drain = <TEGRA_PIN_ENABLE>; 238 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
170 }; 239 };
171 240
241 /* Apalis LCD1 */
242 lcd-d0-pe0 {
243 nvidia,pins = "lcd_d0_pe0",
244 "lcd_d1_pe1",
245 "lcd_d2_pe2",
246 "lcd_d3_pe3",
247 "lcd_d4_pe4",
248 "lcd_d5_pe5",
249 "lcd_d6_pe6",
250 "lcd_d7_pe7",
251 "lcd_d8_pf0",
252 "lcd_d9_pf1",
253 "lcd_d10_pf2",
254 "lcd_d11_pf3",
255 "lcd_d12_pf4",
256 "lcd_d13_pf5",
257 "lcd_d14_pf6",
258 "lcd_d15_pf7",
259 "lcd_d16_pm0",
260 "lcd_d17_pm1",
261 "lcd_d18_pm2",
262 "lcd_d19_pm3",
263 "lcd_d20_pm4",
264 "lcd_d21_pm5",
265 "lcd_d22_pm6",
266 "lcd_d23_pm7",
267 "lcd_de_pj1",
268 "lcd_hsync_pj3",
269 "lcd_pclk_pb3",
270 "lcd_vsync_pj4";
271 nvidia,function = "displaya";
272 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
273 nvidia,tristate = <TEGRA_PIN_DISABLE>;
274 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
275 };
276
172 /* Apalis MMC1 */ 277 /* Apalis MMC1 */
173 sdmmc3_clk_pa6 { 278 sdmmc3-clk-pa6 {
174 nvidia,pins = "sdmmc3_clk_pa6", 279 nvidia,pins = "sdmmc3_clk_pa6";
175 "sdmmc3_cmd_pa7";
176 nvidia,function = "sdmmc3"; 280 nvidia,function = "sdmmc3";
177 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 281 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
178 nvidia,tristate = <TEGRA_PIN_DISABLE>; 282 nvidia,tristate = <TEGRA_PIN_DISABLE>;
179 }; 283 };
180 sdmmc3_dat0_pb7 { 284 sdmmc3-dat0-pb7 {
181 nvidia,pins = "sdmmc3_dat0_pb7", 285 nvidia,pins = "sdmmc3_cmd_pa7",
286 "sdmmc3_dat0_pb7",
182 "sdmmc3_dat1_pb6", 287 "sdmmc3_dat1_pb6",
183 "sdmmc3_dat2_pb5", 288 "sdmmc3_dat2_pb5",
184 "sdmmc3_dat3_pb4", 289 "sdmmc3_dat3_pb4",
@@ -194,10 +299,81 @@
194 pv3 { 299 pv3 {
195 nvidia,pins = "pv3"; 300 nvidia,pins = "pv3";
196 nvidia,function = "rsvd2"; 301 nvidia,function = "rsvd2";
302 nvidia,pull = <TEGRA_PIN_PULL_UP>;
303 nvidia,tristate = <TEGRA_PIN_DISABLE>;
304 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
305 };
306
307 /* Apalis Parallel Camera */
308 cam-mclk-pcc0 {
309 nvidia,pins = "cam_mclk_pcc0";
310 nvidia,function = "vi_alt3";
311 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
312 nvidia,tristate = <TEGRA_PIN_DISABLE>;
313 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
314 };
315 vi-vsync-pd6 {
316 nvidia,pins = "vi_d0_pt4",
317 "vi_d1_pd5",
318 "vi_d2_pl0",
319 "vi_d3_pl1",
320 "vi_d4_pl2",
321 "vi_d5_pl3",
322 "vi_d6_pl4",
323 "vi_d7_pl5",
324 "vi_d8_pl6",
325 "vi_d9_pl7",
326 "vi_d10_pt2",
327 "vi_d11_pt3",
328 "vi_hsync_pd7",
329 "vi_pclk_pt0",
330 "vi_vsync_pd6";
331 nvidia,function = "vi";
197 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 332 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
198 nvidia,tristate = <TEGRA_PIN_DISABLE>; 333 nvidia,tristate = <TEGRA_PIN_DISABLE>;
199 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 334 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
200 }; 335 };
336 /* Multiplexed and therefore disabled */
337 kb-col2-pq2 {
338 nvidia,pins = "kb_col2_pq2",
339 "kb_col3_pq3",
340 "kb_col4_pq4",
341 "kb_row4_pr4";
342 nvidia,function = "rsvd4";
343 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
344 nvidia,tristate = <TEGRA_PIN_ENABLE>;
345 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
346 };
347 kb-row0-pr0 {
348 nvidia,pins = "kb_row0_pr0",
349 "kb_row1_pr1",
350 "kb_row2_pr2",
351 "kb_row3_pr3";
352 nvidia,function = "rsvd3";
353 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
354 nvidia,tristate = <TEGRA_PIN_ENABLE>;
355 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
356 };
357 kb-row5-pr5 {
358 nvidia,pins = "kb_row5_pr5",
359 "kb_row6_pr6",
360 "kb_row7_pr7";
361 nvidia,function = "kbc";
362 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
363 nvidia,tristate = <TEGRA_PIN_ENABLE>;
364 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
365 };
366 /*
367 * VI level-shifter direction
368 * (pull-down => default direction input)
369 */
370 vi-mclk-pt1 {
371 nvidia,pins = "vi_mclk_pt1";
372 nvidia,function = "vi_alt3";
373 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
374 nvidia,tristate = <TEGRA_PIN_ENABLE>;
375 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
376 };
201 377
202 /* Apalis PWM1 */ 378 /* Apalis PWM1 */
203 pu6 { 379 pu6 {
@@ -232,21 +408,30 @@
232 }; 408 };
233 409
234 /* Apalis RESET_MOCI# */ 410 /* Apalis RESET_MOCI# */
235 gmi_rst_n_pi4 { 411 gmi-rst-n-pi4 {
236 nvidia,pins = "gmi_rst_n_pi4"; 412 nvidia,pins = "gmi_rst_n_pi4";
237 nvidia,function = "gmi"; 413 nvidia,function = "gmi";
238 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 414 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
239 nvidia,tristate = <TEGRA_PIN_DISABLE>; 415 nvidia,tristate = <TEGRA_PIN_DISABLE>;
240 }; 416 };
241 417
418 /* Apalis SATA1_ACT# */
419 pex-l0-prsnt-n-pdd0 {
420 nvidia,pins = "pex_l0_prsnt_n_pdd0";
421 nvidia,function = "rsvd3";
422 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
423 nvidia,tristate = <TEGRA_PIN_DISABLE>;
424 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
425 };
426
242 /* Apalis SD1 */ 427 /* Apalis SD1 */
243 sdmmc1_clk_pz0 { 428 sdmmc1-clk-pz0 {
244 nvidia,pins = "sdmmc1_clk_pz0"; 429 nvidia,pins = "sdmmc1_clk_pz0";
245 nvidia,function = "sdmmc1"; 430 nvidia,function = "sdmmc1";
246 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 431 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
247 nvidia,tristate = <TEGRA_PIN_DISABLE>; 432 nvidia,tristate = <TEGRA_PIN_DISABLE>;
248 }; 433 };
249 sdmmc1_cmd_pz1 { 434 sdmmc1-cmd-pz1 {
250 nvidia,pins = "sdmmc1_cmd_pz1", 435 nvidia,pins = "sdmmc1_cmd_pz1",
251 "sdmmc1_dat0_py7", 436 "sdmmc1_dat0_py7",
252 "sdmmc1_dat1_py6", 437 "sdmmc1_dat1_py6",
@@ -257,16 +442,26 @@
257 nvidia,tristate = <TEGRA_PIN_DISABLE>; 442 nvidia,tristate = <TEGRA_PIN_DISABLE>;
258 }; 443 };
259 /* Apalis SD1_CD# */ 444 /* Apalis SD1_CD# */
260 clk2_req_pcc5 { 445 clk2-req-pcc5 {
261 nvidia,pins = "clk2_req_pcc5"; 446 nvidia,pins = "clk2_req_pcc5";
262 nvidia,function = "rsvd2"; 447 nvidia,function = "rsvd2";
448 nvidia,pull = <TEGRA_PIN_PULL_UP>;
449 nvidia,tristate = <TEGRA_PIN_DISABLE>;
450 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
451 };
452
453 /* Apalis SPDIF1 */
454 spdif-out-pk5 {
455 nvidia,pins = "spdif_out_pk5",
456 "spdif_in_pk6";
457 nvidia,function = "spdif";
263 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 458 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
264 nvidia,tristate = <TEGRA_PIN_DISABLE>; 459 nvidia,tristate = <TEGRA_PIN_DISABLE>;
265 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 460 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
266 }; 461 };
267 462
268 /* Apalis SPI1 */ 463 /* Apalis SPI1 */
269 spi1_sck_px5 { 464 spi1-sck-px5 {
270 nvidia,pins = "spi1_sck_px5", 465 nvidia,pins = "spi1_sck_px5",
271 "spi1_mosi_px4", 466 "spi1_mosi_px4",
272 "spi1_miso_px7", 467 "spi1_miso_px7",
@@ -277,7 +472,7 @@
277 }; 472 };
278 473
279 /* Apalis SPI2 */ 474 /* Apalis SPI2 */
280 lcd_sck_pz4 { 475 lcd-sck-pz4 {
281 nvidia,pins = "lcd_sck_pz4", 476 nvidia,pins = "lcd_sck_pz4",
282 "lcd_sdout_pn5", 477 "lcd_sdout_pn5",
283 "lcd_sdin_pz2", 478 "lcd_sdin_pz2",
@@ -287,8 +482,30 @@
287 nvidia,tristate = <TEGRA_PIN_DISABLE>; 482 nvidia,tristate = <TEGRA_PIN_DISABLE>;
288 }; 483 };
289 484
485 /*
486 * Apalis TS (Low-speed type specific)
487 * pins may be used as GPIOs
488 */
489 kb-col5-pq5 {
490 nvidia,pins = "kb_col5_pq5";
491 nvidia,function = "rsvd4";
492 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
493 nvidia,tristate = <TEGRA_PIN_DISABLE>;
494 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
495 };
496 kb-col6-pq6 {
497 nvidia,pins = "kb_col6_pq6",
498 "kb_col7_pq7",
499 "kb_row8_ps0",
500 "kb_row9_ps1";
501 nvidia,function = "kbc";
502 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
503 nvidia,tristate = <TEGRA_PIN_DISABLE>;
504 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
505 };
506
290 /* Apalis UART1 */ 507 /* Apalis UART1 */
291 ulpi_data0 { 508 ulpi-data0 {
292 nvidia,pins = "ulpi_data0_po1", 509 nvidia,pins = "ulpi_data0_po1",
293 "ulpi_data1_po2", 510 "ulpi_data1_po2",
294 "ulpi_data2_po3", 511 "ulpi_data2_po3",
@@ -303,7 +520,7 @@
303 }; 520 };
304 521
305 /* Apalis UART2 */ 522 /* Apalis UART2 */
306 ulpi_clk_py0 { 523 ulpi-clk-py0 {
307 nvidia,pins = "ulpi_clk_py0", 524 nvidia,pins = "ulpi_clk_py0",
308 "ulpi_dir_py1", 525 "ulpi_dir_py1",
309 "ulpi_nxt_py2", 526 "ulpi_nxt_py2",
@@ -314,7 +531,7 @@
314 }; 531 };
315 532
316 /* Apalis UART3 */ 533 /* Apalis UART3 */
317 uart2_rxd_pc3 { 534 uart2-rxd-pc3 {
318 nvidia,pins = "uart2_rxd_pc3", 535 nvidia,pins = "uart2_rxd_pc3",
319 "uart2_txd_pc2"; 536 "uart2_txd_pc2";
320 nvidia,function = "uartb"; 537 nvidia,function = "uartb";
@@ -323,7 +540,7 @@
323 }; 540 };
324 541
325 /* Apalis UART4 */ 542 /* Apalis UART4 */
326 uart3_rxd_pw7 { 543 uart3-rxd-pw7 {
327 nvidia,pins = "uart3_rxd_pw7", 544 nvidia,pins = "uart3_rxd_pw7",
328 "uart3_txd_pw6"; 545 "uart3_txd_pw6";
329 nvidia,function = "uartc"; 546 nvidia,function = "uartc";
@@ -331,8 +548,26 @@
331 nvidia,tristate = <TEGRA_PIN_DISABLE>; 548 nvidia,tristate = <TEGRA_PIN_DISABLE>;
332 }; 549 };
333 550
551 /* Apalis USBH_EN */
552 pex-l0-rst-n-pdd1 {
553 nvidia,pins = "pex_l0_rst_n_pdd1";
554 nvidia,function = "rsvd3";
555 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
556 nvidia,tristate = <TEGRA_PIN_DISABLE>;
557 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
558 };
559
560 /* Apalis USBH_OC# */
561 pex-l0-clkreq-n-pdd2 {
562 nvidia,pins = "pex_l0_clkreq_n_pdd2";
563 nvidia,function = "rsvd3";
564 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
565 nvidia,tristate = <TEGRA_PIN_DISABLE>;
566 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
567 };
568
334 /* Apalis USBO1_EN */ 569 /* Apalis USBO1_EN */
335 gen2_i2c_scl_pt5 { 570 gen2-i2c-scl-pt5 {
336 nvidia,pins = "gen2_i2c_scl_pt5"; 571 nvidia,pins = "gen2_i2c_scl_pt5";
337 nvidia,function = "rsvd4"; 572 nvidia,function = "rsvd4";
338 nvidia,open-drain = <TEGRA_PIN_DISABLE>; 573 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
@@ -341,7 +576,7 @@
341 }; 576 };
342 577
343 /* Apalis USBO1_OC# */ 578 /* Apalis USBO1_OC# */
344 gen2_i2c_sda_pt6 { 579 gen2-i2c-sda-pt6 {
345 nvidia,pins = "gen2_i2c_sda_pt6"; 580 nvidia,pins = "gen2_i2c_sda_pt6";
346 nvidia,function = "rsvd4"; 581 nvidia,function = "rsvd4";
347 nvidia,open-drain = <TEGRA_PIN_DISABLE>; 582 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
@@ -350,6 +585,16 @@
350 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 585 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
351 }; 586 };
352 587
588 /* Apalis VGA1 not supported and therefore disabled */
589 crt-hsync-pv6 {
590 nvidia,pins = "crt_hsync_pv6",
591 "crt_vsync_pv7";
592 nvidia,function = "rsvd2";
593 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
594 nvidia,tristate = <TEGRA_PIN_ENABLE>;
595 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
596 };
597
353 /* Apalis WAKE1_MICO */ 598 /* Apalis WAKE1_MICO */
354 pv1 { 599 pv1 {
355 nvidia,pins = "pv1"; 600 nvidia,pins = "pv1";
@@ -360,14 +605,16 @@
360 }; 605 };
361 606
362 /* eMMC (On-module) */ 607 /* eMMC (On-module) */
363 sdmmc4_clk_pcc4 { 608 sdmmc4-clk-pcc4 {
364 nvidia,pins = "sdmmc4_clk_pcc4", 609 nvidia,pins = "sdmmc4_clk_pcc4",
610 "sdmmc4_cmd_pt7",
365 "sdmmc4_rst_n_pcc3"; 611 "sdmmc4_rst_n_pcc3";
366 nvidia,function = "sdmmc4"; 612 nvidia,function = "sdmmc4";
367 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 613 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
368 nvidia,tristate = <TEGRA_PIN_DISABLE>; 614 nvidia,tristate = <TEGRA_PIN_DISABLE>;
615 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
369 }; 616 };
370 sdmmc4_dat0_paa0 { 617 sdmmc4-dat0-paa0 {
371 nvidia,pins = "sdmmc4_dat0_paa0", 618 nvidia,pins = "sdmmc4_dat0_paa0",
372 "sdmmc4_dat1_paa1", 619 "sdmmc4_dat1_paa1",
373 "sdmmc4_dat2_paa2", 620 "sdmmc4_dat2_paa2",
@@ -379,6 +626,34 @@
379 nvidia,function = "sdmmc4"; 626 nvidia,function = "sdmmc4";
380 nvidia,pull = <TEGRA_PIN_PULL_UP>; 627 nvidia,pull = <TEGRA_PIN_PULL_UP>;
381 nvidia,tristate = <TEGRA_PIN_DISABLE>; 628 nvidia,tristate = <TEGRA_PIN_DISABLE>;
629 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
630 };
631
632 /* LAN i210/i211 DEV_OFF_N, PE_RST_N (On-module) */
633 pex-l2-prsnt-n-pdd7 {
634 nvidia,pins = "pex_l2_prsnt_n_pdd7",
635 "pex_l2_rst_n_pcc6";
636 nvidia,function = "pcie";
637 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
638 nvidia,tristate = <TEGRA_PIN_DISABLE>;
639 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
640 };
641 /* LAN i210/i211 PE_WAKE_N, SDP3 (On-module) */
642 pex-wake-n-pdd3 {
643 nvidia,pins = "pex_wake_n_pdd3",
644 "pex_l2_clkreq_n_pcc7";
645 nvidia,function = "pcie";
646 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
647 nvidia,tristate = <TEGRA_PIN_DISABLE>;
648 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
649 };
650 /* LAN i210/i211 SMB_ALERT_N (On-module) */
651 sys-clk-req-pz5 {
652 nvidia,pins = "sys_clk_req_pz5";
653 nvidia,function = "rsvd2";
654 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
655 nvidia,tristate = <TEGRA_PIN_DISABLE>;
656 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
382 }; 657 };
383 658
384 /* LVDS Transceiver Configuration */ 659 /* LVDS Transceiver Configuration */
@@ -391,7 +666,6 @@
391 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 666 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
392 nvidia,tristate = <TEGRA_PIN_DISABLE>; 667 nvidia,tristate = <TEGRA_PIN_DISABLE>;
393 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 668 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
394 nvidia,lock = <TEGRA_PIN_DISABLE>;
395 }; 669 };
396 pbb3 { 670 pbb3 {
397 nvidia,pins = "pbb3", 671 nvidia,pins = "pbb3",
@@ -402,18 +676,121 @@
402 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 676 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
403 nvidia,tristate = <TEGRA_PIN_DISABLE>; 677 nvidia,tristate = <TEGRA_PIN_DISABLE>;
404 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 678 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
405 nvidia,lock = <TEGRA_PIN_DISABLE>; 679 };
680
681 /* Not connected and therefore disabled */
682 clk-32k-out-pa0 {
683 nvidia,pins = "clk3_out_pee0",
684 "clk3_req_pee1",
685 "clk_32k_out_pa0",
686 "dap4_din_pp5",
687 "dap4_dout_pp6",
688 "dap4_fs_pp4",
689 "dap4_sclk_pp7";
690 nvidia,function = "rsvd2";
691 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
692 nvidia,tristate = <TEGRA_PIN_ENABLE>;
693 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
694 };
695 dap2-fs-pa2 {
696 nvidia,pins = "dap2_fs_pa2",
697 "dap2_sclk_pa3",
698 "dap2_din_pa4",
699 "dap2_dout_pa5",
700 "lcd_dc0_pn6",
701 "lcd_m1_pw1",
702 "lcd_pwr1_pc1",
703 "pex_l1_clkreq_n_pdd6",
704 "pex_l1_prsnt_n_pdd4",
705 "pex_l1_rst_n_pdd5";
706 nvidia,function = "rsvd3";
707 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
708 nvidia,tristate = <TEGRA_PIN_ENABLE>;
709 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
710 };
711 gmi-ad0-pg0 {
712 nvidia,pins = "gmi_ad0_pg0",
713 "gmi_ad2_pg2",
714 "gmi_ad3_pg3",
715 "gmi_ad4_pg4",
716 "gmi_ad5_pg5",
717 "gmi_ad6_pg6",
718 "gmi_ad7_pg7",
719 "gmi_ad8_ph0",
720 "gmi_ad9_ph1",
721 "gmi_ad10_ph2",
722 "gmi_ad11_ph3",
723 "gmi_ad12_ph4",
724 "gmi_ad13_ph5",
725 "gmi_ad14_ph6",
726 "gmi_ad15_ph7",
727 "gmi_adv_n_pk0",
728 "gmi_clk_pk1",
729 "gmi_cs4_n_pk2",
730 "gmi_cs2_n_pk3",
731 "gmi_dqs_pi2",
732 "gmi_iordy_pi5",
733 "gmi_oe_n_pi1",
734 "gmi_wait_pi7",
735 "gmi_wr_n_pi0",
736 "lcd_cs1_n_pw0",
737 "pu0",
738 "pu1",
739 "pu2";
740 nvidia,function = "rsvd4";
741 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
742 nvidia,tristate = <TEGRA_PIN_ENABLE>;
743 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
744 };
745 gmi-cs0-n-pj0 {
746 nvidia,pins = "gmi_cs0_n_pj0",
747 "gmi_cs1_n_pj2",
748 "gmi_cs3_n_pk4";
749 nvidia,function = "rsvd1";
750 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
751 nvidia,tristate = <TEGRA_PIN_ENABLE>;
752 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
753 };
754 gmi-cs6-n-pi3 {
755 nvidia,pins = "gmi_cs6_n_pi3";
756 nvidia,function = "sata";
757 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
758 nvidia,tristate = <TEGRA_PIN_ENABLE>;
759 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
760 };
761 gmi-cs7-n-pi6 {
762 nvidia,pins = "gmi_cs7_n_pi6";
763 nvidia,function = "gmi_alt";
764 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
765 nvidia,tristate = <TEGRA_PIN_ENABLE>;
766 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
767 };
768 lcd-pwr0-pb2 {
769 nvidia,pins = "lcd_pwr0_pb2",
770 "lcd_pwr2_pc6",
771 "lcd_wr_n_pz3";
772 nvidia,function = "hdcp";
773 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
774 nvidia,tristate = <TEGRA_PIN_ENABLE>;
775 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
776 };
777 uart2-cts-n-pj5 {
778 nvidia,pins = "uart2_cts_n_pj5",
779 "uart2_rts_n_pj6";
780 nvidia,function = "gmi";
781 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
782 nvidia,tristate = <TEGRA_PIN_ENABLE>;
783 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
406 }; 784 };
407 785
408 /* Power I2C (On-module) */ 786 /* Power I2C (On-module) */
409 pwr_i2c_scl_pz6 { 787 pwr-i2c-scl-pz6 {
410 nvidia,pins = "pwr_i2c_scl_pz6", 788 nvidia,pins = "pwr_i2c_scl_pz6",
411 "pwr_i2c_sda_pz7"; 789 "pwr_i2c_sda_pz7";
412 nvidia,function = "i2cpwr"; 790 nvidia,function = "i2cpwr";
413 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 791 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
414 nvidia,tristate = <TEGRA_PIN_DISABLE>; 792 nvidia,tristate = <TEGRA_PIN_DISABLE>;
415 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 793 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
416 nvidia,lock = <TEGRA_PIN_DISABLE>;
417 nvidia,open-drain = <TEGRA_PIN_ENABLE>; 794 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
418 }; 795 };
419 796
@@ -422,15 +799,15 @@
422 * temperature sensor therefore requires disabling for 799 * temperature sensor therefore requires disabling for
423 * now 800 * now
424 */ 801 */
425 lcd_dc1_pd2 { 802 lcd-dc1-pd2 {
426 nvidia,pins = "lcd_dc1_pd2"; 803 nvidia,pins = "lcd_dc1_pd2";
427 nvidia,function = "rsvd3"; 804 nvidia,function = "rsvd3";
428 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 805 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
429 nvidia,tristate = <TEGRA_PIN_DISABLE>; 806 nvidia,tristate = <TEGRA_PIN_ENABLE>;
430 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 807 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
431 }; 808 };
432 809
433 /* TOUCH_PEN_INT# */ 810 /* TOUCH_PEN_INT# (On-module) */
434 pv0 { 811 pv0 {
435 nvidia,pins = "pv0"; 812 nvidia,pins = "pv0";
436 nvidia,function = "rsvd1"; 813 nvidia,function = "rsvd1";
@@ -441,7 +818,19 @@
441 }; 818 };
442 }; 819 };
443 820
444 hdmiddc: i2c@7000c700 { 821 serial@70006040 {
822 compatible = "nvidia,tegra30-hsuart";
823 };
824
825 serial@70006200 {
826 compatible = "nvidia,tegra30-hsuart";
827 };
828
829 serial@70006300 {
830 compatible = "nvidia,tegra30-hsuart";
831 };
832
833 hdmi_ddc: i2c@7000c700 {
445 clock-frequency = <10000>; 834 clock-frequency = <10000>;
446 }; 835 };
447 836
@@ -457,12 +846,13 @@
457 sgtl5000: codec@a { 846 sgtl5000: codec@a {
458 compatible = "fsl,sgtl5000"; 847 compatible = "fsl,sgtl5000";
459 reg = <0x0a>; 848 reg = <0x0a>;
460 VDDA-supply = <&sys_3v3_reg>; 849 VDDA-supply = <&reg_module_3v3_audio>;
461 VDDIO-supply = <&sys_3v3_reg>; 850 VDDD-supply = <&reg_1v8_vio>;
851 VDDIO-supply = <&reg_module_3v3>;
462 clocks = <&tegra_car TEGRA30_CLK_EXTERN1>; 852 clocks = <&tegra_car TEGRA30_CLK_EXTERN1>;
463 }; 853 };
464 854
465 pmic: tps65911@2d { 855 pmic: pmic@2d {
466 compatible = "ti,tps65911"; 856 compatible = "ti,tps65911";
467 reg = <0x2d>; 857 reg = <0x2d>;
468 858
@@ -475,43 +865,38 @@
475 #gpio-cells = <2>; 865 #gpio-cells = <2>;
476 gpio-controller; 866 gpio-controller;
477 867
478 vcc1-supply = <&sys_3v3_reg>; 868 vcc1-supply = <&reg_module_3v3>;
479 vcc2-supply = <&sys_3v3_reg>; 869 vcc2-supply = <&reg_module_3v3>;
480 vcc3-supply = <&vio_reg>; 870 vcc3-supply = <&reg_1v8_vio>;
481 vcc4-supply = <&sys_3v3_reg>; 871 vcc4-supply = <&reg_module_3v3>;
482 vcc5-supply = <&sys_3v3_reg>; 872 vcc5-supply = <&reg_module_3v3>;
483 vcc6-supply = <&vio_reg>; 873 vcc6-supply = <&reg_1v8_vio>;
484 vcc7-supply = <&charge_pump_5v0_reg>; 874 vcc7-supply = <&reg_5v0_charge_pump>;
485 vccio-supply = <&sys_3v3_reg>; 875 vccio-supply = <&reg_module_3v3>;
486 876
487 regulators { 877 regulators {
488 /* SW1: +V1.35_VDDIO_DDR */
489 vdd1_reg: vdd1 { 878 vdd1_reg: vdd1 {
490 regulator-name = "vddio_ddr_1v35"; 879 regulator-name = "+V1.35_VDDIO_DDR";
491 regulator-min-microvolt = <1350000>; 880 regulator-min-microvolt = <1350000>;
492 regulator-max-microvolt = <1350000>; 881 regulator-max-microvolt = <1350000>;
493 regulator-always-on; 882 regulator-always-on;
494 }; 883 };
495 884
496 /* SW2: +V1.05 */
497 vdd2_reg: vdd2 { 885 vdd2_reg: vdd2 {
498 regulator-name = 886 regulator-name = "+V1.05";
499 "vdd_pexa,vdd_pexb,vdd_sata";
500 regulator-min-microvolt = <1050000>; 887 regulator-min-microvolt = <1050000>;
501 regulator-max-microvolt = <1050000>; 888 regulator-max-microvolt = <1050000>;
502 }; 889 };
503 890
504 /* SW CTRL: +V1.0_VDD_CPU */
505 vddctrl_reg: vddctrl { 891 vddctrl_reg: vddctrl {
506 regulator-name = "vdd_cpu,vdd_sys"; 892 regulator-name = "+V1.0_VDD_CPU";
507 regulator-min-microvolt = <1150000>; 893 regulator-min-microvolt = <1150000>;
508 regulator-max-microvolt = <1150000>; 894 regulator-max-microvolt = <1150000>;
509 regulator-always-on; 895 regulator-always-on;
510 }; 896 };
511 897
512 /* SWIO: +V1.8 */ 898 reg_1v8_vio: vio {
513 vio_reg: vio { 899 regulator-name = "+V1.8";
514 regulator-name = "vdd_1v8_gen";
515 regulator-min-microvolt = <1800000>; 900 regulator-min-microvolt = <1800000>;
516 regulator-max-microvolt = <1800000>; 901 regulator-max-microvolt = <1800000>;
517 regulator-always-on; 902 regulator-always-on;
@@ -521,27 +906,24 @@
521 906
522 /* 907 /*
523 * EN_+V3.3 switching via FET: 908 * EN_+V3.3 switching via FET:
524 * +V3.3_AUDIO_AVDD_S, +V3.3 and +V1.8_VDD_LAN 909 * +V3.3_AUDIO_AVDD_S, +V3.3
525 * see also v3_3 fixed supply 910 * see also +V3.3 fixed supply
526 */ 911 */
527 ldo2_reg: ldo2 { 912 ldo2_reg: ldo2 {
528 regulator-name = "en_3v3"; 913 regulator-name = "EN_+V3.3";
529 regulator-min-microvolt = <3300000>; 914 regulator-min-microvolt = <3300000>;
530 regulator-max-microvolt = <3300000>; 915 regulator-max-microvolt = <3300000>;
531 regulator-always-on; 916 regulator-always-on;
532 }; 917 };
533 918
534 /* +V1.2_CSI */
535 ldo3_reg: ldo3 { 919 ldo3_reg: ldo3 {
536 regulator-name = 920 regulator-name = "+V1.2_CSI";
537 "avdd_dsi_csi,pwrdet_mipi";
538 regulator-min-microvolt = <1200000>; 921 regulator-min-microvolt = <1200000>;
539 regulator-max-microvolt = <1200000>; 922 regulator-max-microvolt = <1200000>;
540 }; 923 };
541 924
542 /* +V1.2_VDD_RTC */
543 ldo4_reg: ldo4 { 925 ldo4_reg: ldo4 {
544 regulator-name = "vdd_rtc"; 926 regulator-name = "+V1.2_VDD_RTC";
545 regulator-min-microvolt = <1200000>; 927 regulator-min-microvolt = <1200000>;
546 regulator-max-microvolt = <1200000>; 928 regulator-max-microvolt = <1200000>;
547 regulator-always-on; 929 regulator-always-on;
@@ -549,10 +931,10 @@
549 931
550 /* 932 /*
551 * +V2.8_AVDD_VDAC: 933 * +V2.8_AVDD_VDAC:
552 * only required for analog RGB 934 * only required for (unsupported) analog RGB
553 */ 935 */
554 ldo5_reg: ldo5 { 936 ldo5_reg: ldo5 {
555 regulator-name = "avdd_vdac"; 937 regulator-name = "+V2.8_AVDD_VDAC";
556 regulator-min-microvolt = <2800000>; 938 regulator-min-microvolt = <2800000>;
557 regulator-max-microvolt = <2800000>; 939 regulator-max-microvolt = <2800000>;
558 regulator-always-on; 940 regulator-always-on;
@@ -564,22 +946,20 @@
564 * granularity 946 * granularity
565 */ 947 */
566 ldo6_reg: ldo6 { 948 ldo6_reg: ldo6 {
567 regulator-name = "avdd_plle"; 949 regulator-name = "+V1.05_AVDD_PLLE";
568 regulator-min-microvolt = <1100000>; 950 regulator-min-microvolt = <1100000>;
569 regulator-max-microvolt = <1100000>; 951 regulator-max-microvolt = <1100000>;
570 }; 952 };
571 953
572 /* +V1.2_AVDD_PLL */
573 ldo7_reg: ldo7 { 954 ldo7_reg: ldo7 {
574 regulator-name = "avdd_pll"; 955 regulator-name = "+V1.2_AVDD_PLL";
575 regulator-min-microvolt = <1200000>; 956 regulator-min-microvolt = <1200000>;
576 regulator-max-microvolt = <1200000>; 957 regulator-max-microvolt = <1200000>;
577 regulator-always-on; 958 regulator-always-on;
578 }; 959 };
579 960
580 /* +V1.0_VDD_DDR_HS */
581 ldo8_reg: ldo8 { 961 ldo8_reg: ldo8 {
582 regulator-name = "vdd_ddr_hs"; 962 regulator-name = "+V1.0_VDD_DDR_HS";
583 regulator-min-microvolt = <1000000>; 963 regulator-min-microvolt = <1000000>;
584 regulator-max-microvolt = <1000000>; 964 regulator-max-microvolt = <1000000>;
585 regulator-always-on; 965 regulator-always-on;
@@ -588,11 +968,10 @@
588 }; 968 };
589 969
590 /* STMPE811 touch screen controller */ 970 /* STMPE811 touch screen controller */
591 stmpe811@41 { 971 touchscreen@41 {
592 compatible = "st,stmpe811"; 972 compatible = "st,stmpe811";
593 reg = <0x41>; 973 reg = <0x41>;
594 interrupts = <TEGRA_GPIO(V, 0) IRQ_TYPE_LEVEL_LOW>; 974 irq-gpio = <&gpio TEGRA_GPIO(V, 0) IRQ_TYPE_LEVEL_LOW>;
595 interrupt-parent = <&gpio>;
596 interrupt-controller; 975 interrupt-controller;
597 id = <0>; 976 id = <0>;
598 blocks = <0x5>; 977 blocks = <0x5>;
@@ -626,7 +1005,7 @@
626 1005
627 /* 1006 /*
628 * LM95245 temperature sensor 1007 * LM95245 temperature sensor
629 * Note: OVERT_N directly connected to PMIC PWRDN 1008 * Note: OVERT1# directly connected to TPS65911 PMIC PWRDN
630 */ 1009 */
631 temp-sensor@4c { 1010 temp-sensor@4c {
632 compatible = "national,lm95245"; 1011 compatible = "national,lm95245";
@@ -634,7 +1013,7 @@
634 }; 1013 };
635 1014
636 /* SW: +V1.2_VDD_CORE */ 1015 /* SW: +V1.2_VDD_CORE */
637 tps62362@60 { 1016 regulator@60 {
638 compatible = "ti,tps62362"; 1017 compatible = "ti,tps62362";
639 reg = <0x60>; 1018 reg = <0x60>;
640 1019
@@ -659,7 +1038,7 @@
659 reg = <1>; 1038 reg = <1>;
660 clocks = <&clk16m>; 1039 clocks = <&clk16m>;
661 interrupt-parent = <&gpio>; 1040 interrupt-parent = <&gpio>;
662 interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_EDGE_RISING>; 1041 interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_EDGE_FALLING>;
663 spi-max-frequency = <10000000>; 1042 spi-max-frequency = <10000000>;
664 }; 1043 };
665 }; 1044 };
@@ -674,7 +1053,7 @@
674 reg = <0>; 1053 reg = <0>;
675 clocks = <&clk16m>; 1054 clocks = <&clk16m>;
676 interrupt-parent = <&gpio>; 1055 interrupt-parent = <&gpio>;
677 interrupts = <TEGRA_GPIO(W, 2) IRQ_TYPE_EDGE_RISING>; 1056 interrupts = <TEGRA_GPIO(W, 2) IRQ_TYPE_EDGE_FALLING>;
678 spi-max-frequency = <10000000>; 1057 spi-max-frequency = <10000000>;
679 }; 1058 };
680 }; 1059 };
@@ -688,6 +1067,18 @@
688 nvidia,core-pwr-off-time = <0>; 1067 nvidia,core-pwr-off-time = <0>;
689 nvidia,core-power-req-active-high; 1068 nvidia,core-power-req-active-high;
690 nvidia,sys-clock-req-active-high; 1069 nvidia,sys-clock-req-active-high;
1070
1071 /* Set DEV_OFF bit in DCDC control register of TPS65911 PMIC */
1072 i2c-thermtrip {
1073 nvidia,i2c-controller-id = <4>;
1074 nvidia,bus-addr = <0x2d>;
1075 nvidia,reg-addr = <0x3f>;
1076 nvidia,reg-data = <0x1>;
1077 };
1078 };
1079
1080 hda@70030000 {
1081 status = "okay";
691 }; 1082 };
692 1083
693 ahub@70080000 { 1084 ahub@70080000 {
@@ -701,73 +1092,65 @@
701 status = "okay"; 1092 status = "okay";
702 bus-width = <8>; 1093 bus-width = <8>;
703 non-removable; 1094 non-removable;
1095 vmmc-supply = <&reg_module_3v3>; /* VCC */
1096 vqmmc-supply = <&reg_1v8_vio>; /* VCCQ */
1097 mmc-ddr-1_8v;
704 }; 1098 };
705 1099
706 clocks { 1100 clk32k_in: xtal1 {
707 compatible = "simple-bus"; 1101 compatible = "fixed-clock";
708 #address-cells = <1>; 1102 #clock-cells = <0>;
709 #size-cells = <0>; 1103 clock-frequency = <32768>;
1104 };
710 1105
711 clk32k_in: clk@0 { 1106 clk16m: osc4 {
712 compatible = "fixed-clock"; 1107 compatible = "fixed-clock";
713 reg = <0>; 1108 #clock-cells = <0>;
714 #clock-cells = <0>; 1109 clock-frequency = <16000000>;
715 clock-frequency = <32768>; 1110 };
716 };
717 1111
718 clk16m: clk@1 { 1112 reg_1v8_avdd_hdmi_pll: regulator-1v8-avdd-hdmi-pll {
719 compatible = "fixed-clock"; 1113 compatible = "regulator-fixed";
720 reg = <1>; 1114 regulator-name = "+V1.8_AVDD_HDMI_PLL";
721 #clock-cells = <0>; 1115 regulator-min-microvolt = <1800000>;
722 clock-frequency = <16000000>; 1116 regulator-max-microvolt = <1800000>;
723 clock-output-names = "clk16m"; 1117 enable-active-high;
724 }; 1118 gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
1119 vin-supply = <&reg_1v8_vio>;
725 }; 1120 };
726 1121
727 regulators { 1122 reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi {
728 compatible = "simple-bus"; 1123 compatible = "regulator-fixed";
729 #address-cells = <1>; 1124 regulator-name = "+V3.3_AVDD_HDMI";
730 #size-cells = <0>; 1125 regulator-min-microvolt = <3300000>;
731 1126 regulator-max-microvolt = <3300000>;
732 avdd_hdmi_pll_1v8_reg: regulator@100 { 1127 enable-active-high;
733 compatible = "regulator-fixed"; 1128 gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
734 reg = <100>; 1129 vin-supply = <&reg_module_3v3>;
735 regulator-name = "+V1.8_AVDD_HDMI_PLL"; 1130 };
736 regulator-min-microvolt = <1800000>;
737 regulator-max-microvolt = <1800000>;
738 enable-active-high;
739 gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
740 vin-supply = <&vio_reg>;
741 };
742 1131
743 sys_3v3_reg: regulator@101 { 1132 reg_5v0_charge_pump: regulator-5v0-charge-pump {
744 compatible = "regulator-fixed"; 1133 compatible = "regulator-fixed";
745 reg = <101>; 1134 regulator-name = "+V5.0";
746 regulator-name = "3v3"; 1135 regulator-min-microvolt = <5000000>;
747 regulator-min-microvolt = <3300000>; 1136 regulator-max-microvolt = <5000000>;
748 regulator-max-microvolt = <3300000>; 1137 regulator-always-on;
749 regulator-always-on; 1138 };
750 };
751 1139
752 avdd_hdmi_3v3_reg: regulator@102 { 1140 reg_module_3v3: regulator-module-3v3 {
753 compatible = "regulator-fixed"; 1141 compatible = "regulator-fixed";
754 reg = <102>; 1142 regulator-name = "+V3.3";
755 regulator-name = "+V3.3_AVDD_HDMI"; 1143 regulator-min-microvolt = <3300000>;
756 regulator-min-microvolt = <3300000>; 1144 regulator-max-microvolt = <3300000>;
757 regulator-max-microvolt = <3300000>; 1145 regulator-always-on;
758 enable-active-high; 1146 };
759 gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
760 vin-supply = <&sys_3v3_reg>;
761 };
762 1147
763 charge_pump_5v0_reg: regulator@103 { 1148 reg_module_3v3_audio: regulator-module-3v3-audio {
764 compatible = "regulator-fixed"; 1149 compatible = "regulator-fixed";
765 reg = <103>; 1150 regulator-name = "+V3.3_AUDIO_AVDD_S";
766 regulator-name = "5v0"; 1151 regulator-min-microvolt = <3300000>;
767 regulator-min-microvolt = <5000000>; 1152 regulator-max-microvolt = <3300000>;
768 regulator-max-microvolt = <5000000>; 1153 regulator-always-on;
769 regulator-always-on;
770 };
771 }; 1154 };
772 1155
773 sound { 1156 sound {
diff --git a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts
index 16e1f387aa6d..5965150ecdd2 100644
--- a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts
+++ b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts
@@ -1,15 +1,17 @@
1// SPDX-License-Identifier: GPL-2.0 1// SPDX-License-Identifier: GPL-2.0
2/dts-v1/; 2/dts-v1/;
3 3
4#include <dt-bindings/input/input.h>
4#include "tegra30-colibri.dtsi" 5#include "tegra30-colibri.dtsi"
5 6
6/ { 7/ {
7 model = "Toradex Colibri T30 on Colibri Evaluation Board"; 8 model = "Toradex Colibri T30 on Colibri Evaluation Board";
8 compatible = "toradex,colibri_t30-eval-v3", "toradex,colibri_t30", "nvidia,tegra30"; 9 compatible = "toradex,colibri_t30-eval-v3", "toradex,colibri_t30",
10 "nvidia,tegra30";
9 11
10 aliases { 12 aliases {
11 rtc0 = "/i2c@7000c000/rtc@68"; 13 rtc0 = "/i2c@7000c000/rtc@68";
12 rtc1 = "/i2c@7000d000/tps65911@2d"; 14 rtc1 = "/i2c@7000d000/pmic@2d";
13 rtc2 = "/rtc@7000e000"; 15 rtc2 = "/rtc@7000e000";
14 serial0 = &uarta; 16 serial0 = &uarta;
15 serial1 = &uartb; 17 serial1 = &uartb;
@@ -27,22 +29,25 @@
27 nvidia,panel = <&panel>; 29 nvidia,panel = <&panel>;
28 }; 30 };
29 }; 31 };
32
30 hdmi@54280000 { 33 hdmi@54280000 {
31 status = "okay"; 34 status = "okay";
35 hdmi-supply = <&reg_5v0>;
32 }; 36 };
33 }; 37 };
34 38
39 /* Colibri UART-A */
35 serial@70006000 { 40 serial@70006000 {
36 status = "okay"; 41 status = "okay";
37 }; 42 };
38 43
44 /* Colibri UART-C */
39 serial@70006040 { 45 serial@70006040 {
40 compatible = "nvidia,tegra30-hsuart";
41 status = "okay"; 46 status = "okay";
42 }; 47 };
43 48
49 /* Colibri UART-B */
44 serial@70006300 { 50 serial@70006300 {
45 compatible = "nvidia,tegra30-hsuart";
46 status = "okay"; 51 status = "okay";
47 }; 52 };
48 53
@@ -65,8 +70,12 @@
65 }; 70 };
66 }; 71 };
67 72
73 /* GEN2_I2C: unused */
74
75 /* CAM_I2C (I2C3): unused */
76
68 /* DDC_CLOCK/DATA on X3 pin 15/16 (e.g. display EDID) */ 77 /* DDC_CLOCK/DATA on X3 pin 15/16 (e.g. display EDID) */
69 hdmiddc: i2c@7000c700 { 78 i2c@7000c700 {
70 status = "okay"; 79 status = "okay";
71 }; 80 };
72 81
@@ -74,18 +83,17 @@
74 spi@7000d400 { 83 spi@7000d400 {
75 status = "okay"; 84 status = "okay";
76 spi-max-frequency = <25000000>; 85 spi-max-frequency = <25000000>;
77 can0: can@0 { 86
87 can@0 {
78 compatible = "microchip,mcp2515"; 88 compatible = "microchip,mcp2515";
79 reg = <0>; 89 reg = <0>;
80 clocks = <&clk16m>; 90 clocks = <&clk16m>;
81 interrupt-parent = <&gpio>; 91 interrupt-parent = <&gpio>;
82 interrupts = <TEGRA_GPIO(S, 0) IRQ_TYPE_EDGE_RISING>; 92 /* CAN_INT */
93 interrupts = <TEGRA_GPIO(S, 0) IRQ_TYPE_EDGE_FALLING>;
83 spi-max-frequency = <10000000>; 94 spi-max-frequency = <10000000>;
84 }; 95 vdd-supply = <&reg_3v3>;
85 spidev0: spi@1 { 96 xceiver-supply = <&reg_5v0>;
86 compatible = "spidev";
87 reg = <1>;
88 spi-max-frequency = <25000000>;
89 }; 97 };
90 }; 98 };
91 99
@@ -93,19 +101,19 @@
93 sdhci@78000200 { 101 sdhci@78000200 {
94 status = "okay"; 102 status = "okay";
95 bus-width = <4>; 103 bus-width = <4>;
96 cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>; 104 cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>; /* MMCD */
97 no-1-8-v; 105 no-1-8-v;
98 }; 106 };
99 107
100 /* EHCI instance 0: USB1_DP/N -> USBC_P/N */ 108 /* EHCI instance 0: USB1_DP/N -> USBC_P/N */
101 usb@7d000000 { 109 usb@7d000000 {
102 status = "okay"; 110 status = "okay";
111 dr_mode = "otg";
103 }; 112 };
104 113
105 usb-phy@7d000000 { 114 usb-phy@7d000000 {
106 status = "okay"; 115 status = "okay";
107 dr_mode = "otg"; 116 vbus-supply = <&reg_usbc_vbus>;
108 vbus-supply = <&usbc_vbus_reg>;
109 }; 117 };
110 118
111 /* EHCI instance 2: USB3_DP/N -> USBH_P/N */ 119 /* EHCI instance 2: USB3_DP/N -> USBH_P/N */
@@ -115,28 +123,23 @@
115 123
116 usb-phy@7d008000 { 124 usb-phy@7d008000 {
117 status = "okay"; 125 status = "okay";
118 vbus-supply = <&usbh_vbus_reg>; 126 vbus-supply = <&reg_usbh_vbus>;
119 }; 127 };
120 128
121 backlight: backlight { 129 backlight: backlight {
122 compatible = "pwm-backlight"; 130 compatible = "pwm-backlight";
123
124 /* PWM<A> */
125 pwms = <&pwm 0 5000000>;
126 brightness-levels = <255 128 64 32 16 8 4 0>; 131 brightness-levels = <255 128 64 32 16 8 4 0>;
127 default-brightness-level = <6>; 132 default-brightness-level = <6>;
128 /* BL_ON */ 133 /* BL_ON */
129 enable-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; 134 enable-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
135 power-supply = <&reg_3v3>;
136 pwms = <&pwm 0 5000000>; /* PWM<A> */
130 }; 137 };
131 138
132 clocks { 139 clk16m: osc3 {
133 clk16m: clk@1 { 140 compatible = "fixed-clock";
134 compatible = "fixed-clock"; 141 #clock-cells = <0>;
135 reg = <1>; 142 clock-frequency = <16000000>;
136 #clock-cells = <0>;
137 clock-frequency = <16000000>;
138 clock-output-names = "clk16m";
139 };
140 }; 143 };
141 144
142 gpio-keys { 145 gpio-keys {
@@ -157,58 +160,39 @@
157 * edt,et070080dh6: EDT 7.0" LCD TFT 160 * edt,et070080dh6: EDT 7.0" LCD TFT
158 */ 161 */
159 compatible = "edt,et057090dhu", "simple-panel"; 162 compatible = "edt,et057090dhu", "simple-panel";
160
161 backlight = <&backlight>; 163 backlight = <&backlight>;
164 power-supply = <&reg_3v3>;
162 }; 165 };
163 166
164 pwmleds { 167 reg_3v3: regulator-3v3 {
165 compatible = "pwm-leds"; 168 compatible = "regulator-fixed";
166 169 regulator-name = "3.3V_SW";
167 pwmb { 170 regulator-min-microvolt = <3300000>;
168 label = "PWM<B>"; 171 regulator-max-microvolt = <3300000>;
169 pwms = <&pwm 1 19600>;
170 max-brightness = <255>;
171 };
172 pwmc {
173 label = "PWM<C>";
174 pwms = <&pwm 2 19600>;
175 max-brightness = <255>;
176 };
177 pwmd {
178 label = "PWM<D>";
179 pwms = <&pwm 3 19600>;
180 max-brightness = <255>;
181 };
182 }; 172 };
183 173
184 regulators { 174 reg_5v0: regulator-5v0 {
185 sys_5v0_reg: regulator@1 { 175 compatible = "regulator-fixed";
186 compatible = "regulator-fixed"; 176 regulator-name = "5V_SW";
187 reg = <1>; 177 regulator-min-microvolt = <5000000>;
188 regulator-name = "5v0"; 178 regulator-max-microvolt = <5000000>;
189 regulator-min-microvolt = <5000000>; 179 };
190 regulator-max-microvolt = <5000000>;
191 regulator-always-on;
192 };
193 180
194 usbc_vbus_reg: regulator@2 { 181 reg_usbc_vbus: regulator-usbc-vbus {
195 compatible = "regulator-fixed"; 182 compatible = "regulator-fixed";
196 reg = <2>; 183 regulator-name = "VCC_USB5";
197 regulator-name = "usbc_vbus"; 184 regulator-min-microvolt = <5000000>;
198 regulator-min-microvolt = <5000000>; 185 regulator-max-microvolt = <5000000>;
199 regulator-max-microvolt = <5000000>; 186 vin-supply = <&reg_5v0>;
200 vin-supply = <&sys_5v0_reg>; 187 };
201 };
202 188
203 /* USBH_PEN */ 189 /* USBH_PEN resp. USB_P_EN */
204 usbh_vbus_reg: regulator@3 { 190 reg_usbh_vbus: regulator-usbh-vbus {
205 compatible = "regulator-fixed"; 191 compatible = "regulator-fixed";
206 reg = <3>; 192 regulator-name = "VCC_USB[1-4]";
207 regulator-name = "usbh_vbus"; 193 regulator-min-microvolt = <5000000>;
208 regulator-min-microvolt = <5000000>; 194 regulator-max-microvolt = <5000000>;
209 regulator-max-microvolt = <5000000>; 195 gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
210 gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; 196 vin-supply = <&reg_5v0>;
211 vin-supply = <&sys_5v0_reg>;
212 };
213 }; 197 };
214}; 198};
diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi b/arch/arm/boot/dts/tegra30-colibri.dtsi
index 526ed71cf7a3..35af03ca9e90 100644
--- a/arch/arm/boot/dts/tegra30-colibri.dtsi
+++ b/arch/arm/boot/dts/tegra30-colibri.dtsi
@@ -1,27 +1,22 @@
1// SPDX-License-Identifier: GPL-2.0 1// SPDX-License-Identifier: GPL-2.0
2#include <dt-bindings/input/input.h>
3#include "tegra30.dtsi" 2#include "tegra30.dtsi"
4 3
5/* 4/*
6 * Toradex Colibri T30 Module Device Tree 5 * Toradex Colibri T30 Module Device Tree
7 * Compatible for Revisions V1.1B, V1.1C, V1.1D, V1.1E; IT: V1.1A 6 * Compatible for Revisions V1.1B, V1.1C, V1.1D, V1.1E, V1.1F; IT: V1.1A, V1.1B
8 */ 7 */
9/ { 8/ {
10 model = "Toradex Colibri T30";
11 compatible = "toradex,colibri_t30", "nvidia,tegra30";
12
13 memory@80000000 { 9 memory@80000000 {
14 reg = <0x80000000 0x40000000>; 10 reg = <0x80000000 0x40000000>;
15 }; 11 };
16 12
17 host1x@50000000 { 13 host1x@50000000 {
18 hdmi@54280000 { 14 hdmi@54280000 {
19 vdd-supply = <&avdd_hdmi_3v3_reg>; 15 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
20 pll-supply = <&avdd_hdmi_pll_1v8_reg>;
21
22 nvidia,hpd-gpio = 16 nvidia,hpd-gpio =
23 <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; 17 <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
24 nvidia,ddc-i2c-bus = <&hdmiddc>; 18 pll-supply = <&reg_1v8_avdd_hdmi_pll>;
19 vdd-supply = <&reg_3v3_avdd_hdmi>;
25 }; 20 };
26 }; 21 };
27 22
@@ -31,23 +26,173 @@
31 26
32 state_default: pinmux { 27 state_default: pinmux {
33 /* Analogue Audio (On-module) */ 28 /* Analogue Audio (On-module) */
34 clk1_out_pw4 { 29 clk1-out-pw4 {
35 nvidia,pins = "clk1_out_pw4"; 30 nvidia,pins = "clk1_out_pw4";
36 nvidia,function = "extperiph1"; 31 nvidia,function = "extperiph1";
37 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 32 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
38 nvidia,tristate = <TEGRA_PIN_DISABLE>; 33 nvidia,tristate = <TEGRA_PIN_DISABLE>;
39 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 34 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
40 }; 35 };
41 dap3_fs_pp0 { 36 dap3-fs-pp0 {
42 nvidia,pins = "dap3_fs_pp0", 37 nvidia,pins = "dap3_fs_pp0",
43 "dap3_sclk_pp3", 38 "dap3_sclk_pp3",
44 "dap3_din_pp1", 39 "dap3_din_pp1",
45 "dap3_dout_pp2"; 40 "dap3_dout_pp2";
46 nvidia,function = "i2s2"; 41 nvidia,function = "i2s2";
47 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 42 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
48 nvidia,tristate = <TEGRA_PIN_DISABLE>; 43 nvidia,tristate = <TEGRA_PIN_DISABLE>;
49 }; 44 };
50 45
46 /* Colibri Address/Data Bus (GMI) */
47 gmi-ad0-pg0 {
48 nvidia,pins = "gmi_ad0_pg0",
49 "gmi_ad2_pg2",
50 "gmi_ad3_pg3",
51 "gmi_ad4_pg4",
52 "gmi_ad5_pg5",
53 "gmi_ad6_pg6",
54 "gmi_ad7_pg7",
55 "gmi_ad8_ph0",
56 "gmi_ad9_ph1",
57 "gmi_ad10_ph2",
58 "gmi_ad11_ph3",
59 "gmi_ad12_ph4",
60 "gmi_ad13_ph5",
61 "gmi_ad14_ph6",
62 "gmi_ad15_ph7",
63 "gmi_adv_n_pk0",
64 "gmi_clk_pk1",
65 "gmi_cs4_n_pk2",
66 "gmi_cs2_n_pk3",
67 "gmi_iordy_pi5",
68 "gmi_oe_n_pi1",
69 "gmi_wait_pi7",
70 "gmi_wr_n_pi0",
71 "dap1_fs_pn0",
72 "dap1_din_pn1",
73 "dap1_dout_pn2",
74 "dap1_sclk_pn3",
75 "dap2_fs_pa2",
76 "dap2_sclk_pa3",
77 "dap2_din_pa4",
78 "dap2_dout_pa5",
79 "spi1_sck_px5",
80 "spi1_mosi_px4",
81 "spi1_cs0_n_px6",
82 "spi2_cs0_n_px3",
83 "spi2_miso_px1",
84 "spi2_mosi_px0",
85 "spi2_sck_px2",
86 "uart2_cts_n_pj5",
87 "uart2_rts_n_pj6";
88 nvidia,function = "gmi";
89 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
90 nvidia,tristate = <TEGRA_PIN_DISABLE>;
91 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
92 };
93 /* Further pins may be used as GPIOs */
94 dap4-din-pp5 {
95 nvidia,pins = "dap4_din_pp5",
96 "dap4_dout_pp6",
97 "dap4_fs_pp4",
98 "dap4_sclk_pp7",
99 "pbb7",
100 "sdmmc1_clk_pz0",
101 "sdmmc1_cmd_pz1",
102 "sdmmc1_dat0_py7",
103 "sdmmc1_dat1_py6",
104 "sdmmc1_dat3_py4",
105 "uart3_cts_n_pa1",
106 "uart3_txd_pw6",
107 "uart3_rxd_pw7";
108 nvidia,function = "rsvd2";
109 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
110 nvidia,tristate = <TEGRA_PIN_DISABLE>;
111 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
112 };
113 lcd-d18-pm2 {
114 nvidia,pins = "lcd_d18_pm2",
115 "lcd_d19_pm3",
116 "lcd_d20_pm4",
117 "lcd_d21_pm5",
118 "lcd_d22_pm6",
119 "lcd_d23_pm7",
120 "lcd_dc0_pn6",
121 "pex_l2_clkreq_n_pcc7";
122 nvidia,function = "rsvd3";
123 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
124 nvidia,tristate = <TEGRA_PIN_DISABLE>;
125 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
126 };
127 lcd-cs0-n-pn4 {
128 nvidia,pins = "lcd_cs0_n_pn4",
129 "lcd_sdin_pz2",
130 "pu0",
131 "pu1",
132 "pu2",
133 "pu3",
134 "pu4",
135 "pu5",
136 "pu6",
137 "spi1_miso_px7",
138 "uart3_rts_n_pc0";
139 nvidia,function = "rsvd4";
140 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
141 nvidia,tristate = <TEGRA_PIN_DISABLE>;
142 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
143 };
144 lcd-pwr0-pb2 {
145 nvidia,pins = "lcd_pwr0_pb2",
146 "lcd_sck_pz4",
147 "lcd_sdout_pn5",
148 "lcd_wr_n_pz3";
149 nvidia,function = "hdcp";
150 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
151 nvidia,tristate = <TEGRA_PIN_DISABLE>;
152 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
153 };
154 pbb4 {
155 nvidia,pins = "pbb4",
156 "pbb5",
157 "pbb6";
158 nvidia,function = "displayb";
159 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
160 nvidia,tristate = <TEGRA_PIN_DISABLE>;
161 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
162 };
163 /* Multiplexed RDnWR and therefore disabled */
164 lcd-cs1-n-pw0 {
165 nvidia,pins = "lcd_cs1_n_pw0";
166 nvidia,function = "rsvd4";
167 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
168 nvidia,tristate = <TEGRA_PIN_ENABLE>;
169 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
170 };
171 /* Multiplexed GMI_CLK and therefore disabled */
172 owr {
173 nvidia,pins = "owr";
174 nvidia,function = "rsvd3";
175 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
176 nvidia,tristate = <TEGRA_PIN_ENABLE>;
177 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
178 };
179 /* Tri-stating GMI_WR_N on nPWE SODIMM pin 99 */
180 sdmmc3-dat4-pd1 {
181 nvidia,pins = "sdmmc3_dat4_pd1";
182 nvidia,function = "sdmmc3";
183 nvidia,pull = <TEGRA_PIN_PULL_UP>;
184 nvidia,tristate = <TEGRA_PIN_ENABLE>;
185 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
186 };
187 /* Not tri-stating GMI_WR_N on RDnWR SODIMM pin 93 */
188 sdmmc3-dat5-pd0 {
189 nvidia,pins = "sdmmc3_dat5_pd0";
190 nvidia,function = "sdmmc3";
191 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
192 nvidia,tristate = <TEGRA_PIN_ENABLE>;
193 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
194 };
195
51 /* Colibri BL_ON */ 196 /* Colibri BL_ON */
52 pv2 { 197 pv2 {
53 nvidia,pins = "pv2"; 198 nvidia,pins = "pv2";
@@ -57,7 +202,7 @@
57 }; 202 };
58 203
59 /* Colibri Backlight PWM<A> */ 204 /* Colibri Backlight PWM<A> */
60 sdmmc3_dat3_pb4 { 205 sdmmc3-dat3-pb4 {
61 nvidia,pins = "sdmmc3_dat3_pb4"; 206 nvidia,pins = "sdmmc3_dat3_pb4";
62 nvidia,function = "pwm0"; 207 nvidia,function = "pwm0";
63 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 208 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -65,7 +210,7 @@
65 }; 210 };
66 211
67 /* Colibri CAN_INT */ 212 /* Colibri CAN_INT */
68 kb_row8_ps0 { 213 kb-row8-ps0 {
69 nvidia,pins = "kb_row8_ps0"; 214 nvidia,pins = "kb_row8_ps0";
70 nvidia,function = "kbc"; 215 nvidia,function = "kbc";
71 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 216 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -73,26 +218,133 @@
73 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 218 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
74 }; 219 };
75 220
221 /* Colibri DDC */
222 ddc-scl-pv4 {
223 nvidia,pins = "ddc_scl_pv4",
224 "ddc_sda_pv5";
225 nvidia,function = "i2c4";
226 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
227 nvidia,tristate = <TEGRA_PIN_DISABLE>;
228 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
229 };
230
231 /* Colibri EXT_IO* */
232 gen2-i2c-scl-pt5 {
233 nvidia,pins = "gen2_i2c_scl_pt5",
234 "gen2_i2c_sda_pt6";
235 nvidia,function = "rsvd4";
236 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
237 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
238 nvidia,tristate = <TEGRA_PIN_DISABLE>;
239 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
240 };
241 spdif-in-pk6 {
242 nvidia,pins = "spdif_in_pk6";
243 nvidia,function = "hda";
244 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
245 nvidia,tristate = <TEGRA_PIN_DISABLE>;
246 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
247 };
248
249 /* Colibri GPIO */
250 clk2-out-pw5 {
251 nvidia,pins = "clk2_out_pw5",
252 "pcc2",
253 "pv3",
254 "sdmmc1_dat2_py5";
255 nvidia,function = "rsvd2";
256 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
257 nvidia,tristate = <TEGRA_PIN_DISABLE>;
258 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
259 };
260 lcd-pwr1-pc1 {
261 nvidia,pins = "lcd_pwr1_pc1",
262 "pex_l1_clkreq_n_pdd6",
263 "pex_l1_rst_n_pdd5";
264 nvidia,function = "rsvd3";
265 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
266 nvidia,tristate = <TEGRA_PIN_DISABLE>;
267 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
268 };
269 pv1 {
270 nvidia,pins = "pv1",
271 "sdmmc3_dat0_pb7",
272 "sdmmc3_dat1_pb6";
273 nvidia,function = "rsvd1";
274 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
275 nvidia,tristate = <TEGRA_PIN_DISABLE>;
276 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
277 };
278
279 /* Colibri HOTPLUG_DETECT (HDMI) */
280 hdmi-int-pn7 {
281 nvidia,pins = "hdmi_int_pn7";
282 nvidia,function = "hdmi";
283 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
284 nvidia,tristate = <TEGRA_PIN_ENABLE>;
285 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
286 };
287
288 /* Colibri I2C */
289 gen1-i2c-scl-pc4 {
290 nvidia,pins = "gen1_i2c_scl_pc4",
291 "gen1_i2c_sda_pc5";
292 nvidia,function = "i2c1";
293 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
294 nvidia,tristate = <TEGRA_PIN_DISABLE>;
295 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
296 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
297 };
298
299 /* Colibri LCD (L_* resp. LDD<*>) */
300 lcd-d0-pe0 {
301 nvidia,pins = "lcd_d0_pe0",
302 "lcd_d1_pe1",
303 "lcd_d2_pe2",
304 "lcd_d3_pe3",
305 "lcd_d4_pe4",
306 "lcd_d5_pe5",
307 "lcd_d6_pe6",
308 "lcd_d7_pe7",
309 "lcd_d8_pf0",
310 "lcd_d9_pf1",
311 "lcd_d10_pf2",
312 "lcd_d11_pf3",
313 "lcd_d12_pf4",
314 "lcd_d13_pf5",
315 "lcd_d14_pf6",
316 "lcd_d15_pf7",
317 "lcd_d16_pm0",
318 "lcd_d17_pm1",
319 "lcd_de_pj1",
320 "lcd_hsync_pj3",
321 "lcd_pclk_pb3",
322 "lcd_vsync_pj4";
323 nvidia,function = "displaya";
324 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
325 nvidia,tristate = <TEGRA_PIN_DISABLE>;
326 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
327 };
76 /* 328 /*
77 * Colibri L_BIAS, LCD_M1 is muxed with LCD_DE 329 * Colibri L_BIAS, LCD_M1 is muxed with LCD_DE
78 * todays display need DE, disable LCD_M1 330 * today's display need DE, disable LCD_M1
79 */ 331 */
80 lcd_m1_pw1 { 332 lcd-m1-pw1 {
81 nvidia,pins = "lcd_m1_pw1"; 333 nvidia,pins = "lcd_m1_pw1";
82 nvidia,function = "rsvd3"; 334 nvidia,function = "rsvd3";
83 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 335 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
84 nvidia,tristate = <TEGRA_PIN_DISABLE>; 336 nvidia,tristate = <TEGRA_PIN_ENABLE>;
85 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 337 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
86 }; 338 };
87 339
88 /* Colibri MMC */ 340 /* Colibri MMC */
89 kb_row10_ps2 { 341 kb-row10-ps2 {
90 nvidia,pins = "kb_row10_ps2"; 342 nvidia,pins = "kb_row10_ps2";
91 nvidia,function = "sdmmc2"; 343 nvidia,function = "sdmmc2";
92 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 344 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
93 nvidia,tristate = <TEGRA_PIN_DISABLE>; 345 nvidia,tristate = <TEGRA_PIN_DISABLE>;
94 }; 346 };
95 kb_row11_ps3 { 347 kb-row11-ps3 {
96 nvidia,pins = "kb_row11_ps3", 348 nvidia,pins = "kb_row11_ps3",
97 "kb_row12_ps4", 349 "kb_row12_ps4",
98 "kb_row13_ps5", 350 "kb_row13_ps5",
@@ -102,9 +354,108 @@
102 nvidia,pull = <TEGRA_PIN_PULL_UP>; 354 nvidia,pull = <TEGRA_PIN_PULL_UP>;
103 nvidia,tristate = <TEGRA_PIN_DISABLE>; 355 nvidia,tristate = <TEGRA_PIN_DISABLE>;
104 }; 356 };
357 /* Colibri MMC_CD */
358 gmi-wp-n-pc7 {
359 nvidia,pins = "gmi_wp_n_pc7";
360 nvidia,function = "rsvd1";
361 nvidia,pull = <TEGRA_PIN_PULL_UP>;
362 nvidia,tristate = <TEGRA_PIN_DISABLE>;
363 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
364 };
365 /* Multiplexed and therefore disabled */
366 cam-mclk-pcc0 {
367 nvidia,pins = "cam_mclk_pcc0";
368 nvidia,function = "vi_alt3";
369 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
370 nvidia,tristate = <TEGRA_PIN_ENABLE>;
371 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
372 };
373 cam-i2c-scl-pbb1 {
374 nvidia,pins = "cam_i2c_scl_pbb1",
375 "cam_i2c_sda_pbb2";
376 nvidia,function = "rsvd3";
377 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
378 nvidia,tristate = <TEGRA_PIN_ENABLE>;
379 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
380 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
381 };
382 pbb0 {
383 nvidia,pins = "pbb0",
384 "pcc1";
385 nvidia,function = "rsvd2";
386 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
387 nvidia,tristate = <TEGRA_PIN_ENABLE>;
388 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
389 };
390 pbb3 {
391 nvidia,pins = "pbb3";
392 nvidia,function = "displayb";
393 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
394 nvidia,tristate = <TEGRA_PIN_ENABLE>;
395 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
396 };
397
398 /* Colibri nRESET_OUT */
399 gmi-rst-n-pi4 {
400 nvidia,pins = "gmi_rst_n_pi4";
401 nvidia,function = "gmi";
402 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
403 nvidia,tristate = <TEGRA_PIN_DISABLE>;
404 };
405
406 /*
407 * Colibri Parallel Camera (Optional)
408 * pins multiplexed with others and therefore disabled
409 */
410 vi-vsync-pd6 {
411 nvidia,pins = "vi_d0_pt4",
412 "vi_d1_pd5",
413 "vi_d2_pl0",
414 "vi_d3_pl1",
415 "vi_d4_pl2",
416 "vi_d5_pl3",
417 "vi_d6_pl4",
418 "vi_d7_pl5",
419 "vi_d8_pl6",
420 "vi_d9_pl7",
421 "vi_d10_pt2",
422 "vi_d11_pt3",
423 "vi_hsync_pd7",
424 "vi_mclk_pt1",
425 "vi_pclk_pt0",
426 "vi_vsync_pd6";
427 nvidia,function = "vi";
428 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
429 nvidia,tristate = <TEGRA_PIN_ENABLE>;
430 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
431 };
432
433 /* Colibri PWM<B> */
434 sdmmc3-dat2-pb5 {
435 nvidia,pins = "sdmmc3_dat2_pb5";
436 nvidia,function = "pwm1";
437 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
438 nvidia,tristate = <TEGRA_PIN_DISABLE>;
439 };
440
441 /* Colibri PWM<C> */
442 sdmmc3-clk-pa6 {
443 nvidia,pins = "sdmmc3_clk_pa6";
444 nvidia,function = "pwm2";
445 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
446 nvidia,tristate = <TEGRA_PIN_DISABLE>;
447 };
448
449 /* Colibri PWM<D> */
450 sdmmc3-cmd-pa7 {
451 nvidia,pins = "sdmmc3_cmd_pa7";
452 nvidia,function = "pwm3";
453 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
454 nvidia,tristate = <TEGRA_PIN_DISABLE>;
455 };
105 456
106 /* Colibri SSP */ 457 /* Colibri SSP */
107 ulpi_clk_py0 { 458 ulpi-clk-py0 {
108 nvidia,pins = "ulpi_clk_py0", 459 nvidia,pins = "ulpi_clk_py0",
109 "ulpi_dir_py1", 460 "ulpi_dir_py1",
110 "ulpi_nxt_py2", 461 "ulpi_nxt_py2",
@@ -113,16 +464,18 @@
113 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 464 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
114 nvidia,tristate = <TEGRA_PIN_DISABLE>; 465 nvidia,tristate = <TEGRA_PIN_DISABLE>;
115 }; 466 };
116 sdmmc3_dat6_pd3 { 467 /* Multiplexed SSPFRM, SSPTXD and therefore disabled */
468 sdmmc3-dat6-pd3 {
117 nvidia,pins = "sdmmc3_dat6_pd3", 469 nvidia,pins = "sdmmc3_dat6_pd3",
118 "sdmmc3_dat7_pd4"; 470 "sdmmc3_dat7_pd4";
119 nvidia,function = "spdif"; 471 nvidia,function = "spdif";
120 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 472 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
121 nvidia,tristate = <TEGRA_PIN_ENABLE>; 473 nvidia,tristate = <TEGRA_PIN_ENABLE>;
474 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
122 }; 475 };
123 476
124 /* Colibri UART_A */ 477 /* Colibri UART-A */
125 ulpi_data0 { 478 ulpi-data0 {
126 nvidia,pins = "ulpi_data0_po1", 479 nvidia,pins = "ulpi_data0_po1",
127 "ulpi_data1_po2", 480 "ulpi_data1_po2",
128 "ulpi_data2_po3", 481 "ulpi_data2_po3",
@@ -136,8 +489,8 @@
136 nvidia,tristate = <TEGRA_PIN_DISABLE>; 489 nvidia,tristate = <TEGRA_PIN_DISABLE>;
137 }; 490 };
138 491
139 /* Colibri UART_B */ 492 /* Colibri UART-B */
140 gmi_a16_pj7 { 493 gmi-a16-pj7 {
141 nvidia,pins = "gmi_a16_pj7", 494 nvidia,pins = "gmi_a16_pj7",
142 "gmi_a17_pb0", 495 "gmi_a17_pb0",
143 "gmi_a18_pb1", 496 "gmi_a18_pb1",
@@ -147,8 +500,8 @@
147 nvidia,tristate = <TEGRA_PIN_DISABLE>; 500 nvidia,tristate = <TEGRA_PIN_DISABLE>;
148 }; 501 };
149 502
150 /* Colibri UART_C */ 503 /* Colibri UART-C */
151 uart2_rxd { 504 uart2-rxd {
152 nvidia,pins = "uart2_rxd_pc3", 505 nvidia,pins = "uart2_rxd_pc3",
153 "uart2_txd_pc2"; 506 "uart2_txd_pc2";
154 nvidia,function = "uartb"; 507 nvidia,function = "uartb";
@@ -156,15 +509,53 @@
156 nvidia,tristate = <TEGRA_PIN_DISABLE>; 509 nvidia,tristate = <TEGRA_PIN_DISABLE>;
157 }; 510 };
158 511
159 /* eMMC */ 512 /* Colibri USBC_DET */
160 sdmmc4_clk_pcc4 { 513 spdif-out-pk5 {
514 nvidia,pins = "spdif_out_pk5";
515 nvidia,function = "rsvd2";
516 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
517 nvidia,tristate = <TEGRA_PIN_DISABLE>;
518 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
519 };
520
521 /* Colibri USBH_PEN */
522 spi2-cs1-n-pw2 {
523 nvidia,pins = "spi2_cs1_n_pw2";
524 nvidia,function = "spi2_alt";
525 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
526 nvidia,tristate = <TEGRA_PIN_DISABLE>;
527 };
528
529 /* Colibri USBH_OC */
530 spi2-cs2-n-pw3, {
531 nvidia,pins = "spi2_cs2_n_pw3";
532 nvidia,function = "spi2_alt";
533 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
534 nvidia,tristate = <TEGRA_PIN_DISABLE>;
535 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
536 };
537
538 /* Colibri VGA not supported and therefore disabled */
539 crt-hsync-pv6 {
540 nvidia,pins = "crt_hsync_pv6",
541 "crt_vsync_pv7";
542 nvidia,function = "rsvd2";
543 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
544 nvidia,tristate = <TEGRA_PIN_ENABLE>;
545 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
546 };
547
548 /* eMMC (On-module) */
549 sdmmc4-clk-pcc4 {
161 nvidia,pins = "sdmmc4_clk_pcc4", 550 nvidia,pins = "sdmmc4_clk_pcc4",
551 "sdmmc4_cmd_pt7",
162 "sdmmc4_rst_n_pcc3"; 552 "sdmmc4_rst_n_pcc3";
163 nvidia,function = "sdmmc4"; 553 nvidia,function = "sdmmc4";
164 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 554 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
165 nvidia,tristate = <TEGRA_PIN_DISABLE>; 555 nvidia,tristate = <TEGRA_PIN_DISABLE>;
556 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
166 }; 557 };
167 sdmmc4_dat0_paa0 { 558 sdmmc4-dat0-paa0 {
168 nvidia,pins = "sdmmc4_dat0_paa0", 559 nvidia,pins = "sdmmc4_dat0_paa0",
169 "sdmmc4_dat1_paa1", 560 "sdmmc4_dat1_paa1",
170 "sdmmc4_dat2_paa2", 561 "sdmmc4_dat2_paa2",
@@ -176,17 +567,111 @@
176 nvidia,function = "sdmmc4"; 567 nvidia,function = "sdmmc4";
177 nvidia,pull = <TEGRA_PIN_PULL_UP>; 568 nvidia,pull = <TEGRA_PIN_PULL_UP>;
178 nvidia,tristate = <TEGRA_PIN_DISABLE>; 569 nvidia,tristate = <TEGRA_PIN_DISABLE>;
570 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
571 };
572
573 /* LAN_EXT_WAKEUP#, LAN_PME (On-module) */
574 pex-l0-rst-n-pdd1 {
575 nvidia,pins = "pex_l0_rst_n_pdd1",
576 "pex_wake_n_pdd3";
577 nvidia,function = "rsvd3";
578 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
579 nvidia,tristate = <TEGRA_PIN_DISABLE>;
580 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
581 };
582 /* LAN_V_BUS, LAN_RESET# (On-module) */
583 pex-l0-clkreq-n-pdd2 {
584 nvidia,pins = "pex_l0_clkreq_n_pdd2",
585 "pex_l0_prsnt_n_pdd0";
586 nvidia,function = "rsvd3";
587 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
588 nvidia,tristate = <TEGRA_PIN_DISABLE>;
589 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
590 };
591
592 /* nBATT_FAULT(SENSE), nVDD_FAULT(SENSE) */
593 pex-l2-rst-n-pcc6 {
594 nvidia,pins = "pex_l2_rst_n_pcc6",
595 "pex_l2_prsnt_n_pdd7";
596 nvidia,function = "rsvd3";
597 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
598 nvidia,tristate = <TEGRA_PIN_DISABLE>;
599 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
600 };
601
602 /* Not connected and therefore disabled */
603 clk1-req-pee2 {
604 nvidia,pins = "clk1_req_pee2",
605 "pex_l1_prsnt_n_pdd4";
606 nvidia,function = "rsvd3";
607 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
608 nvidia,tristate = <TEGRA_PIN_ENABLE>;
609 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
610 };
611 clk2-req-pcc5 {
612 nvidia,pins = "clk2_req_pcc5",
613 "clk3_out_pee0",
614 "clk3_req_pee1",
615 "clk_32k_out_pa0",
616 "hdmi_cec_pee3",
617 "sys_clk_req_pz5";
618 nvidia,function = "rsvd2";
619 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
620 nvidia,tristate = <TEGRA_PIN_ENABLE>;
621 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
622 };
623 gmi-dqs-pi2 {
624 nvidia,pins = "gmi_dqs_pi2",
625 "kb_col2_pq2",
626 "kb_col3_pq3",
627 "kb_col4_pq4",
628 "kb_col5_pq5",
629 "kb_row4_pr4";
630 nvidia,function = "rsvd4";
631 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
632 nvidia,tristate = <TEGRA_PIN_ENABLE>;
633 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
634 };
635 kb-col0-pq0 {
636 nvidia,pins = "kb_col0_pq0",
637 "kb_col1_pq1",
638 "kb_col6_pq6",
639 "kb_col7_pq7",
640 "kb_row5_pr5",
641 "kb_row6_pr6",
642 "kb_row7_pr7",
643 "kb_row9_ps1";
644 nvidia,function = "kbc";
645 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
646 nvidia,tristate = <TEGRA_PIN_ENABLE>;
647 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
648 };
649 kb-row0-pr0 {
650 nvidia,pins = "kb_row0_pr0",
651 "kb_row1_pr1",
652 "kb_row2_pr2",
653 "kb_row3_pr3";
654 nvidia,function = "rsvd3";
655 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
656 nvidia,tristate = <TEGRA_PIN_ENABLE>;
657 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
658 };
659 lcd-pwr2-pc6 {
660 nvidia,pins = "lcd_pwr2_pc6";
661 nvidia,function = "hdcp";
662 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
663 nvidia,tristate = <TEGRA_PIN_ENABLE>;
664 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
179 }; 665 };
180 666
181 /* Power I2C (On-module) */ 667 /* Power I2C (On-module) */
182 pwr_i2c_scl_pz6 { 668 pwr-i2c-scl-pz6 {
183 nvidia,pins = "pwr_i2c_scl_pz6", 669 nvidia,pins = "pwr_i2c_scl_pz6",
184 "pwr_i2c_sda_pz7"; 670 "pwr_i2c_sda_pz7";
185 nvidia,function = "i2cpwr"; 671 nvidia,function = "i2cpwr";
186 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 672 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
187 nvidia,tristate = <TEGRA_PIN_DISABLE>; 673 nvidia,tristate = <TEGRA_PIN_DISABLE>;
188 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 674 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
189 nvidia,lock = <TEGRA_PIN_DISABLE>;
190 nvidia,open-drain = <TEGRA_PIN_ENABLE>; 675 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
191 }; 676 };
192 677
@@ -195,15 +680,15 @@
195 * temperature sensor therefore requires disabling for 680 * temperature sensor therefore requires disabling for
196 * now 681 * now
197 */ 682 */
198 lcd_dc1_pd2 { 683 lcd-dc1-pd2 {
199 nvidia,pins = "lcd_dc1_pd2"; 684 nvidia,pins = "lcd_dc1_pd2";
200 nvidia,function = "rsvd3"; 685 nvidia,function = "rsvd3";
201 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 686 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
202 nvidia,tristate = <TEGRA_PIN_DISABLE>; 687 nvidia,tristate = <TEGRA_PIN_ENABLE>;
203 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 688 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
204 }; 689 };
205 690
206 /* TOUCH_PEN_INT# */ 691 /* TOUCH_PEN_INT# (On-module) */
207 pv0 { 692 pv0 {
208 nvidia,pins = "pv0"; 693 nvidia,pins = "pv0";
209 nvidia,function = "rsvd1"; 694 nvidia,function = "rsvd1";
@@ -214,13 +699,21 @@
214 }; 699 };
215 }; 700 };
216 701
217 hdmiddc: i2c@7000c700 { 702 serial@70006040 {
703 compatible = "nvidia,tegra30-hsuart";
704 };
705
706 serial@70006300 {
707 compatible = "nvidia,tegra30-hsuart";
708 };
709
710 hdmi_ddc: i2c@7000c700 {
218 clock-frequency = <10000>; 711 clock-frequency = <10000>;
219 }; 712 };
220 713
221 /* 714 /*
222 * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and 715 * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
223 * touch screen controller 716 * touch screen controller (On-module)
224 */ 717 */
225 i2c@7000d000 { 718 i2c@7000d000 {
226 status = "okay"; 719 status = "okay";
@@ -230,12 +723,13 @@
230 sgtl5000: codec@a { 723 sgtl5000: codec@a {
231 compatible = "fsl,sgtl5000"; 724 compatible = "fsl,sgtl5000";
232 reg = <0x0a>; 725 reg = <0x0a>;
233 VDDA-supply = <&sys_3v3_reg>; 726 VDDA-supply = <&reg_module_3v3_audio>;
234 VDDIO-supply = <&sys_3v3_reg>; 727 VDDD-supply = <&reg_1v8_vio>;
728 VDDIO-supply = <&reg_module_3v3>;
235 clocks = <&tegra_car TEGRA30_CLK_EXTERN1>; 729 clocks = <&tegra_car TEGRA30_CLK_EXTERN1>;
236 }; 730 };
237 731
238 pmic: tps65911@2d { 732 pmic: pmic@2d {
239 compatible = "ti,tps65911"; 733 compatible = "ti,tps65911";
240 reg = <0x2d>; 734 reg = <0x2d>;
241 735
@@ -248,19 +742,18 @@
248 #gpio-cells = <2>; 742 #gpio-cells = <2>;
249 gpio-controller; 743 gpio-controller;
250 744
251 vcc1-supply = <&sys_3v3_reg>; 745 vcc1-supply = <&reg_module_3v3>;
252 vcc2-supply = <&sys_3v3_reg>; 746 vcc2-supply = <&reg_module_3v3>;
253 vcc3-supply = <&vio_reg>; 747 vcc3-supply = <&reg_1v8_vio>;
254 vcc4-supply = <&sys_3v3_reg>; 748 vcc4-supply = <&reg_module_3v3>;
255 vcc5-supply = <&sys_3v3_reg>; 749 vcc5-supply = <&reg_module_3v3>;
256 vcc6-supply = <&vio_reg>; 750 vcc6-supply = <&reg_1v8_vio>;
257 vcc7-supply = <&charge_pump_5v0_reg>; 751 vcc7-supply = <&reg_5v0_charge_pump>;
258 vccio-supply = <&sys_3v3_reg>; 752 vccio-supply = <&reg_module_3v3>;
259 753
260 regulators { 754 regulators {
261 /* SW1: +V1.35_VDDIO_DDR */
262 vdd1_reg: vdd1 { 755 vdd1_reg: vdd1 {
263 regulator-name = "vddio_ddr_1v35"; 756 regulator-name = "+V1.35_VDDIO_DDR";
264 regulator-min-microvolt = <1350000>; 757 regulator-min-microvolt = <1350000>;
265 regulator-max-microvolt = <1350000>; 758 regulator-max-microvolt = <1350000>;
266 regulator-always-on; 759 regulator-always-on;
@@ -268,17 +761,15 @@
268 761
269 /* SW2: unused */ 762 /* SW2: unused */
270 763
271 /* SW CTRL: +V1.0_VDD_CPU */
272 vddctrl_reg: vddctrl { 764 vddctrl_reg: vddctrl {
273 regulator-name = "vdd_cpu,vdd_sys"; 765 regulator-name = "+V1.0_VDD_CPU";
274 regulator-min-microvolt = <1150000>; 766 regulator-min-microvolt = <1150000>;
275 regulator-max-microvolt = <1150000>; 767 regulator-max-microvolt = <1150000>;
276 regulator-always-on; 768 regulator-always-on;
277 }; 769 };
278 770
279 /* SWIO: +V1.8 */ 771 reg_1v8_vio: vio {
280 vio_reg: vio { 772 regulator-name = "+V1.8";
281 regulator-name = "vdd_1v8_gen";
282 regulator-min-microvolt = <1800000>; 773 regulator-min-microvolt = <1800000>;
283 regulator-max-microvolt = <1800000>; 774 regulator-max-microvolt = <1800000>;
284 regulator-always-on; 775 regulator-always-on;
@@ -289,10 +780,10 @@
289 /* 780 /*
290 * EN_+V3.3 switching via FET: 781 * EN_+V3.3 switching via FET:
291 * +V3.3_AUDIO_AVDD_S, +V3.3 and +V1.8_VDD_LAN 782 * +V3.3_AUDIO_AVDD_S, +V3.3 and +V1.8_VDD_LAN
292 * see also 3v3 fixed supply 783 * see also +V3.3 fixed supply
293 */ 784 */
294 ldo2_reg: ldo2 { 785 ldo2_reg: ldo2 {
295 regulator-name = "en_3v3"; 786 regulator-name = "EN_+V3.3";
296 regulator-min-microvolt = <3300000>; 787 regulator-min-microvolt = <3300000>;
297 regulator-max-microvolt = <3300000>; 788 regulator-max-microvolt = <3300000>;
298 regulator-always-on; 789 regulator-always-on;
@@ -300,9 +791,8 @@
300 791
301 /* LDO3: unused */ 792 /* LDO3: unused */
302 793
303 /* +V1.2_VDD_RTC */
304 ldo4_reg: ldo4 { 794 ldo4_reg: ldo4 {
305 regulator-name = "vdd_rtc"; 795 regulator-name = "+V1.2_VDD_RTC";
306 regulator-min-microvolt = <1200000>; 796 regulator-min-microvolt = <1200000>;
307 regulator-max-microvolt = <1200000>; 797 regulator-max-microvolt = <1200000>;
308 regulator-always-on; 798 regulator-always-on;
@@ -310,10 +800,10 @@
310 800
311 /* 801 /*
312 * +V2.8_AVDD_VDAC: 802 * +V2.8_AVDD_VDAC:
313 * only required for analog RGB 803 * only required for (unsupported) analog RGB
314 */ 804 */
315 ldo5_reg: ldo5 { 805 ldo5_reg: ldo5 {
316 regulator-name = "avdd_vdac"; 806 regulator-name = "+V2.8_AVDD_VDAC";
317 regulator-min-microvolt = <2800000>; 807 regulator-min-microvolt = <2800000>;
318 regulator-max-microvolt = <2800000>; 808 regulator-max-microvolt = <2800000>;
319 regulator-always-on; 809 regulator-always-on;
@@ -325,22 +815,20 @@
325 * granularity 815 * granularity
326 */ 816 */
327 ldo6_reg: ldo6 { 817 ldo6_reg: ldo6 {
328 regulator-name = "avdd_plle"; 818 regulator-name = "+V1.05_AVDD_PLLE";
329 regulator-min-microvolt = <1100000>; 819 regulator-min-microvolt = <1100000>;
330 regulator-max-microvolt = <1100000>; 820 regulator-max-microvolt = <1100000>;
331 }; 821 };
332 822
333 /* +V1.2_AVDD_PLL */
334 ldo7_reg: ldo7 { 823 ldo7_reg: ldo7 {
335 regulator-name = "avdd_pll"; 824 regulator-name = "+V1.2_AVDD_PLL";
336 regulator-min-microvolt = <1200000>; 825 regulator-min-microvolt = <1200000>;
337 regulator-max-microvolt = <1200000>; 826 regulator-max-microvolt = <1200000>;
338 regulator-always-on; 827 regulator-always-on;
339 }; 828 };
340 829
341 /* +V1.0_VDD_DDR_HS */
342 ldo8_reg: ldo8 { 830 ldo8_reg: ldo8 {
343 regulator-name = "vdd_ddr_hs"; 831 regulator-name = "+V1.0_VDD_DDR_HS";
344 regulator-min-microvolt = <1000000>; 832 regulator-min-microvolt = <1000000>;
345 regulator-max-microvolt = <1000000>; 833 regulator-max-microvolt = <1000000>;
346 regulator-always-on; 834 regulator-always-on;
@@ -349,11 +837,10 @@
349 }; 837 };
350 838
351 /* STMPE811 touch screen controller */ 839 /* STMPE811 touch screen controller */
352 stmpe811@41 { 840 touchscreen@41 {
353 compatible = "st,stmpe811"; 841 compatible = "st,stmpe811";
354 reg = <0x41>; 842 reg = <0x41>;
355 interrupts = <TEGRA_GPIO(V, 0) IRQ_TYPE_LEVEL_LOW>; 843 irq-gpio = <&gpio TEGRA_GPIO(V, 0) IRQ_TYPE_LEVEL_LOW>;
356 interrupt-parent = <&gpio>;
357 interrupt-controller; 844 interrupt-controller;
358 id = <0>; 845 id = <0>;
359 blocks = <0x5>; 846 blocks = <0x5>;
@@ -387,7 +874,7 @@
387 874
388 /* 875 /*
389 * LM95245 temperature sensor 876 * LM95245 temperature sensor
390 * Note: OVERT_N directly connected to PMIC PWRDN 877 * Note: OVERT1# directly connected to TPS65911 PMIC PWRDN
391 */ 878 */
392 temp-sensor@4c { 879 temp-sensor@4c {
393 compatible = "national,lm95245"; 880 compatible = "national,lm95245";
@@ -395,7 +882,7 @@
395 }; 882 };
396 883
397 /* SW: +V1.2_VDD_CORE */ 884 /* SW: +V1.2_VDD_CORE */
398 tps62362@60 { 885 regulator@60 {
399 compatible = "ti,tps62362"; 886 compatible = "ti,tps62362";
400 reg = <0x60>; 887 reg = <0x60>;
401 888
@@ -419,6 +906,18 @@
419 nvidia,core-pwr-off-time = <0>; 906 nvidia,core-pwr-off-time = <0>;
420 nvidia,core-power-req-active-high; 907 nvidia,core-power-req-active-high;
421 nvidia,sys-clock-req-active-high; 908 nvidia,sys-clock-req-active-high;
909
910 /* Set DEV_OFF bit in DCDC control register of TPS65911 PMIC */
911 i2c-thermtrip {
912 nvidia,i2c-controller-id = <4>;
913 nvidia,bus-addr = <0x2d>;
914 nvidia,reg-addr = <0x3f>;
915 nvidia,reg-data = <0x1>;
916 };
917 };
918
919 hda@70030000 {
920 status = "okay";
422 }; 921 };
423 922
424 ahub@70080000 { 923 ahub@70080000 {
@@ -432,75 +931,85 @@
432 status = "okay"; 931 status = "okay";
433 bus-width = <8>; 932 bus-width = <8>;
434 non-removable; 933 non-removable;
934 vmmc-supply = <&reg_module_3v3>; /* VCC */
935 vqmmc-supply = <&reg_1v8_vio>; /* VCCQ */
936 mmc-ddr-1_8v;
435 }; 937 };
436 938
437 /* EHCI instance 1: USB2_DP/N -> AX88772B */ 939 /* EHCI instance 1: USB2_DP/N -> AX88772B (On-module) */
438 usb@7d004000 { 940 usb@7d004000 {
439 status = "okay"; 941 status = "okay";
942 #address-cells = <1>;
943 #size-cells = <0>;
944
945 asix@1 {
946 reg = <1>;
947 local-mac-address = [00 00 00 00 00 00];
948 };
440 }; 949 };
441 950
442 usb-phy@7d004000 { 951 usb-phy@7d004000 {
443 status = "okay"; 952 status = "okay";
444 nvidia,is-wired = <1>; 953 vbus-supply = <&reg_lan_v_bus>;
445 }; 954 };
446 955
447 clocks { 956 clk32k_in: xtal1 {
448 compatible = "simple-bus"; 957 compatible = "fixed-clock";
449 #address-cells = <1>; 958 #clock-cells = <0>;
450 #size-cells = <0>; 959 clock-frequency = <32768>;
960 };
451 961
452 clk32k_in: clk@0 { 962 reg_1v8_avdd_hdmi_pll: regulator-1v8-avdd-hdmi-pll {
453 compatible = "fixed-clock"; 963 compatible = "regulator-fixed";
454 reg = <0>; 964 regulator-name = "+V1.8_AVDD_HDMI_PLL";
455 #clock-cells = <0>; 965 regulator-min-microvolt = <1800000>;
456 clock-frequency = <32768>; 966 regulator-max-microvolt = <1800000>;
457 }; 967 enable-active-high;
968 gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
969 vin-supply = <&reg_1v8_vio>;
458 }; 970 };
459 971
460 regulators { 972 reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi {
461 compatible = "simple-bus"; 973 compatible = "regulator-fixed";
462 #address-cells = <1>; 974 regulator-name = "+V3.3_AVDD_HDMI";
463 #size-cells = <0>; 975 regulator-min-microvolt = <3300000>;
976 regulator-max-microvolt = <3300000>;
977 enable-active-high;
978 gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
979 vin-supply = <&reg_module_3v3>;
980 };
464 981
465 avdd_hdmi_pll_1v8_reg: regulator@100 { 982 reg_5v0_charge_pump: regulator-5v0-charge-pump {
466 compatible = "regulator-fixed"; 983 compatible = "regulator-fixed";
467 reg = <100>; 984 regulator-name = "+V5.0";
468 regulator-name = "+V1.8_AVDD_HDMI_PLL"; 985 regulator-min-microvolt = <5000000>;
469 regulator-min-microvolt = <1800000>; 986 regulator-max-microvolt = <5000000>;
470 regulator-max-microvolt = <1800000>; 987 regulator-always-on;
471 enable-active-high; 988 };
472 gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
473 vin-supply = <&vio_reg>;
474 };
475 989
476 sys_3v3_reg: regulator@101 { 990 reg_lan_v_bus: regulator-lan-v-bus {
477 compatible = "regulator-fixed"; 991 compatible = "regulator-fixed";
478 reg = <101>; 992 regulator-name = "LAN_V_BUS";
479 regulator-name = "3v3"; 993 regulator-min-microvolt = <5000000>;
480 regulator-min-microvolt = <3300000>; 994 regulator-max-microvolt = <5000000>;
481 regulator-max-microvolt = <3300000>; 995 enable-active-high;
482 regulator-always-on; 996 gpio = <&gpio TEGRA_GPIO(DD, 2) GPIO_ACTIVE_HIGH>;
483 }; 997 };
484 998
485 avdd_hdmi_3v3_reg: regulator@102 { 999 reg_module_3v3: regulator-module-3v3 {
486 compatible = "regulator-fixed"; 1000 compatible = "regulator-fixed";
487 reg = <102>; 1001 regulator-name = "+V3.3";
488 regulator-name = "+V3.3_AVDD_HDMI"; 1002 regulator-min-microvolt = <3300000>;
489 regulator-min-microvolt = <3300000>; 1003 regulator-max-microvolt = <3300000>;
490 regulator-max-microvolt = <3300000>; 1004 regulator-always-on;
491 enable-active-high; 1005 };
492 gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
493 vin-supply = <&sys_3v3_reg>;
494 };
495 1006
496 charge_pump_5v0_reg: regulator@103 { 1007 reg_module_3v3_audio: regulator-module-3v3-audio {
497 compatible = "regulator-fixed"; 1008 compatible = "regulator-fixed";
498 reg = <103>; 1009 regulator-name = "+V3.3_AUDIO_AVDD_S";
499 regulator-name = "5v0"; 1010 regulator-min-microvolt = <3300000>;
500 regulator-min-microvolt = <5000000>; 1011 regulator-max-microvolt = <3300000>;
501 regulator-max-microvolt = <5000000>; 1012 regulator-always-on;
502 regulator-always-on;
503 };
504 }; 1013 };
505 1014
506 sound { 1015 sound {
@@ -519,3 +1028,12 @@
519 clock-names = "pll_a", "pll_a_out0", "mclk"; 1028 clock-names = "pll_a", "pll_a_out0", "mclk";
520 }; 1029 };
521}; 1030};
1031
1032&gpio {
1033 lan-reset-n {
1034 gpio-hog;
1035 gpios = <TEGRA_GPIO(DD, 0) GPIO_ACTIVE_HIGH>;
1036 output-high;
1037 line-name = "LAN_RESET#";
1038 };
1039};
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index a6781f653310..d2b553f76719 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -896,7 +896,7 @@
896 nvidia,elastic-limit = <16>; 896 nvidia,elastic-limit = <16>;
897 nvidia,term-range-adj = <6>; 897 nvidia,term-range-adj = <6>;
898 nvidia,xcvr-setup = <51>; 898 nvidia,xcvr-setup = <51>;
899 nvidia.xcvr-setup-use-fuses; 899 nvidia,xcvr-setup-use-fuses;
900 nvidia,xcvr-lsfslew = <1>; 900 nvidia,xcvr-lsfslew = <1>;
901 nvidia,xcvr-lsrslew = <1>; 901 nvidia,xcvr-lsrslew = <1>;
902 nvidia,xcvr-hsslew = <32>; 902 nvidia,xcvr-hsslew = <32>;
@@ -933,7 +933,7 @@
933 nvidia,elastic-limit = <16>; 933 nvidia,elastic-limit = <16>;
934 nvidia,term-range-adj = <6>; 934 nvidia,term-range-adj = <6>;
935 nvidia,xcvr-setup = <51>; 935 nvidia,xcvr-setup = <51>;
936 nvidia.xcvr-setup-use-fuses; 936 nvidia,xcvr-setup-use-fuses;
937 nvidia,xcvr-lsfslew = <2>; 937 nvidia,xcvr-lsfslew = <2>;
938 nvidia,xcvr-lsrslew = <2>; 938 nvidia,xcvr-lsrslew = <2>;
939 nvidia,xcvr-hsslew = <32>; 939 nvidia,xcvr-hsslew = <32>;
@@ -969,7 +969,7 @@
969 nvidia,elastic-limit = <16>; 969 nvidia,elastic-limit = <16>;
970 nvidia,term-range-adj = <6>; 970 nvidia,term-range-adj = <6>;
971 nvidia,xcvr-setup = <51>; 971 nvidia,xcvr-setup = <51>;
972 nvidia.xcvr-setup-use-fuses; 972 nvidia,xcvr-setup-use-fuses;
973 nvidia,xcvr-lsfslew = <2>; 973 nvidia,xcvr-lsfslew = <2>;
974 nvidia,xcvr-lsrslew = <2>; 974 nvidia,xcvr-lsrslew = <2>;
975 nvidia,xcvr-hsslew = <32>; 975 nvidia,xcvr-hsslew = <32>;
@@ -1013,5 +1013,9 @@
1013 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1013 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1014 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1014 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1015 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 1015 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
1016 interrupt-affinity = <&{/cpus/cpu@0}>,
1017 <&{/cpus/cpu@1}>,
1018 <&{/cpus/cpu@2}>,
1019 <&{/cpus/cpu@3}>;
1016 }; 1020 };
1017}; 1021};
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-22 08:10:28 -0400