From 564706f65cda3de52b09e51feb423a43940fe661 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Fri, 31 Aug 2018 14:42:33 +0200 Subject: ARM: dts: tegra30: fix xcvr-setup-use-fuses There was a dot instead of a comma. Fix this. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index a6781f653310..5a04ddefb71f 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -896,7 +896,7 @@ nvidia,elastic-limit = <16>; nvidia,term-range-adj = <6>; nvidia,xcvr-setup = <51>; - nvidia.xcvr-setup-use-fuses; + nvidia,xcvr-setup-use-fuses; nvidia,xcvr-lsfslew = <1>; nvidia,xcvr-lsrslew = <1>; nvidia,xcvr-hsslew = <32>; @@ -933,7 +933,7 @@ nvidia,elastic-limit = <16>; nvidia,term-range-adj = <6>; nvidia,xcvr-setup = <51>; - nvidia.xcvr-setup-use-fuses; + nvidia,xcvr-setup-use-fuses; nvidia,xcvr-lsfslew = <2>; nvidia,xcvr-lsrslew = <2>; nvidia,xcvr-hsslew = <32>; @@ -969,7 +969,7 @@ nvidia,elastic-limit = <16>; nvidia,term-range-adj = <6>; nvidia,xcvr-setup = <51>; - nvidia.xcvr-setup-use-fuses; + nvidia,xcvr-setup-use-fuses; nvidia,xcvr-lsfslew = <2>; nvidia,xcvr-lsrslew = <2>; nvidia,xcvr-hsslew = <32>; -- cgit v1.2.2 From 8188391c127ea34d66f37eda6755d0acb51dc600 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Thu, 16 Aug 2018 10:06:03 +0200 Subject: ARM: dts: tegra20: restore address order Commit 6c468f109884 ("ARM: dts: tegra: add Tegra20 NAND flash controller node") introduced the nand-controller node. However, it got added at the wrong spot not honoring the address order. Fix this. Signed-off-by: Marcel Ziswiler Reviewed-by: Stefan Agner Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20.dtsi | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 15b73bd377f0..80854f7de765 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -419,19 +419,6 @@ status = "disabled"; }; - gmi@70009000 { - compatible = "nvidia,tegra20-gmi"; - reg = <0x70009000 0x1000>; - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0xd0000000 0xfffffff>; - clocks = <&tegra_car TEGRA20_CLK_NOR>; - clock-names = "gmi"; - resets = <&tegra_car 42>; - reset-names = "gmi"; - status = "disabled"; - }; - nand-controller@70008000 { compatible = "nvidia,tegra20-nand"; reg = <0x70008000 0x100>; @@ -447,6 +434,19 @@ status = "disabled"; }; + gmi@70009000 { + compatible = "nvidia,tegra20-gmi"; + reg = <0x70009000 0x1000>; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0xd0000000 0xfffffff>; + clocks = <&tegra_car TEGRA20_CLK_NOR>; + clock-names = "gmi"; + resets = <&tegra_car 42>; + reset-names = "gmi"; + status = "disabled"; + }; + pwm: pwm@7000a000 { compatible = "nvidia,tegra20-pwm"; reg = <0x7000a000 0x100>; -- cgit v1.2.2 From 2db12b16e58a562fdf161b226739d30ea06bcd37 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Thu, 16 Aug 2018 10:06:04 +0200 Subject: ARM: dts: tegra20/tegra30: add pmu interrupt-affinity This is similar to tegra124 and avoids the following being reported upon boot: hw perfevents: no interrupt-affinity property for /pmu, guessing. Signed-off-by: Marcel Ziswiler Reviewed-by: Stefan Agner Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20.dtsi | 2 ++ arch/arm/boot/dts/tegra30.dtsi | 4 ++++ 2 files changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 80854f7de765..20869757d32f 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -865,5 +865,7 @@ compatible = "arm,cortex-a9-pmu"; interrupts = , ; + interrupt-affinity = <&{/cpus/cpu@0}>, + <&{/cpus/cpu@1}>; }; }; diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index 5a04ddefb71f..d2b553f76719 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -1013,5 +1013,9 @@ , , ; + interrupt-affinity = <&{/cpus/cpu@0}>, + <&{/cpus/cpu@1}>, + <&{/cpus/cpu@2}>, + <&{/cpus/cpu@3}>; }; }; -- cgit v1.2.2 From 1c997fe4becdc6fcbc06e23982ceb65621e6572a Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Fri, 31 Aug 2018 18:37:43 +0200 Subject: ARM: tegra: apalis_t30: fix mmc1 cmd pull-up Fix MMC1 cmd pin pull-up causing issues on carrier boards without external pull-up. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-apalis.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi index 2f807d40c1b7..e749e047db7a 100644 --- a/arch/arm/boot/dts/tegra30-apalis.dtsi +++ b/arch/arm/boot/dts/tegra30-apalis.dtsi @@ -171,14 +171,14 @@ /* Apalis MMC1 */ sdmmc3_clk_pa6 { - nvidia,pins = "sdmmc3_clk_pa6", - "sdmmc3_cmd_pa7"; + nvidia,pins = "sdmmc3_clk_pa6"; nvidia,function = "sdmmc3"; nvidia,pull = ; nvidia,tristate = ; }; sdmmc3_dat0_pb7 { - nvidia,pins = "sdmmc3_dat0_pb7", + nvidia,pins = "sdmmc3_cmd_pa7", + "sdmmc3_dat0_pb7", "sdmmc3_dat1_pb6", "sdmmc3_dat2_pb5", "sdmmc3_dat3_pb4", -- cgit v1.2.2 From 055c0107afed975b27d838bbc99ddf2066e868db Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Fri, 31 Aug 2018 18:37:44 +0200 Subject: ARM: tegra: apalis_t30: pull-up sd card detect pins In order to avoid any floating SD card detect pins as may e.g. happen on Ixora V1.1A pull them all up. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-apalis.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi index e749e047db7a..69bb11c31d77 100644 --- a/arch/arm/boot/dts/tegra30-apalis.dtsi +++ b/arch/arm/boot/dts/tegra30-apalis.dtsi @@ -194,7 +194,7 @@ pv3 { nvidia,pins = "pv3"; nvidia,function = "rsvd2"; - nvidia,pull = ; + nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; @@ -260,7 +260,7 @@ clk2_req_pcc5 { nvidia,pins = "clk2_req_pcc5"; nvidia,function = "rsvd2"; - nvidia,pull = ; + nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; -- cgit v1.2.2 From 2c87441c41641036a93511fbe92522ad772e9680 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Fri, 31 Aug 2018 18:37:45 +0200 Subject: ARM: tegra: apalis_t30: add local-mac-address property Add empty local-mac-address property to be filled in by boot loader (e.g. U-Boot). Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-apalis.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi index 69bb11c31d77..f13df31b5e25 100644 --- a/arch/arm/boot/dts/tegra30-apalis.dtsi +++ b/arch/arm/boot/dts/tegra30-apalis.dtsi @@ -34,6 +34,10 @@ pci@3,0 { nvidia,num-lanes = <1>; + pcie@0 { + reg = <0 0 0 0 0>; + local-mac-address = [00 00 00 00 00 00]; + }; }; }; -- cgit v1.2.2 From 4f6b07a2787b97380dc278ce28bd4438817f7525 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Fri, 31 Aug 2018 18:37:46 +0200 Subject: ARM: tegra: apalis_t30: reorder pcie properties Reorder PCIe properties. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-apalis.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi index f13df31b5e25..fc279a073ac5 100644 --- a/arch/arm/boot/dts/tegra30-apalis.dtsi +++ b/arch/arm/boot/dts/tegra30-apalis.dtsi @@ -16,13 +16,13 @@ pcie@3000 { avdd-pexa-supply = <&vdd2_reg>; - vdd-pexa-supply = <&vdd2_reg>; avdd-pexb-supply = <&vdd2_reg>; - vdd-pexb-supply = <&vdd2_reg>; avdd-pex-pll-supply = <&vdd2_reg>; avdd-plle-supply = <&ldo6_reg>; - vddio-pex-ctl-supply = <&sys_3v3_reg>; hvdd-pex-supply = <&sys_3v3_reg>; + vddio-pex-ctl-supply = <&sys_3v3_reg>; + vdd-pexa-supply = <&vdd2_reg>; + vdd-pexb-supply = <&vdd2_reg>; pci@1,0 { nvidia,num-lanes = <4>; -- cgit v1.2.2 From 7890d7856a989a7f2a4c46ec84c4ecda6a760c11 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Fri, 31 Aug 2018 18:37:47 +0200 Subject: ARM: tegra: apalis_t30: annotate/clean-up pcie controller/port nodes Annotate PCIe port nodes and clean-up PCIe controller/port status' with respect to carrier board vs. module level device trees. As port 3 connects to the on-module Gigabit Ethernet MACPHY it is always enabled together with the PCIe controller itself. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-apalis-eval.dts | 6 ------ arch/arm/boot/dts/tegra30-apalis.dtsi | 5 +++++ 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/tegra30-apalis-eval.dts b/arch/arm/boot/dts/tegra30-apalis-eval.dts index 0dc85a20bd45..e3c70e7d8d37 100644 --- a/arch/arm/boot/dts/tegra30-apalis-eval.dts +++ b/arch/arm/boot/dts/tegra30-apalis-eval.dts @@ -23,8 +23,6 @@ }; pcie@3000 { - status = "okay"; - pci@1,0 { status = "okay"; }; @@ -32,10 +30,6 @@ pci@2,0 { status = "okay"; }; - - pci@3,0 { - status = "okay"; - }; }; host1x@50000000 { diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi index fc279a073ac5..c810c044025a 100644 --- a/arch/arm/boot/dts/tegra30-apalis.dtsi +++ b/arch/arm/boot/dts/tegra30-apalis.dtsi @@ -15,6 +15,7 @@ }; pcie@3000 { + status = "okay"; avdd-pexa-supply = <&vdd2_reg>; avdd-pexb-supply = <&vdd2_reg>; avdd-pex-pll-supply = <&vdd2_reg>; @@ -24,15 +25,19 @@ vdd-pexa-supply = <&vdd2_reg>; vdd-pexb-supply = <&vdd2_reg>; + /* Apalis type specific */ pci@1,0 { nvidia,num-lanes = <4>; }; + /* Apalis PCIe */ pci@2,0 { nvidia,num-lanes = <1>; }; + /* I210/I211 Gigabit Ethernet Controller (on-module) */ pci@3,0 { + status = "okay"; nvidia,num-lanes = <1>; pcie@0 { reg = <0 0 0 0 0>; -- cgit v1.2.2 From a772d28d908995a686c4da7a2578c5b359b49000 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Fri, 31 Aug 2018 18:37:48 +0200 Subject: ARM: tegra: apalis_t30: reorder host1x/hdmi properties Reorder Host1x/HDMI properties. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-apalis.dtsi | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi index c810c044025a..648db524abae 100644 --- a/arch/arm/boot/dts/tegra30-apalis.dtsi +++ b/arch/arm/boot/dts/tegra30-apalis.dtsi @@ -48,12 +48,11 @@ host1x@50000000 { hdmi@54280000 { - vdd-supply = <&avdd_hdmi_3v3_reg>; - pll-supply = <&avdd_hdmi_pll_1v8_reg>; - + nvidia,ddc-i2c-bus = <&hdmiddc>; nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; - nvidia,ddc-i2c-bus = <&hdmiddc>; + pll-supply = <&avdd_hdmi_pll_1v8_reg>; + vdd-supply = <&avdd_hdmi_3v3_reg>; }; }; -- cgit v1.2.2 From f98439c3bba5083c3376eb88c80a54dce4837f30 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Fri, 31 Aug 2018 18:37:49 +0200 Subject: ARM: tegra: apalis_t30: regulator clean-up Just cosmetic regulator clean-up. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-apalis-eval.dts | 62 ++++++------- arch/arm/boot/dts/tegra30-apalis.dtsi | 140 +++++++++++++----------------- 2 files changed, 88 insertions(+), 114 deletions(-) diff --git a/arch/arm/boot/dts/tegra30-apalis-eval.dts b/arch/arm/boot/dts/tegra30-apalis-eval.dts index e3c70e7d8d37..07da481bc441 100644 --- a/arch/arm/boot/dts/tegra30-apalis-eval.dts +++ b/arch/arm/boot/dts/tegra30-apalis-eval.dts @@ -153,7 +153,7 @@ usb-phy@7d000000 { status = "okay"; dr_mode = "otg"; - vbus-supply = <&usbo1_vbus_reg>; + vbus-supply = <®_usbo1_vbus>; }; /* EHCI instance 1: USB2_DP/N -> USBH2_DP/N */ @@ -163,7 +163,7 @@ usb-phy@7d004000 { status = "okay"; - vbus-supply = <&usbh_vbus_reg>; + vbus-supply = <®_usbh_vbus>; }; /* EHCI instance 2: USB3_DP/N -> USBH3_DP/N */ @@ -173,7 +173,7 @@ usb-phy@7d008000 { status = "okay"; - vbus-supply = <&usbh_vbus_reg>; + vbus-supply = <®_usbh_vbus>; }; backlight: backlight { @@ -231,38 +231,32 @@ }; }; - regulators { - sys_5v0_reg: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; + reg_5v0: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "5V_SW"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; - /* USBO1_EN */ - usbo1_vbus_reg: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "usbo1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(T, 5) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&sys_5v0_reg>; - }; + /* USBO1_EN */ + reg_usbo1_vbus: regulator-usbo1-vbus { + compatible = "regulator-fixed"; + regulator-name = "VCC_USBO1"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(T, 5) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_5v0>; + }; - /* USBH_EN */ - usbh_vbus_reg: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "usbh_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&sys_5v0_reg>; - }; + /* USBH_EN */ + reg_usbh_vbus: regulator-usbh-vbus { + compatible = "regulator-fixed"; + regulator-name = "VCC_USBH(2A|2C|2D|3|4)"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_5v0>; }; }; diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi index 648db524abae..214a23722ab4 100644 --- a/arch/arm/boot/dts/tegra30-apalis.dtsi +++ b/arch/arm/boot/dts/tegra30-apalis.dtsi @@ -20,8 +20,8 @@ avdd-pexb-supply = <&vdd2_reg>; avdd-pex-pll-supply = <&vdd2_reg>; avdd-plle-supply = <&ldo6_reg>; - hvdd-pex-supply = <&sys_3v3_reg>; - vddio-pex-ctl-supply = <&sys_3v3_reg>; + hvdd-pex-supply = <®_module_3v3>; + vddio-pex-ctl-supply = <®_module_3v3>; vdd-pexa-supply = <&vdd2_reg>; vdd-pexb-supply = <&vdd2_reg>; @@ -51,8 +51,8 @@ nvidia,ddc-i2c-bus = <&hdmiddc>; nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; - pll-supply = <&avdd_hdmi_pll_1v8_reg>; - vdd-supply = <&avdd_hdmi_3v3_reg>; + pll-supply = <®_1v8_avdd_hdmi_pll>; + vdd-supply = <®_3v3_avdd_hdmi>; }; }; @@ -465,8 +465,8 @@ sgtl5000: codec@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; - VDDA-supply = <&sys_3v3_reg>; - VDDIO-supply = <&sys_3v3_reg>; + VDDA-supply = <®_module_3v3>; + VDDIO-supply = <®_module_3v3>; clocks = <&tegra_car TEGRA30_CLK_EXTERN1>; }; @@ -483,43 +483,38 @@ #gpio-cells = <2>; gpio-controller; - vcc1-supply = <&sys_3v3_reg>; - vcc2-supply = <&sys_3v3_reg>; - vcc3-supply = <&vio_reg>; - vcc4-supply = <&sys_3v3_reg>; - vcc5-supply = <&sys_3v3_reg>; - vcc6-supply = <&vio_reg>; - vcc7-supply = <&charge_pump_5v0_reg>; - vccio-supply = <&sys_3v3_reg>; + vcc1-supply = <®_module_3v3>; + vcc2-supply = <®_module_3v3>; + vcc3-supply = <®_1v8_vio>; + vcc4-supply = <®_module_3v3>; + vcc5-supply = <®_module_3v3>; + vcc6-supply = <®_1v8_vio>; + vcc7-supply = <®_5v0_charge_pump>; + vccio-supply = <®_module_3v3>; regulators { - /* SW1: +V1.35_VDDIO_DDR */ vdd1_reg: vdd1 { - regulator-name = "vddio_ddr_1v35"; + regulator-name = "+V1.35_VDDIO_DDR"; regulator-min-microvolt = <1350000>; regulator-max-microvolt = <1350000>; regulator-always-on; }; - /* SW2: +V1.05 */ vdd2_reg: vdd2 { - regulator-name = - "vdd_pexa,vdd_pexb,vdd_sata"; + regulator-name = "+V1.05"; regulator-min-microvolt = <1050000>; regulator-max-microvolt = <1050000>; }; - /* SW CTRL: +V1.0_VDD_CPU */ vddctrl_reg: vddctrl { - regulator-name = "vdd_cpu,vdd_sys"; + regulator-name = "+V1.0_VDD_CPU"; regulator-min-microvolt = <1150000>; regulator-max-microvolt = <1150000>; regulator-always-on; }; - /* SWIO: +V1.8 */ - vio_reg: vio { - regulator-name = "vdd_1v8_gen"; + reg_1v8_vio: vio { + regulator-name = "+V1.8"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; @@ -529,27 +524,24 @@ /* * EN_+V3.3 switching via FET: - * +V3.3_AUDIO_AVDD_S, +V3.3 and +V1.8_VDD_LAN - * see also v3_3 fixed supply + * +V3.3_AUDIO_AVDD_S, +V3.3 + * see also +V3.3 fixed supply */ ldo2_reg: ldo2 { - regulator-name = "en_3v3"; + regulator-name = "EN_+V3.3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; - /* +V1.2_CSI */ ldo3_reg: ldo3 { - regulator-name = - "avdd_dsi_csi,pwrdet_mipi"; + regulator-name = "+V1.2_CSI"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; }; - /* +V1.2_VDD_RTC */ ldo4_reg: ldo4 { - regulator-name = "vdd_rtc"; + regulator-name = "+V1.2_VDD_RTC"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; regulator-always-on; @@ -557,10 +549,10 @@ /* * +V2.8_AVDD_VDAC: - * only required for analog RGB + * only required for (unsupported) analog RGB */ ldo5_reg: ldo5 { - regulator-name = "avdd_vdac"; + regulator-name = "+V2.8_AVDD_VDAC"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; regulator-always-on; @@ -572,22 +564,20 @@ * granularity */ ldo6_reg: ldo6 { - regulator-name = "avdd_plle"; + regulator-name = "+V1.05_AVDD_PLLE"; regulator-min-microvolt = <1100000>; regulator-max-microvolt = <1100000>; }; - /* +V1.2_AVDD_PLL */ ldo7_reg: ldo7 { - regulator-name = "avdd_pll"; + regulator-name = "+V1.2_AVDD_PLL"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; regulator-always-on; }; - /* +V1.0_VDD_DDR_HS */ ldo8_reg: ldo8 { - regulator-name = "vdd_ddr_hs"; + regulator-name = "+V1.0_VDD_DDR_HS"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; regulator-always-on; @@ -732,50 +722,40 @@ }; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - avdd_hdmi_pll_1v8_reg: regulator@100 { - compatible = "regulator-fixed"; - reg = <100>; - regulator-name = "+V1.8_AVDD_HDMI_PLL"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - enable-active-high; - gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; - vin-supply = <&vio_reg>; - }; + reg_1v8_avdd_hdmi_pll: regulator-1v8-avdd-hdmi-pll { + compatible = "regulator-fixed"; + regulator-name = "+V1.8_AVDD_HDMI_PLL"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + enable-active-high; + gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; + vin-supply = <®_1v8_vio>; + }; - sys_3v3_reg: regulator@101 { - compatible = "regulator-fixed"; - reg = <101>; - regulator-name = "3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; + reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi { + compatible = "regulator-fixed"; + regulator-name = "+V3.3_AVDD_HDMI"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; + vin-supply = <®_module_3v3>; + }; - avdd_hdmi_3v3_reg: regulator@102 { - compatible = "regulator-fixed"; - reg = <102>; - regulator-name = "+V3.3_AVDD_HDMI"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; - vin-supply = <&sys_3v3_reg>; - }; + reg_5v0_charge_pump: regulator-5v0-charge-pump { + compatible = "regulator-fixed"; + regulator-name = "+V5.0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; - charge_pump_5v0_reg: regulator@103 { - compatible = "regulator-fixed"; - reg = <103>; - regulator-name = "5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; + reg_module_3v3: regulator-module-3v3 { + compatible = "regulator-fixed"; + regulator-name = "+V3.3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; }; sound { -- cgit v1.2.2 From 32980cbccf161b06137b6b0a1235b4b4082fc1bf Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Fri, 31 Aug 2018 18:37:50 +0200 Subject: ARM: tegra: apalis_t30: add missing regulators Add missing regulators: - reg_module_3v3_audio being VDDA supply of SGTL5000 - VDDD supply of SGTL5000 actually being reg_1v8_vio - carrier board HDMI supply being reg_5v0 - carrier board reg_3v3 actually being backlight and panel power supply Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-apalis-eval.dts | 10 ++++++++++ arch/arm/boot/dts/tegra30-apalis.dtsi | 11 ++++++++++- 2 files changed, 20 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra30-apalis-eval.dts b/arch/arm/boot/dts/tegra30-apalis-eval.dts index 07da481bc441..14a62b5111ec 100644 --- a/arch/arm/boot/dts/tegra30-apalis-eval.dts +++ b/arch/arm/boot/dts/tegra30-apalis-eval.dts @@ -41,6 +41,7 @@ }; hdmi@54280000 { status = "okay"; + hdmi-supply = <®_5v0>; }; }; @@ -185,6 +186,7 @@ default-brightness-level = <6>; /* BKL1_ON */ enable-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; + power-supply = <®_3v3>; }; gpio-keys { @@ -207,6 +209,7 @@ compatible = "edt,et057090dhu", "simple-panel"; backlight = <&backlight>; + power-supply = <®_3v3>; }; pwmleds { @@ -231,6 +234,13 @@ }; }; + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3.3V_SW"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + reg_5v0: regulator-5v0 { compatible = "regulator-fixed"; regulator-name = "5V_SW"; diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi index 214a23722ab4..3b2e15519e4b 100644 --- a/arch/arm/boot/dts/tegra30-apalis.dtsi +++ b/arch/arm/boot/dts/tegra30-apalis.dtsi @@ -465,7 +465,8 @@ sgtl5000: codec@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; - VDDA-supply = <®_module_3v3>; + VDDA-supply = <®_module_3v3_audio>; + VDDD-supply = <®_1v8_vio>; VDDIO-supply = <®_module_3v3>; clocks = <&tegra_car TEGRA30_CLK_EXTERN1>; }; @@ -758,6 +759,14 @@ regulator-always-on; }; + reg_module_3v3_audio: regulator-module-3v3-audio { + compatible = "regulator-fixed"; + regulator-name = "+V3.3_AUDIO_AVDD_S"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + sound { compatible = "toradex,tegra-audio-sgtl5000-apalis_t30", "nvidia,tegra-audio-sgtl5000"; -- cgit v1.2.2 From e073452b4aa1c63f6bd7075269a0eae764a69fba Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Fri, 31 Aug 2018 18:37:51 +0200 Subject: ARM: tegra: apalis_t30: annotate uarts and move compatible to board Annotate UARTs and move the serial UART "nvidia,tegra30-hsuart" compatible definitions from the carrier board to the module level device trees. One could still override this in a custom carrier board device tree if required. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-apalis-eval.dts | 7 ++++--- arch/arm/boot/dts/tegra30-apalis.dtsi | 12 ++++++++++++ 2 files changed, 16 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/tegra30-apalis-eval.dts b/arch/arm/boot/dts/tegra30-apalis-eval.dts index 14a62b5111ec..cd4e45759ac8 100644 --- a/arch/arm/boot/dts/tegra30-apalis-eval.dts +++ b/arch/arm/boot/dts/tegra30-apalis-eval.dts @@ -45,22 +45,23 @@ }; }; + /* Apalis UART1 */ serial@70006000 { status = "okay"; }; + /* Apalis UART2 */ serial@70006040 { - compatible = "nvidia,tegra30-hsuart"; status = "okay"; }; + /* Apalis UART3 */ serial@70006200 { - compatible = "nvidia,tegra30-hsuart"; status = "okay"; }; + /* Apalis UART4 */ serial@70006300 { - compatible = "nvidia,tegra30-hsuart"; status = "okay"; }; diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi index 3b2e15519e4b..7e9d1b022982 100644 --- a/arch/arm/boot/dts/tegra30-apalis.dtsi +++ b/arch/arm/boot/dts/tegra30-apalis.dtsi @@ -449,6 +449,18 @@ }; }; + serial@70006040 { + compatible = "nvidia,tegra30-hsuart"; + }; + + serial@70006200 { + compatible = "nvidia,tegra30-hsuart"; + }; + + serial@70006300 { + compatible = "nvidia,tegra30-hsuart"; + }; + hdmiddc: i2c@7000c700 { clock-frequency = <10000>; }; -- cgit v1.2.2 From 95bcc02a899e162af7d154708416d1d723c34ecd Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Fri, 31 Aug 2018 18:37:52 +0200 Subject: ARM: tegra: apalis_t30: drop unused cami2c label Drop unused cami2c label. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-apalis-eval.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra30-apalis-eval.dts b/arch/arm/boot/dts/tegra30-apalis-eval.dts index cd4e45759ac8..3f15f327f293 100644 --- a/arch/arm/boot/dts/tegra30-apalis-eval.dts +++ b/arch/arm/boot/dts/tegra30-apalis-eval.dts @@ -95,7 +95,7 @@ * CAM_I2C: I2C3_SDA/SCL on MXM3 pin 201/203 (e.g. camera sensor on * carrier board) */ - cami2c: i2c@7000c500 { + i2c@7000c500 { status = "okay"; clock-frequency = <400000>; }; -- cgit v1.2.2 From 4eb7e5ede0157d1b2095aad34e91d247f029226a Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Fri, 31 Aug 2018 18:37:53 +0200 Subject: ARM: tegra: apalis_t30: white-space/newline clean-up White-space and newline clean-up. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-apalis-eval.dts | 5 +++-- arch/arm/boot/dts/tegra30-apalis.dtsi | 1 + 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/tegra30-apalis-eval.dts b/arch/arm/boot/dts/tegra30-apalis-eval.dts index 3f15f327f293..0a8900be0008 100644 --- a/arch/arm/boot/dts/tegra30-apalis-eval.dts +++ b/arch/arm/boot/dts/tegra30-apalis-eval.dts @@ -39,6 +39,7 @@ nvidia,panel = <&panel>; }; }; + hdmi@54280000 { status = "okay"; hdmi-supply = <®_5v0>; @@ -109,6 +110,7 @@ spi@7000d400 { status = "okay"; spi-max-frequency = <25000000>; + spidev0: spidev@1 { compatible = "spidev"; reg = <1>; @@ -120,6 +122,7 @@ spi@7000dc00 { status = "okay"; spi-max-frequency = <25000000>; + spidev1: spidev@2 { compatible = "spidev"; reg = <2>; @@ -180,7 +183,6 @@ backlight: backlight { compatible = "pwm-backlight"; - /* PWM_BKL1 */ pwms = <&pwm 0 5000000>; brightness-levels = <255 231 223 207 191 159 127 0>; @@ -208,7 +210,6 @@ * edt,et070080dh6: EDT 7.0" LCD TFT */ compatible = "edt,et057090dhu", "simple-panel"; - backlight = <&backlight>; power-supply = <®_3v3>; }; diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi index 7e9d1b022982..e84feac9b992 100644 --- a/arch/arm/boot/dts/tegra30-apalis.dtsi +++ b/arch/arm/boot/dts/tegra30-apalis.dtsi @@ -39,6 +39,7 @@ pci@3,0 { status = "okay"; nvidia,num-lanes = <1>; + pcie@0 { reg = <0 0 0 0 0>; local-mac-address = [00 00 00 00 00 00]; -- cgit v1.2.2 From d5330b4731dff3073609b8c56090eca32532db3d Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Fri, 31 Aug 2018 18:37:54 +0200 Subject: ARM: tegra: apalis_t30: drop unused mmc1/sd1 labels Drop unused mmc1/sd1 labels. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-apalis-eval.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/tegra30-apalis-eval.dts b/arch/arm/boot/dts/tegra30-apalis-eval.dts index 0a8900be0008..3f25bb307397 100644 --- a/arch/arm/boot/dts/tegra30-apalis-eval.dts +++ b/arch/arm/boot/dts/tegra30-apalis-eval.dts @@ -134,7 +134,7 @@ status = "okay"; }; - sd1: sdhci@78000000 { + sdhci@78000000 { status = "okay"; bus-width = <4>; /* SD1_CD# */ @@ -142,7 +142,7 @@ no-1-8-v; }; - mmc1: sdhci@78000400 { + sdhci@78000400 { status = "okay"; bus-width = <8>; /* MMC1_CD# */ -- cgit v1.2.2 From 005a00d862114c064d47a67f54f40c7c3128daa1 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Fri, 31 Aug 2018 18:37:55 +0200 Subject: ARM: tegra: apalis_t30: annotate mmc1/sd1 Annotate MMC1/SD1. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-apalis-eval.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/tegra30-apalis-eval.dts b/arch/arm/boot/dts/tegra30-apalis-eval.dts index 3f25bb307397..15e9de06c59a 100644 --- a/arch/arm/boot/dts/tegra30-apalis-eval.dts +++ b/arch/arm/boot/dts/tegra30-apalis-eval.dts @@ -134,6 +134,7 @@ status = "okay"; }; + /* Apalis SD1 */ sdhci@78000000 { status = "okay"; bus-width = <4>; @@ -142,6 +143,7 @@ no-1-8-v; }; + /* Apalis MMC1 */ sdhci@78000400 { status = "okay"; bus-width = <8>; -- cgit v1.2.2 From 8bf0d6b2a7ae84a397ef5b6e9e16c4f6dc679797 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Fri, 31 Aug 2018 18:37:56 +0200 Subject: ARM: tegra: apalis_t30: move dr_mode property from phy to controller Move dr_mode property from USB PHY node to controller. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-apalis-eval.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra30-apalis-eval.dts b/arch/arm/boot/dts/tegra30-apalis-eval.dts index 15e9de06c59a..9f2392a05532 100644 --- a/arch/arm/boot/dts/tegra30-apalis-eval.dts +++ b/arch/arm/boot/dts/tegra30-apalis-eval.dts @@ -155,11 +155,11 @@ /* EHCI instance 0: USB1_DP/N -> USBO1_DP/N */ usb@7d000000 { status = "okay"; + dr_mode = "otg"; }; usb-phy@7d000000 { status = "okay"; - dr_mode = "otg"; vbus-supply = <®_usbo1_vbus>; }; -- cgit v1.2.2 From 654b7139a2943285c96aa83921557f39cfebdad4 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Fri, 31 Aug 2018 18:37:57 +0200 Subject: ARM: tegra: apalis_t30: reorder backlight properties Reorder backlight properties. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-apalis-eval.dts | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/tegra30-apalis-eval.dts b/arch/arm/boot/dts/tegra30-apalis-eval.dts index 9f2392a05532..300ce726ff4d 100644 --- a/arch/arm/boot/dts/tegra30-apalis-eval.dts +++ b/arch/arm/boot/dts/tegra30-apalis-eval.dts @@ -185,13 +185,12 @@ backlight: backlight { compatible = "pwm-backlight"; - /* PWM_BKL1 */ - pwms = <&pwm 0 5000000>; brightness-levels = <255 231 223 207 191 159 127 0>; default-brightness-level = <6>; /* BKL1_ON */ enable-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; power-supply = <®_3v3>; + pwms = <&pwm 0 5000000>; /* BKL1_PWM */ }; gpio-keys { -- cgit v1.2.2 From e0911663bcd69555b9ac4b7bbd443911c5521cbb Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Fri, 31 Aug 2018 18:37:58 +0200 Subject: ARM: tegra: apalis_t30: drop pwmleds Drop pwmleds in favour of using regular PWMs. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-apalis-eval.dts | 22 ---------------------- 1 file changed, 22 deletions(-) diff --git a/arch/arm/boot/dts/tegra30-apalis-eval.dts b/arch/arm/boot/dts/tegra30-apalis-eval.dts index 300ce726ff4d..5d1bc8560dbe 100644 --- a/arch/arm/boot/dts/tegra30-apalis-eval.dts +++ b/arch/arm/boot/dts/tegra30-apalis-eval.dts @@ -215,28 +215,6 @@ power-supply = <®_3v3>; }; - pwmleds { - compatible = "pwm-leds"; - - pwm1 { - label = "PWM1"; - pwms = <&pwm 3 19600>; - max-brightness = <255>; - }; - - pwm2 { - label = "PWM2"; - pwms = <&pwm 2 19600>; - max-brightness = <255>; - }; - - pwm3 { - label = "PWM3"; - pwms = <&pwm 1 19600>; - max-brightness = <255>; - }; - }; - reg_3v3: regulator-3v3 { compatible = "regulator-fixed"; regulator-name = "3.3V_SW"; -- cgit v1.2.2 From 727002e06144caf8cac2c1244fe028ddb3d2db10 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Fri, 31 Aug 2018 18:37:59 +0200 Subject: ARM: tegra: apalis_t30: pinmux clean-up Clean-up pinmuxing: - white-space clean-up - explicitly disable input of BKL1_ON, BKL1_PWM and BKL1_PWM_EN# - annotate Apalis I2C3 usage for CAM - get rid of nvidia,lock property - add missing eMMC sdmmc4_cmd_pt7 and explicitly enable input - explicitly disable lcd_dc1_pd2 (e.g. LM95245 I2C address pin) - annotate TOUCH_PEN_INT# being on-module - As underscores in node names are not recommended replace them all where possible with dashes. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-apalis.dtsi | 88 ++++++++++++++++++----------------- 1 file changed, 45 insertions(+), 43 deletions(-) diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi index e84feac9b992..cb587670a5af 100644 --- a/arch/arm/boot/dts/tegra30-apalis.dtsi +++ b/arch/arm/boot/dts/tegra30-apalis.dtsi @@ -63,18 +63,18 @@ state_default: pinmux { /* Analogue Audio (On-module) */ - clk1_out_pw4 { + clk1-out-pw4 { nvidia,pins = "clk1_out_pw4"; nvidia,function = "extperiph1"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - dap3_fs_pp0 { - nvidia,pins = "dap3_fs_pp0", - "dap3_sclk_pp3", - "dap3_din_pp1", - "dap3_dout_pp2"; + dap3-fs-pp0 { + nvidia,pins = "dap3_fs_pp0", + "dap3_sclk_pp3", + "dap3_din_pp1", + "dap3_dout_pp2"; nvidia,function = "i2s2"; nvidia,pull = ; nvidia,tristate = ; @@ -86,25 +86,28 @@ nvidia,function = "rsvd4"; nvidia,pull = ; nvidia,tristate = ; + nvidia,enable-input = ; }; /* Apalis BKL1_PWM */ - uart3_rts_n_pc0 { + uart3-rts-n-pc0 { nvidia,pins = "uart3_rts_n_pc0"; nvidia,function = "pwm0"; nvidia,pull = ; nvidia,tristate = ; + nvidia,enable-input = ; }; /* BKL1_PWM_EN#, disable TPS65911 PMIC PWM backlight */ - uart3_cts_n_pa1 { + uart3-cts-n-pa1 { nvidia,pins = "uart3_cts_n_pa1"; nvidia,function = "rsvd2"; nvidia,pull = ; nvidia,tristate = ; + nvidia,enable-input = ; }; /* Apalis CAN1 on SPI6 */ - spi2_cs0_n_px3 { + spi2-cs0-n-px3 { nvidia,pins = "spi2_cs0_n_px3", "spi2_miso_px1", "spi2_mosi_px0", @@ -114,7 +117,7 @@ nvidia,tristate = ; }; /* CAN_INT1 */ - spi2_cs1_n_pw2 { + spi2-cs1-n-pw2 { nvidia,pins = "spi2_cs1_n_pw2"; nvidia,function = "spi3"; nvidia,pull = ; @@ -123,7 +126,7 @@ }; /* Apalis CAN2 on SPI4 */ - gmi_a16_pj7 { + gmi-a16-pj7 { nvidia,pins = "gmi_a16_pj7", "gmi_a17_pb0", "gmi_a18_pb1", @@ -134,7 +137,7 @@ nvidia,enable-input = ; }; /* CAN_INT2 */ - spi2_cs2_n_pw3 { + spi2-cs2-n-pw3 { nvidia,pins = "spi2_cs2_n_pw3"; nvidia,function = "spi3"; nvidia,pull = ; @@ -143,20 +146,20 @@ }; /* Apalis Digital Audio */ - clk1_req_pee2 { + clk1-req-pee2 { nvidia,pins = "clk1_req_pee2"; nvidia,function = "hda"; nvidia,pull = ; nvidia,tristate = ; }; - clk2_out_pw5 { + clk2-out-pw5 { nvidia,pins = "clk2_out_pw5"; nvidia,function = "extperiph2"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - dap1_fs_pn0 { + dap1-fs-pn0 { nvidia,pins = "dap1_fs_pn0", "dap1_din_pn1", "dap1_dout_pn2", @@ -166,26 +169,25 @@ nvidia,tristate = ; }; - /* Apalis I2C3 */ - cam_i2c_scl_pbb1 { + /* Apalis I2C3 (CAM) */ + cam-i2c-scl-pbb1 { nvidia,pins = "cam_i2c_scl_pbb1", "cam_i2c_sda_pbb2"; nvidia,function = "i2c3"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; - nvidia,lock = ; nvidia,open-drain = ; }; /* Apalis MMC1 */ - sdmmc3_clk_pa6 { + sdmmc3-clk-pa6 { nvidia,pins = "sdmmc3_clk_pa6"; nvidia,function = "sdmmc3"; nvidia,pull = ; nvidia,tristate = ; }; - sdmmc3_dat0_pb7 { + sdmmc3-dat0-pb7 { nvidia,pins = "sdmmc3_cmd_pa7", "sdmmc3_dat0_pb7", "sdmmc3_dat1_pb6", @@ -241,7 +243,7 @@ }; /* Apalis RESET_MOCI# */ - gmi_rst_n_pi4 { + gmi-rst-n-pi4 { nvidia,pins = "gmi_rst_n_pi4"; nvidia,function = "gmi"; nvidia,pull = ; @@ -249,13 +251,13 @@ }; /* Apalis SD1 */ - sdmmc1_clk_pz0 { + sdmmc1-clk-pz0 { nvidia,pins = "sdmmc1_clk_pz0"; nvidia,function = "sdmmc1"; nvidia,pull = ; nvidia,tristate = ; }; - sdmmc1_cmd_pz1 { + sdmmc1-cmd-pz1 { nvidia,pins = "sdmmc1_cmd_pz1", "sdmmc1_dat0_py7", "sdmmc1_dat1_py6", @@ -266,7 +268,7 @@ nvidia,tristate = ; }; /* Apalis SD1_CD# */ - clk2_req_pcc5 { + clk2-req-pcc5 { nvidia,pins = "clk2_req_pcc5"; nvidia,function = "rsvd2"; nvidia,pull = ; @@ -275,7 +277,7 @@ }; /* Apalis SPI1 */ - spi1_sck_px5 { + spi1-sck-px5 { nvidia,pins = "spi1_sck_px5", "spi1_mosi_px4", "spi1_miso_px7", @@ -286,7 +288,7 @@ }; /* Apalis SPI2 */ - lcd_sck_pz4 { + lcd-sck-pz4 { nvidia,pins = "lcd_sck_pz4", "lcd_sdout_pn5", "lcd_sdin_pz2", @@ -297,7 +299,7 @@ }; /* Apalis UART1 */ - ulpi_data0 { + ulpi-data0 { nvidia,pins = "ulpi_data0_po1", "ulpi_data1_po2", "ulpi_data2_po3", @@ -312,7 +314,7 @@ }; /* Apalis UART2 */ - ulpi_clk_py0 { + ulpi-clk-py0 { nvidia,pins = "ulpi_clk_py0", "ulpi_dir_py1", "ulpi_nxt_py2", @@ -323,7 +325,7 @@ }; /* Apalis UART3 */ - uart2_rxd_pc3 { + uart2-rxd-pc3 { nvidia,pins = "uart2_rxd_pc3", "uart2_txd_pc2"; nvidia,function = "uartb"; @@ -332,7 +334,7 @@ }; /* Apalis UART4 */ - uart3_rxd_pw7 { + uart3-rxd-pw7 { nvidia,pins = "uart3_rxd_pw7", "uart3_txd_pw6"; nvidia,function = "uartc"; @@ -341,7 +343,7 @@ }; /* Apalis USBO1_EN */ - gen2_i2c_scl_pt5 { + gen2-i2c-scl-pt5 { nvidia,pins = "gen2_i2c_scl_pt5"; nvidia,function = "rsvd4"; nvidia,open-drain = ; @@ -350,7 +352,7 @@ }; /* Apalis USBO1_OC# */ - gen2_i2c_sda_pt6 { + gen2-i2c-sda-pt6 { nvidia,pins = "gen2_i2c_sda_pt6"; nvidia,function = "rsvd4"; nvidia,open-drain = ; @@ -369,14 +371,16 @@ }; /* eMMC (On-module) */ - sdmmc4_clk_pcc4 { + sdmmc4-clk-pcc4 { nvidia,pins = "sdmmc4_clk_pcc4", + "sdmmc4_cmd_pt7", "sdmmc4_rst_n_pcc3"; nvidia,function = "sdmmc4"; nvidia,pull = ; nvidia,tristate = ; + nvidia,enable-input = ; }; - sdmmc4_dat0_paa0 { + sdmmc4-dat0-paa0 { nvidia,pins = "sdmmc4_dat0_paa0", "sdmmc4_dat1_paa1", "sdmmc4_dat2_paa2", @@ -388,6 +392,7 @@ nvidia,function = "sdmmc4"; nvidia,pull = ; nvidia,tristate = ; + nvidia,enable-input = ; }; /* LVDS Transceiver Configuration */ @@ -400,7 +405,6 @@ nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; - nvidia,lock = ; }; pbb3 { nvidia,pins = "pbb3", @@ -411,18 +415,16 @@ nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; - nvidia,lock = ; }; /* Power I2C (On-module) */ - pwr_i2c_scl_pz6 { + pwr-i2c-scl-pz6 { nvidia,pins = "pwr_i2c_scl_pz6", "pwr_i2c_sda_pz7"; nvidia,function = "i2cpwr"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; - nvidia,lock = ; nvidia,open-drain = ; }; @@ -431,15 +433,15 @@ * temperature sensor therefore requires disabling for * now */ - lcd_dc1_pd2 { + lcd-dc1-pd2 { nvidia,pins = "lcd_dc1_pd2"; nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; - /* TOUCH_PEN_INT# */ + /* TOUCH_PEN_INT# (On-module) */ pv0 { nvidia,pins = "pv0"; nvidia,function = "rsvd1"; -- cgit v1.2.2 From 368f139bf7287d19c7df150a1da692dae4465d3a Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Fri, 31 Aug 2018 18:38:00 +0200 Subject: ARM: tegra: apalis_t30: add missing pinmux Explicitly mux all T30 SoC balls now: - Apalis GPIO - Apalis HDMI1 - Apalis I2C1 - Apalis I2C2 (DDC) - Apalis LCD1 - Apalis Parallel Camera - Apalis SATA1_ACT# - Apalis SPDIF1 - Apalis TS (Low-speed type specific) - Apalis USBH_EN - Apalis USBH_OC# - Apalis VGA1 - on-module i210/i211 LAN control signals - not connected and therefore disabled signals Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-apalis.dtsi | 370 ++++++++++++++++++++++++++++++++++ 1 file changed, 370 insertions(+) diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi index cb587670a5af..e37d22e2ceef 100644 --- a/arch/arm/boot/dts/tegra30-apalis.dtsi +++ b/arch/arm/boot/dts/tegra30-apalis.dtsi @@ -169,6 +169,68 @@ nvidia,tristate = ; }; + /* Apalis GPIO */ + kb-col0-pq0 { + nvidia,pins = "kb_col0_pq0", + "kb_col1_pq1", + "kb_row10_ps2", + "kb_row11_ps3", + "kb_row12_ps4", + "kb_row13_ps5", + "kb_row14_ps6", + "kb_row15_ps7"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + /* Multiplexed and therefore disabled */ + owr { + nvidia,pins = "owr"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis HDMI1 */ + hdmi-cec-pee3 { + nvidia,pins = "hdmi_cec_pee3"; + nvidia,function = "cec"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + hdmi-int-pn7 { + nvidia,pins = "hdmi_int_pn7"; + nvidia,function = "hdmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis I2C1 */ + gen1-i2c-scl-pc4 { + nvidia,pins = "gen1_i2c_scl_pc4", + "gen1_i2c_sda_pc5"; + nvidia,function = "i2c1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + /* Apalis I2C2 (DDC) */ + ddc-scl-pv4 { + nvidia,pins = "ddc_scl_pv4", + "ddc_sda_pv5"; + nvidia,function = "i2c4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + /* Apalis I2C3 (CAM) */ cam-i2c-scl-pbb1 { nvidia,pins = "cam_i2c_scl_pbb1", @@ -180,6 +242,42 @@ nvidia,open-drain = ; }; + /* Apalis LCD1 */ + lcd-d0-pe0 { + nvidia,pins = "lcd_d0_pe0", + "lcd_d1_pe1", + "lcd_d2_pe2", + "lcd_d3_pe3", + "lcd_d4_pe4", + "lcd_d5_pe5", + "lcd_d6_pe6", + "lcd_d7_pe7", + "lcd_d8_pf0", + "lcd_d9_pf1", + "lcd_d10_pf2", + "lcd_d11_pf3", + "lcd_d12_pf4", + "lcd_d13_pf5", + "lcd_d14_pf6", + "lcd_d15_pf7", + "lcd_d16_pm0", + "lcd_d17_pm1", + "lcd_d18_pm2", + "lcd_d19_pm3", + "lcd_d20_pm4", + "lcd_d21_pm5", + "lcd_d22_pm6", + "lcd_d23_pm7", + "lcd_de_pj1", + "lcd_hsync_pj3", + "lcd_pclk_pb3", + "lcd_vsync_pj4"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + /* Apalis MMC1 */ sdmmc3-clk-pa6 { nvidia,pins = "sdmmc3_clk_pa6"; @@ -210,6 +308,77 @@ nvidia,enable-input = ; }; + /* Apalis Parallel Camera */ + cam-mclk-pcc0 { + nvidia,pins = "cam_mclk_pcc0"; + nvidia,function = "vi_alt3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + vi-vsync-pd6 { + nvidia,pins = "vi_d0_pt4", + "vi_d1_pd5", + "vi_d2_pl0", + "vi_d3_pl1", + "vi_d4_pl2", + "vi_d5_pl3", + "vi_d6_pl4", + "vi_d7_pl5", + "vi_d8_pl6", + "vi_d9_pl7", + "vi_d10_pt2", + "vi_d11_pt3", + "vi_hsync_pd7", + "vi_pclk_pt0", + "vi_vsync_pd6"; + nvidia,function = "vi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + /* Multiplexed and therefore disabled */ + kb-col2-pq2 { + nvidia,pins = "kb_col2_pq2", + "kb_col3_pq3", + "kb_col4_pq4", + "kb_row4_pr4"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb-row0-pr0 { + nvidia,pins = "kb_row0_pr0", + "kb_row1_pr1", + "kb_row2_pr2", + "kb_row3_pr3"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb-row5-pr5 { + nvidia,pins = "kb_row5_pr5", + "kb_row6_pr6", + "kb_row7_pr7"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + /* + * VI level-shifter direction + * (pull-down => default direction input) + */ + vi-mclk-pt1 { + nvidia,pins = "vi_mclk_pt1"; + nvidia,function = "vi_alt3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + /* Apalis PWM1 */ pu6 { nvidia,pins = "pu6"; @@ -250,6 +419,15 @@ nvidia,tristate = ; }; + /* Apalis SATA1_ACT# */ + pex-l0-prsnt-n-pdd0 { + nvidia,pins = "pex_l0_prsnt_n_pdd0"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + /* Apalis SD1 */ sdmmc1-clk-pz0 { nvidia,pins = "sdmmc1_clk_pz0"; @@ -276,6 +454,16 @@ nvidia,enable-input = ; }; + /* Apalis SPDIF1 */ + spdif-out-pk5 { + nvidia,pins = "spdif_out_pk5", + "spdif_in_pk6"; + nvidia,function = "spdif"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + /* Apalis SPI1 */ spi1-sck-px5 { nvidia,pins = "spi1_sck_px5", @@ -298,6 +486,28 @@ nvidia,tristate = ; }; + /* + * Apalis TS (Low-speed type specific) + * pins may be used as GPIOs + */ + kb-col5-pq5 { + nvidia,pins = "kb_col5_pq5"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb-col6-pq6 { + nvidia,pins = "kb_col6_pq6", + "kb_col7_pq7", + "kb_row8_ps0", + "kb_row9_ps1"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + /* Apalis UART1 */ ulpi-data0 { nvidia,pins = "ulpi_data0_po1", @@ -342,6 +552,24 @@ nvidia,tristate = ; }; + /* Apalis USBH_EN */ + pex-l0-rst-n-pdd1 { + nvidia,pins = "pex_l0_rst_n_pdd1"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis USBH_OC# */ + pex-l0-clkreq-n-pdd2 { + nvidia,pins = "pex_l0_clkreq_n_pdd2"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + /* Apalis USBO1_EN */ gen2-i2c-scl-pt5 { nvidia,pins = "gen2_i2c_scl_pt5"; @@ -361,6 +589,16 @@ nvidia,enable-input = ; }; + /* Apalis VGA1 not supported and therefore disabled */ + crt-hsync-pv6 { + nvidia,pins = "crt_hsync_pv6", + "crt_vsync_pv7"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + /* Apalis WAKE1_MICO */ pv1 { nvidia,pins = "pv1"; @@ -395,6 +633,33 @@ nvidia,enable-input = ; }; + /* LAN i210/i211 DEV_OFF_N, PE_RST_N (On-module) */ + pex-l2-prsnt-n-pdd7 { + nvidia,pins = "pex_l2_prsnt_n_pdd7", + "pex_l2_rst_n_pcc6"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + /* LAN i210/i211 PE_WAKE_N, SDP3 (On-module) */ + pex-wake-n-pdd3 { + nvidia,pins = "pex_wake_n_pdd3", + "pex_l2_clkreq_n_pcc7"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + /* LAN i210/i211 SMB_ALERT_N (On-module) */ + sys-clk-req-pz5 { + nvidia,pins = "sys_clk_req_pz5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + /* LVDS Transceiver Configuration */ pbb0 { nvidia,pins = "pbb0", @@ -417,6 +682,111 @@ nvidia,enable-input = ; }; + /* Not connected and therefore disabled */ + clk-32k-out-pa0 { + nvidia,pins = "clk3_out_pee0", + "clk3_req_pee1", + "clk_32k_out_pa0", + "dap4_din_pp5", + "dap4_dout_pp6", + "dap4_fs_pp4", + "dap4_sclk_pp7"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap2-fs-pa2 { + nvidia,pins = "dap2_fs_pa2", + "dap2_sclk_pa3", + "dap2_din_pa4", + "dap2_dout_pa5", + "lcd_dc0_pn6", + "lcd_m1_pw1", + "lcd_pwr1_pc1", + "pex_l1_clkreq_n_pdd6", + "pex_l1_prsnt_n_pdd4", + "pex_l1_rst_n_pdd5"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-ad0-pg0 { + nvidia,pins = "gmi_ad0_pg0", + "gmi_ad2_pg2", + "gmi_ad3_pg3", + "gmi_ad4_pg4", + "gmi_ad5_pg5", + "gmi_ad6_pg6", + "gmi_ad7_pg7", + "gmi_ad8_ph0", + "gmi_ad9_ph1", + "gmi_ad10_ph2", + "gmi_ad11_ph3", + "gmi_ad12_ph4", + "gmi_ad13_ph5", + "gmi_ad14_ph6", + "gmi_ad15_ph7", + "gmi_adv_n_pk0", + "gmi_clk_pk1", + "gmi_cs4_n_pk2", + "gmi_cs2_n_pk3", + "gmi_dqs_pi2", + "gmi_iordy_pi5", + "gmi_oe_n_pi1", + "gmi_wait_pi7", + "gmi_wr_n_pi0", + "lcd_cs1_n_pw0", + "pu0", + "pu1", + "pu2"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-cs0-n-pj0 { + nvidia,pins = "gmi_cs0_n_pj0", + "gmi_cs1_n_pj2", + "gmi_cs3_n_pk4"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-cs6-n-pi3 { + nvidia,pins = "gmi_cs6_n_pi3"; + nvidia,function = "sata"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-cs7-n-pi6 { + nvidia,pins = "gmi_cs7_n_pi6"; + nvidia,function = "gmi_alt"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd-pwr0-pb2 { + nvidia,pins = "lcd_pwr0_pb2", + "lcd_pwr2_pc6", + "lcd_wr_n_pz3"; + nvidia,function = "hdcp"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart2-cts-n-pj5 { + nvidia,pins = "uart2_cts_n_pj5", + "uart2_rts_n_pj6"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + /* Power I2C (On-module) */ pwr-i2c-scl-pz6 { nvidia,pins = "pwr_i2c_scl_pz6", -- cgit v1.2.2 From f38f7998b7c7f55db2947b49733aed2fc177747b Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Fri, 31 Aug 2018 18:38:01 +0200 Subject: ARM: tegra: apalis_t30: use proper irq-gpio for stmpe811 Use proper irq-gpio for stmpe811 touch controller. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-apalis.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi index e37d22e2ceef..43d914f754e8 100644 --- a/arch/arm/boot/dts/tegra30-apalis.dtsi +++ b/arch/arm/boot/dts/tegra30-apalis.dtsi @@ -975,8 +975,7 @@ stmpe811@41 { compatible = "st,stmpe811"; reg = <0x41>; - interrupts = ; - interrupt-parent = <&gpio>; + irq-gpio = <&gpio TEGRA_GPIO(V, 0) IRQ_TYPE_LEVEL_LOW>; interrupt-controller; id = <0>; blocks = <0x5>; -- cgit v1.2.2 From 16f53ab291f3e829ce56a2200870cdbf897df6d7 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Fri, 31 Aug 2018 18:38:02 +0200 Subject: ARM: tegra: apalis_t30: further lm95245 temperature sensor annotation Further LM95245 temperature sensor annotation. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-apalis.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi index 43d914f754e8..c3e37d944c62 100644 --- a/arch/arm/boot/dts/tegra30-apalis.dtsi +++ b/arch/arm/boot/dts/tegra30-apalis.dtsi @@ -1009,7 +1009,7 @@ /* * LM95245 temperature sensor - * Note: OVERT_N directly connected to PMIC PWRDN + * Note: OVERT1# directly connected to TPS65911 PMIC PWRDN */ temp-sensor@4c { compatible = "national,lm95245"; -- cgit v1.2.2 From 5f1fe7b62dceb24268aaf5b9327328cf54abc1f7 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Fri, 31 Aug 2018 18:38:03 +0200 Subject: ARM: tegra: apalis_t30: add i2c-thermtrip Add i2c-thermtrip which would set the DEV_OFF bit in the DCDC control register of the TPS65911 PMIC. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-apalis.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi index c3e37d944c62..02d0117e9398 100644 --- a/arch/arm/boot/dts/tegra30-apalis.dtsi +++ b/arch/arm/boot/dts/tegra30-apalis.dtsi @@ -1071,6 +1071,14 @@ nvidia,core-pwr-off-time = <0>; nvidia,core-power-req-active-high; nvidia,sys-clock-req-active-high; + + /* Set DEV_OFF bit in DCDC control register of TPS65911 PMIC */ + i2c-thermtrip { + nvidia,i2c-controller-id = <4>; + nvidia,bus-addr = <0x2d>; + nvidia,reg-addr = <0x3f>; + nvidia,reg-data = <0x1>; + }; }; ahub@70080000 { -- cgit v1.2.2 From 0f0a3831290d05a32a653736bc14cfc0f391643b Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Fri, 31 Aug 2018 18:38:04 +0200 Subject: ARM: tegra: apalis_t30: add proper emmc vmmc and vqmmc supplies Add proper eMMC vmmc and vqmmc supplies e.g. fixing signalling voltage. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-apalis.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi index 02d0117e9398..2e2cdd454fe3 100644 --- a/arch/arm/boot/dts/tegra30-apalis.dtsi +++ b/arch/arm/boot/dts/tegra30-apalis.dtsi @@ -1092,6 +1092,8 @@ status = "okay"; bus-width = <8>; non-removable; + vmmc-supply = <®_module_3v3>; /* VCC */ + vqmmc-supply = <®_1v8_vio>; /* VCCQ */ }; clocks { -- cgit v1.2.2 From 200be313fdc9bb9810bba3450698c1bf923b814f Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Fri, 31 Aug 2018 18:38:05 +0200 Subject: ARM: tegra: apalis_t30: enable emmc ddr52 mode Add mmc-ddr-1_8v property enabling eMMC DDR52 mode. root@apalis-t30:~# cat /sys/kernel/debug/mmc1/ios clock: 52000000 Hz actual clock: 52000000 Hz vdd: 21 (3.3 ~ 3.4 V) bus mode: 2 (push-pull) chip select: 0 (don't care) power mode: 2 (on) bus width: 3 (8 bits) timing spec: 8 (mmc DDR52) signal voltage: 1 (1.80 V) driver type: 0 (driver type B) root@apalis-t30:~# hdparm -t /dev/mmcblk1 /dev/mmcblk1: Timing buffered disk reads: 232 MB in 3.01 seconds = 77.10 MB/sec Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-apalis.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi index 2e2cdd454fe3..6d6f17422478 100644 --- a/arch/arm/boot/dts/tegra30-apalis.dtsi +++ b/arch/arm/boot/dts/tegra30-apalis.dtsi @@ -1094,6 +1094,7 @@ non-removable; vmmc-supply = <®_module_3v3>; /* VCC */ vqmmc-supply = <®_1v8_vio>; /* VCCQ */ + mmc-ddr-1_8v; }; clocks { -- cgit v1.2.2 From 7b0f47aa62085db10d54849092f58f317b49b84d Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Fri, 31 Aug 2018 18:38:06 +0200 Subject: ARM: tegra: apalis_t30: get rid of fake clocks simple bus Get rid of the fake clocks simple bus and use node names as per the actual schematics. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-apalis.dtsi | 27 +++++++++------------------ 1 file changed, 9 insertions(+), 18 deletions(-) diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi index 6d6f17422478..d80101df2228 100644 --- a/arch/arm/boot/dts/tegra30-apalis.dtsi +++ b/arch/arm/boot/dts/tegra30-apalis.dtsi @@ -1097,25 +1097,16 @@ mmc-ddr-1_8v; }; - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clk@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; + clk32k_in: xtal1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; - clk16m: clk@1 { - compatible = "fixed-clock"; - reg = <1>; - #clock-cells = <0>; - clock-frequency = <16000000>; - clock-output-names = "clk16m"; - }; + clk16m: osc4 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <16000000>; }; reg_1v8_avdd_hdmi_pll: regulator-1v8-avdd-hdmi-pll { -- cgit v1.2.2 From 70451b5e6733d823632ebf1a73ace9b17f28ce47 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Fri, 31 Aug 2018 18:38:07 +0200 Subject: ARM: tegra: apalis_t30: line break long compatible property line Line break long compatible property line. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-apalis-eval.dts | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra30-apalis-eval.dts b/arch/arm/boot/dts/tegra30-apalis-eval.dts index 5d1bc8560dbe..97e2f1822a94 100644 --- a/arch/arm/boot/dts/tegra30-apalis-eval.dts +++ b/arch/arm/boot/dts/tegra30-apalis-eval.dts @@ -6,7 +6,8 @@ / { model = "Toradex Apalis T30 on Apalis Evaluation Board"; - compatible = "toradex,apalis_t30-eval", "toradex,apalis_t30", "nvidia,tegra30"; + compatible = "toradex,apalis_t30-eval", "toradex,apalis_t30", + "nvidia,tegra30"; aliases { rtc0 = "/i2c@7000c000/rtc@68"; -- cgit v1.2.2 From b0fa0105b496abf6c51bf79abf490ea4e0ee9855 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Fri, 31 Aug 2018 18:38:08 +0200 Subject: dt-bindings: add broadcom (formerly plx technology) vendor prefix MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit PLX Technology meanwhile got bought by Broadcom Corporation but the vendor prefix plx is still used in 8 current device trees. This silences the following checkpatch.pl warning: WARNING: DT compatible string vendor "plx" appears un-documented -- check ./Documentation/devicetree/bindings/vendor-prefixes.txt Signed-off-by: Marcel Ziswiler Reviewed-by: Andreas Färber Acked-by: Rob Herring Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 2c3fc512e746..e40312dcba7d 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -297,6 +297,7 @@ pine64 Pine64 pixcir PIXCIR MICROELECTRONICS Co., Ltd plathome Plat'Home Co., Ltd. plda PLDA +plx Broadcom Corporation (formerly PLX Technology) portwell Portwell Inc. poslab Poslab Technology Co., Ltd. powervr PowerVR (deprecated, use img) -- cgit v1.2.2 From 63a11def21eaf5da502e657695dbe389bc40879f Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Fri, 31 Aug 2018 18:38:09 +0200 Subject: ARM: tegra: apalis_t30: drop module level model and compatible Drop model and compatible nodes from the module level device tree as they get overridden by the carrier board device tree anyway. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-apalis.dtsi | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi index d80101df2228..e7793f3b19d2 100644 --- a/arch/arm/boot/dts/tegra30-apalis.dtsi +++ b/arch/arm/boot/dts/tegra30-apalis.dtsi @@ -7,9 +7,6 @@ * 2GB: V1.0B, V1.0C, V1.0E, V1.1A */ / { - model = "Toradex Apalis T30"; - compatible = "toradex,apalis_t30", "nvidia,tegra30"; - memory@80000000 { reg = <0x80000000 0x40000000>; }; -- cgit v1.2.2 From 317d9f7bedc4ee6b4d146e0a434cf3cb9f09b1ff Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Fri, 31 Aug 2018 18:38:10 +0200 Subject: ARM: tegra: apalis_t30: drop obsolete spidev nodes Drop obsolete spidev device tree nodes as nowadays one should do this by binding the spidev driver to specific instances/chip selects at runtime. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-apalis-eval.dts | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/arch/arm/boot/dts/tegra30-apalis-eval.dts b/arch/arm/boot/dts/tegra30-apalis-eval.dts index 97e2f1822a94..bbde98fd9712 100644 --- a/arch/arm/boot/dts/tegra30-apalis-eval.dts +++ b/arch/arm/boot/dts/tegra30-apalis-eval.dts @@ -111,24 +111,12 @@ spi@7000d400 { status = "okay"; spi-max-frequency = <25000000>; - - spidev0: spidev@1 { - compatible = "spidev"; - reg = <1>; - spi-max-frequency = <25000000>; - }; }; /* SPI5: Apalis SPI2 */ spi@7000dc00 { status = "okay"; spi-max-frequency = <25000000>; - - spidev1: spidev@2 { - compatible = "spidev"; - reg = <2>; - spi-max-frequency = <25000000>; - }; }; hda@70030000 { -- cgit v1.2.2 From da25001ca651430f13c0f3bebec0e969b1b4de63 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Fri, 31 Aug 2018 18:38:11 +0200 Subject: ARM: tegra: apalis_t30: hog group for pcie switch reset gpio The Apalis Evaluation Board uses Apalis GPIO7 on MXM3 pin 15 as reset signal for its PLX PEX 8605 PCIe Switch. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-apalis-eval.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/tegra30-apalis-eval.dts b/arch/arm/boot/dts/tegra30-apalis-eval.dts index bbde98fd9712..9d9dda6c0246 100644 --- a/arch/arm/boot/dts/tegra30-apalis-eval.dts +++ b/arch/arm/boot/dts/tegra30-apalis-eval.dts @@ -240,3 +240,13 @@ vin-supply = <®_5v0>; }; }; + +&gpio { + /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */ + pex-perst-n { + gpio-hog; + gpios = ; + output-high; + line-name = "PEX_PERST_N"; + }; +}; -- cgit v1.2.2 From 467176025c5d7f50739117ae2806cc035d9878ab Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Fri, 31 Aug 2018 18:38:12 +0200 Subject: ARM: tegra: apalis_t30: rename hdmiddc to hdmi_ddc Rename hdmiddc to hdmi_ddc to be more in-line with other device trees. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-apalis-eval.dts | 2 +- arch/arm/boot/dts/tegra30-apalis.dtsi | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/tegra30-apalis-eval.dts b/arch/arm/boot/dts/tegra30-apalis-eval.dts index 9d9dda6c0246..9381f65a9bf5 100644 --- a/arch/arm/boot/dts/tegra30-apalis-eval.dts +++ b/arch/arm/boot/dts/tegra30-apalis-eval.dts @@ -103,7 +103,7 @@ }; /* DDC: I2C2_SDA/SCL on MXM3 pin 205/207 (e.g. display EDID) */ - hdmiddc: i2c@7000c700 { + i2c@7000c700 { status = "okay"; }; diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi index e7793f3b19d2..f15954995231 100644 --- a/arch/arm/boot/dts/tegra30-apalis.dtsi +++ b/arch/arm/boot/dts/tegra30-apalis.dtsi @@ -46,7 +46,7 @@ host1x@50000000 { hdmi@54280000 { - nvidia,ddc-i2c-bus = <&hdmiddc>; + nvidia,ddc-i2c-bus = <&hdmi_ddc>; nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; pll-supply = <®_1v8_avdd_hdmi_pll>; @@ -831,7 +831,7 @@ compatible = "nvidia,tegra30-hsuart"; }; - hdmiddc: i2c@7000c700 { + hdmi_ddc: i2c@7000c700 { clock-frequency = <10000>; }; -- cgit v1.2.2 From b4cfc776657b85675cbfc05c191363f78b55fd75 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Fri, 31 Aug 2018 18:38:13 +0200 Subject: ARM: tegra: apalis_t30: rename tps65911@2d, stmpe811@41 and tps62362@60 Rename a few nodes using more common names: - rename tps65911@2d to pmic@2d - rename stmpe811@41 to touchscreen@41 - rename tps62362@60 to regulator@60 Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-apalis-eval.dts | 2 +- arch/arm/boot/dts/tegra30-apalis.dtsi | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/tegra30-apalis-eval.dts b/arch/arm/boot/dts/tegra30-apalis-eval.dts index 9381f65a9bf5..fdfadda72e0d 100644 --- a/arch/arm/boot/dts/tegra30-apalis-eval.dts +++ b/arch/arm/boot/dts/tegra30-apalis-eval.dts @@ -11,7 +11,7 @@ aliases { rtc0 = "/i2c@7000c000/rtc@68"; - rtc1 = "/i2c@7000d000/tps65911@2d"; + rtc1 = "/i2c@7000d000/pmic@2d"; rtc2 = "/rtc@7000e000"; serial0 = &uarta; serial1 = &uartb; diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi index f15954995231..a31b112f631d 100644 --- a/arch/arm/boot/dts/tegra30-apalis.dtsi +++ b/arch/arm/boot/dts/tegra30-apalis.dtsi @@ -853,7 +853,7 @@ clocks = <&tegra_car TEGRA30_CLK_EXTERN1>; }; - pmic: tps65911@2d { + pmic: pmic@2d { compatible = "ti,tps65911"; reg = <0x2d>; @@ -969,7 +969,7 @@ }; /* STMPE811 touch screen controller */ - stmpe811@41 { + touchscreen@41 { compatible = "st,stmpe811"; reg = <0x41>; irq-gpio = <&gpio TEGRA_GPIO(V, 0) IRQ_TYPE_LEVEL_LOW>; @@ -1014,7 +1014,7 @@ }; /* SW: +V1.2_VDD_CORE */ - tps62362@60 { + regulator@60 { compatible = "ti,tps62362"; reg = <0x60>; -- cgit v1.2.2 From b38f6aa4b60a1fcc41f5c469981f8f62d6070ee3 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Fri, 31 Aug 2018 18:38:14 +0200 Subject: ARM: tegra: apalis_t30: fix mcp2515 can controller interrupt polarity Fix the MCP2515 SPI CAN controller interrupt polarity which according to its datasheet defaults to low-active aka falling edge. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-apalis.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi index a31b112f631d..e44b2bce6736 100644 --- a/arch/arm/boot/dts/tegra30-apalis.dtsi +++ b/arch/arm/boot/dts/tegra30-apalis.dtsi @@ -1039,7 +1039,7 @@ reg = <1>; clocks = <&clk16m>; interrupt-parent = <&gpio>; - interrupts = ; + interrupts = ; spi-max-frequency = <10000000>; }; }; @@ -1054,7 +1054,7 @@ reg = <0>; clocks = <&clk16m>; interrupt-parent = <&gpio>; - interrupts = ; + interrupts = ; spi-max-frequency = <10000000>; }; }; -- cgit v1.2.2 From a472e00b1c571408924b69c1c6c2df2320d49247 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Fri, 31 Aug 2018 18:38:15 +0200 Subject: ARM: tegra: apalis_t30: move hda node from carrier to module Move the hda node from the carrier board to the module level device tree. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-apalis-eval.dts | 4 ---- arch/arm/boot/dts/tegra30-apalis.dtsi | 4 ++++ 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/tegra30-apalis-eval.dts b/arch/arm/boot/dts/tegra30-apalis-eval.dts index fdfadda72e0d..749fc6d1ff70 100644 --- a/arch/arm/boot/dts/tegra30-apalis-eval.dts +++ b/arch/arm/boot/dts/tegra30-apalis-eval.dts @@ -119,10 +119,6 @@ spi-max-frequency = <25000000>; }; - hda@70030000 { - status = "okay"; - }; - /* Apalis SD1 */ sdhci@78000000 { status = "okay"; diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi index e44b2bce6736..23cecd327172 100644 --- a/arch/arm/boot/dts/tegra30-apalis.dtsi +++ b/arch/arm/boot/dts/tegra30-apalis.dtsi @@ -1078,6 +1078,10 @@ }; }; + hda@70030000 { + status = "okay"; + }; + ahub@70080000 { i2s@70080500 { status = "okay"; -- cgit v1.2.2 From b57d6b996ebe25e7f1e92de0abc7a2da42005454 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Fri, 31 Aug 2018 18:38:16 +0200 Subject: ARM: tegra: apalis_t30: support v1.1 hardware revision Support the V1.1 hardware revisions with the following change: Changed power rail for MMC1 interface to a 3.3V/1.8V switchable rail in order to be able to run UHS SD cards in ultra high speed 1.8V mode. [ 207.502011] mmc2: host does not support reading read-only switch, assuming write-enable [ 207.517011] mmc2: new ultra high speed SDR104 SDHC card at address aaaa [ 207.534190] mmcblk2: mmc2:aaaa SE32G 29.7 GiB [ 207.545096] mmcblk2: p1 root@apalis-t30:~# cat /sys/kernel/debug/mmc2/ios clock: 208000000 Hz actual clock: 204000000 Hz vdd: 21 (3.3 ~ 3.4 V) bus mode: 2 (push-pull) chip select: 0 (don't care) power mode: 2 (on) bus width: 2 (4 bits) timing spec: 6 (sd uhs SDR104) signal voltage: 1 (1.80 V) driver type: 0 (driver type B) root@apalis-t30:~# hdparm -t /dev/mmcblk2 /dev/mmcblk2: Timing buffered disk reads: 256 MB in 3.02 seconds = 84.71 MB/sec Signed-off-by: Marcel Ziswiler Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/arm/tegra.txt | 2 + arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts | 266 +++++ arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi | 1189 +++++++++++++++++++++++ arch/arm/boot/dts/tegra30-apalis.dtsi | 3 +- 5 files changed, 1459 insertions(+), 2 deletions(-) create mode 100644 arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts create mode 100644 arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi diff --git a/Documentation/devicetree/bindings/arm/tegra.txt b/Documentation/devicetree/bindings/arm/tegra.txt index 32f62bb7006d..1073a5e66122 100644 --- a/Documentation/devicetree/bindings/arm/tegra.txt +++ b/Documentation/devicetree/bindings/arm/tegra.txt @@ -47,6 +47,8 @@ board-specific compatible values: nvidia,ventana toradex,apalis_t30 toradex,apalis_t30-eval + toradex,apalis_t30-v1.1 + toradex,apalis_t30-v1.1-eval toradex,apalis-tk1 toradex,apalis-tk1-eval toradex,colibri_t20-512 diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index b5bd3de87c33..9d6d7790d627 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1071,6 +1071,7 @@ dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \ tegra20-ventana.dtb dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += \ tegra30-apalis-eval.dtb \ + tegra30-apalis-v1.1-eval.dtb \ tegra30-beaver.dtb \ tegra30-cardhu-a02.dtb \ tegra30-cardhu-a04.dtb \ diff --git a/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts b/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts new file mode 100644 index 000000000000..0be50e881684 --- /dev/null +++ b/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts @@ -0,0 +1,266 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/dts-v1/; + +#include +#include "tegra30-apalis-v1.1.dtsi" + +/ { + model = "Toradex Apalis T30 on Apalis Evaluation Board"; + compatible = "toradex,apalis_t30-v1.1-eval", "toradex,apalis_t30-eval", + "toradex,apalis_t30-v1.1", "toradex,apalis_t30", + "nvidia,tegra30"; + + aliases { + rtc0 = "/i2c@7000c000/rtc@68"; + rtc1 = "/i2c@7000d000/pmic@2d"; + rtc2 = "/rtc@7000e000"; + serial0 = &uarta; + serial1 = &uartb; + serial2 = &uartc; + serial3 = &uartd; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + pcie@3000 { + pci@1,0 { + status = "okay"; + }; + + pci@2,0 { + status = "okay"; + }; + }; + + host1x@50000000 { + dc@54200000 { + rgb { + status = "okay"; + nvidia,panel = <&panel>; + }; + }; + + hdmi@54280000 { + status = "okay"; + hdmi-supply = <®_5v0>; + }; + }; + + /* Apalis UART1 */ + serial@70006000 { + status = "okay"; + }; + + /* Apalis UART2 */ + serial@70006040 { + status = "okay"; + }; + + /* Apalis UART3 */ + serial@70006200 { + status = "okay"; + }; + + /* Apalis UART4 */ + serial@70006300 { + status = "okay"; + }; + + pwm@7000a000 { + status = "okay"; + }; + + /* + * GEN1_I2C: I2C1_SDA/SCL on MXM3 pin 209/211 (e.g. RTC on carrier + * board) + */ + i2c@7000c000 { + status = "okay"; + clock-frequency = <400000>; + + pcie-switch@58 { + compatible = "plx,pex8605"; + reg = <0x58>; + }; + + /* M41T0M6 real time clock on carrier board */ + rtc@68 { + compatible = "st,m41t0"; + reg = <0x68>; + }; + }; + + /* GEN2_I2C: unused */ + + /* + * CAM_I2C: I2C3_SDA/SCL on MXM3 pin 201/203 (e.g. camera sensor on + * carrier board) + */ + i2c@7000c500 { + status = "okay"; + clock-frequency = <400000>; + }; + + /* DDC: I2C2_SDA/SCL on MXM3 pin 205/207 (e.g. display EDID) */ + i2c@7000c700 { + status = "okay"; + }; + + /* SPI1: Apalis SPI1 */ + spi@7000d400 { + status = "okay"; + spi-max-frequency = <25000000>; + }; + + /* SPI5: Apalis SPI2 */ + spi@7000dc00 { + status = "okay"; + spi-max-frequency = <25000000>; + }; + + /* Apalis SD1 */ + sdhci@78000000 { + status = "okay"; + bus-width = <4>; + /* SD1_CD# */ + cd-gpios = <&gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_LOW>; + no-1-8-v; + }; + + /* Apalis MMC1 */ + sdhci@78000400 { + status = "okay"; + bus-width = <8>; + /* MMC1_CD# */ + cd-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>; + vqmmc-supply = <®_vddio_sdmmc3>; + }; + + /* EHCI instance 0: USB1_DP/N -> USBO1_DP/N */ + usb@7d000000 { + status = "okay"; + dr_mode = "otg"; + }; + + usb-phy@7d000000 { + status = "okay"; + vbus-supply = <®_usbo1_vbus>; + }; + + /* EHCI instance 1: USB2_DP/N -> USBH2_DP/N */ + usb@7d004000 { + status = "okay"; + }; + + usb-phy@7d004000 { + status = "okay"; + vbus-supply = <®_usbh_vbus>; + }; + + /* EHCI instance 2: USB3_DP/N -> USBH3_DP/N */ + usb@7d008000 { + status = "okay"; + }; + + usb-phy@7d008000 { + status = "okay"; + vbus-supply = <®_usbh_vbus>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = <255 231 223 207 191 159 127 0>; + default-brightness-level = <6>; + /* BKL1_ON */ + enable-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; + power-supply = <®_3v3>; + pwms = <&pwm 0 5000000>; /* BKL1_PWM */ + }; + + gpio-keys { + compatible = "gpio-keys"; + + wakeup { + label = "WAKE1_MICO"; + gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + wakeup-source; + }; + }; + + panel: panel { + /* + * edt,et057090dhu: EDT 5.7" LCD TFT + * edt,et070080dh6: EDT 7.0" LCD TFT + */ + compatible = "edt,et057090dhu", "simple-panel"; + backlight = <&backlight>; + power-supply = <®_3v3>; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3.3V_SW"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_5v0: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "5V_SW"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + /* USBO1_EN */ + reg_usbo1_vbus: regulator-usbo1-vbus { + compatible = "regulator-fixed"; + regulator-name = "VCC_USBO1"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(T, 5) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_5v0>; + }; + + /* USBH_EN */ + reg_usbh_vbus: regulator-usbh-vbus { + compatible = "regulator-fixed"; + regulator-name = "VCC_USBH(2A|2C|2D|3|4)"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_5v0>; + }; + + /* + * 1.8 volt resp. 3.3 volt VDDIO_SDMMC3 depending on + * EN_+3.3_SDMMC3 GPIO + */ + reg_vddio_sdmmc3: regulator-vddio-sdmmc3 { + compatible = "regulator-gpio"; + regulator-name = "VDDIO_SDMMC3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-type = "voltage"; + gpios = <&gpio TEGRA_GPIO(J, 5) GPIO_ACTIVE_HIGH>; + states = <1800000 0x0 + 3300000 0x1>; + startup-delay-us = <100000>; + vin-supply = <&vddio_sdmmc_1v8_reg>; + }; +}; + +&gpio { + /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */ + pex-perst-n { + gpio-hog; + gpios = ; + output-high; + line-name = "PEX_PERST_N"; + }; +}; diff --git a/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi b/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi new file mode 100644 index 000000000000..02f8126481a2 --- /dev/null +++ b/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi @@ -0,0 +1,1189 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +#include "tegra30.dtsi" + +/* + * Toradex Apalis T30 Module Device Tree + * Compatible for Revisions 1GB: V1.1A, V1.1B; 1GB IT: V1.1A, V1.1B; + * 2GB: V1.1A, V1.1B + */ +/ { + memory@80000000 { + reg = <0x80000000 0x40000000>; + }; + + pcie@3000 { + status = "okay"; + avdd-pexa-supply = <&vdd2_reg>; + avdd-pexb-supply = <&vdd2_reg>; + avdd-pex-pll-supply = <&vdd2_reg>; + avdd-plle-supply = <&ldo6_reg>; + hvdd-pex-supply = <®_module_3v3>; + vddio-pex-ctl-supply = <®_module_3v3>; + vdd-pexa-supply = <&vdd2_reg>; + vdd-pexb-supply = <&vdd2_reg>; + + /* Apalis type specific */ + pci@1,0 { + nvidia,num-lanes = <4>; + }; + + /* Apalis PCIe */ + pci@2,0 { + nvidia,num-lanes = <1>; + }; + + /* I210/I211 Gigabit Ethernet Controller (on-module) */ + pci@3,0 { + status = "okay"; + nvidia,num-lanes = <1>; + + pcie@0 { + reg = <0 0 0 0 0>; + local-mac-address = [00 00 00 00 00 00]; + }; + }; + }; + + host1x@50000000 { + hdmi@54280000 { + nvidia,ddc-i2c-bus = <&hdmi_ddc>; + nvidia,hpd-gpio = + <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; + pll-supply = <®_1v8_avdd_hdmi_pll>; + vdd-supply = <®_3v3_avdd_hdmi>; + }; + }; + + pinmux@70000868 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + /* Analogue Audio (On-module) */ + clk1-out-pw4 { + nvidia,pins = "clk1_out_pw4"; + nvidia,function = "extperiph1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap3-fs-pp0 { + nvidia,pins = "dap3_fs_pp0", + "dap3_sclk_pp3", + "dap3_din_pp1", + "dap3_dout_pp2"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* Apalis BKL1_ON */ + pv2 { + nvidia,pins = "pv2"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis BKL1_PWM */ + uart3-rts-n-pc0 { + nvidia,pins = "uart3_rts_n_pc0"; + nvidia,function = "pwm0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + /* BKL1_PWM_EN#, disable TPS65911 PMIC PWM backlight */ + uart3-cts-n-pa1 { + nvidia,pins = "uart3_cts_n_pa1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis CAN1 on SPI6 */ + spi2-cs0-n-px3 { + nvidia,pins = "spi2_cs0_n_px3", + "spi2_miso_px1", + "spi2_mosi_px0", + "spi2_sck_px2"; + nvidia,function = "spi6"; + nvidia,pull = ; + nvidia,tristate = ; + }; + /* CAN_INT1 */ + spi2-cs1-n-pw2 { + nvidia,pins = "spi2_cs1_n_pw2"; + nvidia,function = "spi3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis CAN2 on SPI4 */ + gmi-a16-pj7 { + nvidia,pins = "gmi_a16_pj7", + "gmi_a17_pb0", + "gmi_a18_pb1", + "gmi_a19_pk7"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + /* CAN_INT2 */ + spi2-cs2-n-pw3 { + nvidia,pins = "spi2_cs2_n_pw3"; + nvidia,function = "spi3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis Digital Audio */ + clk1-req-pee2 { + nvidia,pins = "clk1_req_pee2"; + nvidia,function = "hda"; + nvidia,pull = ; + nvidia,tristate = ; + }; + clk2-out-pw5 { + nvidia,pins = "clk2_out_pw5"; + nvidia,function = "extperiph2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap1-fs-pn0 { + nvidia,pins = "dap1_fs_pn0", + "dap1_din_pn1", + "dap1_dout_pn2", + "dap1_sclk_pn3"; + nvidia,function = "hda"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* Apalis GPIO */ + kb-col0-pq0 { + nvidia,pins = "kb_col0_pq0", + "kb_col1_pq1", + "kb_row10_ps2", + "kb_row11_ps3", + "kb_row12_ps4", + "kb_row13_ps5", + "kb_row14_ps6", + "kb_row15_ps7"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + /* Multiplexed and therefore disabled */ + owr { + nvidia,pins = "owr"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis HDMI1 */ + hdmi-cec-pee3 { + nvidia,pins = "hdmi_cec_pee3"; + nvidia,function = "cec"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + hdmi-int-pn7 { + nvidia,pins = "hdmi_int_pn7"; + nvidia,function = "hdmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis I2C1 */ + gen1-i2c-scl-pc4 { + nvidia,pins = "gen1_i2c_scl_pc4", + "gen1_i2c_sda_pc5"; + nvidia,function = "i2c1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + /* Apalis I2C2 (DDC) */ + ddc-scl-pv4 { + nvidia,pins = "ddc_scl_pv4", + "ddc_sda_pv5"; + nvidia,function = "i2c4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis I2C3 (CAM) */ + cam-i2c-scl-pbb1 { + nvidia,pins = "cam_i2c_scl_pbb1", + "cam_i2c_sda_pbb2"; + nvidia,function = "i2c3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + /* Apalis LCD1 */ + lcd-d0-pe0 { + nvidia,pins = "lcd_d0_pe0", + "lcd_d1_pe1", + "lcd_d2_pe2", + "lcd_d3_pe3", + "lcd_d4_pe4", + "lcd_d5_pe5", + "lcd_d6_pe6", + "lcd_d7_pe7", + "lcd_d8_pf0", + "lcd_d9_pf1", + "lcd_d10_pf2", + "lcd_d11_pf3", + "lcd_d12_pf4", + "lcd_d13_pf5", + "lcd_d14_pf6", + "lcd_d15_pf7", + "lcd_d16_pm0", + "lcd_d17_pm1", + "lcd_d18_pm2", + "lcd_d19_pm3", + "lcd_d20_pm4", + "lcd_d21_pm5", + "lcd_d22_pm6", + "lcd_d23_pm7", + "lcd_de_pj1", + "lcd_hsync_pj3", + "lcd_pclk_pb3", + "lcd_vsync_pj4"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis MMC1 */ + sdmmc3-clk-pa6 { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + }; + sdmmc3-dat0-pb7 { + nvidia,pins = "sdmmc3_cmd_pa7", + "sdmmc3_dat0_pb7", + "sdmmc3_dat1_pb6", + "sdmmc3_dat2_pb5", + "sdmmc3_dat3_pb4", + "sdmmc3_dat4_pd1", + "sdmmc3_dat5_pd0", + "sdmmc3_dat6_pd3", + "sdmmc3_dat7_pd4"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + }; + /* Apalis MMC1_CD# */ + pv3 { + nvidia,pins = "pv3"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis Parallel Camera */ + cam-mclk-pcc0 { + nvidia,pins = "cam_mclk_pcc0"; + nvidia,function = "vi_alt3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + vi-vsync-pd6 { + nvidia,pins = "vi_d0_pt4", + "vi_d1_pd5", + "vi_d2_pl0", + "vi_d3_pl1", + "vi_d4_pl2", + "vi_d5_pl3", + "vi_d6_pl4", + "vi_d7_pl5", + "vi_d8_pl6", + "vi_d9_pl7", + "vi_d10_pt2", + "vi_d11_pt3", + "vi_hsync_pd7", + "vi_pclk_pt0", + "vi_vsync_pd6"; + nvidia,function = "vi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + /* Multiplexed and therefore disabled */ + kb-col2-pq2 { + nvidia,pins = "kb_col2_pq2", + "kb_col3_pq3", + "kb_col4_pq4", + "kb_row4_pr4"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb-row0-pr0 { + nvidia,pins = "kb_row0_pr0", + "kb_row1_pr1", + "kb_row2_pr2", + "kb_row3_pr3"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb-row5-pr5 { + nvidia,pins = "kb_row5_pr5", + "kb_row6_pr6", + "kb_row7_pr7"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + /* + * VI level-shifter direction + * (pull-down => default direction input) + */ + vi-mclk-pt1 { + nvidia,pins = "vi_mclk_pt1"; + nvidia,function = "vi_alt3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis PWM1 */ + pu6 { + nvidia,pins = "pu6"; + nvidia,function = "pwm3"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* Apalis PWM2 */ + pu5 { + nvidia,pins = "pu5"; + nvidia,function = "pwm2"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* Apalis PWM3 */ + pu4 { + nvidia,pins = "pu4"; + nvidia,function = "pwm1"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* Apalis PWM4 */ + pu3 { + nvidia,pins = "pu3"; + nvidia,function = "pwm0"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* Apalis RESET_MOCI# */ + gmi-rst-n-pi4 { + nvidia,pins = "gmi_rst_n_pi4"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* Apalis SATA1_ACT# */ + pex-l0-prsnt-n-pdd0 { + nvidia,pins = "pex_l0_prsnt_n_pdd0"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis SD1 */ + sdmmc1-clk-pz0 { + nvidia,pins = "sdmmc1_clk_pz0"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + }; + sdmmc1-cmd-pz1 { + nvidia,pins = "sdmmc1_cmd_pz1", + "sdmmc1_dat0_py7", + "sdmmc1_dat1_py6", + "sdmmc1_dat2_py5", + "sdmmc1_dat3_py4"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + }; + /* Apalis SD1_CD# */ + clk2-req-pcc5 { + nvidia,pins = "clk2_req_pcc5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis SPDIF1 */ + spdif-out-pk5 { + nvidia,pins = "spdif_out_pk5", + "spdif_in_pk6"; + nvidia,function = "spdif"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis SPI1 */ + spi1-sck-px5 { + nvidia,pins = "spi1_sck_px5", + "spi1_mosi_px4", + "spi1_miso_px7", + "spi1_cs0_n_px6"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* Apalis SPI2 */ + lcd-sck-pz4 { + nvidia,pins = "lcd_sck_pz4", + "lcd_sdout_pn5", + "lcd_sdin_pz2", + "lcd_cs0_n_pn4"; + nvidia,function = "spi5"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* + * Apalis TS (Low-speed type specific) + * pins may be used as GPIOs + */ + kb-col5-pq5 { + nvidia,pins = "kb_col5_pq5"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb-col6-pq6 { + nvidia,pins = "kb_col6_pq6", + "kb_col7_pq7", + "kb_row8_ps0", + "kb_row9_ps1"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis UART1 */ + ulpi-data0 { + nvidia,pins = "ulpi_data0_po1", + "ulpi_data1_po2", + "ulpi_data2_po3", + "ulpi_data3_po4", + "ulpi_data4_po5", + "ulpi_data5_po6", + "ulpi_data6_po7", + "ulpi_data7_po0"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* Apalis UART2 */ + ulpi-clk-py0 { + nvidia,pins = "ulpi_clk_py0", + "ulpi_dir_py1", + "ulpi_nxt_py2", + "ulpi_stp_py3"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* Apalis UART3 */ + uart2-rxd-pc3 { + nvidia,pins = "uart2_rxd_pc3", + "uart2_txd_pc2"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* Apalis UART4 */ + uart3-rxd-pw7 { + nvidia,pins = "uart3_rxd_pw7", + "uart3_txd_pw6"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* Apalis USBH_EN */ + pex-l0-rst-n-pdd1 { + nvidia,pins = "pex_l0_rst_n_pdd1"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis USBH_OC# */ + pex-l0-clkreq-n-pdd2 { + nvidia,pins = "pex_l0_clkreq_n_pdd2"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis USBO1_EN */ + gen2-i2c-scl-pt5 { + nvidia,pins = "gen2_i2c_scl_pt5"; + nvidia,function = "rsvd4"; + nvidia,open-drain = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* Apalis USBO1_OC# */ + gen2-i2c-sda-pt6 { + nvidia,pins = "gen2_i2c_sda_pt6"; + nvidia,function = "rsvd4"; + nvidia,open-drain = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis VGA1 not supported and therefore disabled */ + crt-hsync-pv6 { + nvidia,pins = "crt_hsync_pv6", + "crt_vsync_pv7"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis WAKE1_MICO */ + pv1 { + nvidia,pins = "pv1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* eMMC (On-module) */ + sdmmc4-clk-pcc4 { + nvidia,pins = "sdmmc4_clk_pcc4", + "sdmmc4_cmd_pt7", + "sdmmc4_rst_n_pcc3"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4-dat0-paa0 { + nvidia,pins = "sdmmc4_dat0_paa0", + "sdmmc4_dat1_paa1", + "sdmmc4_dat2_paa2", + "sdmmc4_dat3_paa3", + "sdmmc4_dat4_paa4", + "sdmmc4_dat5_paa5", + "sdmmc4_dat6_paa6", + "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* EN_+3.3_SDMMC3 */ + uart2-cts-n-pj5 { + nvidia,pins = "uart2_cts_n_pj5"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* LAN i210/i211 DEV_OFF_N, PE_RST_N (On-module) */ + pex-l2-prsnt-n-pdd7 { + nvidia,pins = "pex_l2_prsnt_n_pdd7", + "pex_l2_rst_n_pcc6"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + /* LAN i210/i211 PE_WAKE_N, SDP3 (On-module) */ + pex-wake-n-pdd3 { + nvidia,pins = "pex_wake_n_pdd3", + "pex_l2_clkreq_n_pcc7"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + /* LAN i210/i211 SMB_ALERT_N (On-module) */ + sys-clk-req-pz5 { + nvidia,pins = "sys_clk_req_pz5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* LVDS Transceiver Configuration */ + pbb0 { + nvidia,pins = "pbb0", + "pbb7", + "pcc1", + "pcc2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb3 { + nvidia,pins = "pbb3", + "pbb4", + "pbb5", + "pbb6"; + nvidia,function = "displayb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Not connected and therefore disabled */ + clk-32k-out-pa0 { + nvidia,pins = "clk3_out_pee0", + "clk3_req_pee1", + "clk_32k_out_pa0", + "dap4_din_pp5", + "dap4_dout_pp6", + "dap4_fs_pp4", + "dap4_sclk_pp7"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap2-fs-pa2 { + nvidia,pins = "dap2_fs_pa2", + "dap2_sclk_pa3", + "dap2_din_pa4", + "dap2_dout_pa5", + "lcd_dc0_pn6", + "lcd_m1_pw1", + "lcd_pwr1_pc1", + "pex_l1_clkreq_n_pdd6", + "pex_l1_prsnt_n_pdd4", + "pex_l1_rst_n_pdd5"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-ad0-pg0 { + nvidia,pins = "gmi_ad0_pg0", + "gmi_ad2_pg2", + "gmi_ad3_pg3", + "gmi_ad4_pg4", + "gmi_ad5_pg5", + "gmi_ad6_pg6", + "gmi_ad7_pg7", + "gmi_ad8_ph0", + "gmi_ad9_ph1", + "gmi_ad10_ph2", + "gmi_ad11_ph3", + "gmi_ad12_ph4", + "gmi_ad13_ph5", + "gmi_ad14_ph6", + "gmi_ad15_ph7", + "gmi_adv_n_pk0", + "gmi_clk_pk1", + "gmi_cs4_n_pk2", + "gmi_cs2_n_pk3", + "gmi_dqs_pi2", + "gmi_iordy_pi5", + "gmi_oe_n_pi1", + "gmi_wait_pi7", + "gmi_wr_n_pi0", + "lcd_cs1_n_pw0", + "pu0", + "pu1", + "pu2"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-cs0-n-pj0 { + nvidia,pins = "gmi_cs0_n_pj0", + "gmi_cs1_n_pj2", + "gmi_cs3_n_pk4"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-cs6-n-pi3 { + nvidia,pins = "gmi_cs6_n_pi3"; + nvidia,function = "sata"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-cs7-n-pi6 { + nvidia,pins = "gmi_cs7_n_pi6"; + nvidia,function = "gmi_alt"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd-pwr0-pb2 { + nvidia,pins = "lcd_pwr0_pb2", + "lcd_pwr2_pc6", + "lcd_wr_n_pz3"; + nvidia,function = "hdcp"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart2-rts-n-pj6 { + nvidia,pins = "uart2_rts_n_pj6"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Power I2C (On-module) */ + pwr-i2c-scl-pz6 { + nvidia,pins = "pwr_i2c_scl_pz6", + "pwr_i2c_sda_pz7"; + nvidia,function = "i2cpwr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + /* + * THERMD_ALERT#, unlatched I2C address pin of LM95245 + * temperature sensor therefore requires disabling for + * now + */ + lcd-dc1-pd2 { + nvidia,pins = "lcd_dc1_pd2"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* TOUCH_PEN_INT# (On-module) */ + pv0 { + nvidia,pins = "pv0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + }; + + serial@70006040 { + compatible = "nvidia,tegra30-hsuart"; + }; + + serial@70006200 { + compatible = "nvidia,tegra30-hsuart"; + }; + + serial@70006300 { + compatible = "nvidia,tegra30-hsuart"; + }; + + hdmi_ddc: i2c@7000c700 { + clock-frequency = <10000>; + }; + + /* + * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and + * touch screen controller + */ + i2c@7000d000 { + status = "okay"; + clock-frequency = <100000>; + + /* SGTL5000 audio codec */ + sgtl5000: codec@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + VDDA-supply = <®_module_3v3_audio>; + VDDD-supply = <®_1v8_vio>; + VDDIO-supply = <®_module_3v3>; + clocks = <&tegra_car TEGRA30_CLK_EXTERN1>; + }; + + pmic: pmic@2d { + compatible = "ti,tps65911"; + reg = <0x2d>; + + interrupts = ; + #interrupt-cells = <2>; + interrupt-controller; + + ti,system-power-controller; + + #gpio-cells = <2>; + gpio-controller; + + vcc1-supply = <®_module_3v3>; + vcc2-supply = <®_module_3v3>; + vcc3-supply = <®_1v8_vio>; + vcc4-supply = <®_module_3v3>; + vcc5-supply = <®_module_3v3>; + vcc6-supply = <®_1v8_vio>; + vcc7-supply = <®_5v0_charge_pump>; + vccio-supply = <®_module_3v3>; + + regulators { + vdd1_reg: vdd1 { + regulator-name = "+V1.35_VDDIO_DDR"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + }; + + vdd2_reg: vdd2 { + regulator-name = "+V1.05"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + vddctrl_reg: vddctrl { + regulator-name = "+V1.0_VDD_CPU"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + regulator-always-on; + }; + + reg_1v8_vio: vio { + regulator-name = "+V1.8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + /* + * 1.8 volt +VDDIO_SDMMC3 in case EN_+3.3_SDMMC3 + * is off + */ + vddio_sdmmc_1v8_reg: ldo1 { + regulator-name = "+VDDIO_SDMMC3_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + /* + * EN_+V3.3 switching via FET: + * +V3.3_AUDIO_AVDD_S, +V3.3 + * see also +V3.3 fixed supply + */ + ldo2_reg: ldo2 { + regulator-name = "EN_+V3.3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo3_reg: ldo3 { + regulator-name = "+V1.2_CSI"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo4_reg: ldo4 { + regulator-name = "+V1.2_VDD_RTC"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + /* + * +V2.8_AVDD_VDAC: + * only required for (unsupported) analog RGB + */ + ldo5_reg: ldo5 { + regulator-name = "+V2.8_AVDD_VDAC"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + /* + * +V1.05_AVDD_PLLE: avdd_plle should be 1.05V + * but LDO6 can't set voltage in 50mV + * granularity + */ + ldo6_reg: ldo6 { + regulator-name = "+V1.05_AVDD_PLLE"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + }; + + ldo7_reg: ldo7 { + regulator-name = "+V1.2_AVDD_PLL"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + ldo8_reg: ldo8 { + regulator-name = "+V1.0_VDD_DDR_HS"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + }; + }; + + /* STMPE811 touch screen controller */ + touchscreen@41 { + compatible = "st,stmpe811"; + reg = <0x41>; + irq-gpio = <&gpio TEGRA_GPIO(V, 0) IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + id = <0>; + blocks = <0x5>; + irq-trigger = <0x1>; + + stmpe_touchscreen { + compatible = "st,stmpe-ts"; + /* 3.25 MHz ADC clock speed */ + st,adc-freq = <1>; + /* 8 sample average control */ + st,ave-ctrl = <3>; + /* 7 length fractional part in z */ + st,fraction-z = <7>; + /* + * 50 mA typical 80 mA max touchscreen drivers + * current limit value + */ + st,i-drive = <1>; + /* 12-bit ADC */ + st,mod-12b = <1>; + /* internal ADC reference */ + st,ref-sel = <0>; + /* ADC converstion time: 80 clocks */ + st,sample-time = <4>; + /* 1 ms panel driver settling time */ + st,settling = <3>; + /* 5 ms touch detect interrupt delay */ + st,touch-det-delay = <5>; + }; + }; + + /* + * LM95245 temperature sensor + * Note: OVERT1# directly connected to TPS65911 PMIC PWRDN + */ + temp-sensor@4c { + compatible = "national,lm95245"; + reg = <0x4c>; + }; + + /* SW: +V1.2_VDD_CORE */ + regulator@60 { + compatible = "ti,tps62362"; + reg = <0x60>; + + regulator-name = "tps62362-vout"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1400000>; + regulator-boot-on; + regulator-always-on; + ti,vsel0-state-low; + /* VSEL1: EN_CORE_DVFS_N low for DVFS */ + ti,vsel1-state-low; + }; + }; + + /* SPI4: CAN2 */ + spi@7000da00 { + status = "okay"; + spi-max-frequency = <10000000>; + + can@1 { + compatible = "microchip,mcp2515"; + reg = <1>; + clocks = <&clk16m>; + interrupt-parent = <&gpio>; + interrupts = ; + spi-max-frequency = <10000000>; + }; + }; + + /* SPI6: CAN1 */ + spi@7000de00 { + status = "okay"; + spi-max-frequency = <10000000>; + + can@0 { + compatible = "microchip,mcp2515"; + reg = <0>; + clocks = <&clk16m>; + interrupt-parent = <&gpio>; + interrupts = ; + spi-max-frequency = <10000000>; + }; + }; + + pmc@7000e400 { + nvidia,invert-interrupt; + nvidia,suspend-mode = <1>; + nvidia,cpu-pwr-good-time = <5000>; + nvidia,cpu-pwr-off-time = <5000>; + nvidia,core-pwr-good-time = <3845 3845>; + nvidia,core-pwr-off-time = <0>; + nvidia,core-power-req-active-high; + nvidia,sys-clock-req-active-high; + + /* Set DEV_OFF bit in DCDC control register of TPS65911 PMIC */ + i2c-thermtrip { + nvidia,i2c-controller-id = <4>; + nvidia,bus-addr = <0x2d>; + nvidia,reg-addr = <0x3f>; + nvidia,reg-data = <0x1>; + }; + }; + + hda@70030000 { + status = "okay"; + }; + + ahub@70080000 { + i2s@70080500 { + status = "okay"; + }; + }; + + /* eMMC */ + sdhci@78000600 { + status = "okay"; + bus-width = <8>; + non-removable; + vmmc-supply = <®_module_3v3>; /* VCC */ + vqmmc-supply = <®_1v8_vio>; /* VCCQ */ + mmc-ddr-1_8v; + }; + + clk32k_in: xtal1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + + clk16m: osc4 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <16000000>; + }; + + reg_1v8_avdd_hdmi_pll: regulator-1v8-avdd-hdmi-pll { + compatible = "regulator-fixed"; + regulator-name = "+V1.8_AVDD_HDMI_PLL"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + enable-active-high; + gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; + vin-supply = <®_1v8_vio>; + }; + + reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi { + compatible = "regulator-fixed"; + regulator-name = "+V3.3_AVDD_HDMI"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; + vin-supply = <®_module_3v3>; + }; + + reg_5v0_charge_pump: regulator-5v0-charge-pump { + compatible = "regulator-fixed"; + regulator-name = "+V5.0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_module_3v3: regulator-module-3v3 { + compatible = "regulator-fixed"; + regulator-name = "+V3.3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_module_3v3_audio: regulator-module-3v3-audio { + compatible = "regulator-fixed"; + regulator-name = "+V3.3_AUDIO_AVDD_S"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + sound { + compatible = "toradex,tegra-audio-sgtl5000-apalis_t30", + "nvidia,tegra-audio-sgtl5000"; + nvidia,model = "Toradex Apalis T30"; + nvidia,audio-routing = + "Headphone Jack", "HP_OUT", + "LINE_IN", "Line In Jack", + "MIC_IN", "Mic Jack"; + nvidia,i2s-controller = <&tegra_i2s2>; + nvidia,audio-codec = <&sgtl5000>; + clocks = <&tegra_car TEGRA30_CLK_PLL_A>, + <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA30_CLK_EXTERN1>; + clock-names = "pll_a", "pll_a_out0", "mclk"; + }; +}; diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi index 23cecd327172..7f112f192fe9 100644 --- a/arch/arm/boot/dts/tegra30-apalis.dtsi +++ b/arch/arm/boot/dts/tegra30-apalis.dtsi @@ -3,8 +3,7 @@ /* * Toradex Apalis T30 Module Device Tree - * Compatible for Revisions 1GB: V1.0A, V1.1A; 1GB IT: V1.1A; - * 2GB: V1.0B, V1.0C, V1.0E, V1.1A + * Compatible for Revisions 1GB: V1.0A; 2GB: V1.0B, V1.0C, V1.0E */ / { memory@80000000 { -- cgit v1.2.2 From a5db2dadb15f67679221c6c7748d62a0eea19214 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sat, 1 Sep 2018 10:12:15 +0200 Subject: ARM: tegra: colibri_t30: add local-mac-address property Add empty local-mac-address property to be filled in by boot loader (e.g. U-Boot). Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-colibri.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi b/arch/arm/boot/dts/tegra30-colibri.dtsi index 526ed71cf7a3..a392b65a0b64 100644 --- a/arch/arm/boot/dts/tegra30-colibri.dtsi +++ b/arch/arm/boot/dts/tegra30-colibri.dtsi @@ -437,6 +437,13 @@ /* EHCI instance 1: USB2_DP/N -> AX88772B */ usb@7d004000 { status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + asix@1 { + reg = <1>; + local-mac-address = [00 00 00 00 00 00]; + }; }; usb-phy@7d004000 { -- cgit v1.2.2 From 033519b0c5f4c9ec39dcdc2afa6b216ff8233567 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sat, 1 Sep 2018 10:12:16 +0200 Subject: ARM: tegra: colibri_t30: reorder host1x/hdmi properties Reorder Host1x/HDMI properties. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-colibri.dtsi | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi b/arch/arm/boot/dts/tegra30-colibri.dtsi index a392b65a0b64..48c41a36b4dc 100644 --- a/arch/arm/boot/dts/tegra30-colibri.dtsi +++ b/arch/arm/boot/dts/tegra30-colibri.dtsi @@ -16,12 +16,11 @@ host1x@50000000 { hdmi@54280000 { - vdd-supply = <&avdd_hdmi_3v3_reg>; - pll-supply = <&avdd_hdmi_pll_1v8_reg>; - + nvidia,ddc-i2c-bus = <&hdmiddc>; nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; - nvidia,ddc-i2c-bus = <&hdmiddc>; + pll-supply = <&avdd_hdmi_pll_1v8_reg>; + vdd-supply = <&avdd_hdmi_3v3_reg>; }; }; -- cgit v1.2.2 From 584a9e55b539fe1a66513dd56d4093c698de6d98 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sat, 1 Sep 2018 10:12:17 +0200 Subject: ARM: tegra: colibri_t30: regulator clean-up Just cosmetic regulator clean-up. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-colibri-eval-v3.dts | 52 +++++------ arch/arm/boot/dts/tegra30-colibri.dtsi | 126 +++++++++++--------------- 2 files changed, 78 insertions(+), 100 deletions(-) diff --git a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts index 16e1f387aa6d..5eb665d89435 100644 --- a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts +++ b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts @@ -105,7 +105,7 @@ usb-phy@7d000000 { status = "okay"; dr_mode = "otg"; - vbus-supply = <&usbc_vbus_reg>; + vbus-supply = <®_usbc_vbus>; }; /* EHCI instance 2: USB3_DP/N -> USBH_P/N */ @@ -115,7 +115,7 @@ usb-phy@7d008000 { status = "okay"; - vbus-supply = <&usbh_vbus_reg>; + vbus-supply = <®_usbh_vbus>; }; backlight: backlight { @@ -181,34 +181,28 @@ }; }; - regulators { - sys_5v0_reg: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; + reg_5v0: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "5V_SW"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; - usbc_vbus_reg: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "usbc_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&sys_5v0_reg>; - }; + reg_usbc_vbus: regulator-usbc-vbus { + compatible = "regulator-fixed"; + regulator-name = "VCC_USB5"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <®_5v0>; + }; - /* USBH_PEN */ - usbh_vbus_reg: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "usbh_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; - vin-supply = <&sys_5v0_reg>; - }; + /* USBH_PEN resp. USB_P_EN */ + reg_usbh_vbus: regulator-usbh-vbus { + compatible = "regulator-fixed"; + regulator-name = "VCC_USB[1-4]"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; + vin-supply = <®_5v0>; }; }; diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi b/arch/arm/boot/dts/tegra30-colibri.dtsi index 48c41a36b4dc..4d7ed25bd594 100644 --- a/arch/arm/boot/dts/tegra30-colibri.dtsi +++ b/arch/arm/boot/dts/tegra30-colibri.dtsi @@ -19,8 +19,8 @@ nvidia,ddc-i2c-bus = <&hdmiddc>; nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; - pll-supply = <&avdd_hdmi_pll_1v8_reg>; - vdd-supply = <&avdd_hdmi_3v3_reg>; + pll-supply = <®_1v8_avdd_hdmi_pll>; + vdd-supply = <®_3v3_avdd_hdmi>; }; }; @@ -229,8 +229,8 @@ sgtl5000: codec@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; - VDDA-supply = <&sys_3v3_reg>; - VDDIO-supply = <&sys_3v3_reg>; + VDDA-supply = <®_module_3v3>; + VDDIO-supply = <®_module_3v3>; clocks = <&tegra_car TEGRA30_CLK_EXTERN1>; }; @@ -247,19 +247,18 @@ #gpio-cells = <2>; gpio-controller; - vcc1-supply = <&sys_3v3_reg>; - vcc2-supply = <&sys_3v3_reg>; - vcc3-supply = <&vio_reg>; - vcc4-supply = <&sys_3v3_reg>; - vcc5-supply = <&sys_3v3_reg>; - vcc6-supply = <&vio_reg>; - vcc7-supply = <&charge_pump_5v0_reg>; - vccio-supply = <&sys_3v3_reg>; + vcc1-supply = <®_module_3v3>; + vcc2-supply = <®_module_3v3>; + vcc3-supply = <®_1v8_vio>; + vcc4-supply = <®_module_3v3>; + vcc5-supply = <®_module_3v3>; + vcc6-supply = <®_1v8_vio>; + vcc7-supply = <®_5v0_charge_pump>; + vccio-supply = <®_module_3v3>; regulators { - /* SW1: +V1.35_VDDIO_DDR */ vdd1_reg: vdd1 { - regulator-name = "vddio_ddr_1v35"; + regulator-name = "+V1.35_VDDIO_DDR"; regulator-min-microvolt = <1350000>; regulator-max-microvolt = <1350000>; regulator-always-on; @@ -267,17 +266,15 @@ /* SW2: unused */ - /* SW CTRL: +V1.0_VDD_CPU */ vddctrl_reg: vddctrl { - regulator-name = "vdd_cpu,vdd_sys"; + regulator-name = "+V1.0_VDD_CPU"; regulator-min-microvolt = <1150000>; regulator-max-microvolt = <1150000>; regulator-always-on; }; - /* SWIO: +V1.8 */ - vio_reg: vio { - regulator-name = "vdd_1v8_gen"; + reg_1v8_vio: vio { + regulator-name = "+V1.8"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; @@ -288,10 +285,10 @@ /* * EN_+V3.3 switching via FET: * +V3.3_AUDIO_AVDD_S, +V3.3 and +V1.8_VDD_LAN - * see also 3v3 fixed supply + * see also +V3.3 fixed supply */ ldo2_reg: ldo2 { - regulator-name = "en_3v3"; + regulator-name = "EN_+V3.3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; @@ -299,9 +296,8 @@ /* LDO3: unused */ - /* +V1.2_VDD_RTC */ ldo4_reg: ldo4 { - regulator-name = "vdd_rtc"; + regulator-name = "+V1.2_VDD_RTC"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; regulator-always-on; @@ -309,10 +305,10 @@ /* * +V2.8_AVDD_VDAC: - * only required for analog RGB + * only required for (unsupported) analog RGB */ ldo5_reg: ldo5 { - regulator-name = "avdd_vdac"; + regulator-name = "+V2.8_AVDD_VDAC"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; regulator-always-on; @@ -324,22 +320,20 @@ * granularity */ ldo6_reg: ldo6 { - regulator-name = "avdd_plle"; + regulator-name = "+V1.05_AVDD_PLLE"; regulator-min-microvolt = <1100000>; regulator-max-microvolt = <1100000>; }; - /* +V1.2_AVDD_PLL */ ldo7_reg: ldo7 { - regulator-name = "avdd_pll"; + regulator-name = "+V1.2_AVDD_PLL"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; regulator-always-on; }; - /* +V1.0_VDD_DDR_HS */ ldo8_reg: ldo8 { - regulator-name = "vdd_ddr_hs"; + regulator-name = "+V1.0_VDD_DDR_HS"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; regulator-always-on; @@ -463,50 +457,40 @@ }; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - avdd_hdmi_pll_1v8_reg: regulator@100 { - compatible = "regulator-fixed"; - reg = <100>; - regulator-name = "+V1.8_AVDD_HDMI_PLL"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - enable-active-high; - gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; - vin-supply = <&vio_reg>; - }; + reg_1v8_avdd_hdmi_pll: regulator-1v8-avdd-hdmi-pll { + compatible = "regulator-fixed"; + regulator-name = "+V1.8_AVDD_HDMI_PLL"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + enable-active-high; + gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; + vin-supply = <®_1v8_vio>; + }; - sys_3v3_reg: regulator@101 { - compatible = "regulator-fixed"; - reg = <101>; - regulator-name = "3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; + reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi { + compatible = "regulator-fixed"; + regulator-name = "+V3.3_AVDD_HDMI"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; + vin-supply = <®_module_3v3>; + }; - avdd_hdmi_3v3_reg: regulator@102 { - compatible = "regulator-fixed"; - reg = <102>; - regulator-name = "+V3.3_AVDD_HDMI"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; - vin-supply = <&sys_3v3_reg>; - }; + reg_5v0_charge_pump: regulator-5v0-charge-pump { + compatible = "regulator-fixed"; + regulator-name = "+V5.0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; - charge_pump_5v0_reg: regulator@103 { - compatible = "regulator-fixed"; - reg = <103>; - regulator-name = "5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; + reg_module_3v3: regulator-module-3v3 { + compatible = "regulator-fixed"; + regulator-name = "+V3.3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; }; sound { -- cgit v1.2.2 From a03fb6312280b19234e728689ab6a2f66a7a2cf1 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sat, 1 Sep 2018 10:12:18 +0200 Subject: ARM: tegra: colibri_t30: add missing regulators Add missing regulators: - reg_module_3v3_audio being VDDA supply of SGTL5000 - VDDD supply of SGTL5000 actually being reg_1v8_vio - reg_lan_v_bus being USB Ethernet chip vbus supply - carrier board HDMI supply being reg_5v0 - carrier board reg_3v3 actually being backlight and panel power supply Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-colibri-eval-v3.dts | 10 ++++++++++ arch/arm/boot/dts/tegra30-colibri.dtsi | 21 ++++++++++++++++++++- 2 files changed, 30 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts index 5eb665d89435..1c057b285153 100644 --- a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts +++ b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts @@ -29,6 +29,7 @@ }; hdmi@54280000 { status = "okay"; + hdmi-supply = <®_5v0>; }; }; @@ -127,6 +128,7 @@ default-brightness-level = <6>; /* BL_ON */ enable-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; + power-supply = <®_3v3>; }; clocks { @@ -159,6 +161,7 @@ compatible = "edt,et057090dhu", "simple-panel"; backlight = <&backlight>; + power-supply = <®_3v3>; }; pwmleds { @@ -181,6 +184,13 @@ }; }; + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3.3V_SW"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + reg_5v0: regulator-5v0 { compatible = "regulator-fixed"; regulator-name = "5V_SW"; diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi b/arch/arm/boot/dts/tegra30-colibri.dtsi index 4d7ed25bd594..dc54eb734f64 100644 --- a/arch/arm/boot/dts/tegra30-colibri.dtsi +++ b/arch/arm/boot/dts/tegra30-colibri.dtsi @@ -229,7 +229,8 @@ sgtl5000: codec@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; - VDDA-supply = <®_module_3v3>; + VDDA-supply = <®_module_3v3_audio>; + VDDD-supply = <®_1v8_vio>; VDDIO-supply = <®_module_3v3>; clocks = <&tegra_car TEGRA30_CLK_EXTERN1>; }; @@ -442,6 +443,7 @@ usb-phy@7d004000 { status = "okay"; nvidia,is-wired = <1>; + vbus-supply = <®_lan_v_bus>; }; clocks { @@ -485,6 +487,15 @@ regulator-always-on; }; + reg_lan_v_bus: regulator-lan-v-bus { + compatible = "regulator-fixed"; + regulator-name = "LAN_V_BUS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(DD, 2) GPIO_ACTIVE_HIGH>; + }; + reg_module_3v3: regulator-module-3v3 { compatible = "regulator-fixed"; regulator-name = "+V3.3"; @@ -493,6 +504,14 @@ regulator-always-on; }; + reg_module_3v3_audio: regulator-module-3v3-audio { + compatible = "regulator-fixed"; + regulator-name = "+V3.3_AUDIO_AVDD_S"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + sound { compatible = "toradex,tegra-audio-sgtl5000-colibri_t30", "nvidia,tegra-audio-sgtl5000"; -- cgit v1.2.2 From 4dc3bf2a5f1b49061ed5b97de0f44edd76c74e22 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sat, 1 Sep 2018 10:12:19 +0200 Subject: ARM: tegra: colibri_t30: annotate uarts and move compatible to board Annotate UARTs and move the serial UART "nvidia,tegra30-hsuart" compatible definitions from the carrier board to the module level device trees. One could still override this in a custom carrier board device tree if required. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-colibri-eval-v3.dts | 5 +++-- arch/arm/boot/dts/tegra30-colibri.dtsi | 8 ++++++++ 2 files changed, 11 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts index 1c057b285153..682ea4ffce83 100644 --- a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts +++ b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts @@ -33,17 +33,18 @@ }; }; + /* Colibri UART-A */ serial@70006000 { status = "okay"; }; + /* Colibri UART-C */ serial@70006040 { - compatible = "nvidia,tegra30-hsuart"; status = "okay"; }; + /* Colibri UART-B */ serial@70006300 { - compatible = "nvidia,tegra30-hsuart"; status = "okay"; }; diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi b/arch/arm/boot/dts/tegra30-colibri.dtsi index dc54eb734f64..a9b9db0a87f8 100644 --- a/arch/arm/boot/dts/tegra30-colibri.dtsi +++ b/arch/arm/boot/dts/tegra30-colibri.dtsi @@ -213,6 +213,14 @@ }; }; + serial@70006040 { + compatible = "nvidia,tegra30-hsuart"; + }; + + serial@70006300 { + compatible = "nvidia,tegra30-hsuart"; + }; + hdmiddc: i2c@7000c700 { clock-frequency = <10000>; }; -- cgit v1.2.2 From 2128fda985e2b4e3a48393c24cea8ae663b62c3c Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sat, 1 Sep 2018 10:12:20 +0200 Subject: ARM: tegra: colibri_t30: white-space clean-up White-space clean-up. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-colibri-eval-v3.dts | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts index 682ea4ffce83..ff321964d225 100644 --- a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts +++ b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts @@ -27,6 +27,7 @@ nvidia,panel = <&panel>; }; }; + hdmi@54280000 { status = "okay"; hdmi-supply = <®_5v0>; @@ -76,6 +77,7 @@ spi@7000d400 { status = "okay"; spi-max-frequency = <25000000>; + can0: can@0 { compatible = "microchip,mcp2515"; reg = <0>; @@ -84,6 +86,7 @@ interrupts = ; spi-max-frequency = <10000000>; }; + spidev0: spi@1 { compatible = "spidev"; reg = <1>; @@ -122,7 +125,6 @@ backlight: backlight { compatible = "pwm-backlight"; - /* PWM */ pwms = <&pwm 0 5000000>; brightness-levels = <255 128 64 32 16 8 4 0>; @@ -160,7 +162,6 @@ * edt,et070080dh6: EDT 7.0" LCD TFT */ compatible = "edt,et057090dhu", "simple-panel"; - backlight = <&backlight>; power-supply = <®_3v3>; }; -- cgit v1.2.2 From 2a3db328b358a8aed5b2c45005b7ef95be402565 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sat, 1 Sep 2018 10:12:21 +0200 Subject: ARM: tegra: colibri_t30: move dr_mode property from phy to controller Move dr_mode property from USB PHY node to controller. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-colibri-eval-v3.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts index ff321964d225..709ff95a1614 100644 --- a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts +++ b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts @@ -105,11 +105,11 @@ /* EHCI instance 0: USB1_DP/N -> USBC_P/N */ usb@7d000000 { status = "okay"; + dr_mode = "otg"; }; usb-phy@7d000000 { status = "okay"; - dr_mode = "otg"; vbus-supply = <®_usbc_vbus>; }; -- cgit v1.2.2 From 7ddc024ffa382c7090640c5209d4a4ffc73c4d0b Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sat, 1 Sep 2018 10:12:22 +0200 Subject: ARM: tegra: colibri_t30: reorder backlight properties Reorder backlight properties. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-colibri-eval-v3.dts | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts index 709ff95a1614..8c492daac165 100644 --- a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts +++ b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts @@ -125,13 +125,12 @@ backlight: backlight { compatible = "pwm-backlight"; - /* PWM */ - pwms = <&pwm 0 5000000>; brightness-levels = <255 128 64 32 16 8 4 0>; default-brightness-level = <6>; /* BL_ON */ enable-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; power-supply = <®_3v3>; + pwms = <&pwm 0 5000000>; /* PWM */ }; clocks { -- cgit v1.2.2 From 0e4c51ebace1a6dd31ff2ca147f0875e1173e078 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sat, 1 Sep 2018 10:12:23 +0200 Subject: ARM: tegra: colibri_t30: drop pwmleds Drop pwmleds in favour of using regular PWMs. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-colibri-eval-v3.dts | 20 -------------------- 1 file changed, 20 deletions(-) diff --git a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts index 8c492daac165..2aaf87ba0c42 100644 --- a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts +++ b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts @@ -165,26 +165,6 @@ power-supply = <®_3v3>; }; - pwmleds { - compatible = "pwm-leds"; - - pwmb { - label = "PWM"; - pwms = <&pwm 1 19600>; - max-brightness = <255>; - }; - pwmc { - label = "PWM"; - pwms = <&pwm 2 19600>; - max-brightness = <255>; - }; - pwmd { - label = "PWM"; - pwms = <&pwm 3 19600>; - max-brightness = <255>; - }; - }; - reg_3v3: regulator-3v3 { compatible = "regulator-fixed"; regulator-name = "3.3V_SW"; -- cgit v1.2.2 From 28e82cf4af51fda9f9e6eb825be353c6f1f411f9 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sat, 1 Sep 2018 10:12:24 +0200 Subject: ARM: tegra: colibri_t30: pinmux clean-up Clean-up pinmuxing: - white-space clean-up - explicitly disable LCD_M1 in favour of LCD_DE on L_BIAS - explicitly disable multiplexed SSPFRM and SSPTXD - get rid of nvidia,lock property - add missing eMMC sdmmc4_cmd_pt7 and explicitly enable input - explicitly disable lcd_dc1_pd2 (e.g. LM95245 I2C address pin) - annotate TOUCH_PEN_INT# being on-module - As underscores in node names are not recommended replace them all where possible with dashes. - Replace underscores in UART annotations (e.g. UART_A) with dashes (e.g. UART-A) to be more in-line with our Colibri standard. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-colibri.dtsi | 72 ++++++++++++++++++---------------- 1 file changed, 38 insertions(+), 34 deletions(-) diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi b/arch/arm/boot/dts/tegra30-colibri.dtsi index a9b9db0a87f8..6bedb69be553 100644 --- a/arch/arm/boot/dts/tegra30-colibri.dtsi +++ b/arch/arm/boot/dts/tegra30-colibri.dtsi @@ -30,18 +30,18 @@ state_default: pinmux { /* Analogue Audio (On-module) */ - clk1_out_pw4 { + clk1-out-pw4 { nvidia,pins = "clk1_out_pw4"; nvidia,function = "extperiph1"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - dap3_fs_pp0 { - nvidia,pins = "dap3_fs_pp0", - "dap3_sclk_pp3", - "dap3_din_pp1", - "dap3_dout_pp2"; + dap3-fs-pp0 { + nvidia,pins = "dap3_fs_pp0", + "dap3_sclk_pp3", + "dap3_din_pp1", + "dap3_dout_pp2"; nvidia,function = "i2s2"; nvidia,pull = ; nvidia,tristate = ; @@ -56,7 +56,7 @@ }; /* Colibri Backlight PWM */ - sdmmc3_dat3_pb4 { + sdmmc3-dat3-pb4 { nvidia,pins = "sdmmc3_dat3_pb4"; nvidia,function = "pwm0"; nvidia,pull = ; @@ -64,7 +64,7 @@ }; /* Colibri CAN_INT */ - kb_row8_ps0 { + kb-row8-ps0 { nvidia,pins = "kb_row8_ps0"; nvidia,function = "kbc"; nvidia,pull = ; @@ -74,24 +74,24 @@ /* * Colibri L_BIAS, LCD_M1 is muxed with LCD_DE - * todays display need DE, disable LCD_M1 + * today's display need DE, disable LCD_M1 */ - lcd_m1_pw1 { + lcd-m1-pw1 { nvidia,pins = "lcd_m1_pw1"; nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; /* Colibri MMC */ - kb_row10_ps2 { + kb-row10-ps2 { nvidia,pins = "kb_row10_ps2"; nvidia,function = "sdmmc2"; nvidia,pull = ; nvidia,tristate = ; }; - kb_row11_ps3 { + kb-row11-ps3 { nvidia,pins = "kb_row11_ps3", "kb_row12_ps4", "kb_row13_ps5", @@ -103,7 +103,7 @@ }; /* Colibri SSP */ - ulpi_clk_py0 { + ulpi-clk-py0 { nvidia,pins = "ulpi_clk_py0", "ulpi_dir_py1", "ulpi_nxt_py2", @@ -112,16 +112,18 @@ nvidia,pull = ; nvidia,tristate = ; }; - sdmmc3_dat6_pd3 { + /* Multiplexed SSPFRM, SSPTXD and therefore disabled */ + sdmmc3-dat6-pd3 { nvidia,pins = "sdmmc3_dat6_pd3", "sdmmc3_dat7_pd4"; nvidia,function = "spdif"; - nvidia,pull = ; + nvidia,pull = ; nvidia,tristate = ; + nvidia,enable-input = ; }; - /* Colibri UART_A */ - ulpi_data0 { + /* Colibri UART-A */ + ulpi-data0 { nvidia,pins = "ulpi_data0_po1", "ulpi_data1_po2", "ulpi_data2_po3", @@ -135,8 +137,8 @@ nvidia,tristate = ; }; - /* Colibri UART_B */ - gmi_a16_pj7 { + /* Colibri UART-B */ + gmi-a16-pj7 { nvidia,pins = "gmi_a16_pj7", "gmi_a17_pb0", "gmi_a18_pb1", @@ -146,8 +148,8 @@ nvidia,tristate = ; }; - /* Colibri UART_C */ - uart2_rxd { + /* Colibri UART-C */ + uart2-rxd { nvidia,pins = "uart2_rxd_pc3", "uart2_txd_pc2"; nvidia,function = "uartb"; @@ -155,15 +157,17 @@ nvidia,tristate = ; }; - /* eMMC */ - sdmmc4_clk_pcc4 { + /* eMMC (On-module) */ + sdmmc4-clk-pcc4 { nvidia,pins = "sdmmc4_clk_pcc4", + "sdmmc4_cmd_pt7", "sdmmc4_rst_n_pcc3"; nvidia,function = "sdmmc4"; nvidia,pull = ; nvidia,tristate = ; + nvidia,enable-input = ; }; - sdmmc4_dat0_paa0 { + sdmmc4-dat0-paa0 { nvidia,pins = "sdmmc4_dat0_paa0", "sdmmc4_dat1_paa1", "sdmmc4_dat2_paa2", @@ -175,17 +179,17 @@ nvidia,function = "sdmmc4"; nvidia,pull = ; nvidia,tristate = ; + nvidia,enable-input = ; }; /* Power I2C (On-module) */ - pwr_i2c_scl_pz6 { + pwr-i2c-scl-pz6 { nvidia,pins = "pwr_i2c_scl_pz6", "pwr_i2c_sda_pz7"; nvidia,function = "i2cpwr"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; - nvidia,lock = ; nvidia,open-drain = ; }; @@ -194,15 +198,15 @@ * temperature sensor therefore requires disabling for * now */ - lcd_dc1_pd2 { + lcd-dc1-pd2 { nvidia,pins = "lcd_dc1_pd2"; nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; - /* TOUCH_PEN_INT# */ + /* TOUCH_PEN_INT# (On-module) */ pv0 { nvidia,pins = "pv0"; nvidia,function = "rsvd1"; -- cgit v1.2.2 From dbd43f25205e7302e3253621d7f104997b2381cb Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sat, 1 Sep 2018 10:12:25 +0200 Subject: ARM: tegra: colibri_t30: add missing pinmux Explicitly mux all T30 SoC balls now: - Colibri Address/Data Bus (GMI) - Colibri DDC - Colibri EXT_IO* - Colibri GPIO - Colibri HOTPLUG_DETECT (HDMI) - Colibri I2C - Colibri LCD (L_* resp. LDD<*>) - Colibri MMC_CD - Colibri nRESET_OUT - Colibri Parallel Camera (Optional) - Colibri PWM, , - Colibri VGA - Colibri USBC_DET - Colibri USBH_PEN - Colibri USBH_OC - on-module AX88772B LAN control signals - Colibri nBATT_FAULT(SENSE) and nVDD_FAULT(SENSE - not connected and therefore disabled signals Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-colibri.dtsi | 486 +++++++++++++++++++++++++++++++++ 1 file changed, 486 insertions(+) diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi b/arch/arm/boot/dts/tegra30-colibri.dtsi index 6bedb69be553..197605d99425 100644 --- a/arch/arm/boot/dts/tegra30-colibri.dtsi +++ b/arch/arm/boot/dts/tegra30-colibri.dtsi @@ -47,6 +47,156 @@ nvidia,tristate = ; }; + /* Colibri Address/Data Bus (GMI) */ + gmi-ad0-pg0 { + nvidia,pins = "gmi_ad0_pg0", + "gmi_ad2_pg2", + "gmi_ad3_pg3", + "gmi_ad4_pg4", + "gmi_ad5_pg5", + "gmi_ad6_pg6", + "gmi_ad7_pg7", + "gmi_ad8_ph0", + "gmi_ad9_ph1", + "gmi_ad10_ph2", + "gmi_ad11_ph3", + "gmi_ad12_ph4", + "gmi_ad13_ph5", + "gmi_ad14_ph6", + "gmi_ad15_ph7", + "gmi_adv_n_pk0", + "gmi_clk_pk1", + "gmi_cs4_n_pk2", + "gmi_cs2_n_pk3", + "gmi_iordy_pi5", + "gmi_oe_n_pi1", + "gmi_wait_pi7", + "gmi_wr_n_pi0", + "dap1_fs_pn0", + "dap1_din_pn1", + "dap1_dout_pn2", + "dap1_sclk_pn3", + "dap2_fs_pa2", + "dap2_sclk_pa3", + "dap2_din_pa4", + "dap2_dout_pa5", + "spi1_sck_px5", + "spi1_mosi_px4", + "spi1_cs0_n_px6", + "spi2_cs0_n_px3", + "spi2_miso_px1", + "spi2_mosi_px0", + "spi2_sck_px2", + "uart2_cts_n_pj5", + "uart2_rts_n_pj6"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + /* Further pins may be used as GPIOs */ + dap4-din-pp5 { + nvidia,pins = "dap4_din_pp5", + "dap4_dout_pp6", + "dap4_fs_pp4", + "dap4_sclk_pp7", + "pbb7", + "sdmmc1_clk_pz0", + "sdmmc1_cmd_pz1", + "sdmmc1_dat0_py7", + "sdmmc1_dat1_py6", + "sdmmc1_dat3_py4", + "uart3_cts_n_pa1", + "uart3_txd_pw6", + "uart3_rxd_pw7"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd-d18-pm2 { + nvidia,pins = "lcd_d18_pm2", + "lcd_d19_pm3", + "lcd_d20_pm4", + "lcd_d21_pm5", + "lcd_d22_pm6", + "lcd_d23_pm7", + "lcd_dc0_pn6", + "pex_l2_clkreq_n_pcc7"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd-cs0-n-pn4 { + nvidia,pins = "lcd_cs0_n_pn4", + "lcd_sdin_pz2", + "pu0", + "pu1", + "pu2", + "pu3", + "pu4", + "pu5", + "pu6", + "spi1_miso_px7", + "uart3_rts_n_pc0"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd-pwr0-pb2 { + nvidia,pins = "lcd_pwr0_pb2", + "lcd_sck_pz4", + "lcd_sdout_pn5", + "lcd_wr_n_pz3"; + nvidia,function = "hdcp"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb4 { + nvidia,pins = "pbb4", + "pbb5", + "pbb6"; + nvidia,function = "displayb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + /* Multiplexed RDnWR and therefore disabled */ + lcd-cs1-n-pw0 { + nvidia,pins = "lcd_cs1_n_pw0"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + /* Multiplexed GMI_CLK and therefore disabled */ + owr { + nvidia,pins = "owr"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + /* Tri-stating GMI_WR_N on nPWE SODIMM pin 99 */ + sdmmc3-dat4-pd1 { + nvidia,pins = "sdmmc3_dat4_pd1"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + /* Not tri-stating GMI_WR_N on RDnWR SODIMM pin 93 */ + sdmmc3-dat5-pd0 { + nvidia,pins = "sdmmc3_dat5_pd0"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + /* Colibri BL_ON */ pv2 { nvidia,pins = "pv2"; @@ -72,6 +222,113 @@ nvidia,enable-input = ; }; + /* Colibri DDC */ + ddc-scl-pv4 { + nvidia,pins = "ddc_scl_pv4", + "ddc_sda_pv5"; + nvidia,function = "i2c4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Colibri EXT_IO* */ + gen2-i2c-scl-pt5 { + nvidia,pins = "gen2_i2c_scl_pt5", + "gen2_i2c_sda_pt6"; + nvidia,function = "rsvd4"; + nvidia,open-drain = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spdif-in-pk6 { + nvidia,pins = "spdif_in_pk6"; + nvidia,function = "hda"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Colibri GPIO */ + clk2-out-pw5 { + nvidia,pins = "clk2_out_pw5", + "pcc2", + "pv3", + "sdmmc1_dat2_py5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd-pwr1-pc1 { + nvidia,pins = "lcd_pwr1_pc1", + "pex_l1_clkreq_n_pdd6", + "pex_l1_rst_n_pdd5"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pv1 { + nvidia,pins = "pv1", + "sdmmc3_dat0_pb7", + "sdmmc3_dat1_pb6"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Colibri HOTPLUG_DETECT (HDMI) */ + hdmi-int-pn7 { + nvidia,pins = "hdmi_int_pn7"; + nvidia,function = "hdmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Colibri I2C */ + gen1-i2c-scl-pc4 { + nvidia,pins = "gen1_i2c_scl_pc4", + "gen1_i2c_sda_pc5"; + nvidia,function = "i2c1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + /* Colibri LCD (L_* resp. LDD<*>) */ + lcd-d0-pe0 { + nvidia,pins = "lcd_d0_pe0", + "lcd_d1_pe1", + "lcd_d2_pe2", + "lcd_d3_pe3", + "lcd_d4_pe4", + "lcd_d5_pe5", + "lcd_d6_pe6", + "lcd_d7_pe7", + "lcd_d8_pf0", + "lcd_d9_pf1", + "lcd_d10_pf2", + "lcd_d11_pf3", + "lcd_d12_pf4", + "lcd_d13_pf5", + "lcd_d14_pf6", + "lcd_d15_pf7", + "lcd_d16_pm0", + "lcd_d17_pm1", + "lcd_de_pj1", + "lcd_hsync_pj3", + "lcd_pclk_pb3", + "lcd_vsync_pj4"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; /* * Colibri L_BIAS, LCD_M1 is muxed with LCD_DE * today's display need DE, disable LCD_M1 @@ -101,6 +358,105 @@ nvidia,pull = ; nvidia,tristate = ; }; + /* Colibri MMC_CD */ + gmi-wp-n-pc7 { + nvidia,pins = "gmi_wp_n_pc7"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + /* Multiplexed and therefore disabled */ + cam-mclk-pcc0 { + nvidia,pins = "cam_mclk_pcc0"; + nvidia,function = "vi_alt3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + cam-i2c-scl-pbb1 { + nvidia,pins = "cam_i2c_scl_pbb1", + "cam_i2c_sda_pbb2"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + pbb0 { + nvidia,pins = "pbb0", + "pcc1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb3 { + nvidia,pins = "pbb3"; + nvidia,function = "displayb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Colibri nRESET_OUT */ + gmi-rst-n-pi4 { + nvidia,pins = "gmi_rst_n_pi4"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* + * Colibri Parallel Camera (Optional) + * pins multiplexed with others and therefore disabled + */ + vi-vsync-pd6 { + nvidia,pins = "vi_d0_pt4", + "vi_d1_pd5", + "vi_d2_pl0", + "vi_d3_pl1", + "vi_d4_pl2", + "vi_d5_pl3", + "vi_d6_pl4", + "vi_d7_pl5", + "vi_d8_pl6", + "vi_d9_pl7", + "vi_d10_pt2", + "vi_d11_pt3", + "vi_hsync_pd7", + "vi_mclk_pt1", + "vi_pclk_pt0", + "vi_vsync_pd6"; + nvidia,function = "vi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Colibri PWM */ + sdmmc3-dat2-pb5 { + nvidia,pins = "sdmmc3_dat2_pb5"; + nvidia,function = "pwm1"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* Colibri PWM */ + sdmmc3-clk-pa6 { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "pwm2"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* Colibri PWM */ + sdmmc3-cmd-pa7 { + nvidia,pins = "sdmmc3_cmd_pa7"; + nvidia,function = "pwm3"; + nvidia,pull = ; + nvidia,tristate = ; + }; /* Colibri SSP */ ulpi-clk-py0 { @@ -157,6 +513,42 @@ nvidia,tristate = ; }; + /* Colibri USBC_DET */ + spdif-out-pk5 { + nvidia,pins = "spdif_out_pk5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Colibri USBH_PEN */ + spi2-cs1-n-pw2 { + nvidia,pins = "spi2_cs1_n_pw2"; + nvidia,function = "spi2_alt"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* Colibri USBH_OC */ + spi2-cs2-n-pw3, { + nvidia,pins = "spi2_cs2_n_pw3"; + nvidia,function = "spi2_alt"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Colibri VGA not supported and therefore disabled */ + crt-hsync-pv6 { + nvidia,pins = "crt_hsync_pv6", + "crt_vsync_pv7"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + /* eMMC (On-module) */ sdmmc4-clk-pcc4 { nvidia,pins = "sdmmc4_clk_pcc4", @@ -182,6 +574,100 @@ nvidia,enable-input = ; }; + /* LAN_EXT_WAKEUP#, LAN_PME (On-module) */ + pex-l0-rst-n-pdd1 { + nvidia,pins = "pex_l0_rst_n_pdd1", + "pex_wake_n_pdd3"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + /* LAN_V_BUS, LAN_RESET# (On-module) */ + pex-l0-clkreq-n-pdd2 { + nvidia,pins = "pex_l0_clkreq_n_pdd2", + "pex_l0_prsnt_n_pdd0"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* nBATT_FAULT(SENSE), nVDD_FAULT(SENSE) */ + pex-l2-rst-n-pcc6 { + nvidia,pins = "pex_l2_rst_n_pcc6", + "pex_l2_prsnt_n_pdd7"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Not connected and therefore disabled */ + clk1-req-pee2 { + nvidia,pins = "clk1_req_pee2", + "pex_l1_prsnt_n_pdd4"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk2-req-pcc5 { + nvidia,pins = "clk2_req_pcc5", + "clk3_out_pee0", + "clk3_req_pee1", + "clk_32k_out_pa0", + "hdmi_cec_pee3", + "sys_clk_req_pz5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-dqs-pi2 { + nvidia,pins = "gmi_dqs_pi2", + "kb_col2_pq2", + "kb_col3_pq3", + "kb_col4_pq4", + "kb_col5_pq5", + "kb_row4_pr4"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb-col0-pq0 { + nvidia,pins = "kb_col0_pq0", + "kb_col1_pq1", + "kb_col6_pq6", + "kb_col7_pq7", + "kb_row5_pr5", + "kb_row6_pr6", + "kb_row7_pr7", + "kb_row9_ps1"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb-row0-pr0 { + nvidia,pins = "kb_row0_pr0", + "kb_row1_pr1", + "kb_row2_pr2", + "kb_row3_pr3"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd-pwr2-pc6 { + nvidia,pins = "lcd_pwr2_pc6"; + nvidia,function = "hdcp"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + /* Power I2C (On-module) */ pwr-i2c-scl-pz6 { nvidia,pins = "pwr_i2c_scl_pz6", -- cgit v1.2.2 From d19c81ca22898152ff91e0578c5c7329f233444d Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sat, 1 Sep 2018 10:12:26 +0200 Subject: ARM: tegra: colibri_t30: use proper irq-gpio for stmpe811 Use proper irq-gpio for stmpe811 touch controller. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-colibri.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi b/arch/arm/boot/dts/tegra30-colibri.dtsi index 197605d99425..3a5151dc8483 100644 --- a/arch/arm/boot/dts/tegra30-colibri.dtsi +++ b/arch/arm/boot/dts/tegra30-colibri.dtsi @@ -844,8 +844,7 @@ stmpe811@41 { compatible = "st,stmpe811"; reg = <0x41>; - interrupts = ; - interrupt-parent = <&gpio>; + irq-gpio = <&gpio TEGRA_GPIO(V, 0) IRQ_TYPE_LEVEL_LOW>; interrupt-controller; id = <0>; blocks = <0x5>; -- cgit v1.2.2 From 71fd500b3806af5b54753ea66de2eb362fa2a1e9 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sat, 1 Sep 2018 10:12:27 +0200 Subject: ARM: tegra: colibri_t30: further lm95245 temperature sensor annotation Further LM95245 temperature sensor annotation. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-colibri.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi b/arch/arm/boot/dts/tegra30-colibri.dtsi index 3a5151dc8483..73ff098612a2 100644 --- a/arch/arm/boot/dts/tegra30-colibri.dtsi +++ b/arch/arm/boot/dts/tegra30-colibri.dtsi @@ -878,7 +878,7 @@ /* * LM95245 temperature sensor - * Note: OVERT_N directly connected to PMIC PWRDN + * Note: OVERT1# directly connected to TPS65911 PMIC PWRDN */ temp-sensor@4c { compatible = "national,lm95245"; -- cgit v1.2.2 From bc1fa5d2716f307e94e7b6f2181a424723c56c21 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sat, 1 Sep 2018 10:12:28 +0200 Subject: ARM: tegra: colibri_t30: add i2c-thermtrip Add i2c-thermtrip which would set the DEV_OFF bit in the DCDC control register of the TPS65911 PMIC. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-colibri.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi b/arch/arm/boot/dts/tegra30-colibri.dtsi index 73ff098612a2..670edd5e4754 100644 --- a/arch/arm/boot/dts/tegra30-colibri.dtsi +++ b/arch/arm/boot/dts/tegra30-colibri.dtsi @@ -910,6 +910,14 @@ nvidia,core-pwr-off-time = <0>; nvidia,core-power-req-active-high; nvidia,sys-clock-req-active-high; + + /* Set DEV_OFF bit in DCDC control register of TPS65911 PMIC */ + i2c-thermtrip { + nvidia,i2c-controller-id = <4>; + nvidia,bus-addr = <0x2d>; + nvidia,reg-addr = <0x3f>; + nvidia,reg-data = <0x1>; + }; }; ahub@70080000 { -- cgit v1.2.2 From 44925e4f6e35b6bb2a602bfd7546965848164a00 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sat, 1 Sep 2018 10:12:29 +0200 Subject: ARM: tegra: colibri_t30: add proper emmc vmmc and vqmmc supplies Add proper eMMC vmmc and vqmmc supplies e.g. fixing signalling voltage. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-colibri.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi b/arch/arm/boot/dts/tegra30-colibri.dtsi index 670edd5e4754..c5cb05f78604 100644 --- a/arch/arm/boot/dts/tegra30-colibri.dtsi +++ b/arch/arm/boot/dts/tegra30-colibri.dtsi @@ -931,6 +931,8 @@ status = "okay"; bus-width = <8>; non-removable; + vmmc-supply = <®_module_3v3>; /* VCC */ + vqmmc-supply = <®_1v8_vio>; /* VCCQ */ }; /* EHCI instance 1: USB2_DP/N -> AX88772B */ -- cgit v1.2.2 From dc741b7bde05a7d1e4382c7c633667fbda0f27cc Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sat, 1 Sep 2018 10:12:30 +0200 Subject: ARM: tegra: colibri_t30: enable emmc ddr52 mode Add mmc-ddr-1_8v property enabling eMMC DDR52 mode. root@colibri-t30:~# cat /sys/kernel/debug/mmc1/ios clock: 52000000 Hz actual clock: 52000000 Hz vdd: 21 (3.3 ~ 3.4 V) bus mode: 2 (push-pull) chip select: 0 (don't care) power mode: 2 (on) bus width: 3 (8 bits) timing spec: 8 (mmc DDR52) signal voltage: 1 (1.80 V) driver type: 0 (driver type B) root@colibri-t30:~# hdparm -t /dev/mmcblk1 /dev/mmcblk1: Timing buffered disk reads: 222 MB in 3.00 seconds = 73.92 MB/sec Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-colibri.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi b/arch/arm/boot/dts/tegra30-colibri.dtsi index c5cb05f78604..95b6444a6f05 100644 --- a/arch/arm/boot/dts/tegra30-colibri.dtsi +++ b/arch/arm/boot/dts/tegra30-colibri.dtsi @@ -933,6 +933,7 @@ non-removable; vmmc-supply = <®_module_3v3>; /* VCC */ vqmmc-supply = <®_1v8_vio>; /* VCCQ */ + mmc-ddr-1_8v; }; /* EHCI instance 1: USB2_DP/N -> AX88772B */ -- cgit v1.2.2 From 932079d01b177bc668d20b4d854cb9de59b5f2cc Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sat, 1 Sep 2018 10:12:31 +0200 Subject: ARM: tegra: colibri_t30: get rid of fake clocks simple bus Get rid of the fake clocks simple bus and use node names as per the actual schematics. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-colibri-eval-v3.dts | 12 ++++-------- arch/arm/boot/dts/tegra30-colibri.dtsi | 15 ++++----------- 2 files changed, 8 insertions(+), 19 deletions(-) diff --git a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts index 2aaf87ba0c42..bcdaeedcbea2 100644 --- a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts +++ b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts @@ -133,14 +133,10 @@ pwms = <&pwm 0 5000000>; /* PWM */ }; - clocks { - clk16m: clk@1 { - compatible = "fixed-clock"; - reg = <1>; - #clock-cells = <0>; - clock-frequency = <16000000>; - clock-output-names = "clk16m"; - }; + clk16m: osc3 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <16000000>; }; gpio-keys { diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi b/arch/arm/boot/dts/tegra30-colibri.dtsi index 95b6444a6f05..4fcdc93ae687 100644 --- a/arch/arm/boot/dts/tegra30-colibri.dtsi +++ b/arch/arm/boot/dts/tegra30-colibri.dtsi @@ -954,17 +954,10 @@ vbus-supply = <®_lan_v_bus>; }; - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clk@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; + clk32k_in: xtal1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; }; reg_1v8_avdd_hdmi_pll: regulator-1v8-avdd-hdmi-pll { -- cgit v1.2.2 From 23a13d4c4dacc79b10b353f0149b5fd59f3a1f47 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sat, 1 Sep 2018 10:12:32 +0200 Subject: ARM: tegra: colibri_t30: line break long compatible property line Line break long compatible property line. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-colibri-eval-v3.dts | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts index bcdaeedcbea2..d8ee7edb24cf 100644 --- a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts +++ b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts @@ -5,7 +5,8 @@ / { model = "Toradex Colibri T30 on Colibri Evaluation Board"; - compatible = "toradex,colibri_t30-eval-v3", "toradex,colibri_t30", "nvidia,tegra30"; + compatible = "toradex,colibri_t30-eval-v3", "toradex,colibri_t30", + "nvidia,tegra30"; aliases { rtc0 = "/i2c@7000c000/rtc@68"; -- cgit v1.2.2 From ead9a4c36db53cf31008ac723e7dc8a4ed53700d Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sat, 1 Sep 2018 10:12:33 +0200 Subject: ARM: tegra: colibri_t30: move input include to carrier board Move input include to carrier board. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-colibri-eval-v3.dts | 1 + arch/arm/boot/dts/tegra30-colibri.dtsi | 1 - 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts index d8ee7edb24cf..16f5e6af68b9 100644 --- a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts +++ b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /dts-v1/; +#include #include "tegra30-colibri.dtsi" / { diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi b/arch/arm/boot/dts/tegra30-colibri.dtsi index 4fcdc93ae687..0d8b0f319c6f 100644 --- a/arch/arm/boot/dts/tegra30-colibri.dtsi +++ b/arch/arm/boot/dts/tegra30-colibri.dtsi @@ -1,5 +1,4 @@ // SPDX-License-Identifier: GPL-2.0 -#include #include "tegra30.dtsi" /* -- cgit v1.2.2 From 0fb83a83691f8681264653ebeb8b29664694d44b Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sat, 1 Sep 2018 10:12:34 +0200 Subject: ARM: tegra: colibri_t30: remove unused nvidia, is-wired property Remove unused nvidia,is-wired property. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-colibri.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi b/arch/arm/boot/dts/tegra30-colibri.dtsi index 0d8b0f319c6f..eb36ae3038a7 100644 --- a/arch/arm/boot/dts/tegra30-colibri.dtsi +++ b/arch/arm/boot/dts/tegra30-colibri.dtsi @@ -949,7 +949,6 @@ usb-phy@7d004000 { status = "okay"; - nvidia,is-wired = <1>; vbus-supply = <®_lan_v_bus>; }; -- cgit v1.2.2 From 1e7c4fc3daa3da63492296f7ed6ce59aaaa4595a Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sat, 1 Sep 2018 10:12:35 +0200 Subject: ARM: tegra: colibri_t30: add gpio hog to unreset usb ethernet chip Add GPIO hog to unreset ASIX AX88772B USB Ethernet chip. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-colibri.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi b/arch/arm/boot/dts/tegra30-colibri.dtsi index eb36ae3038a7..aff94707b3fa 100644 --- a/arch/arm/boot/dts/tegra30-colibri.dtsi +++ b/arch/arm/boot/dts/tegra30-colibri.dtsi @@ -1027,3 +1027,12 @@ clock-names = "pll_a", "pll_a_out0", "mclk"; }; }; + +&gpio { + lan-reset-n { + gpio-hog; + gpios = ; + output-high; + line-name = "LAN_RESET#"; + }; +}; -- cgit v1.2.2 From e0957df84a542286a9c468fe81777d4e837815ce Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sat, 1 Sep 2018 10:12:36 +0200 Subject: ARM: tegra: colibri_t30: enable hda over hdmi Enable HDA over HDMI. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-colibri.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi b/arch/arm/boot/dts/tegra30-colibri.dtsi index aff94707b3fa..1337674c530c 100644 --- a/arch/arm/boot/dts/tegra30-colibri.dtsi +++ b/arch/arm/boot/dts/tegra30-colibri.dtsi @@ -919,6 +919,10 @@ }; }; + hda@70030000 { + status = "okay"; + }; + ahub@70080000 { i2s@70080500 { status = "okay"; -- cgit v1.2.2 From f234e54388483e03d6c3029654c5bd787defe5ff Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sat, 1 Sep 2018 10:12:37 +0200 Subject: ARM: tegra: colibri_t30: annotate sd card detect Annotate SD card detect. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-colibri-eval-v3.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts index 16f5e6af68b9..aca4cd786442 100644 --- a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts +++ b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts @@ -100,7 +100,7 @@ sdhci@78000200 { status = "okay"; bus-width = <4>; - cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>; + cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>; /* MMCD */ no-1-8-v; }; -- cgit v1.2.2 From 20fd13e2a1bf67f002a56a5aa0ca27b2f0978358 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sat, 1 Sep 2018 10:12:38 +0200 Subject: ARM: tegra: colibri_t30: annotate ehci instance 1 Annotate EHCI instance 1 (USB2_DP/N) connecting to ASIX AX88772B USB to Ethernet chip being on-module. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-colibri.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi b/arch/arm/boot/dts/tegra30-colibri.dtsi index 1337674c530c..7a4e454a1960 100644 --- a/arch/arm/boot/dts/tegra30-colibri.dtsi +++ b/arch/arm/boot/dts/tegra30-colibri.dtsi @@ -939,7 +939,7 @@ mmc-ddr-1_8v; }; - /* EHCI instance 1: USB2_DP/N -> AX88772B */ + /* EHCI instance 1: USB2_DP/N -> AX88772B (On-module) */ usb@7d004000 { status = "okay"; #address-cells = <1>; -- cgit v1.2.2 From a1f5a76ff054cc96970b116f88636fa2ecba75d6 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sat, 1 Sep 2018 10:12:39 +0200 Subject: ARM: tegra: colibri_t30: update compatibility comment Update compatibility comment. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-colibri.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi b/arch/arm/boot/dts/tegra30-colibri.dtsi index 7a4e454a1960..9bd7034b8e66 100644 --- a/arch/arm/boot/dts/tegra30-colibri.dtsi +++ b/arch/arm/boot/dts/tegra30-colibri.dtsi @@ -3,7 +3,7 @@ /* * Toradex Colibri T30 Module Device Tree - * Compatible for Revisions V1.1B, V1.1C, V1.1D, V1.1E; IT: V1.1A + * Compatible for Revisions V1.1B, V1.1C, V1.1D, V1.1E, V1.1F; IT: V1.1A, V1.1B */ / { model = "Toradex Colibri T30"; -- cgit v1.2.2 From 9eca7649a712eb147679acd804708fd37ddb5faf Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sat, 1 Sep 2018 10:12:40 +0200 Subject: ARM: tegra: colibri_t30: drop module level model and compatible Drop model and compatible nodes from the module level device tree as they get overridden by the carrier board device tree anyway. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-colibri.dtsi | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi b/arch/arm/boot/dts/tegra30-colibri.dtsi index 9bd7034b8e66..f4aee43402d1 100644 --- a/arch/arm/boot/dts/tegra30-colibri.dtsi +++ b/arch/arm/boot/dts/tegra30-colibri.dtsi @@ -6,9 +6,6 @@ * Compatible for Revisions V1.1B, V1.1C, V1.1D, V1.1E, V1.1F; IT: V1.1A, V1.1B */ / { - model = "Toradex Colibri T30"; - compatible = "toradex,colibri_t30", "nvidia,tegra30"; - memory@80000000 { reg = <0x80000000 0x40000000>; }; -- cgit v1.2.2 From ccb99d44c393a0c1be89d3ae64bdad0237a6bae6 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sat, 1 Sep 2018 10:12:41 +0200 Subject: ARM: tegra: colibri_t30: drop obsolete spidev node Drop obsolete spidev device tree node as nowadays one should do this by binding the spidev driver to specific instances/chip selects at runtime. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-colibri-eval-v3.dts | 6 ------ 1 file changed, 6 deletions(-) diff --git a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts index aca4cd786442..c08e09908578 100644 --- a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts +++ b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts @@ -88,12 +88,6 @@ interrupts = ; spi-max-frequency = <10000000>; }; - - spidev0: spi@1 { - compatible = "spidev"; - reg = <1>; - spi-max-frequency = <25000000>; - }; }; /* SD/MMC */ -- cgit v1.2.2 From 8941e330492502c6b9a28cfe6076e9ab1b80ac07 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sat, 1 Sep 2018 10:12:42 +0200 Subject: ARM: tegra: colibri_t30: rename hdmiddc to hdmi_ddc Rename hdmiddc to hdmi_ddc to be more in-line with other device trees. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-colibri-eval-v3.dts | 2 +- arch/arm/boot/dts/tegra30-colibri.dtsi | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts index c08e09908578..49771ea379ed 100644 --- a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts +++ b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts @@ -71,7 +71,7 @@ }; /* DDC_CLOCK/DATA on X3 pin 15/16 (e.g. display EDID) */ - hdmiddc: i2c@7000c700 { + i2c@7000c700 { status = "okay"; }; diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi b/arch/arm/boot/dts/tegra30-colibri.dtsi index f4aee43402d1..03047d2bba9d 100644 --- a/arch/arm/boot/dts/tegra30-colibri.dtsi +++ b/arch/arm/boot/dts/tegra30-colibri.dtsi @@ -12,7 +12,7 @@ host1x@50000000 { hdmi@54280000 { - nvidia,ddc-i2c-bus = <&hdmiddc>; + nvidia,ddc-i2c-bus = <&hdmi_ddc>; nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; pll-supply = <®_1v8_avdd_hdmi_pll>; @@ -707,7 +707,7 @@ compatible = "nvidia,tegra30-hsuart"; }; - hdmiddc: i2c@7000c700 { + hdmi_ddc: i2c@7000c700 { clock-frequency = <10000>; }; -- cgit v1.2.2 From 63ad93767ad60cd7722c7a0b0c6af59e2d1cfd5b Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sat, 1 Sep 2018 10:12:43 +0200 Subject: ARM: tegra: colibri_t30: rename tps65911@2d, stmpe811@41 and tps62362@60 Rename a few nodes using more common names: - rename tps65911@2d to pmic@2d - rename stmpe811@41 to touchscreen@41 - rename tps62362@60 to regulator@60 Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-colibri-eval-v3.dts | 2 +- arch/arm/boot/dts/tegra30-colibri.dtsi | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts index 49771ea379ed..c63ef3aedb7a 100644 --- a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts +++ b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts @@ -11,7 +11,7 @@ aliases { rtc0 = "/i2c@7000c000/rtc@68"; - rtc1 = "/i2c@7000d000/tps65911@2d"; + rtc1 = "/i2c@7000d000/pmic@2d"; rtc2 = "/rtc@7000e000"; serial0 = &uarta; serial1 = &uartb; diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi b/arch/arm/boot/dts/tegra30-colibri.dtsi index 03047d2bba9d..e32702a4ab10 100644 --- a/arch/arm/boot/dts/tegra30-colibri.dtsi +++ b/arch/arm/boot/dts/tegra30-colibri.dtsi @@ -729,7 +729,7 @@ clocks = <&tegra_car TEGRA30_CLK_EXTERN1>; }; - pmic: tps65911@2d { + pmic: pmic@2d { compatible = "ti,tps65911"; reg = <0x2d>; @@ -837,7 +837,7 @@ }; /* STMPE811 touch screen controller */ - stmpe811@41 { + touchscreen@41 { compatible = "st,stmpe811"; reg = <0x41>; irq-gpio = <&gpio TEGRA_GPIO(V, 0) IRQ_TYPE_LEVEL_LOW>; @@ -882,7 +882,7 @@ }; /* SW: +V1.2_VDD_CORE */ - tps62362@60 { + regulator@60 { compatible = "ti,tps62362"; reg = <0x60>; -- cgit v1.2.2 From 503fcd8464fb6cd18073e97dec59b933930655d6 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sat, 1 Sep 2018 10:12:44 +0200 Subject: ARM: tegra: colibri_t30: fix mcp2515 can controller interrupt polarity Fix the MCP2515 SPI CAN controller interrupt polarity which according to its datasheet defaults to low-active aka falling edge. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-colibri-eval-v3.dts | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts index c63ef3aedb7a..ee0a3e5df5b8 100644 --- a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts +++ b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts @@ -85,7 +85,8 @@ reg = <0>; clocks = <&clk16m>; interrupt-parent = <&gpio>; - interrupts = ; + /* CAN_INT */ + interrupts = ; spi-max-frequency = <10000000>; }; }; -- cgit v1.2.2 From e4f75fd1118d4eec6469f4ff7cc6e790c15dd23e Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sat, 1 Sep 2018 10:12:45 +0200 Subject: ARM: tegra: colibri_t30: remove unused mcp2515 can0 label Get rid of the unused MCP2515 SPI CAN controller can0 label. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-colibri-eval-v3.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts index ee0a3e5df5b8..618a4b3b6bc8 100644 --- a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts +++ b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts @@ -80,7 +80,7 @@ status = "okay"; spi-max-frequency = <25000000>; - can0: can@0 { + can@0 { compatible = "microchip,mcp2515"; reg = <0>; clocks = <&clk16m>; -- cgit v1.2.2 From 070c1342719c5ba165a751205ad96b1f7e85741a Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sat, 1 Sep 2018 10:12:46 +0200 Subject: ARM: tegra: colibri_t30: add mcp2515 vdd and xceiver supplies Add the MCP2515 SPI CAN controller's vdd-supply being the regular carrier board's reg_3v3 and xceiver-supply being reg_5v0. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-colibri-eval-v3.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts index 618a4b3b6bc8..9985d0a91f69 100644 --- a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts +++ b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts @@ -88,6 +88,8 @@ /* CAN_INT */ interrupts = ; spi-max-frequency = <10000000>; + vdd-supply = <®_3v3>; + xceiver-supply = <®_5v0>; }; }; -- cgit v1.2.2 From f7ce7658c03cbbf0933870a56b6e89005c80e404 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sat, 1 Sep 2018 10:12:47 +0200 Subject: ARM: tegra: colibri_t30: annotate unused i2c busses Both GEN2_I2C as well as CAM_I2C (I2C3) are unused in our design. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-colibri-eval-v3.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts index 9985d0a91f69..5965150ecdd2 100644 --- a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts +++ b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts @@ -70,6 +70,10 @@ }; }; + /* GEN2_I2C: unused */ + + /* CAM_I2C (I2C3): unused */ + /* DDC_CLOCK/DATA on X3 pin 15/16 (e.g. display EDID) */ i2c@7000c700 { status = "okay"; -- cgit v1.2.2 From 5ffdfa1aca4cd11b0f0c8a52a81c4e3ddcd49e22 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sat, 1 Sep 2018 10:12:48 +0200 Subject: ARM: tegra: colibri_t30: annotate power I2C being on-module The power I2C bus aka PWR_I2C which connects to the audio codec, PMIC, temperature sensor and touch screen controller is really on-module only. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-colibri.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi b/arch/arm/boot/dts/tegra30-colibri.dtsi index e32702a4ab10..35af03ca9e90 100644 --- a/arch/arm/boot/dts/tegra30-colibri.dtsi +++ b/arch/arm/boot/dts/tegra30-colibri.dtsi @@ -713,7 +713,7 @@ /* * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and - * touch screen controller + * touch screen controller (On-module) */ i2c@7000d000 { status = "okay"; -- cgit v1.2.2 From 864495be67f8c7b1c54d6b87b9bc55bc479485a4 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sat, 1 Sep 2018 15:04:46 +0200 Subject: ARM: tegra: apalis-tk1: add local-mac-address property Add empty local-mac-address property to be filled in by boot loader (e.g. U-Boot). Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi | 5 +++++ arch/arm/boot/dts/tegra124-apalis.dtsi | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi index 573aaa50fff1..09e3641258ae 100644 --- a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi @@ -42,6 +42,11 @@ phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>; phy-names = "pcie-0"; status = "okay"; + + pcie@0 { + reg = <0 0 0 0 0>; + local-mac-address = [00 00 00 00 00 00]; + }; }; }; diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/tegra124-apalis.dtsi index 0f0d4a4988b9..5e7ae5e92fb8 100644 --- a/arch/arm/boot/dts/tegra124-apalis.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis.dtsi @@ -77,6 +77,11 @@ phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>; phy-names = "pcie-0"; status = "okay"; + + pcie@0 { + reg = <0 0 0 0 0>; + local-mac-address = [00 00 00 00 00 00]; + }; }; }; -- cgit v1.2.2 From f2f7bf06c54af33fbc482fe4ae83a4fb9928f956 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sat, 1 Sep 2018 15:04:47 +0200 Subject: ARM: tegra: apalis-tk1: reorder host1x/hdmi properties Reorder Host1x/HDMI properties. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi | 4 ++-- arch/arm/boot/dts/tegra124-apalis.dtsi | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi index 09e3641258ae..86768ba28d67 100644 --- a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi @@ -52,11 +52,11 @@ host1x@50000000 { hdmi@54280000 { - pll-supply = <®_1v05_avdd_hdmi_pll>; - vdd-supply = <®_3v3_avdd_hdmi>; nvidia,ddc-i2c-bus = <&hdmi_ddc>; nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; + pll-supply = <®_1v05_avdd_hdmi_pll>; + vdd-supply = <®_3v3_avdd_hdmi>; }; }; diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/tegra124-apalis.dtsi index 5e7ae5e92fb8..2c291d210677 100644 --- a/arch/arm/boot/dts/tegra124-apalis.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis.dtsi @@ -87,11 +87,11 @@ host1x@50000000 { hdmi@54280000 { - pll-supply = <®_1v05_avdd_hdmi_pll>; - vdd-supply = <®_3v3_avdd_hdmi>; nvidia,ddc-i2c-bus = <&hdmi_ddc>; nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; + pll-supply = <®_1v05_avdd_hdmi_pll>; + vdd-supply = <®_3v3_avdd_hdmi>; }; }; -- cgit v1.2.2 From a945eae0c603882e2744253738f3a209b1e4bd49 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sat, 1 Sep 2018 15:04:48 +0200 Subject: ARM: tegra: apalis-tk1: reorder padctl properties Reorder padctl properties. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi | 22 +++++++++++----------- arch/arm/boot/dts/tegra124-apalis.dtsi | 22 +++++++++++----------- 2 files changed, 22 insertions(+), 22 deletions(-) diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi index 86768ba28d67..f6459588d845 100644 --- a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi @@ -1815,18 +1815,18 @@ lanes { usb2-0 { - nvidia,function = "xusb"; status = "okay"; + nvidia,function = "xusb"; }; usb2-1 { - nvidia,function = "xusb"; status = "okay"; + nvidia,function = "xusb"; }; usb2-2 { - nvidia,function = "xusb"; status = "okay"; + nvidia,function = "xusb"; }; }; }; @@ -1836,28 +1836,28 @@ lanes { pcie-0 { - nvidia,function = "usb3-ss"; status = "okay"; + nvidia,function = "usb3-ss"; }; pcie-1 { - nvidia,function = "usb3-ss"; status = "okay"; + nvidia,function = "usb3-ss"; }; pcie-2 { - nvidia,function = "pcie"; status = "okay"; + nvidia,function = "pcie"; }; pcie-3 { - nvidia,function = "pcie"; status = "okay"; + nvidia,function = "pcie"; }; pcie-4 { - nvidia,function = "pcie"; status = "okay"; + nvidia,function = "pcie"; }; }; }; @@ -1867,8 +1867,8 @@ lanes { sata-0 { - nvidia,function = "sata"; status = "okay"; + nvidia,function = "sata"; }; }; }; @@ -1900,13 +1900,13 @@ }; usb3-0 { - nvidia,usb2-companion = <2>; status = "okay"; + nvidia,usb2-companion = <2>; }; usb3-1 { - nvidia,usb2-companion = <0>; status = "okay"; + nvidia,usb2-companion = <0>; }; }; }; diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/tegra124-apalis.dtsi index 2c291d210677..8919213d8312 100644 --- a/arch/arm/boot/dts/tegra124-apalis.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis.dtsi @@ -1844,18 +1844,18 @@ lanes { usb2-0 { - nvidia,function = "xusb"; status = "okay"; + nvidia,function = "xusb"; }; usb2-1 { - nvidia,function = "xusb"; status = "okay"; + nvidia,function = "xusb"; }; usb2-2 { - nvidia,function = "xusb"; status = "okay"; + nvidia,function = "xusb"; }; }; }; @@ -1865,28 +1865,28 @@ lanes { pcie-0 { - nvidia,function = "usb3-ss"; status = "okay"; + nvidia,function = "usb3-ss"; }; pcie-1 { - nvidia,function = "usb3-ss"; status = "okay"; + nvidia,function = "usb3-ss"; }; pcie-2 { - nvidia,function = "pcie"; status = "okay"; + nvidia,function = "pcie"; }; pcie-3 { - nvidia,function = "pcie"; status = "okay"; + nvidia,function = "pcie"; }; pcie-4 { - nvidia,function = "pcie"; status = "okay"; + nvidia,function = "pcie"; }; }; }; @@ -1896,8 +1896,8 @@ lanes { sata-0 { - nvidia,function = "sata"; status = "okay"; + nvidia,function = "sata"; }; }; }; @@ -1929,13 +1929,13 @@ }; usb3-0 { - nvidia,usb2-companion = <2>; status = "okay"; + nvidia,usb2-companion = <2>; }; usb3-1 { - nvidia,usb2-companion = <0>; status = "okay"; + nvidia,usb2-companion = <0>; }; }; }; -- cgit v1.2.2 From 1bef3a5716b4516c742dee6750cc47f44d77d378 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sat, 1 Sep 2018 15:04:49 +0200 Subject: ARM: tegra: apalis-tk1: regulator clean-up Just cosmetic regulator clean-up. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi | 100 ++++++++++++++-------------- arch/arm/boot/dts/tegra124-apalis.dtsi | 100 ++++++++++++++-------------- 2 files changed, 100 insertions(+), 100 deletions(-) diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi index f6459588d845..13aa8c797d42 100644 --- a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi @@ -21,13 +21,13 @@ pcie@1003000 { status = "okay"; - avddio-pex-supply = <&vdd_1v05>; - avdd-pex-pll-supply = <&vdd_1v05>; - avdd-pll-erefe-supply = <&avdd_1v05>; - dvddio-pex-supply = <&vdd_1v05>; - hvdd-pex-pll-e-supply = <®_3v3>; - hvdd-pex-supply = <®_3v3>; - vddio-pex-ctl-supply = <®_3v3>; + avddio-pex-supply = <®_1v05_vdd>; + avdd-pex-pll-supply = <®_1v05_vdd>; + avdd-pll-erefe-supply = <®_1v05_avdd>; + dvddio-pex-supply = <®_1v05_vdd>; + hvdd-pex-pll-e-supply = <®_module_3v3>; + hvdd-pex-supply = <®_module_3v3>; + vddio-pex-ctl-supply = <®_module_3v3>; /* Apalis PCIe (additional lane Apalis type specific) */ pci@1,0 { @@ -65,7 +65,7 @@ * Node left disabled on purpose - the bootloader will enable * it after having set the VPR up */ - vdd-supply = <&vdd_gpu>; + vdd-supply = <®_vdd_gpu>; }; pinmux: pinmux@70000868 { @@ -1565,8 +1565,8 @@ sgtl5000: codec@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; - VDDA-supply = <®_3v3>; - VDDIO-supply = <&vddio_1v8>; + VDDA-supply = <®_module_3v3>; + VDDIO-supply = <®_1v8_vddio>; clocks = <&tegra_car TEGRA124_CLK_EXTERN1>; }; @@ -1598,18 +1598,18 @@ }; regulators { - vsup-sd2-supply = <®_3v3>; - vsup-sd3-supply = <®_3v3>; - vsup-sd4-supply = <®_3v3>; - vsup-sd5-supply = <®_3v3>; - vin-ldo0-supply = <&vddio_ddr_1v35>; - vin-ldo1-6-supply = <®_3v3>; - vin-ldo2-5-7-supply = <&vddio_1v8>; - vin-ldo3-4-supply = <®_3v3>; - vin-ldo9-10-supply = <®_3v3>; - vin-ldo11-supply = <®_3v3>; - - vdd_cpu: sd0 { + vsup-sd2-supply = <®_module_3v3>; + vsup-sd3-supply = <®_module_3v3>; + vsup-sd4-supply = <®_module_3v3>; + vsup-sd5-supply = <®_module_3v3>; + vin-ldo0-supply = <®_1v35_vddio_ddr>; + vin-ldo1-6-supply = <®_module_3v3>; + vin-ldo2-5-7-supply = <®_1v8_vddio>; + vin-ldo3-4-supply = <®_module_3v3>; + vin-ldo9-10-supply = <®_module_3v3>; + vin-ldo11-supply = <®_module_3v3>; + + reg_vdd_cpu: sd0 { regulator-name = "+VDD_CPU_AP"; regulator-min-microvolt = <700000>; regulator-max-microvolt = <1400000>; @@ -1631,7 +1631,7 @@ ams,ext-control = <1>; }; - vddio_ddr_1v35: sd2 { + reg_1v35_vddio_ddr: sd2 { regulator-name = "+V1.35_VDDIO_DDR(sd2)"; regulator-min-microvolt = <1350000>; @@ -1649,13 +1649,13 @@ regulator-boot-on; }; - vdd_1v05: sd4 { + reg_1v05_vdd: sd4 { regulator-name = "+V1.05"; regulator-min-microvolt = <1050000>; regulator-max-microvolt = <1050000>; }; - vddio_1v8: sd5 { + reg_1v8_vddio: sd5 { regulator-name = "+V1.8"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; @@ -1663,7 +1663,7 @@ regulator-always-on; }; - vdd_gpu: sd6 { + reg_vdd_gpu: sd6 { regulator-name = "+VDD_GPU_AP"; regulator-min-microvolt = <650000>; regulator-max-microvolt = <1200000>; @@ -1673,7 +1673,7 @@ regulator-always-on; }; - avdd_1v05: ldo0 { + reg_1v05_avdd: ldo0 { regulator-name = "+V1.05_AVDD"; regulator-min-microvolt = <1050000>; regulator-max-microvolt = <1050000>; @@ -1785,9 +1785,9 @@ sata@70020000 { phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>; phy-names = "sata-0"; - avdd-supply = <&vdd_1v05>; - hvdd-supply = <®_3v3>; - vddio-supply = <&vdd_1v05>; + avdd-supply = <®_1v05_vdd>; + hvdd-supply = <®_module_3v3>; + vddio-supply = <®_1v05_vdd>; }; usb@70090000 { @@ -1798,14 +1798,14 @@ <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>; phy-names = "usb2-0", "usb3-1", "usb2-1", "usb2-2", "usb3-0"; - avddio-pex-supply = <&vdd_1v05>; - avdd-pll-erefe-supply = <&avdd_1v05>; - avdd-pll-utmip-supply = <&vddio_1v8>; - avdd-usb-ss-pll-supply = <&vdd_1v05>; - avdd-usb-supply = <®_3v3>; - dvddio-pex-supply = <&vdd_1v05>; - hvdd-usb-ss-pll-e-supply = <®_3v3>; - hvdd-usb-ss-supply = <®_3v3>; + avddio-pex-supply = <®_1v05_vdd>; + avdd-pll-erefe-supply = <®_1v05_avdd>; + avdd-pll-utmip-supply = <®_1v8_vddio>; + avdd-usb-ss-pll-supply = <®_1v05_vdd>; + avdd-usb-supply = <®_module_3v3>; + dvddio-pex-supply = <®_1v05_vdd>; + hvdd-usb-ss-pll-e-supply = <®_module_3v3>; + hvdd-usb-ss-supply = <®_module_3v3>; }; padctl@7009f000 { @@ -1921,7 +1921,7 @@ /* CPU DFLL clock */ clock@70110000 { status = "okay"; - vdd-cpu-supply = <&vdd_cpu>; + vdd-cpu-supply = <®_vdd_cpu>; nvidia,i2c-fs-rate = <400000>; }; @@ -1946,7 +1946,7 @@ cpus { cpu@0 { - vdd-cpu-supply = <&vdd_cpu>; + vdd-cpu-supply = <®_vdd_cpu>; }; }; @@ -1956,7 +1956,7 @@ regulator-min-microvolt = <1050000>; regulator-max-microvolt = <1050000>; gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; - vin-supply = <&vdd_1v05>; + vin-supply = <®_1v05_vdd>; }; reg_3v3_mxm: regulator-3v3-mxm { @@ -1968,7 +1968,15 @@ regulator-boot-on; }; - reg_3v3: regulator-3v3 { + reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi { + compatible = "regulator-fixed"; + regulator-name = "+V3.3_AVDD_HDMI"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_1v05_vdd>; + }; + + reg_module_3v3: regulator-module-3v3 { compatible = "regulator-fixed"; regulator-name = "+V3.3"; regulator-min-microvolt = <3300000>; @@ -1981,14 +1989,6 @@ vin-supply = <®_3v3_mxm>; }; - reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi { - compatible = "regulator-fixed"; - regulator-name = "+V3.3_AVDD_HDMI"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vdd_1v05>; - }; - sound { compatible = "toradex,tegra-audio-sgtl5000-apalis_tk1", "nvidia,tegra-audio-sgtl5000"; diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/tegra124-apalis.dtsi index 8919213d8312..40c6ca2d1385 100644 --- a/arch/arm/boot/dts/tegra124-apalis.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis.dtsi @@ -56,13 +56,13 @@ pcie@1003000 { status = "okay"; - avddio-pex-supply = <&vdd_1v05>; - avdd-pex-pll-supply = <&vdd_1v05>; - avdd-pll-erefe-supply = <&avdd_1v05>; - dvddio-pex-supply = <&vdd_1v05>; - hvdd-pex-pll-e-supply = <®_3v3>; - hvdd-pex-supply = <®_3v3>; - vddio-pex-ctl-supply = <®_3v3>; + avddio-pex-supply = <®_1v05_vdd>; + avdd-pex-pll-supply = <®_1v05_vdd>; + avdd-pll-erefe-supply = <®_1v05_avdd>; + dvddio-pex-supply = <®_1v05_vdd>; + hvdd-pex-pll-e-supply = <®_module_3v3>; + hvdd-pex-supply = <®_module_3v3>; + vddio-pex-ctl-supply = <®_module_3v3>; /* Apalis PCIe (additional lane Apalis type specific) */ pci@1,0 { @@ -100,7 +100,7 @@ * Node left disabled on purpose - the bootloader will enable * it after having set the VPR up */ - vdd-supply = <&vdd_gpu>; + vdd-supply = <®_vdd_gpu>; }; pinmux: pinmux@70000868 { @@ -1594,8 +1594,8 @@ sgtl5000: codec@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; - VDDA-supply = <®_3v3>; - VDDIO-supply = <&vddio_1v8>; + VDDA-supply = <®_module_3v3>; + VDDIO-supply = <®_1v8_vddio>; clocks = <&tegra_car TEGRA124_CLK_EXTERN1>; }; @@ -1627,18 +1627,18 @@ }; regulators { - vsup-sd2-supply = <®_3v3>; - vsup-sd3-supply = <®_3v3>; - vsup-sd4-supply = <®_3v3>; - vsup-sd5-supply = <®_3v3>; - vin-ldo0-supply = <&vddio_ddr_1v35>; - vin-ldo1-6-supply = <®_3v3>; - vin-ldo2-5-7-supply = <&vddio_1v8>; - vin-ldo3-4-supply = <®_3v3>; - vin-ldo9-10-supply = <®_3v3>; - vin-ldo11-supply = <®_3v3>; - - vdd_cpu: sd0 { + vsup-sd2-supply = <®_module_3v3>; + vsup-sd3-supply = <®_module_3v3>; + vsup-sd4-supply = <®_module_3v3>; + vsup-sd5-supply = <®_module_3v3>; + vin-ldo0-supply = <®_1v35_vddio_ddr>; + vin-ldo1-6-supply = <®_module_3v3>; + vin-ldo2-5-7-supply = <®_1v8_vddio>; + vin-ldo3-4-supply = <®_module_3v3>; + vin-ldo9-10-supply = <®_module_3v3>; + vin-ldo11-supply = <®_module_3v3>; + + reg_vdd_cpu: sd0 { regulator-name = "+VDD_CPU_AP"; regulator-min-microvolt = <700000>; regulator-max-microvolt = <1400000>; @@ -1660,7 +1660,7 @@ ams,ext-control = <1>; }; - vddio_ddr_1v35: sd2 { + reg_1v35_vddio_ddr: sd2 { regulator-name = "+V1.35_VDDIO_DDR(sd2)"; regulator-min-microvolt = <1350000>; @@ -1678,13 +1678,13 @@ regulator-boot-on; }; - vdd_1v05: sd4 { + reg_1v05_vdd: sd4 { regulator-name = "+V1.05"; regulator-min-microvolt = <1050000>; regulator-max-microvolt = <1050000>; }; - vddio_1v8: sd5 { + reg_1v8_vddio: sd5 { regulator-name = "+V1.8"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; @@ -1692,7 +1692,7 @@ regulator-always-on; }; - vdd_gpu: sd6 { + reg_vdd_gpu: sd6 { regulator-name = "+VDD_GPU_AP"; regulator-min-microvolt = <650000>; regulator-max-microvolt = <1200000>; @@ -1702,7 +1702,7 @@ regulator-always-on; }; - avdd_1v05: ldo0 { + reg_1v05_avdd: ldo0 { regulator-name = "+V1.05_AVDD"; regulator-min-microvolt = <1050000>; regulator-max-microvolt = <1050000>; @@ -1814,9 +1814,9 @@ sata@70020000 { phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>; phy-names = "sata-0"; - avdd-supply = <&vdd_1v05>; - hvdd-supply = <®_3v3>; - vddio-supply = <&vdd_1v05>; + avdd-supply = <®_1v05_vdd>; + hvdd-supply = <®_module_3v3>; + vddio-supply = <®_1v05_vdd>; }; usb@70090000 { @@ -1827,14 +1827,14 @@ <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>; phy-names = "usb2-0", "usb3-1", "usb2-1", "usb2-2", "usb3-0"; - avddio-pex-supply = <&vdd_1v05>; - avdd-pll-erefe-supply = <&avdd_1v05>; - avdd-pll-utmip-supply = <&vddio_1v8>; - avdd-usb-ss-pll-supply = <&vdd_1v05>; - avdd-usb-supply = <®_3v3>; - dvddio-pex-supply = <&vdd_1v05>; - hvdd-usb-ss-pll-e-supply = <®_3v3>; - hvdd-usb-ss-supply = <®_3v3>; + avddio-pex-supply = <®_1v05_vdd>; + avdd-pll-erefe-supply = <®_1v05_avdd>; + avdd-pll-utmip-supply = <®_1v8_vddio>; + avdd-usb-ss-pll-supply = <®_1v05_vdd>; + avdd-usb-supply = <®_module_3v3>; + dvddio-pex-supply = <®_1v05_vdd>; + hvdd-usb-ss-pll-e-supply = <®_module_3v3>; + hvdd-usb-ss-supply = <®_module_3v3>; }; padctl@7009f000 { @@ -1950,7 +1950,7 @@ /* CPU DFLL clock */ clock@70110000 { status = "okay"; - vdd-cpu-supply = <&vdd_cpu>; + vdd-cpu-supply = <®_vdd_cpu>; nvidia,i2c-fs-rate = <400000>; }; @@ -1975,7 +1975,7 @@ cpus { cpu@0 { - vdd-cpu-supply = <&vdd_cpu>; + vdd-cpu-supply = <®_vdd_cpu>; }; }; @@ -1985,7 +1985,7 @@ regulator-min-microvolt = <1050000>; regulator-max-microvolt = <1050000>; gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; - vin-supply = <&vdd_1v05>; + vin-supply = <®_1v05_vdd>; }; reg_3v3_mxm: regulator-3v3-mxm { @@ -1997,7 +1997,15 @@ regulator-boot-on; }; - reg_3v3: regulator-3v3 { + reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi { + compatible = "regulator-fixed"; + regulator-name = "+V3.3_AVDD_HDMI"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_1v05_vdd>; + }; + + reg_module_3v3: regulator-module-3v3 { compatible = "regulator-fixed"; regulator-name = "+V3.3"; regulator-min-microvolt = <3300000>; @@ -2010,14 +2018,6 @@ vin-supply = <®_3v3_mxm>; }; - reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi { - compatible = "regulator-fixed"; - regulator-name = "+V3.3_AVDD_HDMI"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vdd_1v05>; - }; - sound { compatible = "toradex,tegra-audio-sgtl5000-apalis_tk1", "nvidia,tegra-audio-sgtl5000"; -- cgit v1.2.2 From 8c3a9d213bfe8b8f131772342bf61123402b0489 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sat, 1 Sep 2018 15:04:50 +0200 Subject: ARM: tegra: apalis-tk1: add missing regulators Add missing regulators: - reg_module_3v3_audio being VDDA supply of SGTL5000 - VDDD supply of SGTL5000 actually being reg_1v8_vio - TMP451 temperature sensor vcc supply being reg_module_3v3 - usb3-0 vbus supply being reg_usbh_vbus - usb3-1 vbus supply being reg_usbo1_vbus - carrier board HDMI supply being reg_5v0 - carrier board sata target 5v supply being reg_5v0 - carrier board sata target 12v supply being reg_12v0 - carrier board reg_3v3 actually being backlight power supply Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124-apalis-eval.dts | 18 ++++++++++++++++++ arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts | 18 ++++++++++++++++++ arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi | 14 +++++++++++++- arch/arm/boot/dts/tegra124-apalis.dtsi | 14 +++++++++++++- 4 files changed, 62 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/tegra124-apalis-eval.dts b/arch/arm/boot/dts/tegra124-apalis-eval.dts index a6ad759dddb4..c2e918d345de 100644 --- a/arch/arm/boot/dts/tegra124-apalis-eval.dts +++ b/arch/arm/boot/dts/tegra124-apalis-eval.dts @@ -72,6 +72,7 @@ host1x@50000000 { hdmi@54280000 { status = "okay"; + hdmi-supply = <®_5v0>; }; }; @@ -164,6 +165,8 @@ /* Apalis Serial ATA */ sata@70020000 { status = "okay"; + target-5v-supply = <®_5v0>; + target-12v-supply = <®_12v0>; }; hda@70030000 { @@ -230,6 +233,7 @@ default-brightness-level = <6>; /* BKL1_ON */ enable-gpios = <&gpio TEGRA_GPIO(BB, 5) GPIO_ACTIVE_HIGH>; + power-supply = <®_3v3>; }; gpio-keys { @@ -244,6 +248,13 @@ }; }; + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3.3V_SW"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + reg_5v0: regulator-5v0 { compatible = "regulator-fixed"; regulator-name = "5V_SW"; @@ -251,6 +262,13 @@ regulator-max-microvolt = <5000000>; }; + reg_12v0: regulator-12v0 { + compatible = "regulator-fixed"; + regulator-name = "12V_SW"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + /* USBO1_EN */ reg_usbo1_vbus: regulator-usbo1-vbus { compatible = "regulator-fixed"; diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts b/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts index 8a8d5fa0ecd1..eebcc013771e 100644 --- a/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts +++ b/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts @@ -36,6 +36,7 @@ host1x@50000000 { hdmi@54280000 { status = "okay"; + hdmi-supply = <®_5v0>; }; }; @@ -129,6 +130,8 @@ /* Apalis Serial ATA */ sata@70020000 { status = "okay"; + target-5v-supply = <®_5v0>; + target-12v-supply = <®_12v0>; }; hda@70030000 { @@ -195,6 +198,7 @@ default-brightness-level = <6>; /* BKL1_ON */ enable-gpios = <&gpio TEGRA_GPIO(BB, 5) GPIO_ACTIVE_HIGH>; + power-supply = <®_3v3>; }; gpio-keys { @@ -209,6 +213,13 @@ }; }; + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3.3V_SW"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + reg_5v0: regulator-5v0 { compatible = "regulator-fixed"; regulator-name = "5V_SW"; @@ -216,6 +227,13 @@ regulator-max-microvolt = <5000000>; }; + reg_12v0: regulator-12v0 { + compatible = "regulator-fixed"; + regulator-name = "12V_SW"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + /* USBO1_EN */ reg_usbo1_vbus: regulator-usbo1-vbus { compatible = "regulator-fixed"; diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi index 13aa8c797d42..00d5308c993f 100644 --- a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi @@ -1565,7 +1565,8 @@ sgtl5000: codec@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; - VDDA-supply = <®_module_3v3>; + VDDA-supply = <®_module_3v3_audio>; + VDDD-supply = <®_1v8_vddio>; VDDIO-supply = <®_1v8_vddio>; clocks = <&tegra_car TEGRA124_CLK_EXTERN1>; }; @@ -1754,6 +1755,7 @@ interrupt-parent = <&gpio>; interrupts = ; #thermal-sensor-cells = <1>; + vcc-supply = <®_module_3v3>; }; }; @@ -1902,11 +1904,13 @@ usb3-0 { status = "okay"; nvidia,usb2-companion = <2>; + vbus-supply = <®_usbh_vbus>; }; usb3-1 { status = "okay"; nvidia,usb2-companion = <0>; + vbus-supply = <®_usbo1_vbus>; }; }; }; @@ -1989,6 +1993,14 @@ vin-supply = <®_3v3_mxm>; }; + reg_module_3v3_audio: regulator-module-3v3-audio { + compatible = "regulator-fixed"; + regulator-name = "+V3.3_AUDIO_AVDD_S"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + sound { compatible = "toradex,tegra-audio-sgtl5000-apalis_tk1", "nvidia,tegra-audio-sgtl5000"; diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/tegra124-apalis.dtsi index 40c6ca2d1385..65a88d314fd2 100644 --- a/arch/arm/boot/dts/tegra124-apalis.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis.dtsi @@ -1594,7 +1594,8 @@ sgtl5000: codec@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; - VDDA-supply = <®_module_3v3>; + VDDA-supply = <®_module_3v3_audio>; + VDDD-supply = <®_1v8_vddio>; VDDIO-supply = <®_1v8_vddio>; clocks = <&tegra_car TEGRA124_CLK_EXTERN1>; }; @@ -1783,6 +1784,7 @@ interrupt-parent = <&gpio>; interrupts = ; #thermal-sensor-cells = <1>; + vcc-supply = <®_module_3v3>; }; }; @@ -1931,11 +1933,13 @@ usb3-0 { status = "okay"; nvidia,usb2-companion = <2>; + vbus-supply = <®_usbh_vbus>; }; usb3-1 { status = "okay"; nvidia,usb2-companion = <0>; + vbus-supply = <®_usbo1_vbus>; }; }; }; @@ -2018,6 +2022,14 @@ vin-supply = <®_3v3_mxm>; }; + reg_module_3v3_audio: regulator-module-3v3-audio { + compatible = "regulator-fixed"; + regulator-name = "+V3.3_AUDIO_AVDD_S"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + sound { compatible = "toradex,tegra-audio-sgtl5000-apalis_tk1", "nvidia,tegra-audio-sgtl5000"; -- cgit v1.2.2 From 35a2473f6dc89ee39ab30fa1a6b160e5a5d8142a Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sat, 1 Sep 2018 15:04:51 +0200 Subject: ARM: tegra: apalis-tk1: drop unused pinmux label Drop unused pinmux label. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi | 2 +- arch/arm/boot/dts/tegra124-apalis.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi index 00d5308c993f..aaedc83a11bc 100644 --- a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi @@ -68,7 +68,7 @@ vdd-supply = <®_vdd_gpu>; }; - pinmux: pinmux@70000868 { + pinmux@70000868 { pinctrl-names = "default"; pinctrl-0 = <&state_default>; diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/tegra124-apalis.dtsi index 65a88d314fd2..208411692bdc 100644 --- a/arch/arm/boot/dts/tegra124-apalis.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis.dtsi @@ -103,7 +103,7 @@ vdd-supply = <®_vdd_gpu>; }; - pinmux: pinmux@70000868 { + pinmux@70000868 { pinctrl-names = "default"; pinctrl-0 = <&state_default>; -- cgit v1.2.2 From 138ce63521597c69f71b03950d97c7ee727ec5ea Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sat, 1 Sep 2018 15:04:52 +0200 Subject: ARM: tegra: apalis-tk1: white-space clean-up White-space clean-up. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi | 3 --- arch/arm/boot/dts/tegra124-apalis.dtsi | 3 --- 2 files changed, 6 deletions(-) diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi index aaedc83a11bc..14114bc43e38 100644 --- a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi @@ -1881,7 +1881,6 @@ usb2-0 { status = "okay"; mode = "otg"; - vbus-supply = <®_usbo1_vbus>; }; @@ -1889,7 +1888,6 @@ usb2-1 { status = "okay"; mode = "host"; - vbus-supply = <®_usbh_vbus>; }; @@ -1897,7 +1895,6 @@ usb2-2 { status = "okay"; mode = "host"; - vbus-supply = <®_usbh_vbus>; }; diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/tegra124-apalis.dtsi index 208411692bdc..955adebc9e90 100644 --- a/arch/arm/boot/dts/tegra124-apalis.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis.dtsi @@ -1910,7 +1910,6 @@ usb2-0 { status = "okay"; mode = "otg"; - vbus-supply = <®_usbo1_vbus>; }; @@ -1918,7 +1917,6 @@ usb2-1 { status = "okay"; mode = "host"; - vbus-supply = <®_usbh_vbus>; }; @@ -1926,7 +1924,6 @@ usb2-2 { status = "okay"; mode = "host"; - vbus-supply = <®_usbh_vbus>; }; -- cgit v1.2.2 From 958b767d683a8ee77dbed5c19d79818fb15dffe9 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sat, 1 Sep 2018 15:04:53 +0200 Subject: ARM: tegra: apalis-tk1: reorder backlight properties Reorder backlight properties. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124-apalis-eval.dts | 2 +- arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/tegra124-apalis-eval.dts b/arch/arm/boot/dts/tegra124-apalis-eval.dts index c2e918d345de..d9805fc97f5e 100644 --- a/arch/arm/boot/dts/tegra124-apalis-eval.dts +++ b/arch/arm/boot/dts/tegra124-apalis-eval.dts @@ -228,12 +228,12 @@ backlight: backlight { compatible = "pwm-backlight"; - pwms = <&pwm 3 5000000>; /* BKL1_PWM */ brightness-levels = <255 231 223 207 191 159 127 0>; default-brightness-level = <6>; /* BKL1_ON */ enable-gpios = <&gpio TEGRA_GPIO(BB, 5) GPIO_ACTIVE_HIGH>; power-supply = <®_3v3>; + pwms = <&pwm 3 5000000>; /* BKL1_PWM */ }; gpio-keys { diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts b/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts index eebcc013771e..aafaf2c3e195 100644 --- a/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts +++ b/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts @@ -193,12 +193,12 @@ backlight: backlight { compatible = "pwm-backlight"; - pwms = <&pwm 3 5000000>; /* BKL1_PWM */ brightness-levels = <255 231 223 207 191 159 127 0>; default-brightness-level = <6>; /* BKL1_ON */ enable-gpios = <&gpio TEGRA_GPIO(BB, 5) GPIO_ACTIVE_HIGH>; power-supply = <®_3v3>; + pwms = <&pwm 3 5000000>; /* BKL1_PWM */ }; gpio-keys { -- cgit v1.2.2 From fca051b02a57c6cf9f58e83140aaf00e19c74e92 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sat, 1 Sep 2018 15:04:54 +0200 Subject: ARM: tegra: apalis-tk1: add proper emmc vmmc and vqmmc supplies Add proper eMMC vmmc and vqmmc supplies e.g. fixing signalling voltage. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi | 2 ++ arch/arm/boot/dts/tegra124-apalis.dtsi | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi index 14114bc43e38..3408317c0f00 100644 --- a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi @@ -1917,6 +1917,8 @@ status = "okay"; bus-width = <8>; non-removable; + vmmc-supply = <®_module_3v3>; /* VCC */ + vqmmc-supply = <®_1v8_vddio>; /* VCCQ */ }; /* CPU DFLL clock */ diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/tegra124-apalis.dtsi index 955adebc9e90..ba6fc2e51b2d 100644 --- a/arch/arm/boot/dts/tegra124-apalis.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis.dtsi @@ -1946,6 +1946,8 @@ status = "okay"; bus-width = <8>; non-removable; + vmmc-supply = <®_module_3v3>; /* VCC */ + vqmmc-supply = <®_1v8_vddio>; /* VCCQ */ }; /* CPU DFLL clock */ -- cgit v1.2.2 From 8be6e49a653ca79dcae1125238f78db590d86622 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sat, 1 Sep 2018 15:04:55 +0200 Subject: ARM: tegra: apalis-tk1: enable emmc ddr52 mode Add mmc-ddr-1_8v property enabling eMMC DDR52 mode. root@apalis-tk1-mainline:~# cat /sys/kernel/debug/mmc2/ios clock: 52000000 Hz actual clock: 52000000 Hz vdd: 21 (3.3 ~ 3.4 V) bus mode: 2 (push-pull) chip select: 0 (don't care) power mode: 2 (on) bus width: 3 (8 bits) timing spec: 8 (mmc DDR52) signal voltage: 1 (1.80 V) driver type: 0 (driver type B) root@apalis-tk1-mainline:~# hdparm -t /dev/mmcblk2 /dev/mmcblk2: Timing buffered disk reads: 256 MB in 3.02 seconds = 84.83 MB/sec Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi | 1 + arch/arm/boot/dts/tegra124-apalis.dtsi | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi index 3408317c0f00..37e443e21ce6 100644 --- a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi @@ -1919,6 +1919,7 @@ non-removable; vmmc-supply = <®_module_3v3>; /* VCC */ vqmmc-supply = <®_1v8_vddio>; /* VCCQ */ + mmc-ddr-1_8v; }; /* CPU DFLL clock */ diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/tegra124-apalis.dtsi index ba6fc2e51b2d..f76580f6cc80 100644 --- a/arch/arm/boot/dts/tegra124-apalis.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis.dtsi @@ -1948,6 +1948,7 @@ non-removable; vmmc-supply = <®_module_3v3>; /* VCC */ vqmmc-supply = <®_1v8_vddio>; /* VCCQ */ + mmc-ddr-1_8v; }; /* CPU DFLL clock */ -- cgit v1.2.2 From a052d2b67f00dfc6181d7dea6ff911bc7175f52a Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sat, 1 Sep 2018 15:04:56 +0200 Subject: ARM: tegra: apalis-tk1: add toradex, apalis-tk1-v1.2 compatible Add toradex,apalis-tk1-v1.2 compatible. Signed-off-by: Marcel Ziswiler Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/arm/tegra.txt | 2 ++ arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts | 3 ++- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/arm/tegra.txt b/Documentation/devicetree/bindings/arm/tegra.txt index 1073a5e66122..1c90cb32da19 100644 --- a/Documentation/devicetree/bindings/arm/tegra.txt +++ b/Documentation/devicetree/bindings/arm/tegra.txt @@ -51,6 +51,8 @@ board-specific compatible values: toradex,apalis_t30-v1.1-eval toradex,apalis-tk1 toradex,apalis-tk1-eval + toradex,apalis-tk1-v1.2 + toradex,apalis-tk1-v1.2-eval toradex,colibri_t20-512 toradex,colibri_t30 toradex,colibri_t30-eval-v3 diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts b/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts index aafaf2c3e195..89783fe76f65 100644 --- a/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts +++ b/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts @@ -11,7 +11,8 @@ / { model = "Toradex Apalis TK1 on Apalis Evaluation Board"; compatible = "toradex,apalis-tk1-v1.2-eval", "toradex,apalis-tk1-eval", - "toradex,apalis-tk1", "nvidia,tegra124"; + "toradex,apalis-tk1-v1.2", "toradex,apalis-tk1", + "nvidia,tegra124"; aliases { rtc0 = "/i2c@7000c000/rtc@68"; -- cgit v1.2.2 From e0cffa9a1b64099f537887712ba3802f92429675 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sat, 1 Sep 2018 15:04:57 +0200 Subject: ARM: tegra: apalis-tk1: reorder cpu dfll clock properties Reorder CPU DFLL clock properties. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi | 2 +- arch/arm/boot/dts/tegra124-apalis.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi index 37e443e21ce6..07dd208296d3 100644 --- a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi @@ -1925,8 +1925,8 @@ /* CPU DFLL clock */ clock@70110000 { status = "okay"; - vdd-cpu-supply = <®_vdd_cpu>; nvidia,i2c-fs-rate = <400000>; + vdd-cpu-supply = <®_vdd_cpu>; }; ahub@70300000 { diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/tegra124-apalis.dtsi index f76580f6cc80..fe10c5180768 100644 --- a/arch/arm/boot/dts/tegra124-apalis.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis.dtsi @@ -1954,8 +1954,8 @@ /* CPU DFLL clock */ clock@70110000 { status = "okay"; - vdd-cpu-supply = <®_vdd_cpu>; nvidia,i2c-fs-rate = <400000>; + vdd-cpu-supply = <®_vdd_cpu>; }; ahub@70300000 { -- cgit v1.2.2 From a64b51a3ed5bcd89eb948e0b3ea60d1eb4266370 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sat, 1 Sep 2018 15:04:58 +0200 Subject: ARM: tegra: apalis-tk1: reorder SD card properties Reorder SD card properties. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124-apalis-eval.dts | 4 ++-- arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/tegra124-apalis-eval.dts b/arch/arm/boot/dts/tegra124-apalis-eval.dts index d9805fc97f5e..08f60636441d 100644 --- a/arch/arm/boot/dts/tegra124-apalis-eval.dts +++ b/arch/arm/boot/dts/tegra124-apalis-eval.dts @@ -180,18 +180,18 @@ /* Apalis MMC1 */ sdhci@700b0000 { status = "okay"; + bus-width = <4>; /* MMC1_CD# */ cd-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>; - bus-width = <4>; vqmmc-supply = <&vddio_sdmmc1>; }; /* Apalis SD1 */ sdhci@700b0400 { status = "okay"; + bus-width = <4>; /* SD1_CD# */ cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; - bus-width = <4>; vqmmc-supply = <&vddio_sdmmc3>; }; diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts b/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts index 89783fe76f65..97c56e82c51d 100644 --- a/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts +++ b/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts @@ -146,18 +146,18 @@ /* Apalis MMC1 */ sdhci@700b0000 { status = "okay"; + bus-width = <4>; /* MMC1_CD# */ cd-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>; - bus-width = <4>; vqmmc-supply = <&vddio_sdmmc1>; }; /* Apalis SD1 */ sdhci@700b0400 { status = "okay"; + bus-width = <4>; /* SD1_CD# */ cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; - bus-width = <4>; vqmmc-supply = <&vddio_sdmmc3>; }; -- cgit v1.2.2 From 43ff75a8e3ed39f05d83a4938731d876d4ed36a1 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sat, 1 Sep 2018 15:04:59 +0200 Subject: ARM: tegra: apalis-tk1: drop module level model and compatible Drop model and compatible nodes from the module level device tree as they get overridden by the carrier board device tree anyway. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi | 4 ---- arch/arm/boot/dts/tegra124-apalis.dtsi | 3 --- 2 files changed, 7 deletions(-) diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi index 07dd208296d3..e70994518c70 100644 --- a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi @@ -11,10 +11,6 @@ * Compatible for Revisions 2GB: V1.2A */ / { - model = "Toradex Apalis TK1"; - compatible = "toradex,apalis-tk1-v1.2", "toradex,apalis-tk1", - "nvidia,tegra124"; - memory@80000000 { reg = <0x0 0x80000000 0x0 0x80000000>; }; diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/tegra124-apalis.dtsi index fe10c5180768..b1a05c37106d 100644 --- a/arch/arm/boot/dts/tegra124-apalis.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis.dtsi @@ -47,9 +47,6 @@ * Compatible for Revisions 2GB: V1.0A, V1.0B, V1.1A */ / { - model = "Toradex Apalis TK1"; - compatible = "toradex,apalis-tk1", "nvidia,tegra124"; - memory@80000000 { reg = <0x0 0x80000000 0x0 0x80000000>; }; -- cgit v1.2.2 From 4802623981d9f00b5a9428dc18687376ad0544ed Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sat, 1 Sep 2018 15:05:00 +0200 Subject: ARM: tegra: apalis-tk1: drop obsolete spidev nodes Drop obsolete spidev device tree nodes as nowadays one should do this by binding the spidev driver to specific instances/chip selects at runtime. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124-apalis-eval.dts | 12 ------------ arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts | 12 ------------ 2 files changed, 24 deletions(-) diff --git a/arch/arm/boot/dts/tegra124-apalis-eval.dts b/arch/arm/boot/dts/tegra124-apalis-eval.dts index 08f60636441d..2710eb79b63e 100644 --- a/arch/arm/boot/dts/tegra124-apalis-eval.dts +++ b/arch/arm/boot/dts/tegra124-apalis-eval.dts @@ -142,24 +142,12 @@ spi@7000d400 { status = "okay"; spi-max-frequency = <50000000>; - - spidev0: spidev@0 { - compatible = "spidev"; - reg = <0>; - spi-max-frequency = <50000000>; - }; }; /* SPI4: Apalis SPI2 */ spi@7000da00 { status = "okay"; spi-max-frequency = <50000000>; - - spidev1: spidev@0 { - compatible = "spidev"; - reg = <0>; - spi-max-frequency = <50000000>; - }; }; /* Apalis Serial ATA */ diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts b/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts index 97c56e82c51d..574780250031 100644 --- a/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts +++ b/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts @@ -108,24 +108,12 @@ spi@7000d400 { status = "okay"; spi-max-frequency = <50000000>; - - spidev0: spidev@0 { - compatible = "spidev"; - reg = <0>; - spi-max-frequency = <50000000>; - }; }; /* SPI4: Apalis SPI2 */ spi@7000da00 { status = "okay"; spi-max-frequency = <50000000>; - - spidev1: spidev@0 { - compatible = "spidev"; - reg = <0>; - spi-max-frequency = <50000000>; - }; }; /* Apalis Serial ATA */ -- cgit v1.2.2 From 26e19cdf665f0998d30275877a7d5a14f908aa02 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sat, 1 Sep 2018 15:05:01 +0200 Subject: ARM: tegra: apalis-tk1: replace underscores in node names with dashes As underscores in node names are not recommended replace them all where possible with dashes. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124-apalis-eval.dts | 2 +- arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts | 2 +- arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi | 290 ++++++++++++------------ arch/arm/boot/dts/tegra124-apalis.dtsi | 290 ++++++++++++------------ 4 files changed, 292 insertions(+), 292 deletions(-) diff --git a/arch/arm/boot/dts/tegra124-apalis-eval.dts b/arch/arm/boot/dts/tegra124-apalis-eval.dts index 2710eb79b63e..0b4ac640e54f 100644 --- a/arch/arm/boot/dts/tegra124-apalis-eval.dts +++ b/arch/arm/boot/dts/tegra124-apalis-eval.dts @@ -282,7 +282,7 @@ &gpio { /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */ - pex_perst_n { + pex-perst-n { gpio-hog; gpios = ; output-high; diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts b/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts index 574780250031..799382d04bba 100644 --- a/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts +++ b/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts @@ -248,7 +248,7 @@ &gpio { /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */ - pex_perst_n { + pex-perst-n { gpio-hog; gpios = ; output-high; diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi index e70994518c70..6d36521448ce 100644 --- a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi @@ -70,35 +70,35 @@ state_default: pinmux { /* Analogue Audio (On-module) */ - dap3_fs_pp0 { + dap3-fs-pp0 { nvidia,pins = "dap3_fs_pp0"; nvidia,function = "i2s2"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - dap3_din_pp1 { + dap3-din-pp1 { nvidia,pins = "dap3_din_pp1"; nvidia,function = "i2s2"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - dap3_dout_pp2 { + dap3-dout-pp2 { nvidia,pins = "dap3_dout_pp2"; nvidia,function = "i2s2"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - dap3_sclk_pp3 { + dap3-sclk-pp3 { nvidia,pins = "dap3_sclk_pp3"; nvidia,function = "i2s2"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - dap_mclk1_pw4 { + dap-mclk1-pw4 { nvidia,pins = "dap_mclk1_pw4"; nvidia,function = "extperiph1"; nvidia,pull = ; @@ -125,7 +125,7 @@ }; /* Apalis CAM1_MCLK */ - cam_mclk_pcc0 { + cam-mclk-pcc0 { nvidia,pins = "cam_mclk_pcc0"; nvidia,function = "vi_alt3"; nvidia,pull = ; @@ -134,28 +134,28 @@ }; /* Apalis Digital Audio */ - dap2_fs_pa2 { + dap2-fs-pa2 { nvidia,pins = "dap2_fs_pa2"; nvidia,function = "hda"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - dap2_sclk_pa3 { + dap2-sclk-pa3 { nvidia,pins = "dap2_sclk_pa3"; nvidia,function = "hda"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - dap2_din_pa4 { + dap2-din-pa4 { nvidia,pins = "dap2_din_pa4"; nvidia,function = "hda"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - dap2_dout_pa5 { + dap2-dout-pa5 { nvidia,pins = "dap2_dout_pa5"; nvidia,function = "hda"; nvidia,pull = ; @@ -168,7 +168,7 @@ nvidia,tristate = ; nvidia,enable-input = ; }; - clk3_out_pee0 { + clk3-out-pee0 { nvidia,pins = "clk3_out_pee0"; nvidia,function = "extperiph3"; nvidia,pull = ; @@ -177,7 +177,7 @@ }; /* Apalis GPIO */ - usb_vbus_en0_pn4 { + usb-vbus-en0-pn4 { nvidia,pins = "usb_vbus_en0_pn4"; nvidia,function = "rsvd2"; nvidia,pull = ; @@ -185,7 +185,7 @@ nvidia,enable-input = ; nvidia,open-drain = ; }; - usb_vbus_en1_pn5 { + usb-vbus-en1-pn5 { nvidia,pins = "usb_vbus_en1_pn5"; nvidia,function = "rsvd2"; nvidia,pull = ; @@ -193,35 +193,35 @@ nvidia,enable-input = ; nvidia,open-drain = ; }; - pex_l0_rst_n_pdd1 { + pex-l0-rst-n-pdd1 { nvidia,pins = "pex_l0_rst_n_pdd1"; nvidia,function = "rsvd2"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - pex_l0_clkreq_n_pdd2 { + pex-l0-clkreq-n-pdd2 { nvidia,pins = "pex_l0_clkreq_n_pdd2"; nvidia,function = "rsvd2"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - pex_l1_rst_n_pdd5 { + pex-l1-rst-n-pdd5 { nvidia,pins = "pex_l1_rst_n_pdd5"; nvidia,function = "rsvd2"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - pex_l1_clkreq_n_pdd6 { + pex-l1-clkreq-n-pdd6 { nvidia,pins = "pex_l1_clkreq_n_pdd6"; nvidia,function = "rsvd2"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - dp_hpd_pff0 { + dp-hpd-pff0 { nvidia,pins = "dp_hpd_pff0"; nvidia,function = "dp"; nvidia,pull = ; @@ -245,7 +245,7 @@ }; /* Apalis HDMI1_CEC */ - hdmi_cec_pee3 { + hdmi-cec-pee3 { nvidia,pins = "hdmi_cec_pee3"; nvidia,function = "cec"; nvidia,pull = ; @@ -255,7 +255,7 @@ }; /* Apalis HDMI1_HPD */ - hdmi_int_pn7 { + hdmi-int-pn7 { nvidia,pins = "hdmi_int_pn7"; nvidia,function = "rsvd1"; nvidia,pull = ; @@ -265,7 +265,7 @@ }; /* Apalis I2C1 */ - gen1_i2c_scl_pc4 { + gen1-i2c-scl-pc4 { nvidia,pins = "gen1_i2c_scl_pc4"; nvidia,function = "i2c1"; nvidia,pull = ; @@ -273,7 +273,7 @@ nvidia,enable-input = ; nvidia,open-drain = ; }; - gen1_i2c_sda_pc5 { + gen1-i2c-sda-pc5 { nvidia,pins = "gen1_i2c_sda_pc5"; nvidia,function = "i2c1"; nvidia,pull = ; @@ -283,7 +283,7 @@ }; /* Apalis I2C3 (CAM) */ - cam_i2c_scl_pbb1 { + cam-i2c-scl-pbb1 { nvidia,pins = "cam_i2c_scl_pbb1"; nvidia,function = "i2c3"; nvidia,pull = ; @@ -291,7 +291,7 @@ nvidia,enable-input = ; nvidia,open-drain = ; }; - cam_i2c_sda_pbb2 { + cam-i2c-sda-pbb2 { nvidia,pins = "cam_i2c_sda_pbb2"; nvidia,function = "i2c3"; nvidia,pull = ; @@ -301,7 +301,7 @@ }; /* Apalis I2C4 (DDC) */ - ddc_scl_pv4 { + ddc-scl-pv4 { nvidia,pins = "ddc_scl_pv4"; nvidia,function = "i2c4"; nvidia,pull = ; @@ -309,7 +309,7 @@ nvidia,enable-input = ; nvidia,rcv-sel = ; }; - ddc_sda_pv5 { + ddc-sda-pv5 { nvidia,pins = "ddc_sda_pv5"; nvidia,function = "i2c4"; nvidia,pull = ; @@ -319,77 +319,77 @@ }; /* Apalis MMC1 */ - sdmmc1_cd_n_pv3 { /* CD# GPIO */ + sdmmc1-cd-n-pv3 { /* CD# GPIO */ nvidia,pins = "sdmmc1_wp_n_pv3"; nvidia,function = "sdmmc1"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - clk2_out_pw5 { /* D5 GPIO */ + clk2-out-pw5 { /* D5 GPIO */ nvidia,pins = "clk2_out_pw5"; nvidia,function = "rsvd2"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - sdmmc1_dat3_py4 { + sdmmc1-dat3-py4 { nvidia,pins = "sdmmc1_dat3_py4"; nvidia,function = "sdmmc1"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - sdmmc1_dat2_py5 { + sdmmc1-dat2-py5 { nvidia,pins = "sdmmc1_dat2_py5"; nvidia,function = "sdmmc1"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - sdmmc1_dat1_py6 { + sdmmc1-dat1-py6 { nvidia,pins = "sdmmc1_dat1_py6"; nvidia,function = "sdmmc1"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - sdmmc1_dat0_py7 { + sdmmc1-dat0-py7 { nvidia,pins = "sdmmc1_dat0_py7"; nvidia,function = "sdmmc1"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - sdmmc1_clk_pz0 { + sdmmc1-clk-pz0 { nvidia,pins = "sdmmc1_clk_pz0"; nvidia,function = "sdmmc1"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - sdmmc1_cmd_pz1 { + sdmmc1-cmd-pz1 { nvidia,pins = "sdmmc1_cmd_pz1"; nvidia,function = "sdmmc1"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - clk2_req_pcc5 { /* D4 GPIO */ + clk2-req-pcc5 { /* D4 GPIO */ nvidia,pins = "clk2_req_pcc5"; nvidia,function = "rsvd2"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - sdmmc3_clk_lb_in_pee5 { /* D6 GPIO */ + sdmmc3-clk-lb-in-pee5 { /* D6 GPIO */ nvidia,pins = "sdmmc3_clk_lb_in_pee5"; nvidia,function = "rsvd2"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - usb_vbus_en2_pff1 { /* D7 GPIO */ + usb-vbus-en2-pff1 { /* D7 GPIO */ nvidia,pins = "usb_vbus_en2_pff1"; nvidia,function = "rsvd2"; nvidia,pull = ; @@ -429,7 +429,7 @@ }; /* Apalis SATA1_ACT# */ - dap1_dout_pn2 { + dap1-dout-pn2 { nvidia,pins = "dap1_dout_pn2"; nvidia,function = "gmi"; nvidia,pull = ; @@ -438,49 +438,49 @@ }; /* Apalis SD1 */ - sdmmc3_clk_pa6 { + sdmmc3-clk-pa6 { nvidia,pins = "sdmmc3_clk_pa6"; nvidia,function = "sdmmc3"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - sdmmc3_cmd_pa7 { + sdmmc3-cmd-pa7 { nvidia,pins = "sdmmc3_cmd_pa7"; nvidia,function = "sdmmc3"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - sdmmc3_dat3_pb4 { + sdmmc3-dat3-pb4 { nvidia,pins = "sdmmc3_dat3_pb4"; nvidia,function = "sdmmc3"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - sdmmc3_dat2_pb5 { + sdmmc3-dat2-pb5 { nvidia,pins = "sdmmc3_dat2_pb5"; nvidia,function = "sdmmc3"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - sdmmc3_dat1_pb6 { + sdmmc3-dat1-pb6 { nvidia,pins = "sdmmc3_dat1_pb6"; nvidia,function = "sdmmc3"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - sdmmc3_dat0_pb7 { + sdmmc3-dat0-pb7 { nvidia,pins = "sdmmc3_dat0_pb7"; nvidia,function = "sdmmc3"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - sdmmc3_cd_n_pv2 { /* CD# GPIO */ + sdmmc3-cd-n-pv2 { /* CD# GPIO */ nvidia,pins = "sdmmc3_cd_n_pv2"; nvidia,function = "rsvd3"; nvidia,pull = ; @@ -489,14 +489,14 @@ }; /* Apalis SPDIF */ - spdif_out_pk5 { + spdif-out-pk5 { nvidia,pins = "spdif_out_pk5"; nvidia,function = "spdif"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - spdif_in_pk6 { + spdif-in-pk6 { nvidia,pins = "spdif_in_pk6"; nvidia,function = "spdif"; nvidia,pull = ; @@ -505,28 +505,28 @@ }; /* Apalis SPI1 */ - ulpi_clk_py0 { + ulpi-clk-py0 { nvidia,pins = "ulpi_clk_py0"; nvidia,function = "spi1"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - ulpi_dir_py1 { + ulpi-dir-py1 { nvidia,pins = "ulpi_dir_py1"; nvidia,function = "spi1"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - ulpi_nxt_py2 { + ulpi-nxt-py2 { nvidia,pins = "ulpi_nxt_py2"; nvidia,function = "spi1"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - ulpi_stp_py3 { + ulpi-stp-py3 { nvidia,pins = "ulpi_stp_py3"; nvidia,function = "spi1"; nvidia,pull = ; @@ -579,42 +579,42 @@ nvidia,tristate = ; nvidia,enable-input = ; }; - uart1_txd_pu0 { + uart1-txd-pu0 { nvidia,pins = "pu0"; nvidia,function = "uarta"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - uart1_rxd_pu1 { + uart1-rxd-pu1 { nvidia,pins = "pu1"; nvidia,function = "uarta"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - uart1_cts_n_pu2 { + uart1-cts-n-pu2 { nvidia,pins = "pu2"; nvidia,function = "uarta"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - uart1_rts_n_pu3 { + uart1-rts-n-pu3 { nvidia,pins = "pu3"; nvidia,function = "uarta"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - uart3_cts_n_pa1 { /* DSR GPIO */ + uart3-cts-n-pa1 { /* DSR GPIO */ nvidia,pins = "uart3_cts_n_pa1"; nvidia,function = "gmi"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - uart3_rts_n_pc0 { /* DTR GPIO */ + uart3-rts-n-pc0 { /* DTR GPIO */ nvidia,pins = "uart3_rts_n_pc0"; nvidia,function = "gmi"; nvidia,pull = ; @@ -623,28 +623,28 @@ }; /* Apalis UART2 */ - uart2_txd_pc2 { + uart2-txd-pc2 { nvidia,pins = "uart2_txd_pc2"; nvidia,function = "irda"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - uart2_rxd_pc3 { + uart2-rxd-pc3 { nvidia,pins = "uart2_rxd_pc3"; nvidia,function = "irda"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - uart2_cts_n_pj5 { + uart2-cts-n-pj5 { nvidia,pins = "uart2_cts_n_pj5"; nvidia,function = "uartb"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - uart2_rts_n_pj6 { + uart2-rts-n-pj6 { nvidia,pins = "uart2_rts_n_pj6"; nvidia,function = "uartb"; nvidia,pull = ; @@ -653,14 +653,14 @@ }; /* Apalis UART3 */ - uart3_txd_pw6 { + uart3-txd-pw6 { nvidia,pins = "uart3_txd_pw6"; nvidia,function = "uartc"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - uart3_rxd_pw7 { + uart3-rxd-pw7 { nvidia,pins = "uart3_rxd_pw7"; nvidia,function = "uartc"; nvidia,pull = ; @@ -669,14 +669,14 @@ }; /* Apalis UART4 */ - uart4_rxd_pb0 { + uart4-rxd-pb0 { nvidia,pins = "pb0"; nvidia,function = "uartd"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - uart4_txd_pj7 { + uart4-txd-pj7 { nvidia,pins = "pj7"; nvidia,function = "uartd"; nvidia,pull = ; @@ -685,7 +685,7 @@ }; /* Apalis USBH_EN */ - gen2_i2c_sda_pt6 { + gen2-i2c-sda-pt6 { nvidia,pins = "gen2_i2c_sda_pt6"; nvidia,function = "rsvd2"; nvidia,pull = ; @@ -704,7 +704,7 @@ }; /* Apalis USBO1_EN */ - gen2_i2c_scl_pt5 { + gen2-i2c-scl-pt5 { nvidia,pins = "gen2_i2c_scl_pt5"; nvidia,function = "rsvd2"; nvidia,pull = ; @@ -723,7 +723,7 @@ }; /* Apalis WAKE1_MICO */ - pex_wake_n_pdd3 { + pex-wake-n-pdd3 { nvidia,pins = "pex_wake_n_pdd3"; nvidia,function = "rsvd2"; nvidia,pull = ; @@ -732,7 +732,7 @@ }; /* CORE_PWR_REQ */ - core_pwr_req { + core-pwr-req { nvidia,pins = "core_pwr_req"; nvidia,function = "pwron"; nvidia,pull = ; @@ -741,7 +741,7 @@ }; /* CPU_PWR_REQ */ - cpu_pwr_req { + cpu-pwr-req { nvidia,pins = "cpu_pwr_req"; nvidia,function = "cpu"; nvidia,pull = ; @@ -750,14 +750,14 @@ }; /* DVFS */ - dvfs_pwm_px0 { + dvfs-pwm-px0 { nvidia,pins = "dvfs_pwm_px0"; nvidia,function = "cldvfs"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - dvfs_clk_px2 { + dvfs-clk-px2 { nvidia,pins = "dvfs_clk_px2"; nvidia,function = "cldvfs"; nvidia,pull = ; @@ -766,70 +766,70 @@ }; /* eMMC */ - sdmmc4_dat0_paa0 { + sdmmc4-dat0-paa0 { nvidia,pins = "sdmmc4_dat0_paa0"; nvidia,function = "sdmmc4"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - sdmmc4_dat1_paa1 { + sdmmc4-dat1-paa1 { nvidia,pins = "sdmmc4_dat1_paa1"; nvidia,function = "sdmmc4"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - sdmmc4_dat2_paa2 { + sdmmc4-dat2-paa2 { nvidia,pins = "sdmmc4_dat2_paa2"; nvidia,function = "sdmmc4"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - sdmmc4_dat3_paa3 { + sdmmc4-dat3-paa3 { nvidia,pins = "sdmmc4_dat3_paa3"; nvidia,function = "sdmmc4"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - sdmmc4_dat4_paa4 { + sdmmc4-dat4-paa4 { nvidia,pins = "sdmmc4_dat4_paa4"; nvidia,function = "sdmmc4"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - sdmmc4_dat5_paa5 { + sdmmc4-dat5-paa5 { nvidia,pins = "sdmmc4_dat5_paa5"; nvidia,function = "sdmmc4"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - sdmmc4_dat6_paa6 { + sdmmc4-dat6-paa6 { nvidia,pins = "sdmmc4_dat6_paa6"; nvidia,function = "sdmmc4"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - sdmmc4_dat7_paa7 { + sdmmc4-dat7-paa7 { nvidia,pins = "sdmmc4_dat7_paa7"; nvidia,function = "sdmmc4"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - sdmmc4_clk_pcc4 { + sdmmc4-clk-pcc4 { nvidia,pins = "sdmmc4_clk_pcc4"; nvidia,function = "sdmmc4"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - sdmmc4_cmd_pt7 { + sdmmc4-cmd-pt7 { nvidia,pins = "sdmmc4_cmd_pt7"; nvidia,function = "sdmmc4"; nvidia,pull = ; @@ -838,7 +838,7 @@ }; /* JTAG_RTCK */ - jtag_rtck { + jtag-rtck { nvidia,pins = "jtag_rtck"; nvidia,function = "rtck"; nvidia,pull = ; @@ -847,7 +847,7 @@ }; /* LAN_DEV_OFF# */ - ulpi_data5_po6 { + ulpi-data5-po6 { nvidia,pins = "ulpi_data5_po6"; nvidia,function = "ulpi"; nvidia,pull = ; @@ -856,7 +856,7 @@ }; /* LAN_RESET# */ - kb_row10_ps2 { + kb-row10-ps2 { nvidia,pins = "kb_row10_ps2"; nvidia,function = "rsvd2"; nvidia,pull = ; @@ -865,7 +865,7 @@ }; /* LAN_WAKE# */ - ulpi_data4_po5 { + ulpi-data4-po5 { nvidia,pins = "ulpi_data4_po5"; nvidia,function = "ulpi"; nvidia,pull = ; @@ -919,35 +919,35 @@ }; /* MCU SPI */ - gpio_x4_aud_px4 { + gpio-x4-aud-px4 { nvidia,pins = "gpio_x4_aud_px4"; nvidia,function = "spi2"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - gpio_x5_aud_px5 { + gpio-x5-aud-px5 { nvidia,pins = "gpio_x5_aud_px5"; nvidia,function = "spi2"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - gpio_x6_aud_px6 { /* MCU_CS */ + gpio-x6-aud-px6 { /* MCU_CS */ nvidia,pins = "gpio_x6_aud_px6"; nvidia,function = "spi2"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - gpio_x7_aud_px7 { + gpio-x7-aud-px7 { nvidia,pins = "gpio_x7_aud_px7"; nvidia,function = "spi2"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - gpio_w2_aud_pw2 { /* MCU_CSEZP */ + gpio-w2-aud-pw2 { /* MCU_CSEZP */ nvidia,pins = "gpio_w2_aud_pw2"; nvidia,function = "spi2"; nvidia,pull = ; @@ -956,7 +956,7 @@ }; /* PMIC_CLK_32K */ - clk_32k_in { + clk-32k-in { nvidia,pins = "clk_32k_in"; nvidia,function = "clk"; nvidia,pull = ; @@ -965,7 +965,7 @@ }; /* PMIC_CPU_OC_INT */ - clk_32k_out_pa0 { + clk-32k-out-pa0 { nvidia,pins = "clk_32k_out_pa0"; nvidia,function = "soc"; nvidia,pull = ; @@ -974,7 +974,7 @@ }; /* PWR_I2C */ - pwr_i2c_scl_pz6 { + pwr-i2c-scl-pz6 { nvidia,pins = "pwr_i2c_scl_pz6"; nvidia,function = "i2cpwr"; nvidia,pull = ; @@ -982,7 +982,7 @@ nvidia,enable-input = ; nvidia,open-drain = ; }; - pwr_i2c_sda_pz7 { + pwr-i2c-sda-pz7 { nvidia,pins = "pwr_i2c_sda_pz7"; nvidia,function = "i2cpwr"; nvidia,pull = ; @@ -992,7 +992,7 @@ }; /* PWR_INT_N */ - pwr_int_n { + pwr-int-n { nvidia,pins = "pwr_int_n"; nvidia,function = "pmi"; nvidia,pull = ; @@ -1010,7 +1010,7 @@ }; /* RESET_OUT_N */ - reset_out_n { + reset-out-n { nvidia,pins = "reset_out_n"; nvidia,function = "reset_out_n"; nvidia,pull = ; @@ -1019,14 +1019,14 @@ }; /* SHIFT_CTRL_DIR_IN */ - kb_row0_pr0 { + kb-row0-pr0 { nvidia,pins = "kb_row0_pr0"; nvidia,function = "rsvd2"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - kb_row1_pr1 { + kb-row1-pr1 { nvidia,pins = "kb_row1_pr1"; nvidia,function = "rsvd2"; nvidia,pull = ; @@ -1035,7 +1035,7 @@ }; /* Configure level-shifter as output for HDA */ - kb_row11_ps3 { + kb-row11-ps3 { nvidia,pins = "kb_row11_ps3"; nvidia,function = "rsvd2"; nvidia,pull = ; @@ -1044,21 +1044,21 @@ }; /* SHIFT_CTRL_DIR_OUT */ - kb_col5_pq5 { + kb-col5-pq5 { nvidia,pins = "kb_col5_pq5"; nvidia,function = "rsvd2"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - kb_col6_pq6 { + kb-col6-pq6 { nvidia,pins = "kb_col6_pq6"; nvidia,function = "rsvd2"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - kb_col7_pq7 { + kb-col7-pq7 { nvidia,pins = "kb_col7_pq7"; nvidia,function = "rsvd2"; nvidia,pull = ; @@ -1067,35 +1067,35 @@ }; /* SHIFT_CTRL_OE */ - kb_col0_pq0 { + kb-col0-pq0 { nvidia,pins = "kb_col0_pq0"; nvidia,function = "rsvd2"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - kb_col1_pq1 { + kb-col1-pq1 { nvidia,pins = "kb_col1_pq1"; nvidia,function = "rsvd2"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - kb_col2_pq2 { + kb-col2-pq2 { nvidia,pins = "kb_col2_pq2"; nvidia,function = "rsvd2"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - kb_col4_pq4 { + kb-col4-pq4 { nvidia,pins = "kb_col4_pq4"; nvidia,function = "kbc"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - kb_row2_pr2 { + kb-row2-pr2 { nvidia,pins = "kb_row2_pr2"; nvidia,function = "rsvd2"; nvidia,pull = ; @@ -1113,7 +1113,7 @@ }; /* TOUCH_INT */ - gpio_w3_aud_pw3 { + gpio-w3-aud-pw3 { nvidia,pins = "gpio_w3_aud_pw3"; nvidia,function = "spi6"; nvidia,pull = ; @@ -1254,189 +1254,189 @@ nvidia,tristate = ; nvidia,enable-input = ; }; - dap1_fs_pn0 { /* NC */ + dap1-fs-pn0 { /* NC */ nvidia,pins = "dap1_fs_pn0"; nvidia,function = "rsvd4"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - dap1_din_pn1 { /* NC */ + dap1-din-pn1 { /* NC */ nvidia,pins = "dap1_din_pn1"; nvidia,function = "rsvd4"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - dap1_sclk_pn3 { /* NC */ + dap1-sclk-pn3 { /* NC */ nvidia,pins = "dap1_sclk_pn3"; nvidia,function = "rsvd4"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - ulpi_data7_po0 { /* NC */ + ulpi-data7-po0 { /* NC */ nvidia,pins = "ulpi_data7_po0"; nvidia,function = "ulpi"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - ulpi_data0_po1 { /* NC */ + ulpi-data0-po1 { /* NC */ nvidia,pins = "ulpi_data0_po1"; nvidia,function = "ulpi"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - ulpi_data1_po2 { /* NC */ + ulpi-data1-po2 { /* NC */ nvidia,pins = "ulpi_data1_po2"; nvidia,function = "ulpi"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - ulpi_data2_po3 { /* NC */ + ulpi-data2-po3 { /* NC */ nvidia,pins = "ulpi_data2_po3"; nvidia,function = "ulpi"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - ulpi_data3_po4 { /* NC */ + ulpi-data3-po4 { /* NC */ nvidia,pins = "ulpi_data3_po4"; nvidia,function = "ulpi"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - ulpi_data6_po7 { /* NC */ + ulpi-data6-po7 { /* NC */ nvidia,pins = "ulpi_data6_po7"; nvidia,function = "ulpi"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - dap4_fs_pp4 { /* NC */ + dap4-fs-pp4 { /* NC */ nvidia,pins = "dap4_fs_pp4"; nvidia,function = "rsvd4"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - dap4_din_pp5 { /* NC */ + dap4-din-pp5 { /* NC */ nvidia,pins = "dap4_din_pp5"; nvidia,function = "rsvd3"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - dap4_dout_pp6 { /* NC */ + dap4-dout-pp6 { /* NC */ nvidia,pins = "dap4_dout_pp6"; nvidia,function = "rsvd4"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - dap4_sclk_pp7 { /* NC */ + dap4-sclk-pp7 { /* NC */ nvidia,pins = "dap4_sclk_pp7"; nvidia,function = "rsvd3"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - kb_col3_pq3 { /* NC */ + kb-col3-pq3 { /* NC */ nvidia,pins = "kb_col3_pq3"; nvidia,function = "kbc"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - kb_row3_pr3 { /* NC */ + kb-row3-pr3 { /* NC */ nvidia,pins = "kb_row3_pr3"; nvidia,function = "kbc"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - kb_row4_pr4 { /* NC */ + kb-row4-pr4 { /* NC */ nvidia,pins = "kb_row4_pr4"; nvidia,function = "rsvd3"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - kb_row5_pr5 { /* NC */ + kb-row5-pr5 { /* NC */ nvidia,pins = "kb_row5_pr5"; nvidia,function = "rsvd3"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - kb_row6_pr6 { /* NC */ + kb-row6-pr6 { /* NC */ nvidia,pins = "kb_row6_pr6"; nvidia,function = "kbc"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - kb_row7_pr7 { /* NC */ + kb-row7-pr7 { /* NC */ nvidia,pins = "kb_row7_pr7"; nvidia,function = "rsvd2"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - kb_row8_ps0 { /* NC */ + kb-row8-ps0 { /* NC */ nvidia,pins = "kb_row8_ps0"; nvidia,function = "rsvd2"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - kb_row9_ps1 { /* NC */ + kb-row9-ps1 { /* NC */ nvidia,pins = "kb_row9_ps1"; nvidia,function = "rsvd2"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - kb_row12_ps4 { /* NC */ + kb-row12-ps4 { /* NC */ nvidia,pins = "kb_row12_ps4"; nvidia,function = "rsvd2"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - kb_row13_ps5 { /* NC */ + kb-row13-ps5 { /* NC */ nvidia,pins = "kb_row13_ps5"; nvidia,function = "rsvd2"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - kb_row14_ps6 { /* NC */ + kb-row14-ps6 { /* NC */ nvidia,pins = "kb_row14_ps6"; nvidia,function = "rsvd2"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - kb_row15_ps7 { /* NC */ + kb-row15-ps7 { /* NC */ nvidia,pins = "kb_row15_ps7"; nvidia,function = "rsvd3"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - kb_row16_pt0 { /* NC */ + kb-row16-pt0 { /* NC */ nvidia,pins = "kb_row16_pt0"; nvidia,function = "rsvd2"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - kb_row17_pt1 { /* NC */ + kb-row17-pt1 { /* NC */ nvidia,pins = "kb_row17_pt1"; nvidia,function = "rsvd2"; nvidia,pull = ; @@ -1468,14 +1468,14 @@ nvidia,tristate = ; nvidia,enable-input = ; }; - gpio_x1_aud_px1 { /* NC */ + gpio-x1-aud-px1 { /* NC */ nvidia,pins = "gpio_x1_aud_px1"; nvidia,function = "rsvd2"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - gpio_x3_aud_px3 { /* NC */ + gpio-x3-aud-px3 { /* NC */ nvidia,pins = "gpio_x3_aud_px3"; nvidia,function = "rsvd4"; nvidia,pull = ; @@ -1503,14 +1503,14 @@ nvidia,tristate = ; nvidia,enable-input = ; }; - clk3_req_pee1 { /* NC */ + clk3-req-pee1 { /* NC */ nvidia,pins = "clk3_req_pee1"; nvidia,function = "rsvd2"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - dap_mclk1_req_pee2 { /* NC */ + dap-mclk1-req-pee2 { /* NC */ nvidia,pins = "dap_mclk1_req_pee2"; nvidia,function = "rsvd4"; nvidia,pull = ; @@ -1526,7 +1526,7 @@ * SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1 * bits being set to 0xfffd according to the TRM! */ - sdmmc3_clk_lb_out_pee4 { /* NC */ + sdmmc3-clk-lb-out-pee4 { /* NC */ nvidia,pins = "sdmmc3_clk_lb_out_pee4"; nvidia,function = "sdmmc3"; nvidia,pull = ; @@ -1580,14 +1580,14 @@ pinctrl-0 = <&as3722_default>; as3722_default: pinmux { - gpio2_7 { + gpio2-7 { pins = "gpio2", /* PWR_EN_+V3.3 */ "gpio7"; /* +V1.6_LPO */ function = "gpio"; bias-pull-up; }; - gpio0_1_3_4_5_6 { + gpio0-1-3-4-5-6 { pins = "gpio0", "gpio1", "gpio3", "gpio4", "gpio5", "gpio6"; bias-high-impedance; @@ -2048,7 +2048,7 @@ &gpio { /* I210 Gigabit Ethernet Controller Reset */ - lan_reset_n { + lan-reset-n { gpio-hog; gpios = ; output-high; @@ -2056,7 +2056,7 @@ }; /* Control MXM3 pin 26 Reset Module Output Carrier Input */ - reset_moci_ctrl { + reset-moci-ctrl { gpio-hog; gpios = ; output-high; diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/tegra124-apalis.dtsi index b1a05c37106d..a8f1306b5cd7 100644 --- a/arch/arm/boot/dts/tegra124-apalis.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis.dtsi @@ -106,35 +106,35 @@ state_default: pinmux { /* Analogue Audio (On-module) */ - dap3_fs_pp0 { + dap3-fs-pp0 { nvidia,pins = "dap3_fs_pp0"; nvidia,function = "i2s2"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - dap3_din_pp1 { + dap3-din-pp1 { nvidia,pins = "dap3_din_pp1"; nvidia,function = "i2s2"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - dap3_dout_pp2 { + dap3-dout-pp2 { nvidia,pins = "dap3_dout_pp2"; nvidia,function = "i2s2"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - dap3_sclk_pp3 { + dap3-sclk-pp3 { nvidia,pins = "dap3_sclk_pp3"; nvidia,function = "i2s2"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - dap_mclk1_pw4 { + dap-mclk1-pw4 { nvidia,pins = "dap_mclk1_pw4"; nvidia,function = "extperiph1"; nvidia,pull = ; @@ -161,7 +161,7 @@ }; /* Apalis CAM1_MCLK */ - cam_mclk_pcc0 { + cam-mclk-pcc0 { nvidia,pins = "cam_mclk_pcc0"; nvidia,function = "vi_alt3"; nvidia,pull = ; @@ -170,28 +170,28 @@ }; /* Apalis Digital Audio */ - dap2_fs_pa2 { + dap2-fs-pa2 { nvidia,pins = "dap2_fs_pa2"; nvidia,function = "hda"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - dap2_sclk_pa3 { + dap2-sclk-pa3 { nvidia,pins = "dap2_sclk_pa3"; nvidia,function = "hda"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - dap2_din_pa4 { + dap2-din-pa4 { nvidia,pins = "dap2_din_pa4"; nvidia,function = "hda"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - dap2_dout_pa5 { + dap2-dout-pa5 { nvidia,pins = "dap2_dout_pa5"; nvidia,function = "hda"; nvidia,pull = ; @@ -204,7 +204,7 @@ nvidia,tristate = ; nvidia,enable-input = ; }; - clk3_out_pee0 { + clk3-out-pee0 { nvidia,pins = "clk3_out_pee0"; nvidia,function = "extperiph3"; nvidia,pull = ; @@ -213,49 +213,49 @@ }; /* Apalis GPIO */ - ddc_scl_pv4 { + ddc-scl-pv4 { nvidia,pins = "ddc_scl_pv4"; nvidia,function = "rsvd2"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - ddc_sda_pv5 { + ddc-sda-pv5 { nvidia,pins = "ddc_sda_pv5"; nvidia,function = "rsvd2"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - pex_l0_rst_n_pdd1 { + pex-l0-rst-n-pdd1 { nvidia,pins = "pex_l0_rst_n_pdd1"; nvidia,function = "rsvd2"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - pex_l0_clkreq_n_pdd2 { + pex-l0-clkreq-n-pdd2 { nvidia,pins = "pex_l0_clkreq_n_pdd2"; nvidia,function = "rsvd2"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - pex_l1_rst_n_pdd5 { + pex-l1-rst-n-pdd5 { nvidia,pins = "pex_l1_rst_n_pdd5"; nvidia,function = "rsvd2"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - pex_l1_clkreq_n_pdd6 { + pex-l1-clkreq-n-pdd6 { nvidia,pins = "pex_l1_clkreq_n_pdd6"; nvidia,function = "rsvd2"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - dp_hpd_pff0 { + dp-hpd-pff0 { nvidia,pins = "dp_hpd_pff0"; nvidia,function = "dp"; nvidia,pull = ; @@ -279,7 +279,7 @@ }; /* Apalis HDMI1_CEC */ - hdmi_cec_pee3 { + hdmi-cec-pee3 { nvidia,pins = "hdmi_cec_pee3"; nvidia,function = "cec"; nvidia,pull = ; @@ -289,7 +289,7 @@ }; /* Apalis HDMI1_HPD */ - hdmi_int_pn7 { + hdmi-int-pn7 { nvidia,pins = "hdmi_int_pn7"; nvidia,function = "rsvd1"; nvidia,pull = ; @@ -299,7 +299,7 @@ }; /* Apalis I2C1 */ - gen1_i2c_scl_pc4 { + gen1-i2c-scl-pc4 { nvidia,pins = "gen1_i2c_scl_pc4"; nvidia,function = "i2c1"; nvidia,pull = ; @@ -307,7 +307,7 @@ nvidia,enable-input = ; nvidia,open-drain = ; }; - gen1_i2c_sda_pc5 { + gen1-i2c-sda-pc5 { nvidia,pins = "gen1_i2c_sda_pc5"; nvidia,function = "i2c1"; nvidia,pull = ; @@ -317,7 +317,7 @@ }; /* Apalis I2C2 (DDC) */ - gen2_i2c_scl_pt5 { + gen2-i2c-scl-pt5 { nvidia,pins = "gen2_i2c_scl_pt5"; nvidia,function = "i2c2"; nvidia,pull = ; @@ -325,7 +325,7 @@ nvidia,enable-input = ; nvidia,open-drain = ; }; - gen2_i2c_sda_pt6 { + gen2-i2c-sda-pt6 { nvidia,pins = "gen2_i2c_sda_pt6"; nvidia,function = "i2c2"; nvidia,pull = ; @@ -335,7 +335,7 @@ }; /* Apalis I2C3 (CAM) */ - cam_i2c_scl_pbb1 { + cam-i2c-scl-pbb1 { nvidia,pins = "cam_i2c_scl_pbb1"; nvidia,function = "i2c3"; nvidia,pull = ; @@ -343,7 +343,7 @@ nvidia,enable-input = ; nvidia,open-drain = ; }; - cam_i2c_sda_pbb2 { + cam-i2c-sda-pbb2 { nvidia,pins = "cam_i2c_sda_pbb2"; nvidia,function = "i2c3"; nvidia,pull = ; @@ -353,77 +353,77 @@ }; /* Apalis MMC1 */ - sdmmc1_cd_n_pv3 { /* CD# GPIO */ + sdmmc1-cd-n-pv3 { /* CD# GPIO */ nvidia,pins = "sdmmc1_wp_n_pv3"; nvidia,function = "sdmmc1"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - clk2_out_pw5 { /* D5 GPIO */ + clk2-out-pw5 { /* D5 GPIO */ nvidia,pins = "clk2_out_pw5"; nvidia,function = "rsvd2"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - sdmmc1_dat3_py4 { + sdmmc1-dat3-py4 { nvidia,pins = "sdmmc1_dat3_py4"; nvidia,function = "sdmmc1"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - sdmmc1_dat2_py5 { + sdmmc1-dat2-py5 { nvidia,pins = "sdmmc1_dat2_py5"; nvidia,function = "sdmmc1"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - sdmmc1_dat1_py6 { + sdmmc1-dat1-py6 { nvidia,pins = "sdmmc1_dat1_py6"; nvidia,function = "sdmmc1"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - sdmmc1_dat0_py7 { + sdmmc1-dat0-py7 { nvidia,pins = "sdmmc1_dat0_py7"; nvidia,function = "sdmmc1"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - sdmmc1_clk_pz0 { + sdmmc1-clk-pz0 { nvidia,pins = "sdmmc1_clk_pz0"; nvidia,function = "sdmmc1"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - sdmmc1_cmd_pz1 { + sdmmc1-cmd-pz1 { nvidia,pins = "sdmmc1_cmd_pz1"; nvidia,function = "sdmmc1"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - clk2_req_pcc5 { /* D4 GPIO */ + clk2-req-pcc5 { /* D4 GPIO */ nvidia,pins = "clk2_req_pcc5"; nvidia,function = "rsvd2"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - sdmmc3_clk_lb_in_pee5 { /* D6 GPIO */ + sdmmc3-clk-lb-in-pee5 { /* D6 GPIO */ nvidia,pins = "sdmmc3_clk_lb_in_pee5"; nvidia,function = "rsvd2"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - usb_vbus_en2_pff1 { /* D7 GPIO */ + usb-vbus-en2-pff1 { /* D7 GPIO */ nvidia,pins = "usb_vbus_en2_pff1"; nvidia,function = "rsvd2"; nvidia,pull = ; @@ -463,7 +463,7 @@ }; /* Apalis SATA1_ACT# */ - dap1_dout_pn2 { + dap1-dout-pn2 { nvidia,pins = "dap1_dout_pn2"; nvidia,function = "gmi"; nvidia,pull = ; @@ -472,49 +472,49 @@ }; /* Apalis SD1 */ - sdmmc3_clk_pa6 { + sdmmc3-clk-pa6 { nvidia,pins = "sdmmc3_clk_pa6"; nvidia,function = "sdmmc3"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - sdmmc3_cmd_pa7 { + sdmmc3-cmd-pa7 { nvidia,pins = "sdmmc3_cmd_pa7"; nvidia,function = "sdmmc3"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - sdmmc3_dat3_pb4 { + sdmmc3-dat3-pb4 { nvidia,pins = "sdmmc3_dat3_pb4"; nvidia,function = "sdmmc3"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - sdmmc3_dat2_pb5 { + sdmmc3-dat2-pb5 { nvidia,pins = "sdmmc3_dat2_pb5"; nvidia,function = "sdmmc3"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - sdmmc3_dat1_pb6 { + sdmmc3-dat1-pb6 { nvidia,pins = "sdmmc3_dat1_pb6"; nvidia,function = "sdmmc3"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - sdmmc3_dat0_pb7 { + sdmmc3-dat0-pb7 { nvidia,pins = "sdmmc3_dat0_pb7"; nvidia,function = "sdmmc3"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - sdmmc3_cd_n_pv2 { /* CD# GPIO */ + sdmmc3-cd-n-pv2 { /* CD# GPIO */ nvidia,pins = "sdmmc3_cd_n_pv2"; nvidia,function = "rsvd3"; nvidia,pull = ; @@ -523,14 +523,14 @@ }; /* Apalis SPDIF */ - spdif_out_pk5 { + spdif-out-pk5 { nvidia,pins = "spdif_out_pk5"; nvidia,function = "spdif"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - spdif_in_pk6 { + spdif-in-pk6 { nvidia,pins = "spdif_in_pk6"; nvidia,function = "spdif"; nvidia,pull = ; @@ -539,28 +539,28 @@ }; /* Apalis SPI1 */ - ulpi_clk_py0 { + ulpi-clk-py0 { nvidia,pins = "ulpi_clk_py0"; nvidia,function = "spi1"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - ulpi_dir_py1 { + ulpi-dir-py1 { nvidia,pins = "ulpi_dir_py1"; nvidia,function = "spi1"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - ulpi_nxt_py2 { + ulpi-nxt-py2 { nvidia,pins = "ulpi_nxt_py2"; nvidia,function = "spi1"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - ulpi_stp_py3 { + ulpi-stp-py3 { nvidia,pins = "ulpi_stp_py3"; nvidia,function = "spi1"; nvidia,pull = ; @@ -613,42 +613,42 @@ nvidia,tristate = ; nvidia,enable-input = ; }; - uart1_txd_pu0 { + uart1-txd-pu0 { nvidia,pins = "pu0"; nvidia,function = "uarta"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - uart1_rxd_pu1 { + uart1-rxd-pu1 { nvidia,pins = "pu1"; nvidia,function = "uarta"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - uart1_cts_n_pu2 { + uart1-cts-n-pu2 { nvidia,pins = "pu2"; nvidia,function = "uarta"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - uart1_rts_n_pu3 { + uart1-rts-n-pu3 { nvidia,pins = "pu3"; nvidia,function = "uarta"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - uart3_cts_n_pa1 { /* DSR GPIO */ + uart3-cts-n-pa1 { /* DSR GPIO */ nvidia,pins = "uart3_cts_n_pa1"; nvidia,function = "gmi"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - uart3_rts_n_pc0 { /* DTR GPIO */ + uart3-rts-n-pc0 { /* DTR GPIO */ nvidia,pins = "uart3_rts_n_pc0"; nvidia,function = "gmi"; nvidia,pull = ; @@ -657,28 +657,28 @@ }; /* Apalis UART2 */ - uart2_txd_pc2 { + uart2-txd-pc2 { nvidia,pins = "uart2_txd_pc2"; nvidia,function = "irda"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - uart2_rxd_pc3 { + uart2-rxd-pc3 { nvidia,pins = "uart2_rxd_pc3"; nvidia,function = "irda"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - uart2_cts_n_pj5 { + uart2-cts-n-pj5 { nvidia,pins = "uart2_cts_n_pj5"; nvidia,function = "uartb"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - uart2_rts_n_pj6 { + uart2-rts-n-pj6 { nvidia,pins = "uart2_rts_n_pj6"; nvidia,function = "uartb"; nvidia,pull = ; @@ -687,14 +687,14 @@ }; /* Apalis UART3 */ - uart3_txd_pw6 { + uart3-txd-pw6 { nvidia,pins = "uart3_txd_pw6"; nvidia,function = "uartc"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - uart3_rxd_pw7 { + uart3-rxd-pw7 { nvidia,pins = "uart3_rxd_pw7"; nvidia,function = "uartc"; nvidia,pull = ; @@ -703,14 +703,14 @@ }; /* Apalis UART4 */ - uart4_rxd_pb0 { + uart4-rxd-pb0 { nvidia,pins = "pb0"; nvidia,function = "uartd"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - uart4_txd_pj7 { + uart4-txd-pj7 { nvidia,pins = "pj7"; nvidia,function = "uartd"; nvidia,pull = ; @@ -719,7 +719,7 @@ }; /* Apalis USBH_EN */ - usb_vbus_en1_pn5 { + usb-vbus-en1-pn5 { nvidia,pins = "usb_vbus_en1_pn5"; nvidia,function = "rsvd2"; nvidia,pull = ; @@ -738,7 +738,7 @@ }; /* Apalis USBO1_EN */ - usb_vbus_en0_pn4 { + usb-vbus-en0-pn4 { nvidia,pins = "usb_vbus_en0_pn4"; nvidia,function = "rsvd2"; nvidia,pull = ; @@ -757,7 +757,7 @@ }; /* Apalis WAKE1_MICO */ - pex_wake_n_pdd3 { + pex-wake-n-pdd3 { nvidia,pins = "pex_wake_n_pdd3"; nvidia,function = "rsvd2"; nvidia,pull = ; @@ -766,7 +766,7 @@ }; /* CORE_PWR_REQ */ - core_pwr_req { + core-pwr-req { nvidia,pins = "core_pwr_req"; nvidia,function = "pwron"; nvidia,pull = ; @@ -775,7 +775,7 @@ }; /* CPU_PWR_REQ */ - cpu_pwr_req { + cpu-pwr-req { nvidia,pins = "cpu_pwr_req"; nvidia,function = "cpu"; nvidia,pull = ; @@ -784,14 +784,14 @@ }; /* DVFS */ - dvfs_pwm_px0 { + dvfs-pwm-px0 { nvidia,pins = "dvfs_pwm_px0"; nvidia,function = "cldvfs"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - dvfs_clk_px2 { + dvfs-clk-px2 { nvidia,pins = "dvfs_clk_px2"; nvidia,function = "cldvfs"; nvidia,pull = ; @@ -800,70 +800,70 @@ }; /* eMMC */ - sdmmc4_dat0_paa0 { + sdmmc4-dat0-paa0 { nvidia,pins = "sdmmc4_dat0_paa0"; nvidia,function = "sdmmc4"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - sdmmc4_dat1_paa1 { + sdmmc4-dat1-paa1 { nvidia,pins = "sdmmc4_dat1_paa1"; nvidia,function = "sdmmc4"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - sdmmc4_dat2_paa2 { + sdmmc4-dat2-paa2 { nvidia,pins = "sdmmc4_dat2_paa2"; nvidia,function = "sdmmc4"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - sdmmc4_dat3_paa3 { + sdmmc4-dat3-paa3 { nvidia,pins = "sdmmc4_dat3_paa3"; nvidia,function = "sdmmc4"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - sdmmc4_dat4_paa4 { + sdmmc4-dat4-paa4 { nvidia,pins = "sdmmc4_dat4_paa4"; nvidia,function = "sdmmc4"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - sdmmc4_dat5_paa5 { + sdmmc4-dat5-paa5 { nvidia,pins = "sdmmc4_dat5_paa5"; nvidia,function = "sdmmc4"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - sdmmc4_dat6_paa6 { + sdmmc4-dat6-paa6 { nvidia,pins = "sdmmc4_dat6_paa6"; nvidia,function = "sdmmc4"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - sdmmc4_dat7_paa7 { + sdmmc4-dat7-paa7 { nvidia,pins = "sdmmc4_dat7_paa7"; nvidia,function = "sdmmc4"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - sdmmc4_clk_pcc4 { + sdmmc4-clk-pcc4 { nvidia,pins = "sdmmc4_clk_pcc4"; nvidia,function = "sdmmc4"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - sdmmc4_cmd_pt7 { + sdmmc4-cmd-pt7 { nvidia,pins = "sdmmc4_cmd_pt7"; nvidia,function = "sdmmc4"; nvidia,pull = ; @@ -872,7 +872,7 @@ }; /* JTAG_RTCK */ - jtag_rtck { + jtag-rtck { nvidia,pins = "jtag_rtck"; nvidia,function = "rtck"; nvidia,pull = ; @@ -881,7 +881,7 @@ }; /* LAN_DEV_OFF# */ - ulpi_data5_po6 { + ulpi-data5-po6 { nvidia,pins = "ulpi_data5_po6"; nvidia,function = "ulpi"; nvidia,pull = ; @@ -890,7 +890,7 @@ }; /* LAN_RESET# */ - kb_row10_ps2 { + kb-row10-ps2 { nvidia,pins = "kb_row10_ps2"; nvidia,function = "rsvd2"; nvidia,pull = ; @@ -899,7 +899,7 @@ }; /* LAN_WAKE# */ - ulpi_data4_po5 { + ulpi-data4-po5 { nvidia,pins = "ulpi_data4_po5"; nvidia,function = "ulpi"; nvidia,pull = ; @@ -953,35 +953,35 @@ }; /* MCU SPI */ - gpio_x4_aud_px4 { + gpio-x4-aud-px4 { nvidia,pins = "gpio_x4_aud_px4"; nvidia,function = "spi2"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - gpio_x5_aud_px5 { + gpio-x5-aud-px5 { nvidia,pins = "gpio_x5_aud_px5"; nvidia,function = "spi2"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - gpio_x6_aud_px6 { /* MCU_CS */ + gpio-x6-aud-px6 { /* MCU_CS */ nvidia,pins = "gpio_x6_aud_px6"; nvidia,function = "spi2"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - gpio_x7_aud_px7 { + gpio-x7-aud-px7 { nvidia,pins = "gpio_x7_aud_px7"; nvidia,function = "spi2"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - gpio_w2_aud_pw2 { /* MCU_CSEZP */ + gpio-w2-aud-pw2 { /* MCU_CSEZP */ nvidia,pins = "gpio_w2_aud_pw2"; nvidia,function = "spi2"; nvidia,pull = ; @@ -990,7 +990,7 @@ }; /* PMIC_CLK_32K */ - clk_32k_in { + clk-32k-in { nvidia,pins = "clk_32k_in"; nvidia,function = "clk"; nvidia,pull = ; @@ -999,7 +999,7 @@ }; /* PMIC_CPU_OC_INT */ - clk_32k_out_pa0 { + clk-32k-out-pa0 { nvidia,pins = "clk_32k_out_pa0"; nvidia,function = "soc"; nvidia,pull = ; @@ -1008,7 +1008,7 @@ }; /* PWR_I2C */ - pwr_i2c_scl_pz6 { + pwr-i2c-scl-pz6 { nvidia,pins = "pwr_i2c_scl_pz6"; nvidia,function = "i2cpwr"; nvidia,pull = ; @@ -1016,7 +1016,7 @@ nvidia,enable-input = ; nvidia,open-drain = ; }; - pwr_i2c_sda_pz7 { + pwr-i2c-sda-pz7 { nvidia,pins = "pwr_i2c_sda_pz7"; nvidia,function = "i2cpwr"; nvidia,pull = ; @@ -1026,7 +1026,7 @@ }; /* PWR_INT_N */ - pwr_int_n { + pwr-int-n { nvidia,pins = "pwr_int_n"; nvidia,function = "pmi"; nvidia,pull = ; @@ -1044,7 +1044,7 @@ }; /* RESET_OUT_N */ - reset_out_n { + reset-out-n { nvidia,pins = "reset_out_n"; nvidia,function = "reset_out_n"; nvidia,pull = ; @@ -1053,14 +1053,14 @@ }; /* SHIFT_CTRL_DIR_IN */ - kb_row0_pr0 { + kb-row0-pr0 { nvidia,pins = "kb_row0_pr0"; nvidia,function = "rsvd2"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - kb_row1_pr1 { + kb-row1-pr1 { nvidia,pins = "kb_row1_pr1"; nvidia,function = "rsvd2"; nvidia,pull = ; @@ -1069,7 +1069,7 @@ }; /* Configure level-shifter as output for HDA */ - kb_row11_ps3 { + kb-row11-ps3 { nvidia,pins = "kb_row11_ps3"; nvidia,function = "rsvd2"; nvidia,pull = ; @@ -1078,21 +1078,21 @@ }; /* SHIFT_CTRL_DIR_OUT */ - kb_col5_pq5 { + kb-col5-pq5 { nvidia,pins = "kb_col5_pq5"; nvidia,function = "rsvd2"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - kb_col6_pq6 { + kb-col6-pq6 { nvidia,pins = "kb_col6_pq6"; nvidia,function = "rsvd2"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - kb_col7_pq7 { + kb-col7-pq7 { nvidia,pins = "kb_col7_pq7"; nvidia,function = "rsvd2"; nvidia,pull = ; @@ -1101,35 +1101,35 @@ }; /* SHIFT_CTRL_OE */ - kb_col0_pq0 { + kb-col0-pq0 { nvidia,pins = "kb_col0_pq0"; nvidia,function = "rsvd2"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - kb_col1_pq1 { + kb-col1-pq1 { nvidia,pins = "kb_col1_pq1"; nvidia,function = "rsvd2"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - kb_col2_pq2 { + kb-col2-pq2 { nvidia,pins = "kb_col2_pq2"; nvidia,function = "rsvd2"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - kb_col4_pq4 { + kb-col4-pq4 { nvidia,pins = "kb_col4_pq4"; nvidia,function = "kbc"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - kb_row2_pr2 { + kb-row2-pr2 { nvidia,pins = "kb_row2_pr2"; nvidia,function = "rsvd2"; nvidia,pull = ; @@ -1147,7 +1147,7 @@ }; /* TOUCH_INT */ - gpio_w3_aud_pw3 { + gpio-w3-aud-pw3 { nvidia,pins = "gpio_w3_aud_pw3"; nvidia,function = "spi6"; nvidia,pull = ; @@ -1288,189 +1288,189 @@ nvidia,tristate = ; nvidia,enable-input = ; }; - dap1_fs_pn0 { /* NC */ + dap1-fs-pn0 { /* NC */ nvidia,pins = "dap1_fs_pn0"; nvidia,function = "rsvd4"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - dap1_din_pn1 { /* NC */ + dap1-din-pn1 { /* NC */ nvidia,pins = "dap1_din_pn1"; nvidia,function = "rsvd4"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - dap1_sclk_pn3 { /* NC */ + dap1-sclk-pn3 { /* NC */ nvidia,pins = "dap1_sclk_pn3"; nvidia,function = "rsvd4"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - ulpi_data7_po0 { /* NC */ + ulpi-data7-po0 { /* NC */ nvidia,pins = "ulpi_data7_po0"; nvidia,function = "ulpi"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - ulpi_data0_po1 { /* NC */ + ulpi-data0-po1 { /* NC */ nvidia,pins = "ulpi_data0_po1"; nvidia,function = "ulpi"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - ulpi_data1_po2 { /* NC */ + ulpi-data1-po2 { /* NC */ nvidia,pins = "ulpi_data1_po2"; nvidia,function = "ulpi"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - ulpi_data2_po3 { /* NC */ + ulpi-data2-po3 { /* NC */ nvidia,pins = "ulpi_data2_po3"; nvidia,function = "ulpi"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - ulpi_data3_po4 { /* NC */ + ulpi-data3-po4 { /* NC */ nvidia,pins = "ulpi_data3_po4"; nvidia,function = "ulpi"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - ulpi_data6_po7 { /* NC */ + ulpi-data6-po7 { /* NC */ nvidia,pins = "ulpi_data6_po7"; nvidia,function = "ulpi"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - dap4_fs_pp4 { /* NC */ + dap4-fs-pp4 { /* NC */ nvidia,pins = "dap4_fs_pp4"; nvidia,function = "rsvd4"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - dap4_din_pp5 { /* NC */ + dap4-din-pp5 { /* NC */ nvidia,pins = "dap4_din_pp5"; nvidia,function = "rsvd3"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - dap4_dout_pp6 { /* NC */ + dap4-dout-pp6 { /* NC */ nvidia,pins = "dap4_dout_pp6"; nvidia,function = "rsvd4"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - dap4_sclk_pp7 { /* NC */ + dap4-sclk-pp7 { /* NC */ nvidia,pins = "dap4_sclk_pp7"; nvidia,function = "rsvd3"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - kb_col3_pq3 { /* NC */ + kb-col3-pq3 { /* NC */ nvidia,pins = "kb_col3_pq3"; nvidia,function = "kbc"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - kb_row3_pr3 { /* NC */ + kb-row3-pr3 { /* NC */ nvidia,pins = "kb_row3_pr3"; nvidia,function = "kbc"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - kb_row4_pr4 { /* NC */ + kb-row4-pr4 { /* NC */ nvidia,pins = "kb_row4_pr4"; nvidia,function = "rsvd3"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - kb_row5_pr5 { /* NC */ + kb-row5-pr5 { /* NC */ nvidia,pins = "kb_row5_pr5"; nvidia,function = "rsvd3"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - kb_row6_pr6 { /* NC */ + kb-row6-pr6 { /* NC */ nvidia,pins = "kb_row6_pr6"; nvidia,function = "kbc"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - kb_row7_pr7 { /* NC */ + kb-row7-pr7 { /* NC */ nvidia,pins = "kb_row7_pr7"; nvidia,function = "rsvd2"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - kb_row8_ps0 { /* NC */ + kb-row8-ps0 { /* NC */ nvidia,pins = "kb_row8_ps0"; nvidia,function = "rsvd2"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - kb_row9_ps1 { /* NC */ + kb-row9-ps1 { /* NC */ nvidia,pins = "kb_row9_ps1"; nvidia,function = "rsvd2"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - kb_row12_ps4 { /* NC */ + kb-row12-ps4 { /* NC */ nvidia,pins = "kb_row12_ps4"; nvidia,function = "rsvd2"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - kb_row13_ps5 { /* NC */ + kb-row13-ps5 { /* NC */ nvidia,pins = "kb_row13_ps5"; nvidia,function = "rsvd2"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - kb_row14_ps6 { /* NC */ + kb-row14-ps6 { /* NC */ nvidia,pins = "kb_row14_ps6"; nvidia,function = "rsvd2"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - kb_row15_ps7 { /* NC */ + kb-row15-ps7 { /* NC */ nvidia,pins = "kb_row15_ps7"; nvidia,function = "rsvd3"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - kb_row16_pt0 { /* NC */ + kb-row16-pt0 { /* NC */ nvidia,pins = "kb_row16_pt0"; nvidia,function = "rsvd2"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - kb_row17_pt1 { /* NC */ + kb-row17-pt1 { /* NC */ nvidia,pins = "kb_row17_pt1"; nvidia,function = "rsvd2"; nvidia,pull = ; @@ -1498,14 +1498,14 @@ nvidia,tristate = ; nvidia,enable-input = ; }; - gpio_x1_aud_px1 { /* NC */ + gpio-x1-aud-px1 { /* NC */ nvidia,pins = "gpio_x1_aud_px1"; nvidia,function = "rsvd2"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - gpio_x3_aud_px3 { /* NC */ + gpio-x3-aud-px3 { /* NC */ nvidia,pins = "gpio_x3_aud_px3"; nvidia,function = "rsvd4"; nvidia,pull = ; @@ -1533,14 +1533,14 @@ nvidia,tristate = ; nvidia,enable-input = ; }; - clk3_req_pee1 { /* NC */ + clk3-req-pee1 { /* NC */ nvidia,pins = "clk3_req_pee1"; nvidia,function = "rsvd2"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; - dap_mclk1_req_pee2 { /* NC */ + dap-mclk1-req-pee2 { /* NC */ nvidia,pins = "dap_mclk1_req_pee2"; nvidia,function = "rsvd4"; nvidia,pull = ; @@ -1556,7 +1556,7 @@ * SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1 * bits being set to 0xfffd according to the TRM! */ - sdmmc3_clk_lb_out_pee4 { /* NC */ + sdmmc3-clk-lb-out-pee4 { /* NC */ nvidia,pins = "sdmmc3_clk_lb_out_pee4"; nvidia,function = "sdmmc3"; nvidia,pull = ; @@ -1610,14 +1610,14 @@ pinctrl-0 = <&as3722_default>; as3722_default: pinmux { - gpio2_7 { + gpio2-7 { pins = "gpio2", /* PWR_EN_+V3.3 */ "gpio7"; /* +V1.6_LPO */ function = "gpio"; bias-pull-up; }; - gpio0_1_3_4_5_6 { + gpio0-1-3-4-5-6 { pins = "gpio0", "gpio1", "gpio3", "gpio4", "gpio5", "gpio6"; bias-high-impedance; @@ -2078,7 +2078,7 @@ &gpio { /* I210 Gigabit Ethernet Controller Reset */ - lan_reset_n { + lan-reset-n { gpio-hog; gpios = ; output-high; @@ -2086,7 +2086,7 @@ }; /* Control MXM3 pin 26 Reset Module Output Carrier Input */ - reset_moci_ctrl { + reset-moci-ctrl { gpio-hog; gpios = ; output-high; -- cgit v1.2.2 From 94c3847dc5d18b56503415ef7733a4507061b1ca Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sat, 1 Sep 2018 15:05:02 +0200 Subject: ARM: tegra: apalis-tk1: get rid of fake clocks simple bus Get rid of the fake clocks simple bus and use node names as per the actual schematics. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi | 15 ++++----------- arch/arm/boot/dts/tegra124-apalis.dtsi | 15 ++++----------- 2 files changed, 8 insertions(+), 22 deletions(-) diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi index 6d36521448ce..7fe61f1baadd 100644 --- a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi @@ -1931,17 +1931,10 @@ }; }; - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; + clk32k_in: osc3 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; }; cpus { diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/tegra124-apalis.dtsi index a8f1306b5cd7..62af3dc97ede 100644 --- a/arch/arm/boot/dts/tegra124-apalis.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis.dtsi @@ -1961,17 +1961,10 @@ }; }; - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; + clk32k_in: osc3 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; }; cpus { -- cgit v1.2.2 From 6253f885725303c949c0cab2a28fcba9a3695b44 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sat, 1 Sep 2018 15:05:03 +0200 Subject: ARM: tegra: apalis-tk1: shorten temperature-sensor node Shorten temperature-sensor node to just temp-sensor as suggested in the binding documentation. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi | 2 +- arch/arm/boot/dts/tegra124-apalis.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi index 7fe61f1baadd..367eb8c86098 100644 --- a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi @@ -1745,7 +1745,7 @@ * TMP451 temperature sensor * Note: THERM_N directly connected to AS3722 PMIC THERM */ - temperature-sensor@4c { + temp-sensor@4c { compatible = "ti,tmp451"; reg = <0x4c>; interrupt-parent = <&gpio>; diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/tegra124-apalis.dtsi index 62af3dc97ede..13c93cd507d8 100644 --- a/arch/arm/boot/dts/tegra124-apalis.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis.dtsi @@ -1775,7 +1775,7 @@ * TMP451 temperature sensor * Note: THERM_N directly connected to AS3722 PMIC THERM */ - temperature-sensor@4c { + temp-sensor@4c { compatible = "ti,tmp451"; reg = <0x4c>; interrupt-parent = <&gpio>; -- cgit v1.2.2 From 4b601b9f1022bbd67decf8842a3dd86c850c5e83 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sat, 1 Sep 2018 15:05:04 +0200 Subject: ARM: tegra: apalis-tk1: drop unused hdmi_ddc label Drop unused hdmi_ddc label. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124-apalis-eval.dts | 2 +- arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/tegra124-apalis-eval.dts b/arch/arm/boot/dts/tegra124-apalis-eval.dts index 0b4ac640e54f..eaee10ef6512 100644 --- a/arch/arm/boot/dts/tegra124-apalis-eval.dts +++ b/arch/arm/boot/dts/tegra124-apalis-eval.dts @@ -123,7 +123,7 @@ /* * GEN2_I2C: I2C2_SDA/SCL (DDC) on MXM3 pin 205/207 (e.g. display EDID) */ - hdmi_ddc: i2c@7000c400 { + i2c@7000c400 { status = "okay"; }; diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts b/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts index 799382d04bba..7961eb4bd803 100644 --- a/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts +++ b/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts @@ -100,7 +100,7 @@ * I2C4 (DDC): I2C4_SDA/SCL (DDC) on MXM3 pin 205/207 * (e.g. display EDID) */ - hdmi_ddc: i2c@7000c700 { + i2c@7000c700 { status = "okay"; }; -- cgit v1.2.2 From 3c59cae79fbeb6d44e603a49d845428b8ef98718 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sun, 2 Sep 2018 12:08:30 +0200 Subject: ARM: tegra: colibri_t20: move aliases from module to carrier board Move RTC aliases from module to carrier board to be more in-line with all our other device trees. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-colibri-iris.dts | 2 ++ arch/arm/boot/dts/tegra20-colibri.dtsi | 5 ----- 2 files changed, 2 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/tegra20-colibri-iris.dts b/arch/arm/boot/dts/tegra20-colibri-iris.dts index 57f16c0e9917..496b96e229d2 100644 --- a/arch/arm/boot/dts/tegra20-colibri-iris.dts +++ b/arch/arm/boot/dts/tegra20-colibri-iris.dts @@ -8,6 +8,8 @@ compatible = "toradex,iris", "toradex,colibri_t20-512", "nvidia,tegra20"; aliases { + rtc0 = "/i2c@7000d000/tps6586x@34"; + rtc1 = "/rtc@7000e000"; serial0 = &uarta; serial1 = &uartd; }; diff --git a/arch/arm/boot/dts/tegra20-colibri.dtsi b/arch/arm/boot/dts/tegra20-colibri.dtsi index e7b9ab09908a..ad2676b3cd5b 100644 --- a/arch/arm/boot/dts/tegra20-colibri.dtsi +++ b/arch/arm/boot/dts/tegra20-colibri.dtsi @@ -5,11 +5,6 @@ model = "Toradex Colibri T20 256/512 MB"; compatible = "toradex,colibri_t20-512", "nvidia,tegra20"; - aliases { - rtc0 = "/i2c@7000d000/tps6586x@34"; - rtc1 = "/rtc@7000e000"; - }; - memory@0 { /* * Set memory to 256 MB to be safe as this could be used on -- cgit v1.2.2 From 3ef8af133e87d631cf96833e114ca55112096e1d Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sun, 2 Sep 2018 12:08:31 +0200 Subject: ARM: tegra: colibri_t20: iris: integrate i2c real time clock support Integrate support for GEN1_I2C aka I2C_SDA/SCL on SODIMM pin 194/196 and the M41T0M6 real time clock on the carrier board. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-colibri-iris.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/boot/dts/tegra20-colibri-iris.dts b/arch/arm/boot/dts/tegra20-colibri-iris.dts index 496b96e229d2..b6d05da8c93c 100644 --- a/arch/arm/boot/dts/tegra20-colibri-iris.dts +++ b/arch/arm/boot/dts/tegra20-colibri-iris.dts @@ -56,6 +56,21 @@ status = "okay"; }; + /* + * GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier + * board) + */ + i2c@7000c000 { + status = "okay"; + clock-frequency = <400000>; + + /* M41T0M6 real time clock on carrier board */ + rtc@68 { + compatible = "st,m41t0"; + reg = <0x68>; + }; + }; + i2c_ddc: i2c@7000c400 { status = "okay"; }; -- cgit v1.2.2 From 59b6f20bccbd47917ca63ae2b5a5d3f849aa46c0 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sun, 2 Sep 2018 12:08:32 +0200 Subject: ARM: tegra: colibri_t20: iris: add missing aliases Add rtc0 being the ultra low-power I2C one as found on the carrier board and the 3rd UART being NVIDIA's UARTB. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-colibri-iris.dts | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/tegra20-colibri-iris.dts b/arch/arm/boot/dts/tegra20-colibri-iris.dts index b6d05da8c93c..cbf1f4d76813 100644 --- a/arch/arm/boot/dts/tegra20-colibri-iris.dts +++ b/arch/arm/boot/dts/tegra20-colibri-iris.dts @@ -8,10 +8,12 @@ compatible = "toradex,iris", "toradex,colibri_t20-512", "nvidia,tegra20"; aliases { - rtc0 = "/i2c@7000d000/tps6586x@34"; - rtc1 = "/rtc@7000e000"; + rtc0 = "/i2c@7000c000/rtc@68"; + rtc1 = "/i2c@7000d000/tps6586x@34"; + rtc2 = "/rtc@7000e000"; serial0 = &uarta; serial1 = &uartd; + serial2 = &uartb; }; chosen { -- cgit v1.2.2 From 1d6050d67ea820db776691e46e744e6f8d8e2c64 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sun, 2 Sep 2018 12:08:33 +0200 Subject: ARM: tegra: colibri_t20: iris: annotate i2c busses Annotate I2C busses: GEN2_I2C and CAM_I2C (I2C3) being unused and DDC_CLOCK/DATA on X3 pin 15/16 e.g. used for display EDID. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-colibri-iris.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/tegra20-colibri-iris.dts b/arch/arm/boot/dts/tegra20-colibri-iris.dts index cbf1f4d76813..cc9e372a3b58 100644 --- a/arch/arm/boot/dts/tegra20-colibri-iris.dts +++ b/arch/arm/boot/dts/tegra20-colibri-iris.dts @@ -73,6 +73,11 @@ }; }; + /* GEN2_I2C: unused */ + + /* CAM_I2C (I2C3): unused */ + + /* DDC_CLOCK/DATA on X3 pin 15/16 (e.g. display EDID) */ i2c_ddc: i2c@7000c400 { status = "okay"; }; -- cgit v1.2.2 From 364ba1043937b00e4d555fe6268534d18db9f698 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sun, 2 Sep 2018 12:08:34 +0200 Subject: ARM: tegra: colibri_t20: add local-mac-address property Add empty local-mac-address property to be filled in by boot loader (e.g. U-Boot). Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-colibri.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/tegra20-colibri.dtsi b/arch/arm/boot/dts/tegra20-colibri.dtsi index ad2676b3cd5b..84df29a62f84 100644 --- a/arch/arm/boot/dts/tegra20-colibri.dtsi +++ b/arch/arm/boot/dts/tegra20-colibri.dtsi @@ -482,6 +482,13 @@ status = "okay"; nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_LOW>; + #address-cells = <1>; + #size-cells = <0>; + + asix@1 { + reg = <1>; + local-mac-address = [00 00 00 00 00 00]; + }; }; usb-phy@c5004000 { -- cgit v1.2.2 From e6800c214e56f6c7fcadf63e9d60b464d31cea40 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sun, 2 Sep 2018 12:08:35 +0200 Subject: ARM: tegra: colibri_t20: reorder host1x/hdmi properties Reorder Host1x/HDMI properties. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-colibri.dtsi | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/tegra20-colibri.dtsi b/arch/arm/boot/dts/tegra20-colibri.dtsi index 84df29a62f84..166e7c561804 100644 --- a/arch/arm/boot/dts/tegra20-colibri.dtsi +++ b/arch/arm/boot/dts/tegra20-colibri.dtsi @@ -16,12 +16,11 @@ host1x@50000000 { hdmi@54280000 { - vdd-supply = <&hdmi_vdd_reg>; - pll-supply = <&hdmi_pll_reg>; - nvidia,ddc-i2c-bus = <&i2c_ddc>; - nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) - GPIO_ACTIVE_HIGH>; + nvidia,hpd-gpio = + <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; + pll-supply = <&hdmi_pll_reg>; + vdd-supply = <&hdmi_vdd_reg>; }; }; -- cgit v1.2.2 From 142165cf7359afb23e624e5f1df290050682654b Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sun, 2 Sep 2018 12:08:36 +0200 Subject: ARM: tegra: colibri_t20: iris: use no-1-8-v Use no-1-8-v property rather than vmmc/vqmmc supplies and drop now obsolete and anyway non-existent vcc_sd. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-colibri-iris.dts | 13 +------------ 1 file changed, 1 insertion(+), 12 deletions(-) diff --git a/arch/arm/boot/dts/tegra20-colibri-iris.dts b/arch/arm/boot/dts/tegra20-colibri-iris.dts index cc9e372a3b58..3d430fa93e8c 100644 --- a/arch/arm/boot/dts/tegra20-colibri-iris.dts +++ b/arch/arm/boot/dts/tegra20-colibri-iris.dts @@ -101,8 +101,7 @@ sdhci@c8000600 { status = "okay"; bus-width = <4>; - vmmc-supply = <&vcc_sd_reg>; - vqmmc-supply = <&vcc_sd_reg>; + no-1-8-v; }; regulators { @@ -116,15 +115,5 @@ regulator-always-on; gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>; }; - - vcc_sd_reg: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "vcc_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; }; }; -- cgit v1.2.2 From 3647c7b8489d52a5fbd19065ffa2b6b176796c72 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sun, 2 Sep 2018 12:08:37 +0200 Subject: ARM: tegra: colibri_t20: regulator clean-up Just cosmetic regulator clean-up. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-colibri-iris.dts | 20 ++-- arch/arm/boot/dts/tegra20-colibri.dtsi | 147 +++++++++++------------------ 2 files changed, 66 insertions(+), 101 deletions(-) diff --git a/arch/arm/boot/dts/tegra20-colibri-iris.dts b/arch/arm/boot/dts/tegra20-colibri-iris.dts index 3d430fa93e8c..6f89a417b0f2 100644 --- a/arch/arm/boot/dts/tegra20-colibri-iris.dts +++ b/arch/arm/boot/dts/tegra20-colibri-iris.dts @@ -104,16 +104,14 @@ no-1-8-v; }; - regulators { - regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "usb_host_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - regulator-always-on; - gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>; - }; + /* USBH_PEN resp. USB_P_EN */ + reg_usbh_vbus: regulator-usbh-vbus { + compatible = "regulator-fixed"; + regulator-name = "VCC_USB1"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; }; }; diff --git a/arch/arm/boot/dts/tegra20-colibri.dtsi b/arch/arm/boot/dts/tegra20-colibri.dtsi index 166e7c561804..db0264c1f52c 100644 --- a/arch/arm/boot/dts/tegra20-colibri.dtsi +++ b/arch/arm/boot/dts/tegra20-colibri.dtsi @@ -19,8 +19,8 @@ nvidia,ddc-i2c-bus = <&i2c_ddc>; nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; - pll-supply = <&hdmi_pll_reg>; - vdd-supply = <&hdmi_vdd_reg>; + pll-supply = <®_1v8_avdd_hdmi_pll>; + vdd-supply = <®_3v3_avdd_hdmi>; }; }; @@ -260,49 +260,38 @@ #gpio-cells = <2>; gpio-controller; - sys-supply = <&vdd_3v3_reg>; - vin-sm0-supply = <&sys_reg>; - vin-sm1-supply = <&sys_reg>; - vin-sm2-supply = <&sys_reg>; - vinldo01-supply = <&sm2_reg>; - vinldo23-supply = <&vdd_3v3_reg>; - vinldo4-supply = <&vdd_3v3_reg>; - vinldo678-supply = <&vdd_3v3_reg>; - vinldo9-supply = <&vdd_3v3_reg>; + sys-supply = <®_module_3v3>; + vin-sm0-supply = <®_3v3_vsys>; + vin-sm1-supply = <®_3v3_vsys>; + vin-sm2-supply = <®_3v3_vsys>; + vinldo01-supply = <®_1v8_vdd_ddr2>; + vinldo23-supply = <®_module_3v3>; + vinldo4-supply = <®_module_3v3>; + vinldo678-supply = <®_module_3v3>; + vinldo9-supply = <®_module_3v3>; regulators { - #address-cells = <1>; - #size-cells = <0>; - - sys_reg: regulator@0 { - reg = <0>; - regulator-compatible = "sys"; - regulator-name = "vdd_sys"; + reg_3v3_vsys: sys { + regulator-name = "VSYS_3.3V"; regulator-always-on; }; - regulator@1 { - reg = <1>; - regulator-compatible = "sm0"; - regulator-name = "vdd_sm0,vdd_core"; + sm0 { + regulator-name = "VDD_CORE_1.2V"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; regulator-always-on; }; - regulator@2 { - reg = <2>; - regulator-compatible = "sm1"; - regulator-name = "vdd_sm1,vdd_cpu"; + sm1 { + regulator-name = "VDD_CPU_1.0V"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; regulator-always-on; }; - sm2_reg: regulator@3 { - reg = <3>; - regulator-compatible = "sm2"; - regulator-name = "vdd_sm2,vin_ldo*"; + reg_1v8_vdd_ddr2: sm2 { + regulator-name = "VDD_DDR2_1.8V"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; @@ -310,80 +299,68 @@ /* LDO0 is not connected to anything */ - regulator@5 { - reg = <5>; - regulator-compatible = "ldo1"; - regulator-name = "vdd_ldo1,avdd_pll*"; + /* + * +3.3V_ENABLE_N switching via FET: + * AVDD_AUDIO_S and +3.3V + * see also +3.3V fixed supply + */ + ldo1 { + regulator-name = "AVDD_PLL_1.1V"; regulator-min-microvolt = <1100000>; regulator-max-microvolt = <1100000>; regulator-always-on; }; - regulator@6 { - reg = <6>; - regulator-compatible = "ldo2"; - regulator-name = "vdd_ldo2,vdd_rtc"; + ldo2 { + regulator-name = "VDD_RTC_1.2V"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; }; /* LDO3 is not connected to anything */ - regulator@8 { - reg = <8>; - regulator-compatible = "ldo4"; - regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; + ldo4 { + regulator-name = "VDDIO_SYS_1.8V"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; }; - ldo5_reg: regulator@9 { - reg = <9>; - regulator-compatible = "ldo5"; - regulator-name = "vdd_ldo5,vdd_fuse"; + /* Switched via FET from regular +3.3V */ + ldo5 { + regulator-name = "+3.3V_USB"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; - regulator@10 { - reg = <10>; - regulator-compatible = "ldo6"; - regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam"; + ldo6 { + regulator-name = "AVDD_VDAC_2.85V"; regulator-min-microvolt = <2850000>; regulator-max-microvolt = <2850000>; }; - hdmi_vdd_reg: regulator@11 { - reg = <11>; - regulator-compatible = "ldo7"; - regulator-name = "vdd_ldo7,avdd_hdmi"; + reg_3v3_avdd_hdmi: ldo7 { + regulator-name = "AVDD_HDMI_3.3V"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; - hdmi_pll_reg: regulator@12 { - reg = <12>; - regulator-compatible = "ldo8"; - regulator-name = "vdd_ldo8,avdd_hdmi_pll"; + reg_1v8_avdd_hdmi_pll: ldo8 { + regulator-name = "AVDD_HDMI_PLL_1.8V"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; - regulator@13 { - reg = <13>; - regulator-compatible = "ldo9"; - regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx"; + ldo9 { + regulator-name = "VDDIO_RX_DDR_2.85V"; regulator-min-microvolt = <2850000>; regulator-max-microvolt = <2850000>; regulator-always-on; }; - regulator@14 { - reg = <14>; - regulator-compatible = "ldo_rtc"; - regulator-name = "vdd_rtc_out,vdd_cell"; + ldo_rtc { + regulator-name = "VCC_BATT"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; @@ -513,31 +490,21 @@ }; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - vdd_3v3_reg: regulator@100 { - compatible = "regulator-fixed"; - reg = <100>; - regulator-name = "vdd_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; + reg_lan_v_bus: regulator-lan-v-bus { + compatible = "regulator-fixed"; + regulator-name = "LAN_V_BUS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>; + }; - regulator@101 { - compatible = "regulator-fixed"; - reg = <101>; - regulator-name = "internal_usb"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-boot-on; - regulator-always-on; - gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>; - }; + reg_module_3v3: regulator-module-3v3 { + compatible = "regulator-fixed"; + regulator-name = "+V3.3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; }; sound { -- cgit v1.2.2 From 18e6ccefe1509db3c75c000a11bc1f81e701e9c3 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sun, 2 Sep 2018 12:08:38 +0200 Subject: ARM: tegra: colibri_t20: add missing regulators Add missing regulators: - reg_lan_v_bus being USB Ethernet chip vbus supply - carrier board reg_3v3 to be used as backlight and panel power supply - carrier board HDMI supply being reg_5v0 - reg_usbc_vbus being the USB vbus supply of the EHCI instance 0 Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-colibri-iris.dts | 28 ++++++++++++++++++++++++++-- arch/arm/boot/dts/tegra20-colibri.dtsi | 1 + 2 files changed, 27 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/tegra20-colibri-iris.dts b/arch/arm/boot/dts/tegra20-colibri-iris.dts index 6f89a417b0f2..9f0a819c68f2 100644 --- a/arch/arm/boot/dts/tegra20-colibri-iris.dts +++ b/arch/arm/boot/dts/tegra20-colibri-iris.dts @@ -23,6 +23,7 @@ host1x@50000000 { hdmi@54280000 { status = "okay"; + hdmi-supply = <®_5v0>; }; }; @@ -88,6 +89,7 @@ usb-phy@c5000000 { status = "okay"; + vbus-supply = <®_usbc_vbus>; }; usb@c5008000 { @@ -96,6 +98,7 @@ usb-phy@c5008000 { status = "okay"; + vbus-supply = <®_usbh_vbus>; }; sdhci@c8000600 { @@ -104,14 +107,35 @@ no-1-8-v; }; + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_5v0: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usbc_vbus: regulator-usbc-vbus { + compatible = "regulator-fixed"; + regulator-name = "VCC_USB2"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <®_5v0>; + }; + /* USBH_PEN resp. USB_P_EN */ reg_usbh_vbus: regulator-usbh-vbus { compatible = "regulator-fixed"; regulator-name = "VCC_USB1"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - regulator-boot-on; - regulator-always-on; gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; + vin-supply = <®_5v0>; }; }; diff --git a/arch/arm/boot/dts/tegra20-colibri.dtsi b/arch/arm/boot/dts/tegra20-colibri.dtsi index db0264c1f52c..72dc440ec28a 100644 --- a/arch/arm/boot/dts/tegra20-colibri.dtsi +++ b/arch/arm/boot/dts/tegra20-colibri.dtsi @@ -471,6 +471,7 @@ status = "okay"; nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_LOW>; + vbus-supply = <®_lan_v_bus>; }; sdhci@c8000600 { -- cgit v1.2.2 From 2287ef76d0a2c3f3411e72cdc139804900b23e7c Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sun, 2 Sep 2018 12:08:39 +0200 Subject: ARM: tegra: colibri_t20: annotate usb ehci instances Annotate USB EHCI instances. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-colibri-iris.dts | 2 ++ arch/arm/boot/dts/tegra20-colibri.dtsi | 1 + 2 files changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/tegra20-colibri-iris.dts b/arch/arm/boot/dts/tegra20-colibri-iris.dts index 9f0a819c68f2..194f40646a83 100644 --- a/arch/arm/boot/dts/tegra20-colibri-iris.dts +++ b/arch/arm/boot/dts/tegra20-colibri-iris.dts @@ -83,6 +83,7 @@ status = "okay"; }; + /* EHCI instance 0: USB1_DP/N -> USBC_P/N */ usb@c5000000 { status = "okay"; }; @@ -92,6 +93,7 @@ vbus-supply = <®_usbc_vbus>; }; + /* EHCI instance 2: USB3_DP/N -> USBH_P/N */ usb@c5008000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/tegra20-colibri.dtsi b/arch/arm/boot/dts/tegra20-colibri.dtsi index 72dc440ec28a..575e9341a8ef 100644 --- a/arch/arm/boot/dts/tegra20-colibri.dtsi +++ b/arch/arm/boot/dts/tegra20-colibri.dtsi @@ -454,6 +454,7 @@ }; }; + /* EHCI instance 1: ULPI PHY -> AX88772B (On-module) */ usb@c5004000 { status = "okay"; nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) -- cgit v1.2.2 From 4307e2ce5d3105e5cfa3296dd65eb48bf0ef64be Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sun, 2 Sep 2018 12:08:40 +0200 Subject: ARM: tegra: colibri_t20: remove phy-reset-gpio from controller node Remove the phy-reset-gpio from the USB controller node as it is already specified in the PHY node. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-colibri.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/tegra20-colibri.dtsi b/arch/arm/boot/dts/tegra20-colibri.dtsi index 575e9341a8ef..ade908e36582 100644 --- a/arch/arm/boot/dts/tegra20-colibri.dtsi +++ b/arch/arm/boot/dts/tegra20-colibri.dtsi @@ -457,8 +457,6 @@ /* EHCI instance 1: ULPI PHY -> AX88772B (On-module) */ usb@c5004000 { status = "okay"; - nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) - GPIO_ACTIVE_LOW>; #address-cells = <1>; #size-cells = <0>; -- cgit v1.2.2 From 035ae62dfbc93eee222e40d1176e92b3fdd21076 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sun, 2 Sep 2018 12:08:41 +0200 Subject: ARM: tegra: colibri_t20: indentation/line-feed/white-space clean-up Cleaning up indentation, line-feed and white-space. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-colibri.dtsi | 20 +++++++------------- 1 file changed, 7 insertions(+), 13 deletions(-) diff --git a/arch/arm/boot/dts/tegra20-colibri.dtsi b/arch/arm/boot/dts/tegra20-colibri.dtsi index ade908e36582..5559008efc5f 100644 --- a/arch/arm/boot/dts/tegra20-colibri.dtsi +++ b/arch/arm/boot/dts/tegra20-colibri.dtsi @@ -206,10 +206,10 @@ ac97: ac97@70002000 { status = "okay"; - nvidia,codec-reset-gpio = <&gpio TEGRA_GPIO(V, 0) - GPIO_ACTIVE_HIGH>; - nvidia,codec-sync-gpio = <&gpio TEGRA_GPIO(P, 0) - GPIO_ACTIVE_HIGH>; + nvidia,codec-reset-gpio = + <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_HIGH>; + nvidia,codec-sync-gpio = + <&gpio TEGRA_GPIO(P, 0) GPIO_ACTIVE_HIGH>; }; nand-controller@70008000 { @@ -254,12 +254,9 @@ compatible = "ti,tps6586x"; reg = <0x34>; interrupts = ; - ti,system-power-controller; - #gpio-cells = <2>; gpio-controller; - sys-supply = <®_module_3v3>; vin-sm0-supply = <®_3v3_vsys>; vin-sm1-supply = <®_3v3_vsys>; @@ -468,8 +465,8 @@ usb-phy@c5004000 { status = "okay"; - nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) - GPIO_ACTIVE_LOW>; + nvidia,phy-reset-gpio = + <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_LOW>; vbus-supply = <®_lan_v_bus>; }; @@ -509,18 +506,15 @@ sound { compatible = "nvidia,tegra-audio-wm9712-colibri_t20", - "nvidia,tegra-audio-wm9712"; + "nvidia,tegra-audio-wm9712"; nvidia,model = "Colibri T20 AC97 Audio"; - nvidia,audio-routing = "Headphone", "HPOUTL", "Headphone", "HPOUTR", "LineIn", "LINEINL", "LineIn", "LINEINR", "Mic", "MIC1"; - nvidia,ac97-controller = <&ac97>; - clocks = <&tegra_car TEGRA20_CLK_PLL_A>, <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, <&tegra_car TEGRA20_CLK_CDEV1>; -- cgit v1.2.2 From ea60afb8d67fa669f659ade45d5ae6530596503f Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sun, 2 Sep 2018 12:08:42 +0200 Subject: ARM: tegra: colibri_t20: update sound nvidia,model Update sound nvidia,model to be more in-line with our other device trees. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-colibri.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra20-colibri.dtsi b/arch/arm/boot/dts/tegra20-colibri.dtsi index 5559008efc5f..ba84184e09b8 100644 --- a/arch/arm/boot/dts/tegra20-colibri.dtsi +++ b/arch/arm/boot/dts/tegra20-colibri.dtsi @@ -507,7 +507,7 @@ sound { compatible = "nvidia,tegra-audio-wm9712-colibri_t20", "nvidia,tegra-audio-wm9712"; - nvidia,model = "Colibri T20 AC97 Audio"; + nvidia,model = "Toradex Colibri T20"; nvidia,audio-routing = "Headphone", "HPOUTL", "Headphone", "HPOUTR", -- cgit v1.2.2 From a2cb59be1086450c8dea7bfbbf2bf0e47c93ced1 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sun, 2 Sep 2018 12:08:43 +0200 Subject: ARM: tegra: colibri_t20: pinmux clean-up Just cosmetic pinmux clean-up. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-colibri-iris.dts | 10 +- arch/arm/boot/dts/tegra20-colibri.dtsi | 287 ++++++++++++++++++++--------- 2 files changed, 202 insertions(+), 95 deletions(-) diff --git a/arch/arm/boot/dts/tegra20-colibri-iris.dts b/arch/arm/boot/dts/tegra20-colibri-iris.dts index 194f40646a83..e026478b58d0 100644 --- a/arch/arm/boot/dts/tegra20-colibri-iris.dts +++ b/arch/arm/boot/dts/tegra20-colibri-iris.dts @@ -29,23 +29,23 @@ pinmux@70000014 { state_default: pinmux { - hdint { + ddc { nvidia,tristate = ; }; - i2cddc { + hotplug-detect { nvidia,tristate = ; }; - sdio4 { + mmc { nvidia,tristate = ; }; - uarta { + uart-a { nvidia,tristate = ; }; - uartd { + uart-b { nvidia,tristate = ; }; }; diff --git a/arch/arm/boot/dts/tegra20-colibri.dtsi b/arch/arm/boot/dts/tegra20-colibri.dtsi index ba84184e09b8..dfe237cea14b 100644 --- a/arch/arm/boot/dts/tegra20-colibri.dtsi +++ b/arch/arm/boot/dts/tegra20-colibri.dtsi @@ -29,175 +29,282 @@ pinctrl-0 = <&state_default>; state_default: pinmux { - audio_refclk { + /* Analogue Audio AC97 to WM9712 (On-module) */ + audio-refclk { nvidia,pins = "cdev1"; nvidia,function = "plla_out"; nvidia,pull = ; nvidia,tristate = ; }; - crt { - nvidia,pins = "crtp"; - nvidia,function = "crt"; - nvidia,pull = ; - nvidia,tristate = ; - }; dap3 { nvidia,pins = "dap3"; nvidia,function = "dap3"; nvidia,pull = ; nvidia,tristate = ; }; - displaya { - nvidia,pins = "ld0", "ld1", "ld2", "ld3", - "ld4", "ld5", "ld6", "ld7", "ld8", - "ld9", "ld10", "ld11", "ld12", "ld13", - "ld14", "ld15", "ld16", "ld17", - "lhs", "lpw0", "lpw2", "lsc0", - "lsc1", "lsck", "lsda", "lspi", "lvs"; - nvidia,function = "displaya"; - nvidia,tristate = ; - }; - gpio_dte { - nvidia,pins = "dte"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - }; - gpio_gmi { - nvidia,pins = "ata", "atc", "atd", "ate", - "dap1", "dap2", "dap4", "gpu", "irrx", - "irtx", "spia", "spib", "spic"; - nvidia,function = "gmi"; + + /* + * AC97_RESET, ULPI_RESET, AC97_INT aka WM9712 GENIRQ + * (All on-module), SODIMM Pin 45 Wakeup + */ + gpio-uac { + nvidia,pins = "uac"; + nvidia,function = "rsvd2"; nvidia,pull = ; nvidia,tristate = ; }; - gpio_pta { + + /* + * Buffer Enables for nPWE and RDnWR (On-module, + * see GPIO hogging further down below) + */ + gpio-pta { nvidia,pins = "pta"; nvidia,function = "rsvd4"; nvidia,pull = ; nvidia,tristate = ; }; - gpio_uac { - nvidia,pins = "uac"; - nvidia,function = "rsvd2"; - nvidia,pull = ; + + /* + * CLK_32K_OUT, CORE_PWR_REQ, CPU_PWR_REQ, PWR_INT_N, + * SYS_CLK_REQ (All on-module) + */ + pmc { + nvidia,pins = "pmc"; + nvidia,function = "pwr_on"; nvidia,tristate = ; }; - hdint { - nvidia,pins = "hdint"; - nvidia,function = "hdmi"; - nvidia,tristate = ; + + /* Colibri Address/Data Bus (GMI) */ + gpio-gmi { + nvidia,pins = "ata", "atc", "atd", "ate", + "dap1", "dap2", "dap4", "gpu", "irrx", + "irtx", "spia", "spib", "spic"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; }; - i2c1 { - nvidia,pins = "rm"; - nvidia,function = "i2c1"; + + /* Colibri BL_ON */ + bl-on { + nvidia,pins = "dta"; + nvidia,function = "vi"; nvidia,pull = ; nvidia,tristate = ; }; - i2c3 { - nvidia,pins = "dtf"; - nvidia,function = "i2c3"; - nvidia,pull = ; + + /* Colibri Backlight PWM, PWM */ + pwm-a-b { + nvidia,pins = "sdc"; + nvidia,function = "pwm"; nvidia,tristate = ; }; - i2cddc { + + /* Colibri DDC */ + ddc { nvidia,pins = "ddc"; nvidia,function = "i2c2"; nvidia,pull = ; nvidia,tristate = ; }; - i2cp { - nvidia,pins = "i2cp"; - nvidia,function = "i2cp"; + + /* + * Colibri EXT_IO* + * Note: dtf optionally used for I2C3 + */ + ext-io { + nvidia,pins = "dtf"; + nvidia,function = "i2c3"; nvidia,pull = ; - nvidia,tristate = ; + nvidia,tristate = ; }; - irda { - nvidia,pins = "uad"; - nvidia,function = "irda"; + + /* + * Colibri Ethernet (On-module) + * ULPI EHCI instance 1 USB2_DP/N -> AX88772B + */ + ulpi { + nvidia,pins = "uaa", "uab", "uda"; + nvidia,function = "ulpi"; nvidia,pull = ; - nvidia,tristate = ; + nvidia,tristate = ; }; - nand { - nvidia,pins = "kbca", "kbcc", "kbcd", - "kbce", "kbcf"; - nvidia,function = "nand"; + ulpi-refclk { + nvidia,pins = "cdev2"; + nvidia,function = "pllp_out4"; nvidia,pull = ; nvidia,tristate = ; }; - owc { - nvidia,pins = "owc"; - nvidia,function = "owr"; + + /* Colibri HOTPLUG_DETECT (HDMI) */ + hotplug-detect { + nvidia,pins = "hdint"; + nvidia,function = "hdmi"; + nvidia,tristate = ; + }; + + /* Colibri I2C */ + i2c { + nvidia,pins = "rm"; + nvidia,function = "i2c1"; nvidia,pull = ; nvidia,tristate = ; }; - pmc { - nvidia,pins = "pmc"; - nvidia,function = "pwr_on"; - nvidia,tristate = ; + + /* Colibri LCD (L_* resp. LDD<*>) */ + lcd { + nvidia,pins = "ld0", "ld1", "ld2", "ld3", + "ld4", "ld5", "ld6", "ld7", + "ld8", "ld9", "ld10", "ld11", + "ld12", "ld13", "ld14", "ld15", + "ld16", "ld17", "lhs", "lpw0", + "lpw2", "lsc0", "lsc1", "lsck", + "lsda", "lspi", "lvs"; + nvidia,function = "displaya"; + nvidia,tristate = ; }; - pwm { - nvidia,pins = "sdb", "sdc", "sdd"; - nvidia,function = "pwm"; + + /* Colibri MMC */ + mmc { + nvidia,pins = "atb", "gma"; + nvidia,function = "sdio4"; + nvidia,pull = ; nvidia,tristate = ; }; - sdio4 { - nvidia,pins = "atb", "gma", "gme"; + + /* Colibri MMC (Optional 8-bit) */ + mmc-8bit { + nvidia,pins = "gme"; nvidia,function = "sdio4"; nvidia,pull = ; nvidia,tristate = ; }; - spi1 { - nvidia,pins = "spid", "spie", "spif"; - nvidia,function = "spi1"; + + /* + * Colibri Parallel Camera (Optional) + * pins multiplexed with others and therefore disabled + * Note: dta used for BL_ON by default + */ + cif-mclk { + nvidia,pins = "csus"; + nvidia,function = "vi_sensor_clk"; + nvidia,pull = ; + nvidia,tristate = ; + }; + cif { + nvidia,pins = "dtb", "dtc", "dtd"; + nvidia,function = "vi"; nvidia,pull = ; nvidia,tristate = ; }; - spi4 { + + /* Colibri PWM, PWM */ + pwm-c-d { + nvidia,pins = "sdb", "sdd"; + nvidia,function = "pwm"; + nvidia,tristate = ; + }; + + /* Colibri SSP */ + ssp { nvidia,pins = "slxa", "slxc", "slxd", "slxk"; nvidia,function = "spi4"; nvidia,pull = ; nvidia,tristate = ; }; - uarta { + + /* Colibri UART-A */ + uart-a { nvidia,pins = "sdio1"; nvidia,function = "uarta"; nvidia,pull = ; nvidia,tristate = ; }; - uartd { + + /* Colibri UART-B */ + uart-b { nvidia,pins = "gmc"; nvidia,function = "uartd"; nvidia,pull = ; nvidia,tristate = ; }; - ulpi { - nvidia,pins = "uaa", "uab", "uda"; - nvidia,function = "ulpi"; + + /* Colibri UART-C */ + uart-c { + nvidia,pins = "uad"; + nvidia,function = "irda"; nvidia,pull = ; - nvidia,tristate = ; + nvidia,tristate = ; }; - ulpi_refclk { - nvidia,pins = "cdev2"; - nvidia,function = "pllp_out4"; + + /* Colibri USBH_OC */ + usbh-oc { + nvidia,pins = "spih"; + nvidia,function = "spi2_alt"; nvidia,pull = ; nvidia,tristate = ; }; - usb_gpio { - nvidia,pins = "spig", "spih"; + + /* Colibri USBH_PEN */ + usbh-pen { + nvidia,pins = "spig"; nvidia,function = "spi2_alt"; nvidia,pull = ; nvidia,tristate = ; }; - vi { - nvidia,pins = "dta", "dtb", "dtc", "dtd"; - nvidia,function = "vi"; + + /* Colibri VGA not supported */ + vga { + nvidia,pins = "crtp"; + nvidia,function = "crt"; nvidia,pull = ; nvidia,tristate = ; }; - vi_sc { - nvidia,pins = "csus"; - nvidia,function = "vi_sensor_clk"; + + /* + * LAN_V_BUS, VDD_FAULT, BATT_FAULT, WM9712 PENDOWN + * (All On-module); Colibri CAN_INT + */ + gpio-dte { + nvidia,pins = "dte"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* NAND (On-module) */ + nand { + nvidia,pins = "kbca", "kbcc", "kbcd", + "kbce", "kbcf"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* Onewire (Optional) */ + owr { + nvidia,pins = "owc"; + nvidia,function = "owr"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* Power I2C (On-module) */ + i2cp { + nvidia,pins = "i2cp"; + nvidia,function = "i2cp"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* + * SPI1 (Optional) + * Note: spid and spie used for Colibri Address/Data + * Bus (GMI) + */ + spi1 { + nvidia,pins = "spid", "spie", "spif"; + nvidia,function = "spi1"; nvidia,pull = ; nvidia,tristate = ; }; -- cgit v1.2.2 From 992cf09b14e391748c46add889e4249603fa3a39 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sun, 2 Sep 2018 12:08:44 +0200 Subject: ARM: tegra: colibri_t20: add missing pinmux Explicitly add pinmux' for all T20 SoC ball groups now: - Colibri Address/Data Bus (GMI) further pins used as GPIOs - Colibri BL_ON - Colibri EXT_IO* - Colibri L_BIAS, LCD_M1 is muxed with LCD_DE today's display need DE, disable LCD_M1 - more Colibri LCD pins (L_* resp. LDD<*>) - Colibri LCD (Optional 24 BPP Support) - Colibri MMCCD - uart_a_dsr and uart_a_dcd as GPIOs - Colibri USB_CDET - I2C3 (Optional) - JTAG_RTCK - LAN_RESET, LAN_EXT_WAKEUP and LAN_PME (All On-module) - more NAND pins - RESET_OUT - THERMD_ALERT# (On-module), unlatched I2C address pin of LM95245 temperature sensor therefore requires disabling for now Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-colibri-iris.dts | 40 +++++++++ arch/arm/boot/dts/tegra20-colibri.dtsi | 134 +++++++++++++++++++++++++---- 2 files changed, 159 insertions(+), 15 deletions(-) diff --git a/arch/arm/boot/dts/tegra20-colibri-iris.dts b/arch/arm/boot/dts/tegra20-colibri-iris.dts index e026478b58d0..28386b89d910 100644 --- a/arch/arm/boot/dts/tegra20-colibri-iris.dts +++ b/arch/arm/boot/dts/tegra20-colibri-iris.dts @@ -29,6 +29,10 @@ pinmux@70000014 { state_default: pinmux { + bl-on { + nvidia,tristate = ; + }; + ddc { nvidia,tristate = ; }; @@ -37,10 +41,38 @@ nvidia,tristate = ; }; + i2c { + nvidia,tristate = ; + }; + + lcd { + nvidia,tristate = ; + }; + + lm1 { + nvidia,tristate = ; + }; + mmc { nvidia,tristate = ; }; + mmccd { + nvidia,tristate = ; + }; + + pwm-a-b { + nvidia,tristate = ; + }; + + pwm-c-d { + nvidia,tristate = ; + }; + + ssp { + nvidia,tristate = ; + }; + uart-a { nvidia,tristate = ; }; @@ -48,6 +80,14 @@ uart-b { nvidia,tristate = ; }; + + uart-c { + nvidia,tristate = ; + }; + + usbh-pen { + nvidia,tristate = ; + }; }; }; diff --git a/arch/arm/boot/dts/tegra20-colibri.dtsi b/arch/arm/boot/dts/tegra20-colibri.dtsi index dfe237cea14b..aa2ca3dad32c 100644 --- a/arch/arm/boot/dts/tegra20-colibri.dtsi +++ b/arch/arm/boot/dts/tegra20-colibri.dtsi @@ -75,20 +75,36 @@ nvidia,tristate = ; }; - /* Colibri Address/Data Bus (GMI) */ - gpio-gmi { - nvidia,pins = "ata", "atc", "atd", "ate", - "dap1", "dap2", "dap4", "gpu", "irrx", - "irtx", "spia", "spib", "spic"; + /* + * Colibri Address/Data Bus (GMI) + * Note: spid and spie optionally used for SPI1 + */ + gmi { + nvidia,pins = "atc", "atd", "ate", "dap1", + "dap2", "dap4", "gmd", "gpu", + "irrx", "irtx", "spia", "spib", + "spic", "spid", "spie", "uca", + "ucb"; nvidia,function = "gmi"; nvidia,pull = ; - nvidia,tristate = ; + nvidia,tristate = ; + }; + /* Further pins may be used as GPIOs */ + gmi-gpio1 { + nvidia,pins = "lpw0", "lsc1", "lsck", "lsda"; + nvidia,function = "hdmi"; + nvidia,tristate = ; + }; + gmi-gpio2 { + nvidia,pins = "lcsn", "ldc", "lm0", "lsdi"; + nvidia,function = "rsvd4"; + nvidia,tristate = ; }; /* Colibri BL_ON */ bl-on { nvidia,pins = "dta"; - nvidia,function = "vi"; + nvidia,function = "rsvd1"; nvidia,pull = ; nvidia,tristate = ; }; @@ -113,8 +129,8 @@ * Note: dtf optionally used for I2C3 */ ext-io { - nvidia,pins = "dtf"; - nvidia,function = "i2c3"; + nvidia,pins = "dtf", "spdi"; + nvidia,function = "rsvd2"; nvidia,pull = ; nvidia,tristate = ; }; @@ -151,15 +167,31 @@ nvidia,tristate = ; }; + /* + * Colibri L_BIAS, LCD_M1 is muxed with LCD_DE + * today's display need DE, disable LCD_M1 + */ + lm1 { + nvidia,pins = "lm1"; + nvidia,function = "rsvd3"; + nvidia,tristate = ; + }; + /* Colibri LCD (L_* resp. LDD<*>) */ lcd { nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", "ld5", "ld6", "ld7", "ld8", "ld9", "ld10", "ld11", "ld12", "ld13", "ld14", "ld15", - "ld16", "ld17", "lhs", "lpw0", - "lpw2", "lsc0", "lsc1", "lsck", - "lsda", "lspi", "lvs"; + "ld16", "ld17", "lhs", "lsc0", + "lspi", "lvs"; + nvidia,function = "displaya"; + nvidia,tristate = ; + }; + /* Colibri LCD (Optional 24 BPP Support) */ + lcd-24 { + nvidia,pins = "ldi", "lhp0", "lhp1", "lhp2", + "lpp", "lvp1"; nvidia,function = "displaya"; nvidia,tristate = ; }; @@ -172,6 +204,14 @@ nvidia,tristate = ; }; + /* Colibri MMCCD */ + mmccd { + nvidia,pins = "gmb"; + nvidia,function = "gmi_int"; + nvidia,pull = ; + nvidia,tristate = ; + }; + /* Colibri MMC (Optional 8-bit) */ mmc-8bit { nvidia,pins = "gme"; @@ -220,6 +260,16 @@ nvidia,pull = ; nvidia,tristate = ; }; + uart-a-dsr { + nvidia,pins = "lpw1"; + nvidia,function = "rsvd3"; + nvidia,tristate = ; + }; + uart-a-dcd { + nvidia,pins = "lpw2"; + nvidia,function = "hdmi"; + nvidia,tristate = ; + }; /* Colibri UART-B */ uart-b { @@ -237,12 +287,20 @@ nvidia,tristate = ; }; + /* Colibri USB_CDET */ + usb-cdet { + nvidia,pins = "spdo"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + }; + /* Colibri USBH_OC */ usbh-oc { nvidia,pins = "spih"; nvidia,function = "spi2_alt"; nvidia,pull = ; - nvidia,tristate = ; + nvidia,tristate = ; }; /* Colibri USBH_PEN */ @@ -250,7 +308,7 @@ nvidia,pins = "spig"; nvidia,function = "spi2_alt"; nvidia,pull = ; - nvidia,tristate = ; + nvidia,tristate = ; }; /* Colibri VGA not supported */ @@ -261,6 +319,33 @@ nvidia,tristate = ; }; + /* I2C3 (Optional) */ + i2c3 { + nvidia,pins = "dtf"; + nvidia,function = "i2c3"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* JTAG_RTCK */ + jtag-rtck { + nvidia,pins = "gpu7"; + nvidia,function = "rtck"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + /* + * LAN_RESET, LAN_EXT_WAKEUP and LAN_PME + * (All On-module) + */ + gpio-gpv { + nvidia,pins = "gpv"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + }; + /* * LAN_V_BUS, VDD_FAULT, BATT_FAULT, WM9712 PENDOWN * (All On-module); Colibri CAN_INT @@ -274,7 +359,7 @@ /* NAND (On-module) */ nand { - nvidia,pins = "kbca", "kbcc", "kbcd", + nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", "kbce", "kbcf"; nvidia,function = "nand"; nvidia,pull = ; @@ -297,6 +382,14 @@ nvidia,tristate = ; }; + /* RESET_OUT */ + reset-out { + nvidia,pins = "ata"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + }; + /* * SPI1 (Optional) * Note: spid and spie used for Colibri Address/Data @@ -308,6 +401,17 @@ nvidia,pull = ; nvidia,tristate = ; }; + + /* + * THERMD_ALERT# (On-module), unlatched I2C address pin + * of LM95245 temperature sensor therefore requires + * disabling for now + */ + lvp0 { + nvidia,pins = "lvp0"; + nvidia,function = "rsvd3"; + nvidia,tristate = ; + }; }; }; -- cgit v1.2.2 From 9a796cd295edfc0235b3936dd3172467c01ff30c Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sun, 2 Sep 2018 12:08:45 +0200 Subject: ARM: tegra: colibri_t20: iris: display controller rgb panel support Add display controller parallel RGB panel support incl. backlight PWM. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-colibri-iris.dts | 31 ++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm/boot/dts/tegra20-colibri-iris.dts b/arch/arm/boot/dts/tegra20-colibri-iris.dts index 28386b89d910..21713b7ae978 100644 --- a/arch/arm/boot/dts/tegra20-colibri-iris.dts +++ b/arch/arm/boot/dts/tegra20-colibri-iris.dts @@ -21,6 +21,13 @@ }; host1x@50000000 { + dc@54200000 { + rgb { + status = "okay"; + nvidia,panel = <&panel>; + }; + }; + hdmi@54280000 { status = "okay"; hdmi-supply = <®_5v0>; @@ -99,6 +106,10 @@ status = "okay"; }; + pwm@7000a000 { + status = "okay"; + }; + /* * GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier * board) @@ -149,6 +160,26 @@ no-1-8-v; }; + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = <255 128 64 32 16 8 4 0>; + default-brightness-level = <6>; + /* BL_ON */ + enable-gpios = <&gpio TEGRA_GPIO(T, 4) GPIO_ACTIVE_HIGH>; + power-supply = <®_3v3>; + pwms = <&pwm 0 5000000>; /* PWM */ + }; + + panel: panel { + /* + * edt,et057090dhu: EDT 5.7" LCD TFT + * edt,et070080dh6: EDT 7.0" LCD TFT + */ + compatible = "edt,et057090dhu", "simple-panel"; + backlight = <&backlight>; + power-supply = <®_3v3>; + }; + reg_3v3: regulator-3v3 { compatible = "regulator-fixed"; regulator-name = "3.3V"; -- cgit v1.2.2 From 9ccaf9466b9ca2421db98a8430e3d6de2079b1bf Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sun, 2 Sep 2018 12:08:46 +0200 Subject: ARM: tegra: colibri_t20: iris: annotate uarts Annotate UART-A and UART-B. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-colibri-iris.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/tegra20-colibri-iris.dts b/arch/arm/boot/dts/tegra20-colibri-iris.dts index 21713b7ae978..cb3c82287223 100644 --- a/arch/arm/boot/dts/tegra20-colibri-iris.dts +++ b/arch/arm/boot/dts/tegra20-colibri-iris.dts @@ -98,10 +98,12 @@ }; }; + /* Colibri UART-A */ serial@70006000 { status = "okay"; }; + /* Colibri UART-B */ serial@70006300 { status = "okay"; }; -- cgit v1.2.2 From 0d3fda4609e8ae447d44fb29fd0ccd259c6e0b0d Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sun, 2 Sep 2018 12:08:47 +0200 Subject: ARM: tegra: colibri_t20: iris: add uart-c Add UART-C. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-colibri-iris.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/tegra20-colibri-iris.dts b/arch/arm/boot/dts/tegra20-colibri-iris.dts index cb3c82287223..cb7b11567437 100644 --- a/arch/arm/boot/dts/tegra20-colibri-iris.dts +++ b/arch/arm/boot/dts/tegra20-colibri-iris.dts @@ -103,6 +103,11 @@ status = "okay"; }; + /* Colibri UART-C */ + serial@70006040 { + status = "okay"; + }; + /* Colibri UART-B */ serial@70006300 { status = "okay"; -- cgit v1.2.2 From 9ad510b33e1779a0263fcb49bc199727208477cf Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sun, 2 Sep 2018 12:08:48 +0200 Subject: ARM: tegra: colibri_t20: use high speed uart driver Use high speed UART driver compatible nvidia,tegra20-hsuart. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-colibri.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/tegra20-colibri.dtsi b/arch/arm/boot/dts/tegra20-colibri.dtsi index aa2ca3dad32c..86bfe77d9230 100644 --- a/arch/arm/boot/dts/tegra20-colibri.dtsi +++ b/arch/arm/boot/dts/tegra20-colibri.dtsi @@ -423,6 +423,14 @@ <&gpio TEGRA_GPIO(P, 0) GPIO_ACTIVE_HIGH>; }; + serial@70006040 { + compatible = "nvidia,tegra20-hsuart"; + }; + + serial@70006300 { + compatible = "nvidia,tegra20-hsuart"; + }; + nand-controller@70008000 { status = "okay"; -- cgit v1.2.2 From ccf7f6d42790c3e7fc0bb8747f38514f708f267f Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sun, 2 Sep 2018 12:08:49 +0200 Subject: ARM: tegra: colibri_t20: iris: add gpio wakeup key Add SODIMM pin 45 as GPIO wakeup key. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-colibri-iris.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm/boot/dts/tegra20-colibri-iris.dts b/arch/arm/boot/dts/tegra20-colibri-iris.dts index cb7b11567437..5b25e4b38a69 100644 --- a/arch/arm/boot/dts/tegra20-colibri-iris.dts +++ b/arch/arm/boot/dts/tegra20-colibri-iris.dts @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /dts-v1/; +#include #include "tegra20-colibri.dtsi" / { @@ -177,6 +178,18 @@ pwms = <&pwm 0 5000000>; /* PWM */ }; + gpio-keys { + compatible = "gpio-keys"; + + wakeup { + label = "SODIMM pin 45 wakeup"; + gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>; + linux,code = ; + debounce-interval = <10>; + wakeup-source; + }; + }; + panel: panel { /* * edt,et057090dhu: EDT 5.7" LCD TFT -- cgit v1.2.2 From 9b41e68af99adca6f77940c5a8c2e6c3db5c67cc Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sun, 2 Sep 2018 12:08:50 +0200 Subject: ARM: tegra: colibri_t20: iris: add dr_mode property Add dr_mode property to the USB controller. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-colibri-iris.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/tegra20-colibri-iris.dts b/arch/arm/boot/dts/tegra20-colibri-iris.dts index 5b25e4b38a69..7a7530820188 100644 --- a/arch/arm/boot/dts/tegra20-colibri-iris.dts +++ b/arch/arm/boot/dts/tegra20-colibri-iris.dts @@ -145,6 +145,7 @@ /* EHCI instance 0: USB1_DP/N -> USBC_P/N */ usb@c5000000 { status = "okay"; + dr_mode = "otg"; }; usb-phy@c5000000 { -- cgit v1.2.2 From df2be1ae626a0e748f5266e6a7a5134a19490617 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sun, 2 Sep 2018 12:08:51 +0200 Subject: ARM: tegra: colibri_t20: annotate/rename lm95245 temperature sensor Rename and annotate LM95245 temperature sensor more in-line with our other device trees. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-colibri.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra20-colibri.dtsi b/arch/arm/boot/dts/tegra20-colibri.dtsi index 86bfe77d9230..477d67ff74c6 100644 --- a/arch/arm/boot/dts/tegra20-colibri.dtsi +++ b/arch/arm/boot/dts/tegra20-colibri.dtsi @@ -584,7 +584,8 @@ }; }; - temperature-sensor@4c { + /* LM95245 temperature sensor */ + temp-sensor@4c { compatible = "national,lm95245"; reg = <0x4c>; }; -- cgit v1.2.2 From d5178bb6f86084eff4ccaf322775b9d558bbd326 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sun, 2 Sep 2018 12:08:52 +0200 Subject: ARM: tegra: colibri_t20: add i2c-thermtrip Add i2c-thermtrip which would set the SLEEP MODE bit in the SUPPLYENE register of the TPS658643 PMIC. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-colibri.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/tegra20-colibri.dtsi b/arch/arm/boot/dts/tegra20-colibri.dtsi index 477d67ff74c6..9ec56f49c30c 100644 --- a/arch/arm/boot/dts/tegra20-colibri.dtsi +++ b/arch/arm/boot/dts/tegra20-colibri.dtsi @@ -598,6 +598,14 @@ nvidia,core-pwr-good-time = <3845 3845>; nvidia,core-pwr-off-time = <3875>; nvidia,sys-clock-req-active-high; + + /* Set SLEEP MODE bit in SUPPLYENE register of TPS658643 PMIC */ + i2c-thermtrip { + nvidia,i2c-controller-id = <3>; + nvidia,bus-addr = <0x34>; + nvidia,reg-addr = <0x14>; + nvidia,reg-data = <0x8>; + }; }; memory-controller@7000f400 { -- cgit v1.2.2 From 0b51e73ba1e9d4ae6564449e7434f958839779f7 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sun, 2 Sep 2018 12:08:53 +0200 Subject: ARM: tegra: colibri_t20: add gpio hog to unreset usb ethernet chip Add GPIO hog to unreset ASIX AX88772B USB Ethernet chip. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-colibri.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/tegra20-colibri.dtsi b/arch/arm/boot/dts/tegra20-colibri.dtsi index 9ec56f49c30c..281e0dd11565 100644 --- a/arch/arm/boot/dts/tegra20-colibri.dtsi +++ b/arch/arm/boot/dts/tegra20-colibri.dtsi @@ -749,3 +749,12 @@ clock-names = "pll_a", "pll_a_out0", "mclk"; }; }; + +&gpio { + lan-reset-n { + gpio-hog; + gpios = ; + output-high; + line-name = "LAN_RESET#"; + }; +}; -- cgit v1.2.2 From 351c72c8323589351090504515d081384c3ea705 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sun, 2 Sep 2018 12:08:54 +0200 Subject: ARM: tegra: colibri_t20: add gpio hogs for gmi_wr_n buffers Add GPIO hogs for GMI_WR_N buffers: - tri-stating GMI_WR_N on SODIMM pin 99 nPWE - not tri-stating GMI_WR_N on SODIMM pin 93 RDnWR Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-colibri.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/tegra20-colibri.dtsi b/arch/arm/boot/dts/tegra20-colibri.dtsi index 281e0dd11565..aba56b447bcd 100644 --- a/arch/arm/boot/dts/tegra20-colibri.dtsi +++ b/arch/arm/boot/dts/tegra20-colibri.dtsi @@ -757,4 +757,20 @@ output-high; line-name = "LAN_RESET#"; }; + + /* Tri-stating GMI_WR_N on SODIMM pin 99 nPWE */ + npwe { + gpio-hog; + gpios = ; + output-high; + line-name = "Tri-state nPWE"; + }; + + /* Not tri-stating GMI_WR_N on SODIMM pin 93 RDnWR */ + rdnwr { + gpio-hog; + gpios = ; + output-low; + line-name = "Not tri-state RDnWR"; + }; }; -- cgit v1.2.2 From 88fd676b158a72fb0bab4d29b53012316b40f7f4 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sun, 2 Sep 2018 12:08:55 +0200 Subject: ARM: tegra: colibri_t20: annotate/move sd card detect Annotate the SD card, its detect pin and move the SD card detect GPIO definition from the module to the carrier board more in-line with our other device trees. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-colibri-iris.dts | 2 ++ arch/arm/boot/dts/tegra20-colibri.dtsi | 4 ---- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/tegra20-colibri-iris.dts b/arch/arm/boot/dts/tegra20-colibri-iris.dts index 7a7530820188..1583d5118302 100644 --- a/arch/arm/boot/dts/tegra20-colibri-iris.dts +++ b/arch/arm/boot/dts/tegra20-colibri-iris.dts @@ -163,9 +163,11 @@ vbus-supply = <®_usbh_vbus>; }; + /* SD/MMC */ sdhci@c8000600 { status = "okay"; bus-width = <4>; + cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>; /* MMCD */ no-1-8-v; }; diff --git a/arch/arm/boot/dts/tegra20-colibri.dtsi b/arch/arm/boot/dts/tegra20-colibri.dtsi index aba56b447bcd..6b82485ff58e 100644 --- a/arch/arm/boot/dts/tegra20-colibri.dtsi +++ b/arch/arm/boot/dts/tegra20-colibri.dtsi @@ -698,10 +698,6 @@ vbus-supply = <®_lan_v_bus>; }; - sdhci@c8000600 { - cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>; - }; - clocks { compatible = "simple-bus"; #address-cells = <1>; -- cgit v1.2.2 From 6a4a865d1cc6656bea4a017e7537a5315972e692 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sun, 2 Sep 2018 12:08:56 +0200 Subject: ARM: tegra: colibri_t20: add compatibility comment Add compatibility comment. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-colibri.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/tegra20-colibri.dtsi b/arch/arm/boot/dts/tegra20-colibri.dtsi index 6b82485ff58e..ea785f65c89f 100644 --- a/arch/arm/boot/dts/tegra20-colibri.dtsi +++ b/arch/arm/boot/dts/tegra20-colibri.dtsi @@ -1,6 +1,12 @@ // SPDX-License-Identifier: GPL-2.0 #include "tegra20.dtsi" +/* + * Toradex Colibri T20 Module Device Tree + * Compatible for Revisions Colibri T20 256MB V1.1B, V1.2A; + * Colibri T20 256MB IT V1.2A; Colibri T20 512MB V1.1C, V1.2A; + * Colibri T20 512MB IT V1.2A + */ / { model = "Toradex Colibri T20 256/512 MB"; compatible = "toradex,colibri_t20-512", "nvidia,tegra20"; -- cgit v1.2.2 From 4f135281b32362a672fee7ddb5a356e600fb9ce4 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sun, 2 Sep 2018 12:08:57 +0200 Subject: ARM: tegra: colibri_t20: simplify model and compatible properties Simplify model and compatible by dropping the 256/512 MB from the model and -512 from the compatible properties to be more in-line with all our other device trees. Signed-off-by: Marcel Ziswiler Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/arm/tegra.txt | 2 +- arch/arm/boot/dts/tegra20-colibri-iris.dts | 4 ++-- arch/arm/boot/dts/tegra20-colibri.dtsi | 4 ++-- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/tegra.txt b/Documentation/devicetree/bindings/arm/tegra.txt index 1c90cb32da19..5e1b0b30ece2 100644 --- a/Documentation/devicetree/bindings/arm/tegra.txt +++ b/Documentation/devicetree/bindings/arm/tegra.txt @@ -53,7 +53,7 @@ board-specific compatible values: toradex,apalis-tk1-eval toradex,apalis-tk1-v1.2 toradex,apalis-tk1-v1.2-eval - toradex,colibri_t20-512 + toradex,colibri_t20 toradex,colibri_t30 toradex,colibri_t30-eval-v3 toradex,iris diff --git a/arch/arm/boot/dts/tegra20-colibri-iris.dts b/arch/arm/boot/dts/tegra20-colibri-iris.dts index 1583d5118302..cd47ac5b528f 100644 --- a/arch/arm/boot/dts/tegra20-colibri-iris.dts +++ b/arch/arm/boot/dts/tegra20-colibri-iris.dts @@ -5,8 +5,8 @@ #include "tegra20-colibri.dtsi" / { - model = "Toradex Colibri T20 256/512 MB on Iris"; - compatible = "toradex,iris", "toradex,colibri_t20-512", "nvidia,tegra20"; + model = "Toradex Colibri T20 on Iris"; + compatible = "toradex,iris", "toradex,colibri_t20", "nvidia,tegra20"; aliases { rtc0 = "/i2c@7000c000/rtc@68"; diff --git a/arch/arm/boot/dts/tegra20-colibri.dtsi b/arch/arm/boot/dts/tegra20-colibri.dtsi index ea785f65c89f..53e06f31dbea 100644 --- a/arch/arm/boot/dts/tegra20-colibri.dtsi +++ b/arch/arm/boot/dts/tegra20-colibri.dtsi @@ -8,8 +8,8 @@ * Colibri T20 512MB IT V1.2A */ / { - model = "Toradex Colibri T20 256/512 MB"; - compatible = "toradex,colibri_t20-512", "nvidia,tegra20"; + model = "Toradex Colibri T20"; + compatible = "toradex,colibri_t20", "nvidia,tegra20"; memory@0 { /* -- cgit v1.2.2 From a7867ac8a11465be32324d896d81426f534b9a61 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sun, 2 Sep 2018 12:08:58 +0200 Subject: ARM: tegra: colibri_t20: iris: simplify model and compatible properties Simplify model and compatible by dropping the 256/512 MB from the model, -512 from the compatible and rename that property from toradex,iris to toradex,colibri_t20-iris to be more in-line with all our other device trees. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/arm/tegra.txt | 2 +- arch/arm/boot/dts/tegra20-colibri-iris.dts | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/tegra.txt b/Documentation/devicetree/bindings/arm/tegra.txt index 5e1b0b30ece2..0909122a2bee 100644 --- a/Documentation/devicetree/bindings/arm/tegra.txt +++ b/Documentation/devicetree/bindings/arm/tegra.txt @@ -54,9 +54,9 @@ board-specific compatible values: toradex,apalis-tk1-v1.2 toradex,apalis-tk1-v1.2-eval toradex,colibri_t20 + toradex,colibri_t20-iris toradex,colibri_t30 toradex,colibri_t30-eval-v3 - toradex,iris Trusted Foundations ------------------------------------------- diff --git a/arch/arm/boot/dts/tegra20-colibri-iris.dts b/arch/arm/boot/dts/tegra20-colibri-iris.dts index cd47ac5b528f..dbdf596dd151 100644 --- a/arch/arm/boot/dts/tegra20-colibri-iris.dts +++ b/arch/arm/boot/dts/tegra20-colibri-iris.dts @@ -6,7 +6,8 @@ / { model = "Toradex Colibri T20 on Iris"; - compatible = "toradex,iris", "toradex,colibri_t20", "nvidia,tegra20"; + compatible = "toradex,colibri_t20-iris", "toradex,colibri_t20", + "nvidia,tegra20"; aliases { rtc0 = "/i2c@7000c000/rtc@68"; -- cgit v1.2.2 From 463a8f714af25dc93b6b4851fdf7c83676c61289 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sun, 2 Sep 2018 12:08:59 +0200 Subject: ARM: tegra: colibri_t20: iris: add colibri ssp support Add Colibri SSP aka SPI support using the SPI4 instance. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-colibri-iris.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/tegra20-colibri-iris.dts b/arch/arm/boot/dts/tegra20-colibri-iris.dts index dbdf596dd151..b16e04dfa31f 100644 --- a/arch/arm/boot/dts/tegra20-colibri-iris.dts +++ b/arch/arm/boot/dts/tegra20-colibri-iris.dts @@ -164,6 +164,12 @@ vbus-supply = <®_usbh_vbus>; }; + /* SPI4: Colibri SSP */ + spi@7000da00 { + status = "okay"; + spi-max-frequency = <25000000>; + }; + /* SD/MMC */ sdhci@c8000600 { status = "okay"; -- cgit v1.2.2 From 6a32a913bff31f148eb4e129be78afb55fa32467 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sun, 2 Sep 2018 12:09:00 +0200 Subject: ARM: tegra: colibri_t20: drop module level model and compatible Drop model and compatible nodes from the module level device tree as they get overridden by the carrier board device tree anyway. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-colibri.dtsi | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm/boot/dts/tegra20-colibri.dtsi b/arch/arm/boot/dts/tegra20-colibri.dtsi index 53e06f31dbea..b4d429f672da 100644 --- a/arch/arm/boot/dts/tegra20-colibri.dtsi +++ b/arch/arm/boot/dts/tegra20-colibri.dtsi @@ -8,9 +8,6 @@ * Colibri T20 512MB IT V1.2A */ / { - model = "Toradex Colibri T20"; - compatible = "toradex,colibri_t20", "nvidia,tegra20"; - memory@0 { /* * Set memory to 256 MB to be safe as this could be used on -- cgit v1.2.2 From 82e7ceccf2c3902549fdf75bf494fbe3e3e236a4 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sun, 2 Sep 2018 12:09:01 +0200 Subject: ARM: tegra: colibri_t20: rename i2c_ddc to hdmi_ddc Rename i2c_ddc to hdmi_ddc to be more in-line with other device trees. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-colibri.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/tegra20-colibri.dtsi b/arch/arm/boot/dts/tegra20-colibri.dtsi index b4d429f672da..36463fb3c0b3 100644 --- a/arch/arm/boot/dts/tegra20-colibri.dtsi +++ b/arch/arm/boot/dts/tegra20-colibri.dtsi @@ -19,7 +19,7 @@ host1x@50000000 { hdmi@54280000 { - nvidia,ddc-i2c-bus = <&i2c_ddc>; + nvidia,ddc-i2c-bus = <&hdmi_ddc>; nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; pll-supply = <®_1v8_avdd_hdmi_pll>; @@ -459,7 +459,7 @@ }; /* DDC_SCL/SDA on X3 pin 15/16 (e.g. display EDID) */ - i2c_ddc: i2c@7000c400 { + hdmi_ddc: i2c@7000c400 { clock-frequency = <10000>; }; -- cgit v1.2.2 From 613953abdf65789eddbdcde7880de88155f7516a Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sun, 2 Sep 2018 12:09:02 +0200 Subject: ARM: tegra: colibri_t20: iris: drop unused i2c_ddc label Drop unused i2c_ddc label. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-colibri-iris.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra20-colibri-iris.dts b/arch/arm/boot/dts/tegra20-colibri-iris.dts index b16e04dfa31f..00fd2603d780 100644 --- a/arch/arm/boot/dts/tegra20-colibri-iris.dts +++ b/arch/arm/boot/dts/tegra20-colibri-iris.dts @@ -139,7 +139,7 @@ /* CAM_I2C (I2C3): unused */ /* DDC_CLOCK/DATA on X3 pin 15/16 (e.g. display EDID) */ - i2c_ddc: i2c@7000c400 { + i2c@7000c400 { status = "okay"; }; -- cgit v1.2.2 From 8f4a8e0931b8e57a6a962c8cf89796b715aba37c Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sun, 2 Sep 2018 12:09:03 +0200 Subject: ARM: tegra: colibri_t20: rename tps6586x@34 and drop unused pmic label Rename tps6586x@34 to pmic@34 and drop the unused pmic label. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-colibri-iris.dts | 2 +- arch/arm/boot/dts/tegra20-colibri.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/tegra20-colibri-iris.dts b/arch/arm/boot/dts/tegra20-colibri-iris.dts index 00fd2603d780..d8004d68efa0 100644 --- a/arch/arm/boot/dts/tegra20-colibri-iris.dts +++ b/arch/arm/boot/dts/tegra20-colibri-iris.dts @@ -11,7 +11,7 @@ aliases { rtc0 = "/i2c@7000c000/rtc@68"; - rtc1 = "/i2c@7000d000/tps6586x@34"; + rtc1 = "/i2c@7000d000/pmic@34"; rtc2 = "/rtc@7000e000"; serial0 = &uarta; serial1 = &uartd; diff --git a/arch/arm/boot/dts/tegra20-colibri.dtsi b/arch/arm/boot/dts/tegra20-colibri.dtsi index 36463fb3c0b3..473f32f20d8d 100644 --- a/arch/arm/boot/dts/tegra20-colibri.dtsi +++ b/arch/arm/boot/dts/tegra20-colibri.dtsi @@ -472,7 +472,7 @@ status = "okay"; clock-frequency = <100000>; - pmic: tps6586x@34 { + pmic@34 { compatible = "ti,tps6586x"; reg = <0x34>; interrupts = ; -- cgit v1.2.2 From cafed755d5f31ef7bf26f04d87a27ee02b9d036d Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sun, 2 Sep 2018 12:09:04 +0200 Subject: ARM: tegra: colibri_t20: get rid of fake clocks simple bus Get rid of the fake clocks simple bus and use node names as per the actual schematics. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-colibri.dtsi | 15 ++++----------- 1 file changed, 4 insertions(+), 11 deletions(-) diff --git a/arch/arm/boot/dts/tegra20-colibri.dtsi b/arch/arm/boot/dts/tegra20-colibri.dtsi index 473f32f20d8d..243615f6c349 100644 --- a/arch/arm/boot/dts/tegra20-colibri.dtsi +++ b/arch/arm/boot/dts/tegra20-colibri.dtsi @@ -701,17 +701,10 @@ vbus-supply = <®_lan_v_bus>; }; - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; + clk32k_in: xtal3 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; }; reg_lan_v_bus: regulator-lan-v-bus { -- cgit v1.2.2 From 5373f80201fbb05a9a5a29f061e8500b2df91bfb Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sun, 2 Sep 2018 12:09:05 +0200 Subject: ARM: tegra: colibri_t20: rename ac97 label to tegra_ac97 Rename ac97 label to tegra_ac97 to be more in-line with the device tree binding documentation. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-colibri.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/tegra20-colibri.dtsi b/arch/arm/boot/dts/tegra20-colibri.dtsi index 243615f6c349..6162d193e12c 100644 --- a/arch/arm/boot/dts/tegra20-colibri.dtsi +++ b/arch/arm/boot/dts/tegra20-colibri.dtsi @@ -418,7 +418,7 @@ }; }; - ac97: ac97@70002000 { + tegra_ac97: ac97@70002000 { status = "okay"; nvidia,codec-reset-gpio = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_HIGH>; @@ -734,7 +734,7 @@ "LineIn", "LINEINL", "LineIn", "LINEINR", "Mic", "MIC1"; - nvidia,ac97-controller = <&ac97>; + nvidia,ac97-controller = <&tegra_ac97>; clocks = <&tegra_car TEGRA20_CLK_PLL_A>, <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, <&tegra_car TEGRA20_CLK_CDEV1>; -- cgit v1.2.2 From fee8cdc2df088fa2ee4b7f86a803918a3664a26b Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sun, 2 Sep 2018 12:09:06 +0200 Subject: ARM: tegra: colibri_t20: add eval board device tree Add an evaluation board device tree more in-line with all our other device trees. Signed-off-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/arm/tegra.txt | 1 + arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/tegra20-colibri-eval-v3.dts | 262 ++++++++++++++++++++++++ 3 files changed, 264 insertions(+) create mode 100644 arch/arm/boot/dts/tegra20-colibri-eval-v3.dts diff --git a/Documentation/devicetree/bindings/arm/tegra.txt b/Documentation/devicetree/bindings/arm/tegra.txt index 0909122a2bee..c59b15f64346 100644 --- a/Documentation/devicetree/bindings/arm/tegra.txt +++ b/Documentation/devicetree/bindings/arm/tegra.txt @@ -54,6 +54,7 @@ board-specific compatible values: toradex,apalis-tk1-v1.2 toradex,apalis-tk1-v1.2-eval toradex,colibri_t20 + toradex,colibri_t20-eval-v3 toradex,colibri_t20-iris toradex,colibri_t30 toradex,colibri_t30-eval-v3 diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 9d6d7790d627..d89c31088158 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1061,6 +1061,7 @@ dtb-$(CONFIG_ARCH_TANGO) += \ tango4-vantage-1172.dtb dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \ tegra20-harmony.dtb \ + tegra20-colibri-eval-v3.dtb \ tegra20-colibri-iris.dtb \ tegra20-medcom-wide.dtb \ tegra20-paz00.dtb \ diff --git a/arch/arm/boot/dts/tegra20-colibri-eval-v3.dts b/arch/arm/boot/dts/tegra20-colibri-eval-v3.dts new file mode 100644 index 000000000000..3c0f2681fcde --- /dev/null +++ b/arch/arm/boot/dts/tegra20-colibri-eval-v3.dts @@ -0,0 +1,262 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/dts-v1/; + +#include +#include "tegra20-colibri.dtsi" + +/ { + model = "Toradex Colibri T20 on Colibri Evaluation Board"; + compatible = "toradex,colibri_t20-eval-v3", "toradex,colibri_t20", + "nvidia,tegra20"; + + aliases { + rtc0 = "/i2c@7000c000/rtc@68"; + rtc1 = "/i2c@7000d000/pmic@34"; + rtc2 = "/rtc@7000e000"; + serial0 = &uarta; + serial1 = &uartd; + serial2 = &uartb; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + host1x@50000000 { + dc@54200000 { + rgb { + status = "okay"; + nvidia,panel = <&panel>; + }; + }; + + hdmi@54280000 { + status = "okay"; + hdmi-supply = <®_5v0>; + }; + }; + + pinmux@70000014 { + state_default: pinmux { + bl-on { + nvidia,tristate = ; + }; + + ddc { + nvidia,tristate = ; + }; + + hotplug-detect { + nvidia,tristate = ; + }; + + i2c { + nvidia,tristate = ; + }; + + lcd { + nvidia,tristate = ; + }; + + lm1 { + nvidia,tristate = ; + }; + + mmc { + nvidia,tristate = ; + }; + + mmccd { + nvidia,tristate = ; + }; + + pwm-a-b { + nvidia,tristate = ; + }; + + pwm-c-d { + nvidia,tristate = ; + }; + + ssp { + nvidia,tristate = ; + }; + + uart-a { + nvidia,tristate = ; + }; + + uart-b { + nvidia,tristate = ; + }; + + uart-c { + nvidia,tristate = ; + }; + + usbh-pen { + nvidia,tristate = ; + }; + }; + }; + + /* Colibri UART-A */ + serial@70006000 { + status = "okay"; + }; + + /* Colibri UART-C */ + serial@70006040 { + status = "okay"; + }; + + /* Colibri UART-B */ + serial@70006300 { + status = "okay"; + }; + + pwm@7000a000 { + status = "okay"; + }; + + /* + * GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier + * board) + */ + i2c@7000c000 { + status = "okay"; + clock-frequency = <400000>; + + /* M41T0M6 real time clock on carrier board */ + rtc@68 { + compatible = "st,m41t0"; + reg = <0x68>; + }; + }; + + /* GEN2_I2C: unused */ + + /* CAM_I2C (I2C3): unused */ + + /* DDC_CLOCK/DATA on X3 pin 15/16 (e.g. display EDID) */ + i2c@7000c400 { + status = "okay"; + }; + + /* EHCI instance 0: USB1_DP/N -> USBC_P/N */ + usb@c5000000 { + status = "okay"; + dr_mode = "otg"; + }; + + usb-phy@c5000000 { + status = "okay"; + vbus-supply = <®_usbc_vbus>; + }; + + /* EHCI instance 2: USB3_DP/N -> USBH_P/N */ + usb@c5008000 { + status = "okay"; + }; + + usb-phy@c5008000 { + status = "okay"; + vbus-supply = <®_usbh_vbus>; + }; + + /* SPI4: Colibri SSP */ + spi@7000da00 { + status = "okay"; + spi-max-frequency = <25000000>; + + can@0 { + compatible = "microchip,mcp2515"; + reg = <0>; + clocks = <&clk16m>; + interrupt-parent = <&gpio>; + /* CAN_INT */ + interrupts = ; + spi-max-frequency = <10000000>; + vdd-supply = <®_3v3>; + xceiver-supply = <®_5v0>; + }; + }; + + /* SD/MMC */ + sdhci@c8000600 { + status = "okay"; + bus-width = <4>; + cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>; /* MMCD */ + no-1-8-v; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = <255 128 64 32 16 8 4 0>; + default-brightness-level = <6>; + /* BL_ON */ + enable-gpios = <&gpio TEGRA_GPIO(T, 4) GPIO_ACTIVE_HIGH>; + power-supply = <®_3v3>; + pwms = <&pwm 0 5000000>; /* PWM */ + }; + + clk16m: osc3 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <16000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + wakeup { + label = "SODIMM pin 45 wakeup"; + gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>; + linux,code = ; + debounce-interval = <10>; + wakeup-source; + }; + }; + + panel: panel { + /* + * edt,et057090dhu: EDT 5.7" LCD TFT + * edt,et070080dh6: EDT 7.0" LCD TFT + */ + compatible = "edt,et057090dhu", "simple-panel"; + backlight = <&backlight>; + power-supply = <®_3v3>; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3.3V_SW"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_5v0: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "5V_SW"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usbc_vbus: regulator-usbc-vbus { + compatible = "regulator-fixed"; + regulator-name = "VCC_USB5"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <®_5v0>; + }; + + /* USBH_PEN resp. USB_P_EN */ + reg_usbh_vbus: regulator-usbh-vbus { + compatible = "regulator-fixed"; + regulator-name = "VCC_USB[1-4]"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; + vin-supply = <®_5v0>; + }; +}; -- cgit v1.2.2 From 06d561ca0fa73a5b12ef6dfe0da7053e0ee37315 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 30 Aug 2018 19:21:53 +0200 Subject: ARM: tegra: tegra20: Fix mixed tabs-spaces indentation Fix indentation and alignment when spaces were used instead of tabs. This fixes checkpatch errors like: ERROR: code indent should use tabs where possible #306: FILE: arch/arm/boot/dts/tegra20-paz00.dts:306: +^I^I <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;$ Signed-off-by: Krzysztof Kozlowski Acked-by: Marcel Ziswiler Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-paz00.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts index ef245291924f..7d8aef6ebd3a 100644 --- a/arch/arm/boot/dts/tegra20-paz00.dts +++ b/arch/arm/boot/dts/tegra20-paz00.dts @@ -303,7 +303,7 @@ request-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; slave-addr = <138>; clocks = <&tegra_car TEGRA20_CLK_I2C3>, - <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; + <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; clock-names = "div-clk", "fast-clk"; resets = <&tegra_car 67>; reset-names = "i2c"; @@ -599,8 +599,8 @@ GPIO_ACTIVE_HIGH>; clocks = <&tegra_car TEGRA20_CLK_PLL_A>, - <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA20_CLK_CDEV1>; + <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA20_CLK_CDEV1>; clock-names = "pll_a", "pll_a_out0", "mclk"; }; }; -- cgit v1.2.2 From ebea2a43fdafdbce918bd7e200b709d6c33b9f3b Mon Sep 17 00:00:00 2001 From: Marc Dietrich Date: Thu, 2 Aug 2018 10:45:40 +0200 Subject: ARM: dts: paz00: fix wakeup gpio keycode The power key is controlled solely by the EC, which only tiggeres this gpio after wakeup. Fixes immediately return to suspend after wake from LP1. Signed-off-by: Marc Dietrich Tested-by: Nicolas Chauvet Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-paz00.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts index 7d8aef6ebd3a..8861e0976e37 100644 --- a/arch/arm/boot/dts/tegra20-paz00.dts +++ b/arch/arm/boot/dts/tegra20-paz00.dts @@ -524,10 +524,10 @@ gpio-keys { compatible = "gpio-keys"; - power { - label = "Power"; + wakeup { + label = "Wakeup"; gpios = <&gpio TEGRA_GPIO(J, 7) GPIO_ACTIVE_LOW>; - linux,code = ; + linux,code = ; wakeup-source; }; }; -- cgit v1.2.2