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authorDave Airlie <airlied@redhat.com>2015-08-19 20:35:29 -0400
committerDave Airlie <airlied@redhat.com>2015-08-19 20:35:29 -0400
commitd072f4654464b242e536a03102ebd3d481f6b418 (patch)
treec038b52e85fd4f7288637f62363505c46b044d70
parente2a8986f3e287dc036ce1b9452d7b9e2d8839f2b (diff)
parent5b9fb5e6c6c74666f88f34bd0db183b9c4269d97 (diff)
Merge branch 'drm-atmel-hlcdc-devel' of https://github.com/bbrezillon/linux-at91 into drm-next
The following PR add support for 3 more atmel SoCs and for some missing features (new input formats and PRIME support). * 'drm-atmel-hlcdc-devel' of https://github.com/bbrezillon/linux-at91: drm: atmel-hlcdc: add support for sama5d4 SoCs drm: atmel-hlcdc: add support for at91sam9n12 SoC drm: atmel-hlcdc: add support for at91sam9x5 SoCs drm: atmel-hlcdc: add RGB565 and RGB444 output support drm: atmel-hlcdc: add the missing DRM_ATOMIC flag drm: atmel-hlcdc: add PRIME support
Diffstat
-rw-r--r--drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c216
-rw-r--r--drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_output.c4
2 files changed, 219 insertions, 1 deletions
diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c
index 6fad1f9648f3..e058e0ad3c15 100644
--- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c
+++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c
@@ -29,6 +29,115 @@
29 29
30#define ATMEL_HLCDC_LAYER_IRQS_OFFSET 8 30#define ATMEL_HLCDC_LAYER_IRQS_OFFSET 8
31 31
32static const struct atmel_hlcdc_layer_desc atmel_hlcdc_at91sam9n12_layers[] = {
33 {
34 .name = "base",
35 .formats = &atmel_hlcdc_plane_rgb_formats,
36 .regs_offset = 0x40,
37 .id = 0,
38 .type = ATMEL_HLCDC_BASE_LAYER,
39 .nconfigs = 5,
40 .layout = {
41 .xstride = { 2 },
42 .default_color = 3,
43 .general_config = 4,
44 },
45 },
46};
47
48static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc_at91sam9n12 = {
49 .min_width = 0,
50 .min_height = 0,
51 .max_width = 1280,
52 .max_height = 860,
53 .nlayers = ARRAY_SIZE(atmel_hlcdc_at91sam9n12_layers),
54 .layers = atmel_hlcdc_at91sam9n12_layers,
55};
56
57static const struct atmel_hlcdc_layer_desc atmel_hlcdc_at91sam9x5_layers[] = {
58 {
59 .name = "base",
60 .formats = &atmel_hlcdc_plane_rgb_formats,
61 .regs_offset = 0x40,
62 .id = 0,
63 .type = ATMEL_HLCDC_BASE_LAYER,
64 .nconfigs = 5,
65 .layout = {
66 .xstride = { 2 },
67 .default_color = 3,
68 .general_config = 4,
69 .disc_pos = 5,
70 .disc_size = 6,
71 },
72 },
73 {
74 .name = "overlay1",
75 .formats = &atmel_hlcdc_plane_rgb_formats,
76 .regs_offset = 0x100,
77 .id = 1,
78 .type = ATMEL_HLCDC_OVERLAY_LAYER,
79 .nconfigs = 10,
80 .layout = {
81 .pos = 2,
82 .size = 3,
83 .xstride = { 4 },
84 .pstride = { 5 },
85 .default_color = 6,
86 .chroma_key = 7,
87 .chroma_key_mask = 8,
88 .general_config = 9,
89 },
90 },
91 {
92 .name = "high-end-overlay",
93 .formats = &atmel_hlcdc_plane_rgb_and_yuv_formats,
94 .regs_offset = 0x280,
95 .id = 2,
96 .type = ATMEL_HLCDC_OVERLAY_LAYER,
97 .nconfigs = 17,
98 .layout = {
99 .pos = 2,
100 .size = 3,
101 .memsize = 4,
102 .xstride = { 5, 7 },
103 .pstride = { 6, 8 },
104 .default_color = 9,
105 .chroma_key = 10,
106 .chroma_key_mask = 11,
107 .general_config = 12,
108 .csc = 14,
109 },
110 },
111 {
112 .name = "cursor",
113 .formats = &atmel_hlcdc_plane_rgb_formats,
114 .regs_offset = 0x340,
115 .id = 3,
116 .type = ATMEL_HLCDC_CURSOR_LAYER,
117 .nconfigs = 10,
118 .max_width = 128,
119 .max_height = 128,
120 .layout = {
121 .pos = 2,
122 .size = 3,
123 .xstride = { 4 },
124 .default_color = 6,
125 .chroma_key = 7,
126 .chroma_key_mask = 8,
127 .general_config = 9,
128 },
129 },
130};
131
132static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc_at91sam9x5 = {
133 .min_width = 0,
134 .min_height = 0,
135 .max_width = 800,
136 .max_height = 600,
137 .nlayers = ARRAY_SIZE(atmel_hlcdc_at91sam9x5_layers),
138 .layers = atmel_hlcdc_at91sam9x5_layers,
139};
140
32static const struct atmel_hlcdc_layer_desc atmel_hlcdc_sama5d3_layers[] = { 141static const struct atmel_hlcdc_layer_desc atmel_hlcdc_sama5d3_layers[] = {
33 { 142 {
34 .name = "base", 143 .name = "base",
@@ -132,11 +241,105 @@ static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc_sama5d3 = {
132 .layers = atmel_hlcdc_sama5d3_layers, 241 .layers = atmel_hlcdc_sama5d3_layers,
133}; 242};
134 243
244static const struct atmel_hlcdc_layer_desc atmel_hlcdc_sama5d4_layers[] = {
245 {
246 .name = "base",
247 .formats = &atmel_hlcdc_plane_rgb_formats,
248 .regs_offset = 0x40,
249 .id = 0,
250 .type = ATMEL_HLCDC_BASE_LAYER,
251 .nconfigs = 7,
252 .layout = {
253 .xstride = { 2 },
254 .default_color = 3,
255 .general_config = 4,
256 .disc_pos = 5,
257 .disc_size = 6,
258 },
259 },
260 {
261 .name = "overlay1",
262 .formats = &atmel_hlcdc_plane_rgb_formats,
263 .regs_offset = 0x140,
264 .id = 1,
265 .type = ATMEL_HLCDC_OVERLAY_LAYER,
266 .nconfigs = 10,
267 .layout = {
268 .pos = 2,
269 .size = 3,
270 .xstride = { 4 },
271 .pstride = { 5 },
272 .default_color = 6,
273 .chroma_key = 7,
274 .chroma_key_mask = 8,
275 .general_config = 9,
276 },
277 },
278 {
279 .name = "overlay2",
280 .formats = &atmel_hlcdc_plane_rgb_formats,
281 .regs_offset = 0x240,
282 .id = 2,
283 .type = ATMEL_HLCDC_OVERLAY_LAYER,
284 .nconfigs = 10,
285 .layout = {
286 .pos = 2,
287 .size = 3,
288 .xstride = { 4 },
289 .pstride = { 5 },
290 .default_color = 6,
291 .chroma_key = 7,
292 .chroma_key_mask = 8,
293 .general_config = 9,
294 },
295 },
296 {
297 .name = "high-end-overlay",
298 .formats = &atmel_hlcdc_plane_rgb_and_yuv_formats,
299 .regs_offset = 0x340,
300 .id = 3,
301 .type = ATMEL_HLCDC_OVERLAY_LAYER,
302 .nconfigs = 42,
303 .layout = {
304 .pos = 2,
305 .size = 3,
306 .memsize = 4,
307 .xstride = { 5, 7 },
308 .pstride = { 6, 8 },
309 .default_color = 9,
310 .chroma_key = 10,
311 .chroma_key_mask = 11,
312 .general_config = 12,
313 .csc = 14,
314 },
315 },
316};
317
318static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc_sama5d4 = {
319 .min_width = 0,
320 .min_height = 0,
321 .max_width = 2048,
322 .max_height = 2048,
323 .nlayers = ARRAY_SIZE(atmel_hlcdc_sama5d4_layers),
324 .layers = atmel_hlcdc_sama5d4_layers,
325};
135static const struct of_device_id atmel_hlcdc_of_match[] = { 326static const struct of_device_id atmel_hlcdc_of_match[] = {
136 { 327 {
328 .compatible = "atmel,at91sam9n12-hlcdc",
329 .data = &atmel_hlcdc_dc_at91sam9n12,
330 },
331 {
332 .compatible = "atmel,at91sam9x5-hlcdc",
333 .data = &atmel_hlcdc_dc_at91sam9x5,
334 },
335 {
137 .compatible = "atmel,sama5d3-hlcdc", 336 .compatible = "atmel,sama5d3-hlcdc",
138 .data = &atmel_hlcdc_dc_sama5d3, 337 .data = &atmel_hlcdc_dc_sama5d3,
139 }, 338 },
339 {
340 .compatible = "atmel,sama5d4-hlcdc",
341 .data = &atmel_hlcdc_dc_sama5d4,
342 },
140 { /* sentinel */ }, 343 { /* sentinel */ },
141}; 344};
142 345
@@ -485,7 +688,9 @@ static const struct file_operations fops = {
485}; 688};
486 689
487static struct drm_driver atmel_hlcdc_dc_driver = { 690static struct drm_driver atmel_hlcdc_dc_driver = {
488 .driver_features = DRIVER_HAVE_IRQ | DRIVER_GEM | DRIVER_MODESET, 691 .driver_features = DRIVER_HAVE_IRQ | DRIVER_GEM |
692 DRIVER_MODESET | DRIVER_PRIME |
693 DRIVER_ATOMIC,
489 .preclose = atmel_hlcdc_dc_preclose, 694 .preclose = atmel_hlcdc_dc_preclose,
490 .lastclose = atmel_hlcdc_dc_lastclose, 695 .lastclose = atmel_hlcdc_dc_lastclose,
491 .irq_handler = atmel_hlcdc_dc_irq_handler, 696 .irq_handler = atmel_hlcdc_dc_irq_handler,
@@ -497,6 +702,15 @@ static struct drm_driver atmel_hlcdc_dc_driver = {
497 .disable_vblank = atmel_hlcdc_dc_disable_vblank, 702 .disable_vblank = atmel_hlcdc_dc_disable_vblank,
498 .gem_free_object = drm_gem_cma_free_object, 703 .gem_free_object = drm_gem_cma_free_object,
499 .gem_vm_ops = &drm_gem_cma_vm_ops, 704 .gem_vm_ops = &drm_gem_cma_vm_ops,
705 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
706 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
707 .gem_prime_import = drm_gem_prime_import,
708 .gem_prime_export = drm_gem_prime_export,
709 .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
710 .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
711 .gem_prime_vmap = drm_gem_cma_prime_vmap,
712 .gem_prime_vunmap = drm_gem_cma_prime_vunmap,
713 .gem_prime_mmap = drm_gem_cma_prime_mmap,
500 .dumb_create = drm_gem_cma_dumb_create, 714 .dumb_create = drm_gem_cma_dumb_create,
501 .dumb_map_offset = drm_gem_cma_dumb_map_offset, 715 .dumb_map_offset = drm_gem_cma_dumb_map_offset,
502 .dumb_destroy = drm_gem_dumb_destroy, 716 .dumb_destroy = drm_gem_dumb_destroy,
diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_output.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_output.c
index 9c4513005310..067e4c144bd6 100644
--- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_output.c
+++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_output.c
@@ -126,12 +126,16 @@ atmel_hlcdc_rgb_encoder_mode_set(struct drm_encoder *encoder,
126 126
127 if (info->num_bus_formats) { 127 if (info->num_bus_formats) {
128 switch (info->bus_formats[0]) { 128 switch (info->bus_formats[0]) {
129 case MEDIA_BUS_FMT_RGB565_1X16:
130 cfg |= ATMEL_HLCDC_CONNECTOR_RGB565 << 8;
131 break;
129 case MEDIA_BUS_FMT_RGB666_1X18: 132 case MEDIA_BUS_FMT_RGB666_1X18:
130 cfg |= ATMEL_HLCDC_CONNECTOR_RGB666 << 8; 133 cfg |= ATMEL_HLCDC_CONNECTOR_RGB666 << 8;
131 break; 134 break;
132 case MEDIA_BUS_FMT_RGB888_1X24: 135 case MEDIA_BUS_FMT_RGB888_1X24:
133 cfg |= ATMEL_HLCDC_CONNECTOR_RGB888 << 8; 136 cfg |= ATMEL_HLCDC_CONNECTOR_RGB888 << 8;
134 break; 137 break;
138 case MEDIA_BUS_FMT_RGB444_1X12:
135 default: 139 default:
136 break; 140 break;
137 } 141 }
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-27 01:22:09 -0400