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authorBoris Brezillon <boris.brezillon@free-electrons.com>2015-01-07 04:25:41 -0500
committerBoris Brezillon <boris.brezillon@free-electrons.com>2015-08-18 05:02:27 -0400
commit5b9fb5e6c6c74666f88f34bd0db183b9c4269d97 (patch)
tree3cb5b673cd11ee9da2543119a58809dd3e1db6cf
parent6b22cadce2175c997435d93cd3ef9b0389c45ad7 (diff)
drm: atmel-hlcdc: add support for sama5d4 SoCs
Describe capabilities of the HLCDC IP found on sama5d4 SoCs and add a new entry to the atmel_hlcdc_of_match table. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
-rw-r--r--drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c86
1 files changed, 86 insertions, 0 deletions
diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c
index ed83aa3207ea..e058e0ad3c15 100644
--- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c
+++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c
@@ -241,6 +241,88 @@ static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc_sama5d3 = {
241 .layers = atmel_hlcdc_sama5d3_layers, 241 .layers = atmel_hlcdc_sama5d3_layers,
242}; 242};
243 243
244static const struct atmel_hlcdc_layer_desc atmel_hlcdc_sama5d4_layers[] = {
245 {
246 .name = "base",
247 .formats = &atmel_hlcdc_plane_rgb_formats,
248 .regs_offset = 0x40,
249 .id = 0,
250 .type = ATMEL_HLCDC_BASE_LAYER,
251 .nconfigs = 7,
252 .layout = {
253 .xstride = { 2 },
254 .default_color = 3,
255 .general_config = 4,
256 .disc_pos = 5,
257 .disc_size = 6,
258 },
259 },
260 {
261 .name = "overlay1",
262 .formats = &atmel_hlcdc_plane_rgb_formats,
263 .regs_offset = 0x140,
264 .id = 1,
265 .type = ATMEL_HLCDC_OVERLAY_LAYER,
266 .nconfigs = 10,
267 .layout = {
268 .pos = 2,
269 .size = 3,
270 .xstride = { 4 },
271 .pstride = { 5 },
272 .default_color = 6,
273 .chroma_key = 7,
274 .chroma_key_mask = 8,
275 .general_config = 9,
276 },
277 },
278 {
279 .name = "overlay2",
280 .formats = &atmel_hlcdc_plane_rgb_formats,
281 .regs_offset = 0x240,
282 .id = 2,
283 .type = ATMEL_HLCDC_OVERLAY_LAYER,
284 .nconfigs = 10,
285 .layout = {
286 .pos = 2,
287 .size = 3,
288 .xstride = { 4 },
289 .pstride = { 5 },
290 .default_color = 6,
291 .chroma_key = 7,
292 .chroma_key_mask = 8,
293 .general_config = 9,
294 },
295 },
296 {
297 .name = "high-end-overlay",
298 .formats = &atmel_hlcdc_plane_rgb_and_yuv_formats,
299 .regs_offset = 0x340,
300 .id = 3,
301 .type = ATMEL_HLCDC_OVERLAY_LAYER,
302 .nconfigs = 42,
303 .layout = {
304 .pos = 2,
305 .size = 3,
306 .memsize = 4,
307 .xstride = { 5, 7 },
308 .pstride = { 6, 8 },
309 .default_color = 9,
310 .chroma_key = 10,
311 .chroma_key_mask = 11,
312 .general_config = 12,
313 .csc = 14,
314 },
315 },
316};
317
318static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc_sama5d4 = {
319 .min_width = 0,
320 .min_height = 0,
321 .max_width = 2048,
322 .max_height = 2048,
323 .nlayers = ARRAY_SIZE(atmel_hlcdc_sama5d4_layers),
324 .layers = atmel_hlcdc_sama5d4_layers,
325};
244static const struct of_device_id atmel_hlcdc_of_match[] = { 326static const struct of_device_id atmel_hlcdc_of_match[] = {
245 { 327 {
246 .compatible = "atmel,at91sam9n12-hlcdc", 328 .compatible = "atmel,at91sam9n12-hlcdc",
@@ -254,6 +336,10 @@ static const struct of_device_id atmel_hlcdc_of_match[] = {
254 .compatible = "atmel,sama5d3-hlcdc", 336 .compatible = "atmel,sama5d3-hlcdc",
255 .data = &atmel_hlcdc_dc_sama5d3, 337 .data = &atmel_hlcdc_dc_sama5d3,
256 }, 338 },
339 {
340 .compatible = "atmel,sama5d4-hlcdc",
341 .data = &atmel_hlcdc_dc_sama5d4,
342 },
257 { /* sentinel */ }, 343 { /* sentinel */ },
258}; 344};
259 345