drm/msm: Hard code the GPU "slow frequency"

Some A3XX and A4XX GPU targets required that the GPU clock be
programmed to a non zero value when it was disabled so
27Mhz was chosen as the "invalid" frequency.

Even though newer targets do not have the same clock restrictions
we still write 27Mhz on clock disable and expect the clock subsystem
to round down to zero.

For unknown reasons even though the slow clock speed is always
27Mhz and it isn't actually a functional level the legacy device tree
frequency tables always defined it and then did gymnastics to work
around it.

Instead of playing the same silly games just hard code the "slow" clock
speed in the code as 27MHz and save ourselves a bit of infrastructure.

Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>

5 files changed, 11 insertions, 11 deletions

diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c
index bc170b7d5546..9cae68bed0d6 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_device.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
@@ -2,7 +2,7 @@
  * Copyright (C) 2013-2014 Red Hat
  * Author: Rob Clark <robdclark@gmail.com>
  *
- * Copyright (c) 2014 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2014,2017 The Linux Foundation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms of the GNU General Public License version 2 as published by
@@ -231,7 +231,6 @@ static int adreno_bind(struct device *dev, struct device *master, void *data)
 
         /* find clock rates: */
         config.fast_rate = 0;
-        config.slow_rate = ~0;
         for_each_child_of_node(node, child) {
                 if (of_device_is_compatible(child, "qcom,gpu-pwrlevels")) {
                         struct device_node *pwrlvl;
@@ -242,7 +241,6 @@ static int adreno_bind(struct device *dev, struct device *master, void *data)
                                         return ret;
                                 }
                                 config.fast_rate = max(config.fast_rate, val);
-                                config.slow_rate = min(config.slow_rate, val);
                         }
                 }
         }
@@ -251,7 +249,6 @@ static int adreno_bind(struct device *dev, struct device *master, void *data)
                 dev_warn(dev, "could not find clk rates\n");
                 /* This is a safe low speed for all devices: */
                 config.fast_rate = 200000000;
-                config.slow_rate = 27000000;
         }
 
         dev->platform_data = &config;
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index 4cac22633ce4..5b63fc649dcc 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -352,14 +352,13 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
         adreno_gpu->rev = config->rev;
 
         gpu->fast_rate = config->fast_rate;
-        gpu->slow_rate = config->slow_rate;
         gpu->bus_freq  = config->bus_freq;
 #ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING
         gpu->bus_scale_table = config->bus_scale_table;
 #endif
 
-        DBG("fast_rate=%u, slow_rate=%u, bus_freq=%u",
-                        gpu->fast_rate, gpu->slow_rate, gpu->bus_freq);
+        DBG("fast_rate=%u, slow_rate=27000000, bus_freq=%u",
+                        gpu->fast_rate, gpu->bus_freq);
 
         ret = msm_gpu_init(drm, pdev, &adreno_gpu->base, &funcs->base,
                         adreno_gpu->info->name, "kgsl_3d0_reg_memory", "kgsl_3d0_irq",
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
index 42e444a67630..fb4831f9f80b 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
@@ -123,7 +123,7 @@ struct adreno_gpu {
 /* platform config data (ie. from DT, or pdata) */
 struct adreno_platform_config {
         struct adreno_rev rev;
-        uint32_t fast_rate, slow_rate, bus_freq;
+        uint32_t fast_rate, bus_freq;
 #ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING
         struct msm_bus_scale_pdata *bus_scale_table;
 #endif
diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c
index 937f1a0c5d3c..f8ee1489e691 100644
--- a/drivers/gpu/drm/msm/msm_gpu.c
+++ b/drivers/gpu/drm/msm/msm_gpu.c
@@ -123,8 +123,12 @@ static int disable_clk(struct msm_gpu *gpu)
                 if (gpu->grp_clks[i])
                         clk_unprepare(gpu->grp_clks[i]);
 
-        if (gpu->grp_clks[0] && gpu->slow_rate)
-                clk_set_rate(gpu->grp_clks[0], gpu->slow_rate);
+        /*
+         * Set the clock to a deliberately low rate. On older targets the clock
+         * speed had to be non zero to avoid problems. On newer targets this
+         * will be rounded down to zero anyway so it all works out.
+         */
+        clk_set_rate(gpu->grp_clks[0], 27000000);
 
         if (gpu->grp_clks[2])
                 clk_set_rate(gpu->grp_clks[2], 0);
diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h
index 72dba973aabf..44f0c34ee5e4 100644
--- a/drivers/gpu/drm/msm/msm_gpu.h
+++ b/drivers/gpu/drm/msm/msm_gpu.h
@@ -104,7 +104,7 @@ struct msm_gpu {
         /* Power Control: */
         struct regulator *gpu_reg, *gpu_cx;
         struct clk *ebi1_clk, *grp_clks[6];
-        uint32_t fast_rate, slow_rate, bus_freq;
+        uint32_t fast_rate, bus_freq;
 
 #ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING
         struct msm_bus_scale_pdata *bus_scale_table;