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authorArnd Bergmann <arnd@arndb.de>2016-11-30 17:36:38 -0500
committerArnd Bergmann <arnd@arndb.de>2016-11-30 17:36:38 -0500
commitbb2d850778477a5ac30bf2752658856f20c2b1ac (patch)
tree60226df8199755bb2fddba38d024f83708d1a50d
parentf39266cb18da53fe2c0148847a27cd78a82bc5c8 (diff)
parentc458e1b504a6a8c817fc56b4d4704273f2c459bb (diff)
Merge tag 'v4.10-rockchip-dts32-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt
Pull "Rockchip dts32 changes for 4.10" from Heiko Stübner: A bit of attention for the rk3066, fixed tsadc reset node as well as enabling the dma for uart and mmc controllers. And one new soc, the rk1108 combining a single-core Cortex-A7 with a separate DSP core. * tag 'v4.10-rockchip-dts32-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: ARM: dts: rockchip: add the sdmmc pinctrl for rk1108 ARM: dts: rockchip: add rockchip RK1108 Evaluation board ARM: dts: rockchip: add basic support for RK1108 SOC clk: rockchip: add dt-binding header for rk1108 dt-bindings: rockchip-dw-mshc: add RK1108 dw-mshc description ARM: dts: rockchip: enable dma for uart and mmc on rk3066a ARM: dts: rockchip: fix TSADC reset node for rk3066a
Diffstat
-rw-r--r--Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt1
-rw-r--r--arch/arm/boot/dts/Makefile1
-rw-r--r--arch/arm/boot/dts/rk1108-evb.dts69
-rw-r--r--arch/arm/boot/dts/rk1108.dtsi452
-rw-r--r--arch/arm/boot/dts/rk3066a.dtsi19
-rw-r--r--include/dt-bindings/clock/rk1108-cru.h269
6 files changed, 810 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt
index 07184e8f894e..ea9c1c9607f6 100644
--- a/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt
+++ b/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt
@@ -13,6 +13,7 @@ Required Properties:
13 - "rockchip,rk2928-dw-mshc": for Rockchip RK2928 and following, 13 - "rockchip,rk2928-dw-mshc": for Rockchip RK2928 and following,
14 before RK3288 14 before RK3288
15 - "rockchip,rk3288-dw-mshc": for Rockchip RK3288 15 - "rockchip,rk3288-dw-mshc": for Rockchip RK3288
16 - "rockchip,rk1108-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK1108
16 - "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3036 17 - "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3036
17 - "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3368 18 - "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3368
18 - "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3399 19 - "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3399
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index ecc3fc94c0b4..01b77cea3a55 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -656,6 +656,7 @@ dtb-$(CONFIG_ARCH_REALVIEW) += \
656 arm-realview-pba8.dtb \ 656 arm-realview-pba8.dtb \
657 arm-realview-pbx-a9.dtb 657 arm-realview-pbx-a9.dtb
658dtb-$(CONFIG_ARCH_ROCKCHIP) += \ 658dtb-$(CONFIG_ARCH_ROCKCHIP) += \
659 rk1108-evb.dtb \
659 rk3036-evb.dtb \ 660 rk3036-evb.dtb \
660 rk3036-kylin.dtb \ 661 rk3036-kylin.dtb \
661 rk3066a-bqcurie2.dtb \ 662 rk3066a-bqcurie2.dtb \
diff --git a/arch/arm/boot/dts/rk1108-evb.dts b/arch/arm/boot/dts/rk1108-evb.dts
new file mode 100644
index 000000000000..3956cff4ca79
--- /dev/null
+++ b/arch/arm/boot/dts/rk1108-evb.dts
@@ -0,0 +1,69 @@
1/*
2 * This file is dual-licensed: you can use it either under the terms
3 * of the GPL or the X11 license, at your option. Note that this dual
4 * licensing only applies to this file, and not this project as a
5 * whole.
6 *
7 * a) This file is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of the
10 * License, or (at your option) any later version.
11 *
12 * This file is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * Or, alternatively,
18 *
19 * b) Permission is hereby granted, free of charge, to any person
20 * obtaining a copy of this software and associated documentation
21 * files (the "Software"), to deal in the Software without
22 * restriction, including without limitation the rights to use,
23 * copy, modify, merge, publish, distribute, sublicense, and/or
24 * sell copies of the Software, and to permit persons to whom the
25 * Software is furnished to do so, subject to the following
26 * conditions:
27 *
28 * The above copyright notice and this permission notice shall be
29 * included in all copies or substantial portions of the Software.
30 *
31 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
32 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
33 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
34 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
35 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
36 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
37 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
38 * OTHER DEALINGS IN THE SOFTWARE.
39 */
40
41/dts-v1/;
42
43#include "rk1108.dtsi"
44
45/ {
46 model = "Rockchip RK1108 Evaluation board";
47 compatible = "rockchip,rk1108-evb", "rockchip,rk1108";
48
49 memory@60000000 {
50 device_type = "memory";
51 reg = <0x60000000 0x08000000>;
52 };
53
54 chosen {
55 stdout-path = "serial2:1500000n8";
56 };
57};
58
59&uart0 {
60 status = "okay";
61};
62
63&uart1 {
64 status = "okay";
65};
66
67&uart2 {
68 status = "okay";
69};
diff --git a/arch/arm/boot/dts/rk1108.dtsi b/arch/arm/boot/dts/rk1108.dtsi
new file mode 100644
index 000000000000..d7700235e0f5
--- /dev/null
+++ b/arch/arm/boot/dts/rk1108.dtsi
@@ -0,0 +1,452 @@
1/*
2 * This file is dual-licensed: you can use it either under the terms
3 * of the GPL or the X11 license, at your option. Note that this dual
4 * licensing only applies to this file, and not this project as a
5 * whole.
6 *
7 * a) This file is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of the
10 * License, or (at your option) any later version.
11 *
12 * This file is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * Or, alternatively,
18 *
19 * b) Permission is hereby granted, free of charge, to any person
20 * obtaining a copy of this software and associated documentation
21 * files (the "Software"), to deal in the Software without
22 * restriction, including without limitation the rights to use,
23 * copy, modify, merge, publish, distribute, sublicense, and/or
24 * sell copies of the Software, and to permit persons to whom the
25 * Software is furnished to do so, subject to the following
26 * conditions:
27 *
28 * The above copyright notice and this permission notice shall be
29 * included in all copies or substantial portions of the Software.
30 *
31 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
32 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
33 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
34 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
35 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
36 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
37 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
38 * OTHER DEALINGS IN THE SOFTWARE.
39 */
40
41#include <dt-bindings/gpio/gpio.h>
42#include <dt-bindings/interrupt-controller/irq.h>
43#include <dt-bindings/interrupt-controller/arm-gic.h>
44#include <dt-bindings/clock/rk1108-cru.h>
45#include <dt-bindings/pinctrl/rockchip.h>
46/ {
47 #address-cells = <1>;
48 #size-cells = <1>;
49
50 compatible = "rockchip,rk1108";
51
52 interrupt-parent = <&gic>;
53
54 aliases {
55 serial0 = &uart0;
56 serial1 = &uart1;
57 serial2 = &uart2;
58 };
59
60 cpus {
61 #address-cells = <1>;
62 #size-cells = <0>;
63
64 cpu0: cpu@f00 {
65 device_type = "cpu";
66 compatible = "arm,cortex-a7";
67 reg = <0xf00>;
68 };
69 };
70
71 arm-pmu {
72 compatible = "arm,cortex-a7-pmu";
73 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
74 };
75
76 timer {
77 compatible = "arm,armv7-timer";
78 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>,
79 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
80 clock-frequency = <24000000>;
81 };
82
83 xin24m: oscillator {
84 compatible = "fixed-clock";
85 clock-frequency = <24000000>;
86 clock-output-names = "xin24m";
87 #clock-cells = <0>;
88 };
89
90 amba {
91 compatible = "simple-bus";
92 #address-cells = <1>;
93 #size-cells = <1>;
94 ranges;
95
96 pdma: pdma@102a0000 {
97 compatible = "arm,pl330", "arm,primecell";
98 reg = <0x102a0000 0x4000>;
99 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
100 #dma-cells = <1>;
101 arm,pl330-broken-no-flushp;
102 clocks = <&cru ACLK_DMAC>;
103 clock-names = "apb_pclk";
104 };
105 };
106
107 bus_intmem@10080000 {
108 compatible = "mmio-sram";
109 reg = <0x10080000 0x2000>;
110 #address-cells = <1>;
111 #size-cells = <1>;
112 ranges = <0 0x10080000 0x2000>;
113 };
114
115 uart2: serial@10210000 {
116 compatible = "rockchip,rk1108-uart", "snps,dw-apb-uart";
117 reg = <0x10210000 0x100>;
118 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
119 reg-shift = <2>;
120 reg-io-width = <4>;
121 clock-frequency = <24000000>;
122 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
123 clock-names = "baudclk", "apb_pclk";
124 pinctrl-names = "default";
125 pinctrl-0 = <&uart2m0_xfer>;
126 status = "disabled";
127 };
128
129 uart1: serial@10220000 {
130 compatible = "rockchip,rk1108-uart", "snps,dw-apb-uart";
131 reg = <0x10220000 0x100>;
132 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
133 reg-shift = <2>;
134 reg-io-width = <4>;
135 clock-frequency = <24000000>;
136 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
137 clock-names = "baudclk", "apb_pclk";
138 pinctrl-names = "default";
139 pinctrl-0 = <&uart1_xfer>;
140 status = "disabled";
141 };
142
143 uart0: serial@10230000 {
144 compatible = "rockchip,rk1108-uart", "snps,dw-apb-uart";
145 reg = <0x10230000 0x100>;
146 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
147 reg-shift = <2>;
148 reg-io-width = <4>;
149 clock-frequency = <24000000>;
150 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
151 clock-names = "baudclk", "apb_pclk";
152 pinctrl-names = "default";
153 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
154 status = "disabled";
155 };
156
157 grf: syscon@10300000 {
158 compatible = "rockchip,rk1108-grf", "syscon";
159 reg = <0x10300000 0x1000>;
160 };
161
162 pmugrf: syscon@20060000 {
163 compatible = "rockchip,rk1108-pmugrf", "syscon";
164 reg = <0x20060000 0x1000>;
165 };
166
167 cru: clock-controller@20200000 {
168 compatible = "rockchip,rk1108-cru";
169 reg = <0x20200000 0x1000>;
170 rockchip,grf = <&grf>;
171 #clock-cells = <1>;
172 #reset-cells = <1>;
173 };
174
175 emmc: dwmmc@30110000 {
176 compatible = "rockchip,rk1108-dw-mshc", "rockchip,rk3288-dw-mshc";
177 clock-freq-min-max = <400000 150000000>;
178 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
179 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
180 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
181 fifo-depth = <0x100>;
182 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
183 reg = <0x30110000 0x4000>;
184 status = "disabled";
185 };
186
187 sdio: dwmmc@30120000 {
188 compatible = "rockchip,rk1108-dw-mshc", "rockchip,rk3288-dw-mshc";
189 clock-freq-min-max = <400000 150000000>;
190 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
191 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
192 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
193 fifo-depth = <0x100>;
194 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
195 reg = <0x30120000 0x4000>;
196 status = "disabled";
197 };
198
199 sdmmc: dwmmc@30130000 {
200 compatible = "rockchip,rk1108-dw-mshc", "rockchip,rk3288-dw-mshc";
201 clock-freq-min-max = <400000 100000000>;
202 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
203 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
204 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
205 fifo-depth = <0x100>;
206 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
207 reg = <0x30130000 0x4000>;
208 status = "disabled";
209 };
210
211 gic: interrupt-controller@32010000 {
212 compatible = "arm,gic-400";
213 interrupt-controller;
214 #interrupt-cells = <3>;
215 #address-cells = <0>;
216
217 reg = <0x32011000 0x1000>,
218 <0x32012000 0x1000>,
219 <0x32014000 0x2000>,
220 <0x32016000 0x2000>;
221 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
222 };
223
224 pinctrl: pinctrl {
225 compatible = "rockchip,rk1108-pinctrl";
226 rockchip,grf = <&grf>;
227 rockchip,pmu = <&pmugrf>;
228 #address-cells = <1>;
229 #size-cells = <1>;
230 ranges;
231
232 gpio0: gpio0@20030000 {
233 compatible = "rockchip,gpio-bank";
234 reg = <0x20030000 0x100>;
235 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
236 clocks = <&xin24m>;
237
238 gpio-controller;
239 #gpio-cells = <2>;
240
241 interrupt-controller;
242 #interrupt-cells = <2>;
243 };
244
245 gpio1: gpio1@10310000 {
246 compatible = "rockchip,gpio-bank";
247 reg = <0x10310000 0x100>;
248 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
249 clocks = <&xin24m>;
250
251 gpio-controller;
252 #gpio-cells = <2>;
253
254 interrupt-controller;
255 #interrupt-cells = <2>;
256 };
257
258 gpio2: gpio2@10320000 {
259 compatible = "rockchip,gpio-bank";
260 reg = <0x10320000 0x100>;
261 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
262 clocks = <&xin24m>;
263
264 gpio-controller;
265 #gpio-cells = <2>;
266
267 interrupt-controller;
268 #interrupt-cells = <2>;
269 };
270
271 gpio3: gpio3@10330000 {
272 compatible = "rockchip,gpio-bank";
273 reg = <0x10330000 0x100>;
274 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
275 clocks = <&xin24m>;
276
277 gpio-controller;
278 #gpio-cells = <2>;
279
280 interrupt-controller;
281 #interrupt-cells = <2>;
282 };
283
284 pcfg_pull_up: pcfg-pull-up {
285 bias-pull-up;
286 };
287
288 pcfg_pull_down: pcfg-pull-down {
289 bias-pull-down;
290 };
291
292 pcfg_pull_none: pcfg-pull-none {
293 bias-disable;
294 };
295
296 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
297 drive-strength = <8>;
298 };
299
300 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
301 drive-strength = <12>;
302 };
303
304 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
305 bias-pull-up;
306 drive-strength = <8>;
307 };
308
309 pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
310 drive-strength = <4>;
311 };
312
313 pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
314 bias-pull-up;
315 drive-strength = <4>;
316 };
317
318 pcfg_output_high: pcfg-output-high {
319 output-high;
320 };
321
322 pcfg_output_low: pcfg-output-low {
323 output-low;
324 };
325
326 pcfg_input_high: pcfg-input-high {
327 bias-pull-up;
328 input-enable;
329 };
330
331 i2c1 {
332 i2c1_xfer: i2c1-xfer {
333 rockchip,pins = <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>,
334 <2 RK_PD4 RK_FUNC_1 &pcfg_pull_up>;
335 };
336 };
337
338 i2c2m1 {
339 i2c2m1_xfer: i2c2m1-xfer {
340 rockchip,pins = <0 RK_PC2 RK_FUNC_2 &pcfg_pull_none>,
341 <0 RK_PC6 RK_FUNC_3 &pcfg_pull_none>;
342 };
343
344 i2c2m1_gpio: i2c2m1-gpio {
345 rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>,
346 <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
347 };
348 };
349
350 i2c2m05v {
351 i2c2m05v_xfer: i2c2m05v-xfer {
352 rockchip,pins = <1 RK_PD5 RK_FUNC_2 &pcfg_pull_none>,
353 <1 RK_PD4 RK_FUNC_2 &pcfg_pull_none>;
354 };
355
356 i2c2m05v_gpio: i2c2m05v-gpio {
357 rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>,
358 <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
359 };
360 };
361
362 i2c3 {
363 i2c3_xfer: i2c3-xfer {
364 rockchip,pins = <0 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,
365 <0 RK_PC4 RK_FUNC_2 &pcfg_pull_none>;
366 };
367 };
368
369 sdmmc {
370 sdmmc_clk: sdmmc-clk {
371 rockchip,pins = <3 RK_PC4 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
372 };
373
374 sdmmc_cmd: sdmmc-cmd {
375 rockchip,pins = <3 RK_PC5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
376 };
377
378 sdmmc_cd: sdmmc-cd {
379 rockchip,pins = <0 RK_PA1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
380 };
381
382 sdmmc_bus1: sdmmc-bus1 {
383 rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
384 };
385
386 sdmmc_bus4: sdmmc-bus4 {
387 rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
388 <3 RK_PC2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
389 <3 RK_PC1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
390 <3 RK_PC0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
391 };
392 };
393
394 uart0 {
395 uart0_xfer: uart0-xfer {
396 rockchip,pins = <3 RK_PA6 RK_FUNC_1 &pcfg_pull_up>,
397 <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none>;
398 };
399
400 uart0_cts: uart0-cts {
401 rockchip,pins = <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none>;
402 };
403
404 uart0_rts: uart0-rts {
405 rockchip,pins = <3 RK_PA3 RK_FUNC_1 &pcfg_pull_none>;
406 };
407
408 uart0_rts_gpio: uart0-rts-gpio {
409 rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
410 };
411 };
412
413 uart1 {
414 uart1_xfer: uart1-xfer {
415 rockchip,pins = <1 RK_PD3 RK_FUNC_1 &pcfg_pull_up>,
416 <1 RK_PD2 RK_FUNC_1 &pcfg_pull_none>;
417 };
418
419 uart1_cts: uart1-cts {
420 rockchip,pins = <1 RK_PD0 RK_FUNC_1 &pcfg_pull_none>;
421 };
422
423 uart1_rts: uart1-rts {
424 rockchip,pins = <1 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
425 };
426 };
427
428 uart2m0 {
429 uart2m0_xfer: uart2m0-xfer {
430 rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up>,
431 <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
432 };
433 };
434
435 uart2m1 {
436 uart2m1_xfer: uart2m1-xfer {
437 rockchip,pins = <3 RK_PC3 RK_FUNC_2 &pcfg_pull_up>,
438 <3 RK_PC2 RK_FUNC_2 &pcfg_pull_none>;
439 };
440 };
441
442 uart2_5v {
443 uart2_5v_cts: uart2_5v-cts {
444 rockchip,pins = <1 RK_PD4 RK_FUNC_1 &pcfg_pull_none>;
445 };
446
447 uart2_5v_rts: uart2_5v-rts {
448 rockchip,pins = <1 RK_PD5 RK_FUNC_1 &pcfg_pull_none>;
449 };
450 };
451 };
452};
diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi
index fc8dcc72b16f..e498c362b9e7 100644
--- a/arch/arm/boot/dts/rk3066a.dtsi
+++ b/arch/arm/boot/dts/rk3066a.dtsi
@@ -205,7 +205,7 @@
205 clock-names = "saradc", "apb_pclk"; 205 clock-names = "saradc", "apb_pclk";
206 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 206 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
207 #io-channel-cells = <1>; 207 #io-channel-cells = <1>;
208 resets = <&cru SRST_SARADC>; 208 resets = <&cru SRST_TSADC>;
209 reset-names = "saradc-apb"; 209 reset-names = "saradc-apb";
210 status = "disabled"; 210 status = "disabled";
211 }; 211 };
@@ -637,16 +637,25 @@
637 637
638&mmc0 { 638&mmc0 {
639 clock-frequency = <50000000>; 639 clock-frequency = <50000000>;
640 dmas = <&dmac2 1>;
641 dma-names = "rx-tx";
640 max-frequency = <50000000>; 642 max-frequency = <50000000>;
641 pinctrl-names = "default"; 643 pinctrl-names = "default";
642 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>; 644 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>;
643}; 645};
644 646
645&mmc1 { 647&mmc1 {
648 dmas = <&dmac2 3>;
649 dma-names = "rx-tx";
646 pinctrl-names = "default"; 650 pinctrl-names = "default";
647 pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>; 651 pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>;
648}; 652};
649 653
654&emmc {
655 dmas = <&dmac2 4>;
656 dma-names = "rx-tx";
657};
658
650&pwm0 { 659&pwm0 {
651 pinctrl-names = "default"; 660 pinctrl-names = "default";
652 pinctrl-0 = <&pwm0_out>; 661 pinctrl-0 = <&pwm0_out>;
@@ -678,21 +687,29 @@
678}; 687};
679 688
680&uart0 { 689&uart0 {
690 dmas = <&dmac1_s 0>, <&dmac1_s 1>;
691 dma-names = "tx", "rx";
681 pinctrl-names = "default"; 692 pinctrl-names = "default";
682 pinctrl-0 = <&uart0_xfer>; 693 pinctrl-0 = <&uart0_xfer>;
683}; 694};
684 695
685&uart1 { 696&uart1 {
697 dmas = <&dmac1_s 2>, <&dmac1_s 3>;
698 dma-names = "tx", "rx";
686 pinctrl-names = "default"; 699 pinctrl-names = "default";
687 pinctrl-0 = <&uart1_xfer>; 700 pinctrl-0 = <&uart1_xfer>;
688}; 701};
689 702
690&uart2 { 703&uart2 {
704 dmas = <&dmac2 6>, <&dmac2 7>;
705 dma-names = "tx", "rx";
691 pinctrl-names = "default"; 706 pinctrl-names = "default";
692 pinctrl-0 = <&uart2_xfer>; 707 pinctrl-0 = <&uart2_xfer>;
693}; 708};
694 709
695&uart3 { 710&uart3 {
711 dmas = <&dmac2 8>, <&dmac2 9>;
712 dma-names = "tx", "rx";
696 pinctrl-names = "default"; 713 pinctrl-names = "default";
697 pinctrl-0 = <&uart3_xfer>; 714 pinctrl-0 = <&uart3_xfer>;
698}; 715};
diff --git a/include/dt-bindings/clock/rk1108-cru.h b/include/dt-bindings/clock/rk1108-cru.h
new file mode 100644
index 000000000000..9350a5527a36
--- /dev/null
+++ b/include/dt-bindings/clock/rk1108-cru.h
@@ -0,0 +1,269 @@
1/*
2 * Copyright (c) 2016 Rockchip Electronics Co. Ltd.
3 * Author: Shawn Lin <shawn.lin@rock-chips.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK1108_H
17#define _DT_BINDINGS_CLK_ROCKCHIP_RK1108_H
18
19/* pll id */
20#define PLL_APLL 0
21#define PLL_DPLL 1
22#define PLL_GPLL 2
23#define ARMCLK 3
24
25/* sclk gates (special clocks) */
26#define SCLK_SPI0 65
27#define SCLK_NANDC 67
28#define SCLK_SDMMC 68
29#define SCLK_SDIO 69
30#define SCLK_EMMC 71
31#define SCLK_UART0 72
32#define SCLK_UART1 73
33#define SCLK_UART2 74
34#define SCLK_I2S0 75
35#define SCLK_I2S1 76
36#define SCLK_I2S2 77
37#define SCLK_TIMER0 78
38#define SCLK_TIMER1 79
39#define SCLK_SFC 80
40#define SCLK_SDMMC_DRV 81
41#define SCLK_SDIO_DRV 82
42#define SCLK_EMMC_DRV 83
43#define SCLK_SDMMC_SAMPLE 84
44#define SCLK_SDIO_SAMPLE 85
45#define SCLK_EMMC_SAMPLE 86
46
47/* aclk gates */
48#define ACLK_DMAC 192
49#define ACLK_PRE 193
50#define ACLK_CORE 194
51#define ACLK_ENMCORE 195
52
53/* pclk gates */
54#define PCLK_GPIO1 256
55#define PCLK_GPIO2 257
56#define PCLK_GPIO3 258
57#define PCLK_GRF 259
58#define PCLK_I2C1 260
59#define PCLK_I2C2 261
60#define PCLK_I2C3 262
61#define PCLK_SPI 263
62#define PCLK_SFC 264
63#define PCLK_UART0 265
64#define PCLK_UART1 266
65#define PCLK_UART2 267
66#define PCLK_TSADC 268
67#define PCLK_PWM 269
68#define PCLK_TIMER 270
69#define PCLK_PERI 271
70
71/* hclk gates */
72#define HCLK_I2S0_8CH 320
73#define HCLK_I2S1_8CH 321
74#define HCLK_I2S2_2CH 322
75#define HCLK_NANDC 323
76#define HCLK_SDMMC 324
77#define HCLK_SDIO 325
78#define HCLK_EMMC 326
79#define HCLK_PERI 327
80#define HCLK_SFC 328
81
82#define CLK_NR_CLKS (HCLK_SFC + 1)
83
84/* reset id */
85#define SRST_CORE_PO_AD 0
86#define SRST_CORE_AD 1
87#define SRST_L2_AD 2
88#define SRST_CPU_NIU_AD 3
89#define SRST_CORE_PO 4
90#define SRST_CORE 5
91#define SRST_L2 6
92#define SRST_CORE_DBG 8
93#define PRST_DBG 9
94#define RST_DAP 10
95#define PRST_DBG_NIU 11
96#define ARST_STRC_SYS_AD 15
97
98#define SRST_DDRPHY_CLKDIV 16
99#define SRST_DDRPHY 17
100#define PRST_DDRPHY 18
101#define PRST_HDMIPHY 19
102#define PRST_VDACPHY 20
103#define PRST_VADCPHY 21
104#define PRST_MIPI_CSI_PHY 22
105#define PRST_MIPI_DSI_PHY 23
106#define PRST_ACODEC 24
107#define ARST_BUS_NIU 25
108#define PRST_TOP_NIU 26
109#define ARST_INTMEM 27
110#define HRST_ROM 28
111#define ARST_DMAC 29
112#define SRST_MSCH_NIU 30
113#define PRST_MSCH_NIU 31
114
115#define PRST_DDRUPCTL 32
116#define NRST_DDRUPCTL 33
117#define PRST_DDRMON 34
118#define HRST_I2S0_8CH 35
119#define MRST_I2S0_8CH 36
120#define HRST_I2S1_2CH 37
121#define MRST_IS21_2CH 38
122#define HRST_I2S2_2CH 39
123#define MRST_I2S2_2CH 40
124#define HRST_CRYPTO 41
125#define SRST_CRYPTO 42
126#define PRST_SPI 43
127#define SRST_SPI 44
128#define PRST_UART0 45
129#define PRST_UART1 46
130#define PRST_UART2 47
131
132#define SRST_UART0 48
133#define SRST_UART1 49
134#define SRST_UART2 50
135#define PRST_I2C1 51
136#define PRST_I2C2 52
137#define PRST_I2C3 53
138#define SRST_I2C1 54
139#define SRST_I2C2 55
140#define SRST_I2C3 56
141#define PRST_PWM1 58
142#define SRST_PWM1 60
143#define PRST_WDT 61
144#define PRST_GPIO1 62
145#define PRST_GPIO2 63
146
147#define PRST_GPIO3 64
148#define PRST_GRF 65
149#define PRST_EFUSE 66
150#define PRST_EFUSE512 67
151#define PRST_TIMER0 68
152#define SRST_TIMER0 69
153#define SRST_TIMER1 70
154#define PRST_TSADC 71
155#define SRST_TSADC 72
156#define PRST_SARADC 73
157#define SRST_SARADC 74
158#define HRST_SYSBUS 75
159#define PRST_USBGRF 76
160
161#define ARST_PERIPH_NIU 80
162#define HRST_PERIPH_NIU 81
163#define PRST_PERIPH_NIU 82
164#define HRST_PERIPH 83
165#define HRST_SDMMC 84
166#define HRST_SDIO 85
167#define HRST_EMMC 86
168#define HRST_NANDC 87
169#define NRST_NANDC 88
170#define HRST_SFC 89
171#define SRST_SFC 90
172#define ARST_GMAC 91
173#define HRST_OTG 92
174#define SRST_OTG 93
175#define SRST_OTG_ADP 94
176#define HRST_HOST0 95
177
178#define HRST_HOST0_AUX 96
179#define HRST_HOST0_ARB 97
180#define SRST_HOST0_EHCIPHY 98
181#define SRST_HOST0_UTMI 99
182#define SRST_USBPOR 100
183#define SRST_UTMI0 101
184#define SRST_UTMI1 102
185
186#define ARST_VIO0_NIU 102
187#define ARST_VIO1_NIU 103
188#define HRST_VIO_NIU 104
189#define PRST_VIO_NIU 105
190#define ARST_VOP 106
191#define HRST_VOP 107
192#define DRST_VOP 108
193#define ARST_IEP 109
194#define HRST_IEP 110
195#define ARST_RGA 111
196#define HRST_RGA 112
197#define SRST_RGA 113
198#define PRST_CVBS 114
199#define PRST_HDMI 115
200#define SRST_HDMI 116
201#define PRST_MIPI_DSI 117
202
203#define ARST_ISP_NIU 118
204#define HRST_ISP_NIU 119
205#define HRST_ISP 120
206#define SRST_ISP 121
207#define ARST_VIP0 122
208#define HRST_VIP0 123
209#define PRST_VIP0 124
210#define ARST_VIP1 125
211#define HRST_VIP1 126
212#define PRST_VIP1 127
213#define ARST_VIP2 128
214#define HRST_VIP2 129
215#define PRST_VIP2 120
216#define ARST_VIP3 121
217#define HRST_VIP3 122
218#define PRST_VIP4 123
219
220#define PRST_CIF1TO4 124
221#define SRST_CVBS_CLK 125
222#define HRST_CVBS 126
223
224#define ARST_VPU_NIU 140
225#define HRST_VPU_NIU 141
226#define ARST_VPU 142
227#define HRST_VPU 143
228#define ARST_RKVDEC_NIU 144
229#define HRST_RKVDEC_NIU 145
230#define ARST_RKVDEC 146
231#define HRST_RKVDEC 147
232#define SRST_RKVDEC_CABAC 148
233#define SRST_RKVDEC_CORE 149
234#define ARST_RKVENC_NIU 150
235#define HRST_RKVENC_NIU 151
236#define ARST_RKVENC 152
237#define HRST_RKVENC 153
238#define SRST_RKVENC_CORE 154
239
240#define SRST_DSP_CORE 156
241#define SRST_DSP_SYS 157
242#define SRST_DSP_GLOBAL 158
243#define SRST_DSP_OECM 159
244#define PRST_DSP_IOP_NIU 160
245#define ARST_DSP_EPP_NIU 161
246#define ARST_DSP_EDP_NIU 162
247#define PRST_DSP_DBG_NIU 163
248#define PRST_DSP_CFG_NIU 164
249#define PRST_DSP_GRF 165
250#define PRST_DSP_MAILBOX 166
251#define PRST_DSP_INTC 167
252#define PRST_DSP_PFM_MON 169
253#define SRST_DSP_PFM_MON 170
254#define ARST_DSP_EDAP_NIU 171
255
256#define SRST_PMU 172
257#define SRST_PMU_I2C0 173
258#define PRST_PMU_I2C0 174
259#define PRST_PMU_GPIO0 175
260#define PRST_PMU_INTMEM 176
261#define PRST_PMU_PWM0 177
262#define SRST_PMU_PWM0 178
263#define PRST_PMU_GRF 179
264#define SRST_PMU_NIU 180
265#define SRST_PMU_PVTM 181
266#define ARST_DSP_EDP_PERF 184
267#define ARST_DSP_EPP_PERF 185
268
269#endif /* _DT_BINDINGS_CLK_ROCKCHIP_RK1108_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-17 14:17:31 -0400