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authorOlof Johansson <olof@lixom.net>2018-01-11 19:50:50 -0500
committerOlof Johansson <olof@lixom.net>2018-01-11 19:50:50 -0500
commitba05173afe439a1fa6b4aea773e8c5ea62082215 (patch)
tree4f9abb234cad460316dc9030bf3d70a2236ce238
parent8c11fcc212d763de6e6c068e7153a3b8b36b253d (diff)
parentf6f6ac914b82402b910b783cd13bf72de067f69f (diff)
Merge tag 'amlogic-dt64-3' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into next/dt
Another round of 64-bit DT changes for the new Amlogic SoCs. These include IR, SPI and ethernet MAC support for the new AXG family SoCs. * tag 'amlogic-dt64-3' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic: ARM64: dts: meson-axg: enable ethernet for A113D S400 board ARM64: dts: meson-axg: add ethernet mac controller ARM64: dts: meson-axg: add the SPICC controller ARM64: dts: meson-axg: enable IR controller arm64: dts: meson-axg: switch uart_ao clock to CLK81 clk: meson-axg: add clocks dt-bindings required header dt-bindings: clock: add compatible variant for the Meson-AXG Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat
-rw-r--r--Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt7
-rw-r--r--arch/arm64/boot/dts/amlogic/meson-axg-s400.dts13
-rw-r--r--arch/arm64/boot/dts/amlogic/meson-axg.dtsi164
-rw-r--r--include/dt-bindings/clock/axg-clkc.h71
4 files changed, 251 insertions, 4 deletions
diff --git a/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt
index 924040769186..e2b377ed6f91 100644
--- a/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt
+++ b/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt
@@ -5,8 +5,11 @@ controllers within the SoC.
5 5
6Required Properties: 6Required Properties:
7 7
8- compatible: should be "amlogic,gxbb-clkc" for GXBB SoC, 8- compatible: should be:
9 or "amlogic,gxl-clkc" for GXL and GXM SoC. 9 "amlogic,gxbb-clkc" for GXBB SoC,
10 "amlogic,gxl-clkc" for GXL and GXM SoC,
11 "amlogic,axg-clkc" for AXG SoC.
12
10- reg: physical base address of the clock controller and length of memory 13- reg: physical base address of the clock controller and length of memory
11 mapped region. 14 mapped region.
12 15
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
index 70eca1f8736a..447b98d30921 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
@@ -17,6 +17,19 @@
17 }; 17 };
18}; 18};
19 19
20&ethmac {
21 status = "okay";
22 phy-mode = "rgmii";
23 pinctrl-0 = <&eth_rgmii_y_pins>;
24 pinctrl-names = "default";
25};
26
20&uart_AO { 27&uart_AO {
21 status = "okay"; 28 status = "okay";
22}; 29};
30
31&ir {
32 status = "okay";
33 pinctrl-0 = <&remote_input_ao_pins>;
34 pinctrl-names = "default";
35};
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index d288d4724ae3..a80632641b39 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -7,6 +7,7 @@
7#include <dt-bindings/gpio/gpio.h> 7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/interrupt-controller/irq.h> 8#include <dt-bindings/interrupt-controller/irq.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/clock/axg-clkc.h>
10 11
11/ { 12/ {
12 compatible = "amlogic,meson-axg"; 13 compatible = "amlogic,meson-axg";
@@ -140,6 +141,28 @@
140 #reset-cells = <1>; 141 #reset-cells = <1>;
141 }; 142 };
142 143
144 spicc0: spi@13000 {
145 compatible = "amlogic,meson-axg-spicc";
146 reg = <0x0 0x13000 0x0 0x3c>;
147 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
148 clocks = <&clkc CLKID_SPICC0>;
149 clock-names = "core";
150 #address-cells = <1>;
151 #size-cells = <0>;
152 status = "disabled";
153 };
154
155 spicc1: spi@15000 {
156 compatible = "amlogic,meson-axg-spicc";
157 reg = <0x0 0x15000 0x0 0x3c>;
158 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
159 clocks = <&clkc CLKID_SPICC1>;
160 clock-names = "core";
161 #address-cells = <1>;
162 #size-cells = <0>;
163 status = "disabled";
164 };
165
143 uart_A: serial@24000 { 166 uart_A: serial@24000 {
144 compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart"; 167 compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart";
145 reg = <0x0 0x24000 0x0 0x14>; 168 reg = <0x0 0x24000 0x0 0x14>;
@@ -155,6 +178,19 @@
155 }; 178 };
156 }; 179 };
157 180
181 ethmac: ethernet@ff3f0000 {
182 compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac";
183 reg = <0x0 0xff3f0000 0x0 0x10000
184 0x0 0xff634540 0x0 0x8>;
185 interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>;
186 interrupt-names = "macirq";
187 clocks = <&clkc CLKID_ETH>,
188 <&clkc CLKID_FCLK_DIV2>,
189 <&clkc CLKID_MPLL2>;
190 clock-names = "stmmaceth", "clkin0", "clkin1";
191 status = "disabled";
192 };
193
158 gic: interrupt-controller@ffc01000 { 194 gic: interrupt-controller@ffc01000 {
159 compatible = "arm,gic-400"; 195 compatible = "arm,gic-400";
160 reg = <0x0 0xffc01000 0 0x1000>, 196 reg = <0x0 0xffc01000 0 0x1000>,
@@ -215,6 +251,46 @@
215 gpio-ranges = <&pinctrl_periphs 0 0 86>; 251 gpio-ranges = <&pinctrl_periphs 0 0 86>;
216 }; 252 };
217 253
254 eth_rgmii_x_pins: eth-x-rgmii {
255 mux {
256 groups = "eth_mdio_x",
257 "eth_mdc_x",
258 "eth_rgmii_rx_clk_x",
259 "eth_rx_dv_x",
260 "eth_rxd0_x",
261 "eth_rxd1_x",
262 "eth_rxd2_rgmii",
263 "eth_rxd3_rgmii",
264 "eth_rgmii_tx_clk",
265 "eth_txen_x",
266 "eth_txd0_x",
267 "eth_txd1_x",
268 "eth_txd2_rgmii",
269 "eth_txd3_rgmii";
270 function = "eth";
271 };
272 };
273
274 eth_rgmii_y_pins: eth-y-rgmii {
275 mux {
276 groups = "eth_mdio_y",
277 "eth_mdc_y",
278 "eth_rgmii_rx_clk_y",
279 "eth_rx_dv_y",
280 "eth_rxd0_y",
281 "eth_rxd1_y",
282 "eth_rxd2_rgmii",
283 "eth_rxd3_rgmii",
284 "eth_rgmii_tx_clk",
285 "eth_txen_y",
286 "eth_txd0_y",
287 "eth_txd1_y",
288 "eth_txd2_rgmii",
289 "eth_txd3_rgmii";
290 function = "eth";
291 };
292 };
293
218 pwm_a_a_pins: pwm_a_a { 294 pwm_a_a_pins: pwm_a_a {
219 mux { 295 mux {
220 groups = "pwm_a_a"; 296 groups = "pwm_a_a";
@@ -298,6 +374,76 @@
298 function = "pwm_d"; 374 function = "pwm_d";
299 }; 375 };
300 }; 376 };
377
378 spi0_pins: spi0 {
379 mux {
380 groups = "spi0_miso",
381 "spi0_mosi",
382 "spi0_clk";
383 function = "spi0";
384 };
385 };
386
387 spi0_ss0_pins: spi0_ss0 {
388 mux {
389 groups = "spi0_ss0";
390 function = "spi0";
391 };
392 };
393
394 spi0_ss1_pins: spi0_ss1 {
395 mux {
396 groups = "spi0_ss1";
397 function = "spi0";
398 };
399 };
400
401 spi0_ss2_pins: spi0_ss2 {
402 mux {
403 groups = "spi0_ss2";
404 function = "spi0";
405 };
406 };
407
408
409 spi1_a_pins: spi1_a {
410 mux {
411 groups = "spi1_miso_a",
412 "spi1_mosi_a",
413 "spi1_clk_a";
414 function = "spi1";
415 };
416 };
417
418 spi1_ss0_a_pins: spi1_ss0_a {
419 mux {
420 groups = "spi1_ss0_a";
421 function = "spi1";
422 };
423 };
424
425 spi1_ss1_pins: spi1_ss1 {
426 mux {
427 groups = "spi1_ss1";
428 function = "spi1";
429 };
430 };
431
432 spi1_x_pins: spi1_x {
433 mux {
434 groups = "spi1_miso_x",
435 "spi1_mosi_x",
436 "spi1_clk_x";
437 function = "spi1";
438 };
439 };
440
441 spi1_ss0_x_pins: spi1_ss0_x {
442 mux {
443 groups = "spi1_ss0_x";
444 function = "spi1";
445 };
446 };
301 }; 447 };
302 }; 448 };
303 449
@@ -341,6 +487,13 @@
341 #gpio-cells = <2>; 487 #gpio-cells = <2>;
342 gpio-ranges = <&pinctrl_aobus 0 0 15>; 488 gpio-ranges = <&pinctrl_aobus 0 0 15>;
343 }; 489 };
490
491 remote_input_ao_pins: remote_input_ao {
492 mux {
493 groups = "remote_input_ao";
494 function = "remote_input_ao";
495 };
496 };
344 }; 497 };
345 498
346 pwm_AO_ab: pwm@7000 { 499 pwm_AO_ab: pwm@7000 {
@@ -361,7 +514,7 @@
361 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; 514 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
362 reg = <0x0 0x3000 0x0 0x18>; 515 reg = <0x0 0x3000 0x0 0x18>;
363 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; 516 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
364 clocks = <&xtal>, <&xtal>, <&xtal>; 517 clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
365 clock-names = "xtal", "pclk", "baud"; 518 clock-names = "xtal", "pclk", "baud";
366 status = "disabled"; 519 status = "disabled";
367 }; 520 };
@@ -370,10 +523,17 @@
370 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; 523 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
371 reg = <0x0 0x4000 0x0 0x18>; 524 reg = <0x0 0x4000 0x0 0x18>;
372 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; 525 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
373 clocks = <&xtal>, <&xtal>, <&xtal>; 526 clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
374 clock-names = "xtal", "pclk", "baud"; 527 clock-names = "xtal", "pclk", "baud";
375 status = "disabled"; 528 status = "disabled";
376 }; 529 };
530
531 ir: ir@8000 {
532 compatible = "amlogic,meson-gxbb-ir";
533 reg = <0x0 0x8000 0x0 0x20>;
534 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
535 status = "disabled";
536 };
377 }; 537 };
378 }; 538 };
379}; 539};
diff --git a/include/dt-bindings/clock/axg-clkc.h b/include/dt-bindings/clock/axg-clkc.h
new file mode 100644
index 000000000000..941ac70e7f30
--- /dev/null
+++ b/include/dt-bindings/clock/axg-clkc.h
@@ -0,0 +1,71 @@
1/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
2/*
3 * Meson-AXG clock tree IDs
4 *
5 * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
6 */
7
8#ifndef __AXG_CLKC_H
9#define __AXG_CLKC_H
10
11#define CLKID_SYS_PLL 0
12#define CLKID_FIXED_PLL 1
13#define CLKID_FCLK_DIV2 2
14#define CLKID_FCLK_DIV3 3
15#define CLKID_FCLK_DIV4 4
16#define CLKID_FCLK_DIV5 5
17#define CLKID_FCLK_DIV7 6
18#define CLKID_GP0_PLL 7
19#define CLKID_CLK81 10
20#define CLKID_MPLL0 11
21#define CLKID_MPLL1 12
22#define CLKID_MPLL2 13
23#define CLKID_MPLL3 14
24#define CLKID_DDR 15
25#define CLKID_AUDIO_LOCKER 16
26#define CLKID_MIPI_DSI_HOST 17
27#define CLKID_ISA 18
28#define CLKID_PL301 19
29#define CLKID_PERIPHS 20
30#define CLKID_SPICC0 21
31#define CLKID_I2C 22
32#define CLKID_RNG0 23
33#define CLKID_UART0 24
34#define CLKID_MIPI_DSI_PHY 25
35#define CLKID_SPICC1 26
36#define CLKID_PCIE_A 27
37#define CLKID_PCIE_B 28
38#define CLKID_HIU_IFACE 29
39#define CLKID_ASSIST_MISC 30
40#define CLKID_SD_EMMC_B 31
41#define CLKID_SD_EMMC_C 32
42#define CLKID_DMA 33
43#define CLKID_SPI 34
44#define CLKID_AUDIO 35
45#define CLKID_ETH 36
46#define CLKID_UART1 37
47#define CLKID_G2D 38
48#define CLKID_USB0 39
49#define CLKID_USB1 40
50#define CLKID_RESET 41
51#define CLKID_USB 42
52#define CLKID_AHB_ARB0 43
53#define CLKID_EFUSE 44
54#define CLKID_BOOT_ROM 45
55#define CLKID_AHB_DATA_BUS 46
56#define CLKID_AHB_CTRL_BUS 47
57#define CLKID_USB1_DDR_BRIDGE 48
58#define CLKID_USB0_DDR_BRIDGE 49
59#define CLKID_MMC_PCLK 50
60#define CLKID_VPU_INTR 51
61#define CLKID_SEC_AHB_AHB3_BRIDGE 52
62#define CLKID_GIC 53
63#define CLKID_AO_MEDIA_CPU 54
64#define CLKID_AO_AHB_SRAM 55
65#define CLKID_AO_AHB_BUS 56
66#define CLKID_AO_IFACE 57
67#define CLKID_AO_I2C 58
68#define CLKID_SD_EMMC_B_CLK0 59
69#define CLKID_SD_EMMC_C_CLK0 60
70
71#endif /* __AXG_CLKC_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-24 15:22:01 -0400