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authorArnd Bergmann <arnd@arndb.de>2018-01-05 11:17:25 -0500
committerArnd Bergmann <arnd@arndb.de>2018-01-05 11:17:25 -0500
commit8c11fcc212d763de6e6c068e7153a3b8b36b253d (patch)
treeb678f20198f98a44dc6b8a456a89085f89c38664
parentc503f594d63c221db619c901d36d1139f9ce354f (diff)
parent474c5885582c4a79c21bcf01ed98f98c935f1f4a (diff)
Merge tag 'mvebu-dt64-4.16-2' of git://git.infradead.org/linux-mvebu into next/dt
Pull "mvebu dt64 for 4.16 (part 2)" from Gregory CLEMENT: The main change here are the series of commits doing the Armada 7K/8K CP110 DT de-duplication, they include the de-duplication itself and small fixes in the device tree files. Besides them there are 2 other patches: - One adding the crypto support for Armada 37xx SoCs - An other adding Ethernet aliases on A7K/A8K base boards * tag 'mvebu-dt64-4.16-2' of git://git.infradead.org/linux-mvebu: arm64: dts: marvell: add Ethernet aliases arm64: dts: marvell: replace cpm by cp0, cps by cp1 arm64: dts: marvell: de-duplicate CP110 description arm64: dts: marvell: use aliases for SPI busses on Armada 7K/8K arm64: dts: marvell: use mvebu-icu.h where possible arm64: dts: marvell: fix compatible string list for Armada CP110 slave NAND arm64: dts: marvell: fix typos in comment describing the NAND controller arm64: dts: marvell: use lower case for unit address and reg property arm64: dts: marvell: fix watchdog unit address in Armada AP806 arm64: dts: marvell: armada-37xx: add a crypto node ARM64: dts: marvell: armada-cp110: Fix clock resources for various node ARM: dts: kirkwood: fix pin-muxing of MPP7 on OpenBlocks A7
Diffstat
-rw-r--r--arch/arm/boot/dts/kirkwood-openblocks_a7.dts10
-rw-r--r--arch/arm64/boot/dts/marvell/armada-37xx.dtsi14
-rw-r--r--arch/arm64/boot/dts/marvell/armada-7040-db.dts52
-rw-r--r--arch/arm64/boot/dts/marvell/armada-70x0.dtsi37
-rw-r--r--arch/arm64/boot/dts/marvell/armada-8020.dtsi2
-rw-r--r--arch/arm64/boot/dts/marvell/armada-8040-db.dts87
-rw-r--r--arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts82
-rw-r--r--arch/arm64/boot/dts/marvell/armada-8040.dtsi2
-rw-r--r--arch/arm64/boot/dts/marvell/armada-80x0.dtsi80
-rw-r--r--arch/arm64/boot/dts/marvell/armada-ap806.dtsi8
-rw-r--r--arch/arm64/boot/dts/marvell/armada-common.dtsi10
-rw-r--r--arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi449
-rw-r--r--arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi448
-rw-r--r--arch/arm64/boot/dts/marvell/armada-cp110.dtsi424
14 files changed, 678 insertions, 1027 deletions
diff --git a/arch/arm/boot/dts/kirkwood-openblocks_a7.dts b/arch/arm/boot/dts/kirkwood-openblocks_a7.dts
index cf2f5240e176..27cc913ca0f5 100644
--- a/arch/arm/boot/dts/kirkwood-openblocks_a7.dts
+++ b/arch/arm/boot/dts/kirkwood-openblocks_a7.dts
@@ -53,7 +53,8 @@
53 }; 53 };
54 54
55 pinctrl: pin-controller@10000 { 55 pinctrl: pin-controller@10000 {
56 pinctrl-0 = <&pmx_dip_switches &pmx_gpio_header>; 56 pinctrl-0 = <&pmx_dip_switches &pmx_gpio_header
57 &pmx_gpio_header_gpo>;
57 pinctrl-names = "default"; 58 pinctrl-names = "default";
58 59
59 pmx_uart0: pmx-uart0 { 60 pmx_uart0: pmx-uart0 {
@@ -85,11 +86,16 @@
85 * ground. 86 * ground.
86 */ 87 */
87 pmx_gpio_header: pmx-gpio-header { 88 pmx_gpio_header: pmx-gpio-header {
88 marvell,pins = "mpp17", "mpp7", "mpp29", "mpp28", 89 marvell,pins = "mpp17", "mpp29", "mpp28",
89 "mpp35", "mpp34", "mpp40"; 90 "mpp35", "mpp34", "mpp40";
90 marvell,function = "gpio"; 91 marvell,function = "gpio";
91 }; 92 };
92 93
94 pmx_gpio_header_gpo: pxm-gpio-header-gpo {
95 marvell,pins = "mpp7";
96 marvell,function = "gpo";
97 };
98
93 pmx_gpio_init: pmx-init { 99 pmx_gpio_init: pmx-init {
94 marvell,pins = "mpp38"; 100 marvell,pins = "mpp38";
95 marvell,function = "gpio"; 101 marvell,function = "gpio";
diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
index 3056d7168e0b..375026867342 100644
--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
@@ -316,6 +316,20 @@
316 }; 316 };
317 }; 317 };
318 318
319 crypto: crypto@90000 {
320 compatible = "inside-secure,safexcel-eip97";
321 reg = <0x90000 0x20000>;
322 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
323 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
324 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
325 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
326 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
327 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
328 interrupt-names = "mem", "ring0", "ring1",
329 "ring2", "ring3", "eip";
330 clocks = <&nb_periph_clk 15>;
331 };
332
319 sdhci1: sdhci@d0000 { 333 sdhci1: sdhci@d0000 {
320 compatible = "marvell,armada-3700-sdhci", 334 compatible = "marvell,armada-3700-sdhci",
321 "marvell,sdhci-xenon"; 335 "marvell,sdhci-xenon";
diff --git a/arch/arm64/boot/dts/marvell/armada-7040-db.dts b/arch/arm64/boot/dts/marvell/armada-7040-db.dts
index 52b5341cb270..3ae05eee2c9a 100644
--- a/arch/arm64/boot/dts/marvell/armada-7040-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-7040-db.dts
@@ -61,7 +61,13 @@
61 reg = <0x0 0x0 0x0 0x80000000>; 61 reg = <0x0 0x0 0x0 0x80000000>;
62 }; 62 };
63 63
64 cpm_reg_usb3_0_vbus: cpm-usb3-0-vbus { 64 aliases {
65 ethernet0 = &cp0_eth0;
66 ethernet1 = &cp0_eth1;
67 ethernet2 = &cp0_eth2;
68 };
69
70 cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus {
65 compatible = "regulator-fixed"; 71 compatible = "regulator-fixed";
66 regulator-name = "usb3h0-vbus"; 72 regulator-name = "usb3h0-vbus";
67 regulator-min-microvolt = <5000000>; 73 regulator-min-microvolt = <5000000>;
@@ -70,7 +76,7 @@
70 gpio = <&expander0 0 GPIO_ACTIVE_HIGH>; 76 gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
71 }; 77 };
72 78
73 cpm_reg_usb3_1_vbus: cpm-usb3-1-vbus { 79 cp0_reg_usb3_1_vbus: cp0-usb3-1-vbus {
74 compatible = "regulator-fixed"; 80 compatible = "regulator-fixed";
75 regulator-name = "usb3h1-vbus"; 81 regulator-name = "usb3h1-vbus";
76 regulator-min-microvolt = <5000000>; 82 regulator-min-microvolt = <5000000>;
@@ -79,14 +85,14 @@
79 gpio = <&expander0 1 GPIO_ACTIVE_HIGH>; 85 gpio = <&expander0 1 GPIO_ACTIVE_HIGH>;
80 }; 86 };
81 87
82 cpm_usb3_0_phy: cpm-usb3-0-phy { 88 cp0_usb3_0_phy: cp0-usb3-0-phy {
83 compatible = "usb-nop-xceiv"; 89 compatible = "usb-nop-xceiv";
84 vcc-supply = <&cpm_reg_usb3_0_vbus>; 90 vcc-supply = <&cp0_reg_usb3_0_vbus>;
85 }; 91 };
86 92
87 cpm_usb3_1_phy: cpm-usb3-1-phy { 93 cp0_usb3_1_phy: cp0-usb3-1-phy {
88 compatible = "usb-nop-xceiv"; 94 compatible = "usb-nop-xceiv";
89 vcc-supply = <&cpm_reg_usb3_1_vbus>; 95 vcc-supply = <&cp0_reg_usb3_1_vbus>;
90 }; 96 };
91}; 97};
92 98
@@ -129,11 +135,11 @@
129}; 135};
130 136
131 137
132&cpm_pcie2 { 138&cp0_pcie2 {
133 status = "okay"; 139 status = "okay";
134}; 140};
135 141
136&cpm_i2c0 { 142&cp0_i2c0 {
137 status = "okay"; 143 status = "okay";
138 clock-frequency = <100000>; 144 clock-frequency = <100000>;
139 145
@@ -156,7 +162,7 @@
156 }; 162 };
157}; 163};
158 164
159&cpm_nand { 165&cp0_nand {
160 /* 166 /*
161 * SPI on CPM and NAND have common pins on this board. We can 167 * SPI on CPM and NAND have common pins on this board. We can
162 * use only one at a time. To enable the NAND (whihch will 168 * use only one at a time. To enable the NAND (whihch will
@@ -186,7 +192,7 @@
186}; 192};
187 193
188 194
189&cpm_spi1 { 195&cp0_spi1 {
190 status = "okay"; 196 status = "okay";
191 197
192 spi-flash@0 { 198 spi-flash@0 {
@@ -214,17 +220,17 @@
214 }; 220 };
215}; 221};
216 222
217&cpm_sata0 { 223&cp0_sata0 {
218 status = "okay"; 224 status = "okay";
219}; 225};
220 226
221&cpm_usb3_0 { 227&cp0_usb3_0 {
222 usb-phy = <&cpm_usb3_0_phy>; 228 usb-phy = <&cp0_usb3_0_phy>;
223 status = "okay"; 229 status = "okay";
224}; 230};
225 231
226&cpm_usb3_1 { 232&cp0_usb3_1 {
227 usb-phy = <&cpm_usb3_1_phy>; 233 usb-phy = <&cp0_usb3_1_phy>;
228 status = "okay"; 234 status = "okay";
229}; 235};
230 236
@@ -235,14 +241,14 @@
235 non-removable; 241 non-removable;
236}; 242};
237 243
238&cpm_sdhci0 { 244&cp0_sdhci0 {
239 status = "okay"; 245 status = "okay";
240 bus-width = <4>; 246 bus-width = <4>;
241 no-1-8-v; 247 no-1-8-v;
242 cd-gpios = <&expander0 12 GPIO_ACTIVE_LOW>; 248 cd-gpios = <&expander0 12 GPIO_ACTIVE_LOW>;
243}; 249};
244 250
245&cpm_mdio { 251&cp0_mdio {
246 status = "okay"; 252 status = "okay";
247 253
248 phy0: ethernet-phy@0 { 254 phy0: ethernet-phy@0 {
@@ -253,28 +259,28 @@
253 }; 259 };
254}; 260};
255 261
256&cpm_ethernet { 262&cp0_ethernet {
257 status = "okay"; 263 status = "okay";
258}; 264};
259 265
260&cpm_eth0 { 266&cp0_eth0 {
261 status = "okay"; 267 status = "okay";
262 /* Network PHY */ 268 /* Network PHY */
263 phy-mode = "10gbase-kr"; 269 phy-mode = "10gbase-kr";
264 /* Generic PHY, providing serdes lanes */ 270 /* Generic PHY, providing serdes lanes */
265 phys = <&cpm_comphy2 0>; 271 phys = <&cp0_comphy2 0>;
266}; 272};
267 273
268&cpm_eth1 { 274&cp0_eth1 {
269 status = "okay"; 275 status = "okay";
270 /* Network PHY */ 276 /* Network PHY */
271 phy = <&phy0>; 277 phy = <&phy0>;
272 phy-mode = "sgmii"; 278 phy-mode = "sgmii";
273 /* Generic PHY, providing serdes lanes */ 279 /* Generic PHY, providing serdes lanes */
274 phys = <&cpm_comphy0 1>; 280 phys = <&cp0_comphy0 1>;
275}; 281};
276 282
277&cpm_eth2 { 283&cp0_eth2 {
278 status = "okay"; 284 status = "okay";
279 phy = <&phy1>; 285 phy = <&phy1>;
280 phy-mode = "rgmii-id"; 286 phy-mode = "rgmii-id";
diff --git a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
index 0e1a1e5be399..f63b4fbd642b 100644
--- a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
@@ -44,25 +44,46 @@
44 * Device Tree file for the Armada 70x0 SoC 44 * Device Tree file for the Armada 70x0 SoC
45 */ 45 */
46 46
47#include "armada-cp110-master.dtsi"
48
49/ { 47/ {
50 aliases { 48 aliases {
51 gpio1 = &cpm_gpio1; 49 gpio1 = &cp0_gpio1;
52 gpio2 = &cpm_gpio2; 50 gpio2 = &cp0_gpio2;
51 spi1 = &cp0_spi0;
52 spi2 = &cp0_spi1;
53 }; 53 };
54}; 54};
55 55
56&cpm_gpio1 { 56/*
57 * Instantiate the CP110
58 */
59#define CP110_NAME cp0
60#define CP110_BASE f2000000
61#define CP110_PCIE_IO_BASE 0xf9000000
62#define CP110_PCIE_MEM_BASE 0xf6000000
63#define CP110_PCIE0_BASE f2600000
64#define CP110_PCIE1_BASE f2620000
65#define CP110_PCIE2_BASE f2640000
66
67#include "armada-cp110.dtsi"
68
69#undef CP110_NAME
70#undef CP110_BASE
71#undef CP110_PCIE_IO_BASE
72#undef CP110_PCIE_MEM_BASE
73#undef CP110_PCIE0_BASE
74#undef CP110_PCIE1_BASE
75#undef CP110_PCIE2_BASE
76
77&cp0_gpio1 {
57 status = "okay"; 78 status = "okay";
58}; 79};
59 80
60&cpm_gpio2 { 81&cp0_gpio2 {
61 status = "okay"; 82 status = "okay";
62}; 83};
63 84
64&cpm_syscon0 { 85&cp0_syscon0 {
65 cpm_pinctrl: pinctrl { 86 cp0_pinctrl: pinctrl {
66 compatible = "marvell,armada-7k-pinctrl"; 87 compatible = "marvell,armada-7k-pinctrl";
67 88
68 nand_pins: nand-pins { 89 nand_pins: nand-pins {
diff --git a/arch/arm64/boot/dts/marvell/armada-8020.dtsi b/arch/arm64/boot/dts/marvell/armada-8020.dtsi
index 0ba0bc942598..3318d6b0214b 100644
--- a/arch/arm64/boot/dts/marvell/armada-8020.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-8020.dtsi
@@ -60,6 +60,6 @@
60 * oscillator so this one is let enabled. 60 * oscillator so this one is let enabled.
61 */ 61 */
62 62
63&cpm_rtc { 63&cp0_rtc {
64 status = "disabled"; 64 status = "disabled";
65}; 65};
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-db.dts b/arch/arm64/boot/dts/marvell/armada-8040-db.dts
index b1f6cccc5081..dba55baff20f 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-8040-db.dts
@@ -61,46 +61,53 @@
61 reg = <0x0 0x0 0x0 0x80000000>; 61 reg = <0x0 0x0 0x0 0x80000000>;
62 }; 62 };
63 63
64 cpm_reg_usb3_0_vbus: cpm-usb3-0-vbus { 64 aliases {
65 ethernet0 = &cp0_eth0;
66 ethernet1 = &cp0_eth2;
67 ethernet2 = &cp1_eth0;
68 ethernet3 = &cp1_eth1;
69 };
70
71 cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus {
65 compatible = "regulator-fixed"; 72 compatible = "regulator-fixed";
66 regulator-name = "cpm-usb3h0-vbus"; 73 regulator-name = "cp0-usb3h0-vbus";
67 regulator-min-microvolt = <5000000>; 74 regulator-min-microvolt = <5000000>;
68 regulator-max-microvolt = <5000000>; 75 regulator-max-microvolt = <5000000>;
69 enable-active-high; 76 enable-active-high;
70 gpio = <&expander0 0 GPIO_ACTIVE_HIGH>; 77 gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
71 }; 78 };
72 79
73 cpm_reg_usb3_1_vbus: cpm-usb3-1-vbus { 80 cp0_reg_usb3_1_vbus: cp0-usb3-1-vbus {
74 compatible = "regulator-fixed"; 81 compatible = "regulator-fixed";
75 regulator-name = "cpm-usb3h1-vbus"; 82 regulator-name = "cp0-usb3h1-vbus";
76 regulator-min-microvolt = <5000000>; 83 regulator-min-microvolt = <5000000>;
77 regulator-max-microvolt = <5000000>; 84 regulator-max-microvolt = <5000000>;
78 enable-active-high; 85 enable-active-high;
79 gpio = <&expander0 1 GPIO_ACTIVE_HIGH>; 86 gpio = <&expander0 1 GPIO_ACTIVE_HIGH>;
80 }; 87 };
81 88
82 cpm_usb3_0_phy: cpm-usb3-0-phy { 89 cp0_usb3_0_phy: cp0-usb3-0-phy {
83 compatible = "usb-nop-xceiv"; 90 compatible = "usb-nop-xceiv";
84 vcc-supply = <&cpm_reg_usb3_0_vbus>; 91 vcc-supply = <&cp0_reg_usb3_0_vbus>;
85 }; 92 };
86 93
87 cpm_usb3_1_phy: cpm-usb3-1-phy { 94 cp0_usb3_1_phy: cp0-usb3-1-phy {
88 compatible = "usb-nop-xceiv"; 95 compatible = "usb-nop-xceiv";
89 vcc-supply = <&cpm_reg_usb3_1_vbus>; 96 vcc-supply = <&cp0_reg_usb3_1_vbus>;
90 }; 97 };
91 98
92 cps_reg_usb3_0_vbus: cps-usb3-0-vbus { 99 cp1_reg_usb3_0_vbus: cp1-usb3-0-vbus {
93 compatible = "regulator-fixed"; 100 compatible = "regulator-fixed";
94 regulator-name = "cps-usb3h0-vbus"; 101 regulator-name = "cp1-usb3h0-vbus";
95 regulator-min-microvolt = <5000000>; 102 regulator-min-microvolt = <5000000>;
96 regulator-max-microvolt = <5000000>; 103 regulator-max-microvolt = <5000000>;
97 enable-active-high; 104 enable-active-high;
98 gpio = <&expander1 0 GPIO_ACTIVE_HIGH>; 105 gpio = <&expander1 0 GPIO_ACTIVE_HIGH>;
99 }; 106 };
100 107
101 cps_usb3_0_phy: cps-usb3-0-phy { 108 cp1_usb3_0_phy: cp1-usb3-0-phy {
102 compatible = "usb-nop-xceiv"; 109 compatible = "usb-nop-xceiv";
103 vcc-supply = <&cps_reg_usb3_0_vbus>; 110 vcc-supply = <&cp1_reg_usb3_0_vbus>;
104 }; 111 };
105}; 112};
106 113
@@ -144,16 +151,16 @@
144}; 151};
145 152
146/* CON6 on CP0 expansion */ 153/* CON6 on CP0 expansion */
147&cpm_pcie0 { 154&cp0_pcie0 {
148 status = "okay"; 155 status = "okay";
149}; 156};
150 157
151/* CON5 on CP0 expansion */ 158/* CON5 on CP0 expansion */
152&cpm_pcie2 { 159&cp0_pcie2 {
153 status = "okay"; 160 status = "okay";
154}; 161};
155 162
156&cpm_i2c0 { 163&cp0_i2c0 {
157 status = "okay"; 164 status = "okay";
158 clock-frequency = <100000>; 165 clock-frequency = <100000>;
159 166
@@ -178,23 +185,23 @@
178}; 185};
179 186
180/* CON4 on CP0 expansion */ 187/* CON4 on CP0 expansion */
181&cpm_sata0 { 188&cp0_sata0 {
182 status = "okay"; 189 status = "okay";
183}; 190};
184 191
185/* CON9 on CP0 expansion */ 192/* CON9 on CP0 expansion */
186&cpm_usb3_0 { 193&cp0_usb3_0 {
187 usb-phy = <&cpm_usb3_0_phy>; 194 usb-phy = <&cp0_usb3_0_phy>;
188 status = "okay"; 195 status = "okay";
189}; 196};
190 197
191/* CON10 on CP0 expansion */ 198/* CON10 on CP0 expansion */
192&cpm_usb3_1 { 199&cp0_usb3_1 {
193 usb-phy = <&cpm_usb3_1_phy>; 200 usb-phy = <&cp0_usb3_1_phy>;
194 status = "okay"; 201 status = "okay";
195}; 202};
196 203
197&cpm_mdio { 204&cp0_mdio {
198 status = "okay"; 205 status = "okay";
199 206
200 phy1: ethernet-phy@1 { 207 phy1: ethernet-phy@1 {
@@ -202,42 +209,42 @@
202 }; 209 };
203}; 210};
204 211
205&cpm_ethernet { 212&cp0_ethernet {
206 status = "okay"; 213 status = "okay";
207}; 214};
208 215
209&cpm_eth0 { 216&cp0_eth0 {
210 status = "okay"; 217 status = "okay";
211 phy-mode = "10gbase-kr"; 218 phy-mode = "10gbase-kr";
212}; 219};
213 220
214&cpm_eth2 { 221&cp0_eth2 {
215 status = "okay"; 222 status = "okay";
216 phy = <&phy1>; 223 phy = <&phy1>;
217 phy-mode = "rgmii-id"; 224 phy-mode = "rgmii-id";
218}; 225};
219 226
220/* CON6 on CP1 expansion */ 227/* CON6 on CP1 expansion */
221&cps_pcie0 { 228&cp1_pcie0 {
222 status = "okay"; 229 status = "okay";
223}; 230};
224 231
225/* CON7 on CP1 expansion */ 232/* CON7 on CP1 expansion */
226&cps_pcie1 { 233&cp1_pcie1 {
227 status = "okay"; 234 status = "okay";
228}; 235};
229 236
230/* CON5 on CP1 expansion */ 237/* CON5 on CP1 expansion */
231&cps_pcie2 { 238&cp1_pcie2 {
232 status = "okay"; 239 status = "okay";
233}; 240};
234 241
235&cps_i2c0 { 242&cp1_i2c0 {
236 status = "okay"; 243 status = "okay";
237 clock-frequency = <100000>; 244 clock-frequency = <100000>;
238}; 245};
239 246
240&cps_spi1 { 247&cp1_spi1 {
241 status = "okay"; 248 status = "okay";
242 249
243 spi-flash@0 { 250 spi-flash@0 {
@@ -272,14 +279,14 @@
272 * Proper NAND usage will require DPR-76 to be in position 1-2, which disables 279 * Proper NAND usage will require DPR-76 to be in position 1-2, which disables
273 * MDIO signal of CP1. 280 * MDIO signal of CP1.
274 */ 281 */
275&cps_nand { 282&cp1_nand {
276 num-cs = <1>; 283 num-cs = <1>;
277 pinctrl-0 = <&nand_pins>, <&nand_rb>; 284 pinctrl-0 = <&nand_pins>, <&nand_rb>;
278 pinctrl-names = "default"; 285 pinctrl-names = "default";
279 nand-ecc-strength = <4>; 286 nand-ecc-strength = <4>;
280 nand-ecc-step-size = <512>; 287 nand-ecc-step-size = <512>;
281 marvell,nand-enable-arbiter; 288 marvell,nand-enable-arbiter;
282 marvell,system-controller = <&cps_syscon0>; 289 marvell,system-controller = <&cp1_syscon0>;
283 nand-on-flash-bbt; 290 nand-on-flash-bbt;
284 291
285 partition@0 { 292 partition@0 {
@@ -297,22 +304,22 @@
297}; 304};
298 305
299/* CON4 on CP1 expansion */ 306/* CON4 on CP1 expansion */
300&cps_sata0 { 307&cp1_sata0 {
301 status = "okay"; 308 status = "okay";
302}; 309};
303 310
304/* CON9 on CP1 expansion */ 311/* CON9 on CP1 expansion */
305&cps_usb3_0 { 312&cp1_usb3_0 {
306 usb-phy = <&cps_usb3_0_phy>; 313 usb-phy = <&cp1_usb3_0_phy>;
307 status = "okay"; 314 status = "okay";
308}; 315};
309 316
310/* CON10 on CP1 expansion */ 317/* CON10 on CP1 expansion */
311&cps_usb3_1 { 318&cp1_usb3_1 {
312 status = "okay"; 319 status = "okay";
313}; 320};
314 321
315&cps_mdio { 322&cp1_mdio {
316 status = "okay"; 323 status = "okay";
317 324
318 phy0: ethernet-phy@0 { 325 phy0: ethernet-phy@0 {
@@ -320,16 +327,16 @@
320 }; 327 };
321}; 328};
322 329
323&cps_ethernet { 330&cp1_ethernet {
324 status = "okay"; 331 status = "okay";
325}; 332};
326 333
327&cps_eth0 { 334&cp1_eth0 {
328 status = "okay"; 335 status = "okay";
329 phy-mode = "10gbase-kr"; 336 phy-mode = "10gbase-kr";
330}; 337};
331 338
332&cps_eth1 { 339&cp1_eth1 {
333 status = "okay"; 340 status = "okay";
334 phy = <&phy0>; 341 phy = <&phy0>;
335 phy-mode = "rgmii-id"; 342 phy-mode = "rgmii-id";
@@ -341,7 +348,7 @@
341 non-removable; 348 non-removable;
342}; 349};
343 350
344&cpm_sdhci0 { 351&cp0_sdhci0 {
345 status = "okay"; 352 status = "okay";
346 bus-width = <8>; 353 bus-width = <8>;
347 non-removable; 354 non-removable;
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts
index b3350827ee55..626e9d0462c3 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts
+++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts
@@ -62,6 +62,12 @@
62 reg = <0x0 0x0 0x0 0x80000000>; 62 reg = <0x0 0x0 0x0 0x80000000>;
63 }; 63 };
64 64
65 aliases {
66 ethernet0 = &cp0_eth0;
67 ethernet1 = &cp1_eth0;
68 ethernet2 = &cp1_eth1;
69 };
70
65 /* Regulator labels correspond with schematics */ 71 /* Regulator labels correspond with schematics */
66 v_3_3: regulator-3-3v { 72 v_3_3: regulator-3-3v {
67 compatible = "regulator-fixed"; 73 compatible = "regulator-fixed";
@@ -84,9 +90,9 @@
84 v_5v0_usb3_hst_vbus: regulator-usb3-vbus0 { 90 v_5v0_usb3_hst_vbus: regulator-usb3-vbus0 {
85 compatible = "regulator-fixed"; 91 compatible = "regulator-fixed";
86 enable-active-high; 92 enable-active-high;
87 gpio = <&cpm_gpio2 15 GPIO_ACTIVE_HIGH>; 93 gpio = <&cp0_gpio2 15 GPIO_ACTIVE_HIGH>;
88 pinctrl-names = "default"; 94 pinctrl-names = "default";
89 pinctrl-0 = <&cpm_xhci_vbus_pins>; 95 pinctrl-0 = <&cp0_xhci_vbus_pins>;
90 regulator-name = "v_5v0_usb3_hst_vbus"; 96 regulator-name = "v_5v0_usb3_hst_vbus";
91 regulator-min-microvolt = <5000000>; 97 regulator-min-microvolt = <5000000>;
92 regulator-max-microvolt = <5000000>; 98 regulator-max-microvolt = <5000000>;
@@ -120,17 +126,17 @@
120 vqmmc-supply = <&v_vddo_h>; 126 vqmmc-supply = <&v_vddo_h>;
121}; 127};
122 128
123&cpm_i2c0 { 129&cp0_i2c0 {
124 clock-frequency = <100000>; 130 clock-frequency = <100000>;
125 pinctrl-names = "default"; 131 pinctrl-names = "default";
126 pinctrl-0 = <&cpm_i2c0_pins>; 132 pinctrl-0 = <&cp0_i2c0_pins>;
127 status = "okay"; 133 status = "okay";
128}; 134};
129 135
130&cpm_i2c1 { 136&cp0_i2c1 {
131 clock-frequency = <100000>; 137 clock-frequency = <100000>;
132 pinctrl-names = "default"; 138 pinctrl-names = "default";
133 pinctrl-0 = <&cpm_i2c1_pins>; 139 pinctrl-0 = <&cp0_i2c1_pins>;
134 status = "okay"; 140 status = "okay";
135 141
136 i2c-switch@70 { 142 i2c-switch@70 {
@@ -157,9 +163,9 @@
157 }; 163 };
158}; 164};
159 165
160&cpm_mdio { 166&cp0_mdio {
161 pinctrl-names = "default"; 167 pinctrl-names = "default";
162 pinctrl-0 = <&cpm_ge_mdio_pins>; 168 pinctrl-0 = <&cp0_ge_mdio_pins>;
163 status = "okay"; 169 status = "okay";
164 170
165 ge_phy: ethernet-phy@0 { 171 ge_phy: ethernet-phy@0 {
@@ -167,44 +173,44 @@
167 }; 173 };
168}; 174};
169 175
170&cpm_pcie0 { 176&cp0_pcie0 {
171 pinctrl-names = "default"; 177 pinctrl-names = "default";
172 pinctrl-0 = <&cpm_pcie_pins>; 178 pinctrl-0 = <&cp0_pcie_pins>;
173 num-lanes = <4>; 179 num-lanes = <4>;
174 num-viewport = <8>; 180 num-viewport = <8>;
175 reset-gpio = <&cpm_gpio1 20 GPIO_ACTIVE_LOW>; 181 reset-gpio = <&cp0_gpio1 20 GPIO_ACTIVE_LOW>;
176 status = "okay"; 182 status = "okay";
177}; 183};
178 184
179&cpm_pinctrl { 185&cp0_pinctrl {
180 cpm_ge_mdio_pins: ge-mdio-pins { 186 cp0_ge_mdio_pins: ge-mdio-pins {
181 marvell,pins = "mpp32", "mpp34"; 187 marvell,pins = "mpp32", "mpp34";
182 marvell,function = "ge"; 188 marvell,function = "ge";
183 }; 189 };
184 cpm_i2c1_pins: i2c1-pins { 190 cp0_i2c1_pins: i2c1-pins {
185 marvell,pins = "mpp35", "mpp36"; 191 marvell,pins = "mpp35", "mpp36";
186 marvell,function = "i2c1"; 192 marvell,function = "i2c1";
187 }; 193 };
188 cpm_i2c0_pins: i2c0-pins { 194 cp0_i2c0_pins: i2c0-pins {
189 marvell,pins = "mpp37", "mpp38"; 195 marvell,pins = "mpp37", "mpp38";
190 marvell,function = "i2c0"; 196 marvell,function = "i2c0";
191 }; 197 };
192 cpm_xhci_vbus_pins: xhci0-vbus-pins { 198 cp0_xhci_vbus_pins: xhci0-vbus-pins {
193 marvell,pins = "mpp47"; 199 marvell,pins = "mpp47";
194 marvell,function = "gpio"; 200 marvell,function = "gpio";
195 }; 201 };
196 cpm_pcie_pins: pcie-pins { 202 cp0_pcie_pins: pcie-pins {
197 marvell,pins = "mpp52"; 203 marvell,pins = "mpp52";
198 marvell,function = "gpio"; 204 marvell,function = "gpio";
199 }; 205 };
200 cpm_sdhci_pins: sdhci-pins { 206 cp0_sdhci_pins: sdhci-pins {
201 marvell,pins = "mpp55", "mpp56", "mpp57", "mpp58", "mpp59", 207 marvell,pins = "mpp55", "mpp56", "mpp57", "mpp58", "mpp59",
202 "mpp60", "mpp61"; 208 "mpp60", "mpp61";
203 marvell,function = "sdio"; 209 marvell,function = "sdio";
204 }; 210 };
205}; 211};
206 212
207&cpm_xmdio { 213&cp0_xmdio {
208 status = "okay"; 214 status = "okay";
209 215
210 phy0: ethernet-phy@0 { 216 phy0: ethernet-phy@0 {
@@ -218,83 +224,83 @@
218 }; 224 };
219}; 225};
220 226
221&cpm_ethernet { 227&cp0_ethernet {
222 status = "okay"; 228 status = "okay";
223}; 229};
224 230
225&cpm_eth0 { 231&cp0_eth0 {
226 status = "okay"; 232 status = "okay";
227 /* Network PHY */ 233 /* Network PHY */
228 phy = <&phy0>; 234 phy = <&phy0>;
229 phy-mode = "10gbase-kr"; 235 phy-mode = "10gbase-kr";
230 /* Generic PHY, providing serdes lanes */ 236 /* Generic PHY, providing serdes lanes */
231 phys = <&cpm_comphy4 0>; 237 phys = <&cp0_comphy4 0>;
232}; 238};
233 239
234&cpm_sata0 { 240&cp0_sata0 {
235 /* CPM Lane 0 - U29 */ 241 /* CPM Lane 0 - U29 */
236 status = "okay"; 242 status = "okay";
237}; 243};
238 244
239&cpm_sdhci0 { 245&cp0_sdhci0 {
240 /* U6 */ 246 /* U6 */
241 broken-cd; 247 broken-cd;
242 bus-width = <4>; 248 bus-width = <4>;
243 pinctrl-names = "default"; 249 pinctrl-names = "default";
244 pinctrl-0 = <&cpm_sdhci_pins>; 250 pinctrl-0 = <&cp0_sdhci_pins>;
245 status = "okay"; 251 status = "okay";
246 vqmmc-supply = <&v_3_3>; 252 vqmmc-supply = <&v_3_3>;
247}; 253};
248 254
249&cpm_usb3_0 { 255&cp0_usb3_0 {
250 /* J38? - USB2.0 only */ 256 /* J38? - USB2.0 only */
251 status = "okay"; 257 status = "okay";
252}; 258};
253 259
254&cpm_usb3_1 { 260&cp0_usb3_1 {
255 /* J38? - USB2.0 only */ 261 /* J38? - USB2.0 only */
256 status = "okay"; 262 status = "okay";
257}; 263};
258 264
259&cps_ethernet { 265&cp1_ethernet {
260 status = "okay"; 266 status = "okay";
261}; 267};
262 268
263&cps_eth0 { 269&cp1_eth0 {
264 status = "okay"; 270 status = "okay";
265 /* Network PHY */ 271 /* Network PHY */
266 phy = <&phy8>; 272 phy = <&phy8>;
267 phy-mode = "10gbase-kr"; 273 phy-mode = "10gbase-kr";
268 /* Generic PHY, providing serdes lanes */ 274 /* Generic PHY, providing serdes lanes */
269 phys = <&cps_comphy4 0>; 275 phys = <&cp1_comphy4 0>;
270}; 276};
271 277
272&cps_eth1 { 278&cp1_eth1 {
273 /* CPS Lane 0 - J5 (Gigabit RJ45) */ 279 /* CPS Lane 0 - J5 (Gigabit RJ45) */
274 status = "okay"; 280 status = "okay";
275 /* Network PHY */ 281 /* Network PHY */
276 phy = <&ge_phy>; 282 phy = <&ge_phy>;
277 phy-mode = "sgmii"; 283 phy-mode = "sgmii";
278 /* Generic PHY, providing serdes lanes */ 284 /* Generic PHY, providing serdes lanes */
279 phys = <&cps_comphy0 1>; 285 phys = <&cp1_comphy0 1>;
280}; 286};
281 287
282&cps_pinctrl { 288&cp1_pinctrl {
283 cps_spi1_pins: spi1-pins { 289 cp1_spi1_pins: spi1-pins {
284 marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15", "mpp16"; 290 marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15", "mpp16";
285 marvell,function = "spi1"; 291 marvell,function = "spi1";
286 }; 292 };
287}; 293};
288 294
289&cps_sata0 { 295&cp1_sata0 {
290 /* CPS Lane 1 - U32 */ 296 /* CPS Lane 1 - U32 */
291 /* CPS Lane 3 - U31 */ 297 /* CPS Lane 3 - U31 */
292 status = "okay"; 298 status = "okay";
293}; 299};
294 300
295&cps_spi1 { 301&cp1_spi1 {
296 pinctrl-names = "default"; 302 pinctrl-names = "default";
297 pinctrl-0 = <&cps_spi1_pins>; 303 pinctrl-0 = <&cp1_spi1_pins>;
298 status = "okay"; 304 status = "okay";
299 305
300 spi-flash@0 { 306 spi-flash@0 {
@@ -304,7 +310,7 @@
304 }; 310 };
305}; 311};
306 312
307&cps_usb3_0 { 313&cp1_usb3_0 {
308 /* CPS Lane 2 - CON7 */ 314 /* CPS Lane 2 - CON7 */
309 usb-phy = <&usb3h0_phy>; 315 usb-phy = <&usb3h0_phy>;
310 status = "okay"; 316 status = "okay";
diff --git a/arch/arm64/boot/dts/marvell/armada-8040.dtsi b/arch/arm64/boot/dts/marvell/armada-8040.dtsi
index 60fe84f5cbcc..83d2b40e5981 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-8040.dtsi
@@ -59,6 +59,6 @@
59 * disable it. However, the RTC clock in CP slave is connected to the 59 * disable it. However, the RTC clock in CP slave is connected to the
60 * oscillator so this one is let enabled. 60 * oscillator so this one is let enabled.
61 */ 61 */
62&cpm_rtc { 62&cp0_rtc {
63 status = "disabled"; 63 status = "disabled";
64}; 64};
diff --git a/arch/arm64/boot/dts/marvell/armada-80x0.dtsi b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
index b280ddd3c397..0d36b0fa7153 100644
--- a/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
@@ -44,34 +44,77 @@
44 * Device Tree file for the Armada 80x0 SoC family 44 * Device Tree file for the Armada 80x0 SoC family
45 */ 45 */
46 46
47#include "armada-cp110-master.dtsi"
48#include "armada-cp110-slave.dtsi"
49
50/ { 47/ {
51 aliases { 48 aliases {
52 gpio1 = &cps_gpio1; 49 gpio1 = &cp1_gpio1;
53 gpio2 = &cpm_gpio2; 50 gpio2 = &cp0_gpio2;
51 spi1 = &cp0_spi0;
52 spi2 = &cp0_spi1;
53 spi3 = &cp1_spi0;
54 spi4 = &cp1_spi1;
54 }; 55 };
55}; 56};
56 57
58/*
59 * Instantiate the master CP110
60 */
61#define CP110_NAME cp0
62#define CP110_BASE f2000000
63#define CP110_PCIE_IO_BASE 0xf9000000
64#define CP110_PCIE_MEM_BASE 0xf6000000
65#define CP110_PCIE0_BASE f2600000
66#define CP110_PCIE1_BASE f2620000
67#define CP110_PCIE2_BASE f2640000
68
69#include "armada-cp110.dtsi"
70
71#undef CP110_NAME
72#undef CP110_BASE
73#undef CP110_PCIE_IO_BASE
74#undef CP110_PCIE_MEM_BASE
75#undef CP110_PCIE0_BASE
76#undef CP110_PCIE1_BASE
77#undef CP110_PCIE2_BASE
78
79/*
80 * Instantiate the slave CP110
81 */
82#define CP110_NAME cp1
83#define CP110_BASE f4000000
84#define CP110_PCIE_IO_BASE 0xfd000000
85#define CP110_PCIE_MEM_BASE 0xfa000000
86#define CP110_PCIE0_BASE f4600000
87#define CP110_PCIE1_BASE f4620000
88#define CP110_PCIE2_BASE f4640000
89
90#include "armada-cp110.dtsi"
91
92#undef CP110_NAME
93#undef CP110_BASE
94#undef CP110_PCIE_IO_BASE
95#undef CP110_PCIE_MEM_BASE
96#undef CP110_PCIE0_BASE
97#undef CP110_PCIE1_BASE
98#undef CP110_PCIE2_BASE
99
57/* The 80x0 has two CP blocks, but uses only one block from each. */ 100/* The 80x0 has two CP blocks, but uses only one block from each. */
58&cps_gpio1 { 101&cp1_gpio1 {
59 status = "okay"; 102 status = "okay";
60}; 103};
61 104
62&cpm_gpio2 { 105&cp0_gpio2 {
63 status = "okay"; 106 status = "okay";
64}; 107};
65 108
66&cpm_syscon0 { 109&cp0_syscon0 {
67 cpm_pinctrl: pinctrl { 110 cp0_pinctrl: pinctrl {
68 compatible = "marvell,armada-8k-cpm-pinctrl"; 111 compatible = "marvell,armada-8k-cp0-pinctrl";
69 }; 112 };
70}; 113};
71 114
72&cps_syscon0 { 115&cp1_syscon0 {
73 cps_pinctrl: pinctrl { 116 cp1_pinctrl: pinctrl {
74 compatible = "marvell,armada-8k-cps-pinctrl"; 117 compatible = "marvell,armada-8k-cp1-pinctrl";
75 118
76 nand_pins: nand-pins { 119 nand_pins: nand-pins {
77 marvell,pins = 120 marvell,pins =
@@ -91,3 +134,14 @@
91 }; 134 };
92 }; 135 };
93}; 136};
137
138&cp1_crypto {
139 /*
140 * The cryptographic engine found on the cp110
141 * master is enabled by default at the SoC
142 * level. Because it is not possible as of now
143 * to enable two cryptographic engines in
144 * parallel, disable this one by default.
145 */
146 status = "disabled";
147};
diff --git a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
index bbc5a4d3acac..f9b66b81f9fc 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
@@ -58,6 +58,7 @@
58 serial0 = &uart0; 58 serial0 = &uart0;
59 serial1 = &uart1; 59 serial1 = &uart1;
60 gpio0 = &ap_gpio; 60 gpio0 = &ap_gpio;
61 spi0 = &spi0;
61 }; 62 };
62 63
63 psci { 64 psci {
@@ -203,7 +204,6 @@
203 reg = <0x510600 0x50>; 204 reg = <0x510600 0x50>;
204 #address-cells = <1>; 205 #address-cells = <1>;
205 #size-cells = <0>; 206 #size-cells = <0>;
206 cell-index = <0>;
207 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 207 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
208 clocks = <&ap_clk 3>; 208 clocks = <&ap_clk 3>;
209 status = "disabled"; 209 status = "disabled";
@@ -241,7 +241,7 @@
241 241
242 }; 242 };
243 243
244 watchdog: watchdog@600000 { 244 watchdog: watchdog@610000 {
245 compatible = "arm,sbsa-gwdt"; 245 compatible = "arm,sbsa-gwdt";
246 reg = <0x610000 0x1000>, <0x600000 0x1000>; 246 reg = <0x610000 0x1000>, <0x600000 0x1000>;
247 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 247 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
@@ -286,9 +286,9 @@
286 }; 286 };
287 }; 287 };
288 288
289 ap_thermal: thermal@6f808C { 289 ap_thermal: thermal@6f808c {
290 compatible = "marvell,armada-ap806-thermal"; 290 compatible = "marvell,armada-ap806-thermal";
291 reg = <0x6f808C 0x4>, 291 reg = <0x6f808c 0x4>,
292 <0x6f8084 0x8>; 292 <0x6f8084 0x8>;
293 }; 293 };
294 }; 294 };
diff --git a/arch/arm64/boot/dts/marvell/armada-common.dtsi b/arch/arm64/boot/dts/marvell/armada-common.dtsi
new file mode 100644
index 000000000000..c6dd1d81c68d
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/armada-common.dtsi
@@ -0,0 +1,10 @@
1// SPDX-License-Identifier: (GPL-2.0+ OR X11)
2/*
3 * Copyright (C) 2016 Marvell Technology Group Ltd.
4 */
5
6/* Common definitions used by Armada 7K/8K DTs */
7#define PASTER(x, y) x ## y
8#define EVALUATOR(x, y) PASTER(x, y)
9#define CP110_LABEL(name) EVALUATOR(CP110_NAME, EVALUATOR(_, name))
10#define ADDRESSIFY(addr) EVALUATOR(0x, addr)
diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
deleted file mode 100644
index ecbc76d26dff..000000000000
--- a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
+++ /dev/null
@@ -1,449 +0,0 @@
1/*
2 * Copyright (C) 2016 Marvell Technology Group Ltd.
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPLv2 or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43/*
44 * Device Tree file for Marvell Armada CP110 Master.
45 */
46
47#define ICU_GRP_NSR 0x0
48
49/ {
50 cp110-master {
51 #address-cells = <2>;
52 #size-cells = <2>;
53 compatible = "simple-bus";
54 interrupt-parent = <&cpm_icu>;
55 ranges;
56
57 config-space@f2000000 {
58 #address-cells = <1>;
59 #size-cells = <1>;
60 compatible = "simple-bus";
61 ranges = <0x0 0x0 0xf2000000 0x2000000>;
62
63 cpm_ethernet: ethernet@0 {
64 compatible = "marvell,armada-7k-pp22";
65 reg = <0x0 0x100000>, <0x129000 0xb000>;
66 clocks = <&cpm_clk 1 3>, <&cpm_clk 1 9>, <&cpm_clk 1 5>;
67 clock-names = "pp_clk", "gop_clk", "mg_clk";
68 marvell,system-controller = <&cpm_syscon0>;
69 status = "disabled";
70 dma-coherent;
71
72 cpm_eth0: eth0 {
73 interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>,
74 <ICU_GRP_NSR 43 IRQ_TYPE_LEVEL_HIGH>,
75 <ICU_GRP_NSR 47 IRQ_TYPE_LEVEL_HIGH>,
76 <ICU_GRP_NSR 51 IRQ_TYPE_LEVEL_HIGH>,
77 <ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>,
78 <ICU_GRP_NSR 129 IRQ_TYPE_LEVEL_HIGH>;
79 interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
80 "tx-cpu3", "rx-shared", "link";
81 port-id = <0>;
82 gop-port-id = <0>;
83 status = "disabled";
84 };
85
86 cpm_eth1: eth1 {
87 interrupts = <ICU_GRP_NSR 40 IRQ_TYPE_LEVEL_HIGH>,
88 <ICU_GRP_NSR 44 IRQ_TYPE_LEVEL_HIGH>,
89 <ICU_GRP_NSR 48 IRQ_TYPE_LEVEL_HIGH>,
90 <ICU_GRP_NSR 52 IRQ_TYPE_LEVEL_HIGH>,
91 <ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>,
92 <ICU_GRP_NSR 128 IRQ_TYPE_LEVEL_HIGH>;
93 interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
94 "tx-cpu3", "rx-shared", "link";
95 port-id = <1>;
96 gop-port-id = <2>;
97 status = "disabled";
98 };
99
100 cpm_eth2: eth2 {
101 interrupts = <ICU_GRP_NSR 41 IRQ_TYPE_LEVEL_HIGH>,
102 <ICU_GRP_NSR 45 IRQ_TYPE_LEVEL_HIGH>,
103 <ICU_GRP_NSR 49 IRQ_TYPE_LEVEL_HIGH>,
104 <ICU_GRP_NSR 53 IRQ_TYPE_LEVEL_HIGH>,
105 <ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>,
106 <ICU_GRP_NSR 127 IRQ_TYPE_LEVEL_HIGH>;
107 interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
108 "tx-cpu3", "rx-shared", "link";
109 port-id = <2>;
110 gop-port-id = <3>;
111 status = "disabled";
112 };
113 };
114
115 cpm_comphy: phy@120000 {
116 compatible = "marvell,comphy-cp110";
117 reg = <0x120000 0x6000>;
118 marvell,system-controller = <&cpm_syscon0>;
119 #address-cells = <1>;
120 #size-cells = <0>;
121
122 cpm_comphy0: phy@0 {
123 reg = <0>;
124 #phy-cells = <1>;
125 };
126
127 cpm_comphy1: phy@1 {
128 reg = <1>;
129 #phy-cells = <1>;
130 };
131
132 cpm_comphy2: phy@2 {
133 reg = <2>;
134 #phy-cells = <1>;
135 };
136
137 cpm_comphy3: phy@3 {
138 reg = <3>;
139 #phy-cells = <1>;
140 };
141
142 cpm_comphy4: phy@4 {
143 reg = <4>;
144 #phy-cells = <1>;
145 };
146
147 cpm_comphy5: phy@5 {
148 reg = <5>;
149 #phy-cells = <1>;
150 };
151 };
152
153 cpm_mdio: mdio@12a200 {
154 #address-cells = <1>;
155 #size-cells = <0>;
156 compatible = "marvell,orion-mdio";
157 reg = <0x12a200 0x10>;
158 clocks = <&cpm_clk 1 9>, <&cpm_clk 1 5>;
159 status = "disabled";
160 };
161
162 cpm_xmdio: mdio@12a600 {
163 #address-cells = <1>;
164 #size-cells = <0>;
165 compatible = "marvell,xmdio";
166 reg = <0x12a600 0x10>;
167 status = "disabled";
168 };
169
170 cpm_icu: interrupt-controller@1e0000 {
171 compatible = "marvell,cp110-icu";
172 reg = <0x1e0000 0x10>;
173 #interrupt-cells = <3>;
174 interrupt-controller;
175 msi-parent = <&gicp>;
176 };
177
178 cpm_rtc: rtc@284000 {
179 compatible = "marvell,armada-8k-rtc";
180 reg = <0x284000 0x20>, <0x284080 0x24>;
181 reg-names = "rtc", "rtc-soc";
182 interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>;
183 };
184
185 cpm_thermal: thermal@400078 {
186 compatible = "marvell,armada-cp110-thermal";
187 reg = <0x400078 0x4>,
188 <0x400070 0x8>;
189 };
190
191 cpm_syscon0: system-controller@440000 {
192 compatible = "syscon", "simple-mfd";
193 reg = <0x440000 0x2000>;
194
195 cpm_clk: clock {
196 compatible = "marvell,cp110-clock";
197 #clock-cells = <2>;
198 };
199
200 cpm_gpio1: gpio@100 {
201 compatible = "marvell,armada-8k-gpio";
202 offset = <0x100>;
203 ngpios = <32>;
204 gpio-controller;
205 #gpio-cells = <2>;
206 gpio-ranges = <&cpm_pinctrl 0 0 32>;
207 interrupt-controller;
208 interrupts = <ICU_GRP_NSR 86 IRQ_TYPE_LEVEL_HIGH>,
209 <ICU_GRP_NSR 85 IRQ_TYPE_LEVEL_HIGH>,
210 <ICU_GRP_NSR 84 IRQ_TYPE_LEVEL_HIGH>,
211 <ICU_GRP_NSR 83 IRQ_TYPE_LEVEL_HIGH>;
212 status = "disabled";
213 };
214
215 cpm_gpio2: gpio@140 {
216 compatible = "marvell,armada-8k-gpio";
217 offset = <0x140>;
218 ngpios = <31>;
219 gpio-controller;
220 #gpio-cells = <2>;
221 gpio-ranges = <&cpm_pinctrl 0 32 31>;
222 interrupt-controller;
223 interrupts = <ICU_GRP_NSR 82 IRQ_TYPE_LEVEL_HIGH>,
224 <ICU_GRP_NSR 81 IRQ_TYPE_LEVEL_HIGH>,
225 <ICU_GRP_NSR 80 IRQ_TYPE_LEVEL_HIGH>,
226 <ICU_GRP_NSR 79 IRQ_TYPE_LEVEL_HIGH>;
227 status = "disabled";
228 };
229 };
230
231 cpm_usb3_0: usb3@500000 {
232 compatible = "marvell,armada-8k-xhci",
233 "generic-xhci";
234 reg = <0x500000 0x4000>;
235 dma-coherent;
236 interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>;
237 clocks = <&cpm_clk 1 22>;
238 status = "disabled";
239 };
240
241 cpm_usb3_1: usb3@510000 {
242 compatible = "marvell,armada-8k-xhci",
243 "generic-xhci";
244 reg = <0x510000 0x4000>;
245 dma-coherent;
246 interrupts = <ICU_GRP_NSR 105 IRQ_TYPE_LEVEL_HIGH>;
247 clocks = <&cpm_clk 1 23>;
248 status = "disabled";
249 };
250
251 cpm_sata0: sata@540000 {
252 compatible = "marvell,armada-8k-ahci",
253 "generic-ahci";
254 reg = <0x540000 0x30000>;
255 interrupts = <ICU_GRP_NSR 107 IRQ_TYPE_LEVEL_HIGH>;
256 clocks = <&cpm_clk 1 15>;
257 status = "disabled";
258 };
259
260 cpm_xor0: xor@6a0000 {
261 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
262 reg = <0x6a0000 0x1000>,
263 <0x6b0000 0x1000>;
264 dma-coherent;
265 msi-parent = <&gic_v2m0>;
266 clocks = <&cpm_clk 1 8>;
267 };
268
269 cpm_xor1: xor@6c0000 {
270 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
271 reg = <0x6c0000 0x1000>,
272 <0x6d0000 0x1000>;
273 dma-coherent;
274 msi-parent = <&gic_v2m0>;
275 clocks = <&cpm_clk 1 7>;
276 };
277
278 cpm_spi0: spi@700600 {
279 compatible = "marvell,armada-380-spi";
280 reg = <0x700600 0x50>;
281 #address-cells = <0x1>;
282 #size-cells = <0x0>;
283 cell-index = <1>;
284 clocks = <&cpm_clk 1 21>;
285 status = "disabled";
286 };
287
288 cpm_spi1: spi@700680 {
289 compatible = "marvell,armada-380-spi";
290 reg = <0x700680 0x50>;
291 #address-cells = <1>;
292 #size-cells = <0>;
293 cell-index = <2>;
294 clocks = <&cpm_clk 1 21>;
295 status = "disabled";
296 };
297
298 cpm_i2c0: i2c@701000 {
299 compatible = "marvell,mv78230-i2c";
300 reg = <0x701000 0x20>;
301 #address-cells = <1>;
302 #size-cells = <0>;
303 interrupts = <ICU_GRP_NSR 120 IRQ_TYPE_LEVEL_HIGH>;
304 clocks = <&cpm_clk 1 21>;
305 status = "disabled";
306 };
307
308 cpm_i2c1: i2c@701100 {
309 compatible = "marvell,mv78230-i2c";
310 reg = <0x701100 0x20>;
311 #address-cells = <1>;
312 #size-cells = <0>;
313 interrupts = <ICU_GRP_NSR 121 IRQ_TYPE_LEVEL_HIGH>;
314 clocks = <&cpm_clk 1 21>;
315 status = "disabled";
316 };
317
318 cpm_nand: nand@720000 {
319 /*
320 * Due to the limiation of the pin available
321 * this controller is only usable on the CPM
322 * for A7K and on the CPS for A8K.
323 */
324 compatible = "marvell,armada-8k-nand",
325 "marvell,armada370-nand";
326 reg = <0x720000 0x54>;
327 #address-cells = <1>;
328 #size-cells = <1>;
329 interrupts = <ICU_GRP_NSR 115 IRQ_TYPE_LEVEL_HIGH>;
330 clocks = <&cpm_clk 1 2>;
331 marvell,system-controller = <&cpm_syscon0>;
332 status = "disabled";
333 };
334
335 cpm_trng: trng@760000 {
336 compatible = "marvell,armada-8k-rng", "inside-secure,safexcel-eip76";
337 reg = <0x760000 0x7d>;
338 interrupts = <ICU_GRP_NSR 95 IRQ_TYPE_LEVEL_HIGH>;
339 clocks = <&cpm_clk 1 25>;
340 status = "okay";
341 };
342
343 cpm_sdhci0: sdhci@780000 {
344 compatible = "marvell,armada-cp110-sdhci";
345 reg = <0x780000 0x300>;
346 interrupts = <ICU_GRP_NSR 27 IRQ_TYPE_LEVEL_HIGH>;
347 clock-names = "core";
348 clocks = <&cpm_clk 1 4>;
349 dma-coherent;
350 status = "disabled";
351 };
352
353 cpm_crypto: crypto@800000 {
354 compatible = "inside-secure,safexcel-eip197";
355 reg = <0x800000 0x200000>;
356 interrupts = <ICU_GRP_NSR 87 IRQ_TYPE_LEVEL_HIGH>,
357 <ICU_GRP_NSR 88 IRQ_TYPE_LEVEL_HIGH>,
358 <ICU_GRP_NSR 89 IRQ_TYPE_LEVEL_HIGH>,
359 <ICU_GRP_NSR 90 IRQ_TYPE_LEVEL_HIGH>,
360 <ICU_GRP_NSR 91 IRQ_TYPE_LEVEL_HIGH>,
361 <ICU_GRP_NSR 92 IRQ_TYPE_LEVEL_HIGH>;
362 interrupt-names = "mem", "ring0", "ring1",
363 "ring2", "ring3", "eip";
364 clocks = <&cpm_clk 1 26>;
365 dma-coherent;
366 };
367 };
368
369 cpm_pcie0: pcie@f2600000 {
370 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
371 reg = <0 0xf2600000 0 0x10000>,
372 <0 0xf6f00000 0 0x80000>;
373 reg-names = "ctrl", "config";
374 #address-cells = <3>;
375 #size-cells = <2>;
376 #interrupt-cells = <1>;
377 device_type = "pci";
378 dma-coherent;
379 msi-parent = <&gic_v2m0>;
380
381 bus-range = <0 0xff>;
382 ranges =
383 /* downstream I/O */
384 <0x81000000 0 0xf9000000 0 0xf9000000 0 0x10000
385 /* non-prefetchable memory */
386 0x82000000 0 0xf6000000 0 0xf6000000 0 0xf00000>;
387 interrupt-map-mask = <0 0 0 0>;
388 interrupt-map = <0 0 0 0 &cpm_icu ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
389 interrupts = <ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
390 num-lanes = <1>;
391 clocks = <&cpm_clk 1 13>;
392 status = "disabled";
393 };
394
395 cpm_pcie1: pcie@f2620000 {
396 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
397 reg = <0 0xf2620000 0 0x10000>,
398 <0 0xf7f00000 0 0x80000>;
399 reg-names = "ctrl", "config";
400 #address-cells = <3>;
401 #size-cells = <2>;
402 #interrupt-cells = <1>;
403 device_type = "pci";
404 dma-coherent;
405 msi-parent = <&gic_v2m0>;
406
407 bus-range = <0 0xff>;
408 ranges =
409 /* downstream I/O */
410 <0x81000000 0 0xf9010000 0 0xf9010000 0 0x10000
411 /* non-prefetchable memory */
412 0x82000000 0 0xf7000000 0 0xf7000000 0 0xf00000>;
413 interrupt-map-mask = <0 0 0 0>;
414 interrupt-map = <0 0 0 0 &cpm_icu ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
415 interrupts = <ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
416
417 num-lanes = <1>;
418 clocks = <&cpm_clk 1 11>;
419 status = "disabled";
420 };
421
422 cpm_pcie2: pcie@f2640000 {
423 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
424 reg = <0 0xf2640000 0 0x10000>,
425 <0 0xf8f00000 0 0x80000>;
426 reg-names = "ctrl", "config";
427 #address-cells = <3>;
428 #size-cells = <2>;
429 #interrupt-cells = <1>;
430 device_type = "pci";
431 dma-coherent;
432 msi-parent = <&gic_v2m0>;
433
434 bus-range = <0 0xff>;
435 ranges =
436 /* downstream I/O */
437 <0x81000000 0 0xf9020000 0 0xf9020000 0 0x10000
438 /* non-prefetchable memory */
439 0x82000000 0 0xf8000000 0 0xf8000000 0 0xf00000>;
440 interrupt-map-mask = <0 0 0 0>;
441 interrupt-map = <0 0 0 0 &cpm_icu ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
442 interrupts = <ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
443
444 num-lanes = <1>;
445 clocks = <&cpm_clk 1 12>;
446 status = "disabled";
447 };
448 };
449};
diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
deleted file mode 100644
index 6a07c786b788..000000000000
--- a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
+++ /dev/null
@@ -1,448 +0,0 @@
1/*
2 * Copyright (C) 2016 Marvell Technology Group Ltd.
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPLv2 or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43/*
44 * Device Tree file for Marvell Armada CP110 Slave.
45 */
46
47#define ICU_GRP_NSR 0x0
48
49/ {
50 cp110-slave {
51 #address-cells = <2>;
52 #size-cells = <2>;
53 compatible = "simple-bus";
54 interrupt-parent = <&cps_icu>;
55 ranges;
56
57 config-space@f4000000 {
58 #address-cells = <1>;
59 #size-cells = <1>;
60 compatible = "simple-bus";
61 ranges = <0x0 0x0 0xf4000000 0x2000000>;
62
63 cps_ethernet: ethernet@0 {
64 compatible = "marvell,armada-7k-pp22";
65 reg = <0x0 0x100000>, <0x129000 0xb000>;
66 clocks = <&cps_clk 1 3>, <&cps_clk 1 9>, <&cps_clk 1 5>;
67 clock-names = "pp_clk", "gop_clk", "mg_clk";
68 marvell,system-controller = <&cps_syscon0>;
69 status = "disabled";
70 dma-coherent;
71
72 cps_eth0: eth0 {
73 interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>,
74 <ICU_GRP_NSR 43 IRQ_TYPE_LEVEL_HIGH>,
75 <ICU_GRP_NSR 47 IRQ_TYPE_LEVEL_HIGH>,
76 <ICU_GRP_NSR 51 IRQ_TYPE_LEVEL_HIGH>,
77 <ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>,
78 <ICU_GRP_NSR 129 IRQ_TYPE_LEVEL_HIGH>;
79 interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
80 "tx-cpu3", "rx-shared", "link";
81 port-id = <0>;
82 gop-port-id = <0>;
83 status = "disabled";
84 };
85
86 cps_eth1: eth1 {
87 interrupts = <ICU_GRP_NSR 40 IRQ_TYPE_LEVEL_HIGH>,
88 <ICU_GRP_NSR 44 IRQ_TYPE_LEVEL_HIGH>,
89 <ICU_GRP_NSR 48 IRQ_TYPE_LEVEL_HIGH>,
90 <ICU_GRP_NSR 52 IRQ_TYPE_LEVEL_HIGH>,
91 <ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>,
92 <ICU_GRP_NSR 128 IRQ_TYPE_LEVEL_HIGH>;
93 interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
94 "tx-cpu3", "rx-shared", "link";
95 port-id = <1>;
96 gop-port-id = <2>;
97 status = "disabled";
98 };
99
100 cps_eth2: eth2 {
101 interrupts = <ICU_GRP_NSR 41 IRQ_TYPE_LEVEL_HIGH>,
102 <ICU_GRP_NSR 45 IRQ_TYPE_LEVEL_HIGH>,
103 <ICU_GRP_NSR 49 IRQ_TYPE_LEVEL_HIGH>,
104 <ICU_GRP_NSR 53 IRQ_TYPE_LEVEL_HIGH>,
105 <ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>,
106 <ICU_GRP_NSR 127 IRQ_TYPE_LEVEL_HIGH>;
107 interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
108 "tx-cpu3", "rx-shared", "link";
109 port-id = <2>;
110 gop-port-id = <3>;
111 status = "disabled";
112 };
113 };
114
115 cps_comphy: phy@120000 {
116 compatible = "marvell,comphy-cp110";
117 reg = <0x120000 0x6000>;
118 marvell,system-controller = <&cps_syscon0>;
119 #address-cells = <1>;
120 #size-cells = <0>;
121
122 cps_comphy0: phy@0 {
123 reg = <0>;
124 #phy-cells = <1>;
125 };
126
127 cps_comphy1: phy@1 {
128 reg = <1>;
129 #phy-cells = <1>;
130 };
131
132 cps_comphy2: phy@2 {
133 reg = <2>;
134 #phy-cells = <1>;
135 };
136
137 cps_comphy3: phy@3 {
138 reg = <3>;
139 #phy-cells = <1>;
140 };
141
142 cps_comphy4: phy@4 {
143 reg = <4>;
144 #phy-cells = <1>;
145 };
146
147 cps_comphy5: phy@5 {
148 reg = <5>;
149 #phy-cells = <1>;
150 };
151 };
152
153 cps_mdio: mdio@12a200 {
154 #address-cells = <1>;
155 #size-cells = <0>;
156 compatible = "marvell,orion-mdio";
157 reg = <0x12a200 0x10>;
158 clocks = <&cps_clk 1 9>, <&cps_clk 1 5>;
159 status = "disabled";
160 };
161
162 cps_xmdio: mdio@12a600 {
163 #address-cells = <1>;
164 #size-cells = <0>;
165 compatible = "marvell,xmdio";
166 reg = <0x12a600 0x10>;
167 status = "disabled";
168 };
169
170 cps_icu: interrupt-controller@1e0000 {
171 compatible = "marvell,cp110-icu";
172 reg = <0x1e0000 0x10>;
173 #interrupt-cells = <3>;
174 interrupt-controller;
175 msi-parent = <&gicp>;
176 };
177
178 cps_rtc: rtc@284000 {
179 compatible = "marvell,armada-8k-rtc";
180 reg = <0x284000 0x20>, <0x284080 0x24>;
181 reg-names = "rtc", "rtc-soc";
182 interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>;
183 };
184
185 cps_thermal: thermal@400078 {
186 compatible = "marvell,armada-cp110-thermal";
187 reg = <0x400078 0x4>,
188 <0x400070 0x8>;
189 };
190
191 cps_syscon0: system-controller@440000 {
192 compatible = "syscon", "simple-mfd";
193 reg = <0x440000 0x2000>;
194
195 cps_clk: clock {
196 compatible = "marvell,cp110-clock";
197 #clock-cells = <2>;
198 };
199
200 cps_gpio1: gpio@100 {
201 compatible = "marvell,armada-8k-gpio";
202 offset = <0x100>;
203 ngpios = <32>;
204 gpio-controller;
205 #gpio-cells = <2>;
206 gpio-ranges = <&cps_pinctrl 0 0 32>;
207 interrupt-controller;
208 interrupts = <ICU_GRP_NSR 86 IRQ_TYPE_LEVEL_HIGH>,
209 <ICU_GRP_NSR 85 IRQ_TYPE_LEVEL_HIGH>,
210 <ICU_GRP_NSR 84 IRQ_TYPE_LEVEL_HIGH>,
211 <ICU_GRP_NSR 83 IRQ_TYPE_LEVEL_HIGH>;
212 status = "disabled";
213 };
214
215 cps_gpio2: gpio@140 {
216 compatible = "marvell,armada-8k-gpio";
217 offset = <0x140>;
218 ngpios = <31>;
219 gpio-controller;
220 #gpio-cells = <2>;
221 gpio-ranges = <&cps_pinctrl 0 32 31>;
222 interrupt-controller;
223 interrupts = <ICU_GRP_NSR 82 IRQ_TYPE_LEVEL_HIGH>,
224 <ICU_GRP_NSR 81 IRQ_TYPE_LEVEL_HIGH>,
225 <ICU_GRP_NSR 80 IRQ_TYPE_LEVEL_HIGH>,
226 <ICU_GRP_NSR 79 IRQ_TYPE_LEVEL_HIGH>;
227 status = "disabled";
228 };
229
230 };
231
232 cps_usb3_0: usb3@500000 {
233 compatible = "marvell,armada-8k-xhci",
234 "generic-xhci";
235 reg = <0x500000 0x4000>;
236 dma-coherent;
237 interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>;
238 clocks = <&cps_clk 1 22>;
239 status = "disabled";
240 };
241
242 cps_usb3_1: usb3@510000 {
243 compatible = "marvell,armada-8k-xhci",
244 "generic-xhci";
245 reg = <0x510000 0x4000>;
246 dma-coherent;
247 interrupts = <ICU_GRP_NSR 105 IRQ_TYPE_LEVEL_HIGH>;
248 clocks = <&cps_clk 1 23>;
249 status = "disabled";
250 };
251
252 cps_sata0: sata@540000 {
253 compatible = "marvell,armada-8k-ahci",
254 "generic-ahci";
255 reg = <0x540000 0x30000>;
256 interrupts = <ICU_GRP_NSR 107 IRQ_TYPE_LEVEL_HIGH>;
257 clocks = <&cps_clk 1 15>;
258 status = "disabled";
259 };
260
261 cps_xor0: xor@6a0000 {
262 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
263 reg = <0x6a0000 0x1000>,
264 <0x6b0000 0x1000>;
265 dma-coherent;
266 msi-parent = <&gic_v2m0>;
267 clocks = <&cps_clk 1 8>;
268 };
269
270 cps_xor1: xor@6c0000 {
271 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
272 reg = <0x6c0000 0x1000>,
273 <0x6d0000 0x1000>;
274 dma-coherent;
275 msi-parent = <&gic_v2m0>;
276 clocks = <&cps_clk 1 7>;
277 };
278
279 cps_spi0: spi@700600 {
280 compatible = "marvell,armada-380-spi";
281 reg = <0x700600 0x50>;
282 #address-cells = <0x1>;
283 #size-cells = <0x0>;
284 cell-index = <3>;
285 clocks = <&cps_clk 1 21>;
286 status = "disabled";
287 };
288
289 cps_spi1: spi@700680 {
290 compatible = "marvell,armada-380-spi";
291 reg = <0x700680 0x50>;
292 #address-cells = <1>;
293 #size-cells = <0>;
294 cell-index = <4>;
295 clocks = <&cps_clk 1 21>;
296 status = "disabled";
297 };
298
299 cps_i2c0: i2c@701000 {
300 compatible = "marvell,mv78230-i2c";
301 reg = <0x701000 0x20>;
302 #address-cells = <1>;
303 #size-cells = <0>;
304 interrupts = <ICU_GRP_NSR 120 IRQ_TYPE_LEVEL_HIGH>;
305 clocks = <&cps_clk 1 21>;
306 status = "disabled";
307 };
308
309 cps_i2c1: i2c@701100 {
310 compatible = "marvell,mv78230-i2c";
311 reg = <0x701100 0x20>;
312 #address-cells = <1>;
313 #size-cells = <0>;
314 interrupts = <ICU_GRP_NSR 121 IRQ_TYPE_LEVEL_HIGH>;
315 clocks = <&cps_clk 1 21>;
316 status = "disabled";
317 };
318
319 cps_nand: nand@720000 {
320 /*
321 * Due to the limiation of the pin available
322 * this controller is only usable on the CPM
323 * for A7K and on the CPS for A8K.
324 */
325 compatible = "marvell,armada370-nand",
326 "marvell,armada-8k-nand";
327 reg = <0x720000 0x54>;
328 #address-cells = <1>;
329 #size-cells = <1>;
330 interrupts = <ICU_GRP_NSR 115 IRQ_TYPE_LEVEL_HIGH>;
331 clocks = <&cps_clk 1 2>;
332 marvell,system-controller = <&cpm_syscon0>;
333 status = "disabled";
334 };
335
336 cps_trng: trng@760000 {
337 compatible = "marvell,armada-8k-rng", "inside-secure,safexcel-eip76";
338 reg = <0x760000 0x7d>;
339 interrupts = <ICU_GRP_NSR 95 IRQ_TYPE_LEVEL_HIGH>;
340 clocks = <&cps_clk 1 25>;
341 status = "okay";
342 };
343
344 cps_crypto: crypto@800000 {
345 compatible = "inside-secure,safexcel-eip197";
346 reg = <0x800000 0x200000>;
347 interrupts = <ICU_GRP_NSR 87 IRQ_TYPE_LEVEL_HIGH>,
348 <ICU_GRP_NSR 88 IRQ_TYPE_LEVEL_HIGH>,
349 <ICU_GRP_NSR 89 IRQ_TYPE_LEVEL_HIGH>,
350 <ICU_GRP_NSR 90 IRQ_TYPE_LEVEL_HIGH>,
351 <ICU_GRP_NSR 91 IRQ_TYPE_LEVEL_HIGH>,
352 <ICU_GRP_NSR 92 IRQ_TYPE_LEVEL_HIGH>;
353 interrupt-names = "mem", "ring0", "ring1",
354 "ring2", "ring3", "eip";
355 clocks = <&cps_clk 1 26>;
356 dma-coherent;
357 /*
358 * The cryptographic engine found on the cp110
359 * master is enabled by default at the SoC
360 * level. Because it is not possible as of now
361 * to enable two cryptographic engines in
362 * parallel, disable this one by default.
363 */
364 status = "disabled";
365 };
366 };
367
368 cps_pcie0: pcie@f4600000 {
369 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
370 reg = <0 0xf4600000 0 0x10000>,
371 <0 0xfaf00000 0 0x80000>;
372 reg-names = "ctrl", "config";
373 #address-cells = <3>;
374 #size-cells = <2>;
375 #interrupt-cells = <1>;
376 device_type = "pci";
377 dma-coherent;
378 msi-parent = <&gic_v2m0>;
379
380 bus-range = <0 0xff>;
381 ranges =
382 /* downstream I/O */
383 <0x81000000 0 0xfd000000 0 0xfd000000 0 0x10000
384 /* non-prefetchable memory */
385 0x82000000 0 0xfa000000 0 0xfa000000 0 0xf00000>;
386 interrupt-map-mask = <0 0 0 0>;
387 interrupt-map = <0 0 0 0 &cps_icu ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
388 interrupts = <ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
389 num-lanes = <1>;
390 clocks = <&cps_clk 1 13>;
391 status = "disabled";
392 };
393
394 cps_pcie1: pcie@f4620000 {
395 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
396 reg = <0 0xf4620000 0 0x10000>,
397 <0 0xfbf00000 0 0x80000>;
398 reg-names = "ctrl", "config";
399 #address-cells = <3>;
400 #size-cells = <2>;
401 #interrupt-cells = <1>;
402 device_type = "pci";
403 dma-coherent;
404 msi-parent = <&gic_v2m0>;
405
406 bus-range = <0 0xff>;
407 ranges =
408 /* downstream I/O */
409 <0x81000000 0 0xfd010000 0 0xfd010000 0 0x10000
410 /* non-prefetchable memory */
411 0x82000000 0 0xfb000000 0 0xfb000000 0 0xf00000>;
412 interrupt-map-mask = <0 0 0 0>;
413 interrupt-map = <0 0 0 0 &cps_icu ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
414 interrupts = <ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
415
416 num-lanes = <1>;
417 clocks = <&cps_clk 1 11>;
418 status = "disabled";
419 };
420
421 cps_pcie2: pcie@f4640000 {
422 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
423 reg = <0 0xf4640000 0 0x10000>,
424 <0 0xfcf00000 0 0x80000>;
425 reg-names = "ctrl", "config";
426 #address-cells = <3>;
427 #size-cells = <2>;
428 #interrupt-cells = <1>;
429 device_type = "pci";
430 dma-coherent;
431 msi-parent = <&gic_v2m0>;
432
433 bus-range = <0 0xff>;
434 ranges =
435 /* downstream I/O */
436 <0x81000000 0 0xfd020000 0 0xfd020000 0 0x10000
437 /* non-prefetchable memory */
438 0x82000000 0 0xfc000000 0 0xfc000000 0 0xf00000>;
439 interrupt-map-mask = <0 0 0 0>;
440 interrupt-map = <0 0 0 0 &cps_icu ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
441 interrupts = <ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
442
443 num-lanes = <1>;
444 clocks = <&cps_clk 1 12>;
445 status = "disabled";
446 };
447 };
448};
diff --git a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
new file mode 100644
index 000000000000..a8af4136dbe7
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
@@ -0,0 +1,424 @@
1// SPDX-License-Identifier: (GPL-2.0+ OR X11)
2/*
3 * Copyright (C) 2016 Marvell Technology Group Ltd.
4 */
5
6/*
7 * Device Tree file for Marvell Armada CP110.
8 */
9
10#include <dt-bindings/interrupt-controller/mvebu-icu.h>
11
12#include "armada-common.dtsi"
13
14#define CP110_PCIEx_IO_BASE(iface) (CP110_PCIE_IO_BASE + (iface * 0x10000))
15#define CP110_PCIEx_MEM_BASE(iface) (CP110_PCIE_MEM_BASE + (iface * 0x1000000))
16#define CP110_PCIEx_CONF_BASE(iface) (CP110_PCIEx_MEM_BASE(iface) + 0xf00000)
17
18/ {
19 /*
20 * The contents of the node are defined below, in order to
21 * save one indentation level
22 */
23 CP110_NAME: CP110_NAME { };
24};
25
26&CP110_NAME {
27 #address-cells = <2>;
28 #size-cells = <2>;
29 compatible = "simple-bus";
30 interrupt-parent = <&CP110_LABEL(icu)>;
31 ranges;
32
33 config-space@CP110_BASE {
34 #address-cells = <1>;
35 #size-cells = <1>;
36 compatible = "simple-bus";
37 ranges = <0x0 0x0 ADDRESSIFY(CP110_BASE) 0x2000000>;
38
39 CP110_LABEL(ethernet): ethernet@0 {
40 compatible = "marvell,armada-7k-pp22";
41 reg = <0x0 0x100000>, <0x129000 0xb000>;
42 clocks = <&CP110_LABEL(clk) 1 3>, <&CP110_LABEL(clk) 1 9>,
43 <&CP110_LABEL(clk) 1 5>, <&CP110_LABEL(clk) 1 18>;
44 clock-names = "pp_clk", "gop_clk",
45 "mg_clk", "axi_clk";
46 marvell,system-controller = <&CP110_LABEL(syscon0)>;
47 status = "disabled";
48 dma-coherent;
49
50 CP110_LABEL(eth0): eth0 {
51 interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>,
52 <ICU_GRP_NSR 43 IRQ_TYPE_LEVEL_HIGH>,
53 <ICU_GRP_NSR 47 IRQ_TYPE_LEVEL_HIGH>,
54 <ICU_GRP_NSR 51 IRQ_TYPE_LEVEL_HIGH>,
55 <ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>,
56 <ICU_GRP_NSR 129 IRQ_TYPE_LEVEL_HIGH>;
57 interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
58 "tx-cpu3", "rx-shared", "link";
59 port-id = <0>;
60 gop-port-id = <0>;
61 status = "disabled";
62 };
63
64 CP110_LABEL(eth1): eth1 {
65 interrupts = <ICU_GRP_NSR 40 IRQ_TYPE_LEVEL_HIGH>,
66 <ICU_GRP_NSR 44 IRQ_TYPE_LEVEL_HIGH>,
67 <ICU_GRP_NSR 48 IRQ_TYPE_LEVEL_HIGH>,
68 <ICU_GRP_NSR 52 IRQ_TYPE_LEVEL_HIGH>,
69 <ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>,
70 <ICU_GRP_NSR 128 IRQ_TYPE_LEVEL_HIGH>;
71 interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
72 "tx-cpu3", "rx-shared", "link";
73 port-id = <1>;
74 gop-port-id = <2>;
75 status = "disabled";
76 };
77
78 CP110_LABEL(eth2): eth2 {
79 interrupts = <ICU_GRP_NSR 41 IRQ_TYPE_LEVEL_HIGH>,
80 <ICU_GRP_NSR 45 IRQ_TYPE_LEVEL_HIGH>,
81 <ICU_GRP_NSR 49 IRQ_TYPE_LEVEL_HIGH>,
82 <ICU_GRP_NSR 53 IRQ_TYPE_LEVEL_HIGH>,
83 <ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>,
84 <ICU_GRP_NSR 127 IRQ_TYPE_LEVEL_HIGH>;
85 interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
86 "tx-cpu3", "rx-shared", "link";
87 port-id = <2>;
88 gop-port-id = <3>;
89 status = "disabled";
90 };
91 };
92
93 CP110_LABEL(comphy): phy@120000 {
94 compatible = "marvell,comphy-cp110";
95 reg = <0x120000 0x6000>;
96 marvell,system-controller = <&CP110_LABEL(syscon0)>;
97 #address-cells = <1>;
98 #size-cells = <0>;
99
100 CP110_LABEL(comphy0): phy@0 {
101 reg = <0>;
102 #phy-cells = <1>;
103 };
104
105 CP110_LABEL(comphy1): phy@1 {
106 reg = <1>;
107 #phy-cells = <1>;
108 };
109
110 CP110_LABEL(comphy2): phy@2 {
111 reg = <2>;
112 #phy-cells = <1>;
113 };
114
115 CP110_LABEL(comphy3): phy@3 {
116 reg = <3>;
117 #phy-cells = <1>;
118 };
119
120 CP110_LABEL(comphy4): phy@4 {
121 reg = <4>;
122 #phy-cells = <1>;
123 };
124
125 CP110_LABEL(comphy5): phy@5 {
126 reg = <5>;
127 #phy-cells = <1>;
128 };
129 };
130
131 CP110_LABEL(mdio): mdio@12a200 {
132 #address-cells = <1>;
133 #size-cells = <0>;
134 compatible = "marvell,orion-mdio";
135 reg = <0x12a200 0x10>;
136 clocks = <&CP110_LABEL(clk) 1 9>, <&CP110_LABEL(clk) 1 5>,
137 <&CP110_LABEL(clk) 1 6>, <&CP110_LABEL(clk) 1 18>;
138 status = "disabled";
139 };
140
141 CP110_LABEL(xmdio): mdio@12a600 {
142 #address-cells = <1>;
143 #size-cells = <0>;
144 compatible = "marvell,xmdio";
145 reg = <0x12a600 0x10>;
146 status = "disabled";
147 };
148
149 CP110_LABEL(icu): interrupt-controller@1e0000 {
150 compatible = "marvell,cp110-icu";
151 reg = <0x1e0000 0x10>;
152 #interrupt-cells = <3>;
153 interrupt-controller;
154 msi-parent = <&gicp>;
155 };
156
157 CP110_LABEL(rtc): rtc@284000 {
158 compatible = "marvell,armada-8k-rtc";
159 reg = <0x284000 0x20>, <0x284080 0x24>;
160 reg-names = "rtc", "rtc-soc";
161 interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>;
162 };
163
164 CP110_LABEL(thermal): thermal@400078 {
165 compatible = "marvell,armada-cp110-thermal";
166 reg = <0x400078 0x4>,
167 <0x400070 0x8>;
168 };
169
170 CP110_LABEL(syscon0): system-controller@440000 {
171 compatible = "syscon", "simple-mfd";
172 reg = <0x440000 0x2000>;
173
174 CP110_LABEL(clk): clock {
175 compatible = "marvell,cp110-clock";
176 #clock-cells = <2>;
177 };
178
179 CP110_LABEL(gpio1): gpio@100 {
180 compatible = "marvell,armada-8k-gpio";
181 offset = <0x100>;
182 ngpios = <32>;
183 gpio-controller;
184 #gpio-cells = <2>;
185 gpio-ranges = <&CP110_LABEL(pinctrl) 0 0 32>;
186 interrupt-controller;
187 interrupts = <ICU_GRP_NSR 86 IRQ_TYPE_LEVEL_HIGH>,
188 <ICU_GRP_NSR 85 IRQ_TYPE_LEVEL_HIGH>,
189 <ICU_GRP_NSR 84 IRQ_TYPE_LEVEL_HIGH>,
190 <ICU_GRP_NSR 83 IRQ_TYPE_LEVEL_HIGH>;
191 status = "disabled";
192 };
193
194 CP110_LABEL(gpio2): gpio@140 {
195 compatible = "marvell,armada-8k-gpio";
196 offset = <0x140>;
197 ngpios = <31>;
198 gpio-controller;
199 #gpio-cells = <2>;
200 gpio-ranges = <&CP110_LABEL(pinctrl) 0 32 31>;
201 interrupt-controller;
202 interrupts = <ICU_GRP_NSR 82 IRQ_TYPE_LEVEL_HIGH>,
203 <ICU_GRP_NSR 81 IRQ_TYPE_LEVEL_HIGH>,
204 <ICU_GRP_NSR 80 IRQ_TYPE_LEVEL_HIGH>,
205 <ICU_GRP_NSR 79 IRQ_TYPE_LEVEL_HIGH>;
206 status = "disabled";
207 };
208 };
209
210 CP110_LABEL(usb3_0): usb3@500000 {
211 compatible = "marvell,armada-8k-xhci",
212 "generic-xhci";
213 reg = <0x500000 0x4000>;
214 dma-coherent;
215 interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>;
216 clocks = <&CP110_LABEL(clk) 1 22>;
217 status = "disabled";
218 };
219
220 CP110_LABEL(usb3_1): usb3@510000 {
221 compatible = "marvell,armada-8k-xhci",
222 "generic-xhci";
223 reg = <0x510000 0x4000>;
224 dma-coherent;
225 interrupts = <ICU_GRP_NSR 105 IRQ_TYPE_LEVEL_HIGH>;
226 clocks = <&CP110_LABEL(clk) 1 23>;
227 status = "disabled";
228 };
229
230 CP110_LABEL(sata0): sata@540000 {
231 compatible = "marvell,armada-8k-ahci",
232 "generic-ahci";
233 reg = <0x540000 0x30000>;
234 interrupts = <ICU_GRP_NSR 107 IRQ_TYPE_LEVEL_HIGH>;
235 clocks = <&CP110_LABEL(clk) 1 15>;
236 status = "disabled";
237 };
238
239 CP110_LABEL(xor0): xor@6a0000 {
240 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
241 reg = <0x6a0000 0x1000>, <0x6b0000 0x1000>;
242 dma-coherent;
243 msi-parent = <&gic_v2m0>;
244 clocks = <&CP110_LABEL(clk) 1 8>;
245 };
246
247 CP110_LABEL(xor1): xor@6c0000 {
248 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
249 reg = <0x6c0000 0x1000>, <0x6d0000 0x1000>;
250 dma-coherent;
251 msi-parent = <&gic_v2m0>;
252 clocks = <&CP110_LABEL(clk) 1 7>;
253 };
254
255 CP110_LABEL(spi0): spi@700600 {
256 compatible = "marvell,armada-380-spi";
257 reg = <0x700600 0x50>;
258 #address-cells = <0x1>;
259 #size-cells = <0x0>;
260 clocks = <&CP110_LABEL(clk) 1 21>;
261 status = "disabled";
262 };
263
264 CP110_LABEL(spi1): spi@700680 {
265 compatible = "marvell,armada-380-spi";
266 reg = <0x700680 0x50>;
267 #address-cells = <1>;
268 #size-cells = <0>;
269 clocks = <&CP110_LABEL(clk) 1 21>;
270 status = "disabled";
271 };
272
273 CP110_LABEL(i2c0): i2c@701000 {
274 compatible = "marvell,mv78230-i2c";
275 reg = <0x701000 0x20>;
276 #address-cells = <1>;
277 #size-cells = <0>;
278 interrupts = <ICU_GRP_NSR 120 IRQ_TYPE_LEVEL_HIGH>;
279 clocks = <&CP110_LABEL(clk) 1 21>;
280 status = "disabled";
281 };
282
283 CP110_LABEL(i2c1): i2c@701100 {
284 compatible = "marvell,mv78230-i2c";
285 reg = <0x701100 0x20>;
286 #address-cells = <1>;
287 #size-cells = <0>;
288 interrupts = <ICU_GRP_NSR 121 IRQ_TYPE_LEVEL_HIGH>;
289 clocks = <&CP110_LABEL(clk) 1 21>;
290 status = "disabled";
291 };
292
293 CP110_LABEL(nand): nand@720000 {
294 /*
295 * Due to the limitation of the pins available
296 * this controller is only usable on the CPM
297 * for A7K and on the CPS for A8K.
298 */
299 compatible = "marvell,armada-8k-nand",
300 "marvell,armada370-nand";
301 reg = <0x720000 0x54>;
302 #address-cells = <1>;
303 #size-cells = <1>;
304 interrupts = <ICU_GRP_NSR 115 IRQ_TYPE_LEVEL_HIGH>;
305 clocks = <&CP110_LABEL(clk) 1 2>;
306 marvell,system-controller = <&CP110_LABEL(syscon0)>;
307 status = "disabled";
308 };
309
310 CP110_LABEL(trng): trng@760000 {
311 compatible = "marvell,armada-8k-rng",
312 "inside-secure,safexcel-eip76";
313 reg = <0x760000 0x7d>;
314 interrupts = <ICU_GRP_NSR 95 IRQ_TYPE_LEVEL_HIGH>;
315 clocks = <&CP110_LABEL(clk) 1 25>;
316 status = "okay";
317 };
318
319 CP110_LABEL(sdhci0): sdhci@780000 {
320 compatible = "marvell,armada-cp110-sdhci";
321 reg = <0x780000 0x300>;
322 interrupts = <ICU_GRP_NSR 27 IRQ_TYPE_LEVEL_HIGH>;
323 clock-names = "core", "axi";
324 clocks = <&CP110_LABEL(clk) 1 4>, <&CP110_LABEL(clk) 1 18>;
325 dma-coherent;
326 status = "disabled";
327 };
328
329 CP110_LABEL(crypto): crypto@800000 {
330 compatible = "inside-secure,safexcel-eip197";
331 reg = <0x800000 0x200000>;
332 interrupts = <ICU_GRP_NSR 87 IRQ_TYPE_LEVEL_HIGH>,
333 <ICU_GRP_NSR 88 IRQ_TYPE_LEVEL_HIGH>,
334 <ICU_GRP_NSR 89 IRQ_TYPE_LEVEL_HIGH>,
335 <ICU_GRP_NSR 90 IRQ_TYPE_LEVEL_HIGH>,
336 <ICU_GRP_NSR 91 IRQ_TYPE_LEVEL_HIGH>,
337 <ICU_GRP_NSR 92 IRQ_TYPE_LEVEL_HIGH>;
338 interrupt-names = "mem", "ring0", "ring1",
339 "ring2", "ring3", "eip";
340 clocks = <&CP110_LABEL(clk) 1 26>;
341 dma-coherent;
342 };
343 };
344
345 CP110_LABEL(pcie0): pcie@CP110_PCIE0_BASE {
346 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
347 reg = <0 ADDRESSIFY(CP110_PCIE0_BASE) 0 0x10000>,
348 <0 CP110_PCIEx_CONF_BASE(0) 0 0x80000>;
349 reg-names = "ctrl", "config";
350 #address-cells = <3>;
351 #size-cells = <2>;
352 #interrupt-cells = <1>;
353 device_type = "pci";
354 dma-coherent;
355 msi-parent = <&gic_v2m0>;
356
357 bus-range = <0 0xff>;
358 ranges =
359 /* downstream I/O */
360 <0x81000000 0 CP110_PCIEx_IO_BASE(0) 0 CP110_PCIEx_IO_BASE(0) 0 0x10000
361 /* non-prefetchable memory */
362 0x82000000 0 CP110_PCIEx_MEM_BASE(0) 0 CP110_PCIEx_MEM_BASE(0) 0 0xf00000>;
363 interrupt-map-mask = <0 0 0 0>;
364 interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
365 interrupts = <ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
366 num-lanes = <1>;
367 clocks = <&CP110_LABEL(clk) 1 13>;
368 status = "disabled";
369 };
370
371 CP110_LABEL(pcie1): pcie@CP110_PCIE1_BASE {
372 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
373 reg = <0 ADDRESSIFY(CP110_PCIE1_BASE) 0 0x10000>,
374 <0 CP110_PCIEx_CONF_BASE(1) 0 0x80000>;
375 reg-names = "ctrl", "config";
376 #address-cells = <3>;
377 #size-cells = <2>;
378 #interrupt-cells = <1>;
379 device_type = "pci";
380 dma-coherent;
381 msi-parent = <&gic_v2m0>;
382
383 bus-range = <0 0xff>;
384 ranges =
385 /* downstream I/O */
386 <0x81000000 0 CP110_PCIEx_IO_BASE(1) 0 CP110_PCIEx_IO_BASE(1) 0 0x10000
387 /* non-prefetchable memory */
388 0x82000000 0 CP110_PCIEx_MEM_BASE(1) 0 CP110_PCIEx_MEM_BASE(1) 0 0xf00000>;
389 interrupt-map-mask = <0 0 0 0>;
390 interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
391 interrupts = <ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
392
393 num-lanes = <1>;
394 clocks = <&CP110_LABEL(clk) 1 11>;
395 status = "disabled";
396 };
397
398 CP110_LABEL(pcie2): pcie@CP110_PCIE2_BASE {
399 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
400 reg = <0 ADDRESSIFY(CP110_PCIE2_BASE) 0 0x10000>,
401 <0 CP110_PCIEx_CONF_BASE(2) 0 0x80000>;
402 reg-names = "ctrl", "config";
403 #address-cells = <3>;
404 #size-cells = <2>;
405 #interrupt-cells = <1>;
406 device_type = "pci";
407 dma-coherent;
408 msi-parent = <&gic_v2m0>;
409
410 bus-range = <0 0xff>;
411 ranges =
412 /* downstream I/O */
413 <0x81000000 0 CP110_PCIEx_IO_BASE(2) 0 CP110_PCIEx_IO_BASE(2) 0 0x10000
414 /* non-prefetchable memory */
415 0x82000000 0 CP110_PCIEx_MEM_BASE(2) 0 CP110_PCIEx_MEM_BASE(2) 0 0xf00000>;
416 interrupt-map-mask = <0 0 0 0>;
417 interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
418 interrupts = <ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
419
420 num-lanes = <1>;
421 clocks = <&CP110_LABEL(clk) 1 12>;
422 status = "disabled";
423 };
424};
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-24 22:33:39 -0400