aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorAlex Deucher <alexander.deucher@amd.com>2013-07-31 18:32:33 -0400
committerAlex Deucher <alexander.deucher@amd.com>2013-08-07 17:37:10 -0400
commitb841ce7b41ffbecf84285b381b3ac23f05256d31 (patch)
tree0649a5c0c58f91c824c88789e1e1ee3cad383e08
parentfda837241f3680e5dc554c26e178c2deec7a039c (diff)
drm/radeon/dpm: fix spread spectrum setup (v2)
Need to check for engine and memory clock ss separately and only enable dynamic ss if either of them are found. This should fix systems which have a ss table, but do not have entries for engine or memory. On those systems we may enable dynamic spread spectrum without enabling it on the engine or memory clocks which can lead to a hang in some cases. fixes some systems reported here: https://bugs.freedesktop.org/show_bug.cgi?id=66963 v2: fix typo Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r--drivers/gpu/drm/radeon/btc_dpm.c14
-rw-r--r--drivers/gpu/drm/radeon/cypress_dpm.c14
-rw-r--r--drivers/gpu/drm/radeon/ni_dpm.c14
-rw-r--r--drivers/gpu/drm/radeon/rv6xx_dpm.c19
-rw-r--r--drivers/gpu/drm/radeon/rv770_dpm.c30
-rw-r--r--drivers/gpu/drm/radeon/rv770_dpm.h1
-rw-r--r--drivers/gpu/drm/radeon/si_dpm.c14
7 files changed, 30 insertions, 76 deletions
diff --git a/drivers/gpu/drm/radeon/btc_dpm.c b/drivers/gpu/drm/radeon/btc_dpm.c
index e7c128b48112..9953e1fbc46d 100644
--- a/drivers/gpu/drm/radeon/btc_dpm.c
+++ b/drivers/gpu/drm/radeon/btc_dpm.c
@@ -2548,9 +2548,6 @@ int btc_dpm_init(struct radeon_device *rdev)
2548{ 2548{
2549 struct rv7xx_power_info *pi; 2549 struct rv7xx_power_info *pi;
2550 struct evergreen_power_info *eg_pi; 2550 struct evergreen_power_info *eg_pi;
2551 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
2552 u16 data_offset, size;
2553 u8 frev, crev;
2554 struct atom_clock_dividers dividers; 2551 struct atom_clock_dividers dividers;
2555 int ret; 2552 int ret;
2556 2553
@@ -2633,16 +2630,7 @@ int btc_dpm_init(struct radeon_device *rdev)
2633 eg_pi->vddci_control = 2630 eg_pi->vddci_control =
2634 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 0); 2631 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 0);
2635 2632
2636 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 2633 rv770_get_engine_memory_ss(rdev);
2637 &frev, &crev, &data_offset)) {
2638 pi->sclk_ss = true;
2639 pi->mclk_ss = true;
2640 pi->dynamic_ss = true;
2641 } else {
2642 pi->sclk_ss = false;
2643 pi->mclk_ss = false;
2644 pi->dynamic_ss = true;
2645 }
2646 2634
2647 pi->asi = RV770_ASI_DFLT; 2635 pi->asi = RV770_ASI_DFLT;
2648 pi->pasi = CYPRESS_HASI_DFLT; 2636 pi->pasi = CYPRESS_HASI_DFLT;
diff --git a/drivers/gpu/drm/radeon/cypress_dpm.c b/drivers/gpu/drm/radeon/cypress_dpm.c
index c840e079be5b..7e5d0b570a30 100644
--- a/drivers/gpu/drm/radeon/cypress_dpm.c
+++ b/drivers/gpu/drm/radeon/cypress_dpm.c
@@ -2038,9 +2038,6 @@ int cypress_dpm_init(struct radeon_device *rdev)
2038{ 2038{
2039 struct rv7xx_power_info *pi; 2039 struct rv7xx_power_info *pi;
2040 struct evergreen_power_info *eg_pi; 2040 struct evergreen_power_info *eg_pi;
2041 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
2042 uint16_t data_offset, size;
2043 uint8_t frev, crev;
2044 struct atom_clock_dividers dividers; 2041 struct atom_clock_dividers dividers;
2045 int ret; 2042 int ret;
2046 2043
@@ -2092,16 +2089,7 @@ int cypress_dpm_init(struct radeon_device *rdev)
2092 eg_pi->vddci_control = 2089 eg_pi->vddci_control =
2093 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 0); 2090 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 0);
2094 2091
2095 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 2092 rv770_get_engine_memory_ss(rdev);
2096 &frev, &crev, &data_offset)) {
2097 pi->sclk_ss = true;
2098 pi->mclk_ss = true;
2099 pi->dynamic_ss = true;
2100 } else {
2101 pi->sclk_ss = false;
2102 pi->mclk_ss = false;
2103 pi->dynamic_ss = true;
2104 }
2105 2093
2106 pi->asi = RV770_ASI_DFLT; 2094 pi->asi = RV770_ASI_DFLT;
2107 pi->pasi = CYPRESS_HASI_DFLT; 2095 pi->pasi = CYPRESS_HASI_DFLT;
diff --git a/drivers/gpu/drm/radeon/ni_dpm.c b/drivers/gpu/drm/radeon/ni_dpm.c
index c560318d3f19..f0f5f748938a 100644
--- a/drivers/gpu/drm/radeon/ni_dpm.c
+++ b/drivers/gpu/drm/radeon/ni_dpm.c
@@ -4067,9 +4067,6 @@ int ni_dpm_init(struct radeon_device *rdev)
4067 struct rv7xx_power_info *pi; 4067 struct rv7xx_power_info *pi;
4068 struct evergreen_power_info *eg_pi; 4068 struct evergreen_power_info *eg_pi;
4069 struct ni_power_info *ni_pi; 4069 struct ni_power_info *ni_pi;
4070 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
4071 u16 data_offset, size;
4072 u8 frev, crev;
4073 struct atom_clock_dividers dividers; 4070 struct atom_clock_dividers dividers;
4074 int ret; 4071 int ret;
4075 4072
@@ -4162,16 +4159,7 @@ int ni_dpm_init(struct radeon_device *rdev)
4162 eg_pi->vddci_control = 4159 eg_pi->vddci_control =
4163 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 0); 4160 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 0);
4164 4161
4165 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 4162 rv770_get_engine_memory_ss(rdev);
4166 &frev, &crev, &data_offset)) {
4167 pi->sclk_ss = true;
4168 pi->mclk_ss = true;
4169 pi->dynamic_ss = true;
4170 } else {
4171 pi->sclk_ss = false;
4172 pi->mclk_ss = false;
4173 pi->dynamic_ss = true;
4174 }
4175 4163
4176 pi->asi = RV770_ASI_DFLT; 4164 pi->asi = RV770_ASI_DFLT;
4177 pi->pasi = CYPRESS_HASI_DFLT; 4165 pi->pasi = CYPRESS_HASI_DFLT;
diff --git a/drivers/gpu/drm/radeon/rv6xx_dpm.c b/drivers/gpu/drm/radeon/rv6xx_dpm.c
index 363018c60412..e44a90a359a5 100644
--- a/drivers/gpu/drm/radeon/rv6xx_dpm.c
+++ b/drivers/gpu/drm/radeon/rv6xx_dpm.c
@@ -1944,9 +1944,7 @@ static int rv6xx_parse_power_table(struct radeon_device *rdev)
1944 1944
1945int rv6xx_dpm_init(struct radeon_device *rdev) 1945int rv6xx_dpm_init(struct radeon_device *rdev)
1946{ 1946{
1947 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info); 1947 struct radeon_atom_ss ss;
1948 uint16_t data_offset, size;
1949 uint8_t frev, crev;
1950 struct atom_clock_dividers dividers; 1948 struct atom_clock_dividers dividers;
1951 struct rv6xx_power_info *pi; 1949 struct rv6xx_power_info *pi;
1952 int ret; 1950 int ret;
@@ -1989,16 +1987,15 @@ int rv6xx_dpm_init(struct radeon_device *rdev)
1989 1987
1990 pi->gfx_clock_gating = true; 1988 pi->gfx_clock_gating = true;
1991 1989
1992 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 1990 pi->sclk_ss = radeon_atombios_get_asic_ss_info(rdev, &ss,
1993 &frev, &crev, &data_offset)) { 1991 ASIC_INTERNAL_ENGINE_SS, 0);
1994 pi->sclk_ss = true; 1992 pi->mclk_ss = radeon_atombios_get_asic_ss_info(rdev, &ss,
1995 pi->mclk_ss = true; 1993 ASIC_INTERNAL_MEMORY_SS, 0);
1994
1995 if (pi->sclk_ss || pi->mclk_ss)
1996 pi->dynamic_ss = true; 1996 pi->dynamic_ss = true;
1997 } else { 1997 else
1998 pi->sclk_ss = false;
1999 pi->mclk_ss = false;
2000 pi->dynamic_ss = false; 1998 pi->dynamic_ss = false;
2001 }
2002 1999
2003 pi->dynamic_pcie_gen2 = true; 2000 pi->dynamic_pcie_gen2 = true;
2004 2001
diff --git a/drivers/gpu/drm/radeon/rv770_dpm.c b/drivers/gpu/drm/radeon/rv770_dpm.c
index 2ae54bba14d4..094c67a29d0d 100644
--- a/drivers/gpu/drm/radeon/rv770_dpm.c
+++ b/drivers/gpu/drm/radeon/rv770_dpm.c
@@ -2319,12 +2319,25 @@ int rv7xx_parse_power_table(struct radeon_device *rdev)
2319 return 0; 2319 return 0;
2320} 2320}
2321 2321
2322void rv770_get_engine_memory_ss(struct radeon_device *rdev)
2323{
2324 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2325 struct radeon_atom_ss ss;
2326
2327 pi->sclk_ss = radeon_atombios_get_asic_ss_info(rdev, &ss,
2328 ASIC_INTERNAL_ENGINE_SS, 0);
2329 pi->mclk_ss = radeon_atombios_get_asic_ss_info(rdev, &ss,
2330 ASIC_INTERNAL_MEMORY_SS, 0);
2331
2332 if (pi->sclk_ss || pi->mclk_ss)
2333 pi->dynamic_ss = true;
2334 else
2335 pi->dynamic_ss = false;
2336}
2337
2322int rv770_dpm_init(struct radeon_device *rdev) 2338int rv770_dpm_init(struct radeon_device *rdev)
2323{ 2339{
2324 struct rv7xx_power_info *pi; 2340 struct rv7xx_power_info *pi;
2325 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
2326 uint16_t data_offset, size;
2327 uint8_t frev, crev;
2328 struct atom_clock_dividers dividers; 2341 struct atom_clock_dividers dividers;
2329 int ret; 2342 int ret;
2330 2343
@@ -2369,16 +2382,7 @@ int rv770_dpm_init(struct radeon_device *rdev)
2369 pi->mvdd_control = 2382 pi->mvdd_control =
2370 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC, 0); 2383 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC, 0);
2371 2384
2372 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 2385 rv770_get_engine_memory_ss(rdev);
2373 &frev, &crev, &data_offset)) {
2374 pi->sclk_ss = true;
2375 pi->mclk_ss = true;
2376 pi->dynamic_ss = true;
2377 } else {
2378 pi->sclk_ss = false;
2379 pi->mclk_ss = false;
2380 pi->dynamic_ss = false;
2381 }
2382 2386
2383 pi->asi = RV770_ASI_DFLT; 2387 pi->asi = RV770_ASI_DFLT;
2384 pi->pasi = RV770_HASI_DFLT; 2388 pi->pasi = RV770_HASI_DFLT;
diff --git a/drivers/gpu/drm/radeon/rv770_dpm.h b/drivers/gpu/drm/radeon/rv770_dpm.h
index 96b1b2a62a8a..9244effc6b59 100644
--- a/drivers/gpu/drm/radeon/rv770_dpm.h
+++ b/drivers/gpu/drm/radeon/rv770_dpm.h
@@ -275,6 +275,7 @@ void rv770_set_uvd_clock_before_set_eng_clock(struct radeon_device *rdev,
275void rv770_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev, 275void rv770_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev,
276 struct radeon_ps *new_ps, 276 struct radeon_ps *new_ps,
277 struct radeon_ps *old_ps); 277 struct radeon_ps *old_ps);
278void rv770_get_engine_memory_ss(struct radeon_device *rdev);
278 279
279/* smc */ 280/* smc */
280int rv770_read_smc_soft_register(struct radeon_device *rdev, 281int rv770_read_smc_soft_register(struct radeon_device *rdev,
diff --git a/drivers/gpu/drm/radeon/si_dpm.c b/drivers/gpu/drm/radeon/si_dpm.c
index dc06e433048a..71a993f1c8c4 100644
--- a/drivers/gpu/drm/radeon/si_dpm.c
+++ b/drivers/gpu/drm/radeon/si_dpm.c
@@ -6253,9 +6253,6 @@ int si_dpm_init(struct radeon_device *rdev)
6253 struct evergreen_power_info *eg_pi; 6253 struct evergreen_power_info *eg_pi;
6254 struct ni_power_info *ni_pi; 6254 struct ni_power_info *ni_pi;
6255 struct si_power_info *si_pi; 6255 struct si_power_info *si_pi;
6256 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
6257 u16 data_offset, size;
6258 u8 frev, crev;
6259 struct atom_clock_dividers dividers; 6256 struct atom_clock_dividers dividers;
6260 int ret; 6257 int ret;
6261 u32 mask; 6258 u32 mask;
@@ -6346,16 +6343,7 @@ int si_dpm_init(struct radeon_device *rdev)
6346 si_pi->vddc_phase_shed_control = 6343 si_pi->vddc_phase_shed_control =
6347 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, VOLTAGE_OBJ_PHASE_LUT); 6344 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, VOLTAGE_OBJ_PHASE_LUT);
6348 6345
6349 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 6346 rv770_get_engine_memory_ss(rdev);
6350 &frev, &crev, &data_offset)) {
6351 pi->sclk_ss = true;
6352 pi->mclk_ss = true;
6353 pi->dynamic_ss = true;
6354 } else {
6355 pi->sclk_ss = false;
6356 pi->mclk_ss = false;
6357 pi->dynamic_ss = true;
6358 }
6359 6347
6360 pi->asi = RV770_ASI_DFLT; 6348 pi->asi = RV770_ASI_DFLT;
6361 pi->pasi = CYPRESS_HASI_DFLT; 6349 pi->pasi = CYPRESS_HASI_DFLT;