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path: root/drivers/gpu/drm/radeon/si_dpm.c
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Diffstat (limited to 'drivers/gpu/drm/radeon/si_dpm.c')
-rw-r--r--drivers/gpu/drm/radeon/si_dpm.c14
1 files changed, 1 insertions, 13 deletions
diff --git a/drivers/gpu/drm/radeon/si_dpm.c b/drivers/gpu/drm/radeon/si_dpm.c
index dc06e433048a..71a993f1c8c4 100644
--- a/drivers/gpu/drm/radeon/si_dpm.c
+++ b/drivers/gpu/drm/radeon/si_dpm.c
@@ -6253,9 +6253,6 @@ int si_dpm_init(struct radeon_device *rdev)
6253 struct evergreen_power_info *eg_pi; 6253 struct evergreen_power_info *eg_pi;
6254 struct ni_power_info *ni_pi; 6254 struct ni_power_info *ni_pi;
6255 struct si_power_info *si_pi; 6255 struct si_power_info *si_pi;
6256 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
6257 u16 data_offset, size;
6258 u8 frev, crev;
6259 struct atom_clock_dividers dividers; 6256 struct atom_clock_dividers dividers;
6260 int ret; 6257 int ret;
6261 u32 mask; 6258 u32 mask;
@@ -6346,16 +6343,7 @@ int si_dpm_init(struct radeon_device *rdev)
6346 si_pi->vddc_phase_shed_control = 6343 si_pi->vddc_phase_shed_control =
6347 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, VOLTAGE_OBJ_PHASE_LUT); 6344 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, VOLTAGE_OBJ_PHASE_LUT);
6348 6345
6349 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 6346 rv770_get_engine_memory_ss(rdev);
6350 &frev, &crev, &data_offset)) {
6351 pi->sclk_ss = true;
6352 pi->mclk_ss = true;
6353 pi->dynamic_ss = true;
6354 } else {
6355 pi->sclk_ss = false;
6356 pi->mclk_ss = false;
6357 pi->dynamic_ss = true;
6358 }
6359 6347
6360 pi->asi = RV770_ASI_DFLT; 6348 pi->asi = RV770_ASI_DFLT;
6361 pi->pasi = CYPRESS_HASI_DFLT; 6349 pi->pasi = CYPRESS_HASI_DFLT;