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authorMartin Blumenstingl <martin.blumenstingl@googlemail.com>2017-11-17 17:58:57 -0500
committerKevin Hilman <khilman@baylibre.com>2017-12-06 20:04:04 -0500
commitb02d6e73f5fc96fcd71d50a62c764d4e2c500fa6 (patch)
tree8a90fd9b91644b670888332a63678c49f0595d1b
parent6ca77502050eff3aaa311e77b62b917219fe597d (diff)
ARM: dts: meson8b: use stable UART bindings with correct gate clock
Switch to the stable UART bindings and add the correct gate clocks to the non-AO UART nodes. This fixes the non-AO UARTs if the bootloader didn't un-gate the clocks. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
-rw-r--r--arch/arm/boot/dts/meson8b.dtsi16
1 files changed, 12 insertions, 4 deletions
diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
index b6de3edfcb21..7cd03ed3742e 100644
--- a/arch/arm/boot/dts/meson8b.dtsi
+++ b/arch/arm/boot/dts/meson8b.dtsi
@@ -250,19 +250,27 @@
250}; 250};
251 251
252&uart_AO { 252&uart_AO {
253 clocks = <&clkc CLKID_CLK81>; 253 compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
254 clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>;
255 clock-names = "baud", "xtal", "pclk";
254}; 256};
255 257
256&uart_A { 258&uart_A {
257 clocks = <&clkc CLKID_CLK81>; 259 compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
260 clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART0>;
261 clock-names = "baud", "xtal", "pclk";
258}; 262};
259 263
260&uart_B { 264&uart_B {
261 clocks = <&clkc CLKID_CLK81>; 265 compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
266 clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART1>;
267 clock-names = "baud", "xtal", "pclk";
262}; 268};
263 269
264&uart_C { 270&uart_C {
265 clocks = <&clkc CLKID_CLK81>; 271 compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
272 clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART2>;
273 clock-names = "baud", "xtal", "pclk";
266}; 274};
267 275
268&usb0 { 276&usb0 {