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authorOlof Johansson <olof@lixom.net>2018-09-23 09:20:06 -0400
committerOlof Johansson <olof@lixom.net>2018-09-23 09:20:06 -0400
commit923769f7b3a51c7d82caaf8cb651c5dde60aca34 (patch)
treeee5139581a8a8140c373c0771a2f0ce438268afd
parent89cb3a4c976189a5c6529ee5f5db712949080470 (diff)
parent78f26da3ffbce0ea3692a89fe3f5487cb8dda068 (diff)
Merge tag 'v4.20-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt
New soc support for the px30 quad-core Cortex-A35. New boards are the px30 eval board and roc-rk3399-pc. The rk3328 got support for the one gpio controlled via the general register files and the rk3399 finally got its idle-states defined. And finally fixes and improvements for firefly-rk3399 (wifi), roc-rk3328-cc (sdmmc-uhs, io-domains), rk3328-rock64 (gpio-regulator pin fix) and rk3399-sapphire (gpio-regulator pin fix, pmic pin fix and type-c port supply). * tag 'v4.20-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: arm64: dts: rockchip: Add type-c port supply on rk3399-sapphire board arm64: dts: rockchip: fix vcc_host1_5v pin assign on rk3328-rock64 arm64: dts: rockchip: add WiFi module support for Firefly-RK3399 arm64: dts: rockchip: remove dvs2 pinctrl from pmic on rk3399-sapphire arm64: dts: rockchip: Fix VCC5V0_HOST_EN on rk3399-sapphire arm64: dts: rockchip: re-order vcc_sys on rk3399-sapphire arm64: dts: rockchip: add missing vop properties for px30 arm64: dts: rockchip: Add idle-states to device tree for rk3399 arm64: dts: rockchip: add sdmmc UHS support for roc-rk3328-cc arm64: dts: rockchip: add GRF GPIO controller to rk3328 arm64: dts: rockchip: add io-domain to roc-rk3328-cc arm64: dts: rockchip: add PX30 evaluation board devicetree arm64: dts: rockchip: add core dtsi file for PX30 SoCs dt-bindings: rockchip: grf: add grf and pmugrf description for px30 arm64: dts: rockchip: add support for ROC-RK3399-PC board Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat
-rw-r--r--Documentation/devicetree/bindings/arm/rockchip.txt8
-rw-r--r--Documentation/devicetree/bindings/soc/rockchip/grf.txt2
-rw-r--r--arch/arm64/boot/dts/rockchip/Makefile2
-rw-r--r--arch/arm64/boot/dts/rockchip/px30-evb.dts231
-rw-r--r--arch/arm64/boot/dts/rockchip/px30.dtsi2031
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts30
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3328-rock64.dts4
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3328.dtsi7
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3399-firefly.dts36
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dts680
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi44
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3399.dtsi28
12 files changed, 3083 insertions, 20 deletions
diff --git a/Documentation/devicetree/bindings/arm/rockchip.txt b/Documentation/devicetree/bindings/arm/rockchip.txt
index acfd3c773dd0..5fc9c236ca87 100644
--- a/Documentation/devicetree/bindings/arm/rockchip.txt
+++ b/Documentation/devicetree/bindings/arm/rockchip.txt
@@ -59,6 +59,10 @@ Rockchip platforms device tree bindings
59 Required root node properties: 59 Required root node properties:
60 - compatible = "firefly,roc-rk3328-cc", "rockchip,rk3328"; 60 - compatible = "firefly,roc-rk3328-cc", "rockchip,rk3328";
61 61
62- Firefly ROC-RK3399-PC board:
63 Required root node properties:
64 - compatible = "firefly,roc-rk3399-pc", "rockchip,rk3399";
65
62- ChipSPARK PopMetal-RK3288 board: 66- ChipSPARK PopMetal-RK3288 board:
63 Required root node properties: 67 Required root node properties:
64 - compatible = "chipspark,popmetal-rk3288", "rockchip,rk3288"; 68 - compatible = "chipspark,popmetal-rk3288", "rockchip,rk3288";
@@ -168,6 +172,10 @@ Rockchip platforms device tree bindings
168 Required root node properties: 172 Required root node properties:
169 - compatible = "rockchip,px5-evb", "rockchip,px5", "rockchip,rk3368"; 173 - compatible = "rockchip,px5-evb", "rockchip,px5", "rockchip,rk3368";
170 174
175- Rockchip PX30 Evaluation board:
176 Required root node properties:
177 - compatible = "rockchip,px30-evb", "rockchip,px30";
178
171- Rockchip RV1108 Evaluation board 179- Rockchip RV1108 Evaluation board
172 Required root node properties: 180 Required root node properties:
173 - compatible = "rockchip,rv1108-evb", "rockchip,rv1108"; 181 - compatible = "rockchip,rv1108-evb", "rockchip,rv1108";
diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.txt b/Documentation/devicetree/bindings/soc/rockchip/grf.txt
index 7dc5ce858a0e..46e27cd69f18 100644
--- a/Documentation/devicetree/bindings/soc/rockchip/grf.txt
+++ b/Documentation/devicetree/bindings/soc/rockchip/grf.txt
@@ -13,6 +13,7 @@ On RK3328 SoCs, the GRF adds a section for USB2PHYGRF,
13Required Properties: 13Required Properties:
14 14
15- compatible: GRF should be one of the following: 15- compatible: GRF should be one of the following:
16 - "rockchip,px30-grf", "syscon": for px30
16 - "rockchip,rk3036-grf", "syscon": for rk3036 17 - "rockchip,rk3036-grf", "syscon": for rk3036
17 - "rockchip,rk3066-grf", "syscon": for rk3066 18 - "rockchip,rk3066-grf", "syscon": for rk3066
18 - "rockchip,rk3188-grf", "syscon": for rk3188 19 - "rockchip,rk3188-grf", "syscon": for rk3188
@@ -23,6 +24,7 @@ Required Properties:
23 - "rockchip,rk3399-grf", "syscon": for rk3399 24 - "rockchip,rk3399-grf", "syscon": for rk3399
24 - "rockchip,rv1108-grf", "syscon": for rv1108 25 - "rockchip,rv1108-grf", "syscon": for rv1108
25- compatible: PMUGRF should be one of the following: 26- compatible: PMUGRF should be one of the following:
27 - "rockchip,px30-pmugrf", "syscon": for px30
26 - "rockchip,rk3368-pmugrf", "syscon": for rk3368 28 - "rockchip,rk3368-pmugrf", "syscon": for rk3368
27 - "rockchip,rk3399-pmugrf", "syscon": for rk3399 29 - "rockchip,rk3399-pmugrf", "syscon": for rk3399
28- compatible: SGRF should be one of the following 30- compatible: SGRF should be one of the following
diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
index b0092d95b574..d08b7eda28d2 100644
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -1,4 +1,5 @@
1# SPDX-License-Identifier: GPL-2.0 1# SPDX-License-Identifier: GPL-2.0
2dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb.dtb
2dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb 3dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb
3dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb 4dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb
4dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb 5dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb
@@ -14,5 +15,6 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-firefly.dtb
14dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-bob.dtb 15dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-bob.dtb
15dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-kevin.dtb 16dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-kevin.dtb
16dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou.dtb 17dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou.dtb
18dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc.dtb
17dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire.dtb 19dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire.dtb
18dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator.dtb 20dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator.dtb
diff --git a/arch/arm64/boot/dts/rockchip/px30-evb.dts b/arch/arm64/boot/dts/rockchip/px30-evb.dts
new file mode 100644
index 000000000000..c74aa910a631
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/px30-evb.dts
@@ -0,0 +1,231 @@
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
4 */
5
6/dts-v1/;
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/input/input.h>
9#include <dt-bindings/pinctrl/rockchip.h>
10#include "px30.dtsi"
11
12/ {
13 model = "Rockchip PX30 EVB";
14 compatible = "rockchip,px30-evb", "rockchip,px30";
15
16 chosen {
17 stdout-path = "serial2:1500000n8";
18 };
19
20 adc-keys {
21 compatible = "adc-keys";
22 io-channels = <&saradc 2>;
23 io-channel-names = "buttons";
24 keyup-threshold-microvolt = <1800000>;
25 poll-interval = <100>;
26
27 esc-key {
28 label = "esc";
29 linux,code = <KEY_ESC>;
30 press-threshold-microvolt = <1310000>;
31 };
32
33 home-key {
34 label = "home";
35 linux,code = <KEY_HOME>;
36 press-threshold-microvolt = <624000>;
37 };
38
39 menu-key {
40 label = "menu";
41 linux,code = <KEY_MENU>;
42 press-threshold-microvolt = <987000>;
43 };
44
45 vol-down-key {
46 label = "volume down";
47 linux,code = <KEY_VOLUMEDOWN>;
48 press-threshold-microvolt = <300000>;
49 };
50
51 vol-up-key {
52 label = "volume up";
53 linux,code = <KEY_VOLUMEUP>;
54 press-threshold-microvolt = <17000>;
55 };
56 };
57
58 backlight: backlight {
59 compatible = "pwm-backlight";
60 pwms = <&pwm1 0 25000 0>;
61 };
62
63 sdio_pwrseq: sdio-pwrseq {
64 compatible = "mmc-pwrseq-simple";
65 pinctrl-names = "default";
66 pinctrl-0 = <&wifi_enable_h>;
67
68 /*
69 * On the module itself this is one of these (depending
70 * on the actual card populated):
71 * - SDIO_RESET_L_WL_REG_ON
72 * - PDN (power down when low)
73 */
74 reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; /* GPIO3_A4 */
75 };
76
77 vcc_phy: vcc-phy-regulator {
78 compatible = "regulator-fixed";
79 regulator-name = "vcc_phy";
80 regulator-always-on;
81 regulator-boot-on;
82 };
83
84 vcc5v0_sys: vccsys {
85 compatible = "regulator-fixed";
86 regulator-name = "vcc5v0_sys";
87 regulator-always-on;
88 regulator-boot-on;
89 regulator-min-microvolt = <5000000>;
90 regulator-max-microvolt = <5000000>;
91 };
92};
93
94&display_subsystem {
95 status = "okay";
96};
97
98&emmc {
99 bus-width = <8>;
100 cap-mmc-highspeed;
101 mmc-hs200-1_8v;
102 non-removable;
103 status = "okay";
104};
105
106&gmac {
107 clock_in_out = "output";
108 phy-supply = <&vcc_phy>;
109 snps,reset-gpio = <&gpio2 13 GPIO_ACTIVE_LOW>;
110 snps,reset-active-low;
111 snps,reset-delays-us = <0 50000 50000>;
112 status = "okay";
113};
114
115&i2c0 {
116 status = "okay";
117};
118
119&i2s1_2ch {
120 status = "okay";
121};
122
123&io_domains {
124 status = "okay";
125};
126
127&pinctrl {
128 headphone {
129 hp_det: hp-det {
130 rockchip,pins =
131 <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>;
132 };
133 };
134
135 pmic {
136 pmic_int: pmic_int {
137 rockchip,pins =
138 <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
139 };
140
141 soc_slppin_gpio: soc_slppin_gpio {
142 rockchip,pins =
143 <0 RK_PA4 RK_FUNC_GPIO &pcfg_output_low>;
144 };
145
146 soc_slppin_slp: soc_slppin_slp {
147 rockchip,pins =
148 <0 RK_PA4 RK_FUNC_1 &pcfg_pull_none>;
149 };
150
151 soc_slppin_rst: soc_slppin_rst {
152 rockchip,pins =
153 <0 RK_PA4 RK_FUNC_2 &pcfg_pull_none>;
154 };
155 };
156
157 sdio-pwrseq {
158 wifi_enable_h: wifi-enable-h {
159 rockchip,pins =
160 <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
161 };
162 };
163};
164
165&pmu_io_domains {
166 status = "okay";
167};
168
169&pwm1 {
170 status = "okay";
171};
172
173&saradc {
174 status = "okay";
175};
176
177&sdmmc {
178 bus-width = <4>;
179 cap-mmc-highspeed;
180 cap-sd-highspeed;
181 card-detect-delay = <800>;
182 sd-uhs-sdr12;
183 sd-uhs-sdr25;
184 sd-uhs-sdr50;
185 sd-uhs-sdr104;
186 status = "okay";
187};
188
189&sdio {
190 bus-width = <4>;
191 cap-sd-highspeed;
192 keep-power-in-suspend;
193 non-removable;
194 mmc-pwrseq = <&sdio_pwrseq>;
195 sd-uhs-sdr104;
196 status = "okay";
197};
198
199&uart1 {
200 pinctrl-names = "default";
201 pinctrl-0 = <&uart1_xfer &uart1_cts>;
202 status = "okay";
203};
204
205&uart2 {
206 status = "okay";
207};
208
209&usb_host0_ehci {
210 status = "okay";
211};
212
213&usb_host0_ohci {
214 status = "okay";
215};
216
217&vopb {
218 status = "okay";
219};
220
221&vopb_mmu {
222 status = "okay";
223};
224
225&vopl {
226 status = "okay";
227};
228
229&vopl_mmu {
230 status = "okay";
231};
diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi
new file mode 100644
index 000000000000..fa82dd80c801
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/px30.dtsi
@@ -0,0 +1,2031 @@
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
4 */
5
6#include <dt-bindings/clock/px30-cru.h>
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include <dt-bindings/interrupt-controller/irq.h>
10#include <dt-bindings/pinctrl/rockchip.h>
11#include <dt-bindings/power/px30-power.h>
12#include <dt-bindings/soc/rockchip,boot-mode.h>
13
14/ {
15 compatible = "rockchip,px30";
16
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
20
21 aliases {
22 ethernet0 = &gmac;
23 i2c0 = &i2c0;
24 i2c1 = &i2c1;
25 i2c2 = &i2c2;
26 i2c3 = &i2c3;
27 serial0 = &uart0;
28 serial1 = &uart1;
29 serial2 = &uart2;
30 serial3 = &uart3;
31 serial4 = &uart4;
32 serial5 = &uart5;
33 spi0 = &spi0;
34 spi1 = &spi1;
35 };
36
37 cpus {
38 #address-cells = <2>;
39 #size-cells = <0>;
40
41 cpu0: cpu@0 {
42 device_type = "cpu";
43 compatible = "arm,cortex-a35", "arm,armv8";
44 reg = <0x0 0x0>;
45 enable-method = "psci";
46 clocks = <&cru ARMCLK>;
47 #cooling-cells = <2>;
48 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
49 dynamic-power-coefficient = <90>;
50 operating-points-v2 = <&cpu0_opp_table>;
51 };
52
53 cpu1: cpu@1 {
54 device_type = "cpu";
55 compatible = "arm,cortex-a35", "arm,armv8";
56 reg = <0x0 0x1>;
57 enable-method = "psci";
58 clocks = <&cru ARMCLK>;
59 #cooling-cells = <2>;
60 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
61 dynamic-power-coefficient = <90>;
62 operating-points-v2 = <&cpu0_opp_table>;
63 };
64
65 cpu2: cpu@2 {
66 device_type = "cpu";
67 compatible = "arm,cortex-a35", "arm,armv8";
68 reg = <0x0 0x2>;
69 enable-method = "psci";
70 clocks = <&cru ARMCLK>;
71 #cooling-cells = <2>;
72 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
73 dynamic-power-coefficient = <90>;
74 operating-points-v2 = <&cpu0_opp_table>;
75 };
76
77 cpu3: cpu@3 {
78 device_type = "cpu";
79 compatible = "arm,cortex-a35", "arm,armv8";
80 reg = <0x0 0x3>;
81 enable-method = "psci";
82 clocks = <&cru ARMCLK>;
83 #cooling-cells = <2>;
84 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
85 dynamic-power-coefficient = <90>;
86 operating-points-v2 = <&cpu0_opp_table>;
87 };
88
89 idle-states {
90 entry-method = "psci";
91
92 CPU_SLEEP: cpu-sleep {
93 compatible = "arm,idle-state";
94 local-timer-stop;
95 arm,psci-suspend-param = <0x0010000>;
96 entry-latency-us = <120>;
97 exit-latency-us = <250>;
98 min-residency-us = <900>;
99 };
100
101 CLUSTER_SLEEP: cluster-sleep {
102 compatible = "arm,idle-state";
103 local-timer-stop;
104 arm,psci-suspend-param = <0x1010000>;
105 entry-latency-us = <400>;
106 exit-latency-us = <500>;
107 min-residency-us = <2000>;
108 };
109 };
110 };
111
112 cpu0_opp_table: cpu0-opp-table {
113 compatible = "operating-points-v2";
114 opp-shared;
115
116 opp-408000000 {
117 opp-hz = /bits/ 64 <408000000>;
118 opp-microvolt = <950000 950000 1350000>;
119 clock-latency-ns = <40000>;
120 opp-suspend;
121 };
122 opp-600000000 {
123 opp-hz = /bits/ 64 <600000000>;
124 opp-microvolt = <950000 950000 1350000>;
125 clock-latency-ns = <40000>;
126 };
127 opp-816000000 {
128 opp-hz = /bits/ 64 <816000000>;
129 opp-microvolt = <1050000 1050000 1350000>;
130 clock-latency-ns = <40000>;
131 };
132 opp-1008000000 {
133 opp-hz = /bits/ 64 <1008000000>;
134 opp-microvolt = <1175000 1175000 1350000>;
135 clock-latency-ns = <40000>;
136 };
137 opp-1200000000 {
138 opp-hz = /bits/ 64 <1200000000>;
139 opp-microvolt = <1300000 1300000 1350000>;
140 clock-latency-ns = <40000>;
141 };
142 opp-1296000000 {
143 opp-hz = /bits/ 64 <1296000000>;
144 opp-microvolt = <1350000 1350000 1350000>;
145 clock-latency-ns = <40000>;
146 };
147 };
148
149 arm-pmu {
150 compatible = "arm,cortex-a53-pmu";
151 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
152 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
153 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
154 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
155 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
156 };
157
158 display_subsystem: display-subsystem {
159 compatible = "rockchip,display-subsystem";
160 ports = <&vopb_out>, <&vopl_out>;
161 status = "disabled";
162 };
163
164 firmware {
165 optee {
166 compatible = "linaro,optee-tz";
167 method = "smc";
168 };
169 };
170
171 gmac_clkin: external-gmac-clock {
172 compatible = "fixed-clock";
173 clock-frequency = <50000000>;
174 clock-output-names = "gmac_clkin";
175 #clock-cells = <0>;
176 };
177
178 psci {
179 compatible = "arm,psci-1.0";
180 method = "smc";
181 };
182
183 timer {
184 compatible = "arm,armv8-timer";
185 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
186 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
187 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
188 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
189 };
190
191 xin24m: xin24m {
192 compatible = "fixed-clock";
193 #clock-cells = <0>;
194 clock-frequency = <24000000>;
195 clock-output-names = "xin24m";
196 };
197
198 xin32k: xin32k {
199 compatible = "fixed-clock";
200 #clock-cells = <0>;
201 clock-frequency = <32768>;
202 clock-output-names = "xin32k";
203 };
204
205 pmu: power-management@ff000000 {
206 compatible = "rockchip,px30-pmu", "syscon", "simple-mfd";
207 reg = <0x0 0xff000000 0x0 0x1000>;
208
209 power: power-controller {
210 compatible = "rockchip,px30-power-controller";
211 #power-domain-cells = <1>;
212 #address-cells = <1>;
213 #size-cells = <0>;
214
215 /* These power domains are grouped by VD_LOGIC */
216 pd_usb@PX30_PD_USB {
217 reg = <PX30_PD_USB>;
218 clocks = <&cru HCLK_HOST>,
219 <&cru HCLK_OTG>,
220 <&cru SCLK_OTG_ADP>;
221 pm_qos = <&qos_usb_host>, <&qos_usb_otg>;
222 };
223 pd_sdcard@PX30_PD_SDCARD {
224 reg = <PX30_PD_SDCARD>;
225 clocks = <&cru HCLK_SDMMC>,
226 <&cru SCLK_SDMMC>;
227 pm_qos = <&qos_sdmmc>;
228 };
229 pd_gmac@PX30_PD_GMAC {
230 reg = <PX30_PD_GMAC>;
231 clocks = <&cru ACLK_GMAC>,
232 <&cru PCLK_GMAC>,
233 <&cru SCLK_MAC_REF>,
234 <&cru SCLK_GMAC_RX_TX>;
235 pm_qos = <&qos_gmac>;
236 };
237 pd_mmc_nand@PX30_PD_MMC_NAND {
238 reg = <PX30_PD_MMC_NAND>;
239 clocks = <&cru HCLK_NANDC>,
240 <&cru HCLK_EMMC>,
241 <&cru HCLK_SDIO>,
242 <&cru HCLK_SFC>,
243 <&cru SCLK_EMMC>,
244 <&cru SCLK_NANDC>,
245 <&cru SCLK_SDIO>,
246 <&cru SCLK_SFC>;
247 pm_qos = <&qos_emmc>, <&qos_nand>,
248 <&qos_sdio>, <&qos_sfc>;
249 };
250 pd_vpu@PX30_PD_VPU {
251 reg = <PX30_PD_VPU>;
252 clocks = <&cru ACLK_VPU>,
253 <&cru HCLK_VPU>,
254 <&cru SCLK_CORE_VPU>;
255 pm_qos = <&qos_vpu>, <&qos_vpu_r128>;
256 };
257 pd_vo@PX30_PD_VO {
258 reg = <PX30_PD_VO>;
259 clocks = <&cru ACLK_RGA>,
260 <&cru ACLK_VOPB>,
261 <&cru ACLK_VOPL>,
262 <&cru DCLK_VOPB>,
263 <&cru DCLK_VOPL>,
264 <&cru HCLK_RGA>,
265 <&cru HCLK_VOPB>,
266 <&cru HCLK_VOPL>,
267 <&cru PCLK_MIPI_DSI>,
268 <&cru SCLK_RGA_CORE>,
269 <&cru SCLK_VOPB_PWM>;
270 pm_qos = <&qos_rga_rd>, <&qos_rga_wr>,
271 <&qos_vop_m0>, <&qos_vop_m1>;
272 };
273 pd_vi@PX30_PD_VI {
274 reg = <PX30_PD_VI>;
275 clocks = <&cru ACLK_CIF>,
276 <&cru ACLK_ISP>,
277 <&cru HCLK_CIF>,
278 <&cru HCLK_ISP>,
279 <&cru SCLK_ISP>;
280 pm_qos = <&qos_isp_128>, <&qos_isp_rd>,
281 <&qos_isp_wr>, <&qos_isp_m1>,
282 <&qos_vip>;
283 };
284 pd_gpu@PX30_PD_GPU {
285 reg = <PX30_PD_GPU>;
286 clocks = <&cru SCLK_GPU>;
287 pm_qos = <&qos_gpu>;
288 };
289 };
290 };
291
292 pmugrf: syscon@ff010000 {
293 compatible = "rockchip,px30-pmugrf", "syscon", "simple-mfd";
294 reg = <0x0 0xff010000 0x0 0x1000>;
295 #address-cells = <1>;
296 #size-cells = <1>;
297
298 pmu_io_domains: io-domains {
299 compatible = "rockchip,px30-pmu-io-voltage-domain";
300 status = "disabled";
301 };
302
303 reboot-mode {
304 compatible = "syscon-reboot-mode";
305 offset = <0x200>;
306 mode-bootloader = <BOOT_BL_DOWNLOAD>;
307 mode-fastboot = <BOOT_FASTBOOT>;
308 mode-loader = <BOOT_BL_DOWNLOAD>;
309 mode-normal = <BOOT_NORMAL>;
310 mode-recovery = <BOOT_RECOVERY>;
311 };
312 };
313
314 uart0: serial@ff030000 {
315 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
316 reg = <0x0 0xff030000 0x0 0x100>;
317 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
318 clocks = <&pmucru SCLK_UART0_PMU>, <&pmucru PCLK_UART0_PMU>;
319 clock-names = "baudclk", "apb_pclk";
320 dmas = <&dmac 0>, <&dmac 1>;
321 dma-names = "tx", "rx";
322 reg-shift = <2>;
323 reg-io-width = <4>;
324 pinctrl-names = "default";
325 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
326 status = "disabled";
327 };
328
329 i2s1_2ch: i2s@ff070000 {
330 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s";
331 reg = <0x0 0xff070000 0x0 0x1000>;
332 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
333 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>;
334 clock-names = "i2s_clk", "i2s_hclk";
335 dmas = <&dmac 18>, <&dmac 19>;
336 dma-names = "tx", "rx";
337 pinctrl-names = "default";
338 pinctrl-0 = <&i2s1_2ch_sclk &i2s1_2ch_lrck
339 &i2s1_2ch_sdi &i2s1_2ch_sdo>;
340 #sound-dai-cells = <0>;
341 status = "disabled";
342 };
343
344 i2s2_2ch: i2s@ff080000 {
345 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s";
346 reg = <0x0 0xff080000 0x0 0x1000>;
347 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
348 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>;
349 clock-names = "i2s_clk", "i2s_hclk";
350 dmas = <&dmac 20>, <&dmac 21>;
351 dma-names = "tx", "rx";
352 pinctrl-names = "default";
353 pinctrl-0 = <&i2s2_2ch_sclk &i2s2_2ch_lrck
354 &i2s2_2ch_sdi &i2s2_2ch_sdo>;
355 #sound-dai-cells = <0>;
356 status = "disabled";
357 };
358
359 gic: interrupt-controller@ff131000 {
360 compatible = "arm,gic-400";
361 #interrupt-cells = <3>;
362 #address-cells = <0>;
363 interrupt-controller;
364 reg = <0x0 0xff131000 0 0x1000>,
365 <0x0 0xff132000 0 0x2000>,
366 <0x0 0xff134000 0 0x2000>,
367 <0x0 0xff136000 0 0x2000>;
368 interrupts = <GIC_PPI 9
369 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
370 };
371
372 grf: syscon@ff140000 {
373 compatible = "rockchip,px30-grf", "syscon", "simple-mfd";
374 reg = <0x0 0xff140000 0x0 0x1000>;
375 #address-cells = <1>;
376 #size-cells = <1>;
377
378 io_domains: io-domains {
379 compatible = "rockchip,px30-io-voltage-domain";
380 status = "disabled";
381 };
382 };
383
384 uart1: serial@ff158000 {
385 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
386 reg = <0x0 0xff158000 0x0 0x100>;
387 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
388 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
389 clock-names = "baudclk", "apb_pclk";
390 dmas = <&dmac 2>, <&dmac 3>;
391 dma-names = "tx", "rx";
392 reg-shift = <2>;
393 reg-io-width = <4>;
394 pinctrl-names = "default";
395 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
396 status = "disabled";
397 };
398
399 uart2: serial@ff160000 {
400 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
401 reg = <0x0 0xff160000 0x0 0x100>;
402 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
403 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
404 clock-names = "baudclk", "apb_pclk";
405 dmas = <&dmac 4>, <&dmac 5>;
406 dma-names = "tx", "rx";
407 reg-shift = <2>;
408 reg-io-width = <4>;
409 pinctrl-names = "default";
410 pinctrl-0 = <&uart2m0_xfer>;
411 status = "disabled";
412 };
413
414 uart3: serial@ff168000 {
415 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
416 reg = <0x0 0xff168000 0x0 0x100>;
417 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
418 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
419 clock-names = "baudclk", "apb_pclk";
420 dmas = <&dmac 6>, <&dmac 7>;
421 dma-names = "tx", "rx";
422 reg-shift = <2>;
423 reg-io-width = <4>;
424 pinctrl-names = "default";
425 pinctrl-0 = <&uart3m1_xfer &uart3m1_cts &uart3m1_rts>;
426 status = "disabled";
427 };
428
429 uart4: serial@ff170000 {
430 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
431 reg = <0x0 0xff170000 0x0 0x100>;
432 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
433 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
434 clock-names = "baudclk", "apb_pclk";
435 dmas = <&dmac 8>, <&dmac 9>;
436 dma-names = "tx", "rx";
437 reg-shift = <2>;
438 reg-io-width = <4>;
439 pinctrl-names = "default";
440 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
441 status = "disabled";
442 };
443
444 uart5: serial@ff178000 {
445 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
446 reg = <0x0 0xff178000 0x0 0x100>;
447 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
448 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
449 clock-names = "baudclk", "apb_pclk";
450 dmas = <&dmac 10>, <&dmac 11>;
451 dma-names = "tx", "rx";
452 reg-shift = <2>;
453 reg-io-width = <4>;
454 pinctrl-names = "default";
455 pinctrl-0 = <&uart5_xfer &uart5_cts &uart5_rts>;
456 status = "disabled";
457 };
458
459 i2c0: i2c@ff180000 {
460 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
461 reg = <0x0 0xff180000 0x0 0x1000>;
462 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
463 clock-names = "i2c", "pclk";
464 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
465 pinctrl-names = "default";
466 pinctrl-0 = <&i2c0_xfer>;
467 #address-cells = <1>;
468 #size-cells = <0>;
469 status = "disabled";
470 };
471
472 i2c1: i2c@ff190000 {
473 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
474 reg = <0x0 0xff190000 0x0 0x1000>;
475 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
476 clock-names = "i2c", "pclk";
477 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
478 pinctrl-names = "default";
479 pinctrl-0 = <&i2c1_xfer>;
480 #address-cells = <1>;
481 #size-cells = <0>;
482 status = "disabled";
483 };
484
485 i2c2: i2c@ff1a0000 {
486 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
487 reg = <0x0 0xff1a0000 0x0 0x1000>;
488 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
489 clock-names = "i2c", "pclk";
490 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
491 pinctrl-names = "default";
492 pinctrl-0 = <&i2c2_xfer>;
493 #address-cells = <1>;
494 #size-cells = <0>;
495 status = "disabled";
496 };
497
498 i2c3: i2c@ff1b0000 {
499 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
500 reg = <0x0 0xff1b0000 0x0 0x1000>;
501 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
502 clock-names = "i2c", "pclk";
503 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
504 pinctrl-names = "default";
505 pinctrl-0 = <&i2c3_xfer>;
506 #address-cells = <1>;
507 #size-cells = <0>;
508 status = "disabled";
509 };
510
511 spi0: spi@ff1d0000 {
512 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi";
513 reg = <0x0 0xff1d0000 0x0 0x1000>;
514 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
515 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
516 clock-names = "spiclk", "apb_pclk";
517 dmas = <&dmac 12>, <&dmac 13>;
518 dma-names = "tx", "rx";
519 pinctrl-names = "default";
520 pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>;
521 #address-cells = <1>;
522 #size-cells = <0>;
523 status = "disabled";
524 };
525
526 spi1: spi@ff1d8000 {
527 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi";
528 reg = <0x0 0xff1d8000 0x0 0x1000>;
529 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
530 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
531 clock-names = "spiclk", "apb_pclk";
532 dmas = <&dmac 14>, <&dmac 15>;
533 dma-names = "tx", "rx";
534 pinctrl-names = "default";
535 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_csn1 &spi1_miso &spi1_mosi>;
536 #address-cells = <1>;
537 #size-cells = <0>;
538 status = "disabled";
539 };
540
541 wdt: watchdog@ff1e0000 {
542 compatible = "snps,dw-wdt";
543 reg = <0x0 0xff1e0000 0x0 0x100>;
544 clocks = <&cru PCLK_WDT_NS>;
545 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
546 status = "disabled";
547 };
548
549 pwm0: pwm@ff200000 {
550 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
551 reg = <0x0 0xff200000 0x0 0x10>;
552 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
553 clock-names = "pwm", "pclk";
554 pinctrl-names = "default";
555 pinctrl-0 = <&pwm0_pin>;
556 #pwm-cells = <3>;
557 status = "disabled";
558 };
559
560 pwm1: pwm@ff200010 {
561 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
562 reg = <0x0 0xff200010 0x0 0x10>;
563 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
564 clock-names = "pwm", "pclk";
565 pinctrl-names = "default";
566 pinctrl-0 = <&pwm1_pin>;
567 #pwm-cells = <3>;
568 status = "disabled";
569 };
570
571 pwm2: pwm@ff200020 {
572 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
573 reg = <0x0 0xff200020 0x0 0x10>;
574 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
575 clock-names = "pwm", "pclk";
576 pinctrl-names = "default";
577 pinctrl-0 = <&pwm2_pin>;
578 #pwm-cells = <3>;
579 status = "disabled";
580 };
581
582 pwm3: pwm@ff200030 {
583 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
584 reg = <0x0 0xff200030 0x0 0x10>;
585 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
586 clock-names = "pwm", "pclk";
587 pinctrl-names = "default";
588 pinctrl-0 = <&pwm3_pin>;
589 #pwm-cells = <3>;
590 status = "disabled";
591 };
592
593 pwm4: pwm@ff208000 {
594 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
595 reg = <0x0 0xff208000 0x0 0x10>;
596 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
597 clock-names = "pwm", "pclk";
598 pinctrl-names = "default";
599 pinctrl-0 = <&pwm4_pin>;
600 #pwm-cells = <3>;
601 status = "disabled";
602 };
603
604 pwm5: pwm@ff208010 {
605 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
606 reg = <0x0 0xff208010 0x0 0x10>;
607 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
608 clock-names = "pwm", "pclk";
609 pinctrl-names = "default";
610 pinctrl-0 = <&pwm5_pin>;
611 #pwm-cells = <3>;
612 status = "disabled";
613 };
614
615 pwm6: pwm@ff208020 {
616 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
617 reg = <0x0 0xff208020 0x0 0x10>;
618 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
619 clock-names = "pwm", "pclk";
620 pinctrl-names = "default";
621 pinctrl-0 = <&pwm6_pin>;
622 #pwm-cells = <3>;
623 status = "disabled";
624 };
625
626 pwm7: pwm@ff208030 {
627 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
628 reg = <0x0 0xff208030 0x0 0x10>;
629 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
630 clock-names = "pwm", "pclk";
631 pinctrl-names = "default";
632 pinctrl-0 = <&pwm7_pin>;
633 #pwm-cells = <3>;
634 status = "disabled";
635 };
636
637 rktimer: timer@ff210000 {
638 compatible = "rockchip,px30-timer", "rockchip,rk3288-timer";
639 reg = <0x0 0xff210000 0x0 0x1000>;
640 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
641 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>;
642 clock-names = "pclk", "timer";
643 };
644
645 amba {
646 compatible = "simple-bus";
647 #address-cells = <2>;
648 #size-cells = <2>;
649 ranges;
650
651 dmac: dmac@ff240000 {
652 compatible = "arm,pl330", "arm,primecell";
653 reg = <0x0 0xff240000 0x0 0x4000>;
654 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
655 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
656 clocks = <&cru ACLK_DMAC>;
657 clock-names = "apb_pclk";
658 #dma-cells = <1>;
659 };
660 };
661
662 saradc: saradc@ff288000 {
663 compatible = "rockchip,px30-saradc", "rockchip,rk3399-saradc";
664 reg = <0x0 0xff288000 0x0 0x100>;
665 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
666 #io-channel-cells = <1>;
667 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
668 clock-names = "saradc", "apb_pclk";
669 resets = <&cru SRST_SARADC_P>;
670 reset-names = "saradc-apb";
671 status = "disabled";
672 };
673
674 cru: clock-controller@ff2b0000 {
675 compatible = "rockchip,px30-cru";
676 reg = <0x0 0xff2b0000 0x0 0x1000>;
677 rockchip,grf = <&grf>;
678 #clock-cells = <1>;
679 #reset-cells = <1>;
680
681 assigned-clocks = <&cru PLL_NPLL>;
682 assigned-clock-rates = <1188000000>;
683 };
684
685 pmucru: clock-controller@ff2bc000 {
686 compatible = "rockchip,px30-pmucru";
687 reg = <0x0 0xff2bc000 0x0 0x1000>;
688 rockchip,grf = <&grf>;
689 #clock-cells = <1>;
690 #reset-cells = <1>;
691
692 assigned-clocks =
693 <&pmucru PLL_GPLL>, <&pmucru PCLK_PMU_PRE>,
694 <&pmucru SCLK_WIFI_PMU>, <&cru ARMCLK>,
695 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
696 <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>,
697 <&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>;
698 assigned-clock-rates =
699 <1200000000>, <100000000>,
700 <26000000>, <600000000>,
701 <200000000>, <200000000>,
702 <150000000>, <150000000>,
703 <100000000>, <200000000>;
704 };
705
706 usb_host0_ehci: usb@ff340000 {
707 compatible = "generic-ehci";
708 reg = <0x0 0xff340000 0x0 0x10000>;
709 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
710 clocks = <&cru HCLK_HOST>;
711 clock-names = "usbhost";
712 power-domains = <&power PX30_PD_USB>;
713 status = "disabled";
714 };
715
716 usb_host0_ohci: usb@ff350000 {
717 compatible = "generic-ohci";
718 reg = <0x0 0xff350000 0x0 0x10000>;
719 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
720 clocks = <&cru HCLK_HOST>;
721 clock-names = "usbhost";
722 power-domains = <&power PX30_PD_USB>;
723 status = "disabled";
724 };
725
726 gmac: ethernet@ff360000 {
727 compatible = "rockchip,px30-gmac";
728 reg = <0x0 0xff360000 0x0 0x10000>;
729 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
730 interrupt-names = "macirq";
731 clocks = <&cru SCLK_GMAC>, <&cru SCLK_GMAC_RX_TX>,
732 <&cru SCLK_GMAC_RX_TX>, <&cru SCLK_MAC_REF>,
733 <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>,
734 <&cru PCLK_GMAC>, <&cru SCLK_GMAC_RMII>;
735 clock-names = "stmmaceth", "mac_clk_rx",
736 "mac_clk_tx", "clk_mac_ref",
737 "clk_mac_refout", "aclk_mac",
738 "pclk_mac", "clk_mac_speed";
739 rockchip,grf = <&grf>;
740 phy-mode = "rmii";
741 pinctrl-names = "default";
742 pinctrl-0 = <&rmii_pins &mac_refclk_12ma>;
743 power-domains = <&power PX30_PD_GMAC>;
744 resets = <&cru SRST_GMAC_A>;
745 reset-names = "stmmaceth";
746 status = "disabled";
747 };
748
749 sdmmc: dwmmc@ff370000 {
750 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
751 reg = <0x0 0xff370000 0x0 0x4000>;
752 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
753 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
754 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
755 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
756 fifo-depth = <0x100>;
757 max-frequency = <150000000>;
758 pinctrl-names = "default";
759 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
760 power-domains = <&power PX30_PD_SDCARD>;
761 status = "disabled";
762 };
763
764 sdio: dwmmc@ff380000 {
765 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
766 reg = <0x0 0xff380000 0x0 0x4000>;
767 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
768 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
769 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
770 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
771 fifo-depth = <0x100>;
772 max-frequency = <150000000>;
773 pinctrl-names = "default";
774 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>;
775 power-domains = <&power PX30_PD_MMC_NAND>;
776 status = "disabled";
777 };
778
779 emmc: dwmmc@ff390000 {
780 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
781 reg = <0x0 0xff390000 0x0 0x4000>;
782 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
783 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
784 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
785 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
786 fifo-depth = <0x100>;
787 max-frequency = <150000000>;
788 power-domains = <&power PX30_PD_MMC_NAND>;
789 status = "disabled";
790 };
791
792 vopb: vop@ff460000 {
793 compatible = "rockchip,px30-vop-big";
794 reg = <0x0 0xff460000 0x0 0xefc>;
795 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
796 clocks = <&cru ACLK_VOPB>, <&cru DCLK_VOPB>,
797 <&cru HCLK_VOPB>;
798 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
799 resets = <&cru SRST_VOPB_A>, <&cru SRST_VOPB_H>, <&cru SRST_VOPB>;
800 reset-names = "axi", "ahb", "dclk";
801 iommus = <&vopb_mmu>;
802 power-domains = <&power PX30_PD_VO>;
803 rockchip,grf = <&grf>;
804 status = "disabled";
805
806 vopb_out: port {
807 #address-cells = <1>;
808 #size-cells = <0>;
809 };
810 };
811
812 vopb_mmu: iommu@ff460f00 {
813 compatible = "rockchip,iommu";
814 reg = <0x0 0xff460f00 0x0 0x100>;
815 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
816 interrupt-names = "vopb_mmu";
817 clocks = <&cru ACLK_VOPB>, <&cru HCLK_VOPB>;
818 clock-names = "aclk", "hclk";
819 power-domains = <&power PX30_PD_VO>;
820 #iommu-cells = <0>;
821 status = "disabled";
822 };
823
824 vopl: vop@ff470000 {
825 compatible = "rockchip,px30-vop-lit";
826 reg = <0x0 0xff470000 0x0 0xefc>;
827 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
828 clocks = <&cru ACLK_VOPL>, <&cru DCLK_VOPL>,
829 <&cru HCLK_VOPL>;
830 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
831 resets = <&cru SRST_VOPL_A>, <&cru SRST_VOPL_H>, <&cru SRST_VOPL>;
832 reset-names = "axi", "ahb", "dclk";
833 iommus = <&vopl_mmu>;
834 power-domains = <&power PX30_PD_VO>;
835 rockchip,grf = <&grf>;
836 status = "disabled";
837
838 vopl_out: port {
839 #address-cells = <1>;
840 #size-cells = <0>;
841 };
842 };
843
844 vopl_mmu: iommu@ff470f00 {
845 compatible = "rockchip,iommu";
846 reg = <0x0 0xff470f00 0x0 0x100>;
847 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
848 interrupt-names = "vopl_mmu";
849 clocks = <&cru ACLK_VOPL>, <&cru HCLK_VOPL>;
850 clock-names = "aclk", "hclk";
851 power-domains = <&power PX30_PD_VO>;
852 #iommu-cells = <0>;
853 status = "disabled";
854 };
855
856 qos_gmac: qos@ff518000 {
857 compatible = "syscon";
858 reg = <0x0 0xff518000 0x0 0x20>;
859 };
860
861 qos_gpu: qos@ff520000 {
862 compatible = "syscon";
863 reg = <0x0 0xff520000 0x0 0x20>;
864 };
865
866 qos_sdmmc: qos@ff52c000 {
867 compatible = "syscon";
868 reg = <0x0 0xff52c000 0x0 0x20>;
869 };
870
871 qos_emmc: qos@ff538000 {
872 compatible = "syscon";
873 reg = <0x0 0xff538000 0x0 0x20>;
874 };
875
876 qos_nand: qos@ff538080 {
877 compatible = "syscon";
878 reg = <0x0 0xff538080 0x0 0x20>;
879 };
880
881 qos_sdio: qos@ff538100 {
882 compatible = "syscon";
883 reg = <0x0 0xff538100 0x0 0x20>;
884 };
885
886 qos_sfc: qos@ff538180 {
887 compatible = "syscon";
888 reg = <0x0 0xff538180 0x0 0x20>;
889 };
890
891 qos_usb_host: qos@ff540000 {
892 compatible = "syscon";
893 reg = <0x0 0xff540000 0x0 0x20>;
894 };
895
896 qos_usb_otg: qos@ff540080 {
897 compatible = "syscon";
898 reg = <0x0 0xff540080 0x0 0x20>;
899 };
900
901 qos_isp_128: qos@ff548000 {
902 compatible = "syscon";
903 reg = <0x0 0xff548000 0x0 0x20>;
904 };
905
906 qos_isp_rd: qos@ff548080 {
907 compatible = "syscon";
908 reg = <0x0 0xff548080 0x0 0x20>;
909 };
910
911 qos_isp_wr: qos@ff548100 {
912 compatible = "syscon";
913 reg = <0x0 0xff548100 0x0 0x20>;
914 };
915
916 qos_isp_m1: qos@ff548180 {
917 compatible = "syscon";
918 reg = <0x0 0xff548180 0x0 0x20>;
919 };
920
921 qos_vip: qos@ff548200 {
922 compatible = "syscon";
923 reg = <0x0 0xff548200 0x0 0x20>;
924 };
925
926 qos_rga_rd: qos@ff550000 {
927 compatible = "syscon";
928 reg = <0x0 0xff550000 0x0 0x20>;
929 };
930
931 qos_rga_wr: qos@ff550080 {
932 compatible = "syscon";
933 reg = <0x0 0xff550080 0x0 0x20>;
934 };
935
936 qos_vop_m0: qos@ff550100 {
937 compatible = "syscon";
938 reg = <0x0 0xff550100 0x0 0x20>;
939 };
940
941 qos_vop_m1: qos@ff550180 {
942 compatible = "syscon";
943 reg = <0x0 0xff550180 0x0 0x20>;
944 };
945
946 qos_vpu: qos@ff558000 {
947 compatible = "syscon";
948 reg = <0x0 0xff558000 0x0 0x20>;
949 };
950
951 qos_vpu_r128: qos@ff558080 {
952 compatible = "syscon";
953 reg = <0x0 0xff558080 0x0 0x20>;
954 };
955
956 pinctrl: pinctrl {
957 compatible = "rockchip,px30-pinctrl";
958 rockchip,grf = <&grf>;
959 rockchip,pmu = <&pmugrf>;
960 #address-cells = <2>;
961 #size-cells = <2>;
962 ranges;
963
964 gpio0: gpio0@ff040000 {
965 compatible = "rockchip,gpio-bank";
966 reg = <0x0 0xff040000 0x0 0x100>;
967 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
968 clocks = <&pmucru PCLK_GPIO0_PMU>;
969 gpio-controller;
970 #gpio-cells = <2>;
971
972 interrupt-controller;
973 #interrupt-cells = <2>;
974 };
975
976 gpio1: gpio1@ff250000 {
977 compatible = "rockchip,gpio-bank";
978 reg = <0x0 0xff250000 0x0 0x100>;
979 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
980 clocks = <&cru PCLK_GPIO1>;
981 gpio-controller;
982 #gpio-cells = <2>;
983
984 interrupt-controller;
985 #interrupt-cells = <2>;
986 };
987
988 gpio2: gpio2@ff260000 {
989 compatible = "rockchip,gpio-bank";
990 reg = <0x0 0xff260000 0x0 0x100>;
991 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
992 clocks = <&cru PCLK_GPIO2>;
993 gpio-controller;
994 #gpio-cells = <2>;
995
996 interrupt-controller;
997 #interrupt-cells = <2>;
998 };
999
1000 gpio3: gpio3@ff270000 {
1001 compatible = "rockchip,gpio-bank";
1002 reg = <0x0 0xff270000 0x0 0x100>;
1003 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1004 clocks = <&cru PCLK_GPIO3>;
1005 gpio-controller;
1006 #gpio-cells = <2>;
1007
1008 interrupt-controller;
1009 #interrupt-cells = <2>;
1010 };
1011
1012 pcfg_pull_up: pcfg-pull-up {
1013 bias-pull-up;
1014 };
1015
1016 pcfg_pull_down: pcfg-pull-down {
1017 bias-pull-down;
1018 };
1019
1020 pcfg_pull_none: pcfg-pull-none {
1021 bias-disable;
1022 };
1023
1024 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
1025 bias-disable;
1026 drive-strength = <2>;
1027 };
1028
1029 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1030 bias-pull-up;
1031 drive-strength = <2>;
1032 };
1033
1034 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
1035 bias-pull-up;
1036 drive-strength = <4>;
1037 };
1038
1039 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
1040 bias-disable;
1041 drive-strength = <4>;
1042 };
1043
1044 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1045 bias-pull-down;
1046 drive-strength = <4>;
1047 };
1048
1049 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
1050 bias-disable;
1051 drive-strength = <8>;
1052 };
1053
1054 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1055 bias-pull-up;
1056 drive-strength = <8>;
1057 };
1058
1059 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1060 bias-disable;
1061 drive-strength = <12>;
1062 };
1063
1064 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
1065 bias-pull-up;
1066 drive-strength = <12>;
1067 };
1068
1069 pcfg_pull_none_smt: pcfg-pull-none-smt {
1070 bias-disable;
1071 input-schmitt-enable;
1072 };
1073
1074 pcfg_output_high: pcfg-output-high {
1075 output-high;
1076 };
1077
1078 pcfg_output_low: pcfg-output-low {
1079 output-low;
1080 };
1081
1082 pcfg_input_high: pcfg-input-high {
1083 bias-pull-up;
1084 input-enable;
1085 };
1086
1087 pcfg_input: pcfg-input {
1088 input-enable;
1089 };
1090
1091 i2c0 {
1092 i2c0_xfer: i2c0-xfer {
1093 rockchip,pins =
1094 <0 RK_PB0 1 &pcfg_pull_none_smt>,
1095 <0 RK_PB1 1 &pcfg_pull_none_smt>;
1096 };
1097 };
1098
1099 i2c1 {
1100 i2c1_xfer: i2c1-xfer {
1101 rockchip,pins =
1102 <0 RK_PC2 1 &pcfg_pull_none_smt>,
1103 <0 RK_PC3 1 &pcfg_pull_none_smt>;
1104 };
1105 };
1106
1107 i2c2 {
1108 i2c2_xfer: i2c2-xfer {
1109 rockchip,pins =
1110 <2 RK_PB7 2 &pcfg_pull_none_smt>,
1111 <2 RK_PC0 2 &pcfg_pull_none_smt>;
1112 };
1113 };
1114
1115 i2c3 {
1116 i2c3_xfer: i2c3-xfer {
1117 rockchip,pins =
1118 <1 RK_PB4 4 &pcfg_pull_none_smt>,
1119 <1 RK_PB5 4 &pcfg_pull_none_smt>;
1120 };
1121 };
1122
1123 tsadc {
1124 tsadc_otp_gpio: tsadc-otp-gpio {
1125 rockchip,pins =
1126 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
1127 };
1128
1129 tsadc_otp_out: tsadc-otp-out {
1130 rockchip,pins =
1131 <0 RK_PA6 1 &pcfg_pull_none>;
1132 };
1133 };
1134
1135 uart0 {
1136 uart0_xfer: uart0-xfer {
1137 rockchip,pins =
1138 <0 RK_PB2 1 &pcfg_pull_up>,
1139 <0 RK_PB3 1 &pcfg_pull_up>;
1140 };
1141
1142 uart0_cts: uart0-cts {
1143 rockchip,pins =
1144 <0 RK_PB4 1 &pcfg_pull_none>;
1145 };
1146
1147 uart0_rts: uart0-rts {
1148 rockchip,pins =
1149 <0 RK_PB5 1 &pcfg_pull_none>;
1150 };
1151
1152 uart0_rts_gpio: uart0-rts-gpio {
1153 rockchip,pins =
1154 <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
1155 };
1156 };
1157
1158 uart1 {
1159 uart1_xfer: uart1-xfer {
1160 rockchip,pins =
1161 <1 RK_PC1 1 &pcfg_pull_up>,
1162 <1 RK_PC0 1 &pcfg_pull_up>;
1163 };
1164
1165 uart1_cts: uart1-cts {
1166 rockchip,pins =
1167 <1 RK_PC2 1 &pcfg_pull_none>;
1168 };
1169
1170 uart1_rts: uart1-rts {
1171 rockchip,pins =
1172 <1 RK_PC3 1 &pcfg_pull_none>;
1173 };
1174
1175 uart1_rts_gpio: uart1-rts-gpio {
1176 rockchip,pins =
1177 <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
1178 };
1179 };
1180
1181 uart2-m0 {
1182 uart2m0_xfer: uart2m0-xfer {
1183 rockchip,pins =
1184 <1 RK_PD2 2 &pcfg_pull_up>,
1185 <1 RK_PD3 2 &pcfg_pull_up>;
1186 };
1187 };
1188
1189 uart2-m1 {
1190 uart2m1_xfer: uart2m1-xfer {
1191 rockchip,pins =
1192 <2 RK_PB4 2 &pcfg_pull_up>,
1193 <2 RK_PB6 2 &pcfg_pull_up>;
1194 };
1195 };
1196
1197 uart3-m0 {
1198 uart3m0_xfer: uart3m0-xfer {
1199 rockchip,pins =
1200 <0 RK_PC0 2 &pcfg_pull_up>,
1201 <0 RK_PC1 2 &pcfg_pull_up>;
1202 };
1203
1204 uart3m0_cts: uart3m0-cts {
1205 rockchip,pins =
1206 <0 RK_PC2 2 &pcfg_pull_none>;
1207 };
1208
1209 uart3m0_rts: uart3m0-rts {
1210 rockchip,pins =
1211 <0 RK_PC3 2 &pcfg_pull_none>;
1212 };
1213
1214 uart3m0_rts_gpio: uart3m0-rts-gpio {
1215 rockchip,pins =
1216 <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
1217 };
1218 };
1219
1220 uart3-m1 {
1221 uart3m1_xfer: uart3m1-xfer {
1222 rockchip,pins =
1223 <1 RK_PB6 2 &pcfg_pull_up>,
1224 <1 RK_PB7 2 &pcfg_pull_up>;
1225 };
1226
1227 uart3m1_cts: uart3m1-cts {
1228 rockchip,pins =
1229 <1 RK_PB4 2 &pcfg_pull_none>;
1230 };
1231
1232 uart3m1_rts: uart3m1-rts {
1233 rockchip,pins =
1234 <1 RK_PB5 2 &pcfg_pull_none>;
1235 };
1236
1237 uart3m1_rts_gpio: uart3m1-rts-gpio {
1238 rockchip,pins =
1239 <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
1240 };
1241 };
1242
1243 uart4 {
1244 uart4_xfer: uart4-xfer {
1245 rockchip,pins =
1246 <1 RK_PD4 2 &pcfg_pull_up>,
1247 <1 RK_PD5 2 &pcfg_pull_up>;
1248 };
1249
1250 uart4_cts: uart4-cts {
1251 rockchip,pins =
1252 <1 RK_PD6 2 &pcfg_pull_none>;
1253 };
1254
1255 uart4_rts: uart4-rts {
1256 rockchip,pins =
1257 <1 RK_PD7 2 &pcfg_pull_none>;
1258 };
1259 };
1260
1261 uart5 {
1262 uart5_xfer: uart5-xfer {
1263 rockchip,pins =
1264 <3 RK_PA2 4 &pcfg_pull_up>,
1265 <3 RK_PA1 4 &pcfg_pull_up>;
1266 };
1267
1268 uart5_cts: uart5-cts {
1269 rockchip,pins =
1270 <3 RK_PA3 4 &pcfg_pull_none>;
1271 };
1272
1273 uart5_rts: uart5-rts {
1274 rockchip,pins =
1275 <3 RK_PA5 4 &pcfg_pull_none>;
1276 };
1277 };
1278
1279 spi0 {
1280 spi0_clk: spi0-clk {
1281 rockchip,pins =
1282 <1 RK_PB7 3 &pcfg_pull_up_4ma>;
1283 };
1284
1285 spi0_csn: spi0-csn {
1286 rockchip,pins =
1287 <1 RK_PB6 3 &pcfg_pull_up_4ma>;
1288 };
1289
1290 spi0_miso: spi0-miso {
1291 rockchip,pins =
1292 <1 RK_PB5 3 &pcfg_pull_up_4ma>;
1293 };
1294
1295 spi0_mosi: spi0-mosi {
1296 rockchip,pins =
1297 <1 RK_PB4 3 &pcfg_pull_up_4ma>;
1298 };
1299
1300 spi0_clk_hs: spi0-clk-hs {
1301 rockchip,pins =
1302 <1 RK_PB7 3 &pcfg_pull_up_8ma>;
1303 };
1304
1305 spi0_miso_hs: spi0-miso-hs {
1306 rockchip,pins =
1307 <1 RK_PB5 3 &pcfg_pull_up_8ma>;
1308 };
1309
1310 spi0_mosi_hs: spi0-mosi-hs {
1311 rockchip,pins =
1312 <1 RK_PB4 3 &pcfg_pull_up_8ma>;
1313 };
1314 };
1315
1316 spi1 {
1317 spi1_clk: spi1-clk {
1318 rockchip,pins =
1319 <3 RK_PB7 4 &pcfg_pull_up_4ma>;
1320 };
1321
1322 spi1_csn0: spi1-csn0 {
1323 rockchip,pins =
1324 <3 RK_PB1 4 &pcfg_pull_up_4ma>;
1325 };
1326
1327 spi1_csn1: spi1-csn1 {
1328 rockchip,pins =
1329 <3 RK_PB2 2 &pcfg_pull_up_4ma>;
1330 };
1331
1332 spi1_miso: spi1-miso {
1333 rockchip,pins =
1334 <3 RK_PB6 4 &pcfg_pull_up_4ma>;
1335 };
1336
1337 spi1_mosi: spi1-mosi {
1338 rockchip,pins =
1339 <3 RK_PB4 4 &pcfg_pull_up_4ma>;
1340 };
1341
1342 spi1_clk_hs: spi1-clk-hs {
1343 rockchip,pins =
1344 <3 RK_PB7 4 &pcfg_pull_up_8ma>;
1345 };
1346
1347 spi1_miso_hs: spi1-miso-hs {
1348 rockchip,pins =
1349 <3 RK_PB6 4 &pcfg_pull_up_8ma>;
1350 };
1351
1352 spi1_mosi_hs: spi1-mosi-hs {
1353 rockchip,pins =
1354 <3 RK_PB4 4 &pcfg_pull_up_8ma>;
1355 };
1356 };
1357
1358 pdm {
1359 pdm_clk0m0: pdm-clk0m0 {
1360 rockchip,pins =
1361 <3 RK_PC6 2 &pcfg_pull_none>;
1362 };
1363
1364 pdm_clk0m1: pdm-clk0m1 {
1365 rockchip,pins =
1366 <2 RK_PC6 1 &pcfg_pull_none>;
1367 };
1368
1369 pdm_clk1: pdm-clk1 {
1370 rockchip,pins =
1371 <3 RK_PC7 2 &pcfg_pull_none>;
1372 };
1373
1374 pdm_sdi0m0: pdm-sdi0m0 {
1375 rockchip,pins =
1376 <3 RK_PD3 2 &pcfg_pull_none>;
1377 };
1378
1379 pdm_sdi0m1: pdm-sdi0m1 {
1380 rockchip,pins =
1381 <2 RK_PC5 2 &pcfg_pull_none>;
1382 };
1383
1384 pdm_sdi1: pdm-sdi1 {
1385 rockchip,pins =
1386 <3 RK_PD0 2 &pcfg_pull_none>;
1387 };
1388
1389 pdm_sdi2: pdm-sdi2 {
1390 rockchip,pins =
1391 <3 RK_PD1 2 &pcfg_pull_none>;
1392 };
1393
1394 pdm_sdi3: pdm-sdi3 {
1395 rockchip,pins =
1396 <3 RK_PD2 2 &pcfg_pull_none>;
1397 };
1398
1399 pdm_clk0m0_sleep: pdm-clk0m0-sleep {
1400 rockchip,pins =
1401 <3 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>;
1402 };
1403
1404 pdm_clk0m_sleep1: pdm-clk0m1-sleep {
1405 rockchip,pins =
1406 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>;
1407 };
1408
1409 pdm_clk1_sleep: pdm-clk1-sleep {
1410 rockchip,pins =
1411 <3 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
1412 };
1413
1414 pdm_sdi0m0_sleep: pdm-sdi0m0-sleep {
1415 rockchip,pins =
1416 <3 RK_PD3 RK_FUNC_GPIO &pcfg_input_high>;
1417 };
1418
1419 pdm_sdi0m1_sleep: pdm-sdi0m1-sleep {
1420 rockchip,pins =
1421 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>;
1422 };
1423
1424 pdm_sdi1_sleep: pdm-sdi1-sleep {
1425 rockchip,pins =
1426 <3 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>;
1427 };
1428
1429 pdm_sdi2_sleep: pdm-sdi2-sleep {
1430 rockchip,pins =
1431 <3 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>;
1432 };
1433
1434 pdm_sdi3_sleep: pdm-sdi3-sleep {
1435 rockchip,pins =
1436 <3 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>;
1437 };
1438 };
1439
1440 i2s0 {
1441 i2s0_8ch_mclk: i2s0-8ch-mclk {
1442 rockchip,pins =
1443 <3 RK_PC1 2 &pcfg_pull_none>;
1444 };
1445
1446 i2s0_8ch_sclktx: i2s0-8ch-sclktx {
1447 rockchip,pins =
1448 <3 RK_PC3 2 &pcfg_pull_none>;
1449 };
1450
1451 i2s0_8ch_sclkrx: i2s0-8ch-sclkrx {
1452 rockchip,pins =
1453 <3 RK_PB4 2 &pcfg_pull_none>;
1454 };
1455
1456 i2s0_8ch_lrcktx: i2s0-8ch-lrcktx {
1457 rockchip,pins =
1458 <3 RK_PC2 2 &pcfg_pull_none>;
1459 };
1460
1461 i2s0_8ch_lrckrx: i2s0-8ch-lrckrx {
1462 rockchip,pins =
1463 <3 RK_PB5 2 &pcfg_pull_none>;
1464 };
1465
1466 i2s0_8ch_sdo0: i2s0-8ch-sdo0 {
1467 rockchip,pins =
1468 <3 RK_PC4 2 &pcfg_pull_none>;
1469 };
1470
1471 i2s0_8ch_sdo1: i2s0-8ch-sdo1 {
1472 rockchip,pins =
1473 <3 RK_PC0 2 &pcfg_pull_none>;
1474 };
1475
1476 i2s0_8ch_sdo2: i2s0-8ch-sdo2 {
1477 rockchip,pins =
1478 <3 RK_PB7 2 &pcfg_pull_none>;
1479 };
1480
1481 i2s0_8ch_sdo3: i2s0-8ch-sdo3 {
1482 rockchip,pins =
1483 <3 RK_PB6 2 &pcfg_pull_none>;
1484 };
1485
1486 i2s0_8ch_sdi0: i2s0-8ch-sdi0 {
1487 rockchip,pins =
1488 <3 RK_PC5 2 &pcfg_pull_none>;
1489 };
1490
1491 i2s0_8ch_sdi1: i2s0-8ch-sdi1 {
1492 rockchip,pins =
1493 <3 RK_PB3 2 &pcfg_pull_none>;
1494 };
1495
1496 i2s0_8ch_sdi2: i2s0-8ch-sdi2 {
1497 rockchip,pins =
1498 <3 RK_PB1 2 &pcfg_pull_none>;
1499 };
1500
1501 i2s0_8ch_sdi3: i2s0-8ch-sdi3 {
1502 rockchip,pins =
1503 <3 RK_PB0 2 &pcfg_pull_none>;
1504 };
1505 };
1506
1507 i2s1 {
1508 i2s1_2ch_mclk: i2s1-2ch-mclk {
1509 rockchip,pins =
1510 <2 RK_PC3 1 &pcfg_pull_none>;
1511 };
1512
1513 i2s1_2ch_sclk: i2s1-2ch-sclk {
1514 rockchip,pins =
1515 <2 RK_PC2 1 &pcfg_pull_none>;
1516 };
1517
1518 i2s1_2ch_lrck: i2s1-2ch-lrck {
1519 rockchip,pins =
1520 <2 RK_PC1 1 &pcfg_pull_none>;
1521 };
1522
1523 i2s1_2ch_sdi: i2s1-2ch-sdi {
1524 rockchip,pins =
1525 <2 RK_PC5 1 &pcfg_pull_none>;
1526 };
1527
1528 i2s1_2ch_sdo: i2s1-2ch-sdo {
1529 rockchip,pins =
1530 <2 RK_PC4 1 &pcfg_pull_none>;
1531 };
1532 };
1533
1534 i2s2 {
1535 i2s2_2ch_mclk: i2s2-2ch-mclk {
1536 rockchip,pins =
1537 <3 RK_PA1 2 &pcfg_pull_none>;
1538 };
1539
1540 i2s2_2ch_sclk: i2s2-2ch-sclk {
1541 rockchip,pins =
1542 <3 RK_PA2 2 &pcfg_pull_none>;
1543 };
1544
1545 i2s2_2ch_lrck: i2s2-2ch-lrck {
1546 rockchip,pins =
1547 <3 RK_PA3 2 &pcfg_pull_none>;
1548 };
1549
1550 i2s2_2ch_sdi: i2s2-2ch-sdi {
1551 rockchip,pins =
1552 <3 RK_PA5 2 &pcfg_pull_none>;
1553 };
1554
1555 i2s2_2ch_sdo: i2s2-2ch-sdo {
1556 rockchip,pins =
1557 <3 RK_PA7 2 &pcfg_pull_none>;
1558 };
1559 };
1560
1561 sdmmc {
1562 sdmmc_clk: sdmmc-clk {
1563 rockchip,pins =
1564 <1 RK_PD6 1 &pcfg_pull_none_8ma>;
1565 };
1566
1567 sdmmc_cmd: sdmmc-cmd {
1568 rockchip,pins =
1569 <1 RK_PD7 1 &pcfg_pull_up_8ma>;
1570 };
1571
1572 sdmmc_det: sdmmc-det {
1573 rockchip,pins =
1574 <0 RK_PA3 1 &pcfg_pull_up_8ma>;
1575 };
1576
1577 sdmmc_bus1: sdmmc-bus1 {
1578 rockchip,pins =
1579 <1 RK_PD2 1 &pcfg_pull_up_8ma>;
1580 };
1581
1582 sdmmc_bus4: sdmmc-bus4 {
1583 rockchip,pins =
1584 <1 RK_PD2 1 &pcfg_pull_up_8ma>,
1585 <1 RK_PD3 1 &pcfg_pull_up_8ma>,
1586 <1 RK_PD4 1 &pcfg_pull_up_8ma>,
1587 <1 RK_PD5 1 &pcfg_pull_up_8ma>;
1588 };
1589
1590 sdmmc_gpio: sdmmc-gpio {
1591 rockchip,pins =
1592 <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1593 <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1594 <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1595 <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1596 <1 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1597 <1 RK_PD7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1598 };
1599 };
1600
1601 sdio {
1602 sdio_clk: sdio-clk {
1603 rockchip,pins =
1604 <1 RK_PC5 1 &pcfg_pull_none>;
1605 };
1606
1607 sdio_cmd: sdio-cmd {
1608 rockchip,pins =
1609 <1 RK_PC4 1 &pcfg_pull_up>;
1610 };
1611
1612 sdio_bus4: sdio-bus4 {
1613 rockchip,pins =
1614 <1 RK_PC6 1 &pcfg_pull_up>,
1615 <1 RK_PC7 1 &pcfg_pull_up>,
1616 <1 RK_PD0 1 &pcfg_pull_up>,
1617 <1 RK_PD1 1 &pcfg_pull_up>;
1618 };
1619
1620 sdio_gpio: sdio-gpio {
1621 rockchip,pins =
1622 <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>,
1623 <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>,
1624 <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>,
1625 <1 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>,
1626 <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>,
1627 <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
1628 };
1629 };
1630
1631 emmc {
1632 emmc_clk: emmc-clk {
1633 rockchip,pins =
1634 <1 RK_PB1 2 &pcfg_pull_none_8ma>;
1635 };
1636
1637 emmc_cmd: emmc-cmd {
1638 rockchip,pins =
1639 <1 RK_PB2 2 &pcfg_pull_up_8ma>;
1640 };
1641
1642 emmc_pwren: emmc-pwren {
1643 rockchip,pins =
1644 <1 RK_PB0 2 &pcfg_pull_none>;
1645 };
1646
1647 emmc_rstnout: emmc-rstnout {
1648 rockchip,pins =
1649 <1 RK_PB3 2 &pcfg_pull_none>;
1650 };
1651
1652 emmc_bus1: emmc-bus1 {
1653 rockchip,pins =
1654 <1 RK_PA0 2 &pcfg_pull_up_8ma>;
1655 };
1656
1657 emmc_bus4: emmc-bus4 {
1658 rockchip,pins =
1659 <1 RK_PA0 2 &pcfg_pull_up_8ma>,
1660 <1 RK_PA1 2 &pcfg_pull_up_8ma>,
1661 <1 RK_PA2 2 &pcfg_pull_up_8ma>,
1662 <1 RK_PA3 2 &pcfg_pull_up_8ma>;
1663 };
1664
1665 emmc_bus8: emmc-bus8 {
1666 rockchip,pins =
1667 <1 RK_PA0 2 &pcfg_pull_up_8ma>,
1668 <1 RK_PA1 2 &pcfg_pull_up_8ma>,
1669 <1 RK_PA2 2 &pcfg_pull_up_8ma>,
1670 <1 RK_PA3 2 &pcfg_pull_up_8ma>,
1671 <1 RK_PA4 2 &pcfg_pull_up_8ma>,
1672 <1 RK_PA5 2 &pcfg_pull_up_8ma>,
1673 <1 RK_PA6 2 &pcfg_pull_up_8ma>,
1674 <1 RK_PA7 2 &pcfg_pull_up_8ma>;
1675 };
1676 };
1677
1678 flash {
1679 flash_cs0: flash-cs0 {
1680 rockchip,pins =
1681 <1 RK_PB0 1 &pcfg_pull_none>;
1682 };
1683
1684 flash_rdy: flash-rdy {
1685 rockchip,pins =
1686 <1 RK_PB1 1 &pcfg_pull_none>;
1687 };
1688
1689 flash_dqs: flash-dqs {
1690 rockchip,pins =
1691 <1 RK_PB2 1 &pcfg_pull_none>;
1692 };
1693
1694 flash_ale: flash-ale {
1695 rockchip,pins =
1696 <1 RK_PB3 1 &pcfg_pull_none>;
1697 };
1698
1699 flash_cle: flash-cle {
1700 rockchip,pins =
1701 <1 RK_PB4 1 &pcfg_pull_none>;
1702 };
1703
1704 flash_wrn: flash-wrn {
1705 rockchip,pins =
1706 <1 RK_PB5 1 &pcfg_pull_none>;
1707 };
1708
1709 flash_csl: flash-csl {
1710 rockchip,pins =
1711 <1 RK_PB6 1 &pcfg_pull_none>;
1712 };
1713
1714 flash_rdn: flash-rdn {
1715 rockchip,pins =
1716 <1 RK_PB7 1 &pcfg_pull_none>;
1717 };
1718
1719 flash_bus8: flash-bus8 {
1720 rockchip,pins =
1721 <1 RK_PA0 1 &pcfg_pull_up_12ma>,
1722 <1 RK_PA1 1 &pcfg_pull_up_12ma>,
1723 <1 RK_PA2 1 &pcfg_pull_up_12ma>,
1724 <1 RK_PA3 1 &pcfg_pull_up_12ma>,
1725 <1 RK_PA4 1 &pcfg_pull_up_12ma>,
1726 <1 RK_PA5 1 &pcfg_pull_up_12ma>,
1727 <1 RK_PA6 1 &pcfg_pull_up_12ma>,
1728 <1 RK_PA7 1 &pcfg_pull_up_12ma>;
1729 };
1730 };
1731
1732 lcdc {
1733 lcdc_rgb_dclk_pin: lcdc-rgb-dclk-pin {
1734 rockchip,pins =
1735 <3 RK_PA0 1 &pcfg_pull_none_12ma>;
1736 };
1737
1738 lcdc_rgb_m0_hsync_pin: lcdc-rgb-m0-hsync-pin {
1739 rockchip,pins =
1740 <3 RK_PA1 1 &pcfg_pull_none_12ma>;
1741 };
1742
1743 lcdc_rgb_m0_vsync_pin: lcdc-rgb-m0-vsync-pin {
1744 rockchip,pins =
1745 <3 RK_PA2 1 &pcfg_pull_none_12ma>;
1746 };
1747
1748 lcdc_rgb_m0_den_pin: lcdc-rgb-m0-den-pin {
1749 rockchip,pins =
1750 <3 RK_PA3 1 &pcfg_pull_none_12ma>;
1751 };
1752
1753 lcdc_rgb888_m0_data_pins: lcdc-rgb888-m0-data-pins {
1754 rockchip,pins =
1755 <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */
1756 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
1757 <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */
1758 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
1759 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
1760 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
1761 <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */
1762 <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */
1763 <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */
1764 <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */
1765 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
1766 <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */
1767 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
1768 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
1769 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
1770 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
1771 <3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */
1772 <3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */
1773 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
1774 <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */
1775 <3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */
1776 <3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */
1777 <3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */
1778 <3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */
1779 };
1780
1781 lcdc_rgb666_m0_data_pins: lcdc-rgb666-m0-data-pins {
1782 rockchip,pins =
1783 <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */
1784 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
1785 <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */
1786 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
1787 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
1788 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
1789 <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */
1790 <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */
1791 <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */
1792 <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */
1793 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
1794 <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */
1795 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
1796 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
1797 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
1798 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
1799 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
1800 <3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */
1801 };
1802
1803 lcdc_rgb565_m0_data_pins: lcdc-rgb565-m0-data-pins {
1804 rockchip,pins =
1805 <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */
1806 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
1807 <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */
1808 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
1809 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
1810 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
1811 <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */
1812 <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */
1813 <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */
1814 <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */
1815 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
1816 <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */
1817 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
1818 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
1819 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
1820 <3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */
1821 };
1822
1823 lcdc_rgb888_m1_data_pins: lcdc-rgb888-m1-data-pins {
1824 rockchip,pins =
1825 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
1826 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
1827 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
1828 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
1829 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
1830 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
1831 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
1832 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
1833 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
1834 <3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */
1835 <3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */
1836 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
1837 <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */
1838 <3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */
1839 <3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */
1840 <3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */
1841 <3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */
1842 };
1843
1844 lcdc_rgb666_m1_data_pins: lcdc-rgb666-m1-data-pins {
1845 rockchip,pins =
1846 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
1847 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
1848 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
1849 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
1850 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
1851 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
1852 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
1853 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
1854 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
1855 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
1856 <3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */
1857 };
1858
1859 lcdc_rgb565_m1_data_pins: lcdc-rgb565-m1-data-pins {
1860 rockchip,pins =
1861 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
1862 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
1863 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
1864 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
1865 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
1866 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
1867 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
1868 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
1869 <3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */
1870 };
1871 };
1872
1873 pwm0 {
1874 pwm0_pin: pwm0-pin {
1875 rockchip,pins =
1876 <0 RK_PB7 1 &pcfg_pull_none>;
1877 };
1878 };
1879
1880 pwm1 {
1881 pwm1_pin: pwm1-pin {
1882 rockchip,pins =
1883 <0 RK_PC0 1 &pcfg_pull_none>;
1884 };
1885 };
1886
1887 pwm2 {
1888 pwm2_pin: pwm2-pin {
1889 rockchip,pins =
1890 <2 RK_PB5 1 &pcfg_pull_none>;
1891 };
1892 };
1893
1894 pwm3 {
1895 pwm3_pin: pwm3-pin {
1896 rockchip,pins =
1897 <0 RK_PC1 1 &pcfg_pull_none>;
1898 };
1899 };
1900
1901 pwm4 {
1902 pwm4_pin: pwm4-pin {
1903 rockchip,pins =
1904 <3 RK_PC2 3 &pcfg_pull_none>;
1905 };
1906 };
1907
1908 pwm5 {
1909 pwm5_pin: pwm5-pin {
1910 rockchip,pins =
1911 <3 RK_PC3 3 &pcfg_pull_none>;
1912 };
1913 };
1914
1915 pwm6 {
1916 pwm6_pin: pwm6-pin {
1917 rockchip,pins =
1918 <3 RK_PC4 3 &pcfg_pull_none>;
1919 };
1920 };
1921
1922 pwm7 {
1923 pwm7_pin: pwm7-pin {
1924 rockchip,pins =
1925 <3 RK_PC5 3 &pcfg_pull_none>;
1926 };
1927 };
1928
1929 gmac {
1930 rmii_pins: rmii-pins {
1931 rockchip,pins =
1932 <2 RK_PA0 2 &pcfg_pull_none_12ma>, /* mac_txen */
1933 <2 RK_PA1 2 &pcfg_pull_none_12ma>, /* mac_txd1 */
1934 <2 RK_PA2 2 &pcfg_pull_none_12ma>, /* mac_txd0 */
1935 <2 RK_PA3 2 &pcfg_pull_none>, /* mac_rxd0 */
1936 <2 RK_PA4 2 &pcfg_pull_none>, /* mac_rxd1 */
1937 <2 RK_PA5 2 &pcfg_pull_none>, /* mac_rxer */
1938 <2 RK_PA6 2 &pcfg_pull_none>, /* mac_rxdv */
1939 <2 RK_PA7 2 &pcfg_pull_none>, /* mac_mdio */
1940 <2 RK_PB1 2 &pcfg_pull_none>; /* mac_mdc */
1941 };
1942
1943 mac_refclk_12ma: mac-refclk-12ma {
1944 rockchip,pins =
1945 <2 RK_PB2 2 &pcfg_pull_none_12ma>;
1946 };
1947
1948 mac_refclk: mac-refclk {
1949 rockchip,pins =
1950 <2 RK_PB2 2 &pcfg_pull_none>;
1951 };
1952 };
1953
1954 cif-m0 {
1955 cif_clkout_m0: cif-clkout-m0 {
1956 rockchip,pins =
1957 <2 RK_PB3 1 &pcfg_pull_none>;
1958 };
1959
1960 dvp_d2d9_m0: dvp-d2d9-m0 {
1961 rockchip,pins =
1962 <2 RK_PA0 1 &pcfg_pull_none>, /* cif_data2 */
1963 <2 RK_PA1 1 &pcfg_pull_none>, /* cif_data3 */
1964 <2 RK_PA2 1 &pcfg_pull_none>, /* cif_data4 */
1965 <2 RK_PA3 1 &pcfg_pull_none>, /* cif_data5 */
1966 <2 RK_PA4 1 &pcfg_pull_none>, /* cif_data6 */
1967 <2 RK_PA5 1 &pcfg_pull_none>, /* cif_data7 */
1968 <2 RK_PA6 1 &pcfg_pull_none>, /* cif_data8 */
1969 <2 RK_PA7 1 &pcfg_pull_none>, /* cif_data9 */
1970 <2 RK_PB0 1 &pcfg_pull_none>, /* cif_sync */
1971 <2 RK_PB1 1 &pcfg_pull_none>, /* cif_href */
1972 <2 RK_PB2 1 &pcfg_pull_none>, /* cif_clkin */
1973 <2 RK_PB3 1 &pcfg_pull_none>; /* cif_clkout */
1974 };
1975
1976 dvp_d0d1_m0: dvp-d0d1-m0 {
1977 rockchip,pins =
1978 <2 RK_PB4 1 &pcfg_pull_none>, /* cif_data0 */
1979 <2 RK_PB6 1 &pcfg_pull_none>; /* cif_data1 */
1980 };
1981
1982 dvp_d10d11_m0:d10-d11-m0 {
1983 rockchip,pins =
1984 <2 RK_PB7 1 &pcfg_pull_none>, /* cif_data10 */
1985 <2 RK_PC0 1 &pcfg_pull_none>; /* cif_data11 */
1986 };
1987 };
1988
1989 cif-m1 {
1990 cif_clkout_m1: cif-clkout-m1 {
1991 rockchip,pins =
1992 <3 RK_PD0 3 &pcfg_pull_none>;
1993 };
1994
1995 dvp_d2d9_m1: dvp-d2d9-m1 {
1996 rockchip,pins =
1997 <3 RK_PA3 3 &pcfg_pull_none>, /* cif_data2 */
1998 <3 RK_PA5 3 &pcfg_pull_none>, /* cif_data3 */
1999 <3 RK_PA7 3 &pcfg_pull_none>, /* cif_data4 */
2000 <3 RK_PB0 3 &pcfg_pull_none>, /* cif_data5 */
2001 <3 RK_PB1 3 &pcfg_pull_none>, /* cif_data6 */
2002 <3 RK_PB4 3 &pcfg_pull_none>, /* cif_data7 */
2003 <3 RK_PB6 3 &pcfg_pull_none>, /* cif_data8 */
2004 <3 RK_PB7 3 &pcfg_pull_none>, /* cif_data9 */
2005 <3 RK_PD1 3 &pcfg_pull_none>, /* cif_sync */
2006 <3 RK_PD2 3 &pcfg_pull_none>, /* cif_href */
2007 <3 RK_PD3 3 &pcfg_pull_none>, /* cif_clkin */
2008 <3 RK_PD0 3 &pcfg_pull_none>; /* cif_clkout */
2009 };
2010
2011 dvp_d0d1_m1: dvp-d0d1-m1 {
2012 rockchip,pins =
2013 <3 RK_PA1 3 &pcfg_pull_none>, /* cif_data0 */
2014 <3 RK_PA2 3 &pcfg_pull_none>; /* cif_data1 */
2015 };
2016
2017 dvp_d10d11_m1:d10-d11-m1 {
2018 rockchip,pins =
2019 <3 RK_PC6 3 &pcfg_pull_none>, /* cif_data10 */
2020 <3 RK_PC7 3 &pcfg_pull_none>; /* cif_data11 */
2021 };
2022 };
2023
2024 isp {
2025 isp_prelight: isp-prelight {
2026 rockchip,pins =
2027 <3 RK_PD1 4 &pcfg_pull_none>;
2028 };
2029 };
2030 };
2031};
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
index 246c317f6a68..99d0d9912950 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
@@ -41,6 +41,19 @@
41 vin-supply = <&vcc_io>; 41 vin-supply = <&vcc_io>;
42 }; 42 };
43 43
44 vcc_sdio: sdmmcio-regulator {
45 compatible = "regulator-gpio";
46 gpios = <&grf_gpio 0 GPIO_ACTIVE_HIGH>;
47 states = <1800000 0x1
48 3300000 0x0>;
49 regulator-name = "vcc_sdio";
50 regulator-type = "voltage";
51 regulator-min-microvolt = <1800000>;
52 regulator-max-microvolt = <3300000>;
53 regulator-always-on;
54 vin-supply = <&vcc_sys>;
55 };
56
44 vcc_host1_5v: vcc_otg_5v: vcc-host1-5v-regulator { 57 vcc_host1_5v: vcc_otg_5v: vcc-host1-5v-regulator {
45 compatible = "regulator-fixed"; 58 compatible = "regulator-fixed";
46 enable-active-high; 59 enable-active-high;
@@ -208,6 +221,18 @@
208 }; 221 };
209}; 222};
210 223
224&io_domains {
225 status = "okay";
226
227 vccio1-supply = <&vcc_io>;
228 vccio2-supply = <&vcc18_emmc>;
229 vccio3-supply = <&vcc_sdio>;
230 vccio4-supply = <&vcc_18>;
231 vccio5-supply = <&vcc_io>;
232 vccio6-supply = <&vcc_io>;
233 pmuio-supply = <&vcc_io>;
234};
235
211&pinctrl { 236&pinctrl {
212 pmic { 237 pmic {
213 pmic_int_l: pmic-int-l { 238 pmic_int_l: pmic-int-l {
@@ -230,7 +255,12 @@
230 max-frequency = <150000000>; 255 max-frequency = <150000000>;
231 pinctrl-names = "default"; 256 pinctrl-names = "default";
232 pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>; 257 pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
258 sd-uhs-sdr12;
259 sd-uhs-sdr25;
260 sd-uhs-sdr50;
261 sd-uhs-sdr104;
233 vmmc-supply = <&vcc_sd>; 262 vmmc-supply = <&vcc_sd>;
263 vqmmc-supply = <&vcc_sdio>;
234 status = "okay"; 264 status = "okay";
235}; 265};
236 266
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts
index 5272e887a434..5852061e497b 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts
@@ -46,7 +46,7 @@
46 vcc_host1_5v: vcc_otg_5v: vcc-host1-5v-regulator { 46 vcc_host1_5v: vcc_otg_5v: vcc-host1-5v-regulator {
47 compatible = "regulator-fixed"; 47 compatible = "regulator-fixed";
48 enable-active-high; 48 enable-active-high;
49 gpio = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; 49 gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
50 pinctrl-names = "default"; 50 pinctrl-names = "default";
51 pinctrl-0 = <&usb20_host_drv>; 51 pinctrl-0 = <&usb20_host_drv>;
52 regulator-name = "vcc_host1_5v"; 52 regulator-name = "vcc_host1_5v";
@@ -238,7 +238,7 @@
238 238
239 usb2 { 239 usb2 {
240 usb20_host_drv: usb20-host-drv { 240 usb20_host_drv: usb20-host-drv {
241 rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; 241 rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
242 }; 242 };
243 }; 243 };
244 244
diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
index 3f5a2944300f..d3ef6566325e 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -249,6 +249,12 @@
249 status = "disabled"; 249 status = "disabled";
250 }; 250 };
251 251
252 grf_gpio: grf-gpio {
253 compatible = "rockchip,rk3328-grf-gpio";
254 gpio-controller;
255 #gpio-cells = <2>;
256 };
257
252 power: power-controller { 258 power: power-controller {
253 compatible = "rockchip,rk3328-power-controller"; 259 compatible = "rockchip,rk3328-power-controller";
254 #power-domain-cells = <1>; 260 #power-domain-cells = <1>;
@@ -274,7 +280,6 @@
274 mode-bootloader = <BOOT_FASTBOOT>; 280 mode-bootloader = <BOOT_FASTBOOT>;
275 mode-loader = <BOOT_BL_DOWNLOAD>; 281 mode-loader = <BOOT_BL_DOWNLOAD>;
276 }; 282 };
277
278 }; 283 };
279 284
280 uart0: serial@ff110000 { 285 uart0: serial@ff110000 {
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts b/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts
index 38336ab57cc4..c706db0ee9ec 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts
@@ -622,6 +622,12 @@
622 }; 622 };
623 }; 623 };
624 624
625 wifi {
626 wifi_host_wake_l: wifi-host-wake-l {
627 rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
628 };
629 };
630
625 leds { 631 leds {
626 work_led_gpio: work_led-gpio { 632 work_led_gpio: work_led-gpio {
627 rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; 633 rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
@@ -646,6 +652,36 @@
646 status = "okay"; 652 status = "okay";
647}; 653};
648 654
655&sdio0 {
656 /* WiFi & BT combo module Ampak AP6356S */
657 bus-width = <4>;
658 cap-sdio-irq;
659 cap-sd-highspeed;
660 keep-power-in-suspend;
661 mmc-pwrseq = <&sdio_pwrseq>;
662 non-removable;
663 num-slots = <1>;
664 pinctrl-names = "default";
665 pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
666 sd-uhs-sdr104;
667
668 /* Power supply */
669 vqmmc-supply = &vcc1v8_s3; /* IO line */
670 vmmc-supply = &vcc_sdio; /* card's power */
671
672 status = "okay";
673
674 brcmf: wifi@1 {
675 compatible = "brcm,bcm4329-fmac";
676 interrupt-parent = <&gpio0>;
677 interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>;
678 interrupt-names = "host-wake";
679 brcm,drive-strength = <5>;
680 pinctrl-names = "default";
681 pinctrl-0 = <&wifi_host_wake_l>;
682 };
683};
684
649&sdmmc { 685&sdmmc {
650 bus-width = <4>; 686 bus-width = <4>;
651 cap-mmc-highspeed; 687 cap-mmc-highspeed;
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dts b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dts
new file mode 100644
index 000000000000..19f7732d728c
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dts
@@ -0,0 +1,680 @@
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2017 T-Chip Intelligent Technology Co., Ltd
4 */
5
6/dts-v1/;
7#include <dt-bindings/pwm/pwm.h>
8#include "rk3399.dtsi"
9#include "rk3399-opp.dtsi"
10
11/ {
12 model = "Firefly ROC-RK3399-PC Board";
13 compatible = "firefly,roc-rk3399-pc", "rockchip,rk3399";
14
15 chosen {
16 stdout-path = "serial2:1500000n8";
17 };
18
19 backlight: backlight {
20 compatible = "pwm-backlight";
21 pwms = <&pwm0 0 25000 0>;
22 };
23
24 clkin_gmac: external-gmac-clock {
25 compatible = "fixed-clock";
26 clock-frequency = <125000000>;
27 clock-output-names = "clkin_gmac";
28 #clock-cells = <0>;
29 };
30
31 sdio_pwrseq: sdio-pwrseq {
32 compatible = "mmc-pwrseq-simple";
33 clocks = <&rk808 1>;
34 clock-names = "ext_clock";
35 pinctrl-names = "default";
36 pinctrl-0 = <&wifi_enable_h>;
37
38 /*
39 * On the module itself this is one of these (depending
40 * on the actual card populated):
41 * - SDIO_RESET_L_WL_REG_ON
42 * - PDN (power down when low)
43 */
44 reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
45 };
46
47 vcc_vbus_typec0: vcc-vbus-typec0 {
48 compatible = "regulator-fixed";
49 regulator-name = "vcc_vbus_typec0";
50 regulator-always-on;
51 regulator-boot-on;
52 regulator-min-microvolt = <5000000>;
53 regulator-max-microvolt = <5000000>;
54 };
55
56 /*
57 * should be placed inside mp8859, but not until mp8859 has
58 * its own dt-binding.
59 */
60 vcc12v_sys: mp8859-dcdc1 {
61 compatible = "regulator-fixed";
62 regulator-name = "vcc12v_sys";
63 regulator-always-on;
64 regulator-boot-on;
65 regulator-min-microvolt = <12000000>;
66 regulator-max-microvolt = <12000000>;
67 vin-supply = <&vcc_vbus_typec0>;
68 };
69
70 /* switched by pmic_sleep */
71 vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
72 compatible = "regulator-fixed";
73 regulator-name = "vcc1v8_s3";
74 regulator-always-on;
75 regulator-boot-on;
76 regulator-min-microvolt = <1800000>;
77 regulator-max-microvolt = <1800000>;
78 vin-supply = <&vcc_1v8>;
79 };
80
81 vcc3v3_sys: vcc3v3-sys {
82 compatible = "regulator-fixed";
83 regulator-name = "vcc3v3_sys";
84 regulator-always-on;
85 regulator-boot-on;
86 regulator-min-microvolt = <3300000>;
87 regulator-max-microvolt = <3300000>;
88 vin-supply = <&vcc12v_sys>;
89 };
90
91 /* Actually 3 regulators (host0, 1, 2) controlled by the same gpio */
92 vcc5v0_host: vcc5v0-host-regulator {
93 compatible = "regulator-fixed";
94 enable-active-high;
95 gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>;
96 pinctrl-names = "default";
97 pinctrl-0 = <&vcc5v0_host_en &hub_rst>;
98 regulator-name = "vcc5v0_host";
99 regulator-always-on;
100 vin-supply = <&vcc_sys>;
101 };
102
103 vcc_vbus_typec1: vcc-vbus-typec1 {
104 compatible = "regulator-fixed";
105 enable-active-high;
106 gpio = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>;
107 pinctrl-names = "default";
108 pinctrl-0 = <&vcc_vbus_typec1_en>;
109 regulator-name = "vcc_vbus_typec1";
110 regulator-always-on;
111 vin-supply = <&vcc_sys>;
112 };
113
114 vcc_sys: vcc-sys {
115 compatible = "regulator-fixed";
116 regulator-name = "vcc_sys";
117 regulator-always-on;
118 regulator-boot-on;
119 regulator-min-microvolt = <5000000>;
120 regulator-max-microvolt = <5000000>;
121 vin-supply = <&vcc12v_sys>;
122 };
123
124 vdd_log: vdd-log {
125 compatible = "pwm-regulator";
126 pwms = <&pwm2 0 25000 1>;
127 regulator-name = "vdd_log";
128 regulator-always-on;
129 regulator-boot-on;
130 regulator-min-microvolt = <800000>;
131 regulator-max-microvolt = <1400000>;
132 vin-supply = <&vcc3v3_sys>;
133 };
134};
135
136&cpu_l0 {
137 cpu-supply = <&vdd_cpu_l>;
138};
139
140&cpu_l1 {
141 cpu-supply = <&vdd_cpu_l>;
142};
143
144&cpu_l2 {
145 cpu-supply = <&vdd_cpu_l>;
146};
147
148&cpu_l3 {
149 cpu-supply = <&vdd_cpu_l>;
150};
151
152&cpu_b0 {
153 cpu-supply = <&vdd_cpu_b>;
154};
155
156&cpu_b1 {
157 cpu-supply = <&vdd_cpu_b>;
158};
159
160&emmc_phy {
161 status = "okay";
162};
163
164&gmac {
165 assigned-clocks = <&cru SCLK_RMII_SRC>;
166 assigned-clock-parents = <&clkin_gmac>;
167 clock_in_out = "input";
168 phy-supply = <&vcc_lan>;
169 phy-mode = "rgmii";
170 pinctrl-names = "default";
171 pinctrl-0 = <&rgmii_pins>;
172 snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
173 snps,reset-active-low;
174 snps,reset-delays-us = <0 10000 50000>;
175 tx_delay = <0x28>;
176 rx_delay = <0x11>;
177 status = "okay";
178};
179
180&hdmi {
181 ddc-i2c-bus = <&i2c3>;
182 pinctrl-names = "default";
183 pinctrl-0 = <&hdmi_cec>;
184 status = "okay";
185};
186
187&i2c0 {
188 clock-frequency = <400000>;
189 i2c-scl-rising-time-ns = <168>;
190 i2c-scl-falling-time-ns = <4>;
191 status = "okay";
192
193 rk808: pmic@1b {
194 compatible = "rockchip,rk808";
195 reg = <0x1b>;
196 interrupt-parent = <&gpio1>;
197 interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
198 #clock-cells = <1>;
199 clock-output-names = "xin32k", "rk808-clkout2";
200 pinctrl-names = "default";
201 pinctrl-0 = <&pmic_int_l>;
202 rockchip,system-power-controller;
203 wakeup-source;
204
205 vcc1-supply = <&vcc3v3_sys>;
206 vcc2-supply = <&vcc3v3_sys>;
207 vcc3-supply = <&vcc3v3_sys>;
208 vcc4-supply = <&vcc3v3_sys>;
209 vcc6-supply = <&vcc3v3_sys>;
210 vcc7-supply = <&vcc3v3_sys>;
211 vcc8-supply = <&vcc3v3_sys>;
212 vcc9-supply = <&vcc3v3_sys>;
213 vcc10-supply = <&vcc3v3_sys>;
214 vcc11-supply = <&vcc3v3_sys>;
215 vcc12-supply = <&vcc3v3_sys>;
216 vddio-supply = <&vcc1v8_pmu>;
217
218 regulators {
219 vdd_center: DCDC_REG1 {
220 regulator-name = "vdd_center";
221 regulator-always-on;
222 regulator-boot-on;
223 regulator-min-microvolt = <750000>;
224 regulator-max-microvolt = <1350000>;
225 regulator-ramp-delay = <6001>;
226 regulator-state-mem {
227 regulator-off-in-suspend;
228 };
229 };
230
231 vdd_cpu_l: DCDC_REG2 {
232 regulator-name = "vdd_cpu_l";
233 regulator-always-on;
234 regulator-boot-on;
235 regulator-min-microvolt = <750000>;
236 regulator-max-microvolt = <1350000>;
237 regulator-ramp-delay = <6001>;
238 regulator-state-mem {
239 regulator-off-in-suspend;
240 };
241 };
242
243 vcc_ddr: DCDC_REG3 {
244 regulator-name = "vcc_ddr";
245 regulator-always-on;
246 regulator-boot-on;
247 regulator-state-mem {
248 regulator-on-in-suspend;
249 };
250 };
251
252 vcc_1v8: DCDC_REG4 {
253 regulator-name = "vcc_1v8";
254 regulator-always-on;
255 regulator-boot-on;
256 regulator-min-microvolt = <1800000>;
257 regulator-max-microvolt = <1800000>;
258 regulator-state-mem {
259 regulator-on-in-suspend;
260 regulator-suspend-microvolt = <1800000>;
261 };
262 };
263
264 vcca1v8_codec: LDO_REG1 {
265 regulator-name = "vcca1v8_codec";
266 regulator-always-on;
267 regulator-boot-on;
268 regulator-min-microvolt = <1800000>;
269 regulator-max-microvolt = <1800000>;
270 regulator-state-mem {
271 regulator-off-in-suspend;
272 };
273 };
274
275 vcc1v8_hdmi: LDO_REG2 {
276 regulator-name = "vcc1v8_hdmi";
277 regulator-always-on;
278 regulator-boot-on;
279 regulator-min-microvolt = <1800000>;
280 regulator-max-microvolt = <1800000>;
281 regulator-state-mem {
282 regulator-off-in-suspend;
283 };
284 };
285
286 vcc1v8_pmu: LDO_REG3 {
287 regulator-name = "vcc1v8_pmu";
288 regulator-always-on;
289 regulator-boot-on;
290 regulator-min-microvolt = <1800000>;
291 regulator-max-microvolt = <1800000>;
292 regulator-state-mem {
293 regulator-on-in-suspend;
294 regulator-suspend-microvolt = <1800000>;
295 };
296 };
297
298 vcc_sdio: LDO_REG4 {
299 regulator-name = "vcc_sdio";
300 regulator-always-on;
301 regulator-boot-on;
302 regulator-min-microvolt = <1800000>;
303 regulator-max-microvolt = <3000000>;
304 regulator-state-mem {
305 regulator-on-in-suspend;
306 regulator-suspend-microvolt = <3000000>;
307 };
308 };
309
310 vcca3v0_codec: LDO_REG5 {
311 regulator-name = "vcca3v0_codec";
312 regulator-always-on;
313 regulator-boot-on;
314 regulator-min-microvolt = <3000000>;
315 regulator-max-microvolt = <3000000>;
316 regulator-state-mem {
317 regulator-off-in-suspend;
318 };
319 };
320
321 vcc_1v5: LDO_REG6 {
322 regulator-name = "vcc_1v5";
323 regulator-always-on;
324 regulator-boot-on;
325 regulator-min-microvolt = <1500000>;
326 regulator-max-microvolt = <1500000>;
327 regulator-state-mem {
328 regulator-on-in-suspend;
329 regulator-suspend-microvolt = <1500000>;
330 };
331 };
332
333 vcca0v9_hdmi: LDO_REG7 {
334 regulator-name = "vcca0v9_hdmi";
335 regulator-always-on;
336 regulator-boot-on;
337 regulator-min-microvolt = <900000>;
338 regulator-max-microvolt = <900000>;
339 regulator-state-mem {
340 regulator-off-in-suspend;
341 };
342 };
343
344 vcc_3v0: LDO_REG8 {
345 regulator-name = "vcc_3v0";
346 regulator-always-on;
347 regulator-boot-on;
348 regulator-min-microvolt = <3000000>;
349 regulator-max-microvolt = <3000000>;
350 regulator-state-mem {
351 regulator-on-in-suspend;
352 regulator-suspend-microvolt = <3000000>;
353 };
354 };
355
356 vcc3v3_s3: vcc_lan: SWITCH_REG1 {
357 regulator-name = "vcc3v3_s3";
358 regulator-always-on;
359 regulator-boot-on;
360 regulator-state-mem {
361 regulator-off-in-suspend;
362 };
363 };
364
365 vcc3v3_s0: SWITCH_REG2 {
366 regulator-name = "vcc3v3_s0";
367 regulator-always-on;
368 regulator-boot-on;
369 regulator-state-mem {
370 regulator-off-in-suspend;
371 };
372 };
373 };
374 };
375
376 vdd_cpu_b: regulator@40 {
377 compatible = "silergy,syr827";
378 reg = <0x40>;
379 fcs,suspend-voltage-selector = <1>;
380 pinctrl-names = "default";
381 pinctrl-0 = <&vsel1_gpio>;
382 regulator-name = "vdd_cpu_b";
383 regulator-min-microvolt = <712500>;
384 regulator-max-microvolt = <1500000>;
385 regulator-ramp-delay = <1000>;
386 regulator-always-on;
387 regulator-boot-on;
388 vin-supply = <&vcc3v3_sys>;
389
390 regulator-state-mem {
391 regulator-off-in-suspend;
392 };
393 };
394
395 vdd_gpu: regulator@41 {
396 compatible = "silergy,syr828";
397 reg = <0x41>;
398 fcs,suspend-voltage-selector = <1>;
399 pinctrl-names = "default";
400 pinctrl-0 = <&vsel2_gpio>;
401 regulator-name = "vdd_gpu";
402 regulator-min-microvolt = <712500>;
403 regulator-max-microvolt = <1500000>;
404 regulator-ramp-delay = <1000>;
405 regulator-always-on;
406 regulator-boot-on;
407 vin-supply = <&vcc3v3_sys>;
408
409 regulator-state-mem {
410 regulator-off-in-suspend;
411 };
412 };
413};
414
415&i2c1 {
416 i2c-scl-rising-time-ns = <300>;
417 i2c-scl-falling-time-ns = <15>;
418 status = "okay";
419};
420
421&i2c3 {
422 i2c-scl-rising-time-ns = <450>;
423 i2c-scl-falling-time-ns = <15>;
424 status = "okay";
425};
426
427&i2c4 {
428 i2c-scl-rising-time-ns = <600>;
429 i2c-scl-falling-time-ns = <20>;
430 status = "okay";
431
432 fusb1: usb-typec@22 {
433 compatible = "fcs,fusb302";
434 reg = <0x22>;
435 interrupt-parent = <&gpio1>;
436 interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
437 pinctrl-names = "default";
438 pinctrl-0 = <&fusb1_int>;
439 vbus-supply = <&vcc_vbus_typec1>;
440 status = "okay";
441 };
442};
443
444&i2c7 {
445 i2c-scl-rising-time-ns = <600>;
446 i2c-scl-falling-time-ns = <20>;
447 status = "okay";
448
449 fusb0: usb-typec@22 {
450 compatible = "fcs,fusb302";
451 reg = <0x22>;
452 interrupt-parent = <&gpio1>;
453 interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
454 pinctrl-names = "default";
455 pinctrl-0 = <&fusb0_int>;
456 vbus-supply = <&vcc_vbus_typec0>;
457 status = "okay";
458 };
459};
460
461&i2s0 {
462 rockchip,playback-channels = <8>;
463 rockchip,capture-channels = <8>;
464 status = "okay";
465};
466
467&i2s1 {
468 rockchip,playback-channels = <2>;
469 rockchip,capture-channels = <2>;
470 status = "okay";
471};
472
473&i2s2 {
474 status = "okay";
475};
476
477&io_domains {
478 audio-supply = <&vcca1v8_codec>;
479 bt656-supply = <&vcc_3v0>;
480 gpio1830-supply = <&vcc_3v0>;
481 sdmmc-supply = <&vcc_sdio>;
482 status = "okay";
483};
484
485&pmu_io_domains {
486 pmu1830-supply = <&vcc_3v0>;
487 status = "okay";
488};
489
490&pinctrl {
491 lcd-panel {
492 lcd_panel_reset: lcd-panel-reset {
493 rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>;
494 };
495 };
496
497 pmic {
498 vsel1_gpio: vsel1-gpio {
499 rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
500 };
501
502 vsel2_gpio: vsel2-gpio {
503 rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
504 };
505 };
506
507 sdio-pwrseq {
508 wifi_enable_h: wifi-enable-h {
509 rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
510 };
511 };
512
513 pmic {
514 pmic_int_l: pmic-int-l {
515 rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
516 };
517 };
518
519 usb2 {
520 vcc5v0_host_en: vcc5v0-host-en {
521 rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
522 };
523
524 hub_rst: hub-rst {
525 rockchip,pins = <2 RK_PA4 RK_FUNC_GPIO &pcfg_output_high>;
526 };
527 };
528
529 usb-typec {
530 vcc_vbus_typec1_en: vcc-vbus-typec1-en {
531 rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
532 };
533 };
534
535 fusb30x {
536 fusb0_int: fusb0-int {
537 rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
538 };
539
540 fusb1_int: fusb1-int {
541 rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>;
542 };
543 };
544};
545
546&pwm0 {
547 status = "okay";
548};
549
550&pwm2 {
551 status = "okay";
552};
553
554&saradc {
555 vref-supply = <&vcca1v8_s3>;
556 status = "okay";
557};
558
559&sdmmc {
560 bus-width = <4>;
561 cap-mmc-highspeed;
562 cap-sd-highspeed;
563 cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
564 disable-wp;
565 max-frequency = <150000000>;
566 pinctrl-names = "default";
567 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
568 status = "okay";
569};
570
571&sdhci {
572 bus-width = <8>;
573 mmc-hs400-1_8v;
574 mmc-hs400-enhanced-strobe;
575 non-removable;
576 status = "okay";
577};
578
579&tcphy0 {
580 status = "okay";
581};
582
583&tcphy1 {
584 status = "okay";
585};
586
587&tsadc {
588 /* tshut mode 0:CRU 1:GPIO */
589 rockchip,hw-tshut-mode = <1>;
590 /* tshut polarity 0:LOW 1:HIGH */
591 rockchip,hw-tshut-polarity = <1>;
592 status = "okay";
593};
594
595&u2phy0 {
596 status = "okay";
597
598 u2phy0_otg: otg-port {
599 phy-supply = <&vcc_vbus_typec0>;
600 status = "okay";
601 };
602
603 u2phy0_host: host-port {
604 phy-supply = <&vcc5v0_host>;
605 status = "okay";
606 };
607};
608
609&u2phy1 {
610 status = "okay";
611
612 u2phy1_otg: otg-port {
613 phy-supply = <&vcc_vbus_typec1>;
614 status = "okay";
615 };
616
617 u2phy1_host: host-port {
618 phy-supply = <&vcc5v0_host>;
619 status = "okay";
620 };
621};
622
623&uart0 {
624 pinctrl-names = "default";
625 pinctrl-0 = <&uart0_xfer &uart0_cts>;
626 status = "okay";
627};
628
629&uart2 {
630 status = "okay";
631};
632
633&usb_host0_ehci {
634 status = "okay";
635};
636
637&usb_host0_ohci {
638 status = "okay";
639};
640
641&usb_host1_ehci {
642 status = "okay";
643};
644
645&usb_host1_ohci {
646 status = "okay";
647};
648
649&usbdrd3_0 {
650 status = "okay";
651};
652
653&usbdrd_dwc3_0 {
654 status = "okay";
655};
656
657&usbdrd3_1 {
658 status = "okay";
659};
660
661&usbdrd_dwc3_1 {
662 status = "okay";
663 dr_mode = "host";
664};
665
666&vopb {
667 status = "okay";
668};
669
670&vopb_mmu {
671 status = "okay";
672};
673
674&vopl {
675 status = "okay";
676};
677
678&vopl_mmu {
679 status = "okay";
680};
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi
index 36b60791c156..a531cd6c2e83 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi
@@ -103,20 +103,10 @@
103 vin-supply = <&vcc_sys>; 103 vin-supply = <&vcc_sys>;
104 }; 104 };
105 105
106 vcc_sys: vcc-sys {
107 compatible = "regulator-fixed";
108 regulator-name = "vcc_sys";
109 regulator-always-on;
110 regulator-boot-on;
111 regulator-min-microvolt = <5000000>;
112 regulator-max-microvolt = <5000000>;
113 vin-supply = <&dc_12v>;
114 };
115
116 vcc5v0_host: vcc5v0-host-regulator { 106 vcc5v0_host: vcc5v0-host-regulator {
117 compatible = "regulator-fixed"; 107 compatible = "regulator-fixed";
118 enable-active-high; 108 enable-active-high;
119 gpio = <&gpio1 RK_PD1 GPIO_ACTIVE_HIGH>; 109 gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>;
120 pinctrl-names = "default"; 110 pinctrl-names = "default";
121 pinctrl-0 = <&vcc5v0_host_en>; 111 pinctrl-0 = <&vcc5v0_host_en>;
122 regulator-name = "vcc5v0_host"; 112 regulator-name = "vcc5v0_host";
@@ -124,6 +114,26 @@
124 vin-supply = <&vcc_sys>; 114 vin-supply = <&vcc_sys>;
125 }; 115 };
126 116
117 vcc5v0_typec0: vcc5v0-typec0-regulator {
118 compatible = "regulator-fixed";
119 enable-active-high;
120 gpio = <&gpio2 RK_PA0 GPIO_ACTIVE_HIGH>;
121 pinctrl-names = "default";
122 pinctrl-0 = <&vcc5v0_typec0_en>;
123 regulator-name = "vcc5v0_typec0";
124 vin-supply = <&vcc_sys>;
125 };
126
127 vcc_sys: vcc-sys {
128 compatible = "regulator-fixed";
129 regulator-name = "vcc_sys";
130 regulator-always-on;
131 regulator-boot-on;
132 regulator-min-microvolt = <5000000>;
133 regulator-max-microvolt = <5000000>;
134 vin-supply = <&dc_12v>;
135 };
136
127 vdd_log: vdd-log { 137 vdd_log: vdd-log {
128 compatible = "pwm-regulator"; 138 compatible = "pwm-regulator";
129 pwms = <&pwm2 0 25000 1>; 139 pwms = <&pwm2 0 25000 1>;
@@ -208,7 +218,7 @@
208 #clock-cells = <1>; 218 #clock-cells = <1>;
209 clock-output-names = "xin32k", "rk808-clkout2"; 219 clock-output-names = "xin32k", "rk808-clkout2";
210 pinctrl-names = "default"; 220 pinctrl-names = "default";
211 pinctrl-0 = <&pmic_int_l &pmic_dvs2>; 221 pinctrl-0 = <&pmic_int_l>;
212 rockchip,system-power-controller; 222 rockchip,system-power-controller;
213 wakeup-source; 223 wakeup-source;
214 224
@@ -455,11 +465,6 @@
455 <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; 465 <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
456 }; 466 };
457 467
458 pmic_dvs2: pmic-dvs2 {
459 rockchip,pins =
460 <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
461 };
462
463 vsel1_gpio: vsel1-gpio { 468 vsel1_gpio: vsel1-gpio {
464 rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; 469 rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
465 }; 470 };
@@ -474,6 +479,10 @@
474 rockchip,pins = 479 rockchip,pins =
475 <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; 480 <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
476 }; 481 };
482 vcc5v0_typec0_en: vcc5v0-typec0-en {
483 rockchip,pins =
484 <2 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
485 };
477 }; 486 };
478}; 487};
479 488
@@ -531,6 +540,7 @@
531 status = "okay"; 540 status = "okay";
532 541
533 u2phy0_otg: otg-port { 542 u2phy0_otg: otg-port {
543 phy-supply = <&vcc5v0_typec0>;
534 status = "okay"; 544 status = "okay";
535 }; 545 };
536 546
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index c88e603396f6..b426902189c0 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -74,6 +74,7 @@
74 clocks = <&cru ARMCLKL>; 74 clocks = <&cru ARMCLKL>;
75 #cooling-cells = <2>; /* min followed by max */ 75 #cooling-cells = <2>; /* min followed by max */
76 dynamic-power-coefficient = <100>; 76 dynamic-power-coefficient = <100>;
77 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
77 }; 78 };
78 79
79 cpu_l1: cpu@1 { 80 cpu_l1: cpu@1 {
@@ -84,6 +85,7 @@
84 clocks = <&cru ARMCLKL>; 85 clocks = <&cru ARMCLKL>;
85 #cooling-cells = <2>; /* min followed by max */ 86 #cooling-cells = <2>; /* min followed by max */
86 dynamic-power-coefficient = <100>; 87 dynamic-power-coefficient = <100>;
88 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
87 }; 89 };
88 90
89 cpu_l2: cpu@2 { 91 cpu_l2: cpu@2 {
@@ -94,6 +96,7 @@
94 clocks = <&cru ARMCLKL>; 96 clocks = <&cru ARMCLKL>;
95 #cooling-cells = <2>; /* min followed by max */ 97 #cooling-cells = <2>; /* min followed by max */
96 dynamic-power-coefficient = <100>; 98 dynamic-power-coefficient = <100>;
99 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
97 }; 100 };
98 101
99 cpu_l3: cpu@3 { 102 cpu_l3: cpu@3 {
@@ -104,6 +107,7 @@
104 clocks = <&cru ARMCLKL>; 107 clocks = <&cru ARMCLKL>;
105 #cooling-cells = <2>; /* min followed by max */ 108 #cooling-cells = <2>; /* min followed by max */
106 dynamic-power-coefficient = <100>; 109 dynamic-power-coefficient = <100>;
110 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
107 }; 111 };
108 112
109 cpu_b0: cpu@100 { 113 cpu_b0: cpu@100 {
@@ -114,6 +118,7 @@
114 clocks = <&cru ARMCLKB>; 118 clocks = <&cru ARMCLKB>;
115 #cooling-cells = <2>; /* min followed by max */ 119 #cooling-cells = <2>; /* min followed by max */
116 dynamic-power-coefficient = <436>; 120 dynamic-power-coefficient = <436>;
121 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
117 }; 122 };
118 123
119 cpu_b1: cpu@101 { 124 cpu_b1: cpu@101 {
@@ -124,6 +129,29 @@
124 clocks = <&cru ARMCLKB>; 129 clocks = <&cru ARMCLKB>;
125 #cooling-cells = <2>; /* min followed by max */ 130 #cooling-cells = <2>; /* min followed by max */
126 dynamic-power-coefficient = <436>; 131 dynamic-power-coefficient = <436>;
132 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
133 };
134
135 idle-states {
136 entry-method = "psci";
137
138 CPU_SLEEP: cpu-sleep {
139 compatible = "arm,idle-state";
140 local-timer-stop;
141 arm,psci-suspend-param = <0x0010000>;
142 entry-latency-us = <120>;
143 exit-latency-us = <250>;
144 min-residency-us = <900>;
145 };
146
147 CLUSTER_SLEEP: cluster-sleep {
148 compatible = "arm,idle-state";
149 local-timer-stop;
150 arm,psci-suspend-param = <0x1010000>;
151 entry-latency-us = <400>;
152 exit-latency-us = <500>;
153 min-residency-us = <2000>;
154 };
127 }; 155 };
128 }; 156 };
129 157
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-23 15:30:38 -0400