aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorOlof Johansson <olof@lixom.net>2018-09-23 09:19:04 -0400
committerOlof Johansson <olof@lixom.net>2018-09-23 09:19:04 -0400
commit89cb3a4c976189a5c6529ee5f5db712949080470 (patch)
tree75c6b3b7ecf77a76df79cbf6b5416f9fec310524
parentfc48cf437a08995943b6fb9fe43ab0fce52ddc2c (diff)
parent450d6079e8d3c40c7ce67ac8bb4a2da9baf56613 (diff)
Merge tag 'renesas-arm64-dt-for-v4.20' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt
Renesas ARM64 Based SoC DT Updates for v4.20 * Correct whitespace around assignments * R-Car Gen-3 SoCs: - Enable SDR104 for SD devices - Include R-Car product name in DTSI files to ease maintenance * R-Car Gen-3 SoC based boards: Convert to new LVDS DT bindings * R-Car Gen 3 Salvator-X and Salvator-XS boards: - Override secondary addresses of ADV748x to avoid address conflicts * R-Car Gen 3 based Salvator-XS board: Enable SATA * R-Car M3-N (r8a77965) SoC: - Add FDP1 device nodes - Move arm_cc630p and timer nodes to restore sort-order of file - Correct clock/reset for usb2_phy1 - Correct HS-USB compat string - Add OPPs table for cpu devices enabling CPUFreq support - Add CAN device placeholder nodes to facilitate adding initial device tree for KF daughter board - Attach SYS-DMAC to the IPMMU * R-Car M3-N (r8a77965) based ULCB board: - Initial device tree for board and KF daughter board * R-Car E3 (r8a77990) SoC: - Add SYS-DMAC, I2C VIN, CSI-2, MSIOF device nodes - Add BRG support to SCIF2 which allows an increase in serial clock accuracy - Use CPG/MSSR and SYSC binding definitions * R-Car E3 (r8a77990) based Ebisu board: Enable PWM * R-Car D3 (r8a77995) SoC: Attach the SYS-DMAC to the IPMMU * R-Car D3 (r8a77995) based Draak board: Sort device nodes * R-Car V3H (r8a77980) based V3HSK board: - Move lvds0 node to restore sort-order of file * R-Car V3H (r8a77980) SoC: - Add RWDT, CSI2 and VIN, Cortex-A53 PMU nodes - Move IPMMU and CAN clock nodes to restore sort-order of file * R-Car V3M (r8a77970) SoC: - Add MMC nodes - Move CAN clock node to restore sort-order of file * R-Car V3M (r8a77970) based V3MSK board: Add eMMC support * R-Car V3H (r8a77980) based Condor board: Add PCIe, DU, LVDS and HDMI support * RZ/G2M (r8a774a1) SoC: - Initial device tree - Add SYS-DMAC, SCIF, HSCIF, INTC-EX, EtherAVB, RWDT, pinctl, GPIO, SDHI, I2C, IIC-DVFS, thermal, IPMMU, MSIOF, Cortex-A53 CPU core, PWM, Audio, FCPF, FCPV, USB2.0, USB-DMAC, HSUSB and USB3.0 device nodes * tag 'renesas-arm64-dt-for-v4.20' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (58 commits) arm64: dts: r8a77965: add FDP1 device nodes arm64: dts: renesas: draak: Sort device nodes arm64: dts: renesas: enable SDR104 on R-Car Gen3 arm64: dts: renesas: r8a77990: Add SYS-DMAC device nodes arm64: dts: renesas: r8a77990: Add I2C device nodes arm64: dts: renesas: r8a77990: Add VIN and CSI-2 device nodes arm64: dts: renesas: r8a77990: Add all MSIOF nodes arm64: dts: renesas: r8a7795: Move arm_cc630p node arm64: dts: renesas: r8a77990: Add BRG support to SCIF2 arm64: dts: renesas: r8a77990: Use CPG/MSSR and SYSC binding definitions arm64: dts: renesas: salvator-xs: Improve SATA switch settings comments arm64: dts: renesas: r8a77965: Fix clock/reset for usb2_phy1 arm64: dts: renesas: r8a77965: Fix HS-USB compatible arm64: dts: renesas: r8a77965: Move timer node arm64: dts: renesas: v3hsk: Move lvds0 node arm64: dts: renesas: Fix whitespace around assignments arm64: dts: renesas: r8a77965: m3nulcb-kf: Initial device tree arm64: dts: renesas: condor: add PCIe support arm64: dts: renesas: r8a77980: add PCIe support arm64: dts: renesas: r8a774a1: Add USB3.0 device nodes ... Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat
-rw-r--r--arch/arm64/boot/dts/renesas/Makefile2
-rw-r--r--arch/arm64/boot/dts/renesas/r8a774a1.dtsi1664
-rw-r--r--arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts3
-rw-r--r--arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi18
-rw-r--r--arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts3
-rw-r--r--arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts3
-rw-r--r--arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts17
-rw-r--r--arch/arm64/boot/dts/renesas/r8a7795.dtsi104
-rw-r--r--arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts3
-rw-r--r--arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts3
-rw-r--r--arch/arm64/boot/dts/renesas/r8a7796.dtsi86
-rw-r--r--arch/arm64/boot/dts/renesas/r8a77965-m3nulcb-kf.dts16
-rw-r--r--arch/arm64/boot/dts/renesas/r8a77965-m3nulcb.dts33
-rw-r--r--arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts14
-rw-r--r--arch/arm64/boot/dts/renesas/r8a77965.dtsi155
-rw-r--r--arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts26
-rw-r--r--arch/arm64/boot/dts/renesas/r8a77970.dtsi36
-rw-r--r--arch/arm64/boot/dts/renesas/r8a77980-condor.dts123
-rw-r--r--arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts134
-rw-r--r--arch/arm64/boot/dts/renesas/r8a77980.dtsi580
-rw-r--r--arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts24
-rw-r--r--arch/arm64/boot/dts/renesas/r8a77990.dtsi478
-rw-r--r--arch/arm64/boot/dts/renesas/r8a77995-draak.dts276
-rw-r--r--arch/arm64/boot/dts/renesas/r8a77995.dtsi14
-rw-r--r--arch/arm64/boot/dts/renesas/salvator-common.dtsi7
-rw-r--r--arch/arm64/boot/dts/renesas/ulcb-kf.dtsi2
-rw-r--r--arch/arm64/boot/dts/renesas/ulcb.dtsi1
27 files changed, 3462 insertions, 363 deletions
diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
index 9e2394bc3c62..a8ce6594342d 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -8,6 +8,8 @@ dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-x.dtb r8a7796-m3ulcb.dtb
8dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-m3ulcb-kf.dtb 8dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-m3ulcb-kf.dtb
9dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-xs.dtb 9dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-xs.dtb
10dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-salvator-x.dtb r8a77965-salvator-xs.dtb 10dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-salvator-x.dtb r8a77965-salvator-xs.dtb
11dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-m3nulcb.dtb
12dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-m3nulcb-kf.dtb
11dtb-$(CONFIG_ARCH_R8A77970) += r8a77970-eagle.dtb r8a77970-v3msk.dtb 13dtb-$(CONFIG_ARCH_R8A77970) += r8a77970-eagle.dtb r8a77970-v3msk.dtb
12dtb-$(CONFIG_ARCH_R8A77980) += r8a77980-condor.dtb r8a77980-v3hsk.dtb 14dtb-$(CONFIG_ARCH_R8A77980) += r8a77980-condor.dtb r8a77980-v3hsk.dtb
13dtb-$(CONFIG_ARCH_R8A77990) += r8a77990-ebisu.dtb 15dtb-$(CONFIG_ARCH_R8A77990) += r8a77990-ebisu.dtb
diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
new file mode 100644
index 000000000000..046fc937da14
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -0,0 +1,1664 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the r8a774a1 SoC
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/irq.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/clock/renesas-cpg-mssr.h>
11
12/ {
13 compatible = "renesas,r8a774a1";
14 #address-cells = <2>;
15 #size-cells = <2>;
16
17 aliases {
18 i2c0 = &i2c0;
19 i2c1 = &i2c1;
20 i2c2 = &i2c2;
21 i2c3 = &i2c3;
22 i2c4 = &i2c4;
23 i2c5 = &i2c5;
24 i2c6 = &i2c6;
25 i2c7 = &i2c_dvfs;
26 };
27
28 /*
29 * The external audio clocks are configured as 0 Hz fixed frequency
30 * clocks by default.
31 * Boards that provide audio clocks should override them.
32 */
33 audio_clk_a: audio_clk_a {
34 compatible = "fixed-clock";
35 #clock-cells = <0>;
36 clock-frequency = <0>;
37 };
38
39 audio_clk_b: audio_clk_b {
40 compatible = "fixed-clock";
41 #clock-cells = <0>;
42 clock-frequency = <0>;
43 };
44
45 audio_clk_c: audio_clk_c {
46 compatible = "fixed-clock";
47 #clock-cells = <0>;
48 clock-frequency = <0>;
49 };
50
51 /* External CAN clock - to be overridden by boards that provide it */
52 can_clk: can {
53 compatible = "fixed-clock";
54 #clock-cells = <0>;
55 clock-frequency = <0>;
56 };
57
58 cpus {
59 #address-cells = <1>;
60 #size-cells = <0>;
61
62 a57_0: cpu@0 {
63 compatible = "arm,cortex-a57", "arm,armv8";
64 reg = <0x0>;
65 device_type = "cpu";
66 power-domains = <&sysc 0>;
67 next-level-cache = <&L2_CA57>;
68 enable-method = "psci";
69 clocks = <&cpg CPG_CORE 0>;
70 };
71
72 a57_1: cpu@1 {
73 compatible = "arm,cortex-a57", "arm,armv8";
74 reg = <0x1>;
75 device_type = "cpu";
76 power-domains = <&sysc 1>;
77 next-level-cache = <&L2_CA57>;
78 enable-method = "psci";
79 clocks = <&cpg CPG_CORE 0>;
80 };
81
82 a53_0: cpu@100 {
83 compatible = "arm,cortex-a53", "arm,armv8";
84 reg = <0x100>;
85 device_type = "cpu";
86 power-domains = <&sysc 5>;
87 next-level-cache = <&L2_CA53>;
88 enable-method = "psci";
89 clocks =<&cpg CPG_CORE 1>;
90 };
91
92 a53_1: cpu@101 {
93 compatible = "arm,cortex-a53", "arm,armv8";
94 reg = <0x101>;
95 device_type = "cpu";
96 power-domains = <&sysc 6>;
97 next-level-cache = <&L2_CA53>;
98 enable-method = "psci";
99 clocks =<&cpg CPG_CORE 1>;
100 };
101
102 a53_2: cpu@102 {
103 compatible = "arm,cortex-a53", "arm,armv8";
104 reg = <0x102>;
105 device_type = "cpu";
106 power-domains = <&sysc 7>;
107 next-level-cache = <&L2_CA53>;
108 enable-method = "psci";
109 clocks =<&cpg CPG_CORE 1>;
110 };
111
112 a53_3: cpu@103 {
113 compatible = "arm,cortex-a53", "arm,armv8";
114 reg = <0x103>;
115 device_type = "cpu";
116 power-domains = <&sysc 8>;
117 next-level-cache = <&L2_CA53>;
118 enable-method = "psci";
119 clocks =<&cpg CPG_CORE 1>;
120 };
121
122 L2_CA57: cache-controller-0 {
123 compatible = "cache";
124 power-domains = <&sysc 12>;
125 cache-unified;
126 cache-level = <2>;
127 };
128
129 L2_CA53: cache-controller-1 {
130 compatible = "cache";
131 power-domains = <&sysc 21>;
132 cache-unified;
133 cache-level = <2>;
134 };
135 };
136
137 extal_clk: extal {
138 compatible = "fixed-clock";
139 #clock-cells = <0>;
140 /* This value must be overridden by the board */
141 clock-frequency = <0>;
142 };
143
144 extalr_clk: extalr {
145 compatible = "fixed-clock";
146 #clock-cells = <0>;
147 /* This value must be overridden by the board */
148 clock-frequency = <0>;
149 };
150
151 /* External PCIe clock - can be overridden by the board */
152 pcie_bus_clk: pcie_bus {
153 compatible = "fixed-clock";
154 #clock-cells = <0>;
155 clock-frequency = <0>;
156 };
157
158 pmu_a53 {
159 compatible = "arm,cortex-a53-pmu";
160 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
161 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
162 <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
163 <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
164 interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>;
165 };
166
167 pmu_a57 {
168 compatible = "arm,cortex-a57-pmu";
169 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
170 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
171 interrupt-affinity = <&a57_0>, <&a57_1>;
172 };
173
174 psci {
175 compatible = "arm,psci-1.0", "arm,psci-0.2";
176 method = "smc";
177 };
178
179 /* External SCIF clock - to be overridden by boards that provide it */
180 scif_clk: scif {
181 compatible = "fixed-clock";
182 #clock-cells = <0>;
183 clock-frequency = <0>;
184 };
185
186 soc {
187 compatible = "simple-bus";
188 interrupt-parent = <&gic>;
189 #address-cells = <2>;
190 #size-cells = <2>;
191 ranges;
192
193 rwdt: watchdog@e6020000 {
194 compatible = "renesas,r8a774a1-wdt",
195 "renesas,rcar-gen3-wdt";
196 reg = <0 0xe6020000 0 0x0c>;
197 clocks = <&cpg CPG_MOD 402>;
198 power-domains = <&sysc 32>;
199 resets = <&cpg 402>;
200 status = "disabled";
201 };
202
203 gpio0: gpio@e6050000 {
204 compatible = "renesas,gpio-r8a774a1",
205 "renesas,rcar-gen3-gpio";
206 reg = <0 0xe6050000 0 0x50>;
207 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
208 #gpio-cells = <2>;
209 gpio-controller;
210 gpio-ranges = <&pfc 0 0 16>;
211 #interrupt-cells = <2>;
212 interrupt-controller;
213 clocks = <&cpg CPG_MOD 912>;
214 power-domains = <&sysc 32>;
215 resets = <&cpg 912>;
216 };
217
218 gpio1: gpio@e6051000 {
219 compatible = "renesas,gpio-r8a774a1",
220 "renesas,rcar-gen3-gpio";
221 reg = <0 0xe6051000 0 0x50>;
222 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
223 #gpio-cells = <2>;
224 gpio-controller;
225 gpio-ranges = <&pfc 0 32 29>;
226 #interrupt-cells = <2>;
227 interrupt-controller;
228 clocks = <&cpg CPG_MOD 911>;
229 power-domains = <&sysc 32>;
230 resets = <&cpg 911>;
231 };
232
233 gpio2: gpio@e6052000 {
234 compatible = "renesas,gpio-r8a774a1",
235 "renesas,rcar-gen3-gpio";
236 reg = <0 0xe6052000 0 0x50>;
237 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
238 #gpio-cells = <2>;
239 gpio-controller;
240 gpio-ranges = <&pfc 0 64 15>;
241 #interrupt-cells = <2>;
242 interrupt-controller;
243 clocks = <&cpg CPG_MOD 910>;
244 power-domains = <&sysc 32>;
245 resets = <&cpg 910>;
246 };
247
248 gpio3: gpio@e6053000 {
249 compatible = "renesas,gpio-r8a774a1",
250 "renesas,rcar-gen3-gpio";
251 reg = <0 0xe6053000 0 0x50>;
252 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
253 #gpio-cells = <2>;
254 gpio-controller;
255 gpio-ranges = <&pfc 0 96 16>;
256 #interrupt-cells = <2>;
257 interrupt-controller;
258 clocks = <&cpg CPG_MOD 909>;
259 power-domains = <&sysc 32>;
260 resets = <&cpg 909>;
261 };
262
263 gpio4: gpio@e6054000 {
264 compatible = "renesas,gpio-r8a774a1",
265 "renesas,rcar-gen3-gpio";
266 reg = <0 0xe6054000 0 0x50>;
267 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
268 #gpio-cells = <2>;
269 gpio-controller;
270 gpio-ranges = <&pfc 0 128 18>;
271 #interrupt-cells = <2>;
272 interrupt-controller;
273 clocks = <&cpg CPG_MOD 908>;
274 power-domains = <&sysc 32>;
275 resets = <&cpg 908>;
276 };
277
278 gpio5: gpio@e6055000 {
279 compatible = "renesas,gpio-r8a774a1",
280 "renesas,rcar-gen3-gpio";
281 reg = <0 0xe6055000 0 0x50>;
282 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
283 #gpio-cells = <2>;
284 gpio-controller;
285 gpio-ranges = <&pfc 0 160 26>;
286 #interrupt-cells = <2>;
287 interrupt-controller;
288 clocks = <&cpg CPG_MOD 907>;
289 power-domains = <&sysc 32>;
290 resets = <&cpg 907>;
291 };
292
293 gpio6: gpio@e6055400 {
294 compatible = "renesas,gpio-r8a774a1",
295 "renesas,rcar-gen3-gpio";
296 reg = <0 0xe6055400 0 0x50>;
297 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
298 #gpio-cells = <2>;
299 gpio-controller;
300 gpio-ranges = <&pfc 0 192 32>;
301 #interrupt-cells = <2>;
302 interrupt-controller;
303 clocks = <&cpg CPG_MOD 906>;
304 power-domains = <&sysc 32>;
305 resets = <&cpg 906>;
306 };
307
308 gpio7: gpio@e6055800 {
309 compatible = "renesas,gpio-r8a774a1",
310 "renesas,rcar-gen3-gpio";
311 reg = <0 0xe6055800 0 0x50>;
312 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
313 #gpio-cells = <2>;
314 gpio-controller;
315 gpio-ranges = <&pfc 0 224 4>;
316 #interrupt-cells = <2>;
317 interrupt-controller;
318 clocks = <&cpg CPG_MOD 905>;
319 power-domains = <&sysc 32>;
320 resets = <&cpg 905>;
321 };
322
323 pfc: pin-controller@e6060000 {
324 compatible = "renesas,pfc-r8a774a1";
325 reg = <0 0xe6060000 0 0x50c>;
326 };
327
328 cpg: clock-controller@e6150000 {
329 compatible = "renesas,r8a774a1-cpg-mssr";
330 reg = <0 0xe6150000 0 0x0bb0>;
331 clocks = <&extal_clk>, <&extalr_clk>;
332 clock-names = "extal", "extalr";
333 #clock-cells = <2>;
334 #power-domain-cells = <0>;
335 #reset-cells = <1>;
336 };
337
338 rst: reset-controller@e6160000 {
339 compatible = "renesas,r8a774a1-rst";
340 reg = <0 0xe6160000 0 0x018c>;
341 };
342
343 sysc: system-controller@e6180000 {
344 compatible = "renesas,r8a774a1-sysc";
345 reg = <0 0xe6180000 0 0x0400>;
346 #power-domain-cells = <1>;
347 };
348
349 tsc: thermal@e6198000 {
350 compatible = "renesas,r8a774a1-thermal";
351 reg = <0 0xe6198000 0 0x100>,
352 <0 0xe61a0000 0 0x100>,
353 <0 0xe61a8000 0 0x100>;
354 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
355 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
356 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
357 clocks = <&cpg CPG_MOD 522>;
358 power-domains = <&sysc 32>;
359 resets = <&cpg 522>;
360 #thermal-sensor-cells = <1>;
361 status = "okay";
362 };
363
364 intc_ex: interrupt-controller@e61c0000 {
365 compatible = "renesas,intc-ex-r8a774a1", "renesas,irqc";
366 #interrupt-cells = <2>;
367 interrupt-controller;
368 reg = <0 0xe61c0000 0 0x200>;
369 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
370 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
371 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
372 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
373 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
374 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
375 clocks = <&cpg CPG_MOD 407>;
376 power-domains = <&sysc 32>;
377 resets = <&cpg 407>;
378 };
379
380 i2c0: i2c@e6500000 {
381 #address-cells = <1>;
382 #size-cells = <0>;
383 compatible = "renesas,i2c-r8a774a1",
384 "renesas,rcar-gen3-i2c";
385 reg = <0 0xe6500000 0 0x40>;
386 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
387 clocks = <&cpg CPG_MOD 931>;
388 power-domains = <&sysc 32>;
389 resets = <&cpg 931>;
390 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
391 <&dmac2 0x91>, <&dmac2 0x90>;
392 dma-names = "tx", "rx", "tx", "rx";
393 i2c-scl-internal-delay-ns = <110>;
394 status = "disabled";
395 };
396
397 i2c1: i2c@e6508000 {
398 #address-cells = <1>;
399 #size-cells = <0>;
400 compatible = "renesas,i2c-r8a774a1",
401 "renesas,rcar-gen3-i2c";
402 reg = <0 0xe6508000 0 0x40>;
403 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
404 clocks = <&cpg CPG_MOD 930>;
405 power-domains = <&sysc 32>;
406 resets = <&cpg 930>;
407 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
408 <&dmac2 0x93>, <&dmac2 0x92>;
409 dma-names = "tx", "rx", "tx", "rx";
410 i2c-scl-internal-delay-ns = <6>;
411 status = "disabled";
412 };
413
414 i2c2: i2c@e6510000 {
415 #address-cells = <1>;
416 #size-cells = <0>;
417 compatible = "renesas,i2c-r8a774a1",
418 "renesas,rcar-gen3-i2c";
419 reg = <0 0xe6510000 0 0x40>;
420 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
421 clocks = <&cpg CPG_MOD 929>;
422 power-domains = <&sysc 32>;
423 resets = <&cpg 929>;
424 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
425 <&dmac2 0x95>, <&dmac2 0x94>;
426 dma-names = "tx", "rx", "tx", "rx";
427 i2c-scl-internal-delay-ns = <6>;
428 status = "disabled";
429 };
430
431 i2c3: i2c@e66d0000 {
432 #address-cells = <1>;
433 #size-cells = <0>;
434 compatible = "renesas,i2c-r8a774a1",
435 "renesas,rcar-gen3-i2c";
436 reg = <0 0xe66d0000 0 0x40>;
437 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
438 clocks = <&cpg CPG_MOD 928>;
439 power-domains = <&sysc 32>;
440 resets = <&cpg 928>;
441 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
442 dma-names = "tx", "rx";
443 i2c-scl-internal-delay-ns = <110>;
444 status = "disabled";
445 };
446
447 i2c4: i2c@e66d8000 {
448 #address-cells = <1>;
449 #size-cells = <0>;
450 compatible = "renesas,i2c-r8a774a1",
451 "renesas,rcar-gen3-i2c";
452 reg = <0 0xe66d8000 0 0x40>;
453 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
454 clocks = <&cpg CPG_MOD 927>;
455 power-domains = <&sysc 32>;
456 resets = <&cpg 927>;
457 dmas = <&dmac0 0x99>, <&dmac0 0x98>;
458 dma-names = "tx", "rx";
459 i2c-scl-internal-delay-ns = <110>;
460 status = "disabled";
461 };
462
463 i2c5: i2c@e66e0000 {
464 #address-cells = <1>;
465 #size-cells = <0>;
466 compatible = "renesas,i2c-r8a774a1",
467 "renesas,rcar-gen3-i2c";
468 reg = <0 0xe66e0000 0 0x40>;
469 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
470 clocks = <&cpg CPG_MOD 919>;
471 power-domains = <&sysc 32>;
472 resets = <&cpg 919>;
473 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
474 dma-names = "tx", "rx";
475 i2c-scl-internal-delay-ns = <110>;
476 status = "disabled";
477 };
478
479 i2c6: i2c@e66e8000 {
480 #address-cells = <1>;
481 #size-cells = <0>;
482 compatible = "renesas,i2c-r8a774a1",
483 "renesas,rcar-gen3-i2c";
484 reg = <0 0xe66e8000 0 0x40>;
485 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
486 clocks = <&cpg CPG_MOD 918>;
487 power-domains = <&sysc 32>;
488 resets = <&cpg 918>;
489 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
490 dma-names = "tx", "rx";
491 i2c-scl-internal-delay-ns = <6>;
492 status = "disabled";
493 };
494
495 i2c_dvfs: i2c@e60b0000 {
496 #address-cells = <1>;
497 #size-cells = <0>;
498 compatible = "renesas,iic-r8a774a1",
499 "renesas,rcar-gen3-iic",
500 "renesas,rmobile-iic";
501 reg = <0 0xe60b0000 0 0x425>;
502 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
503 clocks = <&cpg CPG_MOD 926>;
504 power-domains = <&sysc 32>;
505 resets = <&cpg 926>;
506 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
507 dma-names = "tx", "rx";
508 status = "disabled";
509 };
510
511 hscif0: serial@e6540000 {
512 compatible = "renesas,hscif-r8a774a1",
513 "renesas,rcar-gen3-hscif",
514 "renesas,hscif";
515 reg = <0 0xe6540000 0 0x60>;
516 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
517 clocks = <&cpg CPG_MOD 520>,
518 <&cpg CPG_CORE 19>,
519 <&scif_clk>;
520 clock-names = "fck", "brg_int", "scif_clk";
521 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
522 <&dmac2 0x31>, <&dmac2 0x30>;
523 dma-names = "tx", "rx", "tx", "rx";
524 power-domains = <&sysc 32>;
525 resets = <&cpg 520>;
526 status = "disabled";
527 };
528
529 hscif1: serial@e6550000 {
530 compatible = "renesas,hscif-r8a774a1",
531 "renesas,rcar-gen3-hscif",
532 "renesas,hscif";
533 reg = <0 0xe6550000 0 0x60>;
534 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
535 clocks = <&cpg CPG_MOD 519>,
536 <&cpg CPG_CORE 19>,
537 <&scif_clk>;
538 clock-names = "fck", "brg_int", "scif_clk";
539 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
540 <&dmac2 0x33>, <&dmac2 0x32>;
541 dma-names = "tx", "rx", "tx", "rx";
542 power-domains = <&sysc 32>;
543 resets = <&cpg 519>;
544 status = "disabled";
545 };
546
547 hscif2: serial@e6560000 {
548 compatible = "renesas,hscif-r8a774a1",
549 "renesas,rcar-gen3-hscif",
550 "renesas,hscif";
551 reg = <0 0xe6560000 0 0x60>;
552 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
553 clocks = <&cpg CPG_MOD 518>,
554 <&cpg CPG_CORE 19>,
555 <&scif_clk>;
556 clock-names = "fck", "brg_int", "scif_clk";
557 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
558 <&dmac2 0x35>, <&dmac2 0x34>;
559 dma-names = "tx", "rx", "tx", "rx";
560 power-domains = <&sysc 32>;
561 resets = <&cpg 518>;
562 status = "disabled";
563 };
564
565 hscif3: serial@e66a0000 {
566 compatible = "renesas,hscif-r8a774a1",
567 "renesas,rcar-gen3-hscif",
568 "renesas,hscif";
569 reg = <0 0xe66a0000 0 0x60>;
570 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
571 clocks = <&cpg CPG_MOD 517>,
572 <&cpg CPG_CORE 19>,
573 <&scif_clk>;
574 clock-names = "fck", "brg_int", "scif_clk";
575 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
576 dma-names = "tx", "rx";
577 power-domains = <&sysc 32>;
578 resets = <&cpg 517>;
579 status = "disabled";
580 };
581
582 hscif4: serial@e66b0000 {
583 compatible = "renesas,hscif-r8a774a1",
584 "renesas,rcar-gen3-hscif",
585 "renesas,hscif";
586 reg = <0 0xe66b0000 0 0x60>;
587 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
588 clocks = <&cpg CPG_MOD 516>,
589 <&cpg CPG_CORE 19>,
590 <&scif_clk>;
591 clock-names = "fck", "brg_int", "scif_clk";
592 dmas = <&dmac0 0x39>, <&dmac0 0x38>;
593 dma-names = "tx", "rx";
594 power-domains = <&sysc 32>;
595 resets = <&cpg 516>;
596 status = "disabled";
597 };
598
599 hsusb: usb@e6590000 {
600 compatible = "renesas,usbhs-r8a774a1",
601 "renesas,rcar-gen3-usbhs";
602 reg = <0 0xe6590000 0 0x100>;
603 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
604 clocks = <&cpg CPG_MOD 704>;
605 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
606 <&usb_dmac1 0>, <&usb_dmac1 1>;
607 dma-names = "ch0", "ch1", "ch2", "ch3";
608 renesas,buswait = <11>;
609 phys = <&usb2_phy0>;
610 phy-names = "usb";
611 power-domains = <&sysc 32>;
612 resets = <&cpg 704>;
613 status = "disabled";
614 };
615
616 usb_dmac0: dma-controller@e65a0000 {
617 compatible = "renesas,r8a774a1-usb-dmac",
618 "renesas,usb-dmac";
619 reg = <0 0xe65a0000 0 0x100>;
620 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
621 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
622 interrupt-names = "ch0", "ch1";
623 clocks = <&cpg CPG_MOD 330>;
624 power-domains = <&sysc 32>;
625 resets = <&cpg 330>;
626 #dma-cells = <1>;
627 dma-channels = <2>;
628 };
629
630 usb_dmac1: dma-controller@e65b0000 {
631 compatible = "renesas,r8a774a1-usb-dmac",
632 "renesas,usb-dmac";
633 reg = <0 0xe65b0000 0 0x100>;
634 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
635 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
636 interrupt-names = "ch0", "ch1";
637 clocks = <&cpg CPG_MOD 331>;
638 power-domains = <&sysc 32>;
639 resets = <&cpg 331>;
640 #dma-cells = <1>;
641 dma-channels = <2>;
642 };
643
644 usb3_phy0: usb-phy@e65ee000 {
645 compatible = "renesas,r8a774a1-usb3-phy",
646 "renesas,rcar-gen3-usb3-phy";
647 reg = <0 0xe65ee000 0 0x90>;
648 clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>,
649 <&usb_extal_clk>;
650 clock-names = "usb3-if", "usb3s_clk", "usb_extal";
651 power-domains = <&sysc 32>;
652 resets = <&cpg 328>;
653 #phy-cells = <0>;
654 status = "disabled";
655 };
656
657 dmac0: dma-controller@e6700000 {
658 compatible = "renesas,dmac-r8a774a1",
659 "renesas,rcar-dmac";
660 reg = <0 0xe6700000 0 0x10000>;
661 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH
662 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
663 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
664 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
665 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
666 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
667 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
668 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
669 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
670 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
671 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
672 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
673 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
674 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
675 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
676 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH
677 GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
678 interrupt-names = "error",
679 "ch0", "ch1", "ch2", "ch3",
680 "ch4", "ch5", "ch6", "ch7",
681 "ch8", "ch9", "ch10", "ch11",
682 "ch12", "ch13", "ch14", "ch15";
683 clocks = <&cpg CPG_MOD 219>;
684 clock-names = "fck";
685 power-domains = <&sysc 32>;
686 resets = <&cpg 219>;
687 #dma-cells = <1>;
688 dma-channels = <16>;
689 };
690
691 dmac1: dma-controller@e7300000 {
692 compatible = "renesas,dmac-r8a774a1",
693 "renesas,rcar-dmac";
694 reg = <0 0xe7300000 0 0x10000>;
695 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
696 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
697 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
698 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
699 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
700 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
701 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
702 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
703 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
704 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
705 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
706 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
707 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
708 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
709 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
710 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH
711 GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
712 interrupt-names = "error",
713 "ch0", "ch1", "ch2", "ch3",
714 "ch4", "ch5", "ch6", "ch7",
715 "ch8", "ch9", "ch10", "ch11",
716 "ch12", "ch13", "ch14", "ch15";
717 clocks = <&cpg CPG_MOD 218>;
718 clock-names = "fck";
719 power-domains = <&sysc 32>;
720 resets = <&cpg 218>;
721 #dma-cells = <1>;
722 dma-channels = <16>;
723 };
724
725 dmac2: dma-controller@e7310000 {
726 compatible = "renesas,dmac-r8a774a1",
727 "renesas,rcar-dmac";
728 reg = <0 0xe7310000 0 0x10000>;
729 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH
730 GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH
731 GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH
732 GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH
733 GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH
734 GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH
735 GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH
736 GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH
737 GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH
738 GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH
739 GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH
740 GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH
741 GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH
742 GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH
743 GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH
744 GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH
745 GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
746 interrupt-names = "error",
747 "ch0", "ch1", "ch2", "ch3",
748 "ch4", "ch5", "ch6", "ch7",
749 "ch8", "ch9", "ch10", "ch11",
750 "ch12", "ch13", "ch14", "ch15";
751 clocks = <&cpg CPG_MOD 217>;
752 clock-names = "fck";
753 power-domains = <&sysc 32>;
754 resets = <&cpg 217>;
755 #dma-cells = <1>;
756 dma-channels = <16>;
757 };
758
759 ipmmu_ds0: mmu@e6740000 {
760 compatible = "renesas,ipmmu-r8a774a1";
761 reg = <0 0xe6740000 0 0x1000>;
762 renesas,ipmmu-main = <&ipmmu_mm 0>;
763 power-domains = <&sysc 32>;
764 #iommu-cells = <1>;
765 };
766
767 ipmmu_ds1: mmu@e7740000 {
768 compatible = "renesas,ipmmu-r8a774a1";
769 reg = <0 0xe7740000 0 0x1000>;
770 renesas,ipmmu-main = <&ipmmu_mm 1>;
771 power-domains = <&sysc 32>;
772 #iommu-cells = <1>;
773 };
774
775 ipmmu_hc: mmu@e6570000 {
776 compatible = "renesas,ipmmu-r8a774a1";
777 reg = <0 0xe6570000 0 0x1000>;
778 renesas,ipmmu-main = <&ipmmu_mm 2>;
779 power-domains = <&sysc 32>;
780 #iommu-cells = <1>;
781 };
782
783 ipmmu_mm: mmu@e67b0000 {
784 compatible = "renesas,ipmmu-r8a774a1";
785 reg = <0 0xe67b0000 0 0x1000>;
786 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
787 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
788 power-domains = <&sysc 32>;
789 #iommu-cells = <1>;
790 };
791
792 ipmmu_mp: mmu@ec670000 {
793 compatible = "renesas,ipmmu-r8a774a1";
794 reg = <0 0xec670000 0 0x1000>;
795 renesas,ipmmu-main = <&ipmmu_mm 4>;
796 power-domains = <&sysc 32>;
797 #iommu-cells = <1>;
798 };
799
800 ipmmu_pv0: mmu@fd800000 {
801 compatible = "renesas,ipmmu-r8a774a1";
802 reg = <0 0xfd800000 0 0x1000>;
803 renesas,ipmmu-main = <&ipmmu_mm 5>;
804 power-domains = <&sysc 32>;
805 #iommu-cells = <1>;
806 };
807
808 ipmmu_pv1: mmu@fd950000 {
809 compatible = "renesas,ipmmu-r8a774a1";
810 reg = <0 0xfd950000 0 0x1000>;
811 renesas,ipmmu-main = <&ipmmu_mm 6>;
812 power-domains = <&sysc 32>;
813 #iommu-cells = <1>;
814 };
815
816 ipmmu_vc0: mmu@fe6b0000 {
817 compatible = "renesas,ipmmu-r8a774a1";
818 reg = <0 0xfe6b0000 0 0x1000>;
819 renesas,ipmmu-main = <&ipmmu_mm 8>;
820 power-domains = <&sysc 14>;
821 #iommu-cells = <1>;
822 };
823
824 ipmmu_vi0: mmu@febd0000 {
825 compatible = "renesas,ipmmu-r8a774a1";
826 reg = <0 0xfebd0000 0 0x1000>;
827 renesas,ipmmu-main = <&ipmmu_mm 9>;
828 power-domains = <&sysc 32>;
829 #iommu-cells = <1>;
830 };
831
832 avb: ethernet@e6800000 {
833 compatible = "renesas,etheravb-r8a774a1",
834 "renesas,etheravb-rcar-gen3";
835 reg = <0 0xe6800000 0 0x800>;
836 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
837 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
838 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
839 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
840 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
841 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
842 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
843 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
844 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
845 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
846 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
847 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
848 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
849 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
850 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
851 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
852 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
853 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
854 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
855 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
856 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
857 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
858 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
859 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
860 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
861 interrupt-names = "ch0", "ch1", "ch2", "ch3",
862 "ch4", "ch5", "ch6", "ch7",
863 "ch8", "ch9", "ch10", "ch11",
864 "ch12", "ch13", "ch14", "ch15",
865 "ch16", "ch17", "ch18", "ch19",
866 "ch20", "ch21", "ch22", "ch23",
867 "ch24";
868 clocks = <&cpg CPG_MOD 812>;
869 power-domains = <&sysc 32>;
870 resets = <&cpg 812>;
871 phy-mode = "rgmii";
872 #address-cells = <1>;
873 #size-cells = <0>;
874 status = "disabled";
875 };
876
877 pwm0: pwm@e6e30000 {
878 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
879 reg = <0 0xe6e30000 0 0x8>;
880 #pwm-cells = <2>;
881 clocks = <&cpg CPG_MOD 523>;
882 resets = <&cpg 523>;
883 power-domains = <&sysc 32>;
884 status = "disabled";
885 };
886
887 pwm1: pwm@e6e31000 {
888 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
889 reg = <0 0xe6e31000 0 0x8>;
890 #pwm-cells = <2>;
891 clocks = <&cpg CPG_MOD 523>;
892 resets = <&cpg 523>;
893 power-domains = <&sysc 32>;
894 status = "disabled";
895 };
896
897 pwm2: pwm@e6e32000 {
898 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
899 reg = <0 0xe6e32000 0 0x8>;
900 #pwm-cells = <2>;
901 clocks = <&cpg CPG_MOD 523>;
902 resets = <&cpg 523>;
903 power-domains = <&sysc 32>;
904 status = "disabled";
905 };
906
907 pwm3: pwm@e6e33000 {
908 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
909 reg = <0 0xe6e33000 0 0x8>;
910 #pwm-cells = <2>;
911 clocks = <&cpg CPG_MOD 523>;
912 resets = <&cpg 523>;
913 power-domains = <&sysc 32>;
914 status = "disabled";
915 };
916
917 pwm4: pwm@e6e34000 {
918 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
919 reg = <0 0xe6e34000 0 0x8>;
920 #pwm-cells = <2>;
921 clocks = <&cpg CPG_MOD 523>;
922 resets = <&cpg 523>;
923 power-domains = <&sysc 32>;
924 status = "disabled";
925 };
926
927 pwm5: pwm@e6e35000 {
928 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
929 reg = <0 0xe6e35000 0 0x8>;
930 #pwm-cells = <2>;
931 clocks = <&cpg CPG_MOD 523>;
932 resets = <&cpg 523>;
933 power-domains = <&sysc 32>;
934 status = "disabled";
935 };
936
937 pwm6: pwm@e6e36000 {
938 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
939 reg = <0 0xe6e36000 0 0x8>;
940 #pwm-cells = <2>;
941 clocks = <&cpg CPG_MOD 523>;
942 resets = <&cpg 523>;
943 power-domains = <&sysc 32>;
944 status = "disabled";
945 };
946
947 scif0: serial@e6e60000 {
948 compatible = "renesas,scif-r8a774a1",
949 "renesas,rcar-gen3-scif", "renesas,scif";
950 reg = <0 0xe6e60000 0 0x40>;
951 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
952 clocks = <&cpg CPG_MOD 207>,
953 <&cpg CPG_CORE 19>,
954 <&scif_clk>;
955 clock-names = "fck", "brg_int", "scif_clk";
956 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
957 <&dmac2 0x51>, <&dmac2 0x50>;
958 dma-names = "tx", "rx", "tx", "rx";
959 power-domains = <&sysc 32>;
960 resets = <&cpg 207>;
961 status = "disabled";
962 };
963
964 scif1: serial@e6e68000 {
965 compatible = "renesas,scif-r8a774a1",
966 "renesas,rcar-gen3-scif", "renesas,scif";
967 reg = <0 0xe6e68000 0 0x40>;
968 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
969 clocks = <&cpg CPG_MOD 206>,
970 <&cpg CPG_CORE 19>,
971 <&scif_clk>;
972 clock-names = "fck", "brg_int", "scif_clk";
973 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
974 <&dmac2 0x53>, <&dmac2 0x52>;
975 dma-names = "tx", "rx", "tx", "rx";
976 power-domains = <&sysc 32>;
977 resets = <&cpg 206>;
978 status = "disabled";
979 };
980
981 scif2: serial@e6e88000 {
982 compatible = "renesas,scif-r8a774a1",
983 "renesas,rcar-gen3-scif", "renesas,scif";
984 reg = <0 0xe6e88000 0 0x40>;
985 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
986 clocks = <&cpg CPG_MOD 310>,
987 <&cpg CPG_CORE 19>,
988 <&scif_clk>;
989 clock-names = "fck", "brg_int", "scif_clk";
990 power-domains = <&sysc 32>;
991 resets = <&cpg 310>;
992 status = "disabled";
993 };
994
995 scif3: serial@e6c50000 {
996 compatible = "renesas,scif-r8a774a1",
997 "renesas,rcar-gen3-scif", "renesas,scif";
998 reg = <0 0xe6c50000 0 0x40>;
999 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1000 clocks = <&cpg CPG_MOD 204>,
1001 <&cpg CPG_CORE 19>,
1002 <&scif_clk>;
1003 clock-names = "fck", "brg_int", "scif_clk";
1004 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
1005 dma-names = "tx", "rx";
1006 power-domains = <&sysc 32>;
1007 resets = <&cpg 204>;
1008 status = "disabled";
1009 };
1010
1011 scif4: serial@e6c40000 {
1012 compatible = "renesas,scif-r8a774a1",
1013 "renesas,rcar-gen3-scif", "renesas,scif";
1014 reg = <0 0xe6c40000 0 0x40>;
1015 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1016 clocks = <&cpg CPG_MOD 203>,
1017 <&cpg CPG_CORE 19>,
1018 <&scif_clk>;
1019 clock-names = "fck", "brg_int", "scif_clk";
1020 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
1021 dma-names = "tx", "rx";
1022 power-domains = <&sysc 32>;
1023 resets = <&cpg 203>;
1024 status = "disabled";
1025 };
1026
1027 scif5: serial@e6f30000 {
1028 compatible = "renesas,scif-r8a774a1",
1029 "renesas,rcar-gen3-scif", "renesas,scif";
1030 reg = <0 0xe6f30000 0 0x40>;
1031 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1032 clocks = <&cpg CPG_MOD 202>,
1033 <&cpg CPG_CORE 19>,
1034 <&scif_clk>;
1035 clock-names = "fck", "brg_int", "scif_clk";
1036 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
1037 <&dmac2 0x5b>, <&dmac2 0x5a>;
1038 dma-names = "tx", "rx", "tx", "rx";
1039 power-domains = <&sysc 32>;
1040 resets = <&cpg 202>;
1041 status = "disabled";
1042 };
1043
1044 msiof0: spi@e6e90000 {
1045 compatible = "renesas,msiof-r8a774a1",
1046 "renesas,rcar-gen3-msiof";
1047 reg = <0 0xe6e90000 0 0x0064>;
1048 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1049 clocks = <&cpg CPG_MOD 211>;
1050 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
1051 <&dmac2 0x41>, <&dmac2 0x40>;
1052 dma-names = "tx", "rx", "tx", "rx";
1053 power-domains = <&sysc 32>;
1054 resets = <&cpg 211>;
1055 #address-cells = <1>;
1056 #size-cells = <0>;
1057 status = "disabled";
1058 };
1059
1060 msiof1: spi@e6ea0000 {
1061 compatible = "renesas,msiof-r8a774a1",
1062 "renesas,rcar-gen3-msiof";
1063 reg = <0 0xe6ea0000 0 0x0064>;
1064 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
1065 clocks = <&cpg CPG_MOD 210>;
1066 dmas = <&dmac1 0x43>, <&dmac1 0x42>,
1067 <&dmac2 0x43>, <&dmac2 0x42>;
1068 dma-names = "tx", "rx", "tx", "rx";
1069 power-domains = <&sysc 32>;
1070 resets = <&cpg 210>;
1071 #address-cells = <1>;
1072 #size-cells = <0>;
1073 status = "disabled";
1074 };
1075
1076 msiof2: spi@e6c00000 {
1077 compatible = "renesas,msiof-r8a774a1",
1078 "renesas,rcar-gen3-msiof";
1079 reg = <0 0xe6c00000 0 0x0064>;
1080 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1081 clocks = <&cpg CPG_MOD 209>;
1082 dmas = <&dmac0 0x45>, <&dmac0 0x44>;
1083 dma-names = "tx", "rx";
1084 power-domains = <&sysc 32>;
1085 resets = <&cpg 209>;
1086 #address-cells = <1>;
1087 #size-cells = <0>;
1088 status = "disabled";
1089 };
1090
1091 msiof3: spi@e6c10000 {
1092 compatible = "renesas,msiof-r8a774a1",
1093 "renesas,rcar-gen3-msiof";
1094 reg = <0 0xe6c10000 0 0x0064>;
1095 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
1096 clocks = <&cpg CPG_MOD 208>;
1097 dmas = <&dmac0 0x47>, <&dmac0 0x46>;
1098 dma-names = "tx", "rx";
1099 power-domains = <&sysc 32>;
1100 resets = <&cpg 208>;
1101 #address-cells = <1>;
1102 #size-cells = <0>;
1103 status = "disabled";
1104 };
1105
1106 rcar_sound: sound@ec500000 {
1107 /*
1108 * #sound-dai-cells is required
1109 *
1110 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1111 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
1112 */
1113 /*
1114 * #clock-cells is required for audio_clkout0/1/2/3
1115 *
1116 * clkout : #clock-cells = <0>; <&rcar_sound>;
1117 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
1118 */
1119 compatible = "renesas,rcar_sound-r8a774a1", "renesas,rcar_sound-gen3";
1120 reg = <0 0xec500000 0 0x1000>, /* SCU */
1121 <0 0xec5a0000 0 0x100>, /* ADG */
1122 <0 0xec540000 0 0x1000>, /* SSIU */
1123 <0 0xec541000 0 0x280>, /* SSI */
1124 <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
1125 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1126
1127 clocks = <&cpg CPG_MOD 1005>,
1128 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
1129 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
1130 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
1131 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
1132 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
1133 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
1134 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
1135 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
1136 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
1137 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
1138 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1139 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1140 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
1141 <&audio_clk_a>, <&audio_clk_b>,
1142 <&audio_clk_c>,
1143 <&cpg CPG_CORE 10>;
1144 clock-names = "ssi-all",
1145 "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1146 "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1147 "ssi.1", "ssi.0",
1148 "src.9", "src.8", "src.7", "src.6",
1149 "src.5", "src.4", "src.3", "src.2",
1150 "src.1", "src.0",
1151 "mix.1", "mix.0",
1152 "ctu.1", "ctu.0",
1153 "dvc.0", "dvc.1",
1154 "clk_a", "clk_b", "clk_c", "clk_i";
1155 power-domains = <&sysc 32>;
1156 resets = <&cpg 1005>,
1157 <&cpg 1006>, <&cpg 1007>,
1158 <&cpg 1008>, <&cpg 1009>,
1159 <&cpg 1010>, <&cpg 1011>,
1160 <&cpg 1012>, <&cpg 1013>,
1161 <&cpg 1014>, <&cpg 1015>;
1162 reset-names = "ssi-all",
1163 "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1164 "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1165 "ssi.1", "ssi.0";
1166 status = "disabled";
1167
1168 rcar_sound,dvc {
1169 dvc0: dvc-0 {
1170 dmas = <&audma1 0xbc>;
1171 dma-names = "tx";
1172 };
1173 dvc1: dvc-1 {
1174 dmas = <&audma1 0xbe>;
1175 dma-names = "tx";
1176 };
1177 };
1178
1179 rcar_sound,mix {
1180 mix0: mix-0 { };
1181 mix1: mix-1 { };
1182 };
1183
1184 rcar_sound,ctu {
1185 ctu00: ctu-0 { };
1186 ctu01: ctu-1 { };
1187 ctu02: ctu-2 { };
1188 ctu03: ctu-3 { };
1189 ctu10: ctu-4 { };
1190 ctu11: ctu-5 { };
1191 ctu12: ctu-6 { };
1192 ctu13: ctu-7 { };
1193 };
1194
1195 rcar_sound,src {
1196 src0: src-0 {
1197 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1198 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1199 dma-names = "rx", "tx";
1200 };
1201 src1: src-1 {
1202 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1203 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1204 dma-names = "rx", "tx";
1205 };
1206 src2: src-2 {
1207 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1208 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1209 dma-names = "rx", "tx";
1210 };
1211 src3: src-3 {
1212 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1213 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1214 dma-names = "rx", "tx";
1215 };
1216 src4: src-4 {
1217 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1218 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1219 dma-names = "rx", "tx";
1220 };
1221 src5: src-5 {
1222 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1223 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1224 dma-names = "rx", "tx";
1225 };
1226 src6: src-6 {
1227 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1228 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1229 dma-names = "rx", "tx";
1230 };
1231 src7: src-7 {
1232 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1233 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1234 dma-names = "rx", "tx";
1235 };
1236 src8: src-8 {
1237 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1238 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1239 dma-names = "rx", "tx";
1240 };
1241 src9: src-9 {
1242 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
1243 dmas = <&audma0 0x97>, <&audma1 0xba>;
1244 dma-names = "rx", "tx";
1245 };
1246 };
1247
1248 rcar_sound,ssi {
1249 ssi0: ssi-0 {
1250 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
1251 dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
1252 dma-names = "rx", "tx", "rxu", "txu";
1253 };
1254 ssi1: ssi-1 {
1255 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
1256 dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
1257 dma-names = "rx", "tx", "rxu", "txu";
1258 };
1259 ssi2: ssi-2 {
1260 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
1261 dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
1262 dma-names = "rx", "tx", "rxu", "txu";
1263 };
1264 ssi3: ssi-3 {
1265 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1266 dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
1267 dma-names = "rx", "tx", "rxu", "txu";
1268 };
1269 ssi4: ssi-4 {
1270 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
1271 dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
1272 dma-names = "rx", "tx", "rxu", "txu";
1273 };
1274 ssi5: ssi-5 {
1275 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1276 dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
1277 dma-names = "rx", "tx", "rxu", "txu";
1278 };
1279 ssi6: ssi-6 {
1280 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
1281 dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
1282 dma-names = "rx", "tx", "rxu", "txu";
1283 };
1284 ssi7: ssi-7 {
1285 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
1286 dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
1287 dma-names = "rx", "tx", "rxu", "txu";
1288 };
1289 ssi8: ssi-8 {
1290 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
1291 dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
1292 dma-names = "rx", "tx", "rxu", "txu";
1293 };
1294 ssi9: ssi-9 {
1295 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
1296 dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
1297 dma-names = "rx", "tx", "rxu", "txu";
1298 };
1299 };
1300
1301 ports {
1302 #address-cells = <1>;
1303 #size-cells = <0>;
1304 port@0 {
1305 reg = <0>;
1306 };
1307 port@1 {
1308 reg = <1>;
1309 };
1310 };
1311 };
1312
1313 audma0: dma-controller@ec700000 {
1314 compatible = "renesas,dmac-r8a774a1",
1315 "renesas,rcar-dmac";
1316 reg = <0 0xec700000 0 0x10000>;
1317 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH
1318 GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
1319 GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
1320 GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
1321 GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
1322 GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
1323 GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
1324 GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
1325 GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
1326 GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
1327 GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
1328 GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
1329 GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
1330 GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH
1331 GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
1332 GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
1333 GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
1334 interrupt-names = "error",
1335 "ch0", "ch1", "ch2", "ch3",
1336 "ch4", "ch5", "ch6", "ch7",
1337 "ch8", "ch9", "ch10", "ch11",
1338 "ch12", "ch13", "ch14", "ch15";
1339 clocks = <&cpg CPG_MOD 502>;
1340 clock-names = "fck";
1341 power-domains = <&sysc 32>;
1342 resets = <&cpg 502>;
1343 #dma-cells = <1>;
1344 dma-channels = <16>;
1345 };
1346
1347 audma1: dma-controller@ec720000 {
1348 compatible = "renesas,dmac-r8a774a1",
1349 "renesas,rcar-dmac";
1350 reg = <0 0xec720000 0 0x10000>;
1351 interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH
1352 GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
1353 GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
1354 GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
1355 GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
1356 GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
1357 GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
1358 GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
1359 GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
1360 GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
1361 GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH
1362 GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
1363 GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
1364 GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH
1365 GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH
1366 GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH
1367 GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
1368 interrupt-names = "error",
1369 "ch0", "ch1", "ch2", "ch3",
1370 "ch4", "ch5", "ch6", "ch7",
1371 "ch8", "ch9", "ch10", "ch11",
1372 "ch12", "ch13", "ch14", "ch15";
1373 clocks = <&cpg CPG_MOD 501>;
1374 clock-names = "fck";
1375 power-domains = <&sysc 32>;
1376 resets = <&cpg 501>;
1377 #dma-cells = <1>;
1378 dma-channels = <16>;
1379 };
1380
1381 xhci0: usb@ee000000 {
1382 compatible = "renesas,xhci-r8a774a1",
1383 "renesas,rcar-gen3-xhci";
1384 reg = <0 0xee000000 0 0xc00>;
1385 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1386 clocks = <&cpg CPG_MOD 328>;
1387 power-domains = <&sysc 32>;
1388 resets = <&cpg 328>;
1389 status = "disabled";
1390 };
1391
1392 usb3_peri0: usb@ee020000 {
1393 compatible = "renesas,r8a774a1-usb3-peri",
1394 "renesas,rcar-gen3-usb3-peri";
1395 reg = <0 0xee020000 0 0x400>;
1396 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1397 clocks = <&cpg CPG_MOD 328>;
1398 power-domains = <&sysc 32>;
1399 resets = <&cpg 328>;
1400 status = "disabled";
1401 };
1402
1403 ohci0: usb@ee080000 {
1404 compatible = "generic-ohci";
1405 reg = <0 0xee080000 0 0x100>;
1406 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1407 clocks = <&cpg CPG_MOD 703>;
1408 phys = <&usb2_phy0>;
1409 phy-names = "usb";
1410 power-domains = <&sysc 32>;
1411 resets = <&cpg 703>;
1412 status = "disabled";
1413 };
1414
1415 ohci1: usb@ee0a0000 {
1416 compatible = "generic-ohci";
1417 reg = <0 0xee0a0000 0 0x100>;
1418 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1419 clocks = <&cpg CPG_MOD 702>;
1420 phys = <&usb2_phy1>;
1421 phy-names = "usb";
1422 power-domains = <&sysc 32>;
1423 resets = <&cpg 702>;
1424 status = "disabled";
1425 };
1426
1427 ehci0: usb@ee080100 {
1428 compatible = "generic-ehci";
1429 reg = <0 0xee080100 0 0x100>;
1430 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1431 clocks = <&cpg CPG_MOD 703>;
1432 phys = <&usb2_phy0>;
1433 phy-names = "usb";
1434 companion = <&ohci0>;
1435 power-domains = <&sysc 32>;
1436 resets = <&cpg 703>;
1437 status = "disabled";
1438 };
1439
1440 ehci1: usb@ee0a0100 {
1441 compatible = "generic-ehci";
1442 reg = <0 0xee0a0100 0 0x100>;
1443 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1444 clocks = <&cpg CPG_MOD 702>;
1445 phys = <&usb2_phy1>;
1446 phy-names = "usb";
1447 companion = <&ohci1>;
1448 power-domains = <&sysc 32>;
1449 resets = <&cpg 702>;
1450 status = "disabled";
1451 };
1452
1453 usb2_phy0: usb-phy@ee080200 {
1454 compatible = "renesas,usb2-phy-r8a774a1",
1455 "renesas,rcar-gen3-usb2-phy";
1456 reg = <0 0xee080200 0 0x700>;
1457 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1458 clocks = <&cpg CPG_MOD 703>;
1459 power-domains = <&sysc 32>;
1460 resets = <&cpg 703>;
1461 #phy-cells = <0>;
1462 status = "disabled";
1463 };
1464
1465 usb2_phy1: usb-phy@ee0a0200 {
1466 compatible = "renesas,usb2-phy-r8a774a1",
1467 "renesas,rcar-gen3-usb2-phy";
1468 reg = <0 0xee0a0200 0 0x700>;
1469 clocks = <&cpg CPG_MOD 702>;
1470 power-domains = <&sysc 32>;
1471 resets = <&cpg 702>;
1472 #phy-cells = <0>;
1473 status = "disabled";
1474 };
1475
1476 sdhi0: sd@ee100000 {
1477 compatible = "renesas,sdhi-r8a774a1",
1478 "renesas,rcar-gen3-sdhi";
1479 reg = <0 0xee100000 0 0x2000>;
1480 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
1481 clocks = <&cpg CPG_MOD 314>;
1482 max-frequency = <200000000>;
1483 power-domains = <&sysc 32>;
1484 resets = <&cpg 314>;
1485 status = "disabled";
1486 };
1487
1488 sdhi1: sd@ee120000 {
1489 compatible = "renesas,sdhi-r8a774a1",
1490 "renesas,rcar-gen3-sdhi";
1491 reg = <0 0xee120000 0 0x2000>;
1492 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
1493 clocks = <&cpg CPG_MOD 313>;
1494 max-frequency = <200000000>;
1495 power-domains = <&sysc 32>;
1496 resets = <&cpg 313>;
1497 status = "disabled";
1498 };
1499
1500 sdhi2: sd@ee140000 {
1501 compatible = "renesas,sdhi-r8a774a1",
1502 "renesas,rcar-gen3-sdhi";
1503 reg = <0 0xee140000 0 0x2000>;
1504 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
1505 clocks = <&cpg CPG_MOD 312>;
1506 max-frequency = <200000000>;
1507 power-domains = <&sysc 32>;
1508 resets = <&cpg 312>;
1509 status = "disabled";
1510 };
1511
1512 sdhi3: sd@ee160000 {
1513 compatible = "renesas,sdhi-r8a774a1",
1514 "renesas,rcar-gen3-sdhi";
1515 reg = <0 0xee160000 0 0x2000>;
1516 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
1517 clocks = <&cpg CPG_MOD 311>;
1518 max-frequency = <200000000>;
1519 power-domains = <&sysc 32>;
1520 resets = <&cpg 311>;
1521 status = "disabled";
1522 };
1523
1524 gic: interrupt-controller@f1010000 {
1525 compatible = "arm,gic-400";
1526 #interrupt-cells = <3>;
1527 #address-cells = <0>;
1528 interrupt-controller;
1529 reg = <0x0 0xf1010000 0 0x1000>,
1530 <0x0 0xf1020000 0 0x20000>,
1531 <0x0 0xf1040000 0 0x20000>,
1532 <0x0 0xf1060000 0 0x20000>;
1533 interrupts = <GIC_PPI 9
1534 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
1535 clocks = <&cpg CPG_MOD 408>;
1536 clock-names = "clk";
1537 power-domains = <&sysc 32>;
1538 resets = <&cpg 408>;
1539 };
1540
1541 fcpf0: fcp@fe950000 {
1542 compatible = "renesas,fcpf";
1543 reg = <0 0xfe950000 0 0x200>;
1544 clocks = <&cpg CPG_MOD 615>;
1545 power-domains = <&sysc 14>;
1546 resets = <&cpg 615>;
1547 };
1548
1549 fcpvb0: fcp@fe96f000 {
1550 compatible = "renesas,fcpv";
1551 reg = <0 0xfe96f000 0 0x200>;
1552 clocks = <&cpg CPG_MOD 607>;
1553 power-domains = <&sysc 14>;
1554 resets = <&cpg 607>;
1555 };
1556
1557 fcpvd0: fcp@fea27000 {
1558 compatible = "renesas,fcpv";
1559 reg = <0 0xfea27000 0 0x200>;
1560 clocks = <&cpg CPG_MOD 603>;
1561 power-domains = <&sysc 32>;
1562 resets = <&cpg 603>;
1563 iommus = <&ipmmu_vi0 8>;
1564 };
1565
1566 fcpvd1: fcp@fea2f000 {
1567 compatible = "renesas,fcpv";
1568 reg = <0 0xfea2f000 0 0x200>;
1569 clocks = <&cpg CPG_MOD 602>;
1570 power-domains = <&sysc 32>;
1571 resets = <&cpg 602>;
1572 iommus = <&ipmmu_vi0 9>;
1573 };
1574
1575 fcpvd2: fcp@fea37000 {
1576 compatible = "renesas,fcpv";
1577 reg = <0 0xfea37000 0 0x200>;
1578 clocks = <&cpg CPG_MOD 601>;
1579 power-domains = <&sysc 32>;
1580 resets = <&cpg 601>;
1581 iommus = <&ipmmu_vi0 10>;
1582 };
1583
1584 fcpvi0: fcp@fe9af000 {
1585 compatible = "renesas,fcpv";
1586 reg = <0 0xfe9af000 0 0x200>;
1587 clocks = <&cpg CPG_MOD 611>;
1588 power-domains = <&sysc 14>;
1589 resets = <&cpg 611>;
1590 iommus = <&ipmmu_vc0 19>;
1591 };
1592
1593 prr: chipid@fff00044 {
1594 compatible = "renesas,prr";
1595 reg = <0 0xfff00044 0 4>;
1596 };
1597 };
1598
1599 thermal-zones {
1600 sensor_thermal1: sensor-thermal1 {
1601 polling-delay-passive = <250>;
1602 polling-delay = <1000>;
1603 thermal-sensors = <&tsc 0>;
1604
1605 trips {
1606 sensor1_crit: sensor1-crit {
1607 temperature = <120000>;
1608 hysteresis = <1000>;
1609 type = "critical";
1610 };
1611 };
1612 };
1613
1614 sensor_thermal2: sensor-thermal2 {
1615 polling-delay-passive = <250>;
1616 polling-delay = <1000>;
1617 thermal-sensors = <&tsc 1>;
1618
1619 trips {
1620 sensor2_crit: sensor2-crit {
1621 temperature = <120000>;
1622 hysteresis = <1000>;
1623 type = "critical";
1624 };
1625 };
1626
1627 };
1628
1629 sensor_thermal3: sensor-thermal3 {
1630 polling-delay-passive = <250>;
1631 polling-delay = <1000>;
1632 thermal-sensors = <&tsc 2>;
1633
1634 trips {
1635 sensor3_crit: sensor3-crit {
1636 temperature = <120000>;
1637 hysteresis = <1000>;
1638 type = "critical";
1639 };
1640 };
1641 };
1642 };
1643
1644 timer {
1645 compatible = "arm,armv8-timer";
1646 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
1647 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
1648 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
1649 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
1650 };
1651
1652 /* External USB clocks - can be overridden by the board */
1653 usb3s0_clk: usb3s0 {
1654 compatible = "fixed-clock";
1655 #clock-cells = <0>;
1656 clock-frequency = <0>;
1657 };
1658
1659 usb_extal_clk: usb_extal {
1660 compatible = "fixed-clock";
1661 #clock-cells = <0>;
1662 clock-frequency = <0>;
1663 };
1664};
diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts
index 6b5fa91f1d5d..0895503b69d0 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts
@@ -40,12 +40,11 @@
40 <&cpg CPG_MOD 723>, 40 <&cpg CPG_MOD 723>,
41 <&cpg CPG_MOD 722>, 41 <&cpg CPG_MOD 722>,
42 <&cpg CPG_MOD 721>, 42 <&cpg CPG_MOD 721>,
43 <&cpg CPG_MOD 727>,
44 <&versaclock5 1>, 43 <&versaclock5 1>,
45 <&x21_clk>, 44 <&x21_clk>,
46 <&x22_clk>, 45 <&x22_clk>,
47 <&versaclock5 2>; 46 <&versaclock5 2>;
48 clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0", 47 clock-names = "du.0", "du.1", "du.2", "du.3",
49 "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3"; 48 "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";
50}; 49};
51 50
diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
index 7b2fbaec9aef..0fb84c219b2f 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
@@ -1,6 +1,6 @@
1// SPDX-License-Identifier: GPL-2.0 1// SPDX-License-Identifier: GPL-2.0
2/* 2/*
3 * Device Tree Source for the r8a7795 ES1.x SoC 3 * Device Tree Source for the R-Car H3 (R8A77950) ES1.x SoC
4 * 4 *
5 * Copyright (C) 2015 Renesas Electronics Corp. 5 * Copyright (C) 2015 Renesas Electronics Corp.
6 */ 6 */
@@ -232,7 +232,7 @@
232 port@1 { 232 port@1 {
233 vin0csi21: endpoint@1 { 233 vin0csi21: endpoint@1 {
234 reg = <1>; 234 reg = <1>;
235 remote-endpoint= <&csi21vin0>; 235 remote-endpoint = <&csi21vin0>;
236 }; 236 };
237 }; 237 };
238 }; 238 };
@@ -243,7 +243,7 @@
243 port@1 { 243 port@1 {
244 vin1csi21: endpoint@1 { 244 vin1csi21: endpoint@1 {
245 reg = <1>; 245 reg = <1>;
246 remote-endpoint= <&csi21vin1>; 246 remote-endpoint = <&csi21vin1>;
247 }; 247 };
248 }; 248 };
249 }; 249 };
@@ -254,7 +254,7 @@
254 port@1 { 254 port@1 {
255 vin2csi21: endpoint@1 { 255 vin2csi21: endpoint@1 {
256 reg = <1>; 256 reg = <1>;
257 remote-endpoint= <&csi21vin2>; 257 remote-endpoint = <&csi21vin2>;
258 }; 258 };
259 }; 259 };
260 }; 260 };
@@ -265,7 +265,7 @@
265 port@1 { 265 port@1 {
266 vin3csi21: endpoint@1 { 266 vin3csi21: endpoint@1 {
267 reg = <1>; 267 reg = <1>;
268 remote-endpoint= <&csi21vin3>; 268 remote-endpoint = <&csi21vin3>;
269 }; 269 };
270 }; 270 };
271 }; 271 };
@@ -276,7 +276,7 @@
276 port@1 { 276 port@1 {
277 vin4csi21: endpoint@1 { 277 vin4csi21: endpoint@1 {
278 reg = <1>; 278 reg = <1>;
279 remote-endpoint= <&csi21vin4>; 279 remote-endpoint = <&csi21vin4>;
280 }; 280 };
281 }; 281 };
282 }; 282 };
@@ -287,7 +287,7 @@
287 port@1 { 287 port@1 {
288 vin5csi21: endpoint@1 { 288 vin5csi21: endpoint@1 {
289 reg = <1>; 289 reg = <1>;
290 remote-endpoint= <&csi21vin5>; 290 remote-endpoint = <&csi21vin5>;
291 }; 291 };
292 }; 292 };
293 }; 293 };
@@ -298,7 +298,7 @@
298 port@1 { 298 port@1 {
299 vin6csi21: endpoint@1 { 299 vin6csi21: endpoint@1 {
300 reg = <1>; 300 reg = <1>;
301 remote-endpoint= <&csi21vin6>; 301 remote-endpoint = <&csi21vin6>;
302 }; 302 };
303 }; 303 };
304 }; 304 };
@@ -309,7 +309,7 @@
309 port@1 { 309 port@1 {
310 vin7csi21: endpoint@1 { 310 vin7csi21: endpoint@1 {
311 reg = <1>; 311 reg = <1>;
312 remote-endpoint= <&csi21vin7>; 312 remote-endpoint = <&csi21vin7>;
313 }; 313 };
314 }; 314 };
315 }; 315 };
diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
index df50bf46406e..54515eaf0310 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
@@ -41,11 +41,10 @@
41 <&cpg CPG_MOD 723>, 41 <&cpg CPG_MOD 723>,
42 <&cpg CPG_MOD 722>, 42 <&cpg CPG_MOD 722>,
43 <&cpg CPG_MOD 721>, 43 <&cpg CPG_MOD 721>,
44 <&cpg CPG_MOD 727>,
45 <&versaclock5 1>, 44 <&versaclock5 1>,
46 <&versaclock5 3>, 45 <&versaclock5 3>,
47 <&versaclock5 4>, 46 <&versaclock5 4>,
48 <&versaclock5 2>; 47 <&versaclock5 2>;
49 clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0", 48 clock-names = "du.0", "du.1", "du.2", "du.3",
50 "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3"; 49 "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";
51}; 50};
diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
index 446822f5751c..1620e8d8dacc 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
@@ -40,12 +40,11 @@
40 <&cpg CPG_MOD 723>, 40 <&cpg CPG_MOD 723>,
41 <&cpg CPG_MOD 722>, 41 <&cpg CPG_MOD 722>,
42 <&cpg CPG_MOD 721>, 42 <&cpg CPG_MOD 721>,
43 <&cpg CPG_MOD 727>,
44 <&versaclock5 1>, 43 <&versaclock5 1>,
45 <&x21_clk>, 44 <&x21_clk>,
46 <&x22_clk>, 45 <&x22_clk>,
47 <&versaclock5 2>; 46 <&versaclock5 2>;
48 clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0", 47 clock-names = "du.0", "du.1", "du.2", "du.3",
49 "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3"; 48 "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";
50}; 49};
51 50
diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts
index 8ded64d0a4d5..cf08a119eec0 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts
@@ -40,12 +40,11 @@
40 <&cpg CPG_MOD 723>, 40 <&cpg CPG_MOD 723>,
41 <&cpg CPG_MOD 722>, 41 <&cpg CPG_MOD 722>,
42 <&cpg CPG_MOD 721>, 42 <&cpg CPG_MOD 721>,
43 <&cpg CPG_MOD 727>,
44 <&versaclock6 1>, 43 <&versaclock6 1>,
45 <&x21_clk>, 44 <&x21_clk>,
46 <&x22_clk>, 45 <&x22_clk>,
47 <&versaclock6 2>; 46 <&versaclock6 2>;
48 clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0", 47 clock-names = "du.0", "du.1", "du.2", "du.3",
49 "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3"; 48 "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";
50}; 49};
51 50
@@ -152,6 +151,15 @@
152 }; 151 };
153}; 152};
154 153
154&pca9654 {
155 pcie_sata_switch {
156 gpio-hog;
157 gpios = <7 GPIO_ACTIVE_HIGH>;
158 output-low; /* enable SATA by default */
159 line-name = "PCIE/SATA switch";
160 };
161};
162
155&pfc { 163&pfc {
156 usb2_pins: usb2 { 164 usb2_pins: usb2 {
157 groups = "usb2"; 165 groups = "usb2";
@@ -176,6 +184,11 @@
176 }; 184 };
177}; 185};
178 186
187/* SW12-7 must be set 'Off' (MD12 set to 1) which is not the default! */
188&sata {
189 status = "okay";
190};
191
179&usb2_phy2 { 192&usb2_phy2 {
180 pinctrl-0 = <&usb2_pins>; 193 pinctrl-0 = <&usb2_pins>;
181 pinctrl-names = "default"; 194 pinctrl-names = "default";
diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index fb9d08ad7659..abb361e41ef6 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -1,6 +1,6 @@
1// SPDX-License-Identifier: GPL-2.0 1// SPDX-License-Identifier: GPL-2.0
2/* 2/*
3 * Device Tree Source for the r8a7795 SoC 3 * Device Tree Source for the R-Car H3 (R8A77950) SoC
4 * 4 *
5 * Copyright (C) 2015 Renesas Electronics Corp. 5 * Copyright (C) 2015 Renesas Electronics Corp.
6 */ 6 */
@@ -123,7 +123,7 @@
123 power-domains = <&sysc R8A7795_PD_CA57_CPU0>; 123 power-domains = <&sysc R8A7795_PD_CA57_CPU0>;
124 next-level-cache = <&L2_CA57>; 124 next-level-cache = <&L2_CA57>;
125 enable-method = "psci"; 125 enable-method = "psci";
126 clocks =<&cpg CPG_CORE R8A7795_CLK_Z>; 126 clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
127 operating-points-v2 = <&cluster0_opp>; 127 operating-points-v2 = <&cluster0_opp>;
128 #cooling-cells = <2>; 128 #cooling-cells = <2>;
129 }; 129 };
@@ -135,7 +135,7 @@
135 power-domains = <&sysc R8A7795_PD_CA57_CPU1>; 135 power-domains = <&sysc R8A7795_PD_CA57_CPU1>;
136 next-level-cache = <&L2_CA57>; 136 next-level-cache = <&L2_CA57>;
137 enable-method = "psci"; 137 enable-method = "psci";
138 clocks =<&cpg CPG_CORE R8A7795_CLK_Z>; 138 clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
139 operating-points-v2 = <&cluster0_opp>; 139 operating-points-v2 = <&cluster0_opp>;
140 #cooling-cells = <2>; 140 #cooling-cells = <2>;
141 }; 141 };
@@ -147,7 +147,7 @@
147 power-domains = <&sysc R8A7795_PD_CA57_CPU2>; 147 power-domains = <&sysc R8A7795_PD_CA57_CPU2>;
148 next-level-cache = <&L2_CA57>; 148 next-level-cache = <&L2_CA57>;
149 enable-method = "psci"; 149 enable-method = "psci";
150 clocks =<&cpg CPG_CORE R8A7795_CLK_Z>; 150 clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
151 operating-points-v2 = <&cluster0_opp>; 151 operating-points-v2 = <&cluster0_opp>;
152 #cooling-cells = <2>; 152 #cooling-cells = <2>;
153 }; 153 };
@@ -159,7 +159,7 @@
159 power-domains = <&sysc R8A7795_PD_CA57_CPU3>; 159 power-domains = <&sysc R8A7795_PD_CA57_CPU3>;
160 next-level-cache = <&L2_CA57>; 160 next-level-cache = <&L2_CA57>;
161 enable-method = "psci"; 161 enable-method = "psci";
162 clocks =<&cpg CPG_CORE R8A7795_CLK_Z>; 162 clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
163 operating-points-v2 = <&cluster0_opp>; 163 operating-points-v2 = <&cluster0_opp>;
164 #cooling-cells = <2>; 164 #cooling-cells = <2>;
165 }; 165 };
@@ -171,7 +171,7 @@
171 power-domains = <&sysc R8A7795_PD_CA53_CPU0>; 171 power-domains = <&sysc R8A7795_PD_CA53_CPU0>;
172 next-level-cache = <&L2_CA53>; 172 next-level-cache = <&L2_CA53>;
173 enable-method = "psci"; 173 enable-method = "psci";
174 clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>; 174 clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
175 operating-points-v2 = <&cluster1_opp>; 175 operating-points-v2 = <&cluster1_opp>;
176 }; 176 };
177 177
@@ -182,7 +182,7 @@
182 power-domains = <&sysc R8A7795_PD_CA53_CPU1>; 182 power-domains = <&sysc R8A7795_PD_CA53_CPU1>;
183 next-level-cache = <&L2_CA53>; 183 next-level-cache = <&L2_CA53>;
184 enable-method = "psci"; 184 enable-method = "psci";
185 clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>; 185 clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
186 operating-points-v2 = <&cluster1_opp>; 186 operating-points-v2 = <&cluster1_opp>;
187 }; 187 };
188 188
@@ -193,7 +193,7 @@
193 power-domains = <&sysc R8A7795_PD_CA53_CPU2>; 193 power-domains = <&sysc R8A7795_PD_CA53_CPU2>;
194 next-level-cache = <&L2_CA53>; 194 next-level-cache = <&L2_CA53>;
195 enable-method = "psci"; 195 enable-method = "psci";
196 clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>; 196 clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
197 operating-points-v2 = <&cluster1_opp>; 197 operating-points-v2 = <&cluster1_opp>;
198 }; 198 };
199 199
@@ -204,7 +204,7 @@
204 power-domains = <&sysc R8A7795_PD_CA53_CPU3>; 204 power-domains = <&sysc R8A7795_PD_CA53_CPU3>;
205 next-level-cache = <&L2_CA53>; 205 next-level-cache = <&L2_CA53>;
206 enable-method = "psci"; 206 enable-method = "psci";
207 clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>; 207 clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
208 operating-points-v2 = <&cluster1_opp>; 208 operating-points-v2 = <&cluster1_opp>;
209 }; 209 };
210 210
@@ -525,15 +525,6 @@
525 status = "disabled"; 525 status = "disabled";
526 }; 526 };
527 527
528 arm_cc630p: crypto@e6601000 {
529 compatible = "arm,cryptocell-630p-ree";
530 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
531 reg = <0x0 0xe6601000 0 0x1000>;
532 clocks = <&cpg CPG_MOD 229>;
533 resets = <&cpg 229>;
534 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
535 };
536
537 i2c3: i2c@e66d0000 { 528 i2c3: i2c@e66d0000 {
538 #address-cells = <1>; 529 #address-cells = <1>;
539 #size-cells = <0>; 530 #size-cells = <0>;
@@ -805,6 +796,15 @@
805 status = "disabled"; 796 status = "disabled";
806 }; 797 };
807 798
799 arm_cc630p: crypto@e6601000 {
800 compatible = "arm,cryptocell-630p-ree";
801 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
802 reg = <0x0 0xe6601000 0 0x1000>;
803 clocks = <&cpg CPG_MOD 229>;
804 resets = <&cpg 229>;
805 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
806 };
807
808 dmac0: dma-controller@e6700000 { 808 dmac0: dma-controller@e6700000 {
809 compatible = "renesas,dmac-r8a7795", 809 compatible = "renesas,dmac-r8a7795",
810 "renesas,rcar-dmac"; 810 "renesas,rcar-dmac";
@@ -1425,11 +1425,11 @@
1425 1425
1426 vin0csi20: endpoint@0 { 1426 vin0csi20: endpoint@0 {
1427 reg = <0>; 1427 reg = <0>;
1428 remote-endpoint= <&csi20vin0>; 1428 remote-endpoint = <&csi20vin0>;
1429 }; 1429 };
1430 vin0csi40: endpoint@2 { 1430 vin0csi40: endpoint@2 {
1431 reg = <2>; 1431 reg = <2>;
1432 remote-endpoint= <&csi40vin0>; 1432 remote-endpoint = <&csi40vin0>;
1433 }; 1433 };
1434 }; 1434 };
1435 }; 1435 };
@@ -1457,11 +1457,11 @@
1457 1457
1458 vin1csi20: endpoint@0 { 1458 vin1csi20: endpoint@0 {
1459 reg = <0>; 1459 reg = <0>;
1460 remote-endpoint= <&csi20vin1>; 1460 remote-endpoint = <&csi20vin1>;
1461 }; 1461 };
1462 vin1csi40: endpoint@2 { 1462 vin1csi40: endpoint@2 {
1463 reg = <2>; 1463 reg = <2>;
1464 remote-endpoint= <&csi40vin1>; 1464 remote-endpoint = <&csi40vin1>;
1465 }; 1465 };
1466 }; 1466 };
1467 }; 1467 };
@@ -1489,11 +1489,11 @@
1489 1489
1490 vin2csi20: endpoint@0 { 1490 vin2csi20: endpoint@0 {
1491 reg = <0>; 1491 reg = <0>;
1492 remote-endpoint= <&csi20vin2>; 1492 remote-endpoint = <&csi20vin2>;
1493 }; 1493 };
1494 vin2csi40: endpoint@2 { 1494 vin2csi40: endpoint@2 {
1495 reg = <2>; 1495 reg = <2>;
1496 remote-endpoint= <&csi40vin2>; 1496 remote-endpoint = <&csi40vin2>;
1497 }; 1497 };
1498 }; 1498 };
1499 }; 1499 };
@@ -1521,11 +1521,11 @@
1521 1521
1522 vin3csi20: endpoint@0 { 1522 vin3csi20: endpoint@0 {
1523 reg = <0>; 1523 reg = <0>;
1524 remote-endpoint= <&csi20vin3>; 1524 remote-endpoint = <&csi20vin3>;
1525 }; 1525 };
1526 vin3csi40: endpoint@2 { 1526 vin3csi40: endpoint@2 {
1527 reg = <2>; 1527 reg = <2>;
1528 remote-endpoint= <&csi40vin3>; 1528 remote-endpoint = <&csi40vin3>;
1529 }; 1529 };
1530 }; 1530 };
1531 }; 1531 };
@@ -1553,11 +1553,11 @@
1553 1553
1554 vin4csi20: endpoint@0 { 1554 vin4csi20: endpoint@0 {
1555 reg = <0>; 1555 reg = <0>;
1556 remote-endpoint= <&csi20vin4>; 1556 remote-endpoint = <&csi20vin4>;
1557 }; 1557 };
1558 vin4csi41: endpoint@3 { 1558 vin4csi41: endpoint@3 {
1559 reg = <3>; 1559 reg = <3>;
1560 remote-endpoint= <&csi41vin4>; 1560 remote-endpoint = <&csi41vin4>;
1561 }; 1561 };
1562 }; 1562 };
1563 }; 1563 };
@@ -1585,11 +1585,11 @@
1585 1585
1586 vin5csi20: endpoint@0 { 1586 vin5csi20: endpoint@0 {
1587 reg = <0>; 1587 reg = <0>;
1588 remote-endpoint= <&csi20vin5>; 1588 remote-endpoint = <&csi20vin5>;
1589 }; 1589 };
1590 vin5csi41: endpoint@3 { 1590 vin5csi41: endpoint@3 {
1591 reg = <3>; 1591 reg = <3>;
1592 remote-endpoint= <&csi41vin5>; 1592 remote-endpoint = <&csi41vin5>;
1593 }; 1593 };
1594 }; 1594 };
1595 }; 1595 };
@@ -1617,11 +1617,11 @@
1617 1617
1618 vin6csi20: endpoint@0 { 1618 vin6csi20: endpoint@0 {
1619 reg = <0>; 1619 reg = <0>;
1620 remote-endpoint= <&csi20vin6>; 1620 remote-endpoint = <&csi20vin6>;
1621 }; 1621 };
1622 vin6csi41: endpoint@3 { 1622 vin6csi41: endpoint@3 {
1623 reg = <3>; 1623 reg = <3>;
1624 remote-endpoint= <&csi41vin6>; 1624 remote-endpoint = <&csi41vin6>;
1625 }; 1625 };
1626 }; 1626 };
1627 }; 1627 };
@@ -1649,11 +1649,11 @@
1649 1649
1650 vin7csi20: endpoint@0 { 1650 vin7csi20: endpoint@0 {
1651 reg = <0>; 1651 reg = <0>;
1652 remote-endpoint= <&csi20vin7>; 1652 remote-endpoint = <&csi20vin7>;
1653 }; 1653 };
1654 vin7csi41: endpoint@3 { 1654 vin7csi41: endpoint@3 {
1655 reg = <3>; 1655 reg = <3>;
1656 remote-endpoint= <&csi41vin7>; 1656 remote-endpoint = <&csi41vin7>;
1657 }; 1657 };
1658 }; 1658 };
1659 }; 1659 };
@@ -2782,9 +2782,7 @@
2782 2782
2783 du: display@feb00000 { 2783 du: display@feb00000 {
2784 compatible = "renesas,du-r8a7795"; 2784 compatible = "renesas,du-r8a7795";
2785 reg = <0 0xfeb00000 0 0x80000>, 2785 reg = <0 0xfeb00000 0 0x80000>;
2786 <0 0xfeb90000 0 0x14>;
2787 reg-names = "du", "lvds.0";
2788 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 2786 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
2789 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2787 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
2790 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, 2788 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
@@ -2792,9 +2790,8 @@
2792 clocks = <&cpg CPG_MOD 724>, 2790 clocks = <&cpg CPG_MOD 724>,
2793 <&cpg CPG_MOD 723>, 2791 <&cpg CPG_MOD 723>,
2794 <&cpg CPG_MOD 722>, 2792 <&cpg CPG_MOD 722>,
2795 <&cpg CPG_MOD 721>, 2793 <&cpg CPG_MOD 721>;
2796 <&cpg CPG_MOD 727>; 2794 clock-names = "du.0", "du.1", "du.2", "du.3";
2797 clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0";
2798 vsps = <&vspd0 0 &vspd1 0 &vspd2 0 &vspd0 1>; 2795 vsps = <&vspd0 0 &vspd1 0 &vspd2 0 &vspd0 1>;
2799 status = "disabled"; 2796 status = "disabled";
2800 2797
@@ -2822,6 +2819,33 @@
2822 port@3 { 2819 port@3 {
2823 reg = <3>; 2820 reg = <3>;
2824 du_out_lvds0: endpoint { 2821 du_out_lvds0: endpoint {
2822 remote-endpoint = <&lvds0_in>;
2823 };
2824 };
2825 };
2826 };
2827
2828 lvds0: lvds@feb90000 {
2829 compatible = "renesas,r8a7795-lvds";
2830 reg = <0 0xfeb90000 0 0x14>;
2831 clocks = <&cpg CPG_MOD 727>;
2832 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
2833 resets = <&cpg 727>;
2834 status = "disabled";
2835
2836 ports {
2837 #address-cells = <1>;
2838 #size-cells = <0>;
2839
2840 port@0 {
2841 reg = <0>;
2842 lvds0_in: endpoint {
2843 remote-endpoint = <&du_out_lvds0>;
2844 };
2845 };
2846 port@1 {
2847 reg = <1>;
2848 lvds0_out: endpoint {
2825 }; 2849 };
2826 }; 2850 };
2827 }; 2851 };
diff --git a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
index cbd8acbf537e..9e4594c27fa6 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
@@ -30,10 +30,9 @@
30 clocks = <&cpg CPG_MOD 724>, 30 clocks = <&cpg CPG_MOD 724>,
31 <&cpg CPG_MOD 723>, 31 <&cpg CPG_MOD 723>,
32 <&cpg CPG_MOD 722>, 32 <&cpg CPG_MOD 722>,
33 <&cpg CPG_MOD 727>,
34 <&versaclock5 1>, 33 <&versaclock5 1>,
35 <&versaclock5 3>, 34 <&versaclock5 3>,
36 <&versaclock5 2>; 35 <&versaclock5 2>;
37 clock-names = "du.0", "du.1", "du.2", "lvds.0", 36 clock-names = "du.0", "du.1", "du.2",
38 "dclkin.0", "dclkin.1", "dclkin.2"; 37 "dclkin.0", "dclkin.1", "dclkin.2";
39}; 38};
diff --git a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts
index 052d72acc862..b4f9567cb9f8 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts
@@ -29,11 +29,10 @@
29 clocks = <&cpg CPG_MOD 724>, 29 clocks = <&cpg CPG_MOD 724>,
30 <&cpg CPG_MOD 723>, 30 <&cpg CPG_MOD 723>,
31 <&cpg CPG_MOD 722>, 31 <&cpg CPG_MOD 722>,
32 <&cpg CPG_MOD 727>,
33 <&versaclock5 1>, 32 <&versaclock5 1>,
34 <&x21_clk>, 33 <&x21_clk>,
35 <&versaclock5 2>; 34 <&versaclock5 2>;
36 clock-names = "du.0", "du.1", "du.2", "lvds.0", 35 clock-names = "du.0", "du.1", "du.2",
37 "dclkin.0", "dclkin.1", "dclkin.2"; 36 "dclkin.0", "dclkin.1", "dclkin.2";
38}; 37};
39 38
diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
index cbd35c00b4af..28a0794a4190 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
@@ -1,6 +1,6 @@
1// SPDX-License-Identifier: GPL-2.0 1// SPDX-License-Identifier: GPL-2.0
2/* 2/*
3 * Device Tree Source for the r8a7796 SoC 3 * Device Tree Source for the R-Car M3-W (R8A77960) SoC
4 * 4 *
5 * Copyright (C) 2016-2017 Renesas Electronics Corp. 5 * Copyright (C) 2016-2017 Renesas Electronics Corp.
6 */ 6 */
@@ -134,7 +134,7 @@
134 power-domains = <&sysc R8A7796_PD_CA57_CPU0>; 134 power-domains = <&sysc R8A7796_PD_CA57_CPU0>;
135 next-level-cache = <&L2_CA57>; 135 next-level-cache = <&L2_CA57>;
136 enable-method = "psci"; 136 enable-method = "psci";
137 clocks =<&cpg CPG_CORE R8A7796_CLK_Z>; 137 clocks = <&cpg CPG_CORE R8A7796_CLK_Z>;
138 operating-points-v2 = <&cluster0_opp>; 138 operating-points-v2 = <&cluster0_opp>;
139 #cooling-cells = <2>; 139 #cooling-cells = <2>;
140 }; 140 };
@@ -146,7 +146,7 @@
146 power-domains = <&sysc R8A7796_PD_CA57_CPU1>; 146 power-domains = <&sysc R8A7796_PD_CA57_CPU1>;
147 next-level-cache = <&L2_CA57>; 147 next-level-cache = <&L2_CA57>;
148 enable-method = "psci"; 148 enable-method = "psci";
149 clocks =<&cpg CPG_CORE R8A7796_CLK_Z>; 149 clocks = <&cpg CPG_CORE R8A7796_CLK_Z>;
150 operating-points-v2 = <&cluster0_opp>; 150 operating-points-v2 = <&cluster0_opp>;
151 #cooling-cells = <2>; 151 #cooling-cells = <2>;
152 }; 152 };
@@ -158,7 +158,7 @@
158 power-domains = <&sysc R8A7796_PD_CA53_CPU0>; 158 power-domains = <&sysc R8A7796_PD_CA53_CPU0>;
159 next-level-cache = <&L2_CA53>; 159 next-level-cache = <&L2_CA53>;
160 enable-method = "psci"; 160 enable-method = "psci";
161 clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>; 161 clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
162 operating-points-v2 = <&cluster1_opp>; 162 operating-points-v2 = <&cluster1_opp>;
163 }; 163 };
164 164
@@ -169,7 +169,7 @@
169 power-domains = <&sysc R8A7796_PD_CA53_CPU1>; 169 power-domains = <&sysc R8A7796_PD_CA53_CPU1>;
170 next-level-cache = <&L2_CA53>; 170 next-level-cache = <&L2_CA53>;
171 enable-method = "psci"; 171 enable-method = "psci";
172 clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>; 172 clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
173 operating-points-v2 = <&cluster1_opp>; 173 operating-points-v2 = <&cluster1_opp>;
174 }; 174 };
175 175
@@ -180,7 +180,7 @@
180 power-domains = <&sysc R8A7796_PD_CA53_CPU2>; 180 power-domains = <&sysc R8A7796_PD_CA53_CPU2>;
181 next-level-cache = <&L2_CA53>; 181 next-level-cache = <&L2_CA53>;
182 enable-method = "psci"; 182 enable-method = "psci";
183 clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>; 183 clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
184 operating-points-v2 = <&cluster1_opp>; 184 operating-points-v2 = <&cluster1_opp>;
185 }; 185 };
186 186
@@ -191,7 +191,7 @@
191 power-domains = <&sysc R8A7796_PD_CA53_CPU3>; 191 power-domains = <&sysc R8A7796_PD_CA53_CPU3>;
192 next-level-cache = <&L2_CA53>; 192 next-level-cache = <&L2_CA53>;
193 enable-method = "psci"; 193 enable-method = "psci";
194 clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>; 194 clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
195 operating-points-v2 = <&cluster1_opp>; 195 operating-points-v2 = <&cluster1_opp>;
196 }; 196 };
197 197
@@ -1299,11 +1299,11 @@
1299 1299
1300 vin0csi20: endpoint@0 { 1300 vin0csi20: endpoint@0 {
1301 reg = <0>; 1301 reg = <0>;
1302 remote-endpoint= <&csi20vin0>; 1302 remote-endpoint = <&csi20vin0>;
1303 }; 1303 };
1304 vin0csi40: endpoint@2 { 1304 vin0csi40: endpoint@2 {
1305 reg = <2>; 1305 reg = <2>;
1306 remote-endpoint= <&csi40vin0>; 1306 remote-endpoint = <&csi40vin0>;
1307 }; 1307 };
1308 }; 1308 };
1309 }; 1309 };
@@ -1331,11 +1331,11 @@
1331 1331
1332 vin1csi20: endpoint@0 { 1332 vin1csi20: endpoint@0 {
1333 reg = <0>; 1333 reg = <0>;
1334 remote-endpoint= <&csi20vin1>; 1334 remote-endpoint = <&csi20vin1>;
1335 }; 1335 };
1336 vin1csi40: endpoint@2 { 1336 vin1csi40: endpoint@2 {
1337 reg = <2>; 1337 reg = <2>;
1338 remote-endpoint= <&csi40vin1>; 1338 remote-endpoint = <&csi40vin1>;
1339 }; 1339 };
1340 }; 1340 };
1341 }; 1341 };
@@ -1363,11 +1363,11 @@
1363 1363
1364 vin2csi20: endpoint@0 { 1364 vin2csi20: endpoint@0 {
1365 reg = <0>; 1365 reg = <0>;
1366 remote-endpoint= <&csi20vin2>; 1366 remote-endpoint = <&csi20vin2>;
1367 }; 1367 };
1368 vin2csi40: endpoint@2 { 1368 vin2csi40: endpoint@2 {
1369 reg = <2>; 1369 reg = <2>;
1370 remote-endpoint= <&csi40vin2>; 1370 remote-endpoint = <&csi40vin2>;
1371 }; 1371 };
1372 }; 1372 };
1373 }; 1373 };
@@ -1395,11 +1395,11 @@
1395 1395
1396 vin3csi20: endpoint@0 { 1396 vin3csi20: endpoint@0 {
1397 reg = <0>; 1397 reg = <0>;
1398 remote-endpoint= <&csi20vin3>; 1398 remote-endpoint = <&csi20vin3>;
1399 }; 1399 };
1400 vin3csi40: endpoint@2 { 1400 vin3csi40: endpoint@2 {
1401 reg = <2>; 1401 reg = <2>;
1402 remote-endpoint= <&csi40vin3>; 1402 remote-endpoint = <&csi40vin3>;
1403 }; 1403 };
1404 }; 1404 };
1405 }; 1405 };
@@ -1427,11 +1427,11 @@
1427 1427
1428 vin4csi20: endpoint@0 { 1428 vin4csi20: endpoint@0 {
1429 reg = <0>; 1429 reg = <0>;
1430 remote-endpoint= <&csi20vin4>; 1430 remote-endpoint = <&csi20vin4>;
1431 }; 1431 };
1432 vin4csi40: endpoint@2 { 1432 vin4csi40: endpoint@2 {
1433 reg = <2>; 1433 reg = <2>;
1434 remote-endpoint= <&csi40vin4>; 1434 remote-endpoint = <&csi40vin4>;
1435 }; 1435 };
1436 }; 1436 };
1437 }; 1437 };
@@ -1459,11 +1459,11 @@
1459 1459
1460 vin5csi20: endpoint@0 { 1460 vin5csi20: endpoint@0 {
1461 reg = <0>; 1461 reg = <0>;
1462 remote-endpoint= <&csi20vin5>; 1462 remote-endpoint = <&csi20vin5>;
1463 }; 1463 };
1464 vin5csi40: endpoint@2 { 1464 vin5csi40: endpoint@2 {
1465 reg = <2>; 1465 reg = <2>;
1466 remote-endpoint= <&csi40vin5>; 1466 remote-endpoint = <&csi40vin5>;
1467 }; 1467 };
1468 }; 1468 };
1469 }; 1469 };
@@ -1491,11 +1491,11 @@
1491 1491
1492 vin6csi20: endpoint@0 { 1492 vin6csi20: endpoint@0 {
1493 reg = <0>; 1493 reg = <0>;
1494 remote-endpoint= <&csi20vin6>; 1494 remote-endpoint = <&csi20vin6>;
1495 }; 1495 };
1496 vin6csi40: endpoint@2 { 1496 vin6csi40: endpoint@2 {
1497 reg = <2>; 1497 reg = <2>;
1498 remote-endpoint= <&csi40vin6>; 1498 remote-endpoint = <&csi40vin6>;
1499 }; 1499 };
1500 }; 1500 };
1501 }; 1501 };
@@ -1523,11 +1523,11 @@
1523 1523
1524 vin7csi20: endpoint@0 { 1524 vin7csi20: endpoint@0 {
1525 reg = <0>; 1525 reg = <0>;
1526 remote-endpoint= <&csi20vin7>; 1526 remote-endpoint = <&csi20vin7>;
1527 }; 1527 };
1528 vin7csi40: endpoint@2 { 1528 vin7csi40: endpoint@2 {
1529 reg = <2>; 1529 reg = <2>;
1530 remote-endpoint= <&csi40vin7>; 1530 remote-endpoint = <&csi40vin7>;
1531 }; 1531 };
1532 }; 1532 };
1533 }; 1533 };
@@ -1997,7 +1997,7 @@
1997 clocks = <&cpg CPG_MOD 703>; 1997 clocks = <&cpg CPG_MOD 703>;
1998 phys = <&usb2_phy0>; 1998 phys = <&usb2_phy0>;
1999 phy-names = "usb"; 1999 phy-names = "usb";
2000 companion= <&ohci0>; 2000 companion = <&ohci0>;
2001 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 2001 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2002 resets = <&cpg 703>; 2002 resets = <&cpg 703>;
2003 status = "disabled"; 2003 status = "disabled";
@@ -2010,7 +2010,7 @@
2010 clocks = <&cpg CPG_MOD 702>; 2010 clocks = <&cpg CPG_MOD 702>;
2011 phys = <&usb2_phy1>; 2011 phys = <&usb2_phy1>;
2012 phy-names = "usb"; 2012 phy-names = "usb";
2013 companion= <&ohci1>; 2013 companion = <&ohci1>;
2014 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 2014 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2015 resets = <&cpg 702>; 2015 resets = <&cpg 702>;
2016 status = "disabled"; 2016 status = "disabled";
@@ -2437,17 +2437,14 @@
2437 2437
2438 du: display@feb00000 { 2438 du: display@feb00000 {
2439 compatible = "renesas,du-r8a7796"; 2439 compatible = "renesas,du-r8a7796";
2440 reg = <0 0xfeb00000 0 0x70000>, 2440 reg = <0 0xfeb00000 0 0x70000>;
2441 <0 0xfeb90000 0 0x14>;
2442 reg-names = "du", "lvds.0";
2443 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 2441 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
2444 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2442 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
2445 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; 2443 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
2446 clocks = <&cpg CPG_MOD 724>, 2444 clocks = <&cpg CPG_MOD 724>,
2447 <&cpg CPG_MOD 723>, 2445 <&cpg CPG_MOD 723>,
2448 <&cpg CPG_MOD 722>, 2446 <&cpg CPG_MOD 722>;
2449 <&cpg CPG_MOD 727>; 2447 clock-names = "du.0", "du.1", "du.2";
2450 clock-names = "du.0", "du.1", "du.2", "lvds.0";
2451 status = "disabled"; 2448 status = "disabled";
2452 2449
2453 vsps = <&vspd0 &vspd1 &vspd2>; 2450 vsps = <&vspd0 &vspd1 &vspd2>;
@@ -2470,6 +2467,33 @@
2470 port@2 { 2467 port@2 {
2471 reg = <2>; 2468 reg = <2>;
2472 du_out_lvds0: endpoint { 2469 du_out_lvds0: endpoint {
2470 remote-endpoint = <&lvds0_in>;
2471 };
2472 };
2473 };
2474 };
2475
2476 lvds0: lvds@feb90000 {
2477 compatible = "renesas,r8a7796-lvds";
2478 reg = <0 0xfeb90000 0 0x14>;
2479 clocks = <&cpg CPG_MOD 727>;
2480 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2481 resets = <&cpg 727>;
2482 status = "disabled";
2483
2484 ports {
2485 #address-cells = <1>;
2486 #size-cells = <0>;
2487
2488 port@0 {
2489 reg = <0>;
2490 lvds0_in: endpoint {
2491 remote-endpoint = <&du_out_lvds0>;
2492 };
2493 };
2494 port@1 {
2495 reg = <1>;
2496 lvds0_out: endpoint {
2473 }; 2497 };
2474 }; 2498 };
2475 }; 2499 };
diff --git a/arch/arm64/boot/dts/renesas/r8a77965-m3nulcb-kf.dts b/arch/arm64/boot/dts/renesas/r8a77965-m3nulcb-kf.dts
new file mode 100644
index 000000000000..dadad97051b9
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a77965-m3nulcb-kf.dts
@@ -0,0 +1,16 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the M3NULCB Kingfisher board
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 * Copyright (C) 2018 Cogent Embedded, Inc.
7 */
8
9#include "r8a77965-m3nulcb.dts"
10#include "ulcb-kf.dtsi"
11
12/ {
13 model = "Renesas M3NULCB Kingfisher board based on r8a77965";
14 compatible = "shimafuji,kingfisher", "renesas,m3nulcb",
15 "renesas,r8a77965";
16};
diff --git a/arch/arm64/boot/dts/renesas/r8a77965-m3nulcb.dts b/arch/arm64/boot/dts/renesas/r8a77965-m3nulcb.dts
new file mode 100644
index 000000000000..964078b6cc49
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a77965-m3nulcb.dts
@@ -0,0 +1,33 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the M3NULCB (R-Car Starter Kit Pro) board
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 * Copyright (C) 2018 Cogent Embedded, Inc.
7 */
8
9/dts-v1/;
10#include "r8a77965.dtsi"
11#include "ulcb.dtsi"
12
13/ {
14 model = "Renesas M3NULCB board based on r8a77965";
15 compatible = "renesas,m3nulcb", "renesas,r8a77965";
16
17 memory@48000000 {
18 device_type = "memory";
19 /* first 128MB is reserved for secure area. */
20 reg = <0x0 0x48000000 0x0 0x78000000>;
21 };
22};
23
24&du {
25 clocks = <&cpg CPG_MOD 724>,
26 <&cpg CPG_MOD 723>,
27 <&cpg CPG_MOD 721>,
28 <&versaclock5 1>,
29 <&versaclock5 3>,
30 <&versaclock5 2>;
31 clock-names = "du.0", "du.1", "du.3",
32 "dclkin.0", "dclkin.1", "dclkin.3";
33};
diff --git a/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts b/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts
index 9de4e3db1621..f03a5e9e0c42 100644
--- a/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts
@@ -47,3 +47,17 @@
47&hdmi0_con { 47&hdmi0_con {
48 remote-endpoint = <&rcar_dw_hdmi0_out>; 48 remote-endpoint = <&rcar_dw_hdmi0_out>;
49}; 49};
50
51&pca9654 {
52 pcie_sata_switch {
53 gpio-hog;
54 gpios = <7 GPIO_ACTIVE_HIGH>;
55 output-low; /* enable SATA by default */
56 line-name = "PCIE/SATA switch";
57 };
58};
59
60/* SW12-7 must be set 'Off' (MD12 set to 1) which is not the default! */
61&sata {
62 status = "okay";
63};
diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
index 0cd44461a0bd..3437d5e34f6a 100644
--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
@@ -1,6 +1,6 @@
1// SPDX-License-Identifier: GPL-2.0 1// SPDX-License-Identifier: GPL-2.0
2/* 2/*
3 * Device Tree Source for the r8a77965 SoC 3 * Device Tree Source for the R-Car M3-N (R8A77965) SoC
4 * 4 *
5 * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org> 5 * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
6 * 6 *
@@ -60,6 +60,46 @@
60 clock-frequency = <0>; 60 clock-frequency = <0>;
61 }; 61 };
62 62
63 cluster0_opp: opp_table0 {
64 compatible = "operating-points-v2";
65 opp-shared;
66
67 opp-500000000 {
68 opp-hz = /bits/ 64 <500000000>;
69 opp-microvolt = <830000>;
70 clock-latency-ns = <300000>;
71 };
72 opp-1000000000 {
73 opp-hz = /bits/ 64 <1000000000>;
74 opp-microvolt = <830000>;
75 clock-latency-ns = <300000>;
76 };
77 opp-1500000000 {
78 opp-hz = /bits/ 64 <1500000000>;
79 opp-microvolt = <830000>;
80 clock-latency-ns = <300000>;
81 opp-suspend;
82 };
83 opp-1600000000 {
84 opp-hz = /bits/ 64 <1600000000>;
85 opp-microvolt = <900000>;
86 clock-latency-ns = <300000>;
87 turbo-mode;
88 };
89 opp-1700000000 {
90 opp-hz = /bits/ 64 <1700000000>;
91 opp-microvolt = <900000>;
92 clock-latency-ns = <300000>;
93 turbo-mode;
94 };
95 opp-1800000000 {
96 opp-hz = /bits/ 64 <1800000000>;
97 opp-microvolt = <960000>;
98 clock-latency-ns = <300000>;
99 turbo-mode;
100 };
101 };
102
63 cpus { 103 cpus {
64 #address-cells = <1>; 104 #address-cells = <1>;
65 #size-cells = <0>; 105 #size-cells = <0>;
@@ -71,6 +111,8 @@
71 power-domains = <&sysc R8A77965_PD_CA57_CPU0>; 111 power-domains = <&sysc R8A77965_PD_CA57_CPU0>;
72 next-level-cache = <&L2_CA57>; 112 next-level-cache = <&L2_CA57>;
73 enable-method = "psci"; 113 enable-method = "psci";
114 clocks = <&cpg CPG_CORE R8A77965_CLK_Z>;
115 operating-points-v2 = <&cluster0_opp>;
74 }; 116 };
75 117
76 a57_1: cpu@1 { 118 a57_1: cpu@1 {
@@ -80,6 +122,8 @@
80 power-domains = <&sysc R8A77965_PD_CA57_CPU1>; 122 power-domains = <&sysc R8A77965_PD_CA57_CPU1>;
81 next-level-cache = <&L2_CA57>; 123 next-level-cache = <&L2_CA57>;
82 enable-method = "psci"; 124 enable-method = "psci";
125 clocks = <&cpg CPG_CORE R8A77965_CLK_Z>;
126 operating-points-v2 = <&cluster0_opp>;
83 }; 127 };
84 128
85 L2_CA57: cache-controller-0 { 129 L2_CA57: cache-controller-0 {
@@ -545,7 +589,7 @@
545 }; 589 };
546 590
547 hsusb: usb@e6590000 { 591 hsusb: usb@e6590000 {
548 compatible = "renesas,usbhs-r8a7796", 592 compatible = "renesas,usbhs-r8a77965",
549 "renesas,rcar-gen3-usbhs"; 593 "renesas,rcar-gen3-usbhs";
550 reg = <0 0xe6590000 0 0x100>; 594 reg = <0 0xe6590000 0 0x100>;
551 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 595 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
@@ -634,6 +678,14 @@
634 resets = <&cpg 219>; 678 resets = <&cpg 219>;
635 #dma-cells = <1>; 679 #dma-cells = <1>;
636 dma-channels = <16>; 680 dma-channels = <16>;
681 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
682 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
683 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
684 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
685 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
686 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
687 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
688 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
637 }; 689 };
638 690
639 dmac1: dma-controller@e7300000 { 691 dmac1: dma-controller@e7300000 {
@@ -668,6 +720,14 @@
668 resets = <&cpg 218>; 720 resets = <&cpg 218>;
669 #dma-cells = <1>; 721 #dma-cells = <1>;
670 dma-channels = <16>; 722 dma-channels = <16>;
723 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
724 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
725 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
726 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
727 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
728 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
729 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
730 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
671 }; 731 };
672 732
673 dmac2: dma-controller@e7310000 { 733 dmac2: dma-controller@e7310000 {
@@ -702,6 +762,14 @@
702 resets = <&cpg 217>; 762 resets = <&cpg 217>;
703 #dma-cells = <1>; 763 #dma-cells = <1>;
704 dma-channels = <16>; 764 dma-channels = <16>;
765 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
766 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
767 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
768 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
769 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
770 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
771 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
772 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
705 }; 773 };
706 774
707 ipmmu_ds0: mmu@e6740000 { 775 ipmmu_ds0: mmu@e6740000 {
@@ -838,6 +906,16 @@
838 status = "disabled"; 906 status = "disabled";
839 }; 907 };
840 908
909 can0: can@e6c30000 {
910 reg = <0 0xe6c30000 0 0x1000>;
911 /* placeholder */
912 };
913
914 can1: can@e6c38000 {
915 reg = <0 0xe6c38000 0 0x1000>;
916 /* placeholder */
917 };
918
841 pwm0: pwm@e6e30000 { 919 pwm0: pwm@e6e30000 {
842 compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar"; 920 compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar";
843 reg = <0 0xe6e30000 0 8>; 921 reg = <0 0xe6e30000 0 8>;
@@ -1089,11 +1167,11 @@
1089 1167
1090 vin0csi20: endpoint@0 { 1168 vin0csi20: endpoint@0 {
1091 reg = <0>; 1169 reg = <0>;
1092 remote-endpoint= <&csi20vin0>; 1170 remote-endpoint = <&csi20vin0>;
1093 }; 1171 };
1094 vin0csi40: endpoint@2 { 1172 vin0csi40: endpoint@2 {
1095 reg = <2>; 1173 reg = <2>;
1096 remote-endpoint= <&csi40vin0>; 1174 remote-endpoint = <&csi40vin0>;
1097 }; 1175 };
1098 }; 1176 };
1099 }; 1177 };
@@ -1121,11 +1199,11 @@
1121 1199
1122 vin1csi20: endpoint@0 { 1200 vin1csi20: endpoint@0 {
1123 reg = <0>; 1201 reg = <0>;
1124 remote-endpoint= <&csi20vin1>; 1202 remote-endpoint = <&csi20vin1>;
1125 }; 1203 };
1126 vin1csi40: endpoint@2 { 1204 vin1csi40: endpoint@2 {
1127 reg = <2>; 1205 reg = <2>;
1128 remote-endpoint= <&csi40vin1>; 1206 remote-endpoint = <&csi40vin1>;
1129 }; 1207 };
1130 }; 1208 };
1131 }; 1209 };
@@ -1153,11 +1231,11 @@
1153 1231
1154 vin2csi20: endpoint@0 { 1232 vin2csi20: endpoint@0 {
1155 reg = <0>; 1233 reg = <0>;
1156 remote-endpoint= <&csi20vin2>; 1234 remote-endpoint = <&csi20vin2>;
1157 }; 1235 };
1158 vin2csi40: endpoint@2 { 1236 vin2csi40: endpoint@2 {
1159 reg = <2>; 1237 reg = <2>;
1160 remote-endpoint= <&csi40vin2>; 1238 remote-endpoint = <&csi40vin2>;
1161 }; 1239 };
1162 }; 1240 };
1163 }; 1241 };
@@ -1185,11 +1263,11 @@
1185 1263
1186 vin3csi20: endpoint@0 { 1264 vin3csi20: endpoint@0 {
1187 reg = <0>; 1265 reg = <0>;
1188 remote-endpoint= <&csi20vin3>; 1266 remote-endpoint = <&csi20vin3>;
1189 }; 1267 };
1190 vin3csi40: endpoint@2 { 1268 vin3csi40: endpoint@2 {
1191 reg = <2>; 1269 reg = <2>;
1192 remote-endpoint= <&csi40vin3>; 1270 remote-endpoint = <&csi40vin3>;
1193 }; 1271 };
1194 }; 1272 };
1195 }; 1273 };
@@ -1217,11 +1295,11 @@
1217 1295
1218 vin4csi20: endpoint@0 { 1296 vin4csi20: endpoint@0 {
1219 reg = <0>; 1297 reg = <0>;
1220 remote-endpoint= <&csi20vin4>; 1298 remote-endpoint = <&csi20vin4>;
1221 }; 1299 };
1222 vin4csi40: endpoint@2 { 1300 vin4csi40: endpoint@2 {
1223 reg = <2>; 1301 reg = <2>;
1224 remote-endpoint= <&csi40vin4>; 1302 remote-endpoint = <&csi40vin4>;
1225 }; 1303 };
1226 }; 1304 };
1227 }; 1305 };
@@ -1249,11 +1327,11 @@
1249 1327
1250 vin5csi20: endpoint@0 { 1328 vin5csi20: endpoint@0 {
1251 reg = <0>; 1329 reg = <0>;
1252 remote-endpoint= <&csi20vin5>; 1330 remote-endpoint = <&csi20vin5>;
1253 }; 1331 };
1254 vin5csi40: endpoint@2 { 1332 vin5csi40: endpoint@2 {
1255 reg = <2>; 1333 reg = <2>;
1256 remote-endpoint= <&csi40vin5>; 1334 remote-endpoint = <&csi40vin5>;
1257 }; 1335 };
1258 }; 1336 };
1259 }; 1337 };
@@ -1281,11 +1359,11 @@
1281 1359
1282 vin6csi20: endpoint@0 { 1360 vin6csi20: endpoint@0 {
1283 reg = <0>; 1361 reg = <0>;
1284 remote-endpoint= <&csi20vin6>; 1362 remote-endpoint = <&csi20vin6>;
1285 }; 1363 };
1286 vin6csi40: endpoint@2 { 1364 vin6csi40: endpoint@2 {
1287 reg = <2>; 1365 reg = <2>;
1288 remote-endpoint= <&csi40vin6>; 1366 remote-endpoint = <&csi40vin6>;
1289 }; 1367 };
1290 }; 1368 };
1291 }; 1369 };
@@ -1313,11 +1391,11 @@
1313 1391
1314 vin7csi20: endpoint@0 { 1392 vin7csi20: endpoint@0 {
1315 reg = <0>; 1393 reg = <0>;
1316 remote-endpoint= <&csi20vin7>; 1394 remote-endpoint = <&csi20vin7>;
1317 }; 1395 };
1318 vin7csi40: endpoint@2 { 1396 vin7csi40: endpoint@2 {
1319 reg = <2>; 1397 reg = <2>;
1320 remote-endpoint= <&csi40vin7>; 1398 remote-endpoint = <&csi40vin7>;
1321 }; 1399 };
1322 }; 1400 };
1323 }; 1401 };
@@ -1452,9 +1530,9 @@
1452 compatible = "renesas,usb2-phy-r8a77965", 1530 compatible = "renesas,usb2-phy-r8a77965",
1453 "renesas,rcar-gen3-usb2-phy"; 1531 "renesas,rcar-gen3-usb2-phy";
1454 reg = <0 0xee0a0200 0 0x700>; 1532 reg = <0 0xee0a0200 0 0x700>;
1455 clocks = <&cpg CPG_MOD 703>; 1533 clocks = <&cpg CPG_MOD 702>;
1456 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; 1534 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
1457 resets = <&cpg 703>; 1535 resets = <&cpg 702>;
1458 #phy-cells = <0>; 1536 #phy-cells = <0>;
1459 status = "disabled"; 1537 status = "disabled";
1460 }; 1538 };
@@ -1507,6 +1585,17 @@
1507 status = "disabled"; 1585 status = "disabled";
1508 }; 1586 };
1509 1587
1588 sata: sata@ee300000 {
1589 compatible = "renesas,sata-r8a77965",
1590 "renesas,rcar-gen3-sata";
1591 reg = <0 0xee300000 0 0x200000>;
1592 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
1593 clocks = <&cpg CPG_MOD 815>;
1594 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
1595 resets = <&cpg 815>;
1596 status = "disabled";
1597 };
1598
1510 gic: interrupt-controller@f1010000 { 1599 gic: interrupt-controller@f1010000 {
1511 compatible = "arm,gic-400"; 1600 compatible = "arm,gic-400";
1512 #interrupt-cells = <3>; 1601 #interrupt-cells = <3>;
@@ -1578,6 +1667,16 @@
1578 status = "disabled"; 1667 status = "disabled";
1579 }; 1668 };
1580 1669
1670 fdp1@fe940000 {
1671 compatible = "renesas,fdp1";
1672 reg = <0 0xfe940000 0 0x2400>;
1673 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
1674 clocks = <&cpg CPG_MOD 119>;
1675 power-domains = <&sysc R8A77965_PD_A3VP>;
1676 resets = <&cpg 119>;
1677 renesas,fcp = <&fcpf0>;
1678 };
1679
1581 fcpf0: fcp@fe950000 { 1680 fcpf0: fcp@fe950000 {
1582 compatible = "renesas,fcpf"; 1681 compatible = "renesas,fcpf";
1583 reg = <0 0xfe950000 0 0x200>; 1682 reg = <0 0xfe950000 0 0x200>;
@@ -1843,14 +1942,6 @@
1843 }; 1942 };
1844 }; 1943 };
1845 1944
1846 timer {
1847 compatible = "arm,armv8-timer";
1848 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1849 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1850 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1851 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
1852 };
1853
1854 thermal-zones { 1945 thermal-zones {
1855 sensor_thermal1: sensor-thermal1 { 1946 sensor_thermal1: sensor-thermal1 {
1856 polling-delay-passive = <250>; 1947 polling-delay-passive = <250>;
@@ -1895,6 +1986,14 @@
1895 }; 1986 };
1896 }; 1987 };
1897 1988
1989 timer {
1990 compatible = "arm,armv8-timer";
1991 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1992 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1993 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1994 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
1995 };
1996
1898 /* External USB clocks - can be overridden by the board */ 1997 /* External USB clocks - can be overridden by the board */
1899 usb3s0_clk: usb3s0 { 1998 usb3s0_clk: usb3s0 {
1900 compatible = "fixed-clock"; 1999 compatible = "fixed-clock";
diff --git a/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts b/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts
index 8eac8ca6550b..0dbcb4cccc18 100644
--- a/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts
@@ -51,6 +51,15 @@
51 regulator-always-on; 51 regulator-always-on;
52 }; 52 };
53 53
54 vcc_vddq_vin0: regulator-2 {
55 compatible = "regulator-fixed";
56 regulator-name = "VCC_VDDQ_VIN0";
57 regulator-min-microvolt = <3300000>;
58 regulator-max-microvolt = <3300000>;
59 regulator-boot-on;
60 regulator-always-on;
61 };
62
54 lvds-decoder { 63 lvds-decoder {
55 compatible = "thine,thc63lvd1024"; 64 compatible = "thine,thc63lvd1024";
56 vcc-supply = <&vcc_d3_3v>; 65 vcc-supply = <&vcc_d3_3v>;
@@ -128,6 +137,12 @@
128 function = "i2c0"; 137 function = "i2c0";
129 }; 138 };
130 139
140 mmc_pins: mmc_3_3v {
141 groups = "mmc_data8", "mmc_ctrl";
142 function = "mmc";
143 power-source = <3300>;
144 };
145
131 scif0_pins: scif0 { 146 scif0_pins: scif0 {
132 groups = "scif0_data"; 147 groups = "scif0_data";
133 function = "scif0"; 148 function = "scif0";
@@ -192,6 +207,17 @@
192 }; 207 };
193}; 208};
194 209
210&mmc0 {
211 pinctrl-0 = <&mmc_pins>;
212 pinctrl-names = "default";
213
214 vmmc-supply = <&vcc_d3_3v>;
215 vqmmc-supply = <&vcc_vddq_vin0>;
216 bus-width = <8>;
217 non-removable;
218 status = "okay";
219};
220
195&scif0 { 221&scif0 {
196 pinctrl-0 = <&scif0_pins>; 222 pinctrl-0 = <&scif0_pins>;
197 pinctrl-names = "default"; 223 pinctrl-names = "default";
diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
index 954168858fed..f4b02707390f 100644
--- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
@@ -1,6 +1,6 @@
1// SPDX-License-Identifier: GPL-2.0 1// SPDX-License-Identifier: GPL-2.0
2/* 2/*
3 * Device Tree Source for the r8a77970 SoC 3 * Device Tree Source for the R-Car V3M (R8A77970) SoC
4 * 4 *
5 * Copyright (C) 2016-2017 Renesas Electronics Corp. 5 * Copyright (C) 2016-2017 Renesas Electronics Corp.
6 * Copyright (C) 2017 Cogent Embedded, Inc. 6 * Copyright (C) 2017 Cogent Embedded, Inc.
@@ -24,6 +24,13 @@
24 i2c4 = &i2c4; 24 i2c4 = &i2c4;
25 }; 25 };
26 26
27 /* External CAN clock - to be overridden by boards that provide it */
28 can_clk: can {
29 compatible = "fixed-clock";
30 #clock-cells = <0>;
31 clock-frequency = <0>;
32 };
33
27 cpus { 34 cpus {
28 #address-cells = <1>; 35 #address-cells = <1>;
29 #size-cells = <0>; 36 #size-cells = <0>;
@@ -82,13 +89,6 @@
82 method = "smc"; 89 method = "smc";
83 }; 90 };
84 91
85 /* External CAN clock - to be overridden by boards that provide it */
86 can_clk: can {
87 compatible = "fixed-clock";
88 #clock-cells = <0>;
89 clock-frequency = <0>;
90 };
91
92 /* External SCIF clock - to be overridden by boards that provide it */ 92 /* External SCIF clock - to be overridden by boards that provide it */
93 scif_clk: scif { 93 scif_clk: scif {
94 compatible = "fixed-clock"; 94 compatible = "fixed-clock";
@@ -567,7 +567,7 @@
567 567
568 vin0csi40: endpoint@2 { 568 vin0csi40: endpoint@2 {
569 reg = <2>; 569 reg = <2>;
570 remote-endpoint= <&csi40vin0>; 570 remote-endpoint = <&csi40vin0>;
571 }; 571 };
572 }; 572 };
573 }; 573 };
@@ -595,7 +595,7 @@
595 595
596 vin1csi40: endpoint@2 { 596 vin1csi40: endpoint@2 {
597 reg = <2>; 597 reg = <2>;
598 remote-endpoint= <&csi40vin1>; 598 remote-endpoint = <&csi40vin1>;
599 }; 599 };
600 }; 600 };
601 }; 601 };
@@ -623,7 +623,7 @@
623 623
624 vin2csi40: endpoint@2 { 624 vin2csi40: endpoint@2 {
625 reg = <2>; 625 reg = <2>;
626 remote-endpoint= <&csi40vin2>; 626 remote-endpoint = <&csi40vin2>;
627 }; 627 };
628 }; 628 };
629 }; 629 };
@@ -651,7 +651,7 @@
651 651
652 vin3csi40: endpoint@2 { 652 vin3csi40: endpoint@2 {
653 reg = <2>; 653 reg = <2>;
654 remote-endpoint= <&csi40vin3>; 654 remote-endpoint = <&csi40vin3>;
655 }; 655 };
656 }; 656 };
657 }; 657 };
@@ -754,6 +754,18 @@
754 #iommu-cells = <1>; 754 #iommu-cells = <1>;
755 }; 755 };
756 756
757 mmc0: mmc@ee140000 {
758 compatible = "renesas,sdhi-r8a77970",
759 "renesas,rcar-gen3-sdhi";
760 reg = <0 0xee140000 0 0x2000>;
761 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
762 clocks = <&cpg CPG_MOD 314>;
763 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
764 resets = <&cpg 314>;
765 max-frequency = <200000000>;
766 status = "disabled";
767 };
768
757 gic: interrupt-controller@f1010000 { 769 gic: interrupt-controller@f1010000 {
758 compatible = "arm,gic-400"; 770 compatible = "arm,gic-400";
759 #interrupt-cells = <3>; 771 #interrupt-cells = <3>;
diff --git a/arch/arm64/boot/dts/renesas/r8a77980-condor.dts b/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
index 9f25c407dfd7..fe2e2c051cc9 100644
--- a/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
@@ -45,6 +45,56 @@
45 regulator-boot-on; 45 regulator-boot-on;
46 regulator-always-on; 46 regulator-always-on;
47 }; 47 };
48
49 d1_8v: regulator-2 {
50 compatible = "regulator-fixed";
51 regulator-name = "D1.8V";
52 regulator-min-microvolt = <1800000>;
53 regulator-max-microvolt = <1800000>;
54 regulator-boot-on;
55 regulator-always-on;
56 };
57
58 hdmi-out {
59 compatible = "hdmi-connector";
60 type = "a";
61
62 port {
63 hdmi_con: endpoint {
64 remote-endpoint = <&adv7511_out>;
65 };
66 };
67 };
68
69 lvds-decoder {
70 compatible = "thine,thc63lvd1024";
71 vcc-supply = <&d3_3v>;
72
73 ports {
74 #address-cells = <1>;
75 #size-cells = <0>;
76
77 port@0 {
78 reg = <0>;
79 thc63lvd1024_in: endpoint {
80 remote-endpoint = <&lvds0_out>;
81 };
82 };
83
84 port@2 {
85 reg = <2>;
86 thc63lvd1024_out: endpoint {
87 remote-endpoint = <&adv7511_in>;
88 };
89 };
90 };
91 };
92
93 x1_clk: x1-clock {
94 compatible = "fixed-clock";
95 #clock-cells = <0>;
96 clock-frequency = <148500000>;
97 };
48}; 98};
49 99
50&avb { 100&avb {
@@ -74,6 +124,13 @@
74 }; 124 };
75}; 125};
76 126
127&du {
128 clocks = <&cpg CPG_MOD 724>,
129 <&x1_clk>;
130 clock-names = "du.0", "dclkin.0";
131 status = "okay";
132};
133
77&extal_clk { 134&extal_clk {
78 clock-frequency = <16666666>; 135 clock-frequency = <16666666>;
79}; 136};
@@ -102,6 +159,55 @@
102 gpio-controller; 159 gpio-controller;
103 #gpio-cells = <2>; 160 #gpio-cells = <2>;
104 }; 161 };
162
163 hdmi@39 {
164 compatible = "adi,adv7511w";
165 reg = <0x39>;
166 interrupt-parent = <&gpio1>;
167 interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
168 avdd-supply = <&d1_8v>;
169 dvdd-supply = <&d1_8v>;
170 pvdd-supply = <&d1_8v>;
171 bgvdd-supply = <&d1_8v>;
172 dvdd-3v-supply = <&d3_3v>;
173
174 adi,input-depth = <8>;
175 adi,input-colorspace = "rgb";
176 adi,input-clock = "1x";
177 adi,input-style = <1>;
178 adi,input-justification = "evenly";
179
180 ports {
181 #address-cells = <1>;
182 #size-cells = <0>;
183
184 port@0 {
185 reg = <0>;
186 adv7511_in: endpoint {
187 remote-endpoint = <&thc63lvd1024_out>;
188 };
189 };
190
191 port@1 {
192 reg = <1>;
193 adv7511_out: endpoint {
194 remote-endpoint = <&hdmi_con>;
195 };
196 };
197 };
198 };
199};
200
201&lvds0 {
202 status = "okay";
203
204 ports {
205 port@1 {
206 lvds0_out: endpoint {
207 remote-endpoint = <&thc63lvd1024_in>;
208 };
209 };
210 };
105}; 211};
106 212
107&mmc0 { 213&mmc0 {
@@ -117,6 +223,18 @@
117 status = "okay"; 223 status = "okay";
118}; 224};
119 225
226&pciec {
227 status = "okay";
228};
229
230&pcie_bus_clk {
231 clock-frequency = <100000000>;
232};
233
234&pcie_phy {
235 status = "okay";
236};
237
120&pfc { 238&pfc {
121 avb_pins: avb { 239 avb_pins: avb {
122 groups = "avb_mdio", "avb_rgmii"; 240 groups = "avb_mdio", "avb_rgmii";
@@ -156,6 +274,11 @@
156 }; 274 };
157}; 275};
158 276
277&rwdt {
278 timeout-sec = <60>;
279 status = "okay";
280};
281
159&scif0 { 282&scif0 {
160 pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>; 283 pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>;
161 pinctrl-names = "default"; 284 pinctrl-names = "default";
diff --git a/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts b/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts
index 9dac42f8f804..dd14a41b32cd 100644
--- a/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts
@@ -27,6 +27,72 @@
27 /* first 128MB is reserved for secure area. */ 27 /* first 128MB is reserved for secure area. */
28 reg = <0 0x48000000 0 0x78000000>; 28 reg = <0 0x48000000 0 0x78000000>;
29 }; 29 };
30
31 hdmi-out {
32 compatible = "hdmi-connector";
33 type = "a";
34
35 port {
36 hdmi_con: endpoint {
37 remote-endpoint = <&adv7511_out>;
38 };
39 };
40 };
41
42 lvds-decoder {
43 compatible = "thine,thc63lvd1024";
44 vcc-supply = <&vcc3v3_d5>;
45
46 ports {
47 #address-cells = <1>;
48 #size-cells = <0>;
49
50 port@0 {
51 reg = <0>;
52 thc63lvd1024_in: endpoint {
53 remote-endpoint = <&lvds0_out>;
54 };
55 };
56
57 port@2 {
58 reg = <2>;
59 thc63lvd1024_out: endpoint {
60 remote-endpoint = <&adv7511_in>;
61 };
62 };
63 };
64 };
65
66 osc1_clk: osc1-clock {
67 compatible = "fixed-clock";
68 #clock-cells = <0>;
69 clock-frequency = <148500000>;
70 };
71
72 vcc1v8_d4: regulator-0 {
73 compatible = "regulator-fixed";
74 regulator-name = "VCC1V8_D4";
75 regulator-min-microvolt = <1800000>;
76 regulator-max-microvolt = <1800000>;
77 regulator-boot-on;
78 regulator-always-on;
79 };
80
81 vcc3v3_d5: regulator-1 {
82 compatible = "regulator-fixed";
83 regulator-name = "VCC3V3_D5";
84 regulator-min-microvolt = <3300000>;
85 regulator-max-microvolt = <3300000>;
86 regulator-boot-on;
87 regulator-always-on;
88 };
89};
90
91&du {
92 clocks = <&cpg CPG_MOD 724>,
93 <&osc1_clk>;
94 clock-names = "du.0", "dclkin.0";
95 status = "okay";
30}; 96};
31 97
32&extal_clk { 98&extal_clk {
@@ -53,6 +119,64 @@
53 }; 119 };
54}; 120};
55 121
122&i2c0 {
123 pinctrl-0 = <&i2c0_pins>;
124 pinctrl-names = "default";
125
126 status = "okay";
127 clock-frequency = <400000>;
128
129 hdmi@39 {
130 compatible = "adi,adv7511w";
131 #sound-dai-cells = <0>;
132 reg = <0x39>;
133 interrupt-parent = <&gpio1>;
134 interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
135 avdd-supply = <&vcc1v8_d4>;
136 dvdd-supply = <&vcc1v8_d4>;
137 pvdd-supply = <&vcc1v8_d4>;
138 bgvdd-supply = <&vcc1v8_d4>;
139 dvdd-3v-supply = <&vcc3v3_d5>;
140
141 adi,input-depth = <8>;
142 adi,input-colorspace = "rgb";
143 adi,input-clock = "1x";
144 adi,input-style = <1>;
145 adi,input-justification = "evenly";
146
147 ports {
148 #address-cells = <1>;
149 #size-cells = <0>;
150
151 port@0 {
152 reg = <0>;
153 adv7511_in: endpoint {
154 remote-endpoint = <&thc63lvd1024_out>;
155 };
156 };
157
158 port@1 {
159 reg = <1>;
160 adv7511_out: endpoint {
161 remote-endpoint = <&hdmi_con>;
162 };
163 };
164 };
165 };
166};
167
168&lvds0 {
169 status = "okay";
170
171 ports {
172 port@1 {
173 lvds0_out: endpoint {
174 remote-endpoint = <&thc63lvd1024_in>;
175 };
176 };
177 };
178};
179
56&pfc { 180&pfc {
57 gether_pins: gether { 181 gether_pins: gether {
58 groups = "gether_mdio_a", "gether_rgmii", 182 groups = "gether_mdio_a", "gether_rgmii",
@@ -60,6 +184,11 @@
60 function = "gether"; 184 function = "gether";
61 }; 185 };
62 186
187 i2c0_pins: i2c0 {
188 groups = "i2c0";
189 function = "i2c0";
190 };
191
63 scif0_pins: scif0 { 192 scif0_pins: scif0 {
64 groups = "scif0_data"; 193 groups = "scif0_data";
65 function = "scif0"; 194 function = "scif0";
@@ -71,6 +200,11 @@
71 }; 200 };
72}; 201};
73 202
203&rwdt {
204 timeout-sec = <60>;
205 status = "okay";
206};
207
74&scif0 { 208&scif0 {
75 pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>; 209 pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>;
76 pinctrl-names = "default"; 210 pinctrl-names = "default";
diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
index b8c9a56562f2..fc2a1d62d773 100644
--- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
@@ -1,6 +1,6 @@
1// SPDX-License-Identifier: GPL-2.0 1// SPDX-License-Identifier: GPL-2.0
2/* 2/*
3 * Device Tree Source for the r8a77980 SoC 3 * Device Tree Source for the R-Car V3H (R8A77980) SoC
4 * 4 *
5 * Copyright (C) 2018 Renesas Electronics Corp. 5 * Copyright (C) 2018 Renesas Electronics Corp.
6 * Copyright (C) 2018 Cogent Embedded, Inc. 6 * Copyright (C) 2018 Cogent Embedded, Inc.
@@ -25,6 +25,13 @@
25 i2c5 = &i2c5; 25 i2c5 = &i2c5;
26 }; 26 };
27 27
28 /* External CAN clock - to be overridden by boards that provide it */
29 can_clk: can {
30 compatible = "fixed-clock";
31 #clock-cells = <0>;
32 clock-frequency = <0>;
33 };
34
28 cpus { 35 cpus {
29 #address-cells = <1>; 36 #address-cells = <1>;
30 #size-cells = <0>; 37 #size-cells = <0>;
@@ -77,27 +84,36 @@
77 }; 84 };
78 }; 85 };
79 86
80 /* External CAN clock - to be overridden by boards that provide it */ 87 extal_clk: extal {
81 can_clk: can {
82 compatible = "fixed-clock"; 88 compatible = "fixed-clock";
83 #clock-cells = <0>; 89 #clock-cells = <0>;
90 /* This value must be overridden by the board */
84 clock-frequency = <0>; 91 clock-frequency = <0>;
85 }; 92 };
86 93
87 extal_clk: extal { 94 extalr_clk: extalr {
88 compatible = "fixed-clock"; 95 compatible = "fixed-clock";
89 #clock-cells = <0>; 96 #clock-cells = <0>;
90 /* This value must be overridden by the board */ 97 /* This value must be overridden by the board */
91 clock-frequency = <0>; 98 clock-frequency = <0>;
92 }; 99 };
93 100
94 extalr_clk: extalr { 101 /* External PCIe clock - can be overridden by the board */
102 pcie_bus_clk: pcie_bus {
95 compatible = "fixed-clock"; 103 compatible = "fixed-clock";
96 #clock-cells = <0>; 104 #clock-cells = <0>;
97 /* This value must be overridden by the board */
98 clock-frequency = <0>; 105 clock-frequency = <0>;
99 }; 106 };
100 107
108 pmu_a53 {
109 compatible = "arm,cortex-a53-pmu";
110 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
111 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
112 <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
113 <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
114 interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>;
115 };
116
101 psci { 117 psci {
102 compatible = "arm,psci-1.0", "arm,psci-0.2"; 118 compatible = "arm,psci-1.0", "arm,psci-0.2";
103 method = "smc"; 119 method = "smc";
@@ -118,6 +134,16 @@
118 #size-cells = <2>; 134 #size-cells = <2>;
119 ranges; 135 ranges;
120 136
137 rwdt: watchdog@e6020000 {
138 compatible = "renesas,r8a77980-wdt",
139 "renesas,rcar-gen3-wdt";
140 reg = <0 0xe6020000 0 0x0c>;
141 clocks = <&cpg CPG_MOD 402>;
142 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
143 resets = <&cpg 402>;
144 status = "disabled";
145 };
146
121 gpio0: gpio@e6050000 { 147 gpio0: gpio@e6050000 {
122 compatible = "renesas,gpio-r8a77980", 148 compatible = "renesas,gpio-r8a77980",
123 "renesas,rcar-gen3-gpio"; 149 "renesas,rcar-gen3-gpio";
@@ -418,6 +444,16 @@
418 status = "disabled"; 444 status = "disabled";
419 }; 445 };
420 446
447 pcie_phy: pcie-phy@e65d0000 {
448 compatible = "renesas,r8a77980-pcie-phy";
449 reg = <0 0xe65d0000 0 0x8000>;
450 #phy-cells = <0>;
451 clocks = <&cpg CPG_MOD 319>;
452 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
453 resets = <&cpg 319>;
454 status = "disabled";
455 };
456
421 canfd: can@e66c0000 { 457 canfd: can@e66c0000 {
422 compatible = "renesas,r8a77980-canfd", 458 compatible = "renesas,r8a77980-canfd",
423 "renesas,rcar-gen3-canfd"; 459 "renesas,rcar-gen3-canfd";
@@ -443,69 +479,6 @@
443 }; 479 };
444 }; 480 };
445 481
446 ipmmu_ds1: mmu@e7740000 {
447 compatible = "renesas,ipmmu-r8a77980";
448 reg = <0 0xe7740000 0 0x1000>;
449 renesas,ipmmu-main = <&ipmmu_mm 0>;
450 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
451 #iommu-cells = <1>;
452 };
453
454 ipmmu_vip0: mmu@e7b00000 {
455 compatible = "renesas,ipmmu-r8a77980";
456 reg = <0 0xe7b00000 0 0x1000>;
457 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
458 #iommu-cells = <1>;
459 };
460
461 ipmmu_vip1: mmu@e7960000 {
462 compatible = "renesas,ipmmu-r8a77980";
463 reg = <0 0xe7960000 0 0x1000>;
464 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
465 #iommu-cells = <1>;
466 };
467
468 ipmmu_ir: mmu@ff8b0000 {
469 compatible = "renesas,ipmmu-r8a77980";
470 reg = <0 0xff8b0000 0 0x1000>;
471 renesas,ipmmu-main = <&ipmmu_mm 3>;
472 power-domains = <&sysc R8A77980_PD_A3IR>;
473 #iommu-cells = <1>;
474 };
475
476 ipmmu_mm: mmu@e67b0000 {
477 compatible = "renesas,ipmmu-r8a77980";
478 reg = <0 0xe67b0000 0 0x1000>;
479 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
480 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
481 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
482 #iommu-cells = <1>;
483 };
484
485 ipmmu_rt: mmu@ffc80000 {
486 compatible = "renesas,ipmmu-r8a77980";
487 reg = <0 0xffc80000 0 0x1000>;
488 renesas,ipmmu-main = <&ipmmu_mm 10>;
489 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
490 #iommu-cells = <1>;
491 };
492
493 ipmmu_vc0: mmu@fe6b0000 {
494 compatible = "renesas,ipmmu-r8a77980";
495 reg = <0 0xfe6b0000 0 0x1000>;
496 renesas,ipmmu-main = <&ipmmu_mm 12>;
497 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
498 #iommu-cells = <1>;
499 };
500
501 ipmmu_vi0: mmu@febd0000 {
502 compatible = "renesas,ipmmu-r8a77980";
503 reg = <0 0xfebd0000 0 0x1000>;
504 renesas,ipmmu-main = <&ipmmu_mm 14>;
505 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
506 #iommu-cells = <1>;
507 };
508
509 avb: ethernet@e6800000 { 482 avb: ethernet@e6800000 {
510 compatible = "renesas,etheravb-r8a77980", 483 compatible = "renesas,etheravb-r8a77980",
511 "renesas,etheravb-rcar-gen3"; 484 "renesas,etheravb-rcar-gen3";
@@ -623,6 +596,302 @@
623 status = "disabled"; 596 status = "disabled";
624 }; 597 };
625 598
599 vin0: video@e6ef0000 {
600 compatible = "renesas,vin-r8a77980";
601 reg = <0 0xe6ef0000 0 0x1000>;
602 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
603 clocks = <&cpg CPG_MOD 811>;
604 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
605 resets = <&cpg 811>;
606 status = "disabled";
607
608 ports {
609 #address-cells = <1>;
610 #size-cells = <0>;
611
612 port@1 {
613 #address-cells = <1>;
614 #size-cells = <0>;
615
616 reg = <1>;
617
618 vin0csi40: endpoint@2 {
619 reg = <2>;
620 remote-endpoint = <&csi40vin0>;
621 };
622 };
623 };
624 };
625
626 vin1: video@e6ef1000 {
627 compatible = "renesas,vin-r8a77980";
628 reg = <0 0xe6ef1000 0 0x1000>;
629 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
630 clocks = <&cpg CPG_MOD 810>;
631 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
632 status = "disabled";
633 resets = <&cpg 810>;
634
635 ports {
636 #address-cells = <1>;
637 #size-cells = <0>;
638
639 port@1 {
640 #address-cells = <1>;
641 #size-cells = <0>;
642
643 reg = <1>;
644
645 vin1csi40: endpoint@2 {
646 reg = <2>;
647 remote-endpoint = <&csi40vin1>;
648 };
649 };
650 };
651 };
652
653 vin2: video@e6ef2000 {
654 compatible = "renesas,vin-r8a77980";
655 reg = <0 0xe6ef2000 0 0x1000>;
656 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
657 clocks = <&cpg CPG_MOD 809>;
658 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
659 resets = <&cpg 809>;
660 status = "disabled";
661
662 ports {
663 #address-cells = <1>;
664 #size-cells = <0>;
665
666 port@1 {
667 #address-cells = <1>;
668 #size-cells = <0>;
669
670 reg = <1>;
671
672 vin2csi40: endpoint@2 {
673 reg = <2>;
674 remote-endpoint = <&csi40vin2>;
675 };
676 };
677 };
678 };
679
680 vin3: video@e6ef3000 {
681 compatible = "renesas,vin-r8a77980";
682 reg = <0 0xe6ef3000 0 0x1000>;
683 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
684 clocks = <&cpg CPG_MOD 808>;
685 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
686 resets = <&cpg 808>;
687 status = "disabled";
688
689 ports {
690 #address-cells = <1>;
691 #size-cells = <0>;
692
693 port@1 {
694 #address-cells = <1>;
695 #size-cells = <0>;
696
697 reg = <1>;
698
699 vin3csi40: endpoint@2 {
700 reg = <2>;
701 remote-endpoint = <&csi40vin3>;
702 };
703 };
704 };
705 };
706
707 vin4: video@e6ef4000 {
708 compatible = "renesas,vin-r8a77980";
709 reg = <0 0xe6ef4000 0 0x1000>;
710 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
711 clocks = <&cpg CPG_MOD 807>;
712 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
713 resets = <&cpg 807>;
714 status = "disabled";
715
716 ports {
717 #address-cells = <1>;
718 #size-cells = <0>;
719
720 port@1 {
721 #address-cells = <1>;
722 #size-cells = <0>;
723
724 reg = <1>;
725
726 vin4csi41: endpoint@2 {
727 reg = <2>;
728 remote-endpoint = <&csi41vin4>;
729 };
730 };
731 };
732 };
733
734 vin5: video@e6ef5000 {
735 compatible = "renesas,vin-r8a77980";
736 reg = <0 0xe6ef5000 0 0x1000>;
737 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
738 clocks = <&cpg CPG_MOD 806>;
739 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
740 resets = <&cpg 806>;
741 status = "disabled";
742
743 ports {
744 #address-cells = <1>;
745 #size-cells = <0>;
746
747 port@1 {
748 #address-cells = <1>;
749 #size-cells = <0>;
750
751 reg = <1>;
752
753 vin5csi41: endpoint@2 {
754 reg = <2>;
755 remote-endpoint = <&csi41vin5>;
756 };
757 };
758 };
759 };
760
761 vin6: video@e6ef6000 {
762 compatible = "renesas,vin-r8a77980";
763 reg = <0 0xe6ef6000 0 0x1000>;
764 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
765 clocks = <&cpg CPG_MOD 805>;
766 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
767 resets = <&cpg 805>;
768 status = "disabled";
769
770 ports {
771 #address-cells = <1>;
772 #size-cells = <0>;
773
774 port@1 {
775 #address-cells = <1>;
776 #size-cells = <0>;
777
778 reg = <1>;
779
780 vin6csi41: endpoint@2 {
781 reg = <2>;
782 remote-endpoint = <&csi41vin6>;
783 };
784 };
785 };
786 };
787
788 vin7: video@e6ef7000 {
789 compatible = "renesas,vin-r8a77980";
790 reg = <0 0xe6ef7000 0 0x1000>;
791 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
792 clocks = <&cpg CPG_MOD 804>;
793 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
794 resets = <&cpg 804>;
795 status = "disabled";
796
797 ports {
798 #address-cells = <1>;
799 #size-cells = <0>;
800
801 port@1 {
802 #address-cells = <1>;
803 #size-cells = <0>;
804
805 reg = <1>;
806
807 vin7csi41: endpoint@2 {
808 reg = <2>;
809 remote-endpoint = <&csi41vin7>;
810 };
811 };
812 };
813 };
814
815 vin8: video@e6ef8000 {
816 compatible = "renesas,vin-r8a77980";
817 reg = <0 0xe6ef8000 0 0x1000>;
818 interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
819 clocks = <&cpg CPG_MOD 628>;
820 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
821 resets = <&cpg 628>;
822 status = "disabled";
823 };
824
825 vin9: video@e6ef9000 {
826 compatible = "renesas,vin-r8a77980";
827 reg = <0 0xe6ef9000 0 0x1000>;
828 interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
829 clocks = <&cpg CPG_MOD 627>;
830 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
831 resets = <&cpg 627>;
832 status = "disabled";
833 };
834
835 vin10: video@e6efa000 {
836 compatible = "renesas,vin-r8a77980";
837 reg = <0 0xe6efa000 0 0x1000>;
838 interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>;
839 clocks = <&cpg CPG_MOD 625>;
840 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
841 resets = <&cpg 625>;
842 status = "disabled";
843 };
844
845 vin11: video@e6efb000 {
846 compatible = "renesas,vin-r8a77980";
847 reg = <0 0xe6efb000 0 0x1000>;
848 interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>;
849 clocks = <&cpg CPG_MOD 618>;
850 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
851 resets = <&cpg 618>;
852 status = "disabled";
853 };
854
855 vin12: video@e6efc000 {
856 compatible = "renesas,vin-r8a77980";
857 reg = <0 0xe6efc000 0 0x1000>;
858 interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
859 clocks = <&cpg CPG_MOD 612>;
860 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
861 resets = <&cpg 612>;
862 status = "disabled";
863 };
864
865 vin13: video@e6efd000 {
866 compatible = "renesas,vin-r8a77980";
867 reg = <0 0xe6efd000 0 0x1000>;
868 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
869 clocks = <&cpg CPG_MOD 608>;
870 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
871 resets = <&cpg 608>;
872 status = "disabled";
873 };
874
875 vin14: video@e6efe000 {
876 compatible = "renesas,vin-r8a77980";
877 reg = <0 0xe6efe000 0 0x1000>;
878 interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>;
879 clocks = <&cpg CPG_MOD 605>;
880 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
881 resets = <&cpg 605>;
882 status = "disabled";
883 };
884
885 vin15: video@e6eff000 {
886 compatible = "renesas,vin-r8a77980";
887 reg = <0 0xe6eff000 0 0x1000>;
888 interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>;
889 clocks = <&cpg CPG_MOD 604>;
890 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
891 resets = <&cpg 604>;
892 status = "disabled";
893 };
894
626 dmac1: dma-controller@e7300000 { 895 dmac1: dma-controller@e7300000 {
627 compatible = "renesas,dmac-r8a77980", 896 compatible = "renesas,dmac-r8a77980",
628 "renesas,rcar-dmac"; 897 "renesas,rcar-dmac";
@@ -703,6 +972,69 @@
703 status = "disabled"; 972 status = "disabled";
704 }; 973 };
705 974
975 ipmmu_ds1: mmu@e7740000 {
976 compatible = "renesas,ipmmu-r8a77980";
977 reg = <0 0xe7740000 0 0x1000>;
978 renesas,ipmmu-main = <&ipmmu_mm 0>;
979 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
980 #iommu-cells = <1>;
981 };
982
983 ipmmu_ir: mmu@ff8b0000 {
984 compatible = "renesas,ipmmu-r8a77980";
985 reg = <0 0xff8b0000 0 0x1000>;
986 renesas,ipmmu-main = <&ipmmu_mm 3>;
987 power-domains = <&sysc R8A77980_PD_A3IR>;
988 #iommu-cells = <1>;
989 };
990
991 ipmmu_mm: mmu@e67b0000 {
992 compatible = "renesas,ipmmu-r8a77980";
993 reg = <0 0xe67b0000 0 0x1000>;
994 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
995 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
996 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
997 #iommu-cells = <1>;
998 };
999
1000 ipmmu_rt: mmu@ffc80000 {
1001 compatible = "renesas,ipmmu-r8a77980";
1002 reg = <0 0xffc80000 0 0x1000>;
1003 renesas,ipmmu-main = <&ipmmu_mm 10>;
1004 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1005 #iommu-cells = <1>;
1006 };
1007
1008 ipmmu_vc0: mmu@fe6b0000 {
1009 compatible = "renesas,ipmmu-r8a77980";
1010 reg = <0 0xfe6b0000 0 0x1000>;
1011 renesas,ipmmu-main = <&ipmmu_mm 12>;
1012 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1013 #iommu-cells = <1>;
1014 };
1015
1016 ipmmu_vi0: mmu@febd0000 {
1017 compatible = "renesas,ipmmu-r8a77980";
1018 reg = <0 0xfebd0000 0 0x1000>;
1019 renesas,ipmmu-main = <&ipmmu_mm 14>;
1020 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1021 #iommu-cells = <1>;
1022 };
1023
1024 ipmmu_vip0: mmu@e7b00000 {
1025 compatible = "renesas,ipmmu-r8a77980";
1026 reg = <0 0xe7b00000 0 0x1000>;
1027 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1028 #iommu-cells = <1>;
1029 };
1030
1031 ipmmu_vip1: mmu@e7960000 {
1032 compatible = "renesas,ipmmu-r8a77980";
1033 reg = <0 0xe7960000 0 0x1000>;
1034 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1035 #iommu-cells = <1>;
1036 };
1037
706 mmc0: mmc@ee140000 { 1038 mmc0: mmc@ee140000 {
707 compatible = "renesas,sdhi-r8a77980", 1039 compatible = "renesas,sdhi-r8a77980",
708 "renesas,rcar-gen3-sdhi"; 1040 "renesas,rcar-gen3-sdhi";
@@ -732,6 +1064,38 @@
732 resets = <&cpg 408>; 1064 resets = <&cpg 408>;
733 }; 1065 };
734 1066
1067 pciec: pcie@fe000000 {
1068 compatible = "renesas,pcie-r8a77980",
1069 "renesas,pcie-rcar-gen3";
1070 reg = <0 0xfe000000 0 0x80000>;
1071 #address-cells = <3>;
1072 #size-cells = <2>;
1073 bus-range = <0x00 0xff>;
1074 device_type = "pci";
1075 ranges = <
1076 0x01000000 0 0x00000000 0 0xfe100000 0 0x0100000
1077 0x02000000 0 0xfe200000 0 0xfe200000 0 0x0200000
1078 0x02000000 0 0x30000000 0 0x30000000 0 0x8000000
1079 0x42000000 0 0x38000000 0 0x38000000 0 0x8000000
1080 >;
1081 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000
1082 0 0x80000000>;
1083 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
1084 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
1085 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
1086 #interrupt-cells = <1>;
1087 interrupt-map-mask = <0 0 0 0>;
1088 interrupt-map = <0 0 0 0 &gic GIC_SPI 148
1089 IRQ_TYPE_LEVEL_HIGH>;
1090 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
1091 clock-names = "pcie", "pcie_bus";
1092 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1093 resets = <&cpg 319>;
1094 phys = <&pcie_phy>;
1095 phy-names = "pcie";
1096 status = "disabled";
1097 };
1098
735 vspd0: vsp@fea20000 { 1099 vspd0: vsp@fea20000 {
736 compatible = "renesas,vsp2"; 1100 compatible = "renesas,vsp2";
737 reg = <0 0xfea20000 0 0x5000>; 1101 reg = <0 0xfea20000 0 0x5000>;
@@ -750,6 +1114,84 @@
750 resets = <&cpg 603>; 1114 resets = <&cpg 603>;
751 }; 1115 };
752 1116
1117 csi40: csi2@feaa0000 {
1118 compatible = "renesas,r8a77980-csi2";
1119 reg = <0 0xfeaa0000 0 0x10000>;
1120 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
1121 clocks = <&cpg CPG_MOD 716>;
1122 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1123 resets = <&cpg 716>;
1124 status = "disabled";
1125
1126 ports {
1127 #address-cells = <1>;
1128 #size-cells = <0>;
1129
1130 port@1 {
1131 #address-cells = <1>;
1132 #size-cells = <0>;
1133
1134 reg = <1>;
1135
1136 csi40vin0: endpoint@0 {
1137 reg = <0>;
1138 remote-endpoint = <&vin0csi40>;
1139 };
1140 csi40vin1: endpoint@1 {
1141 reg = <1>;
1142 remote-endpoint = <&vin1csi40>;
1143 };
1144 csi40vin2: endpoint@2 {
1145 reg = <2>;
1146 remote-endpoint = <&vin2csi40>;
1147 };
1148 csi40vin3: endpoint@3 {
1149 reg = <3>;
1150 remote-endpoint = <&vin3csi40>;
1151 };
1152 };
1153 };
1154 };
1155
1156 csi41: csi2@feab0000 {
1157 compatible = "renesas,r8a77980-csi2";
1158 reg = <0 0xfeab0000 0 0x10000>;
1159 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
1160 clocks = <&cpg CPG_MOD 715>;
1161 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1162 resets = <&cpg 715>;
1163 status = "disabled";
1164
1165 ports {
1166 #address-cells = <1>;
1167 #size-cells = <0>;
1168
1169 port@1 {
1170 #address-cells = <1>;
1171 #size-cells = <0>;
1172
1173 reg = <1>;
1174
1175 csi41vin4: endpoint@0 {
1176 reg = <0>;
1177 remote-endpoint = <&vin4csi41>;
1178 };
1179 csi41vin5: endpoint@1 {
1180 reg = <1>;
1181 remote-endpoint = <&vin5csi41>;
1182 };
1183 csi41vin6: endpoint@2 {
1184 reg = <2>;
1185 remote-endpoint = <&vin6csi41>;
1186 };
1187 csi41vin7: endpoint@3 {
1188 reg = <3>;
1189 remote-endpoint = <&vin7csi41>;
1190 };
1191 };
1192 };
1193 };
1194
753 du: display@feb00000 { 1195 du: display@feb00000 {
754 compatible = "renesas,du-r8a77980", 1196 compatible = "renesas,du-r8a77980",
755 "renesas,du-r8a77970"; 1197 "renesas,du-r8a77970";
diff --git a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
index 2bc3a4884b00..31934a310ac3 100644
--- a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
@@ -67,6 +67,16 @@
67 }; 67 };
68 }; 68 };
69 69
70 pwm3_pins: pwm3 {
71 groups = "pwm3_b";
72 function = "pwm3";
73 };
74
75 pwm5_pins: pwm5 {
76 groups = "pwm5_a";
77 function = "pwm5";
78 };
79
70 usb0_pins: usb { 80 usb0_pins: usb {
71 groups = "usb0_b"; 81 groups = "usb0_b";
72 function = "usb0"; 82 function = "usb0";
@@ -78,6 +88,20 @@
78 }; 88 };
79}; 89};
80 90
91&pwm3 {
92 pinctrl-0 = <&pwm3_pins>;
93 pinctrl-names = "default";
94
95 status = "okay";
96};
97
98&pwm5 {
99 pinctrl-0 = <&pwm5_pins>;
100 pinctrl-names = "default";
101
102 status = "okay";
103};
104
81&rwdt { 105&rwdt {
82 timeout-sec = <60>; 106 timeout-sec = <60>;
83 status = "okay"; 107 status = "okay";
diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
index ae89260baad9..5ce268cda03b 100644
--- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
@@ -1,11 +1,11 @@
1/* SPDX-License-Identifier: GPL-2.0 */ 1/* SPDX-License-Identifier: GPL-2.0 */
2/* 2/*
3 * Device Tree Source for the r8a77990 SoC 3 * Device Tree Source for the R-Car E3 (R8A77990) SoC
4 * 4 *
5 * Copyright (C) 2018 Renesas Electronics Corp. 5 * Copyright (C) 2018 Renesas Electronics Corp.
6 */ 6 */
7 7
8#include <dt-bindings/clock/renesas-cpg-mssr.h> 8#include <dt-bindings/clock/r8a77990-cpg-mssr.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/power/r8a77990-sysc.h> 10#include <dt-bindings/power/r8a77990-sysc.h>
11 11
@@ -14,6 +14,17 @@
14 #address-cells = <2>; 14 #address-cells = <2>;
15 #size-cells = <2>; 15 #size-cells = <2>;
16 16
17 aliases {
18 i2c0 = &i2c0;
19 i2c1 = &i2c1;
20 i2c2 = &i2c2;
21 i2c3 = &i2c3;
22 i2c4 = &i2c4;
23 i2c5 = &i2c5;
24 i2c6 = &i2c6;
25 i2c7 = &i2c7;
26 };
27
17 cpus { 28 cpus {
18 #address-cells = <1>; 29 #address-cells = <1>;
19 #size-cells = <0>; 30 #size-cells = <0>;
@@ -22,7 +33,7 @@
22 compatible = "arm,cortex-a53", "arm,armv8"; 33 compatible = "arm,cortex-a53", "arm,armv8";
23 reg = <0>; 34 reg = <0>;
24 device_type = "cpu"; 35 device_type = "cpu";
25 power-domains = <&sysc 5>; 36 power-domains = <&sysc R8A77990_PD_CA53_CPU0>;
26 next-level-cache = <&L2_CA53>; 37 next-level-cache = <&L2_CA53>;
27 enable-method = "psci"; 38 enable-method = "psci";
28 }; 39 };
@@ -31,14 +42,14 @@
31 compatible = "arm,cortex-a53", "arm,armv8"; 42 compatible = "arm,cortex-a53", "arm,armv8";
32 reg = <1>; 43 reg = <1>;
33 device_type = "cpu"; 44 device_type = "cpu";
34 power-domains = <&sysc 6>; 45 power-domains = <&sysc R8A77990_PD_CA53_CPU1>;
35 next-level-cache = <&L2_CA53>; 46 next-level-cache = <&L2_CA53>;
36 enable-method = "psci"; 47 enable-method = "psci";
37 }; 48 };
38 49
39 L2_CA53: cache-controller-0 { 50 L2_CA53: cache-controller-0 {
40 compatible = "cache"; 51 compatible = "cache";
41 power-domains = <&sysc 21>; 52 power-domains = <&sysc R8A77990_PD_CA53_SCU>;
42 cache-unified; 53 cache-unified;
43 cache-level = <2>; 54 cache-level = <2>;
44 }; 55 };
@@ -63,6 +74,13 @@
63 method = "smc"; 74 method = "smc";
64 }; 75 };
65 76
77 /* External SCIF clock - to be overridden by boards that provide it */
78 scif_clk: scif {
79 compatible = "fixed-clock";
80 #clock-cells = <0>;
81 clock-frequency = <0>;
82 };
83
66 soc: soc { 84 soc: soc {
67 compatible = "simple-bus"; 85 compatible = "simple-bus";
68 interrupt-parent = <&gic>; 86 interrupt-parent = <&gic>;
@@ -75,7 +93,7 @@
75 "renesas,rcar-gen3-wdt"; 93 "renesas,rcar-gen3-wdt";
76 reg = <0 0xe6020000 0 0x0c>; 94 reg = <0 0xe6020000 0 0x0c>;
77 clocks = <&cpg CPG_MOD 402>; 95 clocks = <&cpg CPG_MOD 402>;
78 power-domains = <&sysc 32>; 96 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
79 resets = <&cpg 402>; 97 resets = <&cpg 402>;
80 status = "disabled"; 98 status = "disabled";
81 }; 99 };
@@ -91,7 +109,7 @@
91 #interrupt-cells = <2>; 109 #interrupt-cells = <2>;
92 interrupt-controller; 110 interrupt-controller;
93 clocks = <&cpg CPG_MOD 912>; 111 clocks = <&cpg CPG_MOD 912>;
94 power-domains = <&sysc 32>; 112 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
95 resets = <&cpg 912>; 113 resets = <&cpg 912>;
96 }; 114 };
97 115
@@ -106,7 +124,7 @@
106 #interrupt-cells = <2>; 124 #interrupt-cells = <2>;
107 interrupt-controller; 125 interrupt-controller;
108 clocks = <&cpg CPG_MOD 911>; 126 clocks = <&cpg CPG_MOD 911>;
109 power-domains = <&sysc 32>; 127 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
110 resets = <&cpg 911>; 128 resets = <&cpg 911>;
111 }; 129 };
112 130
@@ -121,7 +139,7 @@
121 #interrupt-cells = <2>; 139 #interrupt-cells = <2>;
122 interrupt-controller; 140 interrupt-controller;
123 clocks = <&cpg CPG_MOD 910>; 141 clocks = <&cpg CPG_MOD 910>;
124 power-domains = <&sysc 32>; 142 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
125 resets = <&cpg 910>; 143 resets = <&cpg 910>;
126 }; 144 };
127 145
@@ -136,7 +154,7 @@
136 #interrupt-cells = <2>; 154 #interrupt-cells = <2>;
137 interrupt-controller; 155 interrupt-controller;
138 clocks = <&cpg CPG_MOD 909>; 156 clocks = <&cpg CPG_MOD 909>;
139 power-domains = <&sysc 32>; 157 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
140 resets = <&cpg 909>; 158 resets = <&cpg 909>;
141 }; 159 };
142 160
@@ -151,7 +169,7 @@
151 #interrupt-cells = <2>; 169 #interrupt-cells = <2>;
152 interrupt-controller; 170 interrupt-controller;
153 clocks = <&cpg CPG_MOD 908>; 171 clocks = <&cpg CPG_MOD 908>;
154 power-domains = <&sysc 32>; 172 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
155 resets = <&cpg 908>; 173 resets = <&cpg 908>;
156 }; 174 };
157 175
@@ -166,7 +184,7 @@
166 #interrupt-cells = <2>; 184 #interrupt-cells = <2>;
167 interrupt-controller; 185 interrupt-controller;
168 clocks = <&cpg CPG_MOD 907>; 186 clocks = <&cpg CPG_MOD 907>;
169 power-domains = <&sysc 32>; 187 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
170 resets = <&cpg 907>; 188 resets = <&cpg 907>;
171 }; 189 };
172 190
@@ -181,10 +199,122 @@
181 #interrupt-cells = <2>; 199 #interrupt-cells = <2>;
182 interrupt-controller; 200 interrupt-controller;
183 clocks = <&cpg CPG_MOD 906>; 201 clocks = <&cpg CPG_MOD 906>;
184 power-domains = <&sysc 32>; 202 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
185 resets = <&cpg 906>; 203 resets = <&cpg 906>;
186 }; 204 };
187 205
206 i2c0: i2c@e6500000 {
207 #address-cells = <1>;
208 #size-cells = <0>;
209 compatible = "renesas,i2c-r8a77990",
210 "renesas,rcar-gen3-i2c";
211 reg = <0 0xe6500000 0 0x40>;
212 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
213 clocks = <&cpg CPG_MOD 931>;
214 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
215 resets = <&cpg 931>;
216 i2c-scl-internal-delay-ns = <110>;
217 status = "disabled";
218 };
219
220 i2c1: i2c@e6508000 {
221 #address-cells = <1>;
222 #size-cells = <0>;
223 compatible = "renesas,i2c-r8a77990",
224 "renesas,rcar-gen3-i2c";
225 reg = <0 0xe6508000 0 0x40>;
226 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
227 clocks = <&cpg CPG_MOD 930>;
228 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
229 resets = <&cpg 930>;
230 i2c-scl-internal-delay-ns = <6>;
231 status = "disabled";
232 };
233
234 i2c2: i2c@e6510000 {
235 #address-cells = <1>;
236 #size-cells = <0>;
237 compatible = "renesas,i2c-r8a77990",
238 "renesas,rcar-gen3-i2c";
239 reg = <0 0xe6510000 0 0x40>;
240 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
241 clocks = <&cpg CPG_MOD 929>;
242 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
243 resets = <&cpg 929>;
244 i2c-scl-internal-delay-ns = <6>;
245 status = "disabled";
246 };
247
248 i2c3: i2c@e66d0000 {
249 #address-cells = <1>;
250 #size-cells = <0>;
251 compatible = "renesas,i2c-r8a77990",
252 "renesas,rcar-gen3-i2c";
253 reg = <0 0xe66d0000 0 0x40>;
254 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
255 clocks = <&cpg CPG_MOD 928>;
256 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
257 resets = <&cpg 928>;
258 i2c-scl-internal-delay-ns = <110>;
259 status = "disabled";
260 };
261
262 i2c4: i2c@e66d8000 {
263 #address-cells = <1>;
264 #size-cells = <0>;
265 compatible = "renesas,i2c-r8a77990",
266 "renesas,rcar-gen3-i2c";
267 reg = <0 0xe66d8000 0 0x40>;
268 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
269 clocks = <&cpg CPG_MOD 927>;
270 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
271 resets = <&cpg 927>;
272 i2c-scl-internal-delay-ns = <6>;
273 status = "disabled";
274 };
275
276 i2c5: i2c@e66e0000 {
277 #address-cells = <1>;
278 #size-cells = <0>;
279 compatible = "renesas,i2c-r8a77990",
280 "renesas,rcar-gen3-i2c";
281 reg = <0 0xe66e0000 0 0x40>;
282 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
283 clocks = <&cpg CPG_MOD 919>;
284 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
285 resets = <&cpg 919>;
286 i2c-scl-internal-delay-ns = <6>;
287 status = "disabled";
288 };
289
290 i2c6: i2c@e66e8000 {
291 #address-cells = <1>;
292 #size-cells = <0>;
293 compatible = "renesas,i2c-r8a77990",
294 "renesas,rcar-gen3-i2c";
295 reg = <0 0xe66e8000 0 0x40>;
296 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
297 clocks = <&cpg CPG_MOD 918>;
298 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
299 resets = <&cpg 918>;
300 i2c-scl-internal-delay-ns = <6>;
301 status = "disabled";
302 };
303
304 i2c7: i2c@e6690000 {
305 #address-cells = <1>;
306 #size-cells = <0>;
307 compatible = "renesas,i2c-r8a77990",
308 "renesas,rcar-gen3-i2c";
309 reg = <0 0xe6690000 0 0x40>;
310 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
311 clocks = <&cpg CPG_MOD 1003>;
312 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
313 resets = <&cpg 1003>;
314 i2c-scl-internal-delay-ns = <6>;
315 status = "disabled";
316 };
317
188 pfc: pin-controller@e6060000 { 318 pfc: pin-controller@e6060000 {
189 compatible = "renesas,pfc-r8a77990"; 319 compatible = "renesas,pfc-r8a77990";
190 reg = <0 0xe6060000 0 0x508>; 320 reg = <0 0xe6060000 0 0x508>;
@@ -211,6 +341,108 @@
211 #power-domain-cells = <1>; 341 #power-domain-cells = <1>;
212 }; 342 };
213 343
344 dmac0: dma-controller@e6700000 {
345 compatible = "renesas,dmac-r8a77990",
346 "renesas,rcar-dmac";
347 reg = <0 0xe6700000 0 0x10000>;
348 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH
349 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
350 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
351 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
352 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
353 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
354 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
355 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
356 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
357 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
358 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
359 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
360 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
361 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
362 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
363 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH
364 GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
365 interrupt-names = "error",
366 "ch0", "ch1", "ch2", "ch3",
367 "ch4", "ch5", "ch6", "ch7",
368 "ch8", "ch9", "ch10", "ch11",
369 "ch12", "ch13", "ch14", "ch15";
370 clocks = <&cpg CPG_MOD 219>;
371 clock-names = "fck";
372 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
373 resets = <&cpg 219>;
374 #dma-cells = <1>;
375 dma-channels = <16>;
376 };
377
378 dmac1: dma-controller@e7300000 {
379 compatible = "renesas,dmac-r8a77990",
380 "renesas,rcar-dmac";
381 reg = <0 0xe7300000 0 0x10000>;
382 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
383 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
384 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
385 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
386 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
387 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
388 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
389 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
390 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
391 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
392 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
393 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
394 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
395 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
396 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
397 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH
398 GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
399 interrupt-names = "error",
400 "ch0", "ch1", "ch2", "ch3",
401 "ch4", "ch5", "ch6", "ch7",
402 "ch8", "ch9", "ch10", "ch11",
403 "ch12", "ch13", "ch14", "ch15";
404 clocks = <&cpg CPG_MOD 218>;
405 clock-names = "fck";
406 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
407 resets = <&cpg 218>;
408 #dma-cells = <1>;
409 dma-channels = <16>;
410 };
411
412 dmac2: dma-controller@e7310000 {
413 compatible = "renesas,dmac-r8a77990",
414 "renesas,rcar-dmac";
415 reg = <0 0xe7310000 0 0x10000>;
416 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH
417 GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH
418 GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH
419 GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH
420 GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH
421 GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH
422 GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH
423 GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH
424 GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH
425 GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH
426 GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH
427 GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH
428 GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH
429 GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH
430 GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH
431 GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH
432 GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
433 interrupt-names = "error",
434 "ch0", "ch1", "ch2", "ch3",
435 "ch4", "ch5", "ch6", "ch7",
436 "ch8", "ch9", "ch10", "ch11",
437 "ch12", "ch13", "ch14", "ch15";
438 clocks = <&cpg CPG_MOD 217>;
439 clock-names = "fck";
440 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
441 resets = <&cpg 217>;
442 #dma-cells = <1>;
443 dma-channels = <16>;
444 };
445
214 ipmmu_ds0: mmu@e6740000 { 446 ipmmu_ds0: mmu@e6740000 {
215 compatible = "renesas,ipmmu-r8a77990"; 447 compatible = "renesas,ipmmu-r8a77990";
216 reg = <0 0xe6740000 0 0x1000>; 448 reg = <0 0xe6740000 0 0x1000>;
@@ -329,7 +561,7 @@
329 "ch20", "ch21", "ch22", "ch23", 561 "ch20", "ch21", "ch22", "ch23",
330 "ch24"; 562 "ch24";
331 clocks = <&cpg CPG_MOD 812>; 563 clocks = <&cpg CPG_MOD 812>;
332 power-domains = <&sysc 32>; 564 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
333 resets = <&cpg 812>; 565 resets = <&cpg 812>;
334 phy-mode = "rgmii"; 566 phy-mode = "rgmii";
335 #address-cells = <1>; 567 #address-cells = <1>;
@@ -337,18 +569,191 @@
337 status = "disabled"; 569 status = "disabled";
338 }; 570 };
339 571
572 pwm0: pwm@e6e30000 {
573 compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
574 reg = <0 0xe6e30000 0 0x8>;
575 clocks = <&cpg CPG_MOD 523>;
576 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
577 resets = <&cpg 523>;
578 #pwm-cells = <2>;
579 status = "disabled";
580 };
581
582 pwm1: pwm@e6e31000 {
583 compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
584 reg = <0 0xe6e31000 0 0x8>;
585 clocks = <&cpg CPG_MOD 523>;
586 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
587 resets = <&cpg 523>;
588 #pwm-cells = <2>;
589 status = "disabled";
590 };
591
592 pwm2: pwm@e6e32000 {
593 compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
594 reg = <0 0xe6e32000 0 0x8>;
595 clocks = <&cpg CPG_MOD 523>;
596 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
597 resets = <&cpg 523>;
598 #pwm-cells = <2>;
599 status = "disabled";
600 };
601
602 pwm3: pwm@e6e33000 {
603 compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
604 reg = <0 0xe6e33000 0 0x8>;
605 clocks = <&cpg CPG_MOD 523>;
606 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
607 resets = <&cpg 523>;
608 #pwm-cells = <2>;
609 status = "disabled";
610 };
611
612 pwm4: pwm@e6e34000 {
613 compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
614 reg = <0 0xe6e34000 0 0x8>;
615 clocks = <&cpg CPG_MOD 523>;
616 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
617 resets = <&cpg 523>;
618 #pwm-cells = <2>;
619 status = "disabled";
620 };
621
622 pwm5: pwm@e6e35000 {
623 compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
624 reg = <0 0xe6e35000 0 0x8>;
625 clocks = <&cpg CPG_MOD 523>;
626 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
627 resets = <&cpg 523>;
628 #pwm-cells = <2>;
629 status = "disabled";
630 };
631
632 pwm6: pwm@e6e36000 {
633 compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
634 reg = <0 0xe6e36000 0 0x8>;
635 clocks = <&cpg CPG_MOD 523>;
636 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
637 resets = <&cpg 523>;
638 #pwm-cells = <2>;
639 status = "disabled";
640 };
641
340 scif2: serial@e6e88000 { 642 scif2: serial@e6e88000 {
341 compatible = "renesas,scif-r8a77990", 643 compatible = "renesas,scif-r8a77990",
342 "renesas,rcar-gen3-scif", "renesas,scif"; 644 "renesas,rcar-gen3-scif", "renesas,scif";
343 reg = <0 0xe6e88000 0 64>; 645 reg = <0 0xe6e88000 0 64>;
344 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 646 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
345 clocks = <&cpg CPG_MOD 310>; 647 clocks = <&cpg CPG_MOD 310>,
346 clock-names = "fck"; 648 <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
347 power-domains = <&sysc 32>; 649 <&scif_clk>;
650 clock-names = "fck", "brg_int", "scif_clk";
651
652 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
348 resets = <&cpg 310>; 653 resets = <&cpg 310>;
349 status = "disabled"; 654 status = "disabled";
350 }; 655 };
351 656
657 msiof0: spi@e6e90000 {
658 compatible = "renesas,msiof-r8a77990",
659 "renesas,rcar-gen3-msiof";
660 reg = <0 0xe6e90000 0 0x0064>;
661 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
662 clocks = <&cpg CPG_MOD 211>;
663 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
664 resets = <&cpg 211>;
665 #address-cells = <1>;
666 #size-cells = <0>;
667 status = "disabled";
668 };
669
670 msiof1: spi@e6ea0000 {
671 compatible = "renesas,msiof-r8a77990",
672 "renesas,rcar-gen3-msiof";
673 reg = <0 0xe6ea0000 0 0x0064>;
674 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
675 clocks = <&cpg CPG_MOD 210>;
676 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
677 resets = <&cpg 210>;
678 #address-cells = <1>;
679 #size-cells = <0>;
680 status = "disabled";
681 };
682
683 msiof2: spi@e6c00000 {
684 compatible = "renesas,msiof-r8a77990",
685 "renesas,rcar-gen3-msiof";
686 reg = <0 0xe6c00000 0 0x0064>;
687 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
688 clocks = <&cpg CPG_MOD 209>;
689 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
690 resets = <&cpg 209>;
691 #address-cells = <1>;
692 #size-cells = <0>;
693 status = "disabled";
694 };
695
696 msiof3: spi@e6c10000 {
697 compatible = "renesas,msiof-r8a77990",
698 "renesas,rcar-gen3-msiof";
699 reg = <0 0xe6c10000 0 0x0064>;
700 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
701 clocks = <&cpg CPG_MOD 208>;
702 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
703 resets = <&cpg 208>;
704 #address-cells = <1>;
705 #size-cells = <0>;
706 status = "disabled";
707 };
708
709 vin4: video@e6ef4000 {
710 compatible = "renesas,vin-r8a77990";
711 reg = <0 0xe6ef4000 0 0x1000>;
712 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
713 clocks = <&cpg CPG_MOD 807>;
714 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
715 resets = <&cpg 807>;
716 renesas,id = <4>;
717 status = "disabled";
718
719 ports {
720 #address-cells = <1>;
721 #size-cells = <0>;
722
723 port@1 {
724 reg = <1>;
725
726 vin4csi40: endpoint {
727 remote-endpoint= <&csi40vin4>;
728 };
729 };
730 };
731 };
732
733 vin5: video@e6ef5000 {
734 compatible = "renesas,vin-r8a77990";
735 reg = <0 0xe6ef5000 0 0x1000>;
736 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
737 clocks = <&cpg CPG_MOD 806>;
738 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
739 resets = <&cpg 806>;
740 renesas,id = <5>;
741 status = "disabled";
742
743 ports {
744 #address-cells = <1>;
745 #size-cells = <0>;
746
747 port@1 {
748 reg = <1>;
749
750 vin5csi40: endpoint {
751 remote-endpoint= <&csi40vin5>;
752 };
753 };
754 };
755 };
756
352 xhci0: usb@ee000000 { 757 xhci0: usb@ee000000 {
353 compatible = "renesas,xhci-r8a77990", 758 compatible = "renesas,xhci-r8a77990",
354 "renesas,rcar-gen3-xhci"; 759 "renesas,rcar-gen3-xhci";
@@ -367,7 +772,7 @@
367 clocks = <&cpg CPG_MOD 703>; 772 clocks = <&cpg CPG_MOD 703>;
368 phys = <&usb2_phy0>; 773 phys = <&usb2_phy0>;
369 phy-names = "usb"; 774 phy-names = "usb";
370 power-domains = <&sysc 32>; 775 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
371 resets = <&cpg 703>; 776 resets = <&cpg 703>;
372 status = "disabled"; 777 status = "disabled";
373 }; 778 };
@@ -380,7 +785,7 @@
380 phys = <&usb2_phy0>; 785 phys = <&usb2_phy0>;
381 phy-names = "usb"; 786 phy-names = "usb";
382 companion = <&ohci0>; 787 companion = <&ohci0>;
383 power-domains = <&sysc 32>; 788 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
384 resets = <&cpg 703>; 789 resets = <&cpg 703>;
385 status = "disabled"; 790 status = "disabled";
386 }; 791 };
@@ -391,7 +796,7 @@
391 reg = <0 0xee080200 0 0x700>; 796 reg = <0 0xee080200 0 0x700>;
392 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 797 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
393 clocks = <&cpg CPG_MOD 703>; 798 clocks = <&cpg CPG_MOD 703>;
394 power-domains = <&sysc 32>; 799 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
395 resets = <&cpg 703>; 800 resets = <&cpg 703>;
396 #phy-cells = <0>; 801 #phy-cells = <0>;
397 status = "disabled"; 802 status = "disabled";
@@ -410,10 +815,41 @@
410 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 815 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
411 clocks = <&cpg CPG_MOD 408>; 816 clocks = <&cpg CPG_MOD 408>;
412 clock-names = "clk"; 817 clock-names = "clk";
413 power-domains = <&sysc 32>; 818 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
414 resets = <&cpg 408>; 819 resets = <&cpg 408>;
415 }; 820 };
416 821
822 csi40: csi2@feaa0000 {
823 compatible = "renesas,r8a77990-csi2", "renesas,rcar-gen3-csi2";
824 reg = <0 0xfeaa0000 0 0x10000>;
825 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
826 clocks = <&cpg CPG_MOD 716>;
827 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
828 resets = <&cpg 716>;
829 status = "disabled";
830
831 ports {
832 #address-cells = <1>;
833 #size-cells = <0>;
834
835 port@1 {
836 #address-cells = <1>;
837 #size-cells = <0>;
838
839 reg = <1>;
840
841 csi40vin4: endpoint@0 {
842 reg = <0>;
843 remote-endpoint = <&vin4csi40>;
844 };
845 csi40vin5: endpoint@1 {
846 reg = <1>;
847 remote-endpoint = <&vin5csi40>;
848 };
849 };
850 };
851 };
852
417 prr: chipid@fff00044 { 853 prr: chipid@fff00044 {
418 compatible = "renesas,prr"; 854 compatible = "renesas,prr";
419 reg = <0 0xfff00044 0 4>; 855 reg = <0 0xfff00044 0 4>;
diff --git a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
index a8e8f2669d4c..e39b73005381 100644
--- a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
@@ -24,38 +24,6 @@
24 stdout-path = "serial0:115200n8"; 24 stdout-path = "serial0:115200n8";
25 }; 25 };
26 26
27 vga {
28 compatible = "vga-connector";
29
30 port {
31 vga_in: endpoint {
32 remote-endpoint = <&adv7123_out>;
33 };
34 };
35 };
36
37 vga-encoder {
38 compatible = "adi,adv7123";
39
40 ports {
41 #address-cells = <1>;
42 #size-cells = <0>;
43
44 port@0 {
45 reg = <0>;
46 adv7123_in: endpoint {
47 remote-endpoint = <&du_out_rgb>;
48 };
49 };
50 port@1 {
51 reg = <1>;
52 adv7123_out: endpoint {
53 remote-endpoint = <&vga_in>;
54 };
55 };
56 };
57 };
58
59 composite-in { 27 composite-in {
60 compatible = "composite-video-connector"; 28 compatible = "composite-video-connector";
61 29
@@ -101,76 +69,86 @@
101 regulator-always-on; 69 regulator-always-on;
102 }; 70 };
103 71
104 x12_clk: x12 { 72 vga {
105 compatible = "fixed-clock"; 73 compatible = "vga-connector";
106 #clock-cells = <0>;
107 clock-frequency = <74250000>;
108 };
109};
110
111&extal_clk {
112 clock-frequency = <48000000>;
113};
114 74
115&pfc { 75 port {
116 avb0_pins: avb { 76 vga_in: endpoint {
117 mux { 77 remote-endpoint = <&adv7123_out>;
118 groups = "avb0_link", "avb0_mdio", "avb0_mii"; 78 };
119 function = "avb0";
120 }; 79 };
121 }; 80 };
122 81
123 du_pins: du { 82 vga-encoder {
124 groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0"; 83 compatible = "adi,adv7123";
125 function = "du";
126 };
127 84
128 i2c0_pins: i2c0 { 85 ports {
129 groups = "i2c0"; 86 #address-cells = <1>;
130 function = "i2c0"; 87 #size-cells = <0>;
131 };
132 88
133 i2c1_pins: i2c1 { 89 port@0 {
134 groups = "i2c1"; 90 reg = <0>;
135 function = "i2c1"; 91 adv7123_in: endpoint {
92 remote-endpoint = <&du_out_rgb>;
93 };
94 };
95 port@1 {
96 reg = <1>;
97 adv7123_out: endpoint {
98 remote-endpoint = <&vga_in>;
99 };
100 };
101 };
136 }; 102 };
137 103
138 pwm0_pins: pwm0 { 104 x12_clk: x12 {
139 groups = "pwm0_c"; 105 compatible = "fixed-clock";
140 function = "pwm0"; 106 #clock-cells = <0>;
107 clock-frequency = <74250000>;
141 }; 108 };
109};
142 110
143 pwm1_pins: pwm1 { 111&avb {
144 groups = "pwm1_c"; 112 pinctrl-0 = <&avb0_pins>;
145 function = "pwm1"; 113 pinctrl-names = "default";
146 }; 114 renesas,no-ether-link;
115 phy-handle = <&phy0>;
116 phy-mode = "rgmii-txid";
117 status = "okay";
147 118
148 scif2_pins: scif2 { 119 phy0: ethernet-phy@0 {
149 groups = "scif2_data"; 120 rxc-skew-ps = <1500>;
150 function = "scif2"; 121 reg = <0>;
122 interrupt-parent = <&gpio5>;
123 interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
151 }; 124 };
125};
152 126
153 sdhi2_pins: sd2 { 127&du {
154 groups = "mmc_data8", "mmc_ctrl"; 128 pinctrl-0 = <&du_pins>;
155 function = "mmc"; 129 pinctrl-names = "default";
156 power-source = <1800>; 130 status = "okay";
157 };
158 131
159 sdhi2_pins_uhs: sd2_uhs { 132 clocks = <&cpg CPG_MOD 724>,
160 groups = "mmc_data8", "mmc_ctrl"; 133 <&cpg CPG_MOD 723>,
161 function = "mmc"; 134 <&x12_clk>;
162 power-source = <1800>; 135 clock-names = "du.0", "du.1", "dclkin.0";
163 };
164 136
165 usb0_pins: usb0 { 137 ports {
166 groups = "usb0"; 138 port@0 {
167 function = "usb0"; 139 endpoint {
140 remote-endpoint = <&adv7123_in>;
141 };
142 };
168 }; 143 };
144};
169 145
170 vin4_pins_cvbs: vin4 { 146&ehci0 {
171 groups = "vin4_data8", "vin4_sync", "vin4_clk"; 147 status = "okay";
172 function = "vin4"; 148};
173 }; 149
150&extal_clk {
151 clock-frequency = <48000000>;
174}; 152};
175 153
176&i2c0 { 154&i2c0 {
@@ -178,12 +156,6 @@
178 pinctrl-names = "default"; 156 pinctrl-names = "default";
179 status = "okay"; 157 status = "okay";
180 158
181 eeprom@50 {
182 compatible = "rohm,br24t01", "atmel,24c01";
183 reg = <0x50>;
184 pagesize = <8>;
185 };
186
187 composite-in@20 { 159 composite-in@20 {
188 compatible = "adi,adv7180cp"; 160 compatible = "adi,adv7180cp";
189 reg = <0x20>; 161 reg = <0x20>;
@@ -254,6 +226,12 @@
254 }; 226 };
255 }; 227 };
256 }; 228 };
229
230 eeprom@50 {
231 compatible = "rohm,br24t01", "atmel,24c01";
232 reg = <0x50>;
233 pagesize = <8>;
234 };
257}; 235};
258 236
259&i2c1 { 237&i2c1 {
@@ -262,47 +240,88 @@
262 status = "okay"; 240 status = "okay";
263}; 241};
264 242
265&du { 243&ohci0 {
266 pinctrl-0 = <&du_pins>;
267 pinctrl-names = "default";
268 status = "okay"; 244 status = "okay";
245};
269 246
270 clocks = <&cpg CPG_MOD 724>, 247&pfc {
271 <&cpg CPG_MOD 723>, 248 avb0_pins: avb {
272 <&x12_clk>; 249 mux {
273 clock-names = "du.0", "du.1", "dclkin.0"; 250 groups = "avb0_link", "avb0_mdio", "avb0_mii";
274 251 function = "avb0";
275 ports {
276 port@0 {
277 endpoint {
278 remote-endpoint = <&adv7123_in>;
279 };
280 }; 252 };
281 }; 253 };
282};
283 254
284&ehci0 { 255 du_pins: du {
285 status = "okay"; 256 groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
257 function = "du";
258 };
259
260 i2c0_pins: i2c0 {
261 groups = "i2c0";
262 function = "i2c0";
263 };
264
265 i2c1_pins: i2c1 {
266 groups = "i2c1";
267 function = "i2c1";
268 };
269
270 pwm0_pins: pwm0 {
271 groups = "pwm0_c";
272 function = "pwm0";
273 };
274
275 pwm1_pins: pwm1 {
276 groups = "pwm1_c";
277 function = "pwm1";
278 };
279
280 scif2_pins: scif2 {
281 groups = "scif2_data";
282 function = "scif2";
283 };
284
285 sdhi2_pins: sd2 {
286 groups = "mmc_data8", "mmc_ctrl";
287 function = "mmc";
288 power-source = <1800>;
289 };
290
291 sdhi2_pins_uhs: sd2_uhs {
292 groups = "mmc_data8", "mmc_ctrl";
293 function = "mmc";
294 power-source = <1800>;
295 };
296
297 usb0_pins: usb0 {
298 groups = "usb0";
299 function = "usb0";
300 };
301
302 vin4_pins_cvbs: vin4 {
303 groups = "vin4_data8", "vin4_sync", "vin4_clk";
304 function = "vin4";
305 };
286}; 306};
287 307
288&ohci0 { 308&pwm0 {
309 pinctrl-0 = <&pwm0_pins>;
310 pinctrl-names = "default";
311
289 status = "okay"; 312 status = "okay";
290}; 313};
291 314
292&avb { 315&pwm1 {
293 pinctrl-0 = <&avb0_pins>; 316 pinctrl-0 = <&pwm1_pins>;
294 pinctrl-names = "default"; 317 pinctrl-names = "default";
295 renesas,no-ether-link; 318
296 phy-handle = <&phy0>;
297 phy-mode = "rgmii-txid";
298 status = "okay"; 319 status = "okay";
320};
299 321
300 phy0: ethernet-phy@0 { 322&rwdt {
301 rxc-skew-ps = <1500>; 323 timeout-sec = <60>;
302 reg = <0>; 324 status = "okay";
303 interrupt-parent = <&gpio5>;
304 interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
305 };
306}; 325};
307 326
308&scif2 { 327&scif2 {
@@ -333,25 +352,6 @@
333 status = "okay"; 352 status = "okay";
334}; 353};
335 354
336&pwm0 {
337 pinctrl-0 = <&pwm0_pins>;
338 pinctrl-names = "default";
339
340 status = "okay";
341};
342
343&pwm1 {
344 pinctrl-0 = <&pwm1_pins>;
345 pinctrl-names = "default";
346
347 status = "okay";
348};
349
350&rwdt {
351 timeout-sec = <60>;
352 status = "okay";
353};
354
355&vin4 { 355&vin4 {
356 pinctrl-0 = <&vin4_pins_cvbs>; 356 pinctrl-0 = <&vin4_pins_cvbs>;
357 pinctrl-names = "default"; 357 pinctrl-names = "default";
diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
index fe77bc43c447..625ba2b302c7 100644
--- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
@@ -1,6 +1,6 @@
1// SPDX-License-Identifier: GPL-2.0 1// SPDX-License-Identifier: GPL-2.0
2/* 2/*
3 * Device Tree Source for the r8a77995 SoC 3 * Device Tree Source for the R-Car D3 (R8A77995) SoC
4 * 4 *
5 * Copyright (C) 2016 Renesas Electronics Corp. 5 * Copyright (C) 2016 Renesas Electronics Corp.
6 * Copyright (C) 2017 Glider bvba 6 * Copyright (C) 2017 Glider bvba
@@ -391,6 +391,10 @@
391 resets = <&cpg 219>; 391 resets = <&cpg 219>;
392 #dma-cells = <1>; 392 #dma-cells = <1>;
393 dma-channels = <8>; 393 dma-channels = <8>;
394 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
395 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
396 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
397 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>;
394 }; 398 };
395 399
396 dmac1: dma-controller@e7300000 { 400 dmac1: dma-controller@e7300000 {
@@ -415,6 +419,10 @@
415 resets = <&cpg 218>; 419 resets = <&cpg 218>;
416 #dma-cells = <1>; 420 #dma-cells = <1>;
417 dma-channels = <8>; 421 dma-channels = <8>;
422 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
423 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
424 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
425 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>;
418 }; 426 };
419 427
420 dmac2: dma-controller@e7310000 { 428 dmac2: dma-controller@e7310000 {
@@ -439,6 +447,10 @@
439 resets = <&cpg 217>; 447 resets = <&cpg 217>;
440 #dma-cells = <1>; 448 #dma-cells = <1>;
441 dma-channels = <8>; 449 dma-channels = <8>;
450 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
451 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
452 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
453 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>;
442 }; 454 };
443 455
444 ipmmu_ds0: mmu@e6740000 { 456 ipmmu_ds0: mmu@e6740000 {
diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi b/arch/arm64/boot/dts/renesas/salvator-common.dtsi
index 7d3d866a0063..d298f7c9ada1 100644
--- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi
+++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi
@@ -420,7 +420,10 @@
420 420
421 video-receiver@70 { 421 video-receiver@70 {
422 compatible = "adi,adv7482"; 422 compatible = "adi,adv7482";
423 reg = <0x70>; 423 reg = <0x70 0x71 0x72 0x73 0x74 0x75
424 0x60 0x61 0x62 0x63 0x64 0x65>;
425 reg-names = "main", "dpll", "cp", "hdmi", "edid", "repeater",
426 "infoframe", "cbus", "cec", "sdp", "txa", "txb" ;
424 427
425 #address-cells = <1>; 428 #address-cells = <1>;
426 #size-cells = <0>; 429 #size-cells = <0>;
@@ -748,6 +751,7 @@
748 wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; 751 wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
749 bus-width = <4>; 752 bus-width = <4>;
750 sd-uhs-sdr50; 753 sd-uhs-sdr50;
754 sd-uhs-sdr104;
751 status = "okay"; 755 status = "okay";
752}; 756};
753 757
@@ -777,6 +781,7 @@
777 wp-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>; 781 wp-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
778 bus-width = <4>; 782 bus-width = <4>;
779 sd-uhs-sdr50; 783 sd-uhs-sdr50;
784 sd-uhs-sdr104;
780 status = "okay"; 785 status = "okay";
781}; 786};
782 787
diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
index 8bf3091a899c..1b316d79df88 100644
--- a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
+++ b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
@@ -127,7 +127,7 @@
127 #address-cells = <1>; 127 #address-cells = <1>;
128 #size-cells = <0>; 128 #size-cells = <0>;
129 reg = <0x71>; 129 reg = <0x71>;
130 reset-gpios= <&gpio3 15 GPIO_ACTIVE_LOW>; 130 reset-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>;
131 }; 131 };
132}; 132};
133 133
diff --git a/arch/arm64/boot/dts/renesas/ulcb.dtsi b/arch/arm64/boot/dts/renesas/ulcb.dtsi
index 0ead552d7eae..7e6078508ba0 100644
--- a/arch/arm64/boot/dts/renesas/ulcb.dtsi
+++ b/arch/arm64/boot/dts/renesas/ulcb.dtsi
@@ -416,6 +416,7 @@
416 cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; 416 cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
417 bus-width = <4>; 417 bus-width = <4>;
418 sd-uhs-sdr50; 418 sd-uhs-sdr50;
419 sd-uhs-sdr104;
419 status = "okay"; 420 status = "okay";
420}; 421};
421 422
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-23 13:23:45 -0400