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authorOlof Johansson <olof@lixom.net>2018-09-23 09:14:40 -0400
committerOlof Johansson <olof@lixom.net>2018-09-23 09:14:40 -0400
commitfc48cf437a08995943b6fb9fe43ab0fce52ddc2c (patch)
tree78deb49ee9b97c781a3e0e36e1680d5207adb046
parent7adb6bab284627050b778d2f2014ea5857fe8a4b (diff)
parent1926bd6bf20fe306797fbf366902674d2d6c20cc (diff)
Merge tag 'renesas-arm-dt-for-v4.20' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt
Renesas ARM Based SoC DT Updates for v4.20 * R-Car Gen1 SoCs: Include product name in DTSI files for ease of maintenance * R-Car Gen2 SoCs: - Convert to new DU DT bindings - Correct SATA device sizes to 2 MiB * R-Car H2 (r8a7790) based Porter board: Add DA9063 OnKey PMIC node * R-Car E2 (r8a7794) based Silk board: Add DA9063 PMIC, RTC and OnKey nodes * R-Car M2-N (r8a7793) based Gose board: Add DA9210 node for CPU DVFS * RZ/G1C (R8A77470) SoC: - Add GPIO nodes - Add PFC support - Use r8a77470-sysc binding definitions * RZ/G1C (r8a77470) iW-RainboW-G23S dev platform: - Specify EtherAVB PHY IRQ - Add pinctl support for scif1 * RZ/N1D (r9a06g032) SoC: Use r9a06g032-sysctrl binding definitions * tag 'renesas-arm-dt-for-v4.20' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: ARM: dts: r9a06g032: Use r9a06g032-sysctrl binding definitions ARM: dts: Include R-Car Gen1 product name in DTSI files ARM: dts: stout: Add DA9063 OnKey node ARM: dts: silk: Add DA9063 RTC and OnKey node ARM: dts: iwg23s-sbc: specify EtherAVB PHY IRQ ARM: dts: r8a77470: Add GPIO support ARM: dts: silk: Add DA9063 PMIC node ARM: dts: gose: Add DA9210 node for CPU DVFS ARM: dts: rcar-gen2: Convert to new DU DT bindings ARM: dts: iwg23s-sbc: Add pinctl support for scif1 ARM: dts: r8a77470: Add PFC support ARM: dts: r8a77470: Use r8a77470-sysc binding definitions ARM: dts: rcar: Correct SATA device sizes to 2 MiB Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat
-rw-r--r--arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts12
-rw-r--r--arch/arm/boot/dts/r8a77470.dtsi123
-rw-r--r--arch/arm/boot/dts/r8a7778.dtsi2
-rw-r--r--arch/arm/boot/dts/r8a7779.dtsi4
-rw-r--r--arch/arm/boot/dts/r8a7790-stout.dts4
-rw-r--r--arch/arm/boot/dts/r8a7790.dtsi4
-rw-r--r--arch/arm/boot/dts/r8a7791.dtsi4
-rw-r--r--arch/arm/boot/dts/r8a7792.dtsi1
-rw-r--r--arch/arm/boot/dts/r8a7793-gose.dts16
-rw-r--r--arch/arm/boot/dts/r8a7794-silk.dts25
-rw-r--r--arch/arm/boot/dts/r8a7794.dtsi1
-rw-r--r--arch/arm/boot/dts/r9a06g032.dtsi7
12 files changed, 178 insertions, 25 deletions
diff --git a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
index e3585daafdd6..22da819f186b 100644
--- a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
+++ b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
@@ -35,6 +35,8 @@
35 35
36 phy3: ethernet-phy@3 { 36 phy3: ethernet-phy@3 {
37 reg = <3>; 37 reg = <3>;
38 interrupt-parent = <&gpio5>;
39 interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
38 micrel,led-mode = <1>; 40 micrel,led-mode = <1>;
39 }; 41 };
40}; 42};
@@ -43,6 +45,16 @@
43 clock-frequency = <20000000>; 45 clock-frequency = <20000000>;
44}; 46};
45 47
48&pfc {
49 scif1_pins: scif1 {
50 groups = "scif1_data_b";
51 function = "scif1";
52 };
53};
54
46&scif1 { 55&scif1 {
56 pinctrl-0 = <&scif1_pins>;
57 pinctrl-names = "default";
58
47 status = "okay"; 59 status = "okay";
48}; 60};
diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi
index 87d32d3e23de..c053a28cd132 100644
--- a/arch/arm/boot/dts/r8a77470.dtsi
+++ b/arch/arm/boot/dts/r8a77470.dtsi
@@ -8,6 +8,7 @@
8#include <dt-bindings/interrupt-controller/irq.h> 8#include <dt-bindings/interrupt-controller/irq.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/clock/r8a77470-cpg-mssr.h> 10#include <dt-bindings/clock/r8a77470-cpg-mssr.h>
11#include <dt-bindings/power/r8a77470-sysc.h>
11/ { 12/ {
12 compatible = "renesas,r8a77470"; 13 compatible = "renesas,r8a77470";
13 #address-cells = <2>; 14 #address-cells = <2>;
@@ -23,7 +24,7 @@
23 reg = <0>; 24 reg = <0>;
24 clock-frequency = <1000000000>; 25 clock-frequency = <1000000000>;
25 clocks = <&cpg CPG_CORE R8A77470_CLK_Z2>; 26 clocks = <&cpg CPG_CORE R8A77470_CLK_Z2>;
26 power-domains = <&sysc 5>; 27 power-domains = <&sysc R8A77470_PD_CA7_CPU0>;
27 next-level-cache = <&L2_CA7>; 28 next-level-cache = <&L2_CA7>;
28 }; 29 };
29 30
@@ -32,7 +33,7 @@
32 compatible = "cache"; 33 compatible = "cache";
33 cache-unified; 34 cache-unified;
34 cache-level = <2>; 35 cache-level = <2>;
35 power-domains = <&sysc 21>; 36 power-domains = <&sysc R8A77470_PD_CA7_SCU>;
36 }; 37 };
37 }; 38 };
38 39
@@ -60,6 +61,102 @@
60 #size-cells = <2>; 61 #size-cells = <2>;
61 ranges; 62 ranges;
62 63
64 gpio0: gpio@e6050000 {
65 compatible = "renesas,gpio-r8a77470",
66 "renesas,rcar-gen2-gpio";
67 reg = <0 0xe6050000 0 0x50>;
68 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
69 #gpio-cells = <2>;
70 gpio-controller;
71 gpio-ranges = <&pfc 0 0 23>;
72 #interrupt-cells = <2>;
73 interrupt-controller;
74 clocks = <&cpg CPG_MOD 912>;
75 power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
76 resets = <&cpg 912>;
77 };
78
79 gpio1: gpio@e6051000 {
80 compatible = "renesas,gpio-r8a77470",
81 "renesas,rcar-gen2-gpio";
82 reg = <0 0xe6051000 0 0x50>;
83 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
84 #gpio-cells = <2>;
85 gpio-controller;
86 gpio-ranges = <&pfc 0 32 23>;
87 #interrupt-cells = <2>;
88 interrupt-controller;
89 clocks = <&cpg CPG_MOD 911>;
90 power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
91 resets = <&cpg 911>;
92 };
93
94 gpio2: gpio@e6052000 {
95 compatible = "renesas,gpio-r8a77470",
96 "renesas,rcar-gen2-gpio";
97 reg = <0 0xe6052000 0 0x50>;
98 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
99 #gpio-cells = <2>;
100 gpio-controller;
101 gpio-ranges = <&pfc 0 64 32>;
102 #interrupt-cells = <2>;
103 interrupt-controller;
104 clocks = <&cpg CPG_MOD 910>;
105 power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
106 resets = <&cpg 910>;
107 };
108
109 gpio3: gpio@e6053000 {
110 compatible = "renesas,gpio-r8a77470",
111 "renesas,rcar-gen2-gpio";
112 reg = <0 0xe6053000 0 0x50>;
113 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
114 #gpio-cells = <2>;
115 gpio-controller;
116 gpio-ranges = <&pfc 0 96 30>;
117 gpio-reserved-ranges = <17 10>;
118 #interrupt-cells = <2>;
119 interrupt-controller;
120 clocks = <&cpg CPG_MOD 909>;
121 power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
122 resets = <&cpg 909>;
123 };
124
125 gpio4: gpio@e6054000 {
126 compatible = "renesas,gpio-r8a77470",
127 "renesas,rcar-gen2-gpio";
128 reg = <0 0xe6054000 0 0x50>;
129 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
130 #gpio-cells = <2>;
131 gpio-controller;
132 gpio-ranges = <&pfc 0 128 26>;
133 #interrupt-cells = <2>;
134 interrupt-controller;
135 clocks = <&cpg CPG_MOD 908>;
136 power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
137 resets = <&cpg 908>;
138 };
139
140 gpio5: gpio@e6055000 {
141 compatible = "renesas,gpio-r8a77470",
142 "renesas,rcar-gen2-gpio";
143 reg = <0 0xe6055000 0 0x50>;
144 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
145 #gpio-cells = <2>;
146 gpio-controller;
147 gpio-ranges = <&pfc 0 160 32>;
148 #interrupt-cells = <2>;
149 interrupt-controller;
150 clocks = <&cpg CPG_MOD 907>;
151 power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
152 resets = <&cpg 907>;
153 };
154
155 pfc: pin-controller@e6060000 {
156 compatible = "renesas,pfc-r8a77470";
157 reg = <0 0xe6060000 0 0x118>;
158 };
159
63 cpg: clock-controller@e6150000 { 160 cpg: clock-controller@e6150000 {
64 compatible = "renesas,r8a77470-cpg-mssr"; 161 compatible = "renesas,r8a77470-cpg-mssr";
65 reg = <0 0xe6150000 0 0x1000>; 162 reg = <0 0xe6150000 0 0x1000>;
@@ -97,7 +194,7 @@
97 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 194 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
98 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 195 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
99 clocks = <&cpg CPG_MOD 407>; 196 clocks = <&cpg CPG_MOD 407>;
100 power-domains = <&sysc 32>; 197 power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
101 resets = <&cpg 407>; 198 resets = <&cpg 407>;
102 }; 199 };
103 200
@@ -151,7 +248,7 @@
151 "ch12", "ch13", "ch14"; 248 "ch12", "ch13", "ch14";
152 clocks = <&cpg CPG_MOD 219>; 249 clocks = <&cpg CPG_MOD 219>;
153 clock-names = "fck"; 250 clock-names = "fck";
154 power-domains = <&sysc 32>; 251 power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
155 resets = <&cpg 219>; 252 resets = <&cpg 219>;
156 #dma-cells = <1>; 253 #dma-cells = <1>;
157 dma-channels = <15>; 254 dma-channels = <15>;
@@ -184,7 +281,7 @@
184 "ch12", "ch13", "ch14"; 281 "ch12", "ch13", "ch14";
185 clocks = <&cpg CPG_MOD 218>; 282 clocks = <&cpg CPG_MOD 218>;
186 clock-names = "fck"; 283 clock-names = "fck";
187 power-domains = <&sysc 32>; 284 power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
188 resets = <&cpg 218>; 285 resets = <&cpg 218>;
189 #dma-cells = <1>; 286 #dma-cells = <1>;
190 dma-channels = <15>; 287 dma-channels = <15>;
@@ -196,7 +293,7 @@
196 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; 293 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
197 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 294 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
198 clocks = <&cpg CPG_MOD 812>; 295 clocks = <&cpg CPG_MOD 812>;
199 power-domains = <&sysc 32>; 296 power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
200 resets = <&cpg 812>; 297 resets = <&cpg 812>;
201 #address-cells = <1>; 298 #address-cells = <1>;
202 #size-cells = <0>; 299 #size-cells = <0>;
@@ -214,7 +311,7 @@
214 dmas = <&dmac0 0x29>, <&dmac0 0x2a>, 311 dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
215 <&dmac1 0x29>, <&dmac1 0x2a>; 312 <&dmac1 0x29>, <&dmac1 0x2a>;
216 dma-names = "tx", "rx", "tx", "rx"; 313 dma-names = "tx", "rx", "tx", "rx";
217 power-domains = <&sysc 32>; 314 power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
218 resets = <&cpg 721>; 315 resets = <&cpg 721>;
219 status = "disabled"; 316 status = "disabled";
220 }; 317 };
@@ -230,7 +327,7 @@
230 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, 327 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
231 <&dmac1 0x2d>, <&dmac1 0x2e>; 328 <&dmac1 0x2d>, <&dmac1 0x2e>;
232 dma-names = "tx", "rx", "tx", "rx"; 329 dma-names = "tx", "rx", "tx", "rx";
233 power-domains = <&sysc 32>; 330 power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
234 resets = <&cpg 720>; 331 resets = <&cpg 720>;
235 status = "disabled"; 332 status = "disabled";
236 }; 333 };
@@ -246,7 +343,7 @@
246 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, 343 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
247 <&dmac1 0x2b>, <&dmac1 0x2c>; 344 <&dmac1 0x2b>, <&dmac1 0x2c>;
248 dma-names = "tx", "rx", "tx", "rx"; 345 dma-names = "tx", "rx", "tx", "rx";
249 power-domains = <&sysc 32>; 346 power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
250 resets = <&cpg 719>; 347 resets = <&cpg 719>;
251 status = "disabled"; 348 status = "disabled";
252 }; 349 };
@@ -262,7 +359,7 @@
262 dmas = <&dmac0 0x2f>, <&dmac0 0x30>, 359 dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
263 <&dmac1 0x2f>, <&dmac1 0x30>; 360 <&dmac1 0x2f>, <&dmac1 0x30>;
264 dma-names = "tx", "rx", "tx", "rx"; 361 dma-names = "tx", "rx", "tx", "rx";
265 power-domains = <&sysc 32>; 362 power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
266 resets = <&cpg 718>; 363 resets = <&cpg 718>;
267 status = "disabled"; 364 status = "disabled";
268 }; 365 };
@@ -278,7 +375,7 @@
278 dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, 375 dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
279 <&dmac1 0xfb>, <&dmac1 0xfc>; 376 <&dmac1 0xfb>, <&dmac1 0xfc>;
280 dma-names = "tx", "rx", "tx", "rx"; 377 dma-names = "tx", "rx", "tx", "rx";
281 power-domains = <&sysc 32>; 378 power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
282 resets = <&cpg 715>; 379 resets = <&cpg 715>;
283 status = "disabled"; 380 status = "disabled";
284 }; 381 };
@@ -294,7 +391,7 @@
294 dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, 391 dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
295 <&dmac1 0xfd>, <&dmac1 0xfe>; 392 <&dmac1 0xfd>, <&dmac1 0xfe>;
296 dma-names = "tx", "rx", "tx", "rx"; 393 dma-names = "tx", "rx", "tx", "rx";
297 power-domains = <&sysc 32>; 394 power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
298 resets = <&cpg 714>; 395 resets = <&cpg 714>;
299 status = "disabled"; 396 status = "disabled";
300 }; 397 };
@@ -309,7 +406,7 @@
309 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 406 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
310 clocks = <&cpg CPG_MOD 408>; 407 clocks = <&cpg CPG_MOD 408>;
311 clock-names = "clk"; 408 clock-names = "clk";
312 power-domains = <&sysc 32>; 409 power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
313 resets = <&cpg 408>; 410 resets = <&cpg 408>;
314 }; 411 };
315 412
diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi
index 1bce16cc6b20..05db0ccad7a6 100644
--- a/arch/arm/boot/dts/r8a7778.dtsi
+++ b/arch/arm/boot/dts/r8a7778.dtsi
@@ -1,6 +1,6 @@
1// SPDX-License-Identifier: GPL-2.0 1// SPDX-License-Identifier: GPL-2.0
2/* 2/*
3 * Device Tree Source for Renesas r8a7778 3 * Device Tree Source for the R-Car M1A (R8A77781) SoC
4 * 4 *
5 * Copyright (C) 2013 Renesas Solutions Corp. 5 * Copyright (C) 2013 Renesas Solutions Corp.
6 * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> 6 * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
index 6b997bc016ee..3bc133d9489c 100644
--- a/arch/arm/boot/dts/r8a7779.dtsi
+++ b/arch/arm/boot/dts/r8a7779.dtsi
@@ -1,6 +1,6 @@
1// SPDX-License-Identifier: GPL-2.0 1// SPDX-License-Identifier: GPL-2.0
2/* 2/*
3 * Device Tree Source for Renesas r8a7779 3 * Device Tree Source for the R-Car H1 (R8A77790) SoC
4 * 4 *
5 * Copyright (C) 2013 Renesas Solutions Corp. 5 * Copyright (C) 2013 Renesas Solutions Corp.
6 * Copyright (C) 2013 Simon Horman 6 * Copyright (C) 2013 Simon Horman
@@ -344,7 +344,7 @@
344 344
345 sata: sata@fc600000 { 345 sata: sata@fc600000 {
346 compatible = "renesas,sata-r8a7779", "renesas,rcar-sata"; 346 compatible = "renesas,sata-r8a7779", "renesas,rcar-sata";
347 reg = <0xfc600000 0x2000>; 347 reg = <0xfc600000 0x200000>;
348 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 348 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
349 clocks = <&mstp1_clks R8A7779_CLK_SATA>; 349 clocks = <&mstp1_clks R8A7779_CLK_SATA>;
350 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; 350 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
diff --git a/arch/arm/boot/dts/r8a7790-stout.dts b/arch/arm/boot/dts/r8a7790-stout.dts
index a13a92c26645..629da4cee1b9 100644
--- a/arch/arm/boot/dts/r8a7790-stout.dts
+++ b/arch/arm/boot/dts/r8a7790-stout.dts
@@ -318,6 +318,10 @@
318 interrupts = <2 IRQ_TYPE_LEVEL_LOW>; 318 interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
319 interrupt-controller; 319 interrupt-controller;
320 320
321 onkey {
322 compatible = "dlg,da9063-onkey";
323 };
324
321 rtc { 325 rtc {
322 compatible = "dlg,da9063-rtc"; 326 compatible = "dlg,da9063-rtc";
323 }; 327 };
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index 0925bdca438f..52a757f47bf0 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -1559,7 +1559,7 @@
1559 sata0: sata@ee300000 { 1559 sata0: sata@ee300000 {
1560 compatible = "renesas,sata-r8a7790", 1560 compatible = "renesas,sata-r8a7790",
1561 "renesas,rcar-gen2-sata"; 1561 "renesas,rcar-gen2-sata";
1562 reg = <0 0xee300000 0 0x2000>; 1562 reg = <0 0xee300000 0 0x200000>;
1563 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 1563 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
1564 clocks = <&cpg CPG_MOD 815>; 1564 clocks = <&cpg CPG_MOD 815>;
1565 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; 1565 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
@@ -1570,7 +1570,7 @@
1570 sata1: sata@ee500000 { 1570 sata1: sata@ee500000 {
1571 compatible = "renesas,sata-r8a7790", 1571 compatible = "renesas,sata-r8a7790",
1572 "renesas,rcar-gen2-sata"; 1572 "renesas,rcar-gen2-sata";
1573 reg = <0 0xee500000 0 0x2000>; 1573 reg = <0 0xee500000 0 0x200000>;
1574 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 1574 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
1575 clocks = <&cpg CPG_MOD 814>; 1575 clocks = <&cpg CPG_MOD 814>;
1576 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; 1576 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index 991ac6feedd5..25b6a99dd87a 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -1543,7 +1543,7 @@
1543 sata0: sata@ee300000 { 1543 sata0: sata@ee300000 {
1544 compatible = "renesas,sata-r8a7791", 1544 compatible = "renesas,sata-r8a7791",
1545 "renesas,rcar-gen2-sata"; 1545 "renesas,rcar-gen2-sata";
1546 reg = <0 0xee300000 0 0x2000>; 1546 reg = <0 0xee300000 0 0x200000>;
1547 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 1547 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
1548 clocks = <&cpg CPG_MOD 815>; 1548 clocks = <&cpg CPG_MOD 815>;
1549 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; 1549 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
@@ -1554,7 +1554,7 @@
1554 sata1: sata@ee500000 { 1554 sata1: sata@ee500000 {
1555 compatible = "renesas,sata-r8a7791", 1555 compatible = "renesas,sata-r8a7791",
1556 "renesas,rcar-gen2-sata"; 1556 "renesas,rcar-gen2-sata";
1557 reg = <0 0xee500000 0 0x2000>; 1557 reg = <0 0xee500000 0 0x200000>;
1558 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 1558 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
1559 clocks = <&cpg CPG_MOD 814>; 1559 clocks = <&cpg CPG_MOD 814>;
1560 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; 1560 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi
index 63a978ec81cc..52d16a260db0 100644
--- a/arch/arm/boot/dts/r8a7792.dtsi
+++ b/arch/arm/boot/dts/r8a7792.dtsi
@@ -829,7 +829,6 @@
829 du: display@feb00000 { 829 du: display@feb00000 {
830 compatible = "renesas,du-r8a7792"; 830 compatible = "renesas,du-r8a7792";
831 reg = <0 0xfeb00000 0 0x40000>; 831 reg = <0 0xfeb00000 0 0x40000>;
832 reg-names = "du";
833 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 832 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
834 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; 833 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
835 clocks = <&cpg CPG_MOD 724>, 834 clocks = <&cpg CPG_MOD 724>,
diff --git a/arch/arm/boot/dts/r8a7793-gose.dts b/arch/arm/boot/dts/r8a7793-gose.dts
index 6b2f3a4fd13d..f51601af89a2 100644
--- a/arch/arm/boot/dts/r8a7793-gose.dts
+++ b/arch/arm/boot/dts/r8a7793-gose.dts
@@ -596,6 +596,10 @@
596 status = "okay"; 596 status = "okay";
597}; 597};
598 598
599&cpu0 {
600 cpu0-supply = <&vdd_dvfs>;
601};
602
599&rwdt { 603&rwdt {
600 timeout-sec = <60>; 604 timeout-sec = <60>;
601 status = "okay"; 605 status = "okay";
@@ -725,6 +729,18 @@
725 compatible = "dlg,da9063-watchdog"; 729 compatible = "dlg,da9063-watchdog";
726 }; 730 };
727 }; 731 };
732
733 vdd_dvfs: regulator@68 {
734 compatible = "dlg,da9210";
735 reg = <0x68>;
736 interrupt-parent = <&irqc0>;
737 interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
738
739 regulator-min-microvolt = <1000000>;
740 regulator-max-microvolt = <1000000>;
741 regulator-boot-on;
742 regulator-always-on;
743 };
728}; 744};
729 745
730&i2c4 { 746&i2c4 {
diff --git a/arch/arm/boot/dts/r8a7794-silk.dts b/arch/arm/boot/dts/r8a7794-silk.dts
index daec965889d3..60e91ebfa65d 100644
--- a/arch/arm/boot/dts/r8a7794-silk.dts
+++ b/arch/arm/boot/dts/r8a7794-silk.dts
@@ -405,6 +405,31 @@
405 clock-frequency = <400000>; 405 clock-frequency = <400000>;
406}; 406};
407 407
408&i2c7 {
409 status = "okay";
410 clock-frequency = <100000>;
411
412 pmic@58 {
413 compatible = "dlg,da9063";
414 reg = <0x58>;
415 interrupt-parent = <&gpio3>;
416 interrupts = <31 IRQ_TYPE_LEVEL_LOW>;
417 interrupt-controller;
418
419 onkey {
420 compatible = "dlg,da9063-onkey";
421 };
422
423 rtc {
424 compatible = "dlg,da9063-rtc";
425 };
426
427 wdt {
428 compatible = "dlg,da9063-watchdog";
429 };
430 };
431};
432
408&mmcif0 { 433&mmcif0 {
409 pinctrl-0 = <&mmcif0_pins>; 434 pinctrl-0 = <&mmcif0_pins>;
410 pinctrl-names = "default"; 435 pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
index ea2ca4bdaf1c..886135a273cb 100644
--- a/arch/arm/boot/dts/r8a7794.dtsi
+++ b/arch/arm/boot/dts/r8a7794.dtsi
@@ -1349,7 +1349,6 @@
1349 du: display@feb00000 { 1349 du: display@feb00000 {
1350 compatible = "renesas,du-r8a7794"; 1350 compatible = "renesas,du-r8a7794";
1351 reg = <0 0xfeb00000 0 0x40000>; 1351 reg = <0 0xfeb00000 0 0x40000>;
1352 reg-names = "du";
1353 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 1352 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
1354 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; 1353 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
1355 clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; 1354 clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi
index afe29c95a006..3e45375b79aa 100644
--- a/arch/arm/boot/dts/r9a06g032.dtsi
+++ b/arch/arm/boot/dts/r9a06g032.dtsi
@@ -7,6 +7,7 @@
7 */ 7 */
8 8
9#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/clock/r9a06g032-sysctrl.h>
10 11
11/ { 12/ {
12 compatible = "renesas,r9a06g032"; 13 compatible = "renesas,r9a06g032";
@@ -21,14 +22,14 @@
21 device_type = "cpu"; 22 device_type = "cpu";
22 compatible = "arm,cortex-a7"; 23 compatible = "arm,cortex-a7";
23 reg = <0>; 24 reg = <0>;
24 clocks = <&sysctrl 84>; 25 clocks = <&sysctrl R9A06G032_CLK_A7MP>;
25 }; 26 };
26 27
27 cpu@1 { 28 cpu@1 {
28 device_type = "cpu"; 29 device_type = "cpu";
29 compatible = "arm,cortex-a7"; 30 compatible = "arm,cortex-a7";
30 reg = <1>; 31 reg = <1>;
31 clocks = <&sysctrl 84>; 32 clocks = <&sysctrl R9A06G032_CLK_A7MP>;
32 enable-method = "renesas,r9a06g032-smp"; 33 enable-method = "renesas,r9a06g032-smp";
33 cpu-release-addr = <0 0x4000c204>; 34 cpu-release-addr = <0 0x4000c204>;
34 }; 35 };
@@ -82,7 +83,7 @@
82 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 83 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
83 reg-shift = <2>; 84 reg-shift = <2>;
84 reg-io-width = <4>; 85 reg-io-width = <4>;
85 clocks = <&sysctrl 146>; 86 clocks = <&sysctrl R9A06G032_CLK_UART0>;
86 clock-names = "baudclk"; 87 clock-names = "baudclk";
87 status = "disabled"; 88 status = "disabled";
88 }; 89 };
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-16 21:44:11 -0400