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authorLinus Torvalds <torvalds@linux-foundation.org>2018-06-11 21:19:45 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2018-06-11 21:19:45 -0400
commit8efcf34a263965e471e3999904f94d1f6799d42a (patch)
treea1fe88517cb8a4eb54b50c3ce32eaa1954518b9c
parent32bcbf8b6d09428907fd045a4ea90562ec7dc4a2 (diff)
parent14321604c82c5415a72e894b83b587a345f5bdf2 (diff)
Merge tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC late updates from Olof Johansson: "This is a branch with a few merge requests that either came in late, or took a while longer for us to review and merge than usual and thus cut it a bit close to the merge window. We stage them in a separate branch and if things look good, we still send them up -- and that's the case here. This is mostly DT additions for Renesas platforms, adding IP block descriptions for existing and new SoCs. There are also some driver updates for Qualcomm platforms for SMEM/QMI and GENI, which is their generalized serial protocol interface" * tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (186 commits) soc: qcom: smem: introduce qcom_smem_virt_to_phys() soc: qcom: qmi: fix a buffer sizing bug MAINTAINERS: Update pattern for qcom_scm soc: Unconditionally include qcom Makefile soc: qcom: smem: check sooner in qcom_smem_set_global_partition() soc: qcom: smem: fix qcom_smem_set_global_partition() soc: qcom: smem: fix off-by-one error in qcom_smem_alloc_private() soc: qcom: smem: byte swap values properly soc: qcom: smem: return proper type for cached entry functions soc: qcom: smem: fix first cache entry calculation soc: qcom: cmd-db: Make endian-agnostic drivers: qcom: add command DB driver arm64: dts: renesas: salvator-common: Add ADV7482 support ARM: dts: r8a7740: Add CEU1 ARM: dts: r8a7740: Add CEU0 arm64: dts: renesas: salvator-common: enable VIN arm64: dts: renesas: r8a77970: add VIN and CSI-2 nodes arm64: dts: renesas: r8a77965: add VIN and CSI-2 nodes arm64: dts: renesas: r8a7796: add VIN and CSI-2 nodes arm64: dts: renesas: r8a7795-es1: add CSI-2 node ...
Diffstat
-rw-r--r--Documentation/devicetree/bindings/firmware/qcom,scm.txt3
-rw-r--r--Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.txt1
-rw-r--r--MAINTAINERS2
-rw-r--r--arch/arm/boot/dts/Makefile1
-rw-r--r--arch/arm/boot/dts/emev2-kzm9d.dts3
-rw-r--r--arch/arm/boot/dts/emev2.dtsi5
-rw-r--r--arch/arm/boot/dts/r7s72100.dtsi1038
-rw-r--r--arch/arm/boot/dts/r8a73a4-ape6evm.dts4
-rw-r--r--arch/arm/boot/dts/r8a73a4.dtsi10
-rw-r--r--arch/arm/boot/dts/r8a7740.dtsi18
-rw-r--r--arch/arm/boot/dts/r8a7743-iwg20m.dtsi5
-rw-r--r--arch/arm/boot/dts/r8a7743.dtsi19
-rw-r--r--arch/arm/boot/dts/r8a7745-iwg22m.dtsi5
-rw-r--r--arch/arm/boot/dts/r8a7745.dtsi19
-rw-r--r--arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts48
-rw-r--r--arch/arm/boot/dts/r8a77470.dtsi336
-rw-r--r--arch/arm/boot/dts/r8a7790-lager.dts8
-rw-r--r--arch/arm/boot/dts/r8a7790.dtsi67
-rw-r--r--arch/arm/boot/dts/r8a7791-koelsch.dts11
-rw-r--r--arch/arm/boot/dts/r8a7791-porter.dts8
-rw-r--r--arch/arm/boot/dts/r8a7791.dtsi37
-rw-r--r--arch/arm/boot/dts/r8a7792-blanche.dts5
-rw-r--r--arch/arm/boot/dts/r8a7792-wheat.dts16
-rw-r--r--arch/arm/boot/dts/r8a7792.dtsi19
-rw-r--r--arch/arm/boot/dts/r8a7793-gose.dts11
-rw-r--r--arch/arm/boot/dts/r8a7793.dtsi37
-rw-r--r--arch/arm/boot/dts/r8a7794-alt.dts14
-rw-r--r--arch/arm/boot/dts/r8a7794-silk.dts8
-rw-r--r--arch/arm/boot/dts/r8a7794.dtsi28
-rw-r--r--arch/arm/boot/dts/sh73a0.dtsi9
-rw-r--r--arch/arm64/Kconfig.platforms6
-rw-r--r--arch/arm64/boot/dts/renesas/Makefile3
-rw-r--r--arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts46
-rw-r--r--arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi144
-rw-r--r--arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts46
-rw-r--r--arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts85
-rw-r--r--arch/arm64/boot/dts/renesas/r8a7795.dtsi2345
-rw-r--r--arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts28
-rw-r--r--arch/arm64/boot/dts/renesas/r8a7796-salvator-xs.dts28
-rw-r--r--arch/arm64/boot/dts/renesas/r8a7796.dtsi2211
-rw-r--r--arch/arm64/boot/dts/renesas/r8a77965-salvator-x.dts28
-rw-r--r--arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts28
-rw-r--r--arch/arm64/boot/dts/renesas/r8a77965.dtsi1465
-rw-r--r--arch/arm64/boot/dts/renesas/r8a77970-eagle.dts116
-rw-r--r--arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts137
-rw-r--r--arch/arm64/boot/dts/renesas/r8a77970.dtsi661
-rw-r--r--arch/arm64/boot/dts/renesas/r8a77980-condor.dts81
-rw-r--r--arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts60
-rw-r--r--arch/arm64/boot/dts/renesas/r8a77980.dtsi99
-rw-r--r--arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts65
-rw-r--r--arch/arm64/boot/dts/renesas/r8a77990.dtsi281
-rw-r--r--arch/arm64/boot/dts/renesas/r8a77995-draak.dts2
-rw-r--r--arch/arm64/boot/dts/renesas/r8a77995.dtsi722
-rw-r--r--arch/arm64/boot/dts/renesas/salvator-common.dtsi187
-rw-r--r--arch/arm64/boot/dts/renesas/ulcb.dtsi37
-rw-r--r--drivers/firmware/qcom_scm.c3
-rw-r--r--drivers/of/platform.c1
-rw-r--r--drivers/soc/Makefile2
-rw-r--r--drivers/soc/qcom/Kconfig18
-rw-r--r--drivers/soc/qcom/Makefile2
-rw-r--r--drivers/soc/qcom/cmd-db.c317
-rw-r--r--drivers/soc/qcom/qcom-geni-se.c748
-rw-r--r--drivers/soc/qcom/qmi_interface.c5
-rw-r--r--drivers/soc/qcom/smd-rpm.c1
-rw-r--r--drivers/soc/qcom/smem.c77
-rw-r--r--include/linux/qcom-geni-se.h425
-rw-r--r--include/linux/soc/qcom/smem.h2
-rw-r--r--include/soc/qcom/cmd-db.h45
68 files changed, 8943 insertions, 3409 deletions
diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.txt b/Documentation/devicetree/bindings/firmware/qcom,scm.txt
index 7b40054be0d8..fcf6979c0b6d 100644
--- a/Documentation/devicetree/bindings/firmware/qcom,scm.txt
+++ b/Documentation/devicetree/bindings/firmware/qcom,scm.txt
@@ -11,9 +11,10 @@ Required properties:
11 * "qcom,scm-msm8660" for MSM8660 platforms 11 * "qcom,scm-msm8660" for MSM8660 platforms
12 * "qcom,scm-msm8690" for MSM8690 platforms 12 * "qcom,scm-msm8690" for MSM8690 platforms
13 * "qcom,scm-msm8996" for MSM8996 platforms 13 * "qcom,scm-msm8996" for MSM8996 platforms
14 * "qcom,scm-ipq4019" for IPQ4019 platforms
14 * "qcom,scm" for later processors (MSM8916, APQ8084, MSM8974, etc) 15 * "qcom,scm" for later processors (MSM8916, APQ8084, MSM8974, etc)
15- clocks: One to three clocks may be required based on compatible. 16- clocks: One to three clocks may be required based on compatible.
16 * No clock required for "qcom,scm-msm8996" 17 * No clock required for "qcom,scm-msm8996", "qcom,scm-ipq4019"
17 * Only core clock required for "qcom,scm-apq8064", "qcom,scm-msm8660", and "qcom,scm-msm8960" 18 * Only core clock required for "qcom,scm-apq8064", "qcom,scm-msm8660", and "qcom,scm-msm8960"
18 * Core, iface, and bus clocks required for "qcom,scm" 19 * Core, iface, and bus clocks required for "qcom,scm"
19- clock-names: Must contain "core" for the core clock, "iface" for the interface 20- clock-names: Must contain "core" for the core clock, "iface" for the interface
diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.txt
index a48049ccf6d0..89e1cb9212f6 100644
--- a/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.txt
+++ b/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.txt
@@ -22,6 +22,7 @@ resources.
22 "qcom,rpm-apq8084" 22 "qcom,rpm-apq8084"
23 "qcom,rpm-msm8916" 23 "qcom,rpm-msm8916"
24 "qcom,rpm-msm8974" 24 "qcom,rpm-msm8974"
25 "qcom,rpm-msm8998"
25 26
26- qcom,smd-channels: 27- qcom,smd-channels:
27 Usage: required 28 Usage: required
diff --git a/MAINTAINERS b/MAINTAINERS
index 0ee6fe90a52b..12b27679ae0c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1830,7 +1830,7 @@ F: drivers/spi/spi-qup.c
1830F: drivers/tty/serial/msm_serial.c 1830F: drivers/tty/serial/msm_serial.c
1831F: drivers/*/pm8???-* 1831F: drivers/*/pm8???-*
1832F: drivers/mfd/ssbi.c 1832F: drivers/mfd/ssbi.c
1833F: drivers/firmware/qcom_scm.c 1833F: drivers/firmware/qcom_scm*
1834T: git git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux.git 1834T: git git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux.git
1835 1835
1836ARM/RADISYS ENP2611 MACHINE SUPPORT 1836ARM/RADISYS ENP2611 MACHINE SUPPORT
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 19124f0efe60..37a3de760d40 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -807,6 +807,7 @@ dtb-$(CONFIG_ARCH_RENESAS) += \
807 r8a7745-iwg22d-sodimm.dtb \ 807 r8a7745-iwg22d-sodimm.dtb \
808 r8a7745-iwg22d-sodimm-dbhd-ca.dtb \ 808 r8a7745-iwg22d-sodimm-dbhd-ca.dtb \
809 r8a7745-sk-rzg1e.dtb \ 809 r8a7745-sk-rzg1e.dtb \
810 r8a77470-iwg23s-sbc.dtb \
810 r8a7778-bockw.dtb \ 811 r8a7778-bockw.dtb \
811 r8a7779-marzen.dtb \ 812 r8a7779-marzen.dtb \
812 r8a7790-lager.dtb \ 813 r8a7790-lager.dtb \
diff --git a/arch/arm/boot/dts/emev2-kzm9d.dts b/arch/arm/boot/dts/emev2-kzm9d.dts
index c238407133bf..0af44b7eadb9 100644
--- a/arch/arm/boot/dts/emev2-kzm9d.dts
+++ b/arch/arm/boot/dts/emev2-kzm9d.dts
@@ -34,9 +34,6 @@
34 34
35 gpio_keys { 35 gpio_keys {
36 compatible = "gpio-keys"; 36 compatible = "gpio-keys";
37 #address-cells = <1>;
38 #size-cells = <0>;
39
40 one { 37 one {
41 debounce-interval = <50>; 38 debounce-interval = <50>;
42 wakeup-source; 39 wakeup-source;
diff --git a/arch/arm/boot/dts/emev2.dtsi b/arch/arm/boot/dts/emev2.dtsi
index 42ea246e71cb..fec1241b858f 100644
--- a/arch/arm/boot/dts/emev2.dtsi
+++ b/arch/arm/boot/dts/emev2.dtsi
@@ -31,13 +31,13 @@
31 #address-cells = <1>; 31 #address-cells = <1>;
32 #size-cells = <0>; 32 #size-cells = <0>;
33 33
34 cpu@0 { 34 cpu0: cpu@0 {
35 device_type = "cpu"; 35 device_type = "cpu";
36 compatible = "arm,cortex-a9"; 36 compatible = "arm,cortex-a9";
37 reg = <0>; 37 reg = <0>;
38 clock-frequency = <533000000>; 38 clock-frequency = <533000000>;
39 }; 39 };
40 cpu@1 { 40 cpu1: cpu@1 {
41 device_type = "cpu"; 41 device_type = "cpu";
42 compatible = "arm,cortex-a9"; 42 compatible = "arm,cortex-a9";
43 reg = <1>; 43 reg = <1>;
@@ -57,6 +57,7 @@
57 compatible = "arm,cortex-a9-pmu"; 57 compatible = "arm,cortex-a9-pmu";
58 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 58 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
59 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 59 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
60 interrupt-affinity = <&cpu0>, <&cpu1>;
60 }; 61 };
61 62
62 clocks@e0110000 { 63 clocks@e0110000 {
diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi
index ab9645a42eca..a54822e97bac 100644
--- a/arch/arm/boot/dts/r7s72100.dtsi
+++ b/arch/arm/boot/dts/r7s72100.dtsi
@@ -15,7 +15,6 @@
15 15
16/ { 16/ {
17 compatible = "renesas,r7s72100"; 17 compatible = "renesas,r7s72100";
18 interrupt-parent = <&gic>;
19 #address-cells = <1>; 18 #address-cells = <1>;
20 #size-cells = <1>; 19 #size-cells = <1>;
21 20
@@ -31,61 +30,370 @@
31 spi4 = &spi4; 30 spi4 = &spi4;
32 }; 31 };
33 32
34 clocks { 33 /* Fixed factor clocks */
35 ranges; 34 b_clk: b {
35 #clock-cells = <0>;
36 compatible = "fixed-factor-clock";
37 clocks = <&cpg_clocks R7S72100_CLK_PLL>;
38 clock-mult = <1>;
39 clock-div = <3>;
40 };
41
42 cpus {
43 #address-cells = <1>;
44 #size-cells = <0>;
45
46 cpu@0 {
47 device_type = "cpu";
48 compatible = "arm,cortex-a9";
49 reg = <0>;
50 clock-frequency = <400000000>;
51 clocks = <&cpg_clocks R7S72100_CLK_I>;
52 next-level-cache = <&L2>;
53 };
54 };
55
56 /* External clocks */
57 extal_clk: extal {
58 #clock-cells = <0>;
59 compatible = "fixed-clock";
60 /* If clk present, value must be set by board */
61 clock-frequency = <0>;
62 };
63
64 p0_clk: p0 {
65 #clock-cells = <0>;
66 compatible = "fixed-factor-clock";
67 clocks = <&cpg_clocks R7S72100_CLK_PLL>;
68 clock-mult = <1>;
69 clock-div = <12>;
70 };
71
72 p1_clk: p1 {
73 #clock-cells = <0>;
74 compatible = "fixed-factor-clock";
75 clocks = <&cpg_clocks R7S72100_CLK_PLL>;
76 clock-mult = <1>;
77 clock-div = <6>;
78 };
79
80 pmu {
81 compatible = "arm,cortex-a9-pmu";
82 interrupts-extended = <&gic GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>;
83 };
84
85 rtc_x1_clk: rtc_x1 {
86 #clock-cells = <0>;
87 compatible = "fixed-clock";
88 /* If clk present, value must be set by board to 32678 */
89 clock-frequency = <0>;
90 };
91
92 rtc_x3_clk: rtc_x3 {
93 #clock-cells = <0>;
94 compatible = "fixed-clock";
95 /* If clk present, value must be set by board to 4000000 */
96 clock-frequency = <0>;
97 };
98
99 soc {
100 compatible = "simple-bus";
101 interrupt-parent = <&gic>;
102
36 #address-cells = <1>; 103 #address-cells = <1>;
37 #size-cells = <1>; 104 #size-cells = <1>;
105 ranges;
106
107 L2: cache-controller@3ffff000 {
108 compatible = "arm,pl310-cache";
109 reg = <0x3ffff000 0x1000>;
110 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
111 arm,early-bresp-disable;
112 arm,full-line-zero-disable;
113 cache-unified;
114 cache-level = <2>;
115 };
116
117 scif0: serial@e8007000 {
118 compatible = "renesas,scif-r7s72100", "renesas,scif";
119 reg = <0xe8007000 64>;
120 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
121 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
122 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
123 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
124 clocks = <&mstp4_clks R7S72100_CLK_SCIF0>;
125 clock-names = "fck";
126 power-domains = <&cpg_clocks>;
127 status = "disabled";
128 };
129
130 scif1: serial@e8007800 {
131 compatible = "renesas,scif-r7s72100", "renesas,scif";
132 reg = <0xe8007800 64>;
133 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
134 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
135 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
136 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
137 clocks = <&mstp4_clks R7S72100_CLK_SCIF1>;
138 clock-names = "fck";
139 power-domains = <&cpg_clocks>;
140 status = "disabled";
141 };
142
143 scif2: serial@e8008000 {
144 compatible = "renesas,scif-r7s72100", "renesas,scif";
145 reg = <0xe8008000 64>;
146 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
147 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
148 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
149 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
150 clocks = <&mstp4_clks R7S72100_CLK_SCIF2>;
151 clock-names = "fck";
152 power-domains = <&cpg_clocks>;
153 status = "disabled";
154 };
155
156 scif3: serial@e8008800 {
157 compatible = "renesas,scif-r7s72100", "renesas,scif";
158 reg = <0xe8008800 64>;
159 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
160 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
161 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
162 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
163 clocks = <&mstp4_clks R7S72100_CLK_SCIF3>;
164 clock-names = "fck";
165 power-domains = <&cpg_clocks>;
166 status = "disabled";
167 };
38 168
39 /* External clocks */ 169 scif4: serial@e8009000 {
40 extal_clk: extal { 170 compatible = "renesas,scif-r7s72100", "renesas,scif";
41 #clock-cells = <0>; 171 reg = <0xe8009000 64>;
42 compatible = "fixed-clock"; 172 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
43 /* If clk present, value must be set by board */ 173 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
44 clock-frequency = <0>; 174 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
175 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
176 clocks = <&mstp4_clks R7S72100_CLK_SCIF4>;
177 clock-names = "fck";
178 power-domains = <&cpg_clocks>;
179 status = "disabled";
45 }; 180 };
46 181
47 usb_x1_clk: usb_x1 { 182 scif5: serial@e8009800 {
48 #clock-cells = <0>; 183 compatible = "renesas,scif-r7s72100", "renesas,scif";
49 compatible = "fixed-clock"; 184 reg = <0xe8009800 64>;
50 /* If clk present, value must be set by board */ 185 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
51 clock-frequency = <0>; 186 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
187 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
188 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
189 clocks = <&mstp4_clks R7S72100_CLK_SCIF5>;
190 clock-names = "fck";
191 power-domains = <&cpg_clocks>;
192 status = "disabled";
52 }; 193 };
53 194
54 rtc_x1_clk: rtc_x1 { 195 scif6: serial@e800a000 {
55 #clock-cells = <0>; 196 compatible = "renesas,scif-r7s72100", "renesas,scif";
56 compatible = "fixed-clock"; 197 reg = <0xe800a000 64>;
57 /* If clk present, value must be set by board to 32678 */ 198 interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
58 clock-frequency = <0>; 199 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
200 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
201 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
202 clocks = <&mstp4_clks R7S72100_CLK_SCIF6>;
203 clock-names = "fck";
204 power-domains = <&cpg_clocks>;
205 status = "disabled";
59 }; 206 };
60 207
61 rtc_x3_clk: rtc_x3 { 208 scif7: serial@e800a800 {
62 #clock-cells = <0>; 209 compatible = "renesas,scif-r7s72100", "renesas,scif";
63 compatible = "fixed-clock"; 210 reg = <0xe800a800 64>;
64 /* If clk present, value must be set by board to 4000000 */ 211 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
65 clock-frequency = <0>; 212 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
213 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
214 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
215 clocks = <&mstp4_clks R7S72100_CLK_SCIF7>;
216 clock-names = "fck";
217 power-domains = <&cpg_clocks>;
218 status = "disabled";
66 }; 219 };
67 220
68 /* Fixed factor clocks */ 221 spi0: spi@e800c800 {
69 b_clk: b { 222 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
70 #clock-cells = <0>; 223 reg = <0xe800c800 0x24>;
71 compatible = "fixed-factor-clock"; 224 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
72 clocks = <&cpg_clocks R7S72100_CLK_PLL>; 225 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
73 clock-mult = <1>; 226 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
74 clock-div = <3>; 227 interrupt-names = "error", "rx", "tx";
228 clocks = <&mstp10_clks R7S72100_CLK_SPI0>;
229 power-domains = <&cpg_clocks>;
230 num-cs = <1>;
231 #address-cells = <1>;
232 #size-cells = <0>;
233 status = "disabled";
75 }; 234 };
76 p1_clk: p1 { 235
77 #clock-cells = <0>; 236 spi1: spi@e800d000 {
78 compatible = "fixed-factor-clock"; 237 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
79 clocks = <&cpg_clocks R7S72100_CLK_PLL>; 238 reg = <0xe800d000 0x24>;
80 clock-mult = <1>; 239 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
81 clock-div = <6>; 240 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
241 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
242 interrupt-names = "error", "rx", "tx";
243 clocks = <&mstp10_clks R7S72100_CLK_SPI1>;
244 power-domains = <&cpg_clocks>;
245 num-cs = <1>;
246 #address-cells = <1>;
247 #size-cells = <0>;
248 status = "disabled";
249 };
250
251 spi2: spi@e800d800 {
252 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
253 reg = <0xe800d800 0x24>;
254 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
255 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
256 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
257 interrupt-names = "error", "rx", "tx";
258 clocks = <&mstp10_clks R7S72100_CLK_SPI2>;
259 power-domains = <&cpg_clocks>;
260 num-cs = <1>;
261 #address-cells = <1>;
262 #size-cells = <0>;
263 status = "disabled";
82 }; 264 };
83 p0_clk: p0 { 265
84 #clock-cells = <0>; 266 spi3: spi@e800e000 {
85 compatible = "fixed-factor-clock"; 267 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
86 clocks = <&cpg_clocks R7S72100_CLK_PLL>; 268 reg = <0xe800e000 0x24>;
87 clock-mult = <1>; 269 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
88 clock-div = <12>; 270 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
271 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
272 interrupt-names = "error", "rx", "tx";
273 clocks = <&mstp10_clks R7S72100_CLK_SPI3>;
274 power-domains = <&cpg_clocks>;
275 num-cs = <1>;
276 #address-cells = <1>;
277 #size-cells = <0>;
278 status = "disabled";
279 };
280
281 spi4: spi@e800e800 {
282 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
283 reg = <0xe800e800 0x24>;
284 interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
285 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
286 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
287 interrupt-names = "error", "rx", "tx";
288 clocks = <&mstp10_clks R7S72100_CLK_SPI4>;
289 power-domains = <&cpg_clocks>;
290 num-cs = <1>;
291 #address-cells = <1>;
292 #size-cells = <0>;
293 status = "disabled";
294 };
295
296 usbhs0: usb@e8010000 {
297 compatible = "renesas,usbhs-r7s72100", "renesas,rza1-usbhs";
298 reg = <0xe8010000 0x1a0>;
299 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
300 clocks = <&mstp7_clks R7S72100_CLK_USB0>;
301 renesas,buswait = <4>;
302 power-domains = <&cpg_clocks>;
303 status = "disabled";
304 };
305
306 usbhs1: usb@e8207000 {
307 compatible = "renesas,usbhs-r7s72100", "renesas,rza1-usbhs";
308 reg = <0xe8207000 0x1a0>;
309 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
310 clocks = <&mstp7_clks R7S72100_CLK_USB1>;
311 renesas,buswait = <4>;
312 power-domains = <&cpg_clocks>;
313 status = "disabled";
314 };
315
316 mmcif: mmc@e804c800 {
317 compatible = "renesas,mmcif-r7s72100", "renesas,sh-mmcif";
318 reg = <0xe804c800 0x80>;
319 interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH
320 GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH
321 GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
322 clocks = <&mstp8_clks R7S72100_CLK_MMCIF>;
323 power-domains = <&cpg_clocks>;
324 reg-io-width = <4>;
325 bus-width = <8>;
326 status = "disabled";
327 };
328
329 sdhi0: sd@e804e000 {
330 compatible = "renesas,sdhi-r7s72100";
331 reg = <0xe804e000 0x100>;
332 interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH
333 GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH
334 GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
335
336 clocks = <&mstp12_clks R7S72100_CLK_SDHI00>,
337 <&mstp12_clks R7S72100_CLK_SDHI01>;
338 clock-names = "core", "cd";
339 power-domains = <&cpg_clocks>;
340 cap-sd-highspeed;
341 cap-sdio-irq;
342 status = "disabled";
343 };
344
345 sdhi1: sd@e804e800 {
346 compatible = "renesas,sdhi-r7s72100";
347 reg = <0xe804e800 0x100>;
348 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH
349 GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH
350 GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>;
351
352 clocks = <&mstp12_clks R7S72100_CLK_SDHI10>,
353 <&mstp12_clks R7S72100_CLK_SDHI11>;
354 clock-names = "core", "cd";
355 power-domains = <&cpg_clocks>;
356 cap-sd-highspeed;
357 cap-sdio-irq;
358 status = "disabled";
359 };
360
361 gic: interrupt-controller@e8201000 {
362 compatible = "arm,pl390";
363 #interrupt-cells = <3>;
364 #address-cells = <0>;
365 interrupt-controller;
366 reg = <0xe8201000 0x1000>,
367 <0xe8202000 0x1000>;
368 };
369
370 ether: ethernet@e8203000 {
371 compatible = "renesas,ether-r7s72100";
372 reg = <0xe8203000 0x800>,
373 <0xe8204800 0x200>;
374 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
375 clocks = <&mstp7_clks R7S72100_CLK_ETHER>;
376 power-domains = <&cpg_clocks>;
377 phy-mode = "mii";
378 #address-cells = <1>;
379 #size-cells = <0>;
380 status = "disabled";
381 };
382
383 ceu: camera@e8210000 {
384 reg = <0xe8210000 0x3000>;
385 compatible = "renesas,r7s72100-ceu";
386 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
387 clocks = <&mstp6_clks R7S72100_CLK_CEU>;
388 power-domains = <&cpg_clocks>;
389 status = "disabled";
390 };
391
392 wdt: watchdog@fcfe0000 {
393 compatible = "renesas,r7s72100-wdt", "renesas,rza-wdt";
394 reg = <0xfcfe0000 0x6>;
395 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
396 clocks = <&p0_clk>;
89 }; 397 };
90 398
91 /* Special CPG clocks */ 399 /* Special CPG clocks */
@@ -135,9 +443,9 @@
135 #clock-cells = <1>; 443 #clock-cells = <1>;
136 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; 444 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
137 reg = <0xfcfe042c 4>; 445 reg = <0xfcfe042c 4>;
138 clocks = <&p0_clk>; 446 clocks = <&b_clk>, <&p0_clk>;
139 clock-indices = <R7S72100_CLK_RTC>; 447 clock-indices = <R7S72100_CLK_CEU R7S72100_CLK_RTC>;
140 clock-output-names = "rtc"; 448 clock-output-names = "ceu", "rtc";
141 }; 449 };
142 450
143 mstp7_clks: mstp7_clks@fcfe0430 { 451 mstp7_clks: mstp7_clks@fcfe0430 {
@@ -192,479 +500,209 @@
192 >; 500 >;
193 clock-output-names = "sdhi00", "sdhi01", "sdhi10", "sdhi11"; 501 clock-output-names = "sdhi00", "sdhi01", "sdhi10", "sdhi11";
194 }; 502 };
195 };
196
197 cpus {
198 #address-cells = <1>;
199 #size-cells = <0>;
200
201 cpu@0 {
202 device_type = "cpu";
203 compatible = "arm,cortex-a9";
204 reg = <0>;
205 clock-frequency = <400000000>;
206 clocks = <&cpg_clocks R7S72100_CLK_I>;
207 next-level-cache = <&L2>;
208 };
209 };
210
211 pinctrl: pin-controller@fcfe3000 {
212 compatible = "renesas,r7s72100-ports";
213
214 reg = <0xfcfe3000 0x4230>;
215
216 port0: gpio-0 {
217 gpio-controller;
218 #gpio-cells = <2>;
219 gpio-ranges = <&pinctrl 0 0 6>;
220 };
221
222 port1: gpio-1 {
223 gpio-controller;
224 #gpio-cells = <2>;
225 gpio-ranges = <&pinctrl 0 16 16>;
226 };
227 503
228 port2: gpio-2 { 504 pinctrl: pin-controller@fcfe3000 {
229 gpio-controller; 505 compatible = "renesas,r7s72100-ports";
230 #gpio-cells = <2>; 506
231 gpio-ranges = <&pinctrl 0 32 16>; 507 reg = <0xfcfe3000 0x4230>;
508
509 port0: gpio-0 {
510 gpio-controller;
511 #gpio-cells = <2>;
512 gpio-ranges = <&pinctrl 0 0 6>;
513 };
514
515 port1: gpio-1 {
516 gpio-controller;
517 #gpio-cells = <2>;
518 gpio-ranges = <&pinctrl 0 16 16>;
519 };
520
521 port2: gpio-2 {
522 gpio-controller;
523 #gpio-cells = <2>;
524 gpio-ranges = <&pinctrl 0 32 16>;
525 };
526
527 port3: gpio-3 {
528 gpio-controller;
529 #gpio-cells = <2>;
530 gpio-ranges = <&pinctrl 0 48 16>;
531 };
532
533 port4: gpio-4 {
534 gpio-controller;
535 #gpio-cells = <2>;
536 gpio-ranges = <&pinctrl 0 64 16>;
537 };
538
539 port5: gpio-5 {
540 gpio-controller;
541 #gpio-cells = <2>;
542 gpio-ranges = <&pinctrl 0 80 11>;
543 };
544
545 port6: gpio-6 {
546 gpio-controller;
547 #gpio-cells = <2>;
548 gpio-ranges = <&pinctrl 0 96 16>;
549 };
550
551 port7: gpio-7 {
552 gpio-controller;
553 #gpio-cells = <2>;
554 gpio-ranges = <&pinctrl 0 112 16>;
555 };
556
557 port8: gpio-8 {
558 gpio-controller;
559 #gpio-cells = <2>;
560 gpio-ranges = <&pinctrl 0 128 16>;
561 };
562
563 port9: gpio-9 {
564 gpio-controller;
565 #gpio-cells = <2>;
566 gpio-ranges = <&pinctrl 0 144 8>;
567 };
568
569 port10: gpio-10 {
570 gpio-controller;
571 #gpio-cells = <2>;
572 gpio-ranges = <&pinctrl 0 160 16>;
573 };
574
575 port11: gpio-11 {
576 gpio-controller;
577 #gpio-cells = <2>;
578 gpio-ranges = <&pinctrl 0 176 16>;
579 };
232 }; 580 };
233 581
234 port3: gpio-3 { 582 ostm0: timer@fcfec000 {
235 gpio-controller; 583 compatible = "renesas,r7s72100-ostm", "renesas,ostm";
236 #gpio-cells = <2>; 584 reg = <0xfcfec000 0x30>;
237 gpio-ranges = <&pinctrl 0 48 16>; 585 interrupts = <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>;
586 clocks = <&mstp5_clks R7S72100_CLK_OSTM0>;
587 power-domains = <&cpg_clocks>;
588 status = "disabled";
238 }; 589 };
239 590
240 port4: gpio-4 { 591 ostm1: timer@fcfec400 {
241 gpio-controller; 592 compatible = "renesas,r7s72100-ostm", "renesas,ostm";
242 #gpio-cells = <2>; 593 reg = <0xfcfec400 0x30>;
243 gpio-ranges = <&pinctrl 0 64 16>; 594 interrupts = <GIC_SPI 103 IRQ_TYPE_EDGE_RISING>;
595 clocks = <&mstp5_clks R7S72100_CLK_OSTM1>;
596 power-domains = <&cpg_clocks>;
597 status = "disabled";
244 }; 598 };
245 599
246 port5: gpio-5 { 600 i2c0: i2c@fcfee000 {
247 gpio-controller; 601 #address-cells = <1>;
248 #gpio-cells = <2>; 602 #size-cells = <0>;
249 gpio-ranges = <&pinctrl 0 80 11>; 603 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
604 reg = <0xfcfee000 0x44>;
605 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
606 <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>,
607 <GIC_SPI 159 IRQ_TYPE_EDGE_RISING>,
608 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
609 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
610 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
611 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
612 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
613 clocks = <&mstp9_clks R7S72100_CLK_I2C0>;
614 clock-frequency = <100000>;
615 power-domains = <&cpg_clocks>;
616 status = "disabled";
250 }; 617 };
251 618
252 port6: gpio-6 { 619 i2c1: i2c@fcfee400 {
253 gpio-controller; 620 #address-cells = <1>;
254 #gpio-cells = <2>; 621 #size-cells = <0>;
255 gpio-ranges = <&pinctrl 0 96 16>; 622 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
623 reg = <0xfcfee400 0x44>;
624 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
625 <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>,
626 <GIC_SPI 167 IRQ_TYPE_EDGE_RISING>,
627 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
628 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
629 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
630 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
631 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
632 clocks = <&mstp9_clks R7S72100_CLK_I2C1>;
633 clock-frequency = <100000>;
634 power-domains = <&cpg_clocks>;
635 status = "disabled";
256 }; 636 };
257 637
258 port7: gpio-7 { 638 i2c2: i2c@fcfee800 {
259 gpio-controller; 639 #address-cells = <1>;
260 #gpio-cells = <2>; 640 #size-cells = <0>;
261 gpio-ranges = <&pinctrl 0 112 16>; 641 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
642 reg = <0xfcfee800 0x44>;
643 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
644 <GIC_SPI 174 IRQ_TYPE_EDGE_RISING>,
645 <GIC_SPI 175 IRQ_TYPE_EDGE_RISING>,
646 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
647 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
648 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
649 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
650 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
651 clocks = <&mstp9_clks R7S72100_CLK_I2C2>;
652 clock-frequency = <100000>;
653 power-domains = <&cpg_clocks>;
654 status = "disabled";
262 }; 655 };
263 656
264 port8: gpio-8 { 657 i2c3: i2c@fcfeec00 {
265 gpio-controller; 658 #address-cells = <1>;
266 #gpio-cells = <2>; 659 #size-cells = <0>;
267 gpio-ranges = <&pinctrl 0 128 16>; 660 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
661 reg = <0xfcfeec00 0x44>;
662 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
663 <GIC_SPI 182 IRQ_TYPE_EDGE_RISING>,
664 <GIC_SPI 183 IRQ_TYPE_EDGE_RISING>,
665 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
666 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
667 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
668 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
669 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
670 clocks = <&mstp9_clks R7S72100_CLK_I2C3>;
671 clock-frequency = <100000>;
672 power-domains = <&cpg_clocks>;
673 status = "disabled";
268 }; 674 };
269 675
270 port9: gpio-9 { 676 mtu2: timer@fcff0000 {
271 gpio-controller; 677 compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
272 #gpio-cells = <2>; 678 reg = <0xfcff0000 0x400>;
273 gpio-ranges = <&pinctrl 0 144 8>; 679 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
680 interrupt-names = "tgi0a";
681 clocks = <&mstp3_clks R7S72100_CLK_MTU2>;
682 clock-names = "fck";
683 power-domains = <&cpg_clocks>;
684 status = "disabled";
274 }; 685 };
275 686
276 port10: gpio-10 { 687 rtc: rtc@fcff1000 {
277 gpio-controller; 688 compatible = "renesas,r7s72100-rtc", "renesas,sh-rtc";
278 #gpio-cells = <2>; 689 reg = <0xfcff1000 0x2e>;
279 gpio-ranges = <&pinctrl 0 160 16>; 690 interrupts = <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
691 <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
692 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>;
693 interrupt-names = "alarm", "period", "carry";
694 clocks = <&mstp6_clks R7S72100_CLK_RTC>, <&rtc_x1_clk>,
695 <&rtc_x3_clk>, <&extal_clk>;
696 clock-names = "fck", "rtc_x1", "rtc_x3", "extal";
697 power-domains = <&cpg_clocks>;
698 status = "disabled";
280 }; 699 };
281
282 port11: gpio-11 {
283 gpio-controller;
284 #gpio-cells = <2>;
285 gpio-ranges = <&pinctrl 0 176 16>;
286 };
287 };
288
289 scif0: serial@e8007000 {
290 compatible = "renesas,scif-r7s72100", "renesas,scif";
291 reg = <0xe8007000 64>;
292 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
293 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
294 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
295 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
296 clocks = <&mstp4_clks R7S72100_CLK_SCIF0>;
297 clock-names = "fck";
298 power-domains = <&cpg_clocks>;
299 status = "disabled";
300 };
301
302 scif1: serial@e8007800 {
303 compatible = "renesas,scif-r7s72100", "renesas,scif";
304 reg = <0xe8007800 64>;
305 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
306 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
307 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
308 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
309 clocks = <&mstp4_clks R7S72100_CLK_SCIF1>;
310 clock-names = "fck";
311 power-domains = <&cpg_clocks>;
312 status = "disabled";
313 };
314
315 scif2: serial@e8008000 {
316 compatible = "renesas,scif-r7s72100", "renesas,scif";
317 reg = <0xe8008000 64>;
318 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
319 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
320 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
321 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
322 clocks = <&mstp4_clks R7S72100_CLK_SCIF2>;
323 clock-names = "fck";
324 power-domains = <&cpg_clocks>;
325 status = "disabled";
326 };
327
328 scif3: serial@e8008800 {
329 compatible = "renesas,scif-r7s72100", "renesas,scif";
330 reg = <0xe8008800 64>;
331 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
332 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
333 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
334 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
335 clocks = <&mstp4_clks R7S72100_CLK_SCIF3>;
336 clock-names = "fck";
337 power-domains = <&cpg_clocks>;
338 status = "disabled";
339 };
340
341 scif4: serial@e8009000 {
342 compatible = "renesas,scif-r7s72100", "renesas,scif";
343 reg = <0xe8009000 64>;
344 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
345 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
346 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
347 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
348 clocks = <&mstp4_clks R7S72100_CLK_SCIF4>;
349 clock-names = "fck";
350 power-domains = <&cpg_clocks>;
351 status = "disabled";
352 };
353
354 scif5: serial@e8009800 {
355 compatible = "renesas,scif-r7s72100", "renesas,scif";
356 reg = <0xe8009800 64>;
357 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
358 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
359 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
360 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
361 clocks = <&mstp4_clks R7S72100_CLK_SCIF5>;
362 clock-names = "fck";
363 power-domains = <&cpg_clocks>;
364 status = "disabled";
365 };
366
367 scif6: serial@e800a000 {
368 compatible = "renesas,scif-r7s72100", "renesas,scif";
369 reg = <0xe800a000 64>;
370 interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
371 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
372 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
373 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
374 clocks = <&mstp4_clks R7S72100_CLK_SCIF6>;
375 clock-names = "fck";
376 power-domains = <&cpg_clocks>;
377 status = "disabled";
378 };
379
380 scif7: serial@e800a800 {
381 compatible = "renesas,scif-r7s72100", "renesas,scif";
382 reg = <0xe800a800 64>;
383 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
384 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
385 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
386 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
387 clocks = <&mstp4_clks R7S72100_CLK_SCIF7>;
388 clock-names = "fck";
389 power-domains = <&cpg_clocks>;
390 status = "disabled";
391 };
392
393 spi0: spi@e800c800 {
394 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
395 reg = <0xe800c800 0x24>;
396 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
397 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
398 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
399 interrupt-names = "error", "rx", "tx";
400 clocks = <&mstp10_clks R7S72100_CLK_SPI0>;
401 power-domains = <&cpg_clocks>;
402 num-cs = <1>;
403 #address-cells = <1>;
404 #size-cells = <0>;
405 status = "disabled";
406 };
407
408 spi1: spi@e800d000 {
409 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
410 reg = <0xe800d000 0x24>;
411 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
412 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
413 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
414 interrupt-names = "error", "rx", "tx";
415 clocks = <&mstp10_clks R7S72100_CLK_SPI1>;
416 power-domains = <&cpg_clocks>;
417 num-cs = <1>;
418 #address-cells = <1>;
419 #size-cells = <0>;
420 status = "disabled";
421 };
422
423 spi2: spi@e800d800 {
424 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
425 reg = <0xe800d800 0x24>;
426 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
427 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
428 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
429 interrupt-names = "error", "rx", "tx";
430 clocks = <&mstp10_clks R7S72100_CLK_SPI2>;
431 power-domains = <&cpg_clocks>;
432 num-cs = <1>;
433 #address-cells = <1>;
434 #size-cells = <0>;
435 status = "disabled";
436 };
437
438 spi3: spi@e800e000 {
439 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
440 reg = <0xe800e000 0x24>;
441 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
442 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
443 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
444 interrupt-names = "error", "rx", "tx";
445 clocks = <&mstp10_clks R7S72100_CLK_SPI3>;
446 power-domains = <&cpg_clocks>;
447 num-cs = <1>;
448 #address-cells = <1>;
449 #size-cells = <0>;
450 status = "disabled";
451 };
452
453 spi4: spi@e800e800 {
454 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
455 reg = <0xe800e800 0x24>;
456 interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
457 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
458 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
459 interrupt-names = "error", "rx", "tx";
460 clocks = <&mstp10_clks R7S72100_CLK_SPI4>;
461 power-domains = <&cpg_clocks>;
462 num-cs = <1>;
463 #address-cells = <1>;
464 #size-cells = <0>;
465 status = "disabled";
466 };
467
468 gic: interrupt-controller@e8201000 {
469 compatible = "arm,pl390";
470 #interrupt-cells = <3>;
471 #address-cells = <0>;
472 interrupt-controller;
473 reg = <0xe8201000 0x1000>,
474 <0xe8202000 0x1000>;
475 };
476
477 L2: cache-controller@3ffff000 {
478 compatible = "arm,pl310-cache";
479 reg = <0x3ffff000 0x1000>;
480 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
481 arm,early-bresp-disable;
482 arm,full-line-zero-disable;
483 cache-unified;
484 cache-level = <2>;
485 };
486
487 wdt: watchdog@fcfe0000 {
488 compatible = "renesas,r7s72100-wdt", "renesas,rza-wdt";
489 reg = <0xfcfe0000 0x6>;
490 interrupts = <GIC_SPI 106 IRQ_TYPE_EDGE_RISING>;
491 clocks = <&p0_clk>;
492 };
493
494 i2c0: i2c@fcfee000 {
495 #address-cells = <1>;
496 #size-cells = <0>;
497 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
498 reg = <0xfcfee000 0x44>;
499 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
500 <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>,
501 <GIC_SPI 159 IRQ_TYPE_EDGE_RISING>,
502 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
503 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
504 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
505 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
506 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
507 clocks = <&mstp9_clks R7S72100_CLK_I2C0>;
508 clock-frequency = <100000>;
509 power-domains = <&cpg_clocks>;
510 status = "disabled";
511 };
512
513 i2c1: i2c@fcfee400 {
514 #address-cells = <1>;
515 #size-cells = <0>;
516 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
517 reg = <0xfcfee400 0x44>;
518 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
519 <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>,
520 <GIC_SPI 167 IRQ_TYPE_EDGE_RISING>,
521 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
522 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
523 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
524 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
525 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
526 clocks = <&mstp9_clks R7S72100_CLK_I2C1>;
527 clock-frequency = <100000>;
528 power-domains = <&cpg_clocks>;
529 status = "disabled";
530 };
531
532 i2c2: i2c@fcfee800 {
533 #address-cells = <1>;
534 #size-cells = <0>;
535 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
536 reg = <0xfcfee800 0x44>;
537 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
538 <GIC_SPI 174 IRQ_TYPE_EDGE_RISING>,
539 <GIC_SPI 175 IRQ_TYPE_EDGE_RISING>,
540 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
541 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
542 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
543 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
544 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
545 clocks = <&mstp9_clks R7S72100_CLK_I2C2>;
546 clock-frequency = <100000>;
547 power-domains = <&cpg_clocks>;
548 status = "disabled";
549 };
550
551 i2c3: i2c@fcfeec00 {
552 #address-cells = <1>;
553 #size-cells = <0>;
554 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
555 reg = <0xfcfeec00 0x44>;
556 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
557 <GIC_SPI 182 IRQ_TYPE_EDGE_RISING>,
558 <GIC_SPI 183 IRQ_TYPE_EDGE_RISING>,
559 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
560 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
561 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
562 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
563 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
564 clocks = <&mstp9_clks R7S72100_CLK_I2C3>;
565 clock-frequency = <100000>;
566 power-domains = <&cpg_clocks>;
567 status = "disabled";
568 };
569
570 mtu2: timer@fcff0000 {
571 compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
572 reg = <0xfcff0000 0x400>;
573 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
574 interrupt-names = "tgi0a";
575 clocks = <&mstp3_clks R7S72100_CLK_MTU2>;
576 clock-names = "fck";
577 power-domains = <&cpg_clocks>;
578 status = "disabled";
579 };
580
581 ether: ethernet@e8203000 {
582 compatible = "renesas,ether-r7s72100";
583 reg = <0xe8203000 0x800>,
584 <0xe8204800 0x200>;
585 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
586 clocks = <&mstp7_clks R7S72100_CLK_ETHER>;
587 power-domains = <&cpg_clocks>;
588 phy-mode = "mii";
589 #address-cells = <1>;
590 #size-cells = <0>;
591 status = "disabled";
592 };
593
594 mmcif: mmc@e804c800 {
595 compatible = "renesas,mmcif-r7s72100", "renesas,sh-mmcif";
596 reg = <0xe804c800 0x80>;
597 interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH
598 GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH
599 GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
600 clocks = <&mstp8_clks R7S72100_CLK_MMCIF>;
601 power-domains = <&cpg_clocks>;
602 reg-io-width = <4>;
603 bus-width = <8>;
604 status = "disabled";
605 };
606
607 sdhi0: sd@e804e000 {
608 compatible = "renesas,sdhi-r7s72100";
609 reg = <0xe804e000 0x100>;
610 interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH
611 GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH
612 GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
613
614 clocks = <&mstp12_clks R7S72100_CLK_SDHI00>,
615 <&mstp12_clks R7S72100_CLK_SDHI01>;
616 clock-names = "core", "cd";
617 power-domains = <&cpg_clocks>;
618 cap-sd-highspeed;
619 cap-sdio-irq;
620 status = "disabled";
621 };
622
623 sdhi1: sd@e804e800 {
624 compatible = "renesas,sdhi-r7s72100";
625 reg = <0xe804e800 0x100>;
626 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH
627 GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH
628 GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>;
629
630 clocks = <&mstp12_clks R7S72100_CLK_SDHI10>,
631 <&mstp12_clks R7S72100_CLK_SDHI11>;
632 clock-names = "core", "cd";
633 power-domains = <&cpg_clocks>;
634 cap-sd-highspeed;
635 cap-sdio-irq;
636 status = "disabled";
637 };
638
639 ostm0: timer@fcfec000 {
640 compatible = "renesas,r7s72100-ostm", "renesas,ostm";
641 reg = <0xfcfec000 0x30>;
642 interrupts = <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>;
643 clocks = <&mstp5_clks R7S72100_CLK_OSTM0>;
644 power-domains = <&cpg_clocks>;
645 status = "disabled";
646 };
647
648 ostm1: timer@fcfec400 {
649 compatible = "renesas,r7s72100-ostm", "renesas,ostm";
650 reg = <0xfcfec400 0x30>;
651 interrupts = <GIC_SPI 103 IRQ_TYPE_EDGE_RISING>;
652 clocks = <&mstp5_clks R7S72100_CLK_OSTM1>;
653 power-domains = <&cpg_clocks>;
654 status = "disabled";
655 }; 700 };
656 701
657 rtc: rtc@fcff1000 { 702 usb_x1_clk: usb_x1 {
658 compatible = "renesas,r7s72100-rtc", "renesas,sh-rtc"; 703 #clock-cells = <0>;
659 reg = <0xfcff1000 0x2e>; 704 compatible = "fixed-clock";
660 interrupts = <GIC_SPI 276 IRQ_TYPE_EDGE_RISING 705 /* If clk present, value must be set by board */
661 GIC_SPI 277 IRQ_TYPE_EDGE_RISING 706 clock-frequency = <0>;
662 GIC_SPI 278 IRQ_TYPE_EDGE_RISING>;
663 interrupt-names = "alarm", "period", "carry";
664 clocks = <&mstp6_clks R7S72100_CLK_RTC>, <&rtc_x1_clk>,
665 <&rtc_x3_clk>, <&extal_clk>;
666 clock-names = "fck", "rtc_x1", "rtc_x3", "extal";
667 power-domains = <&cpg_clocks>;
668 status = "disabled";
669 }; 707 };
670}; 708};
diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm.dts b/arch/arm/boot/dts/r8a73a4-ape6evm.dts
index ec7c86e06538..125c39c0222f 100644
--- a/arch/arm/boot/dts/r8a73a4-ape6evm.dts
+++ b/arch/arm/boot/dts/r8a73a4-ape6evm.dts
@@ -234,7 +234,7 @@
234&sdhi0 { 234&sdhi0 {
235 vmmc-supply = <&vcc_sdhi0>; 235 vmmc-supply = <&vcc_sdhi0>;
236 bus-width = <4>; 236 bus-width = <4>;
237 toshiba,mmc-wrprotect-disable; 237 disable-wp;
238 pinctrl-names = "default"; 238 pinctrl-names = "default";
239 pinctrl-0 = <&sdhi0_pins>; 239 pinctrl-0 = <&sdhi0_pins>;
240 status = "okay"; 240 status = "okay";
@@ -244,7 +244,7 @@
244 vmmc-supply = <&ape6evm_fixed_3v3>; 244 vmmc-supply = <&ape6evm_fixed_3v3>;
245 bus-width = <4>; 245 bus-width = <4>;
246 broken-cd; 246 broken-cd;
247 toshiba,mmc-wrprotect-disable; 247 disable-wp;
248 pinctrl-names = "default"; 248 pinctrl-names = "default";
249 pinctrl-0 = <&sdhi1_pins>; 249 pinctrl-0 = <&sdhi1_pins>;
250 status = "okay"; 250 status = "okay";
diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi
index 8e48090e4fdc..080d037f5733 100644
--- a/arch/arm/boot/dts/r8a73a4.dtsi
+++ b/arch/arm/boot/dts/r8a73a4.dtsi
@@ -57,10 +57,10 @@
57 57
58 timer { 58 timer {
59 compatible = "arm,armv7-timer"; 59 compatible = "arm,armv7-timer";
60 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 60 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
61 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 61 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
62 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 62 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
63 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 63 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
64 }; 64 };
65 65
66 dbsc1: memory-controller@e6790000 { 66 dbsc1: memory-controller@e6790000 {
@@ -464,7 +464,7 @@
464 <0 0xf1002000 0 0x2000>, 464 <0 0xf1002000 0 0x2000>,
465 <0 0xf1004000 0 0x2000>, 465 <0 0xf1004000 0 0x2000>,
466 <0 0xf1006000 0 0x2000>; 466 <0 0xf1006000 0 0x2000>;
467 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 467 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
468 clocks = <&mstp4_clks R8A73A4_CLK_INTC_SYS>; 468 clocks = <&mstp4_clks R8A73A4_CLK_INTC_SYS>;
469 clock-names = "clk"; 469 clock-names = "clk";
470 power-domains = <&pd_c4>; 470 power-domains = <&pd_c4>;
diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi
index afd3bc5e6cf2..eb9a911deefb 100644
--- a/arch/arm/boot/dts/r8a7740.dtsi
+++ b/arch/arm/boot/dts/r8a7740.dtsi
@@ -67,6 +67,24 @@
67 power-domains = <&pd_d4>; 67 power-domains = <&pd_d4>;
68 }; 68 };
69 69
70 ceu0: ceu@fe910000 {
71 reg = <0xfe910000 0x3000>;
72 compatible = "renesas,r8a7740-ceu";
73 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
74 clocks = <&mstp1_clks R8A7740_CLK_CEU20>;
75 power-domains = <&pd_a4r>;
76 status = "disabled";
77 };
78
79 ceu1: ceu@fe914000 {
80 reg = <0xfe914000 0x3000>;
81 compatible = "renesas,r8a7740-ceu";
82 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
83 clocks = <&mstp1_clks R8A7740_CLK_CEU21>;
84 power-domains = <&pd_a4r>;
85 status = "disabled";
86 };
87
70 cmt1: timer@e6138000 { 88 cmt1: timer@e6138000 {
71 compatible = "renesas,cmt-48-r8a7740", "renesas,cmt-48"; 89 compatible = "renesas,cmt-48-r8a7740", "renesas,cmt-48";
72 reg = <0xe6138000 0x170>; 90 reg = <0xe6138000 0x170>;
diff --git a/arch/arm/boot/dts/r8a7743-iwg20m.dtsi b/arch/arm/boot/dts/r8a7743-iwg20m.dtsi
index 1d3e9503c5bd..d364685d9184 100644
--- a/arch/arm/boot/dts/r8a7743-iwg20m.dtsi
+++ b/arch/arm/boot/dts/r8a7743-iwg20m.dtsi
@@ -91,6 +91,11 @@
91 }; 91 };
92}; 92};
93 93
94&rwdt {
95 timeout-sec = <60>;
96 status = "okay";
97};
98
94&sdhi0 { 99&sdhi0 {
95 pinctrl-0 = <&sdhi0_pins>; 100 pinctrl-0 = <&sdhi0_pins>;
96 pinctrl-names = "default"; 101 pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
index 1d9073ba0ce0..142949d7066f 100644
--- a/arch/arm/boot/dts/r8a7743.dtsi
+++ b/arch/arm/boot/dts/r8a7743.dtsi
@@ -125,6 +125,13 @@
125 clock-frequency = <0>; 125 clock-frequency = <0>;
126 }; 126 };
127 127
128 pmu {
129 compatible = "arm,cortex-a15-pmu";
130 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
131 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
132 interrupt-affinity = <&cpu0>, <&cpu1>;
133 };
134
128 /* External SCIF clock */ 135 /* External SCIF clock */
129 scif_clk: scif { 136 scif_clk: scif {
130 compatible = "fixed-clock"; 137 compatible = "fixed-clock";
@@ -297,6 +304,16 @@
297 reg = <0 0xe6160000 0 0x100>; 304 reg = <0 0xe6160000 0 0x100>;
298 }; 305 };
299 306
307 rwdt: watchdog@e6020000 {
308 compatible = "renesas,r8a7743-wdt",
309 "renesas,rcar-gen2-wdt";
310 reg = <0 0xe6020000 0 0x0c>;
311 clocks = <&cpg CPG_MOD 402>;
312 power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
313 resets = <&cpg 402>;
314 status = "disabled";
315 };
316
300 sysc: system-controller@e6180000 { 317 sysc: system-controller@e6180000 {
301 compatible = "renesas,r8a7743-sysc"; 318 compatible = "renesas,r8a7743-sysc";
302 reg = <0 0xe6180000 0 0x200>; 319 reg = <0 0xe6180000 0 0x200>;
@@ -407,7 +424,7 @@
407 424
408 smp-sram@0 { 425 smp-sram@0 {
409 compatible = "renesas,smp-sram"; 426 compatible = "renesas,smp-sram";
410 reg = <0 0x10>; 427 reg = <0 0x100>;
411 }; 428 };
412 }; 429 };
413 430
diff --git a/arch/arm/boot/dts/r8a7745-iwg22m.dtsi b/arch/arm/boot/dts/r8a7745-iwg22m.dtsi
index 8d0a392b6811..29b6e10fdf96 100644
--- a/arch/arm/boot/dts/r8a7745-iwg22m.dtsi
+++ b/arch/arm/boot/dts/r8a7745-iwg22m.dtsi
@@ -91,6 +91,11 @@
91 }; 91 };
92}; 92};
93 93
94&rwdt {
95 timeout-sec = <60>;
96 status = "okay";
97};
98
94&sdhi1 { 99&sdhi1 {
95 pinctrl-0 = <&sdhi1_pins>; 100 pinctrl-0 = <&sdhi1_pins>;
96 pinctrl-names = "default"; 101 pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
index dd49a8b48f3e..1cb7a7ab0418 100644
--- a/arch/arm/boot/dts/r8a7745.dtsi
+++ b/arch/arm/boot/dts/r8a7745.dtsi
@@ -105,6 +105,13 @@
105 clock-frequency = <0>; 105 clock-frequency = <0>;
106 }; 106 };
107 107
108 pmu {
109 compatible = "arm,cortex-a7-pmu";
110 interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
111 <&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
112 interrupt-affinity = <&cpu0>, <&cpu1>;
113 };
114
108 /* External SCIF clock */ 115 /* External SCIF clock */
109 scif_clk: scif { 116 scif_clk: scif {
110 compatible = "fixed-clock"; 117 compatible = "fixed-clock";
@@ -262,6 +269,16 @@
262 reg = <0 0xe6160000 0 0x100>; 269 reg = <0 0xe6160000 0 0x100>;
263 }; 270 };
264 271
272 rwdt: watchdog@e6020000 {
273 compatible = "renesas,r8a7745-wdt",
274 "renesas,rcar-gen2-wdt";
275 reg = <0 0xe6020000 0 0x0c>;
276 clocks = <&cpg CPG_MOD 402>;
277 power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
278 resets = <&cpg 402>;
279 status = "disabled";
280 };
281
265 sysc: system-controller@e6180000 { 282 sysc: system-controller@e6180000 {
266 compatible = "renesas,r8a7745-sysc"; 283 compatible = "renesas,r8a7745-sysc";
267 reg = <0 0xe6180000 0 0x200>; 284 reg = <0 0xe6180000 0 0x200>;
@@ -360,7 +377,7 @@
360 377
361 smp-sram@0 { 378 smp-sram@0 {
362 compatible = "renesas,smp-sram"; 379 compatible = "renesas,smp-sram";
363 reg = <0 0x10>; 380 reg = <0 0x100>;
364 }; 381 };
365 }; 382 };
366 383
diff --git a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
new file mode 100644
index 000000000000..e3585daafdd6
--- /dev/null
+++ b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
@@ -0,0 +1,48 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the iWave-RZ/G1C single board computer
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 */
7
8/dts-v1/;
9#include "r8a77470.dtsi"
10/ {
11 model = "iWave iW-RainboW-G23S single board computer based on RZ/G1C";
12 compatible = "iwave,g23s", "renesas,r8a77470";
13
14 aliases {
15 ethernet0 = &avb;
16 serial1 = &scif1;
17 };
18
19 chosen {
20 bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
21 stdout-path = "serial1:115200n8";
22 };
23
24 memory@40000000 {
25 device_type = "memory";
26 reg = <0 0x40000000 0 0x20000000>;
27 };
28};
29
30&avb {
31 phy-handle = <&phy3>;
32 phy-mode = "gmii";
33 renesas,no-ether-link;
34 status = "okay";
35
36 phy3: ethernet-phy@3 {
37 reg = <3>;
38 micrel,led-mode = <1>;
39 };
40};
41
42&extal_clk {
43 clock-frequency = <20000000>;
44};
45
46&scif1 {
47 status = "okay";
48};
diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi
new file mode 100644
index 000000000000..c85032f9605b
--- /dev/null
+++ b/arch/arm/boot/dts/r8a77470.dtsi
@@ -0,0 +1,336 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the r8a77470 SoC
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/irq.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/clock/renesas-cpg-mssr.h>
11/ {
12 compatible = "renesas,r8a77470";
13 #address-cells = <2>;
14 #size-cells = <2>;
15
16 cpus {
17 #address-cells = <1>;
18 #size-cells = <0>;
19
20 cpu0: cpu@0 {
21 device_type = "cpu";
22 compatible = "arm,cortex-a7";
23 reg = <0>;
24 clock-frequency = <1000000000>;
25 clocks = <&cpg CPG_CORE 0>;
26 power-domains = <&sysc 5>;
27 next-level-cache = <&L2_CA7>;
28 };
29
30
31 L2_CA7: cache-controller-0 {
32 compatible = "cache";
33 cache-unified;
34 cache-level = <2>;
35 power-domains = <&sysc 21>;
36 };
37 };
38
39 /* External root clock */
40 extal_clk: extal {
41 compatible = "fixed-clock";
42 #clock-cells = <0>;
43 /* This value must be overridden by the board. */
44 clock-frequency = <0>;
45 };
46
47 /* External SCIF clock */
48 scif_clk: scif {
49 compatible = "fixed-clock";
50 #clock-cells = <0>;
51 /* This value must be overridden by the board. */
52 clock-frequency = <0>;
53 };
54
55 soc {
56 compatible = "simple-bus";
57 interrupt-parent = <&gic>;
58
59 #address-cells = <2>;
60 #size-cells = <2>;
61 ranges;
62
63 cpg: clock-controller@e6150000 {
64 compatible = "renesas,r8a77470-cpg-mssr";
65 reg = <0 0xe6150000 0 0x1000>;
66 clocks = <&extal_clk>, <&usb_extal_clk>;
67 clock-names = "extal", "usb_extal";
68 #clock-cells = <2>;
69 #power-domain-cells = <0>;
70 #reset-cells = <1>;
71 };
72
73 rst: reset-controller@e6160000 {
74 compatible = "renesas,r8a77470-rst";
75 reg = <0 0xe6160000 0 0x100>;
76 };
77
78 sysc: system-controller@e6180000 {
79 compatible = "renesas,r8a77470-sysc";
80 reg = <0 0xe6180000 0 0x200>;
81 #power-domain-cells = <1>;
82 };
83
84 irqc: interrupt-controller@e61c0000 {
85 compatible = "renesas,irqc-r8a77470", "renesas,irqc";
86 #interrupt-cells = <2>;
87 interrupt-controller;
88 reg = <0 0xe61c0000 0 0x200>;
89 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
90 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
91 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
92 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
93 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
94 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
95 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
96 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
97 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
98 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
99 clocks = <&cpg CPG_MOD 407>;
100 power-domains = <&sysc 32>;
101 resets = <&cpg 407>;
102 };
103
104 icram0: sram@e63a0000 {
105 compatible = "mmio-sram";
106 reg = <0 0xe63a0000 0 0x12000>;
107 };
108
109 icram1: sram@e63c0000 {
110 compatible = "mmio-sram";
111 reg = <0 0xe63c0000 0 0x1000>;
112 #address-cells = <1>;
113 #size-cells = <1>;
114 ranges = <0 0 0xe63c0000 0x1000>;
115
116 smp-sram@0 {
117 compatible = "renesas,smp-sram";
118 reg = <0 0x100>;
119 };
120 };
121
122 icram2: sram@e6300000 {
123 compatible = "mmio-sram";
124 reg = <0 0xe6300000 0 0x20000>;
125 };
126
127 dmac0: dma-controller@e6700000 {
128 compatible = "renesas,dmac-r8a77470",
129 "renesas,rcar-dmac";
130 reg = <0 0xe6700000 0 0x20000>;
131 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
132 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
133 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
134 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
135 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
136 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
137 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
138 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
139 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
140 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
141 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
142 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
143 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
144 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
145 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
146 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
147 interrupt-names = "error",
148 "ch0", "ch1", "ch2", "ch3",
149 "ch4", "ch5", "ch6", "ch7",
150 "ch8", "ch9", "ch10", "ch11",
151 "ch12", "ch13", "ch14";
152 clocks = <&cpg CPG_MOD 219>;
153 clock-names = "fck";
154 power-domains = <&sysc 32>;
155 resets = <&cpg 219>;
156 #dma-cells = <1>;
157 dma-channels = <15>;
158 };
159
160 dmac1: dma-controller@e6720000 {
161 compatible = "renesas,dmac-r8a77470",
162 "renesas,rcar-dmac";
163 reg = <0 0xe6720000 0 0x20000>;
164 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
165 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
166 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
167 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
168 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
169 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
170 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
171 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
172 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
173 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
174 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
175 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
176 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
177 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
178 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
179 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
180 interrupt-names = "error",
181 "ch0", "ch1", "ch2", "ch3",
182 "ch4", "ch5", "ch6", "ch7",
183 "ch8", "ch9", "ch10", "ch11",
184 "ch12", "ch13", "ch14";
185 clocks = <&cpg CPG_MOD 218>;
186 clock-names = "fck";
187 power-domains = <&sysc 32>;
188 resets = <&cpg 218>;
189 #dma-cells = <1>;
190 dma-channels = <15>;
191 };
192
193 avb: ethernet@e6800000 {
194 compatible = "renesas,etheravb-r8a77470",
195 "renesas,etheravb-rcar-gen2";
196 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
197 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
198 clocks = <&cpg CPG_MOD 812>;
199 power-domains = <&sysc 32>;
200 resets = <&cpg 812>;
201 #address-cells = <1>;
202 #size-cells = <0>;
203 status = "disabled";
204 };
205
206 scif0: serial@e6e60000 {
207 compatible = "renesas,scif-r8a77470",
208 "renesas,rcar-gen2-scif", "renesas,scif";
209 reg = <0 0xe6e60000 0 0x40>;
210 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
211 clocks = <&cpg CPG_MOD 721>,
212 <&cpg CPG_CORE 5>, <&scif_clk>;
213 clock-names = "fck", "brg_int", "scif_clk";
214 dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
215 <&dmac1 0x29>, <&dmac1 0x2a>;
216 dma-names = "tx", "rx", "tx", "rx";
217 power-domains = <&sysc 32>;
218 resets = <&cpg 721>;
219 status = "disabled";
220 };
221
222 scif1: serial@e6e68000 {
223 compatible = "renesas,scif-r8a77470",
224 "renesas,rcar-gen2-scif", "renesas,scif";
225 reg = <0 0xe6e68000 0 0x40>;
226 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
227 clocks = <&cpg CPG_MOD 720>,
228 <&cpg CPG_CORE 5>, <&scif_clk>;
229 clock-names = "fck", "brg_int", "scif_clk";
230 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
231 <&dmac1 0x2d>, <&dmac1 0x2e>;
232 dma-names = "tx", "rx", "tx", "rx";
233 power-domains = <&sysc 32>;
234 resets = <&cpg 720>;
235 status = "disabled";
236 };
237
238 scif2: serial@e6e58000 {
239 compatible = "renesas,scif-r8a77470",
240 "renesas,rcar-gen2-scif", "renesas,scif";
241 reg = <0 0xe6e58000 0 0x40>;
242 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
243 clocks = <&cpg CPG_MOD 719>,
244 <&cpg CPG_CORE 5>, <&scif_clk>;
245 clock-names = "fck", "brg_int", "scif_clk";
246 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
247 <&dmac1 0x2b>, <&dmac1 0x2c>;
248 dma-names = "tx", "rx", "tx", "rx";
249 power-domains = <&sysc 32>;
250 resets = <&cpg 719>;
251 status = "disabled";
252 };
253
254 scif3: serial@e6ea8000 {
255 compatible = "renesas,scif-r8a77470",
256 "renesas,rcar-gen2-scif", "renesas,scif";
257 reg = <0 0xe6ea8000 0 0x40>;
258 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
259 clocks = <&cpg CPG_MOD 718>,
260 <&cpg CPG_CORE 5>, <&scif_clk>;
261 clock-names = "fck", "brg_int", "scif_clk";
262 dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
263 <&dmac1 0x2f>, <&dmac1 0x30>;
264 dma-names = "tx", "rx", "tx", "rx";
265 power-domains = <&sysc 32>;
266 resets = <&cpg 718>;
267 status = "disabled";
268 };
269
270 scif4: serial@e6ee0000 {
271 compatible = "renesas,scif-r8a77470",
272 "renesas,rcar-gen2-scif", "renesas,scif";
273 reg = <0 0xe6ee0000 0 0x40>;
274 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
275 clocks = <&cpg CPG_MOD 715>,
276 <&cpg CPG_CORE 5>, <&scif_clk>;
277 clock-names = "fck", "brg_int", "scif_clk";
278 dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
279 <&dmac1 0xfb>, <&dmac1 0xfc>;
280 dma-names = "tx", "rx", "tx", "rx";
281 power-domains = <&sysc 32>;
282 resets = <&cpg 715>;
283 status = "disabled";
284 };
285
286 scif5: serial@e6ee8000 {
287 compatible = "renesas,scif-r8a77470",
288 "renesas,rcar-gen2-scif", "renesas,scif";
289 reg = <0 0xe6ee8000 0 0x40>;
290 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
291 clocks = <&cpg CPG_MOD 714>,
292 <&cpg CPG_CORE 5>, <&scif_clk>;
293 clock-names = "fck", "brg_int", "scif_clk";
294 dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
295 <&dmac1 0xfd>, <&dmac1 0xfe>;
296 dma-names = "tx", "rx", "tx", "rx";
297 power-domains = <&sysc 32>;
298 resets = <&cpg 714>;
299 status = "disabled";
300 };
301
302 gic: interrupt-controller@f1001000 {
303 compatible = "arm,gic-400";
304 #interrupt-cells = <3>;
305 #address-cells = <0>;
306 interrupt-controller;
307 reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>,
308 <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>;
309 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
310 clocks = <&cpg CPG_MOD 408>;
311 clock-names = "clk";
312 power-domains = <&sysc 32>;
313 resets = <&cpg 408>;
314 };
315
316 prr: chipid@ff000044 {
317 compatible = "renesas,prr";
318 reg = <0 0xff000044 0 4>;
319 };
320 };
321
322 timer {
323 compatible = "arm,armv7-timer";
324 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
325 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
326 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
327 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
328 };
329
330 /* External USB clock - can be overridden by the board */
331 usb_extal_clk: usb_extal {
332 compatible = "fixed-clock";
333 #clock-cells = <0>;
334 clock-frequency = <48000000>;
335 };
336};
diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts
index f07f9018c3e7..092610e3f953 100644
--- a/arch/arm/boot/dts/r8a7790-lager.dts
+++ b/arch/arm/boot/dts/r8a7790-lager.dts
@@ -902,9 +902,6 @@
902 status = "okay"; 902 status = "okay";
903 903
904 port { 904 port {
905 #address-cells = <1>;
906 #size-cells = <0>;
907
908 vin1ep0: endpoint { 905 vin1ep0: endpoint {
909 remote-endpoint = <&adv7180>; 906 remote-endpoint = <&adv7180>;
910 bus-width = <8>; 907 bus-width = <8>;
@@ -929,6 +926,11 @@
929 }; 926 };
930}; 927};
931 928
929&rwdt {
930 timeout-sec = <60>;
931 status = "okay";
932};
933
932&ssi1 { 934&ssi1 {
933 shared-pin; 935 shared-pin;
934}; 936};
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index 05a0fc23ac88..4d06b154bd7e 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -202,6 +202,24 @@
202 clock-frequency = <0>; 202 clock-frequency = <0>;
203 }; 203 };
204 204
205 pmu-0 {
206 compatible = "arm,cortex-a15-pmu";
207 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
208 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
209 <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
210 <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
211 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
212 };
213
214 pmu-1 {
215 compatible = "arm,cortex-a7-pmu";
216 interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
217 <&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
218 <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
219 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
220 interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
221 };
222
205 /* External SCIF clock */ 223 /* External SCIF clock */
206 scif_clk: scif { 224 scif_clk: scif {
207 compatible = "fixed-clock"; 225 compatible = "fixed-clock";
@@ -218,6 +236,16 @@
218 #size-cells = <2>; 236 #size-cells = <2>;
219 ranges; 237 ranges;
220 238
239 rwdt: watchdog@e6020000 {
240 compatible = "renesas,r8a7790-wdt",
241 "renesas,rcar-gen2-wdt";
242 reg = <0 0xe6020000 0 0x0c>;
243 clocks = <&cpg CPG_MOD 402>;
244 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
245 resets = <&cpg 402>;
246 status = "disabled";
247 };
248
221 gpio0: gpio@e6050000 { 249 gpio0: gpio@e6050000 {
222 compatible = "renesas,gpio-r8a7790", 250 compatible = "renesas,gpio-r8a7790",
223 "renesas,rcar-gen2-gpio"; 251 "renesas,rcar-gen2-gpio";
@@ -443,7 +471,7 @@
443 471
444 smp-sram@0 { 472 smp-sram@0 {
445 compatible = "renesas,smp-sram"; 473 compatible = "renesas,smp-sram";
446 reg = <0 0x10>; 474 reg = <0 0x100>;
447 }; 475 };
448 }; 476 };
449 477
@@ -1544,7 +1572,7 @@
1544 interrupt-controller; 1572 interrupt-controller;
1545 reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>, 1573 reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>,
1546 <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; 1574 <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>;
1547 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1575 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
1548 clocks = <&cpg CPG_MOD 408>; 1576 clocks = <&cpg CPG_MOD 408>;
1549 clock-names = "clk"; 1577 clock-names = "clk";
1550 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; 1578 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
@@ -1615,6 +1643,33 @@
1615 resets = <&cpg 127>; 1643 resets = <&cpg 127>;
1616 }; 1644 };
1617 1645
1646 fdp1@fe940000 {
1647 compatible = "renesas,fdp1";
1648 reg = <0 0xfe940000 0 0x2400>;
1649 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
1650 clocks = <&cpg CPG_MOD 119>;
1651 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1652 resets = <&cpg 119>;
1653 };
1654
1655 fdp1@fe944000 {
1656 compatible = "renesas,fdp1";
1657 reg = <0 0xfe944000 0 0x2400>;
1658 interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
1659 clocks = <&cpg CPG_MOD 118>;
1660 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1661 resets = <&cpg 118>;
1662 };
1663
1664 fdp1@fe948000 {
1665 compatible = "renesas,fdp1";
1666 reg = <0 0xfe948000 0 0x2400>;
1667 interrupts = <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
1668 clocks = <&cpg CPG_MOD 117>;
1669 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1670 resets = <&cpg 117>;
1671 };
1672
1618 jpu: jpeg-codec@fe980000 { 1673 jpu: jpeg-codec@fe980000 {
1619 compatible = "renesas,jpu-r8a7790", 1674 compatible = "renesas,jpu-r8a7790",
1620 "renesas,rcar-gen2-jpu"; 1675 "renesas,rcar-gen2-jpu";
@@ -1773,10 +1828,10 @@
1773 1828
1774 timer { 1829 timer {
1775 compatible = "arm,armv7-timer"; 1830 compatible = "arm,armv7-timer";
1776 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1831 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1777 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1832 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1778 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1833 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1779 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1834 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
1780 }; 1835 };
1781 1836
1782 /* External USB clock - can be overridden by the board */ 1837 /* External USB clock - can be overridden by the board */
diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts
index 9d7213a0b8b8..8ab793d8b2fd 100644
--- a/arch/arm/boot/dts/r8a7791-koelsch.dts
+++ b/arch/arm/boot/dts/r8a7791-koelsch.dts
@@ -643,6 +643,11 @@
643 status = "okay"; 643 status = "okay";
644}; 644};
645 645
646&rwdt {
647 timeout-sec = <60>;
648 status = "okay";
649};
650
646&sata0 { 651&sata0 {
647 status = "okay"; 652 status = "okay";
648}; 653};
@@ -850,9 +855,6 @@
850 pinctrl-names = "default"; 855 pinctrl-names = "default";
851 856
852 port { 857 port {
853 #address-cells = <1>;
854 #size-cells = <0>;
855
856 vin0ep2: endpoint { 858 vin0ep2: endpoint {
857 remote-endpoint = <&adv7612_out>; 859 remote-endpoint = <&adv7612_out>;
858 bus-width = <24>; 860 bus-width = <24>;
@@ -871,9 +873,6 @@
871 pinctrl-names = "default"; 873 pinctrl-names = "default";
872 874
873 port { 875 port {
874 #address-cells = <1>;
875 #size-cells = <0>;
876
877 vin1ep: endpoint { 876 vin1ep: endpoint {
878 remote-endpoint = <&adv7180>; 877 remote-endpoint = <&adv7180>;
879 bus-width = <8>; 878 bus-width = <8>;
diff --git a/arch/arm/boot/dts/r8a7791-porter.dts b/arch/arm/boot/dts/r8a7791-porter.dts
index ae9ed9ff53ef..a01101b49d99 100644
--- a/arch/arm/boot/dts/r8a7791-porter.dts
+++ b/arch/arm/boot/dts/r8a7791-porter.dts
@@ -386,9 +386,6 @@
386 pinctrl-names = "default"; 386 pinctrl-names = "default";
387 387
388 port { 388 port {
389 #address-cells = <1>;
390 #size-cells = <0>;
391
392 vin0ep: endpoint { 389 vin0ep: endpoint {
393 remote-endpoint = <&adv7180>; 390 remote-endpoint = <&adv7180>;
394 bus-width = <8>; 391 bus-width = <8>;
@@ -481,6 +478,11 @@
481 }; 478 };
482}; 479};
483 480
481&rwdt {
482 timeout-sec = <60>;
483 status = "okay";
484};
485
484&ssi1 { 486&ssi1 {
485 shared-pin; 487 shared-pin;
486}; 488};
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index 506b20885413..6e1dd7ad7bd6 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -126,6 +126,13 @@
126 clock-frequency = <0>; 126 clock-frequency = <0>;
127 }; 127 };
128 128
129 pmu {
130 compatible = "arm,cortex-a15-pmu";
131 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
132 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
133 interrupt-affinity = <&cpu0>, <&cpu1>;
134 };
135
129 /* External SCIF clock */ 136 /* External SCIF clock */
130 scif_clk: scif { 137 scif_clk: scif {
131 compatible = "fixed-clock"; 138 compatible = "fixed-clock";
@@ -142,6 +149,16 @@
142 #size-cells = <2>; 149 #size-cells = <2>;
143 ranges; 150 ranges;
144 151
152 rwdt: watchdog@e6020000 {
153 compatible = "renesas,r8a7791-wdt",
154 "renesas,rcar-gen2-wdt";
155 reg = <0 0xe6020000 0 0x0c>;
156 clocks = <&cpg CPG_MOD 402>;
157 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
158 resets = <&cpg 402>;
159 status = "disabled";
160 };
161
145 gpio0: gpio@e6050000 { 162 gpio0: gpio@e6050000 {
146 compatible = "renesas,gpio-r8a7791", 163 compatible = "renesas,gpio-r8a7791",
147 "renesas,rcar-gen2-gpio"; 164 "renesas,rcar-gen2-gpio";
@@ -407,7 +424,7 @@
407 424
408 smp-sram@0 { 425 smp-sram@0 {
409 compatible = "renesas,smp-sram"; 426 compatible = "renesas,smp-sram";
410 reg = <0 0x10>; 427 reg = <0 0x100>;
411 }; 428 };
412 }; 429 };
413 430
@@ -1621,6 +1638,24 @@
1621 resets = <&cpg 127>; 1638 resets = <&cpg 127>;
1622 }; 1639 };
1623 1640
1641 fdp1@fe940000 {
1642 compatible = "renesas,fdp1";
1643 reg = <0 0xfe940000 0 0x2400>;
1644 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
1645 clocks = <&cpg CPG_MOD 119>;
1646 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
1647 resets = <&cpg 119>;
1648 };
1649
1650 fdp1@fe944000 {
1651 compatible = "renesas,fdp1";
1652 reg = <0 0xfe944000 0 0x2400>;
1653 interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
1654 clocks = <&cpg CPG_MOD 118>;
1655 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
1656 resets = <&cpg 118>;
1657 };
1658
1624 jpu: jpeg-codec@fe980000 { 1659 jpu: jpeg-codec@fe980000 {
1625 compatible = "renesas,jpu-r8a7791", 1660 compatible = "renesas,jpu-r8a7791",
1626 "renesas,rcar-gen2-jpu"; 1661 "renesas,rcar-gen2-jpu";
diff --git a/arch/arm/boot/dts/r8a7792-blanche.dts b/arch/arm/boot/dts/r8a7792-blanche.dts
index 9b67dca6c9ef..04fb70931b3b 100644
--- a/arch/arm/boot/dts/r8a7792-blanche.dts
+++ b/arch/arm/boot/dts/r8a7792-blanche.dts
@@ -239,6 +239,11 @@
239 }; 239 };
240}; 240};
241 241
242&rwdt {
243 timeout-sec = <60>;
244 status = "okay";
245};
246
242&scif0 { 247&scif0 {
243 pinctrl-0 = <&scif0_pins>; 248 pinctrl-0 = <&scif0_pins>;
244 pinctrl-names = "default"; 249 pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/r8a7792-wheat.dts b/arch/arm/boot/dts/r8a7792-wheat.dts
index b9471b67b728..db01de7a3811 100644
--- a/arch/arm/boot/dts/r8a7792-wheat.dts
+++ b/arch/arm/boot/dts/r8a7792-wheat.dts
@@ -168,6 +168,11 @@
168 }; 168 };
169}; 169};
170 170
171&rwdt {
172 timeout-sec = <60>;
173 status = "okay";
174};
175
171&scif0 { 176&scif0 {
172 pinctrl-0 = <&scif0_pins>; 177 pinctrl-0 = <&scif0_pins>;
173 pinctrl-names = "default"; 178 pinctrl-names = "default";
@@ -240,9 +245,15 @@
240 status = "okay"; 245 status = "okay";
241 clock-frequency = <400000>; 246 clock-frequency = <400000>;
242 247
248 /*
249 * The adv75xx resets its addresses to defaults during low power mode.
250 * Because we have two ADV7513 devices on the same bus, we must change
251 * both of them away from the defaults so that they do not conflict.
252 */
243 hdmi@3d { 253 hdmi@3d {
244 compatible = "adi,adv7513"; 254 compatible = "adi,adv7513";
245 reg = <0x3d>; 255 reg = <0x3d>, <0x2d>, <0x4d>, <0x5d>;
256 reg-names = "main", "cec", "edid", "packet";
246 257
247 adi,input-depth = <8>; 258 adi,input-depth = <8>;
248 adi,input-colorspace = "rgb"; 259 adi,input-colorspace = "rgb";
@@ -272,7 +283,8 @@
272 283
273 hdmi@39 { 284 hdmi@39 {
274 compatible = "adi,adv7513"; 285 compatible = "adi,adv7513";
275 reg = <0x39>; 286 reg = <0x39>, <0x29>, <0x49>, <0x59>;
287 reg-names = "main", "cec", "edid", "packet";
276 288
277 adi,input-depth = <8>; 289 adi,input-depth = <8>;
278 adi,input-colorspace = "rgb"; 290 adi,input-colorspace = "rgb";
diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi
index 268987ff0201..f44257dd86f6 100644
--- a/arch/arm/boot/dts/r8a7792.dtsi
+++ b/arch/arm/boot/dts/r8a7792.dtsi
@@ -85,6 +85,13 @@
85 clock-frequency = <0>; 85 clock-frequency = <0>;
86 }; 86 };
87 87
88 pmu {
89 compatible = "arm,cortex-a15-pmu";
90 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
91 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
92 interrupt-affinity = <&cpu0>, <&cpu1>;
93 };
94
88 /* External SCIF clock */ 95 /* External SCIF clock */
89 scif_clk: scif { 96 scif_clk: scif {
90 compatible = "fixed-clock"; 97 compatible = "fixed-clock";
@@ -101,6 +108,16 @@
101 #size-cells = <2>; 108 #size-cells = <2>;
102 ranges; 109 ranges;
103 110
111 rwdt: watchdog@e6020000 {
112 compatible = "renesas,r8a7792-wdt",
113 "renesas,rcar-gen2-wdt";
114 reg = <0 0xe6020000 0 0x0c>;
115 clocks = <&cpg CPG_MOD 402>;
116 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
117 resets = <&cpg 402>;
118 status = "disabled";
119 };
120
104 gpio0: gpio@e6050000 { 121 gpio0: gpio@e6050000 {
105 compatible = "renesas,gpio-r8a7792", 122 compatible = "renesas,gpio-r8a7792",
106 "renesas,rcar-gen2-gpio"; 123 "renesas,rcar-gen2-gpio";
@@ -341,7 +358,7 @@
341 358
342 smp-sram@0 { 359 smp-sram@0 {
343 compatible = "renesas,smp-sram"; 360 compatible = "renesas,smp-sram";
344 reg = <0 0x10>; 361 reg = <0 0x100>;
345 }; 362 };
346 }; 363 };
347 364
diff --git a/arch/arm/boot/dts/r8a7793-gose.dts b/arch/arm/boot/dts/r8a7793-gose.dts
index 96e117d8b2cc..aa209f6e5d71 100644
--- a/arch/arm/boot/dts/r8a7793-gose.dts
+++ b/arch/arm/boot/dts/r8a7793-gose.dts
@@ -599,6 +599,11 @@
599 status = "okay"; 599 status = "okay";
600}; 600};
601 601
602&rwdt {
603 timeout-sec = <60>;
604 status = "okay";
605};
606
602&scif0 { 607&scif0 {
603 pinctrl-0 = <&scif0_pins>; 608 pinctrl-0 = <&scif0_pins>;
604 pinctrl-names = "default"; 609 pinctrl-names = "default";
@@ -758,9 +763,6 @@
758 pinctrl-names = "default"; 763 pinctrl-names = "default";
759 764
760 port { 765 port {
761 #address-cells = <1>;
762 #size-cells = <0>;
763
764 vin0ep2: endpoint { 766 vin0ep2: endpoint {
765 remote-endpoint = <&adv7612_out>; 767 remote-endpoint = <&adv7612_out>;
766 bus-width = <24>; 768 bus-width = <24>;
@@ -780,9 +782,6 @@
780 status = "okay"; 782 status = "okay";
781 783
782 port { 784 port {
783 #address-cells = <1>;
784 #size-cells = <0>;
785
786 vin1ep: endpoint { 785 vin1ep: endpoint {
787 remote-endpoint = <&adv7180_out>; 786 remote-endpoint = <&adv7180_out>;
788 bus-width = <8>; 787 bus-width = <8>;
diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi
index 4f526030dc7c..4abecfc0ca98 100644
--- a/arch/arm/boot/dts/r8a7793.dtsi
+++ b/arch/arm/boot/dts/r8a7793.dtsi
@@ -110,6 +110,13 @@
110 clock-frequency = <0>; 110 clock-frequency = <0>;
111 }; 111 };
112 112
113 pmu {
114 compatible = "arm,cortex-a15-pmu";
115 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
116 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
117 interrupt-affinity = <&cpu0>, <&cpu1>;
118 };
119
113 /* External SCIF clock */ 120 /* External SCIF clock */
114 scif_clk: scif { 121 scif_clk: scif {
115 compatible = "fixed-clock"; 122 compatible = "fixed-clock";
@@ -126,6 +133,16 @@
126 #size-cells = <2>; 133 #size-cells = <2>;
127 ranges; 134 ranges;
128 135
136 rwdt: watchdog@e6020000 {
137 compatible = "renesas,r8a7793-wdt",
138 "renesas,rcar-gen2-wdt";
139 reg = <0 0xe6020000 0 0x0c>;
140 clocks = <&cpg CPG_MOD 402>;
141 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
142 resets = <&cpg 402>;
143 status = "disabled";
144 };
145
129 gpio0: gpio@e6050000 { 146 gpio0: gpio@e6050000 {
130 compatible = "renesas,gpio-r8a7793", 147 compatible = "renesas,gpio-r8a7793",
131 "renesas,rcar-gen2-gpio"; 148 "renesas,rcar-gen2-gpio";
@@ -392,7 +409,7 @@
392 409
393 smp-sram@0 { 410 smp-sram@0 {
394 compatible = "renesas,smp-sram"; 411 compatible = "renesas,smp-sram";
395 reg = <0 0x10>; 412 reg = <0 0x100>;
396 }; 413 };
397 }; 414 };
398 415
@@ -1290,6 +1307,24 @@
1290 resets = <&cpg 408>; 1307 resets = <&cpg 408>;
1291 }; 1308 };
1292 1309
1310 fdp1@fe940000 {
1311 compatible = "renesas,fdp1";
1312 reg = <0 0xfe940000 0 0x2400>;
1313 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
1314 clocks = <&cpg CPG_MOD 119>;
1315 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
1316 resets = <&cpg 119>;
1317 };
1318
1319 fdp1@fe944000 {
1320 compatible = "renesas,fdp1";
1321 reg = <0 0xfe944000 0 0x2400>;
1322 interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
1323 clocks = <&cpg CPG_MOD 118>;
1324 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
1325 resets = <&cpg 118>;
1326 };
1327
1293 du: display@feb00000 { 1328 du: display@feb00000 {
1294 compatible = "renesas,du-r8a7793"; 1329 compatible = "renesas,du-r8a7793";
1295 reg = <0 0xfeb00000 0 0x40000>; 1330 reg = <0 0xfeb00000 0 0x40000>;
diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts
index 26a883484ea8..e17027532941 100644
--- a/arch/arm/boot/dts/r8a7794-alt.dts
+++ b/arch/arm/boot/dts/r8a7794-alt.dts
@@ -181,6 +181,12 @@
181 }; 181 };
182 }; 182 };
183 }; 183 };
184
185 eeprom@50 {
186 compatible = "renesas,r1ex24002", "atmel,24c02";
187 reg = <0x50>;
188 pagesize = <16>;
189 };
184 }; 190 };
185 191
186 /* 192 /*
@@ -330,6 +336,11 @@
330 status = "okay"; 336 status = "okay";
331}; 337};
332 338
339&rwdt {
340 timeout-sec = <60>;
341 status = "okay";
342};
343
333&sdhi0 { 344&sdhi0 {
334 pinctrl-0 = <&sdhi0_pins>; 345 pinctrl-0 = <&sdhi0_pins>;
335 pinctrl-1 = <&sdhi0_pins_uhs>; 346 pinctrl-1 = <&sdhi0_pins_uhs>;
@@ -375,9 +386,6 @@
375 pinctrl-names = "default"; 386 pinctrl-names = "default";
376 387
377 port { 388 port {
378 #address-cells = <1>;
379 #size-cells = <0>;
380
381 vin0ep: endpoint { 389 vin0ep: endpoint {
382 remote-endpoint = <&adv7180>; 390 remote-endpoint = <&adv7180>;
383 bus-width = <8>; 391 bus-width = <8>;
diff --git a/arch/arm/boot/dts/r8a7794-silk.dts b/arch/arm/boot/dts/r8a7794-silk.dts
index 351cb3b3d966..7808aaee6644 100644
--- a/arch/arm/boot/dts/r8a7794-silk.dts
+++ b/arch/arm/boot/dts/r8a7794-silk.dts
@@ -475,9 +475,6 @@
475 pinctrl-names = "default"; 475 pinctrl-names = "default";
476 476
477 port { 477 port {
478 #address-cells = <1>;
479 #size-cells = <0>;
480
481 vin0ep: endpoint { 478 vin0ep: endpoint {
482 remote-endpoint = <&adv7180>; 479 remote-endpoint = <&adv7180>;
483 bus-width = <8>; 480 bus-width = <8>;
@@ -540,6 +537,11 @@
540 }; 537 };
541}; 538};
542 539
540&rwdt {
541 timeout-sec = <60>;
542 status = "okay";
543};
544
543&ssi1 { 545&ssi1 {
544 shared-pin; 546 shared-pin;
545}; 547};
diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
index d588efa6aeaa..736196903d22 100644
--- a/arch/arm/boot/dts/r8a7794.dtsi
+++ b/arch/arm/boot/dts/r8a7794.dtsi
@@ -103,6 +103,13 @@
103 clock-frequency = <0>; 103 clock-frequency = <0>;
104 }; 104 };
105 105
106 pmu {
107 compatible = "arm,cortex-a7-pmu";
108 interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
109 <&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
110 interrupt-affinity = <&cpu0>, <&cpu1>;
111 };
112
106 /* External SCIF clock */ 113 /* External SCIF clock */
107 scif_clk: scif { 114 scif_clk: scif {
108 compatible = "fixed-clock"; 115 compatible = "fixed-clock";
@@ -119,6 +126,16 @@
119 #size-cells = <2>; 126 #size-cells = <2>;
120 ranges; 127 ranges;
121 128
129 rwdt: watchdog@e6020000 {
130 compatible = "renesas,r8a7794-wdt",
131 "renesas,rcar-gen2-wdt";
132 reg = <0 0xe6020000 0 0x0c>;
133 clocks = <&cpg CPG_MOD 402>;
134 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
135 resets = <&cpg 402>;
136 status = "disabled";
137 };
138
122 gpio0: gpio@e6050000 { 139 gpio0: gpio@e6050000 {
123 compatible = "renesas,gpio-r8a7794", 140 compatible = "renesas,gpio-r8a7794",
124 "renesas,rcar-gen2-gpio"; 141 "renesas,rcar-gen2-gpio";
@@ -348,7 +365,7 @@
348 365
349 smp-sram@0 { 366 smp-sram@0 {
350 compatible = "renesas,smp-sram"; 367 compatible = "renesas,smp-sram";
351 reg = <0 0x10>; 368 reg = <0 0x100>;
352 }; 369 };
353 }; 370 };
354 371
@@ -1323,6 +1340,15 @@
1323 resets = <&cpg 128>; 1340 resets = <&cpg 128>;
1324 }; 1341 };
1325 1342
1343 fdp1@fe940000 {
1344 compatible = "renesas,fdp1";
1345 reg = <0 0xfe940000 0 0x2400>;
1346 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
1347 clocks = <&cpg CPG_MOD 119>;
1348 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
1349 resets = <&cpg 119>;
1350 };
1351
1326 du: display@feb00000 { 1352 du: display@feb00000 {
1327 compatible = "renesas,du-r8a7794"; 1353 compatible = "renesas,du-r8a7794";
1328 reg = <0 0xfeb00000 0 0x40000>; 1354 reg = <0 0xfeb00000 0 0x40000>;
diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi
index 914a7c2a584f..c953648a5f41 100644
--- a/arch/arm/boot/dts/sh73a0.dtsi
+++ b/arch/arm/boot/dts/sh73a0.dtsi
@@ -22,7 +22,7 @@
22 #address-cells = <1>; 22 #address-cells = <1>;
23 #size-cells = <0>; 23 #size-cells = <0>;
24 24
25 cpu@0 { 25 cpu0: cpu@0 {
26 device_type = "cpu"; 26 device_type = "cpu";
27 compatible = "arm,cortex-a9"; 27 compatible = "arm,cortex-a9";
28 reg = <0>; 28 reg = <0>;
@@ -31,7 +31,7 @@
31 power-domains = <&pd_a2sl>; 31 power-domains = <&pd_a2sl>;
32 next-level-cache = <&L2>; 32 next-level-cache = <&L2>;
33 }; 33 };
34 cpu@1 { 34 cpu1: cpu@1 {
35 device_type = "cpu"; 35 device_type = "cpu";
36 compatible = "arm,cortex-a9"; 36 compatible = "arm,cortex-a9";
37 reg = <1>; 37 reg = <1>;
@@ -91,6 +91,7 @@
91 compatible = "arm,cortex-a9-pmu"; 91 compatible = "arm,cortex-a9-pmu";
92 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 92 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
93 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 93 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
94 interrupt-affinity = <&cpu0>, <&cpu1>;
94 }; 95 };
95 96
96 cmt1: timer@e6138000 { 97 cmt1: timer@e6138000 {
@@ -336,7 +337,7 @@
336 GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 337 GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
337 clocks = <&mstp3_clks SH73A0_CLK_SDHI1>; 338 clocks = <&mstp3_clks SH73A0_CLK_SDHI1>;
338 power-domains = <&pd_a3sp>; 339 power-domains = <&pd_a3sp>;
339 toshiba,mmc-wrprotect-disable; 340 disable-wp;
340 cap-sd-highspeed; 341 cap-sd-highspeed;
341 status = "disabled"; 342 status = "disabled";
342 }; 343 };
@@ -348,7 +349,7 @@
348 GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 349 GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
349 clocks = <&mstp3_clks SH73A0_CLK_SDHI2>; 350 clocks = <&mstp3_clks SH73A0_CLK_SDHI2>;
350 power-domains = <&pd_a3sp>; 351 power-domains = <&pd_a3sp>;
351 toshiba,mmc-wrprotect-disable; 352 disable-wp;
352 cap-sd-highspeed; 353 cap-sd-highspeed;
353 status = "disabled"; 354 status = "disabled";
354 }; 355 };
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 2b1535cdeb7c..d5aeac351fc3 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -208,6 +208,12 @@ config ARCH_R8A77980
208 help 208 help
209 This enables support for the Renesas R-Car V3H SoC. 209 This enables support for the Renesas R-Car V3H SoC.
210 210
211config ARCH_R8A77990
212 bool "Renesas R-Car E3 SoC Platform"
213 depends on ARCH_RENESAS
214 help
215 This enables support for the Renesas R-Car E3 SoC.
216
211config ARCH_R8A77995 217config ARCH_R8A77995
212 bool "Renesas R-Car D3 SoC Platform" 218 bool "Renesas R-Car D3 SoC Platform"
213 depends on ARCH_RENESAS 219 depends on ARCH_RENESAS
diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
index 5ede06000ea4..9e2394bc3c62 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -9,5 +9,6 @@ dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-m3ulcb-kf.dtb
9dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-xs.dtb 9dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-xs.dtb
10dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-salvator-x.dtb r8a77965-salvator-xs.dtb 10dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-salvator-x.dtb r8a77965-salvator-xs.dtb
11dtb-$(CONFIG_ARCH_R8A77970) += r8a77970-eagle.dtb r8a77970-v3msk.dtb 11dtb-$(CONFIG_ARCH_R8A77970) += r8a77970-eagle.dtb r8a77970-v3msk.dtb
12dtb-$(CONFIG_ARCH_R8A77980) += r8a77980-condor.dtb 12dtb-$(CONFIG_ARCH_R8A77980) += r8a77980-condor.dtb r8a77980-v3hsk.dtb
13dtb-$(CONFIG_ARCH_R8A77990) += r8a77990-ebisu.dtb
13dtb-$(CONFIG_ARCH_R8A77995) += r8a77995-draak.dtb 14dtb-$(CONFIG_ARCH_R8A77995) += r8a77995-draak.dtb
diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts
index 7f2a3d923f21..3f46345a4644 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts
@@ -56,6 +56,12 @@
56 status = "okay"; 56 status = "okay";
57}; 57};
58 58
59&sound_card {
60 dais = <&rsnd_port0 /* ak4613 */
61 &rsnd_port1 /* HDMI0 */
62 &rsnd_port2>; /* HDMI1 */
63};
64
59&hdmi0 { 65&hdmi0 {
60 status = "okay"; 66 status = "okay";
61 67
@@ -66,6 +72,12 @@
66 remote-endpoint = <&hdmi0_con>; 72 remote-endpoint = <&hdmi0_con>;
67 }; 73 };
68 }; 74 };
75 port@2 {
76 reg = <2>;
77 dw_hdmi0_snd_in: endpoint {
78 remote-endpoint = <&rsnd_endpoint1>;
79 };
80 };
69 }; 81 };
70}; 82};
71 83
@@ -83,6 +95,12 @@
83 remote-endpoint = <&hdmi1_con>; 95 remote-endpoint = <&hdmi1_con>;
84 }; 96 };
85 }; 97 };
98 port@2 {
99 reg = <2>;
100 dw_hdmi1_snd_in: endpoint {
101 remote-endpoint = <&rsnd_endpoint2>;
102 };
103 };
86 }; 104 };
87}; 105};
88 106
@@ -94,6 +112,34 @@
94 status = "okay"; 112 status = "okay";
95}; 113};
96 114
115&rcar_sound {
116 ports {
117 /* rsnd_port0 is on salvator-common */
118 rsnd_port1: port@1 {
119 rsnd_endpoint1: endpoint {
120 remote-endpoint = <&dw_hdmi0_snd_in>;
121
122 dai-format = "i2s";
123 bitclock-master = <&rsnd_endpoint1>;
124 frame-master = <&rsnd_endpoint1>;
125
126 playback = <&ssi2>;
127 };
128 };
129 rsnd_port2: port@2 {
130 rsnd_endpoint2: endpoint {
131 remote-endpoint = <&dw_hdmi1_snd_in>;
132
133 dai-format = "i2s";
134 bitclock-master = <&rsnd_endpoint2>;
135 frame-master = <&rsnd_endpoint2>;
136
137 playback = <&ssi3>;
138 };
139 };
140 };
141};
142
97&pfc { 143&pfc {
98 usb2_pins: usb2 { 144 usb2_pins: usb2 {
99 groups = "usb2"; 145 groups = "usb2";
diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
index f9acd125d687..e19dcd6cb767 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
@@ -39,7 +39,6 @@
39 reg = <0 0xe7730000 0 0x1000>; 39 reg = <0 0xe7730000 0 0x1000>;
40 renesas,ipmmu-main = <&ipmmu_mm 8>; 40 renesas,ipmmu-main = <&ipmmu_mm 8>;
41 #iommu-cells = <1>; 41 #iommu-cells = <1>;
42 status = "disabled";
43 }; 42 };
44 43
45 /delete-node/ usb-phy@ee0e0200; 44 /delete-node/ usb-phy@ee0e0200;
@@ -108,6 +107,61 @@
108 resets = <&cpg 117>; 107 resets = <&cpg 117>;
109 renesas,fcp = <&fcpf2>; 108 renesas,fcp = <&fcpf2>;
110 }; 109 };
110
111 csi21: csi2@fea90000 {
112 compatible = "renesas,r8a7795-csi2";
113 reg = <0 0xfea90000 0 0x10000>;
114 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
115 clocks = <&cpg CPG_MOD 713>;
116 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
117 resets = <&cpg 713>;
118 status = "disabled";
119
120 ports {
121 #address-cells = <1>;
122 #size-cells = <0>;
123
124 port@1 {
125 #address-cells = <1>;
126 #size-cells = <0>;
127
128 reg = <1>;
129
130 csi21vin0: endpoint@0 {
131 reg = <0>;
132 remote-endpoint = <&vin0csi21>;
133 };
134 csi21vin1: endpoint@1 {
135 reg = <1>;
136 remote-endpoint = <&vin1csi21>;
137 };
138 csi21vin2: endpoint@2 {
139 reg = <2>;
140 remote-endpoint = <&vin2csi21>;
141 };
142 csi21vin3: endpoint@3 {
143 reg = <3>;
144 remote-endpoint = <&vin3csi21>;
145 };
146 csi21vin4: endpoint@4 {
147 reg = <4>;
148 remote-endpoint = <&vin4csi21>;
149 };
150 csi21vin5: endpoint@5 {
151 reg = <5>;
152 remote-endpoint = <&vin5csi21>;
153 };
154 csi21vin6: endpoint@6 {
155 reg = <6>;
156 remote-endpoint = <&vin6csi21>;
157 };
158 csi21vin7: endpoint@7 {
159 reg = <7>;
160 remote-endpoint = <&vin7csi21>;
161 };
162 };
163 };
164 };
111}; 165};
112 166
113&gpio1 { 167&gpio1 {
@@ -175,3 +229,91 @@
175&du { 229&du {
176 vsps = <&vspd0 &vspd1 &vspd2 &vspd3>; 230 vsps = <&vspd0 &vspd1 &vspd2 &vspd3>;
177}; 231};
232
233&vin0 {
234 ports {
235 port@1 {
236 vin0csi21: endpoint@1 {
237 reg = <1>;
238 remote-endpoint= <&csi21vin0>;
239 };
240 };
241 };
242};
243
244&vin1 {
245 ports {
246 port@1 {
247 vin1csi21: endpoint@1 {
248 reg = <1>;
249 remote-endpoint= <&csi21vin1>;
250 };
251 };
252 };
253};
254
255&vin2 {
256 ports {
257 port@1 {
258 vin2csi21: endpoint@1 {
259 reg = <1>;
260 remote-endpoint= <&csi21vin2>;
261 };
262 };
263 };
264};
265
266&vin3 {
267 ports {
268 port@1 {
269 vin3csi21: endpoint@1 {
270 reg = <1>;
271 remote-endpoint= <&csi21vin3>;
272 };
273 };
274 };
275};
276
277&vin4 {
278 ports {
279 port@1 {
280 vin4csi21: endpoint@1 {
281 reg = <1>;
282 remote-endpoint= <&csi21vin4>;
283 };
284 };
285 };
286};
287
288&vin5 {
289 ports {
290 port@1 {
291 vin5csi21: endpoint@1 {
292 reg = <1>;
293 remote-endpoint= <&csi21vin5>;
294 };
295 };
296 };
297};
298
299&vin6 {
300 ports {
301 port@1 {
302 vin6csi21: endpoint@1 {
303 reg = <1>;
304 remote-endpoint= <&csi21vin6>;
305 };
306 };
307 };
308};
309
310&vin7 {
311 ports {
312 port@1 {
313 vin7csi21: endpoint@1 {
314 reg = <1>;
315 remote-endpoint= <&csi21vin7>;
316 };
317 };
318 };
319};
diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
index af467419266a..0efbef5ea9b7 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
@@ -56,6 +56,12 @@
56 status = "okay"; 56 status = "okay";
57}; 57};
58 58
59&sound_card {
60 dais = <&rsnd_port0 /* ak4613 */
61 &rsnd_port1 /* HDMI0 */
62 &rsnd_port2>; /* HDMI1 */
63};
64
59&hdmi0 { 65&hdmi0 {
60 status = "okay"; 66 status = "okay";
61 67
@@ -66,6 +72,12 @@
66 remote-endpoint = <&hdmi0_con>; 72 remote-endpoint = <&hdmi0_con>;
67 }; 73 };
68 }; 74 };
75 port@2 {
76 reg = <2>;
77 dw_hdmi0_snd_in: endpoint {
78 remote-endpoint = <&rsnd_endpoint1>;
79 };
80 };
69 }; 81 };
70}; 82};
71 83
@@ -83,6 +95,12 @@
83 remote-endpoint = <&hdmi1_con>; 95 remote-endpoint = <&hdmi1_con>;
84 }; 96 };
85 }; 97 };
98 port@2 {
99 reg = <2>;
100 dw_hdmi1_snd_in: endpoint {
101 remote-endpoint = <&rsnd_endpoint2>;
102 };
103 };
86 }; 104 };
87}; 105};
88 106
@@ -94,6 +112,34 @@
94 status = "okay"; 112 status = "okay";
95}; 113};
96 114
115&rcar_sound {
116 ports {
117 /* rsnd_port0 is on salvator-common */
118 rsnd_port1: port@1 {
119 rsnd_endpoint1: endpoint {
120 remote-endpoint = <&dw_hdmi0_snd_in>;
121
122 dai-format = "i2s";
123 bitclock-master = <&rsnd_endpoint1>;
124 frame-master = <&rsnd_endpoint1>;
125
126 playback = <&ssi2>;
127 };
128 };
129 rsnd_port2: port@2 {
130 rsnd_endpoint2: endpoint {
131 remote-endpoint = <&dw_hdmi1_snd_in>;
132
133 dai-format = "i2s";
134 bitclock-master = <&rsnd_endpoint2>;
135 frame-master = <&rsnd_endpoint2>;
136
137 playback = <&ssi3>;
138 };
139 };
140 };
141};
142
97&pfc { 143&pfc {
98 usb2_pins: usb2 { 144 usb2_pins: usb2 {
99 groups = "usb2"; 145 groups = "usb2";
diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts
index 8b50ceb746e8..e231b5a7cbab 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts
@@ -56,6 +56,22 @@
56 status = "okay"; 56 status = "okay";
57}; 57};
58 58
59&ehci3 {
60 dr_mode = "otg";
61 status = "okay";
62};
63
64&hsusb3 {
65 dr_mode = "otg";
66 status = "okay";
67};
68
69&sound_card {
70 dais = <&rsnd_port0 /* ak4613 */
71 &rsnd_port1 /* HDMI0 */
72 &rsnd_port2>; /* HDMI1 */
73};
74
59&hdmi0 { 75&hdmi0 {
60 status = "okay"; 76 status = "okay";
61 77
@@ -66,6 +82,12 @@
66 remote-endpoint = <&hdmi0_con>; 82 remote-endpoint = <&hdmi0_con>;
67 }; 83 };
68 }; 84 };
85 port@2 {
86 reg = <2>;
87 dw_hdmi0_snd_in: endpoint {
88 remote-endpoint = <&rsnd_endpoint1>;
89 };
90 };
69 }; 91 };
70}; 92};
71 93
@@ -83,6 +105,12 @@
83 remote-endpoint = <&hdmi1_con>; 105 remote-endpoint = <&hdmi1_con>;
84 }; 106 };
85 }; 107 };
108 port@2 {
109 reg = <2>;
110 dw_hdmi1_snd_in: endpoint {
111 remote-endpoint = <&rsnd_endpoint2>;
112 };
113 };
86 }; 114 };
87}; 115};
88 116
@@ -94,11 +122,61 @@
94 status = "okay"; 122 status = "okay";
95}; 123};
96 124
125&ohci3 {
126 dr_mode = "otg";
127 status = "okay";
128};
129
130&rcar_sound {
131 ports {
132 /* rsnd_port0 is on salvator-common */
133 rsnd_port1: port@1 {
134 rsnd_endpoint1: endpoint {
135 remote-endpoint = <&dw_hdmi0_snd_in>;
136
137 dai-format = "i2s";
138 bitclock-master = <&rsnd_endpoint1>;
139 frame-master = <&rsnd_endpoint1>;
140
141 playback = <&ssi2>;
142 };
143 };
144 rsnd_port2: port@2 {
145 rsnd_endpoint2: endpoint {
146 remote-endpoint = <&dw_hdmi1_snd_in>;
147
148 dai-format = "i2s";
149 bitclock-master = <&rsnd_endpoint2>;
150 frame-master = <&rsnd_endpoint2>;
151
152 playback = <&ssi3>;
153 };
154 };
155 };
156};
157
97&pfc { 158&pfc {
98 usb2_pins: usb2 { 159 usb2_pins: usb2 {
99 groups = "usb2"; 160 groups = "usb2";
100 function = "usb2"; 161 function = "usb2";
101 }; 162 };
163
164 /*
165 * - On Salvator-X[S], GP6_3[01] are connected to ADV7482 as irq pins
166 * (when SW31 is the default setting on Salvator-XS).
167 * - If SW31 is the default setting, you cannot use USB2.0 ch3 on
168 * r8a7795 with Salvator-XS.
169 * Hence the SW31 setting must be changed like 2) below.
170 * 1) Default setting of SW31: ON-ON-OFF-OFF-OFF-OFF:
171 * - Connect GP6_3[01] to ADV7842.
172 * 2) Changed setting of SW31: OFF-OFF-ON-ON-ON-ON:
173 * - Connect GP6_3[01] to BD082065 (USB2.0 ch3's host power).
174 * - Connect GP6_{04,21} to ADV7842.
175 */
176 usb2_ch3_pins: usb2_ch3 {
177 groups = "usb2_ch3";
178 function = "usb2_ch3";
179 };
102}; 180};
103 181
104&usb2_phy2 { 182&usb2_phy2 {
@@ -107,3 +185,10 @@
107 185
108 status = "okay"; 186 status = "okay";
109}; 187};
188
189&usb2_phy3 {
190 pinctrl-0 = <&usb2_ch3_pins>;
191 pinctrl-names = "default";
192
193 status = "okay";
194};
diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index 1d5e3ac0231c..d842940b2f43 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -30,6 +30,91 @@
30 i2c7 = &i2c_dvfs; 30 i2c7 = &i2c_dvfs;
31 }; 31 };
32 32
33 /*
34 * The external audio clocks are configured as 0 Hz fixed frequency
35 * clocks by default.
36 * Boards that provide audio clocks should override them.
37 */
38 audio_clk_a: audio_clk_a {
39 compatible = "fixed-clock";
40 #clock-cells = <0>;
41 clock-frequency = <0>;
42 };
43
44 audio_clk_b: audio_clk_b {
45 compatible = "fixed-clock";
46 #clock-cells = <0>;
47 clock-frequency = <0>;
48 };
49
50 audio_clk_c: audio_clk_c {
51 compatible = "fixed-clock";
52 #clock-cells = <0>;
53 clock-frequency = <0>;
54 };
55
56 /* External CAN clock - to be overridden by boards that provide it */
57 can_clk: can {
58 compatible = "fixed-clock";
59 #clock-cells = <0>;
60 clock-frequency = <0>;
61 };
62
63 cluster0_opp: opp_table0 {
64 compatible = "operating-points-v2";
65 opp-shared;
66
67 opp-500000000 {
68 opp-hz = /bits/ 64 <500000000>;
69 opp-microvolt = <830000>;
70 clock-latency-ns = <300000>;
71 };
72 opp-1000000000 {
73 opp-hz = /bits/ 64 <1000000000>;
74 opp-microvolt = <830000>;
75 clock-latency-ns = <300000>;
76 };
77 opp-1500000000 {
78 opp-hz = /bits/ 64 <1500000000>;
79 opp-microvolt = <830000>;
80 clock-latency-ns = <300000>;
81 opp-suspend;
82 };
83 opp-1600000000 {
84 opp-hz = /bits/ 64 <1600000000>;
85 opp-microvolt = <900000>;
86 clock-latency-ns = <300000>;
87 turbo-mode;
88 };
89 opp-1700000000 {
90 opp-hz = /bits/ 64 <1700000000>;
91 opp-microvolt = <960000>;
92 clock-latency-ns = <300000>;
93 turbo-mode;
94 };
95 };
96
97 cluster1_opp: opp_table1 {
98 compatible = "operating-points-v2";
99 opp-shared;
100
101 opp-800000000 {
102 opp-hz = /bits/ 64 <800000000>;
103 opp-microvolt = <820000>;
104 clock-latency-ns = <300000>;
105 };
106 opp-1000000000 {
107 opp-hz = /bits/ 64 <1000000000>;
108 opp-microvolt = <820000>;
109 clock-latency-ns = <300000>;
110 };
111 opp-1200000000 {
112 opp-hz = /bits/ 64 <1200000000>;
113 opp-microvolt = <820000>;
114 clock-latency-ns = <300000>;
115 };
116 };
117
33 cpus { 118 cpus {
34 #address-cells = <1>; 119 #address-cells = <1>;
35 #size-cells = <0>; 120 #size-cells = <0>;
@@ -47,7 +132,7 @@
47 }; 132 };
48 133
49 a57_1: cpu@1 { 134 a57_1: cpu@1 {
50 compatible = "arm,cortex-a57","arm,armv8"; 135 compatible = "arm,cortex-a57", "arm,armv8";
51 reg = <0x1>; 136 reg = <0x1>;
52 device_type = "cpu"; 137 device_type = "cpu";
53 power-domains = <&sysc R8A7795_PD_CA57_CPU1>; 138 power-domains = <&sysc R8A7795_PD_CA57_CPU1>;
@@ -59,7 +144,7 @@
59 }; 144 };
60 145
61 a57_2: cpu@2 { 146 a57_2: cpu@2 {
62 compatible = "arm,cortex-a57","arm,armv8"; 147 compatible = "arm,cortex-a57", "arm,armv8";
63 reg = <0x2>; 148 reg = <0x2>;
64 device_type = "cpu"; 149 device_type = "cpu";
65 power-domains = <&sysc R8A7795_PD_CA57_CPU2>; 150 power-domains = <&sysc R8A7795_PD_CA57_CPU2>;
@@ -71,7 +156,7 @@
71 }; 156 };
72 157
73 a57_3: cpu@3 { 158 a57_3: cpu@3 {
74 compatible = "arm,cortex-a57","arm,armv8"; 159 compatible = "arm,cortex-a57", "arm,armv8";
75 reg = <0x3>; 160 reg = <0x3>;
76 device_type = "cpu"; 161 device_type = "cpu";
77 power-domains = <&sysc R8A7795_PD_CA57_CPU3>; 162 power-domains = <&sysc R8A7795_PD_CA57_CPU3>;
@@ -94,7 +179,7 @@
94 }; 179 };
95 180
96 a53_1: cpu@101 { 181 a53_1: cpu@101 {
97 compatible = "arm,cortex-a53","arm,armv8"; 182 compatible = "arm,cortex-a53", "arm,armv8";
98 reg = <0x101>; 183 reg = <0x101>;
99 device_type = "cpu"; 184 device_type = "cpu";
100 power-domains = <&sysc R8A7795_PD_CA53_CPU1>; 185 power-domains = <&sysc R8A7795_PD_CA53_CPU1>;
@@ -105,7 +190,7 @@
105 }; 190 };
106 191
107 a53_2: cpu@102 { 192 a53_2: cpu@102 {
108 compatible = "arm,cortex-a53","arm,armv8"; 193 compatible = "arm,cortex-a53", "arm,armv8";
109 reg = <0x102>; 194 reg = <0x102>;
110 device_type = "cpu"; 195 device_type = "cpu";
111 power-domains = <&sysc R8A7795_PD_CA53_CPU2>; 196 power-domains = <&sysc R8A7795_PD_CA53_CPU2>;
@@ -116,7 +201,7 @@
116 }; 201 };
117 202
118 a53_3: cpu@103 { 203 a53_3: cpu@103 {
119 compatible = "arm,cortex-a53","arm,armv8"; 204 compatible = "arm,cortex-a53", "arm,armv8";
120 reg = <0x103>; 205 reg = <0x103>;
121 device_type = "cpu"; 206 device_type = "cpu";
122 power-domains = <&sysc R8A7795_PD_CA53_CPU3>; 207 power-domains = <&sysc R8A7795_PD_CA53_CPU3>;
@@ -155,91 +240,6 @@
155 clock-frequency = <0>; 240 clock-frequency = <0>;
156 }; 241 };
157 242
158 /*
159 * The external audio clocks are configured as 0 Hz fixed frequency
160 * clocks by default.
161 * Boards that provide audio clocks should override them.
162 */
163 audio_clk_a: audio_clk_a {
164 compatible = "fixed-clock";
165 #clock-cells = <0>;
166 clock-frequency = <0>;
167 };
168
169 audio_clk_b: audio_clk_b {
170 compatible = "fixed-clock";
171 #clock-cells = <0>;
172 clock-frequency = <0>;
173 };
174
175 audio_clk_c: audio_clk_c {
176 compatible = "fixed-clock";
177 #clock-cells = <0>;
178 clock-frequency = <0>;
179 };
180
181 /* External CAN clock - to be overridden by boards that provide it */
182 can_clk: can {
183 compatible = "fixed-clock";
184 #clock-cells = <0>;
185 clock-frequency = <0>;
186 };
187
188 cluster0_opp: opp_table0 {
189 compatible = "operating-points-v2";
190 opp-shared;
191
192 opp-500000000 {
193 opp-hz = /bits/ 64 <500000000>;
194 opp-microvolt = <830000>;
195 clock-latency-ns = <300000>;
196 };
197 opp-1000000000 {
198 opp-hz = /bits/ 64 <1000000000>;
199 opp-microvolt = <830000>;
200 clock-latency-ns = <300000>;
201 };
202 opp-1500000000 {
203 opp-hz = /bits/ 64 <1500000000>;
204 opp-microvolt = <830000>;
205 clock-latency-ns = <300000>;
206 opp-suspend;
207 };
208 opp-1600000000 {
209 opp-hz = /bits/ 64 <1600000000>;
210 opp-microvolt = <900000>;
211 clock-latency-ns = <300000>;
212 turbo-mode;
213 };
214 opp-1700000000 {
215 opp-hz = /bits/ 64 <1700000000>;
216 opp-microvolt = <960000>;
217 clock-latency-ns = <300000>;
218 turbo-mode;
219 };
220 };
221
222 cluster1_opp: opp_table1 {
223 compatible = "operating-points-v2";
224 opp-shared;
225
226 opp-800000000 {
227 opp-hz = /bits/ 64 <800000000>;
228 opp-microvolt = <820000>;
229 clock-latency-ns = <300000>;
230 };
231 opp-1000000000 {
232 opp-hz = /bits/ 64 <1000000000>;
233 opp-microvolt = <820000>;
234 clock-latency-ns = <300000>;
235 };
236 opp-1200000000 {
237 opp-hz = /bits/ 64 <1200000000>;
238 opp-microvolt = <820000>;
239 clock-latency-ns = <300000>;
240 };
241 };
242
243 /* External PCIe clock - can be overridden by the board */ 243 /* External PCIe clock - can be overridden by the board */
244 pcie_bus_clk: pcie_bus { 244 pcie_bus_clk: pcie_bus {
245 compatible = "fixed-clock"; 245 compatible = "fixed-clock";
@@ -247,18 +247,6 @@
247 clock-frequency = <0>; 247 clock-frequency = <0>;
248 }; 248 };
249 249
250 pmu_a57 {
251 compatible = "arm,cortex-a57-pmu";
252 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
253 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
254 <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
255 <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
256 interrupt-affinity = <&a57_0>,
257 <&a57_1>,
258 <&a57_2>,
259 <&a57_3>;
260 };
261
262 pmu_a53 { 250 pmu_a53 {
263 compatible = "arm,cortex-a53-pmu"; 251 compatible = "arm,cortex-a53-pmu";
264 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 252 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
@@ -271,6 +259,18 @@
271 <&a53_3>; 259 <&a53_3>;
272 }; 260 };
273 261
262 pmu_a57 {
263 compatible = "arm,cortex-a57-pmu";
264 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
265 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
266 <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
267 <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
268 interrupt-affinity = <&a57_0>,
269 <&a57_1>,
270 <&a57_2>,
271 <&a57_3>;
272 };
273
274 psci { 274 psci {
275 compatible = "arm,psci-1.0", "arm,psci-0.2"; 275 compatible = "arm,psci-1.0", "arm,psci-0.2";
276 method = "smc"; 276 method = "smc";
@@ -291,23 +291,6 @@
291 #size-cells = <2>; 291 #size-cells = <2>;
292 ranges; 292 ranges;
293 293
294 gic: interrupt-controller@f1010000 {
295 compatible = "arm,gic-400";
296 #interrupt-cells = <3>;
297 #address-cells = <0>;
298 interrupt-controller;
299 reg = <0x0 0xf1010000 0 0x1000>,
300 <0x0 0xf1020000 0 0x20000>,
301 <0x0 0xf1040000 0 0x20000>,
302 <0x0 0xf1060000 0 0x20000>;
303 interrupts = <GIC_PPI 9
304 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
305 clocks = <&cpg CPG_MOD 408>;
306 clock-names = "clk";
307 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
308 resets = <&cpg 408>;
309 };
310
311 wdt0: watchdog@e6020000 { 294 wdt0: watchdog@e6020000 {
312 compatible = "renesas,r8a7795-wdt", "renesas,rcar-gen3-wdt"; 295 compatible = "renesas,r8a7795-wdt", "renesas,rcar-gen3-wdt";
313 reg = <0 0xe6020000 0 0x0c>; 296 reg = <0 0xe6020000 0 0x0c>;
@@ -437,6 +420,11 @@
437 resets = <&cpg 905>; 420 resets = <&cpg 905>;
438 }; 421 };
439 422
423 pfc: pin-controller@e6060000 {
424 compatible = "renesas,pfc-r8a7795";
425 reg = <0 0xe6060000 0 0x50c>;
426 };
427
440 cpg: clock-controller@e6150000 { 428 cpg: clock-controller@e6150000 {
441 compatible = "renesas,r8a7795-cpg-mssr"; 429 compatible = "renesas,r8a7795-cpg-mssr";
442 reg = <0 0xe6150000 0 0x1000>; 430 reg = <0 0xe6150000 0 0x1000>;
@@ -452,20 +440,25 @@
452 reg = <0 0xe6160000 0 0x0200>; 440 reg = <0 0xe6160000 0 0x0200>;
453 }; 441 };
454 442
455 prr: chipid@fff00044 {
456 compatible = "renesas,prr";
457 reg = <0 0xfff00044 0 4>;
458 };
459
460 sysc: system-controller@e6180000 { 443 sysc: system-controller@e6180000 {
461 compatible = "renesas,r8a7795-sysc"; 444 compatible = "renesas,r8a7795-sysc";
462 reg = <0 0xe6180000 0 0x0400>; 445 reg = <0 0xe6180000 0 0x0400>;
463 #power-domain-cells = <1>; 446 #power-domain-cells = <1>;
464 }; 447 };
465 448
466 pfc: pin-controller@e6060000 { 449 tsc: thermal@e6198000 {
467 compatible = "renesas,pfc-r8a7795"; 450 compatible = "renesas,r8a7795-thermal";
468 reg = <0 0xe6060000 0 0x50c>; 451 reg = <0 0xe6198000 0 0x100>,
452 <0 0xe61a0000 0 0x100>,
453 <0 0xe61a8000 0 0x100>;
454 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
455 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
456 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
457 clocks = <&cpg CPG_MOD 522>;
458 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
459 resets = <&cpg 522>;
460 #thermal-sensor-cells = <1>;
461 status = "okay";
469 }; 462 };
470 463
471 intc_ex: interrupt-controller@e61c0000 { 464 intc_ex: interrupt-controller@e61c0000 {
@@ -484,153 +477,326 @@
484 resets = <&cpg 407>; 477 resets = <&cpg 407>;
485 }; 478 };
486 479
487 ipmmu_vi0: mmu@febd0000 { 480 i2c0: i2c@e6500000 {
488 compatible = "renesas,ipmmu-r8a7795"; 481 #address-cells = <1>;
489 reg = <0 0xfebd0000 0 0x1000>; 482 #size-cells = <0>;
490 renesas,ipmmu-main = <&ipmmu_mm 14>; 483 compatible = "renesas,i2c-r8a7795",
484 "renesas,rcar-gen3-i2c";
485 reg = <0 0xe6500000 0 0x40>;
486 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
487 clocks = <&cpg CPG_MOD 931>;
491 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 488 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
492 #iommu-cells = <1>; 489 resets = <&cpg 931>;
490 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
491 <&dmac2 0x91>, <&dmac2 0x90>;
492 dma-names = "tx", "rx", "tx", "rx";
493 i2c-scl-internal-delay-ns = <110>;
494 status = "disabled";
493 }; 495 };
494 496
495 ipmmu_vi1: mmu@febe0000 { 497 i2c1: i2c@e6508000 {
496 compatible = "renesas,ipmmu-r8a7795"; 498 #address-cells = <1>;
497 reg = <0 0xfebe0000 0 0x1000>; 499 #size-cells = <0>;
498 renesas,ipmmu-main = <&ipmmu_mm 15>; 500 compatible = "renesas,i2c-r8a7795",
501 "renesas,rcar-gen3-i2c";
502 reg = <0 0xe6508000 0 0x40>;
503 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
504 clocks = <&cpg CPG_MOD 930>;
499 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 505 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
500 #iommu-cells = <1>; 506 resets = <&cpg 930>;
507 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
508 <&dmac2 0x93>, <&dmac2 0x92>;
509 dma-names = "tx", "rx", "tx", "rx";
510 i2c-scl-internal-delay-ns = <6>;
501 status = "disabled"; 511 status = "disabled";
502 }; 512 };
503 513
504 ipmmu_vp0: mmu@fe990000 { 514 i2c2: i2c@e6510000 {
505 compatible = "renesas,ipmmu-r8a7795"; 515 #address-cells = <1>;
506 reg = <0 0xfe990000 0 0x1000>; 516 #size-cells = <0>;
507 renesas,ipmmu-main = <&ipmmu_mm 16>; 517 compatible = "renesas,i2c-r8a7795",
508 power-domains = <&sysc R8A7795_PD_A3VP>; 518 "renesas,rcar-gen3-i2c";
509 #iommu-cells = <1>; 519 reg = <0 0xe6510000 0 0x40>;
520 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
521 clocks = <&cpg CPG_MOD 929>;
522 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
523 resets = <&cpg 929>;
524 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
525 <&dmac2 0x95>, <&dmac2 0x94>;
526 dma-names = "tx", "rx", "tx", "rx";
527 i2c-scl-internal-delay-ns = <6>;
510 status = "disabled"; 528 status = "disabled";
511 }; 529 };
512 530
513 ipmmu_vp1: mmu@fe980000 { 531 i2c3: i2c@e66d0000 {
514 compatible = "renesas,ipmmu-r8a7795"; 532 #address-cells = <1>;
515 reg = <0 0xfe980000 0 0x1000>; 533 #size-cells = <0>;
516 renesas,ipmmu-main = <&ipmmu_mm 17>; 534 compatible = "renesas,i2c-r8a7795",
517 power-domains = <&sysc R8A7795_PD_A3VP>; 535 "renesas,rcar-gen3-i2c";
518 #iommu-cells = <1>; 536 reg = <0 0xe66d0000 0 0x40>;
537 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
538 clocks = <&cpg CPG_MOD 928>;
539 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
540 resets = <&cpg 928>;
541 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
542 dma-names = "tx", "rx";
543 i2c-scl-internal-delay-ns = <110>;
544 status = "disabled";
519 }; 545 };
520 546
521 ipmmu_vc0: mmu@fe6b0000 { 547 i2c4: i2c@e66d8000 {
522 compatible = "renesas,ipmmu-r8a7795"; 548 #address-cells = <1>;
523 reg = <0 0xfe6b0000 0 0x1000>; 549 #size-cells = <0>;
524 renesas,ipmmu-main = <&ipmmu_mm 12>; 550 compatible = "renesas,i2c-r8a7795",
525 power-domains = <&sysc R8A7795_PD_A3VC>; 551 "renesas,rcar-gen3-i2c";
526 #iommu-cells = <1>; 552 reg = <0 0xe66d8000 0 0x40>;
553 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
554 clocks = <&cpg CPG_MOD 927>;
555 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
556 resets = <&cpg 927>;
557 dmas = <&dmac0 0x99>, <&dmac0 0x98>;
558 dma-names = "tx", "rx";
559 i2c-scl-internal-delay-ns = <110>;
527 status = "disabled"; 560 status = "disabled";
528 }; 561 };
529 562
530 ipmmu_vc1: mmu@fe6f0000 { 563 i2c5: i2c@e66e0000 {
531 compatible = "renesas,ipmmu-r8a7795"; 564 #address-cells = <1>;
532 reg = <0 0xfe6f0000 0 0x1000>; 565 #size-cells = <0>;
533 renesas,ipmmu-main = <&ipmmu_mm 13>; 566 compatible = "renesas,i2c-r8a7795",
534 power-domains = <&sysc R8A7795_PD_A3VC>; 567 "renesas,rcar-gen3-i2c";
535 #iommu-cells = <1>; 568 reg = <0 0xe66e0000 0 0x40>;
569 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
570 clocks = <&cpg CPG_MOD 919>;
571 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
572 resets = <&cpg 919>;
573 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
574 dma-names = "tx", "rx";
575 i2c-scl-internal-delay-ns = <110>;
536 status = "disabled"; 576 status = "disabled";
537 }; 577 };
538 578
539 ipmmu_pv0: mmu@fd800000 { 579 i2c6: i2c@e66e8000 {
540 compatible = "renesas,ipmmu-r8a7795"; 580 #address-cells = <1>;
541 reg = <0 0xfd800000 0 0x1000>; 581 #size-cells = <0>;
542 renesas,ipmmu-main = <&ipmmu_mm 6>; 582 compatible = "renesas,i2c-r8a7795",
583 "renesas,rcar-gen3-i2c";
584 reg = <0 0xe66e8000 0 0x40>;
585 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
586 clocks = <&cpg CPG_MOD 918>;
543 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 587 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
544 #iommu-cells = <1>; 588 resets = <&cpg 918>;
589 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
590 dma-names = "tx", "rx";
591 i2c-scl-internal-delay-ns = <6>;
545 status = "disabled"; 592 status = "disabled";
546 }; 593 };
547 594
548 ipmmu_pv1: mmu@fd950000 { 595 i2c_dvfs: i2c@e60b0000 {
549 compatible = "renesas,ipmmu-r8a7795"; 596 #address-cells = <1>;
550 reg = <0 0xfd950000 0 0x1000>; 597 #size-cells = <0>;
551 renesas,ipmmu-main = <&ipmmu_mm 7>; 598 compatible = "renesas,iic-r8a7795",
599 "renesas,rcar-gen3-iic",
600 "renesas,rmobile-iic";
601 reg = <0 0xe60b0000 0 0x425>;
602 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
603 clocks = <&cpg CPG_MOD 926>;
552 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 604 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
553 #iommu-cells = <1>; 605 resets = <&cpg 926>;
606 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
607 dma-names = "tx", "rx";
554 status = "disabled"; 608 status = "disabled";
555 }; 609 };
556 610
557 ipmmu_pv2: mmu@fd960000 { 611 hscif0: serial@e6540000 {
558 compatible = "renesas,ipmmu-r8a7795"; 612 compatible = "renesas,hscif-r8a7795",
559 reg = <0 0xfd960000 0 0x1000>; 613 "renesas,rcar-gen3-hscif",
560 renesas,ipmmu-main = <&ipmmu_mm 8>; 614 "renesas,hscif";
615 reg = <0 0xe6540000 0 96>;
616 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
617 clocks = <&cpg CPG_MOD 520>,
618 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
619 <&scif_clk>;
620 clock-names = "fck", "brg_int", "scif_clk";
621 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
622 <&dmac2 0x31>, <&dmac2 0x30>;
623 dma-names = "tx", "rx", "tx", "rx";
561 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 624 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
562 #iommu-cells = <1>; 625 resets = <&cpg 520>;
563 status = "disabled"; 626 status = "disabled";
564 }; 627 };
565 628
566 ipmmu_pv3: mmu@fd970000 { 629 hscif1: serial@e6550000 {
567 compatible = "renesas,ipmmu-r8a7795"; 630 compatible = "renesas,hscif-r8a7795",
568 reg = <0 0xfd970000 0 0x1000>; 631 "renesas,rcar-gen3-hscif",
569 renesas,ipmmu-main = <&ipmmu_mm 9>; 632 "renesas,hscif";
633 reg = <0 0xe6550000 0 96>;
634 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
635 clocks = <&cpg CPG_MOD 519>,
636 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
637 <&scif_clk>;
638 clock-names = "fck", "brg_int", "scif_clk";
639 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
640 <&dmac2 0x33>, <&dmac2 0x32>;
641 dma-names = "tx", "rx", "tx", "rx";
570 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 642 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
571 #iommu-cells = <1>; 643 resets = <&cpg 519>;
572 status = "disabled"; 644 status = "disabled";
573 }; 645 };
574 646
575 ipmmu_ir: mmu@ff8b0000 { 647 hscif2: serial@e6560000 {
576 compatible = "renesas,ipmmu-r8a7795"; 648 compatible = "renesas,hscif-r8a7795",
577 reg = <0 0xff8b0000 0 0x1000>; 649 "renesas,rcar-gen3-hscif",
578 renesas,ipmmu-main = <&ipmmu_mm 3>; 650 "renesas,hscif";
579 power-domains = <&sysc R8A7795_PD_A3IR>; 651 reg = <0 0xe6560000 0 96>;
580 #iommu-cells = <1>; 652 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
653 clocks = <&cpg CPG_MOD 518>,
654 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
655 <&scif_clk>;
656 clock-names = "fck", "brg_int", "scif_clk";
657 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
658 <&dmac2 0x35>, <&dmac2 0x34>;
659 dma-names = "tx", "rx";
660 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
661 resets = <&cpg 518>;
581 status = "disabled"; 662 status = "disabled";
582 }; 663 };
583 664
584 ipmmu_hc: mmu@e6570000 { 665 hscif3: serial@e66a0000 {
585 compatible = "renesas,ipmmu-r8a7795"; 666 compatible = "renesas,hscif-r8a7795",
586 reg = <0 0xe6570000 0 0x1000>; 667 "renesas,rcar-gen3-hscif",
587 renesas,ipmmu-main = <&ipmmu_mm 2>; 668 "renesas,hscif";
669 reg = <0 0xe66a0000 0 96>;
670 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
671 clocks = <&cpg CPG_MOD 517>,
672 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
673 <&scif_clk>;
674 clock-names = "fck", "brg_int", "scif_clk";
675 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
676 dma-names = "tx", "rx";
588 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 677 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
589 #iommu-cells = <1>; 678 resets = <&cpg 517>;
590 status = "disabled"; 679 status = "disabled";
591 }; 680 };
592 681
593 ipmmu_rt: mmu@ffc80000 { 682 hscif4: serial@e66b0000 {
594 compatible = "renesas,ipmmu-r8a7795"; 683 compatible = "renesas,hscif-r8a7795",
595 reg = <0 0xffc80000 0 0x1000>; 684 "renesas,rcar-gen3-hscif",
596 renesas,ipmmu-main = <&ipmmu_mm 10>; 685 "renesas,hscif";
686 reg = <0 0xe66b0000 0 96>;
687 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
688 clocks = <&cpg CPG_MOD 516>,
689 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
690 <&scif_clk>;
691 clock-names = "fck", "brg_int", "scif_clk";
692 dmas = <&dmac0 0x39>, <&dmac0 0x38>;
693 dma-names = "tx", "rx";
597 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 694 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
598 #iommu-cells = <1>; 695 resets = <&cpg 516>;
599 status = "disabled"; 696 status = "disabled";
600 }; 697 };
601 698
602 ipmmu_mp0: mmu@ec670000 { 699 hsusb: usb@e6590000 {
603 compatible = "renesas,ipmmu-r8a7795"; 700 compatible = "renesas,usbhs-r8a7795",
604 reg = <0 0xec670000 0 0x1000>; 701 "renesas,rcar-gen3-usbhs";
605 renesas,ipmmu-main = <&ipmmu_mm 4>; 702 reg = <0 0xe6590000 0 0x100>;
703 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
704 clocks = <&cpg CPG_MOD 704>;
705 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
706 <&usb_dmac1 0>, <&usb_dmac1 1>;
707 dma-names = "ch0", "ch1", "ch2", "ch3";
708 renesas,buswait = <11>;
709 phys = <&usb2_phy0>;
710 phy-names = "usb";
606 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 711 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
607 #iommu-cells = <1>; 712 resets = <&cpg 704>;
608 status = "disabled"; 713 status = "disabled";
609 }; 714 };
610 715
611 ipmmu_ds0: mmu@e6740000 { 716 hsusb3: usb@e659c000 {
612 compatible = "renesas,ipmmu-r8a7795"; 717 compatible = "renesas,usbhs-r8a7795",
613 reg = <0 0xe6740000 0 0x1000>; 718 "renesas,rcar-gen3-usbhs";
614 renesas,ipmmu-main = <&ipmmu_mm 0>; 719 reg = <0 0xe659c000 0 0x100>;
720 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
721 clocks = <&cpg CPG_MOD 705>;
722 dmas = <&usb_dmac2 0>, <&usb_dmac2 1>,
723 <&usb_dmac3 0>, <&usb_dmac3 1>;
724 dma-names = "ch0", "ch1", "ch2", "ch3";
725 renesas,buswait = <11>;
726 phys = <&usb2_phy3>;
727 phy-names = "usb";
615 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 728 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
616 #iommu-cells = <1>; 729 resets = <&cpg 705>;
730 status = "disabled";
617 }; 731 };
618 732
619 ipmmu_ds1: mmu@e7740000 { 733 usb_dmac0: dma-controller@e65a0000 {
620 compatible = "renesas,ipmmu-r8a7795"; 734 compatible = "renesas,r8a7795-usb-dmac",
621 reg = <0 0xe7740000 0 0x1000>; 735 "renesas,usb-dmac";
622 renesas,ipmmu-main = <&ipmmu_mm 1>; 736 reg = <0 0xe65a0000 0 0x100>;
737 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
738 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
739 interrupt-names = "ch0", "ch1";
740 clocks = <&cpg CPG_MOD 330>;
623 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 741 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
624 #iommu-cells = <1>; 742 resets = <&cpg 330>;
743 #dma-cells = <1>;
744 dma-channels = <2>;
625 }; 745 };
626 746
627 ipmmu_mm: mmu@e67b0000 { 747 usb_dmac1: dma-controller@e65b0000 {
628 compatible = "renesas,ipmmu-r8a7795"; 748 compatible = "renesas,r8a7795-usb-dmac",
629 reg = <0 0xe67b0000 0 0x1000>; 749 "renesas,usb-dmac";
630 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 750 reg = <0 0xe65b0000 0 0x100>;
631 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 751 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
752 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
753 interrupt-names = "ch0", "ch1";
754 clocks = <&cpg CPG_MOD 331>;
632 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 755 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
633 #iommu-cells = <1>; 756 resets = <&cpg 331>;
757 #dma-cells = <1>;
758 dma-channels = <2>;
759 };
760
761 usb_dmac2: dma-controller@e6460000 {
762 compatible = "renesas,r8a7795-usb-dmac",
763 "renesas,usb-dmac";
764 reg = <0 0xe6460000 0 0x100>;
765 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH
766 GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
767 interrupt-names = "ch0", "ch1";
768 clocks = <&cpg CPG_MOD 326>;
769 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
770 resets = <&cpg 326>;
771 #dma-cells = <1>;
772 dma-channels = <2>;
773 };
774
775 usb_dmac3: dma-controller@e6470000 {
776 compatible = "renesas,r8a7795-usb-dmac",
777 "renesas,usb-dmac";
778 reg = <0 0xe6470000 0 0x100>;
779 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH
780 GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
781 interrupt-names = "ch0", "ch1";
782 clocks = <&cpg CPG_MOD 329>;
783 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
784 resets = <&cpg 329>;
785 #dma-cells = <1>;
786 dma-channels = <2>;
787 };
788
789 usb3_phy0: usb-phy@e65ee000 {
790 compatible = "renesas,r8a7795-usb3-phy",
791 "renesas,rcar-gen3-usb3-phy";
792 reg = <0 0xe65ee000 0 0x90>;
793 clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>,
794 <&usb_extal_clk>;
795 clock-names = "usb3-if", "usb3s_clk", "usb_extal";
796 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
797 resets = <&cpg 328>;
798 #phy-cells = <0>;
799 status = "disabled";
634 }; 800 };
635 801
636 dmac0: dma-controller@e6700000 { 802 dmac0: dma-controller@e6700000 {
@@ -759,88 +925,141 @@
759 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; 925 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
760 }; 926 };
761 927
762 audma0: dma-controller@ec700000 { 928 ipmmu_ds0: mmu@e6740000 {
763 compatible = "renesas,dmac-r8a7795", 929 compatible = "renesas,ipmmu-r8a7795";
764 "renesas,rcar-dmac"; 930 reg = <0 0xe6740000 0 0x1000>;
765 reg = <0 0xec700000 0 0x10000>; 931 renesas,ipmmu-main = <&ipmmu_mm 0>;
766 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH
767 GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
768 GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
769 GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
770 GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
771 GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
772 GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
773 GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
774 GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
775 GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
776 GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
777 GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
778 GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
779 GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH
780 GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
781 GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
782 GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
783 interrupt-names = "error",
784 "ch0", "ch1", "ch2", "ch3",
785 "ch4", "ch5", "ch6", "ch7",
786 "ch8", "ch9", "ch10", "ch11",
787 "ch12", "ch13", "ch14", "ch15";
788 clocks = <&cpg CPG_MOD 502>;
789 clock-names = "fck";
790 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 932 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
791 resets = <&cpg 502>; 933 #iommu-cells = <1>;
792 #dma-cells = <1>;
793 dma-channels = <16>;
794 iommus = <&ipmmu_mp0 0>, <&ipmmu_mp0 1>,
795 <&ipmmu_mp0 2>, <&ipmmu_mp0 3>,
796 <&ipmmu_mp0 4>, <&ipmmu_mp0 5>,
797 <&ipmmu_mp0 6>, <&ipmmu_mp0 7>,
798 <&ipmmu_mp0 8>, <&ipmmu_mp0 9>,
799 <&ipmmu_mp0 10>, <&ipmmu_mp0 11>,
800 <&ipmmu_mp0 12>, <&ipmmu_mp0 13>,
801 <&ipmmu_mp0 14>, <&ipmmu_mp0 15>;
802 }; 934 };
803 935
804 audma1: dma-controller@ec720000 { 936 ipmmu_ds1: mmu@e7740000 {
805 compatible = "renesas,dmac-r8a7795", 937 compatible = "renesas,ipmmu-r8a7795";
806 "renesas,rcar-dmac"; 938 reg = <0 0xe7740000 0 0x1000>;
807 reg = <0 0xec720000 0 0x10000>; 939 renesas,ipmmu-main = <&ipmmu_mm 1>;
808 interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH
809 GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
810 GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
811 GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
812 GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
813 GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
814 GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
815 GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
816 GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
817 GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
818 GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH
819 GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
820 GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
821 GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH
822 GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH
823 GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH
824 GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
825 interrupt-names = "error",
826 "ch0", "ch1", "ch2", "ch3",
827 "ch4", "ch5", "ch6", "ch7",
828 "ch8", "ch9", "ch10", "ch11",
829 "ch12", "ch13", "ch14", "ch15";
830 clocks = <&cpg CPG_MOD 501>;
831 clock-names = "fck";
832 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 940 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
833 resets = <&cpg 501>; 941 #iommu-cells = <1>;
834 #dma-cells = <1>; 942 };
835 dma-channels = <16>; 943
836 iommus = <&ipmmu_mp0 16>, <&ipmmu_mp0 17>, 944 ipmmu_hc: mmu@e6570000 {
837 <&ipmmu_mp0 18>, <&ipmmu_mp0 19>, 945 compatible = "renesas,ipmmu-r8a7795";
838 <&ipmmu_mp0 20>, <&ipmmu_mp0 21>, 946 reg = <0 0xe6570000 0 0x1000>;
839 <&ipmmu_mp0 22>, <&ipmmu_mp0 23>, 947 renesas,ipmmu-main = <&ipmmu_mm 2>;
840 <&ipmmu_mp0 24>, <&ipmmu_mp0 25>, 948 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
841 <&ipmmu_mp0 26>, <&ipmmu_mp0 27>, 949 #iommu-cells = <1>;
842 <&ipmmu_mp0 28>, <&ipmmu_mp0 29>, 950 };
843 <&ipmmu_mp0 30>, <&ipmmu_mp0 31>; 951
952 ipmmu_ir: mmu@ff8b0000 {
953 compatible = "renesas,ipmmu-r8a7795";
954 reg = <0 0xff8b0000 0 0x1000>;
955 renesas,ipmmu-main = <&ipmmu_mm 3>;
956 power-domains = <&sysc R8A7795_PD_A3IR>;
957 #iommu-cells = <1>;
958 };
959
960 ipmmu_mm: mmu@e67b0000 {
961 compatible = "renesas,ipmmu-r8a7795";
962 reg = <0 0xe67b0000 0 0x1000>;
963 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
964 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
965 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
966 #iommu-cells = <1>;
967 };
968
969 ipmmu_mp0: mmu@ec670000 {
970 compatible = "renesas,ipmmu-r8a7795";
971 reg = <0 0xec670000 0 0x1000>;
972 renesas,ipmmu-main = <&ipmmu_mm 4>;
973 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
974 #iommu-cells = <1>;
975 };
976
977 ipmmu_pv0: mmu@fd800000 {
978 compatible = "renesas,ipmmu-r8a7795";
979 reg = <0 0xfd800000 0 0x1000>;
980 renesas,ipmmu-main = <&ipmmu_mm 6>;
981 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
982 #iommu-cells = <1>;
983 };
984
985 ipmmu_pv1: mmu@fd950000 {
986 compatible = "renesas,ipmmu-r8a7795";
987 reg = <0 0xfd950000 0 0x1000>;
988 renesas,ipmmu-main = <&ipmmu_mm 7>;
989 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
990 #iommu-cells = <1>;
991 };
992
993 ipmmu_pv2: mmu@fd960000 {
994 compatible = "renesas,ipmmu-r8a7795";
995 reg = <0 0xfd960000 0 0x1000>;
996 renesas,ipmmu-main = <&ipmmu_mm 8>;
997 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
998 #iommu-cells = <1>;
999 };
1000
1001 ipmmu_pv3: mmu@fd970000 {
1002 compatible = "renesas,ipmmu-r8a7795";
1003 reg = <0 0xfd970000 0 0x1000>;
1004 renesas,ipmmu-main = <&ipmmu_mm 9>;
1005 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1006 #iommu-cells = <1>;
1007 };
1008
1009 ipmmu_rt: mmu@ffc80000 {
1010 compatible = "renesas,ipmmu-r8a7795";
1011 reg = <0 0xffc80000 0 0x1000>;
1012 renesas,ipmmu-main = <&ipmmu_mm 10>;
1013 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1014 #iommu-cells = <1>;
1015 };
1016
1017 ipmmu_vc0: mmu@fe6b0000 {
1018 compatible = "renesas,ipmmu-r8a7795";
1019 reg = <0 0xfe6b0000 0 0x1000>;
1020 renesas,ipmmu-main = <&ipmmu_mm 12>;
1021 power-domains = <&sysc R8A7795_PD_A3VC>;
1022 #iommu-cells = <1>;
1023 };
1024
1025 ipmmu_vc1: mmu@fe6f0000 {
1026 compatible = "renesas,ipmmu-r8a7795";
1027 reg = <0 0xfe6f0000 0 0x1000>;
1028 renesas,ipmmu-main = <&ipmmu_mm 13>;
1029 power-domains = <&sysc R8A7795_PD_A3VC>;
1030 #iommu-cells = <1>;
1031 };
1032
1033 ipmmu_vi0: mmu@febd0000 {
1034 compatible = "renesas,ipmmu-r8a7795";
1035 reg = <0 0xfebd0000 0 0x1000>;
1036 renesas,ipmmu-main = <&ipmmu_mm 14>;
1037 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1038 #iommu-cells = <1>;
1039 };
1040
1041 ipmmu_vi1: mmu@febe0000 {
1042 compatible = "renesas,ipmmu-r8a7795";
1043 reg = <0 0xfebe0000 0 0x1000>;
1044 renesas,ipmmu-main = <&ipmmu_mm 15>;
1045 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1046 #iommu-cells = <1>;
1047 };
1048
1049 ipmmu_vp0: mmu@fe990000 {
1050 compatible = "renesas,ipmmu-r8a7795";
1051 reg = <0 0xfe990000 0 0x1000>;
1052 renesas,ipmmu-main = <&ipmmu_mm 16>;
1053 power-domains = <&sysc R8A7795_PD_A3VP>;
1054 #iommu-cells = <1>;
1055 };
1056
1057 ipmmu_vp1: mmu@fe980000 {
1058 compatible = "renesas,ipmmu-r8a7795";
1059 reg = <0 0xfe980000 0 0x1000>;
1060 renesas,ipmmu-main = <&ipmmu_mm 17>;
1061 power-domains = <&sysc R8A7795_PD_A3VP>;
1062 #iommu-cells = <1>;
844 }; 1063 };
845 1064
846 avb: ethernet@e6800000 { 1065 avb: ethernet@e6800000 {
@@ -946,211 +1165,173 @@
946 }; 1165 };
947 }; 1166 };
948 1167
949 drif00: rif@e6f40000 { 1168 pwm0: pwm@e6e30000 {
950 compatible = "renesas,r8a7795-drif", 1169 compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar";
951 "renesas,rcar-gen3-drif"; 1170 reg = <0 0xe6e30000 0 0x8>;
952 reg = <0 0xe6f40000 0 0x64>; 1171 clocks = <&cpg CPG_MOD 523>;
953 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
954 clocks = <&cpg CPG_MOD 515>;
955 clock-names = "fck";
956 dmas = <&dmac1 0x20>, <&dmac2 0x20>;
957 dma-names = "rx", "rx";
958 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1172 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
959 resets = <&cpg 515>; 1173 resets = <&cpg 523>;
960 renesas,bonding = <&drif01>; 1174 #pwm-cells = <2>;
961 status = "disabled"; 1175 status = "disabled";
962 }; 1176 };
963 1177
964 drif01: rif@e6f50000 { 1178 pwm1: pwm@e6e31000 {
965 compatible = "renesas,r8a7795-drif", 1179 compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar";
966 "renesas,rcar-gen3-drif"; 1180 reg = <0 0xe6e31000 0 0x8>;
967 reg = <0 0xe6f50000 0 0x64>; 1181 clocks = <&cpg CPG_MOD 523>;
968 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
969 clocks = <&cpg CPG_MOD 514>;
970 clock-names = "fck";
971 dmas = <&dmac1 0x22>, <&dmac2 0x22>;
972 dma-names = "rx", "rx";
973 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1182 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
974 resets = <&cpg 514>; 1183 resets = <&cpg 523>;
975 renesas,bonding = <&drif00>; 1184 #pwm-cells = <2>;
976 status = "disabled"; 1185 status = "disabled";
977 }; 1186 };
978 1187
979 drif10: rif@e6f60000 { 1188 pwm2: pwm@e6e32000 {
980 compatible = "renesas,r8a7795-drif", 1189 compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar";
981 "renesas,rcar-gen3-drif"; 1190 reg = <0 0xe6e32000 0 0x8>;
982 reg = <0 0xe6f60000 0 0x64>; 1191 clocks = <&cpg CPG_MOD 523>;
983 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
984 clocks = <&cpg CPG_MOD 513>;
985 clock-names = "fck";
986 dmas = <&dmac1 0x24>, <&dmac2 0x24>;
987 dma-names = "rx", "rx";
988 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1192 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
989 resets = <&cpg 513>; 1193 resets = <&cpg 523>;
990 renesas,bonding = <&drif11>; 1194 #pwm-cells = <2>;
991 status = "disabled"; 1195 status = "disabled";
992 }; 1196 };
993 1197
994 drif11: rif@e6f70000 { 1198 pwm3: pwm@e6e33000 {
995 compatible = "renesas,r8a7795-drif", 1199 compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar";
996 "renesas,rcar-gen3-drif"; 1200 reg = <0 0xe6e33000 0 0x8>;
997 reg = <0 0xe6f70000 0 0x64>; 1201 clocks = <&cpg CPG_MOD 523>;
998 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
999 clocks = <&cpg CPG_MOD 512>;
1000 clock-names = "fck";
1001 dmas = <&dmac1 0x26>, <&dmac2 0x26>;
1002 dma-names = "rx", "rx";
1003 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1202 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1004 resets = <&cpg 512>; 1203 resets = <&cpg 523>;
1005 renesas,bonding = <&drif10>; 1204 #pwm-cells = <2>;
1006 status = "disabled"; 1205 status = "disabled";
1007 }; 1206 };
1008 1207
1009 drif20: rif@e6f80000 { 1208 pwm4: pwm@e6e34000 {
1010 compatible = "renesas,r8a7795-drif", 1209 compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar";
1011 "renesas,rcar-gen3-drif"; 1210 reg = <0 0xe6e34000 0 0x8>;
1012 reg = <0 0xe6f80000 0 0x64>; 1211 clocks = <&cpg CPG_MOD 523>;
1013 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1014 clocks = <&cpg CPG_MOD 511>;
1015 clock-names = "fck";
1016 dmas = <&dmac1 0x28>, <&dmac2 0x28>;
1017 dma-names = "rx", "rx";
1018 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1212 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1019 resets = <&cpg 511>; 1213 resets = <&cpg 523>;
1020 renesas,bonding = <&drif21>; 1214 #pwm-cells = <2>;
1021 status = "disabled"; 1215 status = "disabled";
1022 }; 1216 };
1023 1217
1024 drif21: rif@e6f90000 { 1218 pwm5: pwm@e6e35000 {
1025 compatible = "renesas,r8a7795-drif", 1219 compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar";
1026 "renesas,rcar-gen3-drif"; 1220 reg = <0 0xe6e35000 0 0x8>;
1027 reg = <0 0xe6f90000 0 0x64>; 1221 clocks = <&cpg CPG_MOD 523>;
1028 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1029 clocks = <&cpg CPG_MOD 510>;
1030 clock-names = "fck";
1031 dmas = <&dmac1 0x2a>, <&dmac2 0x2a>;
1032 dma-names = "rx", "rx";
1033 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1222 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1034 resets = <&cpg 510>; 1223 resets = <&cpg 523>;
1035 renesas,bonding = <&drif20>; 1224 #pwm-cells = <2>;
1036 status = "disabled"; 1225 status = "disabled";
1037 }; 1226 };
1038 1227
1039 drif30: rif@e6fa0000 { 1228 pwm6: pwm@e6e36000 {
1040 compatible = "renesas,r8a7795-drif", 1229 compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar";
1041 "renesas,rcar-gen3-drif"; 1230 reg = <0 0xe6e36000 0 0x8>;
1042 reg = <0 0xe6fa0000 0 0x64>; 1231 clocks = <&cpg CPG_MOD 523>;
1043 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1044 clocks = <&cpg CPG_MOD 509>;
1045 clock-names = "fck";
1046 dmas = <&dmac1 0x2c>, <&dmac2 0x2c>;
1047 dma-names = "rx", "rx";
1048 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1232 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1049 resets = <&cpg 509>; 1233 resets = <&cpg 523>;
1050 renesas,bonding = <&drif31>; 1234 #pwm-cells = <2>;
1051 status = "disabled"; 1235 status = "disabled";
1052 }; 1236 };
1053 1237
1054 drif31: rif@e6fb0000 { 1238 scif0: serial@e6e60000 {
1055 compatible = "renesas,r8a7795-drif", 1239 compatible = "renesas,scif-r8a7795",
1056 "renesas,rcar-gen3-drif"; 1240 "renesas,rcar-gen3-scif", "renesas,scif";
1057 reg = <0 0xe6fb0000 0 0x64>; 1241 reg = <0 0xe6e60000 0 64>;
1058 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 1242 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
1059 clocks = <&cpg CPG_MOD 508>; 1243 clocks = <&cpg CPG_MOD 207>,
1060 clock-names = "fck"; 1244 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
1061 dmas = <&dmac1 0x2e>, <&dmac2 0x2e>; 1245 <&scif_clk>;
1062 dma-names = "rx", "rx"; 1246 clock-names = "fck", "brg_int", "scif_clk";
1247 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
1248 <&dmac2 0x51>, <&dmac2 0x50>;
1249 dma-names = "tx", "rx", "tx", "rx";
1063 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1250 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1064 resets = <&cpg 508>; 1251 resets = <&cpg 207>;
1065 renesas,bonding = <&drif30>;
1066 status = "disabled"; 1252 status = "disabled";
1067 }; 1253 };
1068 1254
1069 hscif0: serial@e6540000 { 1255 scif1: serial@e6e68000 {
1070 compatible = "renesas,hscif-r8a7795", 1256 compatible = "renesas,scif-r8a7795",
1071 "renesas,rcar-gen3-hscif", 1257 "renesas,rcar-gen3-scif", "renesas,scif";
1072 "renesas,hscif"; 1258 reg = <0 0xe6e68000 0 64>;
1073 reg = <0 0xe6540000 0 96>; 1259 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
1074 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 1260 clocks = <&cpg CPG_MOD 206>,
1075 clocks = <&cpg CPG_MOD 520>,
1076 <&cpg CPG_CORE R8A7795_CLK_S3D1>, 1261 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
1077 <&scif_clk>; 1262 <&scif_clk>;
1078 clock-names = "fck", "brg_int", "scif_clk"; 1263 clock-names = "fck", "brg_int", "scif_clk";
1079 dmas = <&dmac1 0x31>, <&dmac1 0x30>, 1264 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
1080 <&dmac2 0x31>, <&dmac2 0x30>; 1265 <&dmac2 0x53>, <&dmac2 0x52>;
1081 dma-names = "tx", "rx", "tx", "rx"; 1266 dma-names = "tx", "rx", "tx", "rx";
1082 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1267 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1083 resets = <&cpg 520>; 1268 resets = <&cpg 206>;
1084 status = "disabled"; 1269 status = "disabled";
1085 }; 1270 };
1086 1271
1087 hscif1: serial@e6550000 { 1272 scif2: serial@e6e88000 {
1088 compatible = "renesas,hscif-r8a7795", 1273 compatible = "renesas,scif-r8a7795",
1089 "renesas,rcar-gen3-hscif", 1274 "renesas,rcar-gen3-scif", "renesas,scif";
1090 "renesas,hscif"; 1275 reg = <0 0xe6e88000 0 64>;
1091 reg = <0 0xe6550000 0 96>; 1276 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
1092 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 1277 clocks = <&cpg CPG_MOD 310>,
1093 clocks = <&cpg CPG_MOD 519>,
1094 <&cpg CPG_CORE R8A7795_CLK_S3D1>, 1278 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
1095 <&scif_clk>; 1279 <&scif_clk>;
1096 clock-names = "fck", "brg_int", "scif_clk"; 1280 clock-names = "fck", "brg_int", "scif_clk";
1097 dmas = <&dmac1 0x33>, <&dmac1 0x32>, 1281 dmas = <&dmac1 0x13>, <&dmac1 0x12>,
1098 <&dmac2 0x33>, <&dmac2 0x32>; 1282 <&dmac2 0x13>, <&dmac2 0x12>;
1099 dma-names = "tx", "rx", "tx", "rx"; 1283 dma-names = "tx", "rx", "tx", "rx";
1100 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1284 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1101 resets = <&cpg 519>; 1285 resets = <&cpg 310>;
1102 status = "disabled"; 1286 status = "disabled";
1103 }; 1287 };
1104 1288
1105 hscif2: serial@e6560000 { 1289 scif3: serial@e6c50000 {
1106 compatible = "renesas,hscif-r8a7795", 1290 compatible = "renesas,scif-r8a7795",
1107 "renesas,rcar-gen3-hscif", 1291 "renesas,rcar-gen3-scif", "renesas,scif";
1108 "renesas,hscif"; 1292 reg = <0 0xe6c50000 0 64>;
1109 reg = <0 0xe6560000 0 96>; 1293 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1110 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 1294 clocks = <&cpg CPG_MOD 204>,
1111 clocks = <&cpg CPG_MOD 518>,
1112 <&cpg CPG_CORE R8A7795_CLK_S3D1>, 1295 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
1113 <&scif_clk>; 1296 <&scif_clk>;
1114 clock-names = "fck", "brg_int", "scif_clk"; 1297 clock-names = "fck", "brg_int", "scif_clk";
1115 dmas = <&dmac1 0x35>, <&dmac1 0x34>, 1298 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
1116 <&dmac2 0x35>, <&dmac2 0x34>; 1299 dma-names = "tx", "rx";
1117 dma-names = "tx", "rx", "tx", "rx";
1118 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1300 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1119 resets = <&cpg 518>; 1301 resets = <&cpg 204>;
1120 status = "disabled"; 1302 status = "disabled";
1121 }; 1303 };
1122 1304
1123 hscif3: serial@e66a0000 { 1305 scif4: serial@e6c40000 {
1124 compatible = "renesas,hscif-r8a7795", 1306 compatible = "renesas,scif-r8a7795",
1125 "renesas,rcar-gen3-hscif", 1307 "renesas,rcar-gen3-scif", "renesas,scif";
1126 "renesas,hscif"; 1308 reg = <0 0xe6c40000 0 64>;
1127 reg = <0 0xe66a0000 0 96>; 1309 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1128 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 1310 clocks = <&cpg CPG_MOD 203>,
1129 clocks = <&cpg CPG_MOD 517>,
1130 <&cpg CPG_CORE R8A7795_CLK_S3D1>, 1311 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
1131 <&scif_clk>; 1312 <&scif_clk>;
1132 clock-names = "fck", "brg_int", "scif_clk"; 1313 clock-names = "fck", "brg_int", "scif_clk";
1133 dmas = <&dmac0 0x37>, <&dmac0 0x36>; 1314 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
1134 dma-names = "tx", "rx"; 1315 dma-names = "tx", "rx";
1135 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1316 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1136 resets = <&cpg 517>; 1317 resets = <&cpg 203>;
1137 status = "disabled"; 1318 status = "disabled";
1138 }; 1319 };
1139 1320
1140 hscif4: serial@e66b0000 { 1321 scif5: serial@e6f30000 {
1141 compatible = "renesas,hscif-r8a7795", 1322 compatible = "renesas,scif-r8a7795",
1142 "renesas,rcar-gen3-hscif", 1323 "renesas,rcar-gen3-scif", "renesas,scif";
1143 "renesas,hscif"; 1324 reg = <0 0xe6f30000 0 64>;
1144 reg = <0 0xe66b0000 0 96>; 1325 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1145 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 1326 clocks = <&cpg CPG_MOD 202>,
1146 clocks = <&cpg CPG_MOD 516>,
1147 <&cpg CPG_CORE R8A7795_CLK_S3D1>, 1327 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
1148 <&scif_clk>; 1328 <&scif_clk>;
1149 clock-names = "fck", "brg_int", "scif_clk"; 1329 clock-names = "fck", "brg_int", "scif_clk";
1150 dmas = <&dmac0 0x39>, <&dmac0 0x38>; 1330 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
1151 dma-names = "tx", "rx"; 1331 <&dmac2 0x5b>, <&dmac2 0x5a>;
1332 dma-names = "tx", "rx", "tx", "rx";
1152 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1333 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1153 resets = <&cpg 516>; 1334 resets = <&cpg 202>;
1154 status = "disabled"; 1335 status = "disabled";
1155 }; 1336 };
1156 1337
@@ -1216,304 +1397,379 @@
1216 status = "disabled"; 1397 status = "disabled";
1217 }; 1398 };
1218 1399
1219 scif0: serial@e6e60000 { 1400 vin0: video@e6ef0000 {
1220 compatible = "renesas,scif-r8a7795", 1401 compatible = "renesas,vin-r8a7795";
1221 "renesas,rcar-gen3-scif", "renesas,scif"; 1402 reg = <0 0xe6ef0000 0 0x1000>;
1222 reg = <0 0xe6e60000 0 64>; 1403 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
1223 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 1404 clocks = <&cpg CPG_MOD 811>;
1224 clocks = <&cpg CPG_MOD 207>,
1225 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
1226 <&scif_clk>;
1227 clock-names = "fck", "brg_int", "scif_clk";
1228 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
1229 <&dmac2 0x51>, <&dmac2 0x50>;
1230 dma-names = "tx", "rx", "tx", "rx";
1231 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1405 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1232 resets = <&cpg 207>; 1406 resets = <&cpg 811>;
1407 renesas,id = <0>;
1233 status = "disabled"; 1408 status = "disabled";
1234 };
1235 1409
1236 scif1: serial@e6e68000 { 1410 ports {
1237 compatible = "renesas,scif-r8a7795", 1411 #address-cells = <1>;
1238 "renesas,rcar-gen3-scif", "renesas,scif"; 1412 #size-cells = <0>;
1239 reg = <0 0xe6e68000 0 64>;
1240 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
1241 clocks = <&cpg CPG_MOD 206>,
1242 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
1243 <&scif_clk>;
1244 clock-names = "fck", "brg_int", "scif_clk";
1245 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
1246 <&dmac2 0x53>, <&dmac2 0x52>;
1247 dma-names = "tx", "rx", "tx", "rx";
1248 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1249 resets = <&cpg 206>;
1250 status = "disabled";
1251 };
1252 1413
1253 scif2: serial@e6e88000 { 1414 port@1 {
1254 compatible = "renesas,scif-r8a7795", 1415 #address-cells = <1>;
1255 "renesas,rcar-gen3-scif", "renesas,scif"; 1416 #size-cells = <0>;
1256 reg = <0 0xe6e88000 0 64>;
1257 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
1258 clocks = <&cpg CPG_MOD 310>,
1259 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
1260 <&scif_clk>;
1261 clock-names = "fck", "brg_int", "scif_clk";
1262 dmas = <&dmac1 0x13>, <&dmac1 0x12>,
1263 <&dmac2 0x13>, <&dmac2 0x12>;
1264 dma-names = "tx", "rx", "tx", "rx";
1265 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1266 resets = <&cpg 310>;
1267 status = "disabled";
1268 };
1269 1417
1270 scif3: serial@e6c50000 { 1418 reg = <1>;
1271 compatible = "renesas,scif-r8a7795",
1272 "renesas,rcar-gen3-scif", "renesas,scif";
1273 reg = <0 0xe6c50000 0 64>;
1274 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1275 clocks = <&cpg CPG_MOD 204>,
1276 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
1277 <&scif_clk>;
1278 clock-names = "fck", "brg_int", "scif_clk";
1279 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
1280 dma-names = "tx", "rx";
1281 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1282 resets = <&cpg 204>;
1283 status = "disabled";
1284 };
1285 1419
1286 scif4: serial@e6c40000 { 1420 vin0csi20: endpoint@0 {
1287 compatible = "renesas,scif-r8a7795", 1421 reg = <0>;
1288 "renesas,rcar-gen3-scif", "renesas,scif"; 1422 remote-endpoint= <&csi20vin0>;
1289 reg = <0 0xe6c40000 0 64>; 1423 };
1290 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1424 vin0csi40: endpoint@2 {
1291 clocks = <&cpg CPG_MOD 203>, 1425 reg = <2>;
1292 <&cpg CPG_CORE R8A7795_CLK_S3D1>, 1426 remote-endpoint= <&csi40vin0>;
1293 <&scif_clk>; 1427 };
1294 clock-names = "fck", "brg_int", "scif_clk"; 1428 };
1295 dmas = <&dmac0 0x59>, <&dmac0 0x58>; 1429 };
1296 dma-names = "tx", "rx";
1297 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1298 resets = <&cpg 203>;
1299 status = "disabled";
1300 }; 1430 };
1301 1431
1302 scif5: serial@e6f30000 { 1432 vin1: video@e6ef1000 {
1303 compatible = "renesas,scif-r8a7795", 1433 compatible = "renesas,vin-r8a7795";
1304 "renesas,rcar-gen3-scif", "renesas,scif"; 1434 reg = <0 0xe6ef1000 0 0x1000>;
1305 reg = <0 0xe6f30000 0 64>; 1435 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
1306 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1436 clocks = <&cpg CPG_MOD 810>;
1307 clocks = <&cpg CPG_MOD 202>,
1308 <&cpg CPG_CORE R8A7795_CLK_S3D1>,
1309 <&scif_clk>;
1310 clock-names = "fck", "brg_int", "scif_clk";
1311 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
1312 <&dmac2 0x5b>, <&dmac2 0x5a>;
1313 dma-names = "tx", "rx", "tx", "rx";
1314 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1437 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1315 resets = <&cpg 202>; 1438 resets = <&cpg 810>;
1439 renesas,id = <1>;
1316 status = "disabled"; 1440 status = "disabled";
1317 };
1318 1441
1319 i2c_dvfs: i2c@e60b0000 { 1442 ports {
1320 #address-cells = <1>; 1443 #address-cells = <1>;
1321 #size-cells = <0>; 1444 #size-cells = <0>;
1322 compatible = "renesas,iic-r8a7795", 1445
1323 "renesas,rcar-gen3-iic", 1446 port@1 {
1324 "renesas,rmobile-iic"; 1447 #address-cells = <1>;
1325 reg = <0 0xe60b0000 0 0x425>; 1448 #size-cells = <0>;
1326 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 1449
1327 clocks = <&cpg CPG_MOD 926>; 1450 reg = <1>;
1328 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1451
1329 resets = <&cpg 926>; 1452 vin1csi20: endpoint@0 {
1330 dmas = <&dmac0 0x11>, <&dmac0 0x10>; 1453 reg = <0>;
1331 dma-names = "tx", "rx"; 1454 remote-endpoint= <&csi20vin1>;
1332 status = "disabled"; 1455 };
1456 vin1csi40: endpoint@2 {
1457 reg = <2>;
1458 remote-endpoint= <&csi40vin1>;
1459 };
1460 };
1461 };
1333 }; 1462 };
1334 1463
1335 i2c0: i2c@e6500000 { 1464 vin2: video@e6ef2000 {
1336 #address-cells = <1>; 1465 compatible = "renesas,vin-r8a7795";
1337 #size-cells = <0>; 1466 reg = <0 0xe6ef2000 0 0x1000>;
1338 compatible = "renesas,i2c-r8a7795", 1467 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1339 "renesas,rcar-gen3-i2c"; 1468 clocks = <&cpg CPG_MOD 809>;
1340 reg = <0 0xe6500000 0 0x40>;
1341 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
1342 clocks = <&cpg CPG_MOD 931>;
1343 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1469 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1344 resets = <&cpg 931>; 1470 resets = <&cpg 809>;
1345 dmas = <&dmac1 0x91>, <&dmac1 0x90>, 1471 renesas,id = <2>;
1346 <&dmac2 0x91>, <&dmac2 0x90>;
1347 dma-names = "tx", "rx", "tx", "rx";
1348 i2c-scl-internal-delay-ns = <110>;
1349 status = "disabled"; 1472 status = "disabled";
1473
1474 ports {
1475 #address-cells = <1>;
1476 #size-cells = <0>;
1477
1478 port@1 {
1479 #address-cells = <1>;
1480 #size-cells = <0>;
1481
1482 reg = <1>;
1483
1484 vin2csi20: endpoint@0 {
1485 reg = <0>;
1486 remote-endpoint= <&csi20vin2>;
1487 };
1488 vin2csi40: endpoint@2 {
1489 reg = <2>;
1490 remote-endpoint= <&csi40vin2>;
1491 };
1492 };
1493 };
1350 }; 1494 };
1351 1495
1352 i2c1: i2c@e6508000 { 1496 vin3: video@e6ef3000 {
1353 #address-cells = <1>; 1497 compatible = "renesas,vin-r8a7795";
1354 #size-cells = <0>; 1498 reg = <0 0xe6ef3000 0 0x1000>;
1355 compatible = "renesas,i2c-r8a7795", 1499 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
1356 "renesas,rcar-gen3-i2c"; 1500 clocks = <&cpg CPG_MOD 808>;
1357 reg = <0 0xe6508000 0 0x40>;
1358 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
1359 clocks = <&cpg CPG_MOD 930>;
1360 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1501 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1361 resets = <&cpg 930>; 1502 resets = <&cpg 808>;
1362 dmas = <&dmac1 0x93>, <&dmac1 0x92>, 1503 renesas,id = <3>;
1363 <&dmac2 0x93>, <&dmac2 0x92>;
1364 dma-names = "tx", "rx", "tx", "rx";
1365 i2c-scl-internal-delay-ns = <6>;
1366 status = "disabled"; 1504 status = "disabled";
1505
1506 ports {
1507 #address-cells = <1>;
1508 #size-cells = <0>;
1509
1510 port@1 {
1511 #address-cells = <1>;
1512 #size-cells = <0>;
1513
1514 reg = <1>;
1515
1516 vin3csi20: endpoint@0 {
1517 reg = <0>;
1518 remote-endpoint= <&csi20vin3>;
1519 };
1520 vin3csi40: endpoint@2 {
1521 reg = <2>;
1522 remote-endpoint= <&csi40vin3>;
1523 };
1524 };
1525 };
1367 }; 1526 };
1368 1527
1369 i2c2: i2c@e6510000 { 1528 vin4: video@e6ef4000 {
1370 #address-cells = <1>; 1529 compatible = "renesas,vin-r8a7795";
1371 #size-cells = <0>; 1530 reg = <0 0xe6ef4000 0 0x1000>;
1372 compatible = "renesas,i2c-r8a7795", 1531 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
1373 "renesas,rcar-gen3-i2c"; 1532 clocks = <&cpg CPG_MOD 807>;
1374 reg = <0 0xe6510000 0 0x40>;
1375 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
1376 clocks = <&cpg CPG_MOD 929>;
1377 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1533 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1378 resets = <&cpg 929>; 1534 resets = <&cpg 807>;
1379 dmas = <&dmac1 0x95>, <&dmac1 0x94>, 1535 renesas,id = <4>;
1380 <&dmac2 0x95>, <&dmac2 0x94>;
1381 dma-names = "tx", "rx", "tx", "rx";
1382 i2c-scl-internal-delay-ns = <6>;
1383 status = "disabled"; 1536 status = "disabled";
1537
1538 ports {
1539 #address-cells = <1>;
1540 #size-cells = <0>;
1541
1542 port@1 {
1543 #address-cells = <1>;
1544 #size-cells = <0>;
1545
1546 reg = <1>;
1547
1548 vin4csi20: endpoint@0 {
1549 reg = <0>;
1550 remote-endpoint= <&csi20vin4>;
1551 };
1552 vin4csi41: endpoint@3 {
1553 reg = <3>;
1554 remote-endpoint= <&csi41vin4>;
1555 };
1556 };
1557 };
1384 }; 1558 };
1385 1559
1386 i2c3: i2c@e66d0000 { 1560 vin5: video@e6ef5000 {
1387 #address-cells = <1>; 1561 compatible = "renesas,vin-r8a7795";
1388 #size-cells = <0>; 1562 reg = <0 0xe6ef5000 0 0x1000>;
1389 compatible = "renesas,i2c-r8a7795", 1563 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
1390 "renesas,rcar-gen3-i2c"; 1564 clocks = <&cpg CPG_MOD 806>;
1391 reg = <0 0xe66d0000 0 0x40>;
1392 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
1393 clocks = <&cpg CPG_MOD 928>;
1394 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1565 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1395 resets = <&cpg 928>; 1566 resets = <&cpg 806>;
1396 dmas = <&dmac0 0x97>, <&dmac0 0x96>; 1567 renesas,id = <5>;
1397 dma-names = "tx", "rx";
1398 i2c-scl-internal-delay-ns = <110>;
1399 status = "disabled"; 1568 status = "disabled";
1569
1570 ports {
1571 #address-cells = <1>;
1572 #size-cells = <0>;
1573
1574 port@1 {
1575 #address-cells = <1>;
1576 #size-cells = <0>;
1577
1578 reg = <1>;
1579
1580 vin5csi20: endpoint@0 {
1581 reg = <0>;
1582 remote-endpoint= <&csi20vin5>;
1583 };
1584 vin5csi41: endpoint@3 {
1585 reg = <3>;
1586 remote-endpoint= <&csi41vin5>;
1587 };
1588 };
1589 };
1400 }; 1590 };
1401 1591
1402 i2c4: i2c@e66d8000 { 1592 vin6: video@e6ef6000 {
1403 #address-cells = <1>; 1593 compatible = "renesas,vin-r8a7795";
1404 #size-cells = <0>; 1594 reg = <0 0xe6ef6000 0 0x1000>;
1405 compatible = "renesas,i2c-r8a7795", 1595 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
1406 "renesas,rcar-gen3-i2c"; 1596 clocks = <&cpg CPG_MOD 805>;
1407 reg = <0 0xe66d8000 0 0x40>;
1408 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1409 clocks = <&cpg CPG_MOD 927>;
1410 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1597 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1411 resets = <&cpg 927>; 1598 resets = <&cpg 805>;
1412 dmas = <&dmac0 0x99>, <&dmac0 0x98>; 1599 renesas,id = <6>;
1413 dma-names = "tx", "rx";
1414 i2c-scl-internal-delay-ns = <110>;
1415 status = "disabled"; 1600 status = "disabled";
1601
1602 ports {
1603 #address-cells = <1>;
1604 #size-cells = <0>;
1605
1606 port@1 {
1607 #address-cells = <1>;
1608 #size-cells = <0>;
1609
1610 reg = <1>;
1611
1612 vin6csi20: endpoint@0 {
1613 reg = <0>;
1614 remote-endpoint= <&csi20vin6>;
1615 };
1616 vin6csi41: endpoint@3 {
1617 reg = <3>;
1618 remote-endpoint= <&csi41vin6>;
1619 };
1620 };
1621 };
1416 }; 1622 };
1417 1623
1418 i2c5: i2c@e66e0000 { 1624 vin7: video@e6ef7000 {
1419 #address-cells = <1>; 1625 compatible = "renesas,vin-r8a7795";
1420 #size-cells = <0>; 1626 reg = <0 0xe6ef7000 0 0x1000>;
1421 compatible = "renesas,i2c-r8a7795", 1627 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
1422 "renesas,rcar-gen3-i2c"; 1628 clocks = <&cpg CPG_MOD 804>;
1423 reg = <0 0xe66e0000 0 0x40>;
1424 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1425 clocks = <&cpg CPG_MOD 919>;
1426 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1629 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1427 resets = <&cpg 919>; 1630 resets = <&cpg 804>;
1428 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; 1631 renesas,id = <7>;
1429 dma-names = "tx", "rx";
1430 i2c-scl-internal-delay-ns = <110>;
1431 status = "disabled"; 1632 status = "disabled";
1633
1634 ports {
1635 #address-cells = <1>;
1636 #size-cells = <0>;
1637
1638 port@1 {
1639 #address-cells = <1>;
1640 #size-cells = <0>;
1641
1642 reg = <1>;
1643
1644 vin7csi20: endpoint@0 {
1645 reg = <0>;
1646 remote-endpoint= <&csi20vin7>;
1647 };
1648 vin7csi41: endpoint@3 {
1649 reg = <3>;
1650 remote-endpoint= <&csi41vin7>;
1651 };
1652 };
1653 };
1432 }; 1654 };
1433 1655
1434 i2c6: i2c@e66e8000 { 1656 drif00: rif@e6f40000 {
1435 #address-cells = <1>; 1657 compatible = "renesas,r8a7795-drif",
1436 #size-cells = <0>; 1658 "renesas,rcar-gen3-drif";
1437 compatible = "renesas,i2c-r8a7795", 1659 reg = <0 0xe6f40000 0 0x64>;
1438 "renesas,rcar-gen3-i2c"; 1660 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1439 reg = <0 0xe66e8000 0 0x40>; 1661 clocks = <&cpg CPG_MOD 515>;
1440 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1662 clock-names = "fck";
1441 clocks = <&cpg CPG_MOD 918>; 1663 dmas = <&dmac1 0x20>, <&dmac2 0x20>;
1664 dma-names = "rx", "rx";
1442 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1665 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1443 resets = <&cpg 918>; 1666 resets = <&cpg 515>;
1444 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; 1667 renesas,bonding = <&drif01>;
1445 dma-names = "tx", "rx";
1446 i2c-scl-internal-delay-ns = <6>;
1447 status = "disabled"; 1668 status = "disabled";
1448 }; 1669 };
1449 1670
1450 pwm0: pwm@e6e30000 { 1671 drif01: rif@e6f50000 {
1451 compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; 1672 compatible = "renesas,r8a7795-drif",
1452 reg = <0 0xe6e30000 0 0x8>; 1673 "renesas,rcar-gen3-drif";
1453 clocks = <&cpg CPG_MOD 523>; 1674 reg = <0 0xe6f50000 0 0x64>;
1675 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1676 clocks = <&cpg CPG_MOD 514>;
1677 clock-names = "fck";
1678 dmas = <&dmac1 0x22>, <&dmac2 0x22>;
1679 dma-names = "rx", "rx";
1454 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1680 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1455 resets = <&cpg 523>; 1681 resets = <&cpg 514>;
1456 #pwm-cells = <2>; 1682 renesas,bonding = <&drif00>;
1457 status = "disabled"; 1683 status = "disabled";
1458 }; 1684 };
1459 1685
1460 pwm1: pwm@e6e31000 { 1686 drif10: rif@e6f60000 {
1461 compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; 1687 compatible = "renesas,r8a7795-drif",
1462 reg = <0 0xe6e31000 0 0x8>; 1688 "renesas,rcar-gen3-drif";
1463 clocks = <&cpg CPG_MOD 523>; 1689 reg = <0 0xe6f60000 0 0x64>;
1690 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1691 clocks = <&cpg CPG_MOD 513>;
1692 clock-names = "fck";
1693 dmas = <&dmac1 0x24>, <&dmac2 0x24>;
1694 dma-names = "rx", "rx";
1464 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1695 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1465 resets = <&cpg 523>; 1696 resets = <&cpg 513>;
1466 #pwm-cells = <2>; 1697 renesas,bonding = <&drif11>;
1467 status = "disabled"; 1698 status = "disabled";
1468 }; 1699 };
1469 1700
1470 pwm2: pwm@e6e32000 { 1701 drif11: rif@e6f70000 {
1471 compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; 1702 compatible = "renesas,r8a7795-drif",
1472 reg = <0 0xe6e32000 0 0x8>; 1703 "renesas,rcar-gen3-drif";
1473 clocks = <&cpg CPG_MOD 523>; 1704 reg = <0 0xe6f70000 0 0x64>;
1705 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1706 clocks = <&cpg CPG_MOD 512>;
1707 clock-names = "fck";
1708 dmas = <&dmac1 0x26>, <&dmac2 0x26>;
1709 dma-names = "rx", "rx";
1474 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1710 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1475 resets = <&cpg 523>; 1711 resets = <&cpg 512>;
1476 #pwm-cells = <2>; 1712 renesas,bonding = <&drif10>;
1477 status = "disabled"; 1713 status = "disabled";
1478 }; 1714 };
1479 1715
1480 pwm3: pwm@e6e33000 { 1716 drif20: rif@e6f80000 {
1481 compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; 1717 compatible = "renesas,r8a7795-drif",
1482 reg = <0 0xe6e33000 0 0x8>; 1718 "renesas,rcar-gen3-drif";
1483 clocks = <&cpg CPG_MOD 523>; 1719 reg = <0 0xe6f80000 0 0x64>;
1720 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1721 clocks = <&cpg CPG_MOD 511>;
1722 clock-names = "fck";
1723 dmas = <&dmac1 0x28>, <&dmac2 0x28>;
1724 dma-names = "rx", "rx";
1484 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1725 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1485 resets = <&cpg 523>; 1726 resets = <&cpg 511>;
1486 #pwm-cells = <2>; 1727 renesas,bonding = <&drif21>;
1487 status = "disabled"; 1728 status = "disabled";
1488 }; 1729 };
1489 1730
1490 pwm4: pwm@e6e34000 { 1731 drif21: rif@e6f90000 {
1491 compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; 1732 compatible = "renesas,r8a7795-drif",
1492 reg = <0 0xe6e34000 0 0x8>; 1733 "renesas,rcar-gen3-drif";
1493 clocks = <&cpg CPG_MOD 523>; 1734 reg = <0 0xe6f90000 0 0x64>;
1735 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1736 clocks = <&cpg CPG_MOD 510>;
1737 clock-names = "fck";
1738 dmas = <&dmac1 0x2a>, <&dmac2 0x2a>;
1739 dma-names = "rx", "rx";
1494 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1740 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1495 resets = <&cpg 523>; 1741 resets = <&cpg 510>;
1496 #pwm-cells = <2>; 1742 renesas,bonding = <&drif20>;
1497 status = "disabled"; 1743 status = "disabled";
1498 }; 1744 };
1499 1745
1500 pwm5: pwm@e6e35000 { 1746 drif30: rif@e6fa0000 {
1501 compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; 1747 compatible = "renesas,r8a7795-drif",
1502 reg = <0 0xe6e35000 0 0x8>; 1748 "renesas,rcar-gen3-drif";
1503 clocks = <&cpg CPG_MOD 523>; 1749 reg = <0 0xe6fa0000 0 0x64>;
1750 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1751 clocks = <&cpg CPG_MOD 509>;
1752 clock-names = "fck";
1753 dmas = <&dmac1 0x2c>, <&dmac2 0x2c>;
1754 dma-names = "rx", "rx";
1504 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1755 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1505 resets = <&cpg 523>; 1756 resets = <&cpg 509>;
1506 #pwm-cells = <2>; 1757 renesas,bonding = <&drif31>;
1507 status = "disabled"; 1758 status = "disabled";
1508 }; 1759 };
1509 1760
1510 pwm6: pwm@e6e36000 { 1761 drif31: rif@e6fb0000 {
1511 compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; 1762 compatible = "renesas,r8a7795-drif",
1512 reg = <0 0xe6e36000 0 0x8>; 1763 "renesas,rcar-gen3-drif";
1513 clocks = <&cpg CPG_MOD 523>; 1764 reg = <0 0xe6fb0000 0 0x64>;
1765 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1766 clocks = <&cpg CPG_MOD 508>;
1767 clock-names = "fck";
1768 dmas = <&dmac1 0x2e>, <&dmac2 0x2e>;
1769 dma-names = "rx", "rx";
1514 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1770 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1515 resets = <&cpg 523>; 1771 resets = <&cpg 508>;
1516 #pwm-cells = <2>; 1772 renesas,bonding = <&drif30>;
1517 status = "disabled"; 1773 status = "disabled";
1518 }; 1774 };
1519 1775
@@ -1711,31 +1967,104 @@
1711 dma-names = "rx", "tx", "rxu", "txu"; 1967 dma-names = "rx", "tx", "rxu", "txu";
1712 }; 1968 };
1713 }; 1969 };
1970
1971 ports {
1972 #address-cells = <1>;
1973 #size-cells = <0>;
1974 port@0 {
1975 reg = <0>;
1976 };
1977 port@1 {
1978 reg = <1>;
1979 };
1980 port@2 {
1981 reg = <2>;
1982 };
1983 };
1714 }; 1984 };
1715 1985
1716 sata: sata@ee300000 { 1986 audma0: dma-controller@ec700000 {
1717 compatible = "renesas,sata-r8a7795", 1987 compatible = "renesas,dmac-r8a7795",
1718 "renesas,rcar-gen3-sata"; 1988 "renesas,rcar-dmac";
1719 reg = <0 0xee300000 0 0x200000>; 1989 reg = <0 0xec700000 0 0x10000>;
1720 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 1990 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH
1721 clocks = <&cpg CPG_MOD 815>; 1991 GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
1992 GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
1993 GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
1994 GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
1995 GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
1996 GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
1997 GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
1998 GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
1999 GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
2000 GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
2001 GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
2002 GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
2003 GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH
2004 GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
2005 GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
2006 GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
2007 interrupt-names = "error",
2008 "ch0", "ch1", "ch2", "ch3",
2009 "ch4", "ch5", "ch6", "ch7",
2010 "ch8", "ch9", "ch10", "ch11",
2011 "ch12", "ch13", "ch14", "ch15";
2012 clocks = <&cpg CPG_MOD 502>;
2013 clock-names = "fck";
1722 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2014 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1723 resets = <&cpg 815>; 2015 resets = <&cpg 502>;
1724 status = "disabled"; 2016 #dma-cells = <1>;
1725 iommus = <&ipmmu_hc 2>; 2017 dma-channels = <16>;
2018 iommus = <&ipmmu_mp0 0>, <&ipmmu_mp0 1>,
2019 <&ipmmu_mp0 2>, <&ipmmu_mp0 3>,
2020 <&ipmmu_mp0 4>, <&ipmmu_mp0 5>,
2021 <&ipmmu_mp0 6>, <&ipmmu_mp0 7>,
2022 <&ipmmu_mp0 8>, <&ipmmu_mp0 9>,
2023 <&ipmmu_mp0 10>, <&ipmmu_mp0 11>,
2024 <&ipmmu_mp0 12>, <&ipmmu_mp0 13>,
2025 <&ipmmu_mp0 14>, <&ipmmu_mp0 15>;
1726 }; 2026 };
1727 2027
1728 usb3_phy0: usb-phy@e65ee000 { 2028 audma1: dma-controller@ec720000 {
1729 compatible = "renesas,r8a7795-usb3-phy", 2029 compatible = "renesas,dmac-r8a7795",
1730 "renesas,rcar-gen3-usb3-phy"; 2030 "renesas,rcar-dmac";
1731 reg = <0 0xe65ee000 0 0x90>; 2031 reg = <0 0xec720000 0 0x10000>;
1732 clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, 2032 interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH
1733 <&usb_extal_clk>; 2033 GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
1734 clock-names = "usb3-if", "usb3s_clk", "usb_extal"; 2034 GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
2035 GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
2036 GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
2037 GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
2038 GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
2039 GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
2040 GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
2041 GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
2042 GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH
2043 GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
2044 GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
2045 GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH
2046 GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH
2047 GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH
2048 GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
2049 interrupt-names = "error",
2050 "ch0", "ch1", "ch2", "ch3",
2051 "ch4", "ch5", "ch6", "ch7",
2052 "ch8", "ch9", "ch10", "ch11",
2053 "ch12", "ch13", "ch14", "ch15";
2054 clocks = <&cpg CPG_MOD 501>;
2055 clock-names = "fck";
1735 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2056 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1736 resets = <&cpg 328>; 2057 resets = <&cpg 501>;
1737 #phy-cells = <0>; 2058 #dma-cells = <1>;
1738 status = "disabled"; 2059 dma-channels = <16>;
2060 iommus = <&ipmmu_mp0 16>, <&ipmmu_mp0 17>,
2061 <&ipmmu_mp0 18>, <&ipmmu_mp0 19>,
2062 <&ipmmu_mp0 20>, <&ipmmu_mp0 21>,
2063 <&ipmmu_mp0 22>, <&ipmmu_mp0 23>,
2064 <&ipmmu_mp0 24>, <&ipmmu_mp0 25>,
2065 <&ipmmu_mp0 26>, <&ipmmu_mp0 27>,
2066 <&ipmmu_mp0 28>, <&ipmmu_mp0 29>,
2067 <&ipmmu_mp0 30>, <&ipmmu_mp0 31>;
1739 }; 2068 };
1740 2069
1741 xhci0: usb@ee000000 { 2070 xhci0: usb@ee000000 {
@@ -1759,153 +2088,51 @@
1759 status = "disabled"; 2088 status = "disabled";
1760 }; 2089 };
1761 2090
1762 usb_dmac0: dma-controller@e65a0000 { 2091 ohci0: usb@ee080000 {
1763 compatible = "renesas,r8a7795-usb-dmac", 2092 compatible = "generic-ohci";
1764 "renesas,usb-dmac"; 2093 reg = <0 0xee080000 0 0x100>;
1765 reg = <0 0xe65a0000 0 0x100>;
1766 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
1767 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
1768 interrupt-names = "ch0", "ch1";
1769 clocks = <&cpg CPG_MOD 330>;
1770 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1771 resets = <&cpg 330>;
1772 #dma-cells = <1>;
1773 dma-channels = <2>;
1774 };
1775
1776 usb_dmac1: dma-controller@e65b0000 {
1777 compatible = "renesas,r8a7795-usb-dmac",
1778 "renesas,usb-dmac";
1779 reg = <0 0xe65b0000 0 0x100>;
1780 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
1781 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
1782 interrupt-names = "ch0", "ch1";
1783 clocks = <&cpg CPG_MOD 331>;
1784 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1785 resets = <&cpg 331>;
1786 #dma-cells = <1>;
1787 dma-channels = <2>;
1788 };
1789
1790 usb_dmac2: dma-controller@e6460000 {
1791 compatible = "renesas,r8a7795-usb-dmac",
1792 "renesas,usb-dmac";
1793 reg = <0 0xe6460000 0 0x100>;
1794 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH
1795 GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
1796 interrupt-names = "ch0", "ch1";
1797 clocks = <&cpg CPG_MOD 326>;
1798 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1799 resets = <&cpg 326>;
1800 #dma-cells = <1>;
1801 dma-channels = <2>;
1802 };
1803
1804 usb_dmac3: dma-controller@e6470000 {
1805 compatible = "renesas,r8a7795-usb-dmac",
1806 "renesas,usb-dmac";
1807 reg = <0 0xe6470000 0 0x100>;
1808 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH
1809 GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1810 interrupt-names = "ch0", "ch1";
1811 clocks = <&cpg CPG_MOD 329>;
1812 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1813 resets = <&cpg 329>;
1814 #dma-cells = <1>;
1815 dma-channels = <2>;
1816 };
1817
1818 sdhi0: sd@ee100000 {
1819 compatible = "renesas,sdhi-r8a7795",
1820 "renesas,rcar-gen3-sdhi";
1821 reg = <0 0xee100000 0 0x2000>;
1822 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
1823 clocks = <&cpg CPG_MOD 314>;
1824 max-frequency = <200000000>;
1825 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1826 resets = <&cpg 314>;
1827 status = "disabled";
1828 };
1829
1830 sdhi1: sd@ee120000 {
1831 compatible = "renesas,sdhi-r8a7795",
1832 "renesas,rcar-gen3-sdhi";
1833 reg = <0 0xee120000 0 0x2000>;
1834 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
1835 clocks = <&cpg CPG_MOD 313>;
1836 max-frequency = <200000000>;
1837 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1838 resets = <&cpg 313>;
1839 status = "disabled";
1840 };
1841
1842 sdhi2: sd@ee140000 {
1843 compatible = "renesas,sdhi-r8a7795",
1844 "renesas,rcar-gen3-sdhi";
1845 reg = <0 0xee140000 0 0x2000>;
1846 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
1847 clocks = <&cpg CPG_MOD 312>;
1848 max-frequency = <200000000>;
1849 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1850 resets = <&cpg 312>;
1851 status = "disabled";
1852 };
1853
1854 sdhi3: sd@ee160000 {
1855 compatible = "renesas,sdhi-r8a7795",
1856 "renesas,rcar-gen3-sdhi";
1857 reg = <0 0xee160000 0 0x2000>;
1858 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
1859 clocks = <&cpg CPG_MOD 311>;
1860 max-frequency = <200000000>;
1861 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1862 resets = <&cpg 311>;
1863 status = "disabled";
1864 };
1865
1866 usb2_phy0: usb-phy@ee080200 {
1867 compatible = "renesas,usb2-phy-r8a7795",
1868 "renesas,rcar-gen3-usb2-phy";
1869 reg = <0 0xee080200 0 0x700>;
1870 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 2094 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1871 clocks = <&cpg CPG_MOD 703>; 2095 clocks = <&cpg CPG_MOD 703>;
2096 phys = <&usb2_phy0>;
2097 phy-names = "usb";
1872 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2098 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1873 resets = <&cpg 703>; 2099 resets = <&cpg 703>;
1874 #phy-cells = <0>;
1875 status = "disabled"; 2100 status = "disabled";
1876 }; 2101 };
1877 2102
1878 usb2_phy1: usb-phy@ee0a0200 { 2103 ohci1: usb@ee0a0000 {
1879 compatible = "renesas,usb2-phy-r8a7795", 2104 compatible = "generic-ohci";
1880 "renesas,rcar-gen3-usb2-phy"; 2105 reg = <0 0xee0a0000 0 0x100>;
1881 reg = <0 0xee0a0200 0 0x700>; 2106 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1882 clocks = <&cpg CPG_MOD 702>; 2107 clocks = <&cpg CPG_MOD 702>;
2108 phys = <&usb2_phy1>;
2109 phy-names = "usb";
1883 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2110 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1884 resets = <&cpg 702>; 2111 resets = <&cpg 702>;
1885 #phy-cells = <0>;
1886 status = "disabled"; 2112 status = "disabled";
1887 }; 2113 };
1888 2114
1889 usb2_phy2: usb-phy@ee0c0200 { 2115 ohci2: usb@ee0c0000 {
1890 compatible = "renesas,usb2-phy-r8a7795", 2116 compatible = "generic-ohci";
1891 "renesas,rcar-gen3-usb2-phy"; 2117 reg = <0 0xee0c0000 0 0x100>;
1892 reg = <0 0xee0c0200 0 0x700>; 2118 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
1893 clocks = <&cpg CPG_MOD 701>; 2119 clocks = <&cpg CPG_MOD 701>;
2120 phys = <&usb2_phy2>;
2121 phy-names = "usb";
1894 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2122 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1895 resets = <&cpg 701>; 2123 resets = <&cpg 701>;
1896 #phy-cells = <0>;
1897 status = "disabled"; 2124 status = "disabled";
1898 }; 2125 };
1899 2126
1900 usb2_phy3: usb-phy@ee0e0200 { 2127 ohci3: usb@ee0e0000 {
1901 compatible = "renesas,usb2-phy-r8a7795", 2128 compatible = "generic-ohci";
1902 "renesas,rcar-gen3-usb2-phy"; 2129 reg = <0 0xee0e0000 0 0x100>;
1903 reg = <0 0xee0e0200 0 0x700>;
1904 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 2130 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
1905 clocks = <&cpg CPG_MOD 700>; 2131 clocks = <&cpg CPG_MOD 700>;
2132 phys = <&usb2_phy3>;
2133 phy-names = "usb";
1906 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2134 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1907 resets = <&cpg 700>; 2135 resets = <&cpg 700>;
1908 #phy-cells = <0>;
1909 status = "disabled"; 2136 status = "disabled";
1910 }; 2137 };
1911 2138
@@ -1961,88 +2188,129 @@
1961 status = "disabled"; 2188 status = "disabled";
1962 }; 2189 };
1963 2190
1964 ohci0: usb@ee080000 { 2191 usb2_phy0: usb-phy@ee080200 {
1965 compatible = "generic-ohci"; 2192 compatible = "renesas,usb2-phy-r8a7795",
1966 reg = <0 0xee080000 0 0x100>; 2193 "renesas,rcar-gen3-usb2-phy";
2194 reg = <0 0xee080200 0 0x700>;
1967 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 2195 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1968 clocks = <&cpg CPG_MOD 703>; 2196 clocks = <&cpg CPG_MOD 703>;
1969 phys = <&usb2_phy0>;
1970 phy-names = "usb";
1971 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2197 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1972 resets = <&cpg 703>; 2198 resets = <&cpg 703>;
2199 #phy-cells = <0>;
1973 status = "disabled"; 2200 status = "disabled";
1974 }; 2201 };
1975 2202
1976 ohci1: usb@ee0a0000 { 2203 usb2_phy1: usb-phy@ee0a0200 {
1977 compatible = "generic-ohci"; 2204 compatible = "renesas,usb2-phy-r8a7795",
1978 reg = <0 0xee0a0000 0 0x100>; 2205 "renesas,rcar-gen3-usb2-phy";
1979 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 2206 reg = <0 0xee0a0200 0 0x700>;
1980 clocks = <&cpg CPG_MOD 702>; 2207 clocks = <&cpg CPG_MOD 702>;
1981 phys = <&usb2_phy1>;
1982 phy-names = "usb";
1983 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2208 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1984 resets = <&cpg 702>; 2209 resets = <&cpg 702>;
2210 #phy-cells = <0>;
1985 status = "disabled"; 2211 status = "disabled";
1986 }; 2212 };
1987 2213
1988 ohci2: usb@ee0c0000 { 2214 usb2_phy2: usb-phy@ee0c0200 {
1989 compatible = "generic-ohci"; 2215 compatible = "renesas,usb2-phy-r8a7795",
1990 reg = <0 0xee0c0000 0 0x100>; 2216 "renesas,rcar-gen3-usb2-phy";
1991 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 2217 reg = <0 0xee0c0200 0 0x700>;
1992 clocks = <&cpg CPG_MOD 701>; 2218 clocks = <&cpg CPG_MOD 701>;
1993 phys = <&usb2_phy2>;
1994 phy-names = "usb";
1995 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2219 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1996 resets = <&cpg 701>; 2220 resets = <&cpg 701>;
2221 #phy-cells = <0>;
1997 status = "disabled"; 2222 status = "disabled";
1998 }; 2223 };
1999 2224
2000 ohci3: usb@ee0e0000 { 2225 usb2_phy3: usb-phy@ee0e0200 {
2001 compatible = "generic-ohci"; 2226 compatible = "renesas,usb2-phy-r8a7795",
2002 reg = <0 0xee0e0000 0 0x100>; 2227 "renesas,rcar-gen3-usb2-phy";
2228 reg = <0 0xee0e0200 0 0x700>;
2003 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 2229 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
2004 clocks = <&cpg CPG_MOD 700>; 2230 clocks = <&cpg CPG_MOD 700>;
2005 phys = <&usb2_phy3>;
2006 phy-names = "usb";
2007 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2231 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
2008 resets = <&cpg 700>; 2232 resets = <&cpg 700>;
2233 #phy-cells = <0>;
2009 status = "disabled"; 2234 status = "disabled";
2010 }; 2235 };
2011 2236
2012 hsusb: usb@e6590000 { 2237 sdhi0: sd@ee100000 {
2013 compatible = "renesas,usbhs-r8a7795", 2238 compatible = "renesas,sdhi-r8a7795",
2014 "renesas,rcar-gen3-usbhs"; 2239 "renesas,rcar-gen3-sdhi";
2015 reg = <0 0xe6590000 0 0x100>; 2240 reg = <0 0xee100000 0 0x2000>;
2016 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 2241 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
2017 clocks = <&cpg CPG_MOD 704>; 2242 clocks = <&cpg CPG_MOD 314>;
2018 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, 2243 max-frequency = <200000000>;
2019 <&usb_dmac1 0>, <&usb_dmac1 1>;
2020 dma-names = "ch0", "ch1", "ch2", "ch3";
2021 renesas,buswait = <11>;
2022 phys = <&usb2_phy0>;
2023 phy-names = "usb";
2024 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2244 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
2025 resets = <&cpg 704>; 2245 resets = <&cpg 314>;
2026 status = "disabled"; 2246 status = "disabled";
2027 }; 2247 };
2028 2248
2029 hsusb3: usb@e659c000 { 2249 sdhi1: sd@ee120000 {
2030 compatible = "renesas,usbhs-r8a7795", 2250 compatible = "renesas,sdhi-r8a7795",
2031 "renesas,rcar-gen3-usbhs"; 2251 "renesas,rcar-gen3-sdhi";
2032 reg = <0 0xe659c000 0 0x100>; 2252 reg = <0 0xee120000 0 0x2000>;
2033 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 2253 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
2034 clocks = <&cpg CPG_MOD 705>; 2254 clocks = <&cpg CPG_MOD 313>;
2035 dmas = <&usb_dmac2 0>, <&usb_dmac2 1>, 2255 max-frequency = <200000000>;
2036 <&usb_dmac3 0>, <&usb_dmac3 1>;
2037 dma-names = "ch0", "ch1", "ch2", "ch3";
2038 renesas,buswait = <11>;
2039 phys = <&usb2_phy3>;
2040 phy-names = "usb";
2041 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2256 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
2042 resets = <&cpg 705>; 2257 resets = <&cpg 313>;
2258 status = "disabled";
2259 };
2260
2261 sdhi2: sd@ee140000 {
2262 compatible = "renesas,sdhi-r8a7795",
2263 "renesas,rcar-gen3-sdhi";
2264 reg = <0 0xee140000 0 0x2000>;
2265 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
2266 clocks = <&cpg CPG_MOD 312>;
2267 max-frequency = <200000000>;
2268 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
2269 resets = <&cpg 312>;
2270 status = "disabled";
2271 };
2272
2273 sdhi3: sd@ee160000 {
2274 compatible = "renesas,sdhi-r8a7795",
2275 "renesas,rcar-gen3-sdhi";
2276 reg = <0 0xee160000 0 0x2000>;
2277 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
2278 clocks = <&cpg CPG_MOD 311>;
2279 max-frequency = <200000000>;
2280 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
2281 resets = <&cpg 311>;
2043 status = "disabled"; 2282 status = "disabled";
2044 }; 2283 };
2045 2284
2285 sata: sata@ee300000 {
2286 compatible = "renesas,sata-r8a7795",
2287 "renesas,rcar-gen3-sata";
2288 reg = <0 0xee300000 0 0x200000>;
2289 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
2290 clocks = <&cpg CPG_MOD 815>;
2291 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
2292 resets = <&cpg 815>;
2293 status = "disabled";
2294 iommus = <&ipmmu_hc 2>;
2295 };
2296
2297 gic: interrupt-controller@f1010000 {
2298 compatible = "arm,gic-400";
2299 #interrupt-cells = <3>;
2300 #address-cells = <0>;
2301 interrupt-controller;
2302 reg = <0x0 0xf1010000 0 0x1000>,
2303 <0x0 0xf1020000 0 0x20000>,
2304 <0x0 0xf1040000 0 0x20000>,
2305 <0x0 0xf1060000 0 0x20000>;
2306 interrupts = <GIC_PPI 9
2307 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
2308 clocks = <&cpg CPG_MOD 408>;
2309 clock-names = "clk";
2310 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
2311 resets = <&cpg 408>;
2312 };
2313
2046 pciec0: pcie@fe000000 { 2314 pciec0: pcie@fe000000 {
2047 compatible = "renesas,pcie-r8a7795", 2315 compatible = "renesas,pcie-r8a7795",
2048 "renesas,pcie-rcar-gen3"; 2316 "renesas,pcie-rcar-gen3";
@@ -2137,24 +2405,24 @@
2137 resets = <&cpg 820>; 2405 resets = <&cpg 820>;
2138 }; 2406 };
2139 2407
2140 vspbc: vsp@fe920000 { 2408 fdp1@fe940000 {
2141 compatible = "renesas,vsp2"; 2409 compatible = "renesas,fdp1";
2142 reg = <0 0xfe920000 0 0x8000>; 2410 reg = <0 0xfe940000 0 0x2400>;
2143 interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>; 2411 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
2144 clocks = <&cpg CPG_MOD 624>; 2412 clocks = <&cpg CPG_MOD 119>;
2145 power-domains = <&sysc R8A7795_PD_A3VP>; 2413 power-domains = <&sysc R8A7795_PD_A3VP>;
2146 resets = <&cpg 624>; 2414 resets = <&cpg 119>;
2147 2415 renesas,fcp = <&fcpf0>;
2148 renesas,fcp = <&fcpvb1>;
2149 }; 2416 };
2150 2417
2151 fcpvb1: fcp@fe92f000 { 2418 fdp1@fe944000 {
2152 compatible = "renesas,fcpv"; 2419 compatible = "renesas,fdp1";
2153 reg = <0 0xfe92f000 0 0x200>; 2420 reg = <0 0xfe944000 0 0x2400>;
2154 clocks = <&cpg CPG_MOD 606>; 2421 interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
2422 clocks = <&cpg CPG_MOD 118>;
2155 power-domains = <&sysc R8A7795_PD_A3VP>; 2423 power-domains = <&sysc R8A7795_PD_A3VP>;
2156 resets = <&cpg 606>; 2424 resets = <&cpg 118>;
2157 iommus = <&ipmmu_vp1 7>; 2425 renesas,fcp = <&fcpf1>;
2158 }; 2426 };
2159 2427
2160 fcpf0: fcp@fe950000 { 2428 fcpf0: fcp@fe950000 {
@@ -2175,17 +2443,6 @@
2175 iommus = <&ipmmu_vp1 1>; 2443 iommus = <&ipmmu_vp1 1>;
2176 }; 2444 };
2177 2445
2178 vspbd: vsp@fe960000 {
2179 compatible = "renesas,vsp2";
2180 reg = <0 0xfe960000 0 0x8000>;
2181 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
2182 clocks = <&cpg CPG_MOD 626>;
2183 power-domains = <&sysc R8A7795_PD_A3VP>;
2184 resets = <&cpg 626>;
2185
2186 renesas,fcp = <&fcpvb0>;
2187 };
2188
2189 fcpvb0: fcp@fe96f000 { 2446 fcpvb0: fcp@fe96f000 {
2190 compatible = "renesas,fcpv"; 2447 compatible = "renesas,fcpv";
2191 reg = <0 0xfe96f000 0 0x200>; 2448 reg = <0 0xfe96f000 0 0x200>;
@@ -2195,15 +2452,13 @@
2195 iommus = <&ipmmu_vp0 5>; 2452 iommus = <&ipmmu_vp0 5>;
2196 }; 2453 };
2197 2454
2198 vspi0: vsp@fe9a0000 { 2455 fcpvb1: fcp@fe92f000 {
2199 compatible = "renesas,vsp2"; 2456 compatible = "renesas,fcpv";
2200 reg = <0 0xfe9a0000 0 0x8000>; 2457 reg = <0 0xfe92f000 0 0x200>;
2201 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>; 2458 clocks = <&cpg CPG_MOD 606>;
2202 clocks = <&cpg CPG_MOD 631>;
2203 power-domains = <&sysc R8A7795_PD_A3VP>; 2459 power-domains = <&sysc R8A7795_PD_A3VP>;
2204 resets = <&cpg 631>; 2460 resets = <&cpg 606>;
2205 2461 iommus = <&ipmmu_vp1 7>;
2206 renesas,fcp = <&fcpvi0>;
2207 }; 2462 };
2208 2463
2209 fcpvi0: fcp@fe9af000 { 2464 fcpvi0: fcp@fe9af000 {
@@ -2215,17 +2470,6 @@
2215 iommus = <&ipmmu_vp0 8>; 2470 iommus = <&ipmmu_vp0 8>;
2216 }; 2471 };
2217 2472
2218 vspi1: vsp@fe9b0000 {
2219 compatible = "renesas,vsp2";
2220 reg = <0 0xfe9b0000 0 0x8000>;
2221 interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
2222 clocks = <&cpg CPG_MOD 630>;
2223 power-domains = <&sysc R8A7795_PD_A3VP>;
2224 resets = <&cpg 630>;
2225
2226 renesas,fcp = <&fcpvi1>;
2227 };
2228
2229 fcpvi1: fcp@fe9bf000 { 2473 fcpvi1: fcp@fe9bf000 {
2230 compatible = "renesas,fcpv"; 2474 compatible = "renesas,fcpv";
2231 reg = <0 0xfe9bf000 0 0x200>; 2475 reg = <0 0xfe9bf000 0 0x200>;
@@ -2235,6 +2479,55 @@
2235 iommus = <&ipmmu_vp1 9>; 2479 iommus = <&ipmmu_vp1 9>;
2236 }; 2480 };
2237 2481
2482 fcpvd0: fcp@fea27000 {
2483 compatible = "renesas,fcpv";
2484 reg = <0 0xfea27000 0 0x200>;
2485 clocks = <&cpg CPG_MOD 603>;
2486 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
2487 resets = <&cpg 603>;
2488 iommus = <&ipmmu_vi0 8>;
2489 };
2490
2491 fcpvd1: fcp@fea2f000 {
2492 compatible = "renesas,fcpv";
2493 reg = <0 0xfea2f000 0 0x200>;
2494 clocks = <&cpg CPG_MOD 602>;
2495 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
2496 resets = <&cpg 602>;
2497 iommus = <&ipmmu_vi0 9>;
2498 };
2499
2500 fcpvd2: fcp@fea37000 {
2501 compatible = "renesas,fcpv";
2502 reg = <0 0xfea37000 0 0x200>;
2503 clocks = <&cpg CPG_MOD 601>;
2504 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
2505 resets = <&cpg 601>;
2506 iommus = <&ipmmu_vi1 10>;
2507 };
2508
2509 vspbd: vsp@fe960000 {
2510 compatible = "renesas,vsp2";
2511 reg = <0 0xfe960000 0 0x8000>;
2512 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
2513 clocks = <&cpg CPG_MOD 626>;
2514 power-domains = <&sysc R8A7795_PD_A3VP>;
2515 resets = <&cpg 626>;
2516
2517 renesas,fcp = <&fcpvb0>;
2518 };
2519
2520 vspbc: vsp@fe920000 {
2521 compatible = "renesas,vsp2";
2522 reg = <0 0xfe920000 0 0x8000>;
2523 interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;
2524 clocks = <&cpg CPG_MOD 624>;
2525 power-domains = <&sysc R8A7795_PD_A3VP>;
2526 resets = <&cpg 624>;
2527
2528 renesas,fcp = <&fcpvb1>;
2529 };
2530
2238 vspd0: vsp@fea20000 { 2531 vspd0: vsp@fea20000 {
2239 compatible = "renesas,vsp2"; 2532 compatible = "renesas,vsp2";
2240 reg = <0 0xfea20000 0 0x8000>; 2533 reg = <0 0xfea20000 0 0x8000>;
@@ -2246,15 +2539,6 @@
2246 renesas,fcp = <&fcpvd0>; 2539 renesas,fcp = <&fcpvd0>;
2247 }; 2540 };
2248 2541
2249 fcpvd0: fcp@fea27000 {
2250 compatible = "renesas,fcpv";
2251 reg = <0 0xfea27000 0 0x200>;
2252 clocks = <&cpg CPG_MOD 603>;
2253 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
2254 resets = <&cpg 603>;
2255 iommus = <&ipmmu_vi0 8>;
2256 };
2257
2258 vspd1: vsp@fea28000 { 2542 vspd1: vsp@fea28000 {
2259 compatible = "renesas,vsp2"; 2543 compatible = "renesas,vsp2";
2260 reg = <0 0xfea28000 0 0x8000>; 2544 reg = <0 0xfea28000 0 0x8000>;
@@ -2266,15 +2550,6 @@
2266 renesas,fcp = <&fcpvd1>; 2550 renesas,fcp = <&fcpvd1>;
2267 }; 2551 };
2268 2552
2269 fcpvd1: fcp@fea2f000 {
2270 compatible = "renesas,fcpv";
2271 reg = <0 0xfea2f000 0 0x200>;
2272 clocks = <&cpg CPG_MOD 602>;
2273 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
2274 resets = <&cpg 602>;
2275 iommus = <&ipmmu_vi0 9>;
2276 };
2277
2278 vspd2: vsp@fea30000 { 2553 vspd2: vsp@fea30000 {
2279 compatible = "renesas,vsp2"; 2554 compatible = "renesas,vsp2";
2280 reg = <0 0xfea30000 0 0x8000>; 2555 reg = <0 0xfea30000 0 0x8000>;
@@ -2286,33 +2561,159 @@
2286 renesas,fcp = <&fcpvd2>; 2561 renesas,fcp = <&fcpvd2>;
2287 }; 2562 };
2288 2563
2289 fcpvd2: fcp@fea37000 { 2564 vspi0: vsp@fe9a0000 {
2290 compatible = "renesas,fcpv"; 2565 compatible = "renesas,vsp2";
2291 reg = <0 0xfea37000 0 0x200>; 2566 reg = <0 0xfe9a0000 0 0x8000>;
2292 clocks = <&cpg CPG_MOD 601>; 2567 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
2293 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2568 clocks = <&cpg CPG_MOD 631>;
2294 resets = <&cpg 601>; 2569 power-domains = <&sysc R8A7795_PD_A3VP>;
2295 iommus = <&ipmmu_vi1 10>; 2570 resets = <&cpg 631>;
2571
2572 renesas,fcp = <&fcpvi0>;
2296 }; 2573 };
2297 2574
2298 fdp1@fe940000 { 2575 vspi1: vsp@fe9b0000 {
2299 compatible = "renesas,fdp1"; 2576 compatible = "renesas,vsp2";
2300 reg = <0 0xfe940000 0 0x2400>; 2577 reg = <0 0xfe9b0000 0 0x8000>;
2301 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; 2578 interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
2302 clocks = <&cpg CPG_MOD 119>; 2579 clocks = <&cpg CPG_MOD 630>;
2303 power-domains = <&sysc R8A7795_PD_A3VP>; 2580 power-domains = <&sysc R8A7795_PD_A3VP>;
2304 resets = <&cpg 119>; 2581 resets = <&cpg 630>;
2305 renesas,fcp = <&fcpf0>; 2582
2583 renesas,fcp = <&fcpvi1>;
2306 }; 2584 };
2307 2585
2308 fdp1@fe944000 { 2586 csi20: csi2@fea80000 {
2309 compatible = "renesas,fdp1"; 2587 compatible = "renesas,r8a7795-csi2";
2310 reg = <0 0xfe944000 0 0x2400>; 2588 reg = <0 0xfea80000 0 0x10000>;
2311 interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 2589 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
2312 clocks = <&cpg CPG_MOD 118>; 2590 clocks = <&cpg CPG_MOD 714>;
2313 power-domains = <&sysc R8A7795_PD_A3VP>; 2591 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
2314 resets = <&cpg 118>; 2592 resets = <&cpg 714>;
2315 renesas,fcp = <&fcpf1>; 2593 status = "disabled";
2594
2595 ports {
2596 #address-cells = <1>;
2597 #size-cells = <0>;
2598
2599 port@1 {
2600 #address-cells = <1>;
2601 #size-cells = <0>;
2602
2603 reg = <1>;
2604
2605 csi20vin0: endpoint@0 {
2606 reg = <0>;
2607 remote-endpoint = <&vin0csi20>;
2608 };
2609 csi20vin1: endpoint@1 {
2610 reg = <1>;
2611 remote-endpoint = <&vin1csi20>;
2612 };
2613 csi20vin2: endpoint@2 {
2614 reg = <2>;
2615 remote-endpoint = <&vin2csi20>;
2616 };
2617 csi20vin3: endpoint@3 {
2618 reg = <3>;
2619 remote-endpoint = <&vin3csi20>;
2620 };
2621 csi20vin4: endpoint@4 {
2622 reg = <4>;
2623 remote-endpoint = <&vin4csi20>;
2624 };
2625 csi20vin5: endpoint@5 {
2626 reg = <5>;
2627 remote-endpoint = <&vin5csi20>;
2628 };
2629 csi20vin6: endpoint@6 {
2630 reg = <6>;
2631 remote-endpoint = <&vin6csi20>;
2632 };
2633 csi20vin7: endpoint@7 {
2634 reg = <7>;
2635 remote-endpoint = <&vin7csi20>;
2636 };
2637 };
2638 };
2639 };
2640
2641 csi40: csi2@feaa0000 {
2642 compatible = "renesas,r8a7795-csi2";
2643 reg = <0 0xfeaa0000 0 0x10000>;
2644 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
2645 clocks = <&cpg CPG_MOD 716>;
2646 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
2647 resets = <&cpg 716>;
2648 status = "disabled";
2649
2650 ports {
2651 #address-cells = <1>;
2652 #size-cells = <0>;
2653
2654 port@1 {
2655 #address-cells = <1>;
2656 #size-cells = <0>;
2657
2658 reg = <1>;
2659
2660 csi40vin0: endpoint@0 {
2661 reg = <0>;
2662 remote-endpoint = <&vin0csi40>;
2663 };
2664 csi40vin1: endpoint@1 {
2665 reg = <1>;
2666 remote-endpoint = <&vin1csi40>;
2667 };
2668 csi40vin2: endpoint@2 {
2669 reg = <2>;
2670 remote-endpoint = <&vin2csi40>;
2671 };
2672 csi40vin3: endpoint@3 {
2673 reg = <3>;
2674 remote-endpoint = <&vin3csi40>;
2675 };
2676 };
2677 };
2678 };
2679
2680 csi41: csi2@feab0000 {
2681 compatible = "renesas,r8a7795-csi2";
2682 reg = <0 0xfeab0000 0 0x10000>;
2683 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
2684 clocks = <&cpg CPG_MOD 715>;
2685 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
2686 resets = <&cpg 715>;
2687 status = "disabled";
2688
2689 ports {
2690 #address-cells = <1>;
2691 #size-cells = <0>;
2692
2693 port@1 {
2694 #address-cells = <1>;
2695 #size-cells = <0>;
2696
2697 reg = <1>;
2698
2699 csi41vin4: endpoint@0 {
2700 reg = <0>;
2701 remote-endpoint = <&vin4csi41>;
2702 };
2703 csi41vin5: endpoint@1 {
2704 reg = <1>;
2705 remote-endpoint = <&vin5csi41>;
2706 };
2707 csi41vin6: endpoint@2 {
2708 reg = <2>;
2709 remote-endpoint = <&vin6csi41>;
2710 };
2711 csi41vin7: endpoint@3 {
2712 reg = <3>;
2713 remote-endpoint = <&vin7csi41>;
2714 };
2715 };
2716 };
2316 }; 2717 };
2317 2718
2318 hdmi0: hdmi@fead0000 { 2719 hdmi0: hdmi@fead0000 {
@@ -2337,6 +2738,10 @@
2337 port@1 { 2738 port@1 {
2338 reg = <1>; 2739 reg = <1>;
2339 }; 2740 };
2741 port@2 {
2742 /* HDMI sound */
2743 reg = <2>;
2744 };
2340 }; 2745 };
2341 }; 2746 };
2342 2747
@@ -2362,6 +2767,10 @@
2362 port@1 { 2767 port@1 {
2363 reg = <1>; 2768 reg = <1>;
2364 }; 2769 };
2770 port@2 {
2771 /* HDMI sound */
2772 reg = <2>;
2773 };
2365 }; 2774 };
2366 }; 2775 };
2367 2776
@@ -2412,38 +2821,12 @@
2412 }; 2821 };
2413 }; 2822 };
2414 2823
2415 tsc: thermal@e6198000 { 2824 prr: chipid@fff00044 {
2416 compatible = "renesas,r8a7795-thermal"; 2825 compatible = "renesas,prr";
2417 reg = <0 0xe6198000 0 0x100>, 2826 reg = <0 0xfff00044 0 4>;
2418 <0 0xe61a0000 0 0x100>,
2419 <0 0xe61a8000 0 0x100>;
2420 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
2421 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
2422 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
2423 clocks = <&cpg CPG_MOD 522>;
2424 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
2425 resets = <&cpg 522>;
2426 #thermal-sensor-cells = <1>;
2427 status = "okay";
2428 }; 2827 };
2429 }; 2828 };
2430 2829
2431 timer {
2432 compatible = "arm,armv8-timer";
2433 interrupts-extended = <&gic GIC_PPI 13
2434 (GIC_CPU_MASK_SIMPLE(8) |
2435 IRQ_TYPE_LEVEL_LOW)>,
2436 <&gic GIC_PPI 14
2437 (GIC_CPU_MASK_SIMPLE(8) |
2438 IRQ_TYPE_LEVEL_LOW)>,
2439 <&gic GIC_PPI 11
2440 (GIC_CPU_MASK_SIMPLE(8) |
2441 IRQ_TYPE_LEVEL_LOW)>,
2442 <&gic GIC_PPI 10
2443 (GIC_CPU_MASK_SIMPLE(8) |
2444 IRQ_TYPE_LEVEL_LOW)>;
2445 };
2446
2447 thermal-zones { 2830 thermal-zones {
2448 sensor_thermal1: sensor-thermal1 { 2831 sensor_thermal1: sensor-thermal1 {
2449 polling-delay-passive = <250>; 2832 polling-delay-passive = <250>;
@@ -2453,12 +2836,12 @@
2453 trips { 2836 trips {
2454 sensor1_passive: sensor1-passive { 2837 sensor1_passive: sensor1-passive {
2455 temperature = <95000>; 2838 temperature = <95000>;
2456 hysteresis = <2000>; 2839 hysteresis = <1000>;
2457 type = "passive"; 2840 type = "passive";
2458 }; 2841 };
2459 sensor1_crit: sensor1-crit { 2842 sensor1_crit: sensor1-crit {
2460 temperature = <120000>; 2843 temperature = <120000>;
2461 hysteresis = <2000>; 2844 hysteresis = <1000>;
2462 type = "critical"; 2845 type = "critical";
2463 }; 2846 };
2464 }; 2847 };
@@ -2479,12 +2862,12 @@
2479 trips { 2862 trips {
2480 sensor2_passive: sensor2-passive { 2863 sensor2_passive: sensor2-passive {
2481 temperature = <95000>; 2864 temperature = <95000>;
2482 hysteresis = <2000>; 2865 hysteresis = <1000>;
2483 type = "passive"; 2866 type = "passive";
2484 }; 2867 };
2485 sensor2_crit: sensor2-crit { 2868 sensor2_crit: sensor2-crit {
2486 temperature = <120000>; 2869 temperature = <120000>;
2487 hysteresis = <2000>; 2870 hysteresis = <1000>;
2488 type = "critical"; 2871 type = "critical";
2489 }; 2872 };
2490 }; 2873 };
@@ -2505,12 +2888,12 @@
2505 trips { 2888 trips {
2506 sensor3_passive: sensor3-passive { 2889 sensor3_passive: sensor3-passive {
2507 temperature = <95000>; 2890 temperature = <95000>;
2508 hysteresis = <2000>; 2891 hysteresis = <1000>;
2509 type = "passive"; 2892 type = "passive";
2510 }; 2893 };
2511 sensor3_crit: sensor3-crit { 2894 sensor3_crit: sensor3-crit {
2512 temperature = <120000>; 2895 temperature = <120000>;
2513 hysteresis = <2000>; 2896 hysteresis = <1000>;
2514 type = "critical"; 2897 type = "critical";
2515 }; 2898 };
2516 }; 2899 };
@@ -2524,6 +2907,14 @@
2524 }; 2907 };
2525 }; 2908 };
2526 2909
2910 timer {
2911 compatible = "arm,armv8-timer";
2912 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2913 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2914 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2915 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
2916 };
2917
2527 /* External USB clocks - can be overridden by the board */ 2918 /* External USB clocks - can be overridden by the board */
2528 usb3s0_clk: usb3s0 { 2919 usb3s0_clk: usb3s0 {
2529 compatible = "fixed-clock"; 2920 compatible = "fixed-clock";
diff --git a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts
index 498c9e807dc4..90cca09b9a5e 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts
@@ -40,6 +40,11 @@
40 "dclkin.0", "dclkin.1", "dclkin.2"; 40 "dclkin.0", "dclkin.1", "dclkin.2";
41}; 41};
42 42
43&sound_card {
44 dais = <&rsnd_port0 /* ak4613 */
45 &rsnd_port1>; /* HDMI0 */
46};
47
43&hdmi0 { 48&hdmi0 {
44 status = "okay"; 49 status = "okay";
45 50
@@ -50,9 +55,32 @@
50 remote-endpoint = <&hdmi0_con>; 55 remote-endpoint = <&hdmi0_con>;
51 }; 56 };
52 }; 57 };
58 port@2 {
59 reg = <2>;
60 dw_hdmi0_snd_in: endpoint {
61 remote-endpoint = <&rsnd_endpoint1>;
62 };
63 };
53 }; 64 };
54}; 65};
55 66
56&hdmi0_con { 67&hdmi0_con {
57 remote-endpoint = <&rcar_dw_hdmi0_out>; 68 remote-endpoint = <&rcar_dw_hdmi0_out>;
58}; 69};
70
71&rcar_sound {
72 ports {
73 /* rsnd_port0 is on salvator-common */
74 rsnd_port1: port@1 {
75 rsnd_endpoint1: endpoint {
76 remote-endpoint = <&dw_hdmi0_snd_in>;
77
78 dai-format = "i2s";
79 bitclock-master = <&rsnd_endpoint1>;
80 frame-master = <&rsnd_endpoint1>;
81
82 playback = <&ssi2>;
83 };
84 };
85 };
86};
diff --git a/arch/arm64/boot/dts/renesas/r8a7796-salvator-xs.dts b/arch/arm64/boot/dts/renesas/r8a7796-salvator-xs.dts
index 2c37055efa94..ddf35d4cd5e5 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796-salvator-xs.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7796-salvator-xs.dts
@@ -40,6 +40,11 @@
40 "dclkin.0", "dclkin.1", "dclkin.2"; 40 "dclkin.0", "dclkin.1", "dclkin.2";
41}; 41};
42 42
43&sound_card {
44 dais = <&rsnd_port0 /* ak4613 */
45 &rsnd_port1>; /* HDMI0 */
46};
47
43&hdmi0 { 48&hdmi0 {
44 status = "okay"; 49 status = "okay";
45 50
@@ -50,9 +55,32 @@
50 remote-endpoint = <&hdmi0_con>; 55 remote-endpoint = <&hdmi0_con>;
51 }; 56 };
52 }; 57 };
58 port@2 {
59 reg = <2>;
60 dw_hdmi0_snd_in: endpoint {
61 remote-endpoint = <&rsnd_endpoint1>;
62 };
63 };
53 }; 64 };
54}; 65};
55 66
56&hdmi0_con { 67&hdmi0_con {
57 remote-endpoint = <&rcar_dw_hdmi0_out>; 68 remote-endpoint = <&rcar_dw_hdmi0_out>;
58}; 69};
70
71&rcar_sound {
72 ports {
73 /* rsnd_port0 is on salvator-common */
74 rsnd_port1: port@1 {
75 rsnd_endpoint1: endpoint {
76 remote-endpoint = <&dw_hdmi0_snd_in>;
77
78 dai-format = "i2s";
79 bitclock-master = <&rsnd_endpoint1>;
80 frame-master = <&rsnd_endpoint1>;
81
82 playback = <&ssi2>;
83 };
84 };
85 };
86};
diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
index 556eb8e45499..7c25be6b5af3 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
@@ -60,6 +60,72 @@
60 clock-frequency = <0>; 60 clock-frequency = <0>;
61 }; 61 };
62 62
63 cluster0_opp: opp_table0 {
64 compatible = "operating-points-v2";
65 opp-shared;
66
67 opp-500000000 {
68 opp-hz = /bits/ 64 <500000000>;
69 opp-microvolt = <820000>;
70 clock-latency-ns = <300000>;
71 };
72 opp-1000000000 {
73 opp-hz = /bits/ 64 <1000000000>;
74 opp-microvolt = <820000>;
75 clock-latency-ns = <300000>;
76 };
77 opp-1500000000 {
78 opp-hz = /bits/ 64 <1500000000>;
79 opp-microvolt = <820000>;
80 clock-latency-ns = <300000>;
81 };
82 opp-1600000000 {
83 opp-hz = /bits/ 64 <1600000000>;
84 opp-microvolt = <900000>;
85 clock-latency-ns = <300000>;
86 turbo-mode;
87 };
88 opp-1700000000 {
89 opp-hz = /bits/ 64 <1700000000>;
90 opp-microvolt = <900000>;
91 clock-latency-ns = <300000>;
92 turbo-mode;
93 };
94 opp-1800000000 {
95 opp-hz = /bits/ 64 <1800000000>;
96 opp-microvolt = <960000>;
97 clock-latency-ns = <300000>;
98 turbo-mode;
99 };
100 };
101
102 cluster1_opp: opp_table1 {
103 compatible = "operating-points-v2";
104 opp-shared;
105
106 opp-800000000 {
107 opp-hz = /bits/ 64 <800000000>;
108 opp-microvolt = <820000>;
109 clock-latency-ns = <300000>;
110 };
111 opp-1000000000 {
112 opp-hz = /bits/ 64 <1000000000>;
113 opp-microvolt = <820000>;
114 clock-latency-ns = <300000>;
115 };
116 opp-1200000000 {
117 opp-hz = /bits/ 64 <1200000000>;
118 opp-microvolt = <820000>;
119 clock-latency-ns = <300000>;
120 };
121 opp-1300000000 {
122 opp-hz = /bits/ 64 <1300000000>;
123 opp-microvolt = <820000>;
124 clock-latency-ns = <300000>;
125 turbo-mode;
126 };
127 };
128
63 cpus { 129 cpus {
64 #address-cells = <1>; 130 #address-cells = <1>;
65 #size-cells = <0>; 131 #size-cells = <0>;
@@ -77,7 +143,7 @@
77 }; 143 };
78 144
79 a57_1: cpu@1 { 145 a57_1: cpu@1 {
80 compatible = "arm,cortex-a57","arm,armv8"; 146 compatible = "arm,cortex-a57", "arm,armv8";
81 reg = <0x1>; 147 reg = <0x1>;
82 device_type = "cpu"; 148 device_type = "cpu";
83 power-domains = <&sysc R8A7796_PD_CA57_CPU1>; 149 power-domains = <&sysc R8A7796_PD_CA57_CPU1>;
@@ -100,7 +166,7 @@
100 }; 166 };
101 167
102 a53_1: cpu@101 { 168 a53_1: cpu@101 {
103 compatible = "arm,cortex-a53","arm,armv8"; 169 compatible = "arm,cortex-a53", "arm,armv8";
104 reg = <0x101>; 170 reg = <0x101>;
105 device_type = "cpu"; 171 device_type = "cpu";
106 power-domains = <&sysc R8A7796_PD_CA53_CPU1>; 172 power-domains = <&sysc R8A7796_PD_CA53_CPU1>;
@@ -111,7 +177,7 @@
111 }; 177 };
112 178
113 a53_2: cpu@102 { 179 a53_2: cpu@102 {
114 compatible = "arm,cortex-a53","arm,armv8"; 180 compatible = "arm,cortex-a53", "arm,armv8";
115 reg = <0x102>; 181 reg = <0x102>;
116 device_type = "cpu"; 182 device_type = "cpu";
117 power-domains = <&sysc R8A7796_PD_CA53_CPU2>; 183 power-domains = <&sysc R8A7796_PD_CA53_CPU2>;
@@ -122,7 +188,7 @@
122 }; 188 };
123 189
124 a53_3: cpu@103 { 190 a53_3: cpu@103 {
125 compatible = "arm,cortex-a53","arm,armv8"; 191 compatible = "arm,cortex-a53", "arm,armv8";
126 reg = <0x103>; 192 reg = <0x103>;
127 device_type = "cpu"; 193 device_type = "cpu";
128 power-domains = <&sysc R8A7796_PD_CA53_CPU3>; 194 power-domains = <&sysc R8A7796_PD_CA53_CPU3>;
@@ -161,72 +227,6 @@
161 clock-frequency = <0>; 227 clock-frequency = <0>;
162 }; 228 };
163 229
164 cluster0_opp: opp_table0 {
165 compatible = "operating-points-v2";
166 opp-shared;
167
168 opp-500000000 {
169 opp-hz = /bits/ 64 <500000000>;
170 opp-microvolt = <820000>;
171 clock-latency-ns = <300000>;
172 };
173 opp-1000000000 {
174 opp-hz = /bits/ 64 <1000000000>;
175 opp-microvolt = <820000>;
176 clock-latency-ns = <300000>;
177 };
178 opp-1500000000 {
179 opp-hz = /bits/ 64 <1500000000>;
180 opp-microvolt = <820000>;
181 clock-latency-ns = <300000>;
182 };
183 opp-1600000000 {
184 opp-hz = /bits/ 64 <1600000000>;
185 opp-microvolt = <900000>;
186 clock-latency-ns = <300000>;
187 turbo-mode;
188 };
189 opp-1700000000 {
190 opp-hz = /bits/ 64 <1700000000>;
191 opp-microvolt = <900000>;
192 clock-latency-ns = <300000>;
193 turbo-mode;
194 };
195 opp-1800000000 {
196 opp-hz = /bits/ 64 <1800000000>;
197 opp-microvolt = <960000>;
198 clock-latency-ns = <300000>;
199 turbo-mode;
200 };
201 };
202
203 cluster1_opp: opp_table1 {
204 compatible = "operating-points-v2";
205 opp-shared;
206
207 opp-800000000 {
208 opp-hz = /bits/ 64 <800000000>;
209 opp-microvolt = <820000>;
210 clock-latency-ns = <300000>;
211 };
212 opp-1000000000 {
213 opp-hz = /bits/ 64 <1000000000>;
214 opp-microvolt = <820000>;
215 clock-latency-ns = <300000>;
216 };
217 opp-1200000000 {
218 opp-hz = /bits/ 64 <1200000000>;
219 opp-microvolt = <820000>;
220 clock-latency-ns = <300000>;
221 };
222 opp-1300000000 {
223 opp-hz = /bits/ 64 <1300000000>;
224 opp-microvolt = <820000>;
225 clock-latency-ns = <300000>;
226 turbo-mode;
227 };
228 };
229
230 /* External PCIe clock - can be overridden by the board */ 230 /* External PCIe clock - can be overridden by the board */
231 pcie_bus_clk: pcie_bus { 231 pcie_bus_clk: pcie_bus {
232 compatible = "fixed-clock"; 232 compatible = "fixed-clock";
@@ -234,13 +234,6 @@
234 clock-frequency = <0>; 234 clock-frequency = <0>;
235 }; 235 };
236 236
237 pmu_a57 {
238 compatible = "arm,cortex-a57-pmu";
239 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
240 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
241 interrupt-affinity = <&a57_0>, <&a57_1>;
242 };
243
244 pmu_a53 { 237 pmu_a53 {
245 compatible = "arm,cortex-a53-pmu"; 238 compatible = "arm,cortex-a53-pmu";
246 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 239 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
@@ -250,6 +243,13 @@
250 interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>; 243 interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>;
251 }; 244 };
252 245
246 pmu_a57 {
247 compatible = "arm,cortex-a57-pmu";
248 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
249 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
250 interrupt-affinity = <&a57_0>, <&a57_1>;
251 };
252
253 psci { 253 psci {
254 compatible = "arm,psci-1.0", "arm,psci-0.2"; 254 compatible = "arm,psci-1.0", "arm,psci-0.2";
255 method = "smc"; 255 method = "smc";
@@ -269,23 +269,6 @@
269 #size-cells = <2>; 269 #size-cells = <2>;
270 ranges; 270 ranges;
271 271
272 gic: interrupt-controller@f1010000 {
273 compatible = "arm,gic-400";
274 #interrupt-cells = <3>;
275 #address-cells = <0>;
276 interrupt-controller;
277 reg = <0x0 0xf1010000 0 0x1000>,
278 <0x0 0xf1020000 0 0x20000>,
279 <0x0 0xf1040000 0 0x20000>,
280 <0x0 0xf1060000 0 0x20000>;
281 interrupts = <GIC_PPI 9
282 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
283 clocks = <&cpg CPG_MOD 408>;
284 clock-names = "clk";
285 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
286 resets = <&cpg 408>;
287 };
288
289 wdt0: watchdog@e6020000 { 272 wdt0: watchdog@e6020000 {
290 compatible = "renesas,r8a7796-wdt", 273 compatible = "renesas,r8a7796-wdt",
291 "renesas,rcar-gen3-wdt"; 274 "renesas,rcar-gen3-wdt";
@@ -421,100 +404,6 @@
421 reg = <0 0xe6060000 0 0x50c>; 404 reg = <0 0xe6060000 0 0x50c>;
422 }; 405 };
423 406
424 ipmmu_vi0: mmu@febd0000 {
425 compatible = "renesas,ipmmu-r8a7796";
426 reg = <0 0xfebd0000 0 0x1000>;
427 renesas,ipmmu-main = <&ipmmu_mm 9>;
428 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
429 #iommu-cells = <1>;
430 };
431
432 ipmmu_vc0: mmu@fe6b0000 {
433 compatible = "renesas,ipmmu-r8a7796";
434 reg = <0 0xfe6b0000 0 0x1000>;
435 renesas,ipmmu-main = <&ipmmu_mm 8>;
436 power-domains = <&sysc R8A7796_PD_A3VC>;
437 #iommu-cells = <1>;
438 status = "disabled";
439 };
440
441 ipmmu_pv0: mmu@fd800000 {
442 compatible = "renesas,ipmmu-r8a7796";
443 reg = <0 0xfd800000 0 0x1000>;
444 renesas,ipmmu-main = <&ipmmu_mm 5>;
445 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
446 #iommu-cells = <1>;
447 };
448
449 ipmmu_pv1: mmu@fd950000 {
450 compatible = "renesas,ipmmu-r8a7796";
451 reg = <0 0xfd950000 0 0x1000>;
452 renesas,ipmmu-main = <&ipmmu_mm 6>;
453 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
454 #iommu-cells = <1>;
455 status = "disabled";
456 };
457
458 ipmmu_ir: mmu@ff8b0000 {
459 compatible = "renesas,ipmmu-r8a7796";
460 reg = <0 0xff8b0000 0 0x1000>;
461 renesas,ipmmu-main = <&ipmmu_mm 3>;
462 power-domains = <&sysc R8A7796_PD_A3IR>;
463 #iommu-cells = <1>;
464 status = "disabled";
465 };
466
467 ipmmu_hc: mmu@e6570000 {
468 compatible = "renesas,ipmmu-r8a7796";
469 reg = <0 0xe6570000 0 0x1000>;
470 renesas,ipmmu-main = <&ipmmu_mm 2>;
471 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
472 #iommu-cells = <1>;
473 status = "disabled";
474 };
475
476 ipmmu_rt: mmu@ffc80000 {
477 compatible = "renesas,ipmmu-r8a7796";
478 reg = <0 0xffc80000 0 0x1000>;
479 renesas,ipmmu-main = <&ipmmu_mm 7>;
480 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
481 #iommu-cells = <1>;
482 status = "disabled";
483 };
484
485 ipmmu_mp: mmu@ec670000 {
486 compatible = "renesas,ipmmu-r8a7796";
487 reg = <0 0xec670000 0 0x1000>;
488 renesas,ipmmu-main = <&ipmmu_mm 4>;
489 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
490 #iommu-cells = <1>;
491 };
492
493 ipmmu_ds0: mmu@e6740000 {
494 compatible = "renesas,ipmmu-r8a7796";
495 reg = <0 0xe6740000 0 0x1000>;
496 renesas,ipmmu-main = <&ipmmu_mm 0>;
497 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
498 #iommu-cells = <1>;
499 };
500
501 ipmmu_ds1: mmu@e7740000 {
502 compatible = "renesas,ipmmu-r8a7796";
503 reg = <0 0xe7740000 0 0x1000>;
504 renesas,ipmmu-main = <&ipmmu_mm 1>;
505 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
506 #iommu-cells = <1>;
507 };
508
509 ipmmu_mm: mmu@e67b0000 {
510 compatible = "renesas,ipmmu-r8a7796";
511 reg = <0 0xe67b0000 0 0x1000>;
512 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
513 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
514 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
515 #iommu-cells = <1>;
516 };
517
518 cpg: clock-controller@e6150000 { 407 cpg: clock-controller@e6150000 {
519 compatible = "renesas,r8a7796-cpg-mssr"; 408 compatible = "renesas,r8a7796-cpg-mssr";
520 reg = <0 0xe6150000 0 0x1000>; 409 reg = <0 0xe6150000 0 0x1000>;
@@ -530,17 +419,27 @@
530 reg = <0 0xe6160000 0 0x0200>; 419 reg = <0 0xe6160000 0 0x0200>;
531 }; 420 };
532 421
533 prr: chipid@fff00044 {
534 compatible = "renesas,prr";
535 reg = <0 0xfff00044 0 4>;
536 };
537
538 sysc: system-controller@e6180000 { 422 sysc: system-controller@e6180000 {
539 compatible = "renesas,r8a7796-sysc"; 423 compatible = "renesas,r8a7796-sysc";
540 reg = <0 0xe6180000 0 0x0400>; 424 reg = <0 0xe6180000 0 0x0400>;
541 #power-domain-cells = <1>; 425 #power-domain-cells = <1>;
542 }; 426 };
543 427
428 tsc: thermal@e6198000 {
429 compatible = "renesas,r8a7796-thermal";
430 reg = <0 0xe6198000 0 0x100>,
431 <0 0xe61a0000 0 0x100>,
432 <0 0xe61a8000 0 0x100>;
433 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
434 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
435 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
436 clocks = <&cpg CPG_MOD 522>;
437 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
438 resets = <&cpg 522>;
439 #thermal-sensor-cells = <1>;
440 status = "okay";
441 };
442
544 intc_ex: interrupt-controller@e61c0000 { 443 intc_ex: interrupt-controller@e61c0000 {
545 compatible = "renesas,intc-ex-r8a7796", "renesas,irqc"; 444 compatible = "renesas,intc-ex-r8a7796", "renesas,irqc";
546 #interrupt-cells = <2>; 445 #interrupt-cells = <2>;
@@ -557,92 +456,6 @@
557 resets = <&cpg 407>; 456 resets = <&cpg 407>;
558 }; 457 };
559 458
560 i2c_dvfs: i2c@e60b0000 {
561 #address-cells = <1>;
562 #size-cells = <0>;
563 compatible = "renesas,iic-r8a7796",
564 "renesas,rcar-gen3-iic",
565 "renesas,rmobile-iic";
566 reg = <0 0xe60b0000 0 0x425>;
567 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
568 clocks = <&cpg CPG_MOD 926>;
569 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
570 resets = <&cpg 926>;
571 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
572 dma-names = "tx", "rx";
573 status = "disabled";
574 };
575
576 pwm0: pwm@e6e30000 {
577 compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
578 reg = <0 0xe6e30000 0 8>;
579 #pwm-cells = <2>;
580 clocks = <&cpg CPG_MOD 523>;
581 resets = <&cpg 523>;
582 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
583 status = "disabled";
584 };
585
586 pwm1: pwm@e6e31000 {
587 compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
588 reg = <0 0xe6e31000 0 8>;
589 #pwm-cells = <2>;
590 clocks = <&cpg CPG_MOD 523>;
591 resets = <&cpg 523>;
592 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
593 status = "disabled";
594 };
595
596 pwm2: pwm@e6e32000 {
597 compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
598 reg = <0 0xe6e32000 0 8>;
599 #pwm-cells = <2>;
600 clocks = <&cpg CPG_MOD 523>;
601 resets = <&cpg 523>;
602 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
603 status = "disabled";
604 };
605
606 pwm3: pwm@e6e33000 {
607 compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
608 reg = <0 0xe6e33000 0 8>;
609 #pwm-cells = <2>;
610 clocks = <&cpg CPG_MOD 523>;
611 resets = <&cpg 523>;
612 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
613 status = "disabled";
614 };
615
616 pwm4: pwm@e6e34000 {
617 compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
618 reg = <0 0xe6e34000 0 8>;
619 #pwm-cells = <2>;
620 clocks = <&cpg CPG_MOD 523>;
621 resets = <&cpg 523>;
622 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
623 status = "disabled";
624 };
625
626 pwm5: pwm@e6e35000 {
627 compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
628 reg = <0 0xe6e35000 0 8>;
629 #pwm-cells = <2>;
630 clocks = <&cpg CPG_MOD 523>;
631 resets = <&cpg 523>;
632 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
633 status = "disabled";
634 };
635
636 pwm6: pwm@e6e36000 {
637 compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
638 reg = <0 0xe6e36000 0 8>;
639 #pwm-cells = <2>;
640 clocks = <&cpg CPG_MOD 523>;
641 resets = <&cpg 523>;
642 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
643 status = "disabled";
644 };
645
646 i2c0: i2c@e6500000 { 459 i2c0: i2c@e6500000 {
647 #address-cells = <1>; 460 #address-cells = <1>;
648 #size-cells = <0>; 461 #size-cells = <0>;
@@ -758,181 +571,381 @@
758 status = "disabled"; 571 status = "disabled";
759 }; 572 };
760 573
761 can0: can@e6c30000 { 574 i2c_dvfs: i2c@e60b0000 {
762 compatible = "renesas,can-r8a7796", 575 #address-cells = <1>;
763 "renesas,rcar-gen3-can"; 576 #size-cells = <0>;
764 reg = <0 0xe6c30000 0 0x1000>; 577 compatible = "renesas,iic-r8a7796",
765 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 578 "renesas,rcar-gen3-iic",
766 clocks = <&cpg CPG_MOD 916>, 579 "renesas,rmobile-iic";
767 <&cpg CPG_CORE R8A7796_CLK_CANFD>, 580 reg = <0 0xe60b0000 0 0x425>;
768 <&can_clk>; 581 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
769 clock-names = "clkp1", "clkp2", "can_clk"; 582 clocks = <&cpg CPG_MOD 926>;
770 assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>;
771 assigned-clock-rates = <40000000>;
772 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 583 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
773 resets = <&cpg 916>; 584 resets = <&cpg 926>;
585 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
586 dma-names = "tx", "rx";
774 status = "disabled"; 587 status = "disabled";
775 }; 588 };
776 589
777 can1: can@e6c38000 { 590 hscif0: serial@e6540000 {
778 compatible = "renesas,can-r8a7796", 591 compatible = "renesas,hscif-r8a7796",
779 "renesas,rcar-gen3-can"; 592 "renesas,rcar-gen3-hscif",
780 reg = <0 0xe6c38000 0 0x1000>; 593 "renesas,hscif";
781 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 594 reg = <0 0xe6540000 0 0x60>;
782 clocks = <&cpg CPG_MOD 915>, 595 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
783 <&cpg CPG_CORE R8A7796_CLK_CANFD>, 596 clocks = <&cpg CPG_MOD 520>,
784 <&can_clk>; 597 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
785 clock-names = "clkp1", "clkp2", "can_clk"; 598 <&scif_clk>;
786 assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>; 599 clock-names = "fck", "brg_int", "scif_clk";
787 assigned-clock-rates = <40000000>; 600 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
601 <&dmac2 0x31>, <&dmac2 0x30>;
602 dma-names = "tx", "rx", "tx", "rx";
788 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 603 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
789 resets = <&cpg 915>; 604 resets = <&cpg 520>;
790 status = "disabled"; 605 status = "disabled";
791 }; 606 };
792 607
793 canfd: can@e66c0000 { 608 hscif1: serial@e6550000 {
794 compatible = "renesas,r8a7796-canfd", 609 compatible = "renesas,hscif-r8a7796",
795 "renesas,rcar-gen3-canfd"; 610 "renesas,rcar-gen3-hscif",
796 reg = <0 0xe66c0000 0 0x8000>; 611 "renesas,hscif";
797 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 612 reg = <0 0xe6550000 0 0x60>;
798 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 613 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
799 clocks = <&cpg CPG_MOD 914>, 614 clocks = <&cpg CPG_MOD 519>,
800 <&cpg CPG_CORE R8A7796_CLK_CANFD>, 615 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
801 <&can_clk>; 616 <&scif_clk>;
802 clock-names = "fck", "canfd", "can_clk"; 617 clock-names = "fck", "brg_int", "scif_clk";
803 assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>; 618 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
804 assigned-clock-rates = <40000000>; 619 <&dmac2 0x33>, <&dmac2 0x32>;
620 dma-names = "tx", "rx", "tx", "rx";
805 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 621 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
806 resets = <&cpg 914>; 622 resets = <&cpg 519>;
807 status = "disabled"; 623 status = "disabled";
808
809 channel0 {
810 status = "disabled";
811 };
812
813 channel1 {
814 status = "disabled";
815 };
816 }; 624 };
817 625
818 drif00: rif@e6f40000 { 626 hscif2: serial@e6560000 {
819 compatible = "renesas,r8a7796-drif", 627 compatible = "renesas,hscif-r8a7796",
820 "renesas,rcar-gen3-drif"; 628 "renesas,rcar-gen3-hscif",
821 reg = <0 0xe6f40000 0 0x64>; 629 "renesas,hscif";
822 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 630 reg = <0 0xe6560000 0 0x60>;
823 clocks = <&cpg CPG_MOD 515>; 631 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
824 clock-names = "fck"; 632 clocks = <&cpg CPG_MOD 518>,
825 dmas = <&dmac1 0x20>, <&dmac2 0x20>; 633 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
826 dma-names = "rx", "rx"; 634 <&scif_clk>;
635 clock-names = "fck", "brg_int", "scif_clk";
636 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
637 <&dmac2 0x35>, <&dmac2 0x34>;
638 dma-names = "tx", "rx", "tx", "rx";
827 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 639 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
828 resets = <&cpg 515>; 640 resets = <&cpg 518>;
829 renesas,bonding = <&drif01>;
830 status = "disabled"; 641 status = "disabled";
831 }; 642 };
832 643
833 drif01: rif@e6f50000 { 644 hscif3: serial@e66a0000 {
834 compatible = "renesas,r8a7796-drif", 645 compatible = "renesas,hscif-r8a7796",
835 "renesas,rcar-gen3-drif"; 646 "renesas,rcar-gen3-hscif",
836 reg = <0 0xe6f50000 0 0x64>; 647 "renesas,hscif";
837 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 648 reg = <0 0xe66a0000 0 0x60>;
838 clocks = <&cpg CPG_MOD 514>; 649 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
839 clock-names = "fck"; 650 clocks = <&cpg CPG_MOD 517>,
840 dmas = <&dmac1 0x22>, <&dmac2 0x22>; 651 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
841 dma-names = "rx", "rx"; 652 <&scif_clk>;
653 clock-names = "fck", "brg_int", "scif_clk";
654 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
655 dma-names = "tx", "rx";
842 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 656 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
843 resets = <&cpg 514>; 657 resets = <&cpg 517>;
844 renesas,bonding = <&drif00>;
845 status = "disabled"; 658 status = "disabled";
846 }; 659 };
847 660
848 drif10: rif@e6f60000 { 661 hscif4: serial@e66b0000 {
849 compatible = "renesas,r8a7796-drif", 662 compatible = "renesas,hscif-r8a7796",
850 "renesas,rcar-gen3-drif"; 663 "renesas,rcar-gen3-hscif",
851 reg = <0 0xe6f60000 0 0x64>; 664 "renesas,hscif";
852 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 665 reg = <0 0xe66b0000 0 0x60>;
853 clocks = <&cpg CPG_MOD 513>; 666 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
854 clock-names = "fck"; 667 clocks = <&cpg CPG_MOD 516>,
855 dmas = <&dmac1 0x24>, <&dmac2 0x24>; 668 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
856 dma-names = "rx", "rx"; 669 <&scif_clk>;
670 clock-names = "fck", "brg_int", "scif_clk";
671 dmas = <&dmac0 0x39>, <&dmac0 0x38>;
672 dma-names = "tx", "rx";
857 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 673 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
858 resets = <&cpg 513>; 674 resets = <&cpg 516>;
859 renesas,bonding = <&drif11>;
860 status = "disabled"; 675 status = "disabled";
861 }; 676 };
862 677
863 drif11: rif@e6f70000 { 678 hsusb: usb@e6590000 {
864 compatible = "renesas,r8a7796-drif", 679 compatible = "renesas,usbhs-r8a7796",
865 "renesas,rcar-gen3-drif"; 680 "renesas,rcar-gen3-usbhs";
866 reg = <0 0xe6f70000 0 0x64>; 681 reg = <0 0xe6590000 0 0x100>;
867 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 682 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
868 clocks = <&cpg CPG_MOD 512>; 683 clocks = <&cpg CPG_MOD 704>;
869 clock-names = "fck"; 684 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
870 dmas = <&dmac1 0x26>, <&dmac2 0x26>; 685 <&usb_dmac1 0>, <&usb_dmac1 1>;
871 dma-names = "rx", "rx"; 686 dma-names = "ch0", "ch1", "ch2", "ch3";
687 renesas,buswait = <11>;
688 phys = <&usb2_phy0>;
689 phy-names = "usb";
872 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 690 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
873 resets = <&cpg 512>; 691 resets = <&cpg 704>;
874 renesas,bonding = <&drif10>;
875 status = "disabled"; 692 status = "disabled";
876 }; 693 };
877 694
878 drif20: rif@e6f80000 { 695 usb_dmac0: dma-controller@e65a0000 {
879 compatible = "renesas,r8a7796-drif", 696 compatible = "renesas,r8a7796-usb-dmac",
880 "renesas,rcar-gen3-drif"; 697 "renesas,usb-dmac";
881 reg = <0 0xe6f80000 0 0x64>; 698 reg = <0 0xe65a0000 0 0x100>;
882 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 699 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
883 clocks = <&cpg CPG_MOD 511>; 700 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
884 clock-names = "fck"; 701 interrupt-names = "ch0", "ch1";
885 dmas = <&dmac1 0x28>, <&dmac2 0x28>; 702 clocks = <&cpg CPG_MOD 330>;
886 dma-names = "rx", "rx";
887 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 703 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
888 resets = <&cpg 511>; 704 resets = <&cpg 330>;
889 renesas,bonding = <&drif21>; 705 #dma-cells = <1>;
706 dma-channels = <2>;
707 };
708
709 usb_dmac1: dma-controller@e65b0000 {
710 compatible = "renesas,r8a7796-usb-dmac",
711 "renesas,usb-dmac";
712 reg = <0 0xe65b0000 0 0x100>;
713 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
714 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
715 interrupt-names = "ch0", "ch1";
716 clocks = <&cpg CPG_MOD 331>;
717 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
718 resets = <&cpg 331>;
719 #dma-cells = <1>;
720 dma-channels = <2>;
721 };
722
723 usb3_phy0: usb-phy@e65ee000 {
724 compatible = "renesas,r8a7796-usb3-phy",
725 "renesas,rcar-gen3-usb3-phy";
726 reg = <0 0xe65ee000 0 0x90>;
727 clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>,
728 <&usb_extal_clk>;
729 clock-names = "usb3-if", "usb3s_clk", "usb_extal";
730 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
731 resets = <&cpg 328>;
732 #phy-cells = <0>;
890 status = "disabled"; 733 status = "disabled";
891 }; 734 };
892 735
893 drif21: rif@e6f90000 { 736 dmac0: dma-controller@e6700000 {
894 compatible = "renesas,r8a7796-drif", 737 compatible = "renesas,dmac-r8a7796",
895 "renesas,rcar-gen3-drif"; 738 "renesas,rcar-dmac";
896 reg = <0 0xe6f90000 0 0x64>; 739 reg = <0 0xe6700000 0 0x10000>;
897 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 740 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH
898 clocks = <&cpg CPG_MOD 510>; 741 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
742 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
743 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
744 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
745 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
746 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
747 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
748 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
749 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
750 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
751 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
752 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
753 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
754 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
755 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH
756 GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
757 interrupt-names = "error",
758 "ch0", "ch1", "ch2", "ch3",
759 "ch4", "ch5", "ch6", "ch7",
760 "ch8", "ch9", "ch10", "ch11",
761 "ch12", "ch13", "ch14", "ch15";
762 clocks = <&cpg CPG_MOD 219>;
899 clock-names = "fck"; 763 clock-names = "fck";
900 dmas = <&dmac1 0x2a>, <&dmac2 0x2a>;
901 dma-names = "rx", "rx";
902 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 764 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
903 resets = <&cpg 510>; 765 resets = <&cpg 219>;
904 renesas,bonding = <&drif20>; 766 #dma-cells = <1>;
905 status = "disabled"; 767 dma-channels = <16>;
768 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
769 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
770 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
771 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
772 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
773 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
774 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
775 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
906 }; 776 };
907 777
908 drif30: rif@e6fa0000 { 778 dmac1: dma-controller@e7300000 {
909 compatible = "renesas,r8a7796-drif", 779 compatible = "renesas,dmac-r8a7796",
910 "renesas,rcar-gen3-drif"; 780 "renesas,rcar-dmac";
911 reg = <0 0xe6fa0000 0 0x64>; 781 reg = <0 0xe7300000 0 0x10000>;
912 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 782 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
913 clocks = <&cpg CPG_MOD 509>; 783 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
784 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
785 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
786 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
787 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
788 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
789 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
790 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
791 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
792 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
793 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
794 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
795 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
796 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
797 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH
798 GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
799 interrupt-names = "error",
800 "ch0", "ch1", "ch2", "ch3",
801 "ch4", "ch5", "ch6", "ch7",
802 "ch8", "ch9", "ch10", "ch11",
803 "ch12", "ch13", "ch14", "ch15";
804 clocks = <&cpg CPG_MOD 218>;
914 clock-names = "fck"; 805 clock-names = "fck";
915 dmas = <&dmac1 0x2c>, <&dmac2 0x2c>;
916 dma-names = "rx", "rx";
917 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 806 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
918 resets = <&cpg 509>; 807 resets = <&cpg 218>;
919 renesas,bonding = <&drif31>; 808 #dma-cells = <1>;
920 status = "disabled"; 809 dma-channels = <16>;
810 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
811 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
812 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
813 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
814 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
815 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
816 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
817 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
921 }; 818 };
922 819
923 drif31: rif@e6fb0000 { 820 dmac2: dma-controller@e7310000 {
924 compatible = "renesas,r8a7796-drif", 821 compatible = "renesas,dmac-r8a7796",
925 "renesas,rcar-gen3-drif"; 822 "renesas,rcar-dmac";
926 reg = <0 0xe6fb0000 0 0x64>; 823 reg = <0 0xe7310000 0 0x10000>;
927 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 824 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH
928 clocks = <&cpg CPG_MOD 508>; 825 GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH
826 GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH
827 GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH
828 GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH
829 GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH
830 GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH
831 GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH
832 GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH
833 GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH
834 GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH
835 GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH
836 GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH
837 GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH
838 GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH
839 GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH
840 GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
841 interrupt-names = "error",
842 "ch0", "ch1", "ch2", "ch3",
843 "ch4", "ch5", "ch6", "ch7",
844 "ch8", "ch9", "ch10", "ch11",
845 "ch12", "ch13", "ch14", "ch15";
846 clocks = <&cpg CPG_MOD 217>;
929 clock-names = "fck"; 847 clock-names = "fck";
930 dmas = <&dmac1 0x2e>, <&dmac2 0x2e>;
931 dma-names = "rx", "rx";
932 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 848 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
933 resets = <&cpg 508>; 849 resets = <&cpg 217>;
934 renesas,bonding = <&drif30>; 850 #dma-cells = <1>;
935 status = "disabled"; 851 dma-channels = <16>;
852 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
853 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
854 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
855 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
856 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
857 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
858 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
859 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
860 };
861
862 ipmmu_ds0: mmu@e6740000 {
863 compatible = "renesas,ipmmu-r8a7796";
864 reg = <0 0xe6740000 0 0x1000>;
865 renesas,ipmmu-main = <&ipmmu_mm 0>;
866 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
867 #iommu-cells = <1>;
868 };
869
870 ipmmu_ds1: mmu@e7740000 {
871 compatible = "renesas,ipmmu-r8a7796";
872 reg = <0 0xe7740000 0 0x1000>;
873 renesas,ipmmu-main = <&ipmmu_mm 1>;
874 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
875 #iommu-cells = <1>;
876 };
877
878 ipmmu_hc: mmu@e6570000 {
879 compatible = "renesas,ipmmu-r8a7796";
880 reg = <0 0xe6570000 0 0x1000>;
881 renesas,ipmmu-main = <&ipmmu_mm 2>;
882 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
883 #iommu-cells = <1>;
884 };
885
886 ipmmu_ir: mmu@ff8b0000 {
887 compatible = "renesas,ipmmu-r8a7796";
888 reg = <0 0xff8b0000 0 0x1000>;
889 renesas,ipmmu-main = <&ipmmu_mm 3>;
890 power-domains = <&sysc R8A7796_PD_A3IR>;
891 #iommu-cells = <1>;
892 };
893
894 ipmmu_mm: mmu@e67b0000 {
895 compatible = "renesas,ipmmu-r8a7796";
896 reg = <0 0xe67b0000 0 0x1000>;
897 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
898 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
899 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
900 #iommu-cells = <1>;
901 };
902
903 ipmmu_mp: mmu@ec670000 {
904 compatible = "renesas,ipmmu-r8a7796";
905 reg = <0 0xec670000 0 0x1000>;
906 renesas,ipmmu-main = <&ipmmu_mm 4>;
907 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
908 #iommu-cells = <1>;
909 };
910
911 ipmmu_pv0: mmu@fd800000 {
912 compatible = "renesas,ipmmu-r8a7796";
913 reg = <0 0xfd800000 0 0x1000>;
914 renesas,ipmmu-main = <&ipmmu_mm 5>;
915 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
916 #iommu-cells = <1>;
917 };
918
919 ipmmu_pv1: mmu@fd950000 {
920 compatible = "renesas,ipmmu-r8a7796";
921 reg = <0 0xfd950000 0 0x1000>;
922 renesas,ipmmu-main = <&ipmmu_mm 6>;
923 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
924 #iommu-cells = <1>;
925 };
926
927 ipmmu_rt: mmu@ffc80000 {
928 compatible = "renesas,ipmmu-r8a7796";
929 reg = <0 0xffc80000 0 0x1000>;
930 renesas,ipmmu-main = <&ipmmu_mm 7>;
931 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
932 #iommu-cells = <1>;
933 };
934
935 ipmmu_vc0: mmu@fe6b0000 {
936 compatible = "renesas,ipmmu-r8a7796";
937 reg = <0 0xfe6b0000 0 0x1000>;
938 renesas,ipmmu-main = <&ipmmu_mm 8>;
939 power-domains = <&sysc R8A7796_PD_A3VC>;
940 #iommu-cells = <1>;
941 };
942
943 ipmmu_vi0: mmu@febd0000 {
944 compatible = "renesas,ipmmu-r8a7796";
945 reg = <0 0xfebd0000 0 0x1000>;
946 renesas,ipmmu-main = <&ipmmu_mm 9>;
947 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
948 #iommu-cells = <1>;
936 }; 949 };
937 950
938 avb: ethernet@e6800000 { 951 avb: ethernet@e6800000 {
@@ -981,91 +994,130 @@
981 status = "disabled"; 994 status = "disabled";
982 }; 995 };
983 996
984 hscif0: serial@e6540000 { 997 can0: can@e6c30000 {
985 compatible = "renesas,hscif-r8a7796", 998 compatible = "renesas,can-r8a7796",
986 "renesas,rcar-gen3-hscif", 999 "renesas,rcar-gen3-can";
987 "renesas,hscif"; 1000 reg = <0 0xe6c30000 0 0x1000>;
988 reg = <0 0xe6540000 0 0x60>; 1001 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
989 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 1002 clocks = <&cpg CPG_MOD 916>,
990 clocks = <&cpg CPG_MOD 520>, 1003 <&cpg CPG_CORE R8A7796_CLK_CANFD>,
991 <&cpg CPG_CORE R8A7796_CLK_S3D1>, 1004 <&can_clk>;
992 <&scif_clk>; 1005 clock-names = "clkp1", "clkp2", "can_clk";
993 clock-names = "fck", "brg_int", "scif_clk"; 1006 assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>;
994 dmas = <&dmac1 0x31>, <&dmac1 0x30>, 1007 assigned-clock-rates = <40000000>;
995 <&dmac2 0x31>, <&dmac2 0x30>;
996 dma-names = "tx", "rx", "tx", "rx";
997 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 1008 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
998 resets = <&cpg 520>; 1009 resets = <&cpg 916>;
999 status = "disabled"; 1010 status = "disabled";
1000 }; 1011 };
1001 1012
1002 hscif1: serial@e6550000 { 1013 can1: can@e6c38000 {
1003 compatible = "renesas,hscif-r8a7796", 1014 compatible = "renesas,can-r8a7796",
1004 "renesas,rcar-gen3-hscif", 1015 "renesas,rcar-gen3-can";
1005 "renesas,hscif"; 1016 reg = <0 0xe6c38000 0 0x1000>;
1006 reg = <0 0xe6550000 0 0x60>; 1017 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
1007 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 1018 clocks = <&cpg CPG_MOD 915>,
1008 clocks = <&cpg CPG_MOD 519>, 1019 <&cpg CPG_CORE R8A7796_CLK_CANFD>,
1009 <&cpg CPG_CORE R8A7796_CLK_S3D1>, 1020 <&can_clk>;
1010 <&scif_clk>; 1021 clock-names = "clkp1", "clkp2", "can_clk";
1011 clock-names = "fck", "brg_int", "scif_clk"; 1022 assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>;
1012 dmas = <&dmac1 0x33>, <&dmac1 0x32>, 1023 assigned-clock-rates = <40000000>;
1013 <&dmac2 0x33>, <&dmac2 0x32>;
1014 dma-names = "tx", "rx", "tx", "rx";
1015 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 1024 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1016 resets = <&cpg 519>; 1025 resets = <&cpg 915>;
1017 status = "disabled"; 1026 status = "disabled";
1018 }; 1027 };
1019 1028
1020 hscif2: serial@e6560000 { 1029 canfd: can@e66c0000 {
1021 compatible = "renesas,hscif-r8a7796", 1030 compatible = "renesas,r8a7796-canfd",
1022 "renesas,rcar-gen3-hscif", 1031 "renesas,rcar-gen3-canfd";
1023 "renesas,hscif"; 1032 reg = <0 0xe66c0000 0 0x8000>;
1024 reg = <0 0xe6560000 0 0x60>; 1033 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
1025 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 1034 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1026 clocks = <&cpg CPG_MOD 518>, 1035 clocks = <&cpg CPG_MOD 914>,
1027 <&cpg CPG_CORE R8A7796_CLK_S3D1>, 1036 <&cpg CPG_CORE R8A7796_CLK_CANFD>,
1028 <&scif_clk>; 1037 <&can_clk>;
1029 clock-names = "fck", "brg_int", "scif_clk"; 1038 clock-names = "fck", "canfd", "can_clk";
1030 dmas = <&dmac1 0x35>, <&dmac1 0x34>, 1039 assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>;
1031 <&dmac2 0x35>, <&dmac2 0x34>; 1040 assigned-clock-rates = <40000000>;
1032 dma-names = "tx", "rx", "tx", "rx";
1033 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 1041 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1034 resets = <&cpg 518>; 1042 resets = <&cpg 914>;
1035 status = "disabled"; 1043 status = "disabled";
1044
1045 channel0 {
1046 status = "disabled";
1047 };
1048
1049 channel1 {
1050 status = "disabled";
1051 };
1036 }; 1052 };
1037 1053
1038 hscif3: serial@e66a0000 { 1054 pwm0: pwm@e6e30000 {
1039 compatible = "renesas,hscif-r8a7796", 1055 compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
1040 "renesas,rcar-gen3-hscif", 1056 reg = <0 0xe6e30000 0 8>;
1041 "renesas,hscif"; 1057 #pwm-cells = <2>;
1042 reg = <0 0xe66a0000 0 0x60>; 1058 clocks = <&cpg CPG_MOD 523>;
1043 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 1059 resets = <&cpg 523>;
1044 clocks = <&cpg CPG_MOD 517>,
1045 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
1046 <&scif_clk>;
1047 clock-names = "fck", "brg_int", "scif_clk";
1048 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
1049 dma-names = "tx", "rx";
1050 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 1060 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1051 resets = <&cpg 517>;
1052 status = "disabled"; 1061 status = "disabled";
1053 }; 1062 };
1054 1063
1055 hscif4: serial@e66b0000 { 1064 pwm1: pwm@e6e31000 {
1056 compatible = "renesas,hscif-r8a7796", 1065 compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
1057 "renesas,rcar-gen3-hscif", 1066 reg = <0 0xe6e31000 0 8>;
1058 "renesas,hscif"; 1067 #pwm-cells = <2>;
1059 reg = <0 0xe66b0000 0 0x60>; 1068 clocks = <&cpg CPG_MOD 523>;
1060 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 1069 resets = <&cpg 523>;
1061 clocks = <&cpg CPG_MOD 516>, 1070 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1062 <&cpg CPG_CORE R8A7796_CLK_S3D1>, 1071 status = "disabled";
1063 <&scif_clk>; 1072 };
1064 clock-names = "fck", "brg_int", "scif_clk"; 1073
1065 dmas = <&dmac0 0x39>, <&dmac0 0x38>; 1074 pwm2: pwm@e6e32000 {
1066 dma-names = "tx", "rx"; 1075 compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
1076 reg = <0 0xe6e32000 0 8>;
1077 #pwm-cells = <2>;
1078 clocks = <&cpg CPG_MOD 523>;
1079 resets = <&cpg 523>;
1080 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1081 status = "disabled";
1082 };
1083
1084 pwm3: pwm@e6e33000 {
1085 compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
1086 reg = <0 0xe6e33000 0 8>;
1087 #pwm-cells = <2>;
1088 clocks = <&cpg CPG_MOD 523>;
1089 resets = <&cpg 523>;
1090 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1091 status = "disabled";
1092 };
1093
1094 pwm4: pwm@e6e34000 {
1095 compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
1096 reg = <0 0xe6e34000 0 8>;
1097 #pwm-cells = <2>;
1098 clocks = <&cpg CPG_MOD 523>;
1099 resets = <&cpg 523>;
1100 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1101 status = "disabled";
1102 };
1103
1104 pwm5: pwm@e6e35000 {
1105 compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
1106 reg = <0 0xe6e35000 0 8>;
1107 #pwm-cells = <2>;
1108 clocks = <&cpg CPG_MOD 523>;
1109 resets = <&cpg 523>;
1110 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1111 status = "disabled";
1112 };
1113
1114 pwm6: pwm@e6e36000 {
1115 compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
1116 reg = <0 0xe6e36000 0 8>;
1117 #pwm-cells = <2>;
1118 clocks = <&cpg CPG_MOD 523>;
1119 resets = <&cpg 523>;
1067 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 1120 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1068 resets = <&cpg 516>;
1069 status = "disabled"; 1121 status = "disabled";
1070 }; 1122 };
1071 1123
@@ -1228,430 +1280,380 @@
1228 status = "disabled"; 1280 status = "disabled";
1229 }; 1281 };
1230 1282
1231 dmac0: dma-controller@e6700000 { 1283 vin0: video@e6ef0000 {
1232 compatible = "renesas,dmac-r8a7796", 1284 compatible = "renesas,vin-r8a7796";
1233 "renesas,rcar-dmac"; 1285 reg = <0 0xe6ef0000 0 0x1000>;
1234 reg = <0 0xe6700000 0 0x10000>; 1286 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
1235 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH 1287 clocks = <&cpg CPG_MOD 811>;
1236 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
1237 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
1238 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
1239 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
1240 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
1241 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
1242 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
1243 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
1244 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
1245 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
1246 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
1247 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
1248 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
1249 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
1250 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH
1251 GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
1252 interrupt-names = "error",
1253 "ch0", "ch1", "ch2", "ch3",
1254 "ch4", "ch5", "ch6", "ch7",
1255 "ch8", "ch9", "ch10", "ch11",
1256 "ch12", "ch13", "ch14", "ch15";
1257 clocks = <&cpg CPG_MOD 219>;
1258 clock-names = "fck";
1259 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 1288 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1260 resets = <&cpg 219>; 1289 resets = <&cpg 811>;
1261 #dma-cells = <1>; 1290 renesas,id = <0>;
1262 dma-channels = <16>; 1291 status = "disabled";
1263 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
1264 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
1265 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
1266 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
1267 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
1268 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
1269 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
1270 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
1271 };
1272 1292
1273 dmac1: dma-controller@e7300000 { 1293 ports {
1274 compatible = "renesas,dmac-r8a7796", 1294 #address-cells = <1>;
1275 "renesas,rcar-dmac"; 1295 #size-cells = <0>;
1276 reg = <0 0xe7300000 0 0x10000>;
1277 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
1278 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
1279 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
1280 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
1281 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
1282 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
1283 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
1284 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
1285 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
1286 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
1287 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
1288 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
1289 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
1290 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
1291 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
1292 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH
1293 GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
1294 interrupt-names = "error",
1295 "ch0", "ch1", "ch2", "ch3",
1296 "ch4", "ch5", "ch6", "ch7",
1297 "ch8", "ch9", "ch10", "ch11",
1298 "ch12", "ch13", "ch14", "ch15";
1299 clocks = <&cpg CPG_MOD 218>;
1300 clock-names = "fck";
1301 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1302 resets = <&cpg 218>;
1303 #dma-cells = <1>;
1304 dma-channels = <16>;
1305 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
1306 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
1307 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
1308 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
1309 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
1310 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
1311 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
1312 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
1313 };
1314 1296
1315 dmac2: dma-controller@e7310000 { 1297 port@1 {
1316 compatible = "renesas,dmac-r8a7796", 1298 #address-cells = <1>;
1317 "renesas,rcar-dmac"; 1299 #size-cells = <0>;
1318 reg = <0 0xe7310000 0 0x10000>;
1319 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH
1320 GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH
1321 GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH
1322 GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH
1323 GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH
1324 GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH
1325 GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH
1326 GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH
1327 GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH
1328 GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH
1329 GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH
1330 GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH
1331 GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH
1332 GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH
1333 GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH
1334 GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH
1335 GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
1336 interrupt-names = "error",
1337 "ch0", "ch1", "ch2", "ch3",
1338 "ch4", "ch5", "ch6", "ch7",
1339 "ch8", "ch9", "ch10", "ch11",
1340 "ch12", "ch13", "ch14", "ch15";
1341 clocks = <&cpg CPG_MOD 217>;
1342 clock-names = "fck";
1343 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1344 resets = <&cpg 217>;
1345 #dma-cells = <1>;
1346 dma-channels = <16>;
1347 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
1348 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
1349 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
1350 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
1351 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
1352 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
1353 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
1354 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
1355 };
1356 1300
1357 audma0: dma-controller@ec700000 { 1301 reg = <1>;
1358 compatible = "renesas,dmac-r8a7796",
1359 "renesas,rcar-dmac";
1360 reg = <0 0xec700000 0 0x10000>;
1361 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH
1362 GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
1363 GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
1364 GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
1365 GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
1366 GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
1367 GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
1368 GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
1369 GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
1370 GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
1371 GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
1372 GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
1373 GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
1374 GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH
1375 GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
1376 GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
1377 GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
1378 interrupt-names = "error",
1379 "ch0", "ch1", "ch2", "ch3",
1380 "ch4", "ch5", "ch6", "ch7",
1381 "ch8", "ch9", "ch10", "ch11",
1382 "ch12", "ch13", "ch14", "ch15";
1383 clocks = <&cpg CPG_MOD 502>;
1384 clock-names = "fck";
1385 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1386 resets = <&cpg 502>;
1387 #dma-cells = <1>;
1388 dma-channels = <16>;
1389 iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>,
1390 <&ipmmu_mp 2>, <&ipmmu_mp 3>,
1391 <&ipmmu_mp 4>, <&ipmmu_mp 5>,
1392 <&ipmmu_mp 6>, <&ipmmu_mp 7>,
1393 <&ipmmu_mp 8>, <&ipmmu_mp 9>,
1394 <&ipmmu_mp 10>, <&ipmmu_mp 11>,
1395 <&ipmmu_mp 12>, <&ipmmu_mp 13>,
1396 <&ipmmu_mp 14>, <&ipmmu_mp 15>;
1397 };
1398 1302
1399 audma1: dma-controller@ec720000 { 1303 vin0csi20: endpoint@0 {
1400 compatible = "renesas,dmac-r8a7796", 1304 reg = <0>;
1401 "renesas,rcar-dmac"; 1305 remote-endpoint= <&csi20vin0>;
1402 reg = <0 0xec720000 0 0x10000>; 1306 };
1403 interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH 1307 vin0csi40: endpoint@2 {
1404 GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH 1308 reg = <2>;
1405 GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH 1309 remote-endpoint= <&csi40vin0>;
1406 GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH 1310 };
1407 GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH 1311 };
1408 GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH 1312 };
1409 GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
1410 GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
1411 GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
1412 GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
1413 GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH
1414 GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
1415 GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
1416 GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH
1417 GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH
1418 GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH
1419 GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
1420 interrupt-names = "error",
1421 "ch0", "ch1", "ch2", "ch3",
1422 "ch4", "ch5", "ch6", "ch7",
1423 "ch8", "ch9", "ch10", "ch11",
1424 "ch12", "ch13", "ch14", "ch15";
1425 clocks = <&cpg CPG_MOD 501>;
1426 clock-names = "fck";
1427 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1428 resets = <&cpg 501>;
1429 #dma-cells = <1>;
1430 dma-channels = <16>;
1431 iommus = <&ipmmu_mp 16>, <&ipmmu_mp 17>,
1432 <&ipmmu_mp 18>, <&ipmmu_mp 19>,
1433 <&ipmmu_mp 20>, <&ipmmu_mp 21>,
1434 <&ipmmu_mp 22>, <&ipmmu_mp 23>,
1435 <&ipmmu_mp 24>, <&ipmmu_mp 25>,
1436 <&ipmmu_mp 26>, <&ipmmu_mp 27>,
1437 <&ipmmu_mp 28>, <&ipmmu_mp 29>,
1438 <&ipmmu_mp 30>, <&ipmmu_mp 31>;
1439 }; 1313 };
1440 1314
1441 usb_dmac0: dma-controller@e65a0000 { 1315 vin1: video@e6ef1000 {
1442 compatible = "renesas,r8a7796-usb-dmac", 1316 compatible = "renesas,vin-r8a7796";
1443 "renesas,usb-dmac"; 1317 reg = <0 0xe6ef1000 0 0x1000>;
1444 reg = <0 0xe65a0000 0 0x100>; 1318 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
1445 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 1319 clocks = <&cpg CPG_MOD 810>;
1446 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
1447 interrupt-names = "ch0", "ch1";
1448 clocks = <&cpg CPG_MOD 330>;
1449 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 1320 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1450 resets = <&cpg 330>; 1321 resets = <&cpg 810>;
1451 #dma-cells = <1>; 1322 renesas,id = <1>;
1452 dma-channels = <2>; 1323 status = "disabled";
1453 };
1454 1324
1455 usb_dmac1: dma-controller@e65b0000 { 1325 ports {
1456 compatible = "renesas,r8a7796-usb-dmac", 1326 #address-cells = <1>;
1457 "renesas,usb-dmac"; 1327 #size-cells = <0>;
1458 reg = <0 0xe65b0000 0 0x100>;
1459 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
1460 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
1461 interrupt-names = "ch0", "ch1";
1462 clocks = <&cpg CPG_MOD 331>;
1463 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1464 resets = <&cpg 331>;
1465 #dma-cells = <1>;
1466 dma-channels = <2>;
1467 };
1468 1328
1469 hsusb: usb@e6590000 { 1329 port@1 {
1470 compatible = "renesas,usbhs-r8a7796", 1330 #address-cells = <1>;
1471 "renesas,rcar-gen3-usbhs"; 1331 #size-cells = <0>;
1472 reg = <0 0xe6590000 0 0x100>; 1332
1473 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1333 reg = <1>;
1474 clocks = <&cpg CPG_MOD 704>; 1334
1475 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, 1335 vin1csi20: endpoint@0 {
1476 <&usb_dmac1 0>, <&usb_dmac1 1>; 1336 reg = <0>;
1477 dma-names = "ch0", "ch1", "ch2", "ch3"; 1337 remote-endpoint= <&csi20vin1>;
1478 renesas,buswait = <11>; 1338 };
1479 phys = <&usb2_phy0>; 1339 vin1csi40: endpoint@2 {
1480 phy-names = "usb"; 1340 reg = <2>;
1481 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 1341 remote-endpoint= <&csi40vin1>;
1482 resets = <&cpg 704>; 1342 };
1483 status = "disabled"; 1343 };
1344 };
1484 }; 1345 };
1485 1346
1486 usb3_phy0: usb-phy@e65ee000 { 1347 vin2: video@e6ef2000 {
1487 compatible = "renesas,r8a7796-usb3-phy", 1348 compatible = "renesas,vin-r8a7796";
1488 "renesas,rcar-gen3-usb3-phy"; 1349 reg = <0 0xe6ef2000 0 0x1000>;
1489 reg = <0 0xe65ee000 0 0x90>; 1350 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1490 clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, 1351 clocks = <&cpg CPG_MOD 809>;
1491 <&usb_extal_clk>;
1492 clock-names = "usb3-if", "usb3s_clk", "usb_extal";
1493 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 1352 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1494 resets = <&cpg 328>; 1353 resets = <&cpg 809>;
1495 #phy-cells = <0>; 1354 renesas,id = <2>;
1496 status = "disabled"; 1355 status = "disabled";
1356
1357 ports {
1358 #address-cells = <1>;
1359 #size-cells = <0>;
1360
1361 port@1 {
1362 #address-cells = <1>;
1363 #size-cells = <0>;
1364
1365 reg = <1>;
1366
1367 vin2csi20: endpoint@0 {
1368 reg = <0>;
1369 remote-endpoint= <&csi20vin2>;
1370 };
1371 vin2csi40: endpoint@2 {
1372 reg = <2>;
1373 remote-endpoint= <&csi40vin2>;
1374 };
1375 };
1376 };
1497 }; 1377 };
1498 1378
1499 xhci0: usb@ee000000 { 1379 vin3: video@e6ef3000 {
1500 compatible = "renesas,xhci-r8a7796", 1380 compatible = "renesas,vin-r8a7796";
1501 "renesas,rcar-gen3-xhci"; 1381 reg = <0 0xe6ef3000 0 0x1000>;
1502 reg = <0 0xee000000 0 0xc00>; 1382 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
1503 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1383 clocks = <&cpg CPG_MOD 808>;
1504 clocks = <&cpg CPG_MOD 328>;
1505 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 1384 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1506 resets = <&cpg 328>; 1385 resets = <&cpg 808>;
1386 renesas,id = <3>;
1507 status = "disabled"; 1387 status = "disabled";
1388
1389 ports {
1390 #address-cells = <1>;
1391 #size-cells = <0>;
1392
1393 port@1 {
1394 #address-cells = <1>;
1395 #size-cells = <0>;
1396
1397 reg = <1>;
1398
1399 vin3csi20: endpoint@0 {
1400 reg = <0>;
1401 remote-endpoint= <&csi20vin3>;
1402 };
1403 vin3csi40: endpoint@2 {
1404 reg = <2>;
1405 remote-endpoint= <&csi40vin3>;
1406 };
1407 };
1408 };
1508 }; 1409 };
1509 1410
1510 usb3_peri0: usb@ee020000 { 1411 vin4: video@e6ef4000 {
1511 compatible = "renesas,r8a7796-usb3-peri", 1412 compatible = "renesas,vin-r8a7796";
1512 "renesas,rcar-gen3-usb3-peri"; 1413 reg = <0 0xe6ef4000 0 0x1000>;
1513 reg = <0 0xee020000 0 0x400>; 1414 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
1514 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 1415 clocks = <&cpg CPG_MOD 807>;
1515 clocks = <&cpg CPG_MOD 328>;
1516 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 1416 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1517 resets = <&cpg 328>; 1417 resets = <&cpg 807>;
1418 renesas,id = <4>;
1518 status = "disabled"; 1419 status = "disabled";
1420
1421 ports {
1422 #address-cells = <1>;
1423 #size-cells = <0>;
1424
1425 port@1 {
1426 #address-cells = <1>;
1427 #size-cells = <0>;
1428
1429 reg = <1>;
1430
1431 vin4csi20: endpoint@0 {
1432 reg = <0>;
1433 remote-endpoint= <&csi20vin4>;
1434 };
1435 vin4csi40: endpoint@2 {
1436 reg = <2>;
1437 remote-endpoint= <&csi40vin4>;
1438 };
1439 };
1440 };
1519 }; 1441 };
1520 1442
1521 ohci0: usb@ee080000 { 1443 vin5: video@e6ef5000 {
1522 compatible = "generic-ohci"; 1444 compatible = "renesas,vin-r8a7796";
1523 reg = <0 0xee080000 0 0x100>; 1445 reg = <0 0xe6ef5000 0 0x1000>;
1524 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1446 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
1525 clocks = <&cpg CPG_MOD 703>; 1447 clocks = <&cpg CPG_MOD 806>;
1526 phys = <&usb2_phy0>;
1527 phy-names = "usb";
1528 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 1448 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1529 resets = <&cpg 703>; 1449 resets = <&cpg 806>;
1450 renesas,id = <5>;
1530 status = "disabled"; 1451 status = "disabled";
1452
1453 ports {
1454 #address-cells = <1>;
1455 #size-cells = <0>;
1456
1457 port@1 {
1458 #address-cells = <1>;
1459 #size-cells = <0>;
1460
1461 reg = <1>;
1462
1463 vin5csi20: endpoint@0 {
1464 reg = <0>;
1465 remote-endpoint= <&csi20vin5>;
1466 };
1467 vin5csi40: endpoint@2 {
1468 reg = <2>;
1469 remote-endpoint= <&csi40vin5>;
1470 };
1471 };
1472 };
1531 }; 1473 };
1532 1474
1533 ehci0: usb@ee080100 { 1475 vin6: video@e6ef6000 {
1534 compatible = "generic-ehci"; 1476 compatible = "renesas,vin-r8a7796";
1535 reg = <0 0xee080100 0 0x100>; 1477 reg = <0 0xe6ef6000 0 0x1000>;
1536 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1478 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
1537 clocks = <&cpg CPG_MOD 703>; 1479 clocks = <&cpg CPG_MOD 805>;
1538 phys = <&usb2_phy0>;
1539 phy-names = "usb";
1540 companion= <&ohci0>;
1541 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 1480 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1542 resets = <&cpg 703>; 1481 resets = <&cpg 805>;
1482 renesas,id = <6>;
1543 status = "disabled"; 1483 status = "disabled";
1484
1485 ports {
1486 #address-cells = <1>;
1487 #size-cells = <0>;
1488
1489 port@1 {
1490 #address-cells = <1>;
1491 #size-cells = <0>;
1492
1493 reg = <1>;
1494
1495 vin6csi20: endpoint@0 {
1496 reg = <0>;
1497 remote-endpoint= <&csi20vin6>;
1498 };
1499 vin6csi40: endpoint@2 {
1500 reg = <2>;
1501 remote-endpoint= <&csi40vin6>;
1502 };
1503 };
1504 };
1544 }; 1505 };
1545 1506
1546 usb2_phy0: usb-phy@ee080200 { 1507 vin7: video@e6ef7000 {
1547 compatible = "renesas,usb2-phy-r8a7796", 1508 compatible = "renesas,vin-r8a7796";
1548 "renesas,rcar-gen3-usb2-phy"; 1509 reg = <0 0xe6ef7000 0 0x1000>;
1549 reg = <0 0xee080200 0 0x700>; 1510 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
1550 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1511 clocks = <&cpg CPG_MOD 804>;
1551 clocks = <&cpg CPG_MOD 703>;
1552 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 1512 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1553 resets = <&cpg 703>; 1513 resets = <&cpg 804>;
1554 #phy-cells = <0>; 1514 renesas,id = <7>;
1555 status = "disabled"; 1515 status = "disabled";
1516
1517 ports {
1518 #address-cells = <1>;
1519 #size-cells = <0>;
1520
1521 port@1 {
1522 #address-cells = <1>;
1523 #size-cells = <0>;
1524
1525 reg = <1>;
1526
1527 vin7csi20: endpoint@0 {
1528 reg = <0>;
1529 remote-endpoint= <&csi20vin7>;
1530 };
1531 vin7csi40: endpoint@2 {
1532 reg = <2>;
1533 remote-endpoint= <&csi40vin7>;
1534 };
1535 };
1536 };
1556 }; 1537 };
1557 1538
1558 ohci1: usb@ee0a0000 { 1539 drif00: rif@e6f40000 {
1559 compatible = "generic-ohci"; 1540 compatible = "renesas,r8a7796-drif",
1560 reg = <0 0xee0a0000 0 0x100>; 1541 "renesas,rcar-gen3-drif";
1561 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1542 reg = <0 0xe6f40000 0 0x64>;
1562 clocks = <&cpg CPG_MOD 702>; 1543 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1563 phys = <&usb2_phy1>; 1544 clocks = <&cpg CPG_MOD 515>;
1564 phy-names = "usb"; 1545 clock-names = "fck";
1546 dmas = <&dmac1 0x20>, <&dmac2 0x20>;
1547 dma-names = "rx", "rx";
1565 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 1548 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1566 resets = <&cpg 702>; 1549 resets = <&cpg 515>;
1550 renesas,bonding = <&drif01>;
1567 status = "disabled"; 1551 status = "disabled";
1568 }; 1552 };
1569 1553
1570 ehci1: usb@ee0a0100 { 1554 drif01: rif@e6f50000 {
1571 compatible = "generic-ehci"; 1555 compatible = "renesas,r8a7796-drif",
1572 reg = <0 0xee0a0100 0 0x100>; 1556 "renesas,rcar-gen3-drif";
1573 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1557 reg = <0 0xe6f50000 0 0x64>;
1574 clocks = <&cpg CPG_MOD 702>; 1558 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1575 phys = <&usb2_phy1>; 1559 clocks = <&cpg CPG_MOD 514>;
1576 phy-names = "usb"; 1560 clock-names = "fck";
1577 companion= <&ohci1>; 1561 dmas = <&dmac1 0x22>, <&dmac2 0x22>;
1562 dma-names = "rx", "rx";
1578 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 1563 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1579 resets = <&cpg 702>; 1564 resets = <&cpg 514>;
1565 renesas,bonding = <&drif00>;
1580 status = "disabled"; 1566 status = "disabled";
1581 }; 1567 };
1582 1568
1583 usb2_phy1: usb-phy@ee0a0200 { 1569 drif10: rif@e6f60000 {
1584 compatible = "renesas,usb2-phy-r8a7796", 1570 compatible = "renesas,r8a7796-drif",
1585 "renesas,rcar-gen3-usb2-phy"; 1571 "renesas,rcar-gen3-drif";
1586 reg = <0 0xee0a0200 0 0x700>; 1572 reg = <0 0xe6f60000 0 0x64>;
1587 clocks = <&cpg CPG_MOD 702>; 1573 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1574 clocks = <&cpg CPG_MOD 513>;
1575 clock-names = "fck";
1576 dmas = <&dmac1 0x24>, <&dmac2 0x24>;
1577 dma-names = "rx", "rx";
1588 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 1578 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1589 resets = <&cpg 702>; 1579 resets = <&cpg 513>;
1590 #phy-cells = <0>; 1580 renesas,bonding = <&drif11>;
1591 status = "disabled"; 1581 status = "disabled";
1592 }; 1582 };
1593 1583
1594 sdhi0: sd@ee100000 { 1584 drif11: rif@e6f70000 {
1595 compatible = "renesas,sdhi-r8a7796", 1585 compatible = "renesas,r8a7796-drif",
1596 "renesas,rcar-gen3-sdhi"; 1586 "renesas,rcar-gen3-drif";
1597 reg = <0 0xee100000 0 0x2000>; 1587 reg = <0 0xe6f70000 0 0x64>;
1598 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 1588 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1599 clocks = <&cpg CPG_MOD 314>; 1589 clocks = <&cpg CPG_MOD 512>;
1600 max-frequency = <200000000>; 1590 clock-names = "fck";
1591 dmas = <&dmac1 0x26>, <&dmac2 0x26>;
1592 dma-names = "rx", "rx";
1601 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 1593 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1602 resets = <&cpg 314>; 1594 resets = <&cpg 512>;
1595 renesas,bonding = <&drif10>;
1603 status = "disabled"; 1596 status = "disabled";
1604 }; 1597 };
1605 1598
1606 sdhi1: sd@ee120000 { 1599 drif20: rif@e6f80000 {
1607 compatible = "renesas,sdhi-r8a7796", 1600 compatible = "renesas,r8a7796-drif",
1608 "renesas,rcar-gen3-sdhi"; 1601 "renesas,rcar-gen3-drif";
1609 reg = <0 0xee120000 0 0x2000>; 1602 reg = <0 0xe6f80000 0 0x64>;
1610 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1603 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1611 clocks = <&cpg CPG_MOD 313>; 1604 clocks = <&cpg CPG_MOD 511>;
1612 max-frequency = <200000000>; 1605 clock-names = "fck";
1606 dmas = <&dmac1 0x28>, <&dmac2 0x28>;
1607 dma-names = "rx", "rx";
1613 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 1608 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1614 resets = <&cpg 313>; 1609 resets = <&cpg 511>;
1610 renesas,bonding = <&drif21>;
1615 status = "disabled"; 1611 status = "disabled";
1616 }; 1612 };
1617 1613
1618 sdhi2: sd@ee140000 { 1614 drif21: rif@e6f90000 {
1619 compatible = "renesas,sdhi-r8a7796", 1615 compatible = "renesas,r8a7796-drif",
1620 "renesas,rcar-gen3-sdhi"; 1616 "renesas,rcar-gen3-drif";
1621 reg = <0 0xee140000 0 0x2000>; 1617 reg = <0 0xe6f90000 0 0x64>;
1622 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 1618 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1623 clocks = <&cpg CPG_MOD 312>; 1619 clocks = <&cpg CPG_MOD 510>;
1624 max-frequency = <200000000>; 1620 clock-names = "fck";
1621 dmas = <&dmac1 0x2a>, <&dmac2 0x2a>;
1622 dma-names = "rx", "rx";
1625 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 1623 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1626 resets = <&cpg 312>; 1624 resets = <&cpg 510>;
1625 renesas,bonding = <&drif20>;
1627 status = "disabled"; 1626 status = "disabled";
1628 }; 1627 };
1629 1628
1630 sdhi3: sd@ee160000 { 1629 drif30: rif@e6fa0000 {
1631 compatible = "renesas,sdhi-r8a7796", 1630 compatible = "renesas,r8a7796-drif",
1632 "renesas,rcar-gen3-sdhi"; 1631 "renesas,rcar-gen3-drif";
1633 reg = <0 0xee160000 0 0x2000>; 1632 reg = <0 0xe6fa0000 0 0x64>;
1634 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 1633 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1635 clocks = <&cpg CPG_MOD 311>; 1634 clocks = <&cpg CPG_MOD 509>;
1636 max-frequency = <200000000>; 1635 clock-names = "fck";
1636 dmas = <&dmac1 0x2c>, <&dmac2 0x2c>;
1637 dma-names = "rx", "rx";
1637 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 1638 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1638 resets = <&cpg 311>; 1639 resets = <&cpg 509>;
1640 renesas,bonding = <&drif31>;
1639 status = "disabled"; 1641 status = "disabled";
1640 }; 1642 };
1641 1643
1642 tsc: thermal@e6198000 { 1644 drif31: rif@e6fb0000 {
1643 compatible = "renesas,r8a7796-thermal"; 1645 compatible = "renesas,r8a7796-drif",
1644 reg = <0 0xe6198000 0 0x100>, 1646 "renesas,rcar-gen3-drif";
1645 <0 0xe61a0000 0 0x100>, 1647 reg = <0 0xe6fb0000 0 0x64>;
1646 <0 0xe61a8000 0 0x100>; 1648 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1647 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 1649 clocks = <&cpg CPG_MOD 508>;
1648 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 1650 clock-names = "fck";
1649 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 1651 dmas = <&dmac1 0x2e>, <&dmac2 0x2e>;
1650 clocks = <&cpg CPG_MOD 522>; 1652 dma-names = "rx", "rx";
1651 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 1653 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1652 resets = <&cpg 522>; 1654 resets = <&cpg 508>;
1653 #thermal-sensor-cells = <1>; 1655 renesas,bonding = <&drif30>;
1654 status = "okay"; 1656 status = "disabled";
1655 }; 1657 };
1656 1658
1657 rcar_sound: sound@ec500000 { 1659 rcar_sound: sound@ec500000 {
@@ -1848,6 +1850,261 @@
1848 dma-names = "rx", "tx", "rxu", "txu"; 1850 dma-names = "rx", "tx", "rxu", "txu";
1849 }; 1851 };
1850 }; 1852 };
1853
1854 ports {
1855 #address-cells = <1>;
1856 #size-cells = <0>;
1857 port@0 {
1858 reg = <0>;
1859 };
1860 port@1 {
1861 reg = <1>;
1862 };
1863 };
1864 };
1865
1866 audma0: dma-controller@ec700000 {
1867 compatible = "renesas,dmac-r8a7796",
1868 "renesas,rcar-dmac";
1869 reg = <0 0xec700000 0 0x10000>;
1870 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH
1871 GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
1872 GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
1873 GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
1874 GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
1875 GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
1876 GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
1877 GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
1878 GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
1879 GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
1880 GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
1881 GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
1882 GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
1883 GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH
1884 GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
1885 GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
1886 GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
1887 interrupt-names = "error",
1888 "ch0", "ch1", "ch2", "ch3",
1889 "ch4", "ch5", "ch6", "ch7",
1890 "ch8", "ch9", "ch10", "ch11",
1891 "ch12", "ch13", "ch14", "ch15";
1892 clocks = <&cpg CPG_MOD 502>;
1893 clock-names = "fck";
1894 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1895 resets = <&cpg 502>;
1896 #dma-cells = <1>;
1897 dma-channels = <16>;
1898 iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>,
1899 <&ipmmu_mp 2>, <&ipmmu_mp 3>,
1900 <&ipmmu_mp 4>, <&ipmmu_mp 5>,
1901 <&ipmmu_mp 6>, <&ipmmu_mp 7>,
1902 <&ipmmu_mp 8>, <&ipmmu_mp 9>,
1903 <&ipmmu_mp 10>, <&ipmmu_mp 11>,
1904 <&ipmmu_mp 12>, <&ipmmu_mp 13>,
1905 <&ipmmu_mp 14>, <&ipmmu_mp 15>;
1906 };
1907
1908 audma1: dma-controller@ec720000 {
1909 compatible = "renesas,dmac-r8a7796",
1910 "renesas,rcar-dmac";
1911 reg = <0 0xec720000 0 0x10000>;
1912 interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH
1913 GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
1914 GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
1915 GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
1916 GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
1917 GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
1918 GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
1919 GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
1920 GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
1921 GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
1922 GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH
1923 GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
1924 GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
1925 GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH
1926 GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH
1927 GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH
1928 GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
1929 interrupt-names = "error",
1930 "ch0", "ch1", "ch2", "ch3",
1931 "ch4", "ch5", "ch6", "ch7",
1932 "ch8", "ch9", "ch10", "ch11",
1933 "ch12", "ch13", "ch14", "ch15";
1934 clocks = <&cpg CPG_MOD 501>;
1935 clock-names = "fck";
1936 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1937 resets = <&cpg 501>;
1938 #dma-cells = <1>;
1939 dma-channels = <16>;
1940 iommus = <&ipmmu_mp 16>, <&ipmmu_mp 17>,
1941 <&ipmmu_mp 18>, <&ipmmu_mp 19>,
1942 <&ipmmu_mp 20>, <&ipmmu_mp 21>,
1943 <&ipmmu_mp 22>, <&ipmmu_mp 23>,
1944 <&ipmmu_mp 24>, <&ipmmu_mp 25>,
1945 <&ipmmu_mp 26>, <&ipmmu_mp 27>,
1946 <&ipmmu_mp 28>, <&ipmmu_mp 29>,
1947 <&ipmmu_mp 30>, <&ipmmu_mp 31>;
1948 };
1949
1950 xhci0: usb@ee000000 {
1951 compatible = "renesas,xhci-r8a7796",
1952 "renesas,rcar-gen3-xhci";
1953 reg = <0 0xee000000 0 0xc00>;
1954 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1955 clocks = <&cpg CPG_MOD 328>;
1956 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1957 resets = <&cpg 328>;
1958 status = "disabled";
1959 };
1960
1961 usb3_peri0: usb@ee020000 {
1962 compatible = "renesas,r8a7796-usb3-peri",
1963 "renesas,rcar-gen3-usb3-peri";
1964 reg = <0 0xee020000 0 0x400>;
1965 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1966 clocks = <&cpg CPG_MOD 328>;
1967 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1968 resets = <&cpg 328>;
1969 status = "disabled";
1970 };
1971
1972 ohci0: usb@ee080000 {
1973 compatible = "generic-ohci";
1974 reg = <0 0xee080000 0 0x100>;
1975 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1976 clocks = <&cpg CPG_MOD 703>;
1977 phys = <&usb2_phy0>;
1978 phy-names = "usb";
1979 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1980 resets = <&cpg 703>;
1981 status = "disabled";
1982 };
1983
1984 ohci1: usb@ee0a0000 {
1985 compatible = "generic-ohci";
1986 reg = <0 0xee0a0000 0 0x100>;
1987 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1988 clocks = <&cpg CPG_MOD 702>;
1989 phys = <&usb2_phy1>;
1990 phy-names = "usb";
1991 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1992 resets = <&cpg 702>;
1993 status = "disabled";
1994 };
1995
1996 ehci0: usb@ee080100 {
1997 compatible = "generic-ehci";
1998 reg = <0 0xee080100 0 0x100>;
1999 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
2000 clocks = <&cpg CPG_MOD 703>;
2001 phys = <&usb2_phy0>;
2002 phy-names = "usb";
2003 companion= <&ohci0>;
2004 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2005 resets = <&cpg 703>;
2006 status = "disabled";
2007 };
2008
2009 ehci1: usb@ee0a0100 {
2010 compatible = "generic-ehci";
2011 reg = <0 0xee0a0100 0 0x100>;
2012 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
2013 clocks = <&cpg CPG_MOD 702>;
2014 phys = <&usb2_phy1>;
2015 phy-names = "usb";
2016 companion= <&ohci1>;
2017 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2018 resets = <&cpg 702>;
2019 status = "disabled";
2020 };
2021
2022 usb2_phy0: usb-phy@ee080200 {
2023 compatible = "renesas,usb2-phy-r8a7796",
2024 "renesas,rcar-gen3-usb2-phy";
2025 reg = <0 0xee080200 0 0x700>;
2026 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
2027 clocks = <&cpg CPG_MOD 703>;
2028 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2029 resets = <&cpg 703>;
2030 #phy-cells = <0>;
2031 status = "disabled";
2032 };
2033
2034 usb2_phy1: usb-phy@ee0a0200 {
2035 compatible = "renesas,usb2-phy-r8a7796",
2036 "renesas,rcar-gen3-usb2-phy";
2037 reg = <0 0xee0a0200 0 0x700>;
2038 clocks = <&cpg CPG_MOD 702>;
2039 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2040 resets = <&cpg 702>;
2041 #phy-cells = <0>;
2042 status = "disabled";
2043 };
2044
2045 sdhi0: sd@ee100000 {
2046 compatible = "renesas,sdhi-r8a7796",
2047 "renesas,rcar-gen3-sdhi";
2048 reg = <0 0xee100000 0 0x2000>;
2049 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
2050 clocks = <&cpg CPG_MOD 314>;
2051 max-frequency = <200000000>;
2052 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2053 resets = <&cpg 314>;
2054 status = "disabled";
2055 };
2056
2057 sdhi1: sd@ee120000 {
2058 compatible = "renesas,sdhi-r8a7796",
2059 "renesas,rcar-gen3-sdhi";
2060 reg = <0 0xee120000 0 0x2000>;
2061 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
2062 clocks = <&cpg CPG_MOD 313>;
2063 max-frequency = <200000000>;
2064 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2065 resets = <&cpg 313>;
2066 status = "disabled";
2067 };
2068
2069 sdhi2: sd@ee140000 {
2070 compatible = "renesas,sdhi-r8a7796",
2071 "renesas,rcar-gen3-sdhi";
2072 reg = <0 0xee140000 0 0x2000>;
2073 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
2074 clocks = <&cpg CPG_MOD 312>;
2075 max-frequency = <200000000>;
2076 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2077 resets = <&cpg 312>;
2078 status = "disabled";
2079 };
2080
2081 sdhi3: sd@ee160000 {
2082 compatible = "renesas,sdhi-r8a7796",
2083 "renesas,rcar-gen3-sdhi";
2084 reg = <0 0xee160000 0 0x2000>;
2085 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
2086 clocks = <&cpg CPG_MOD 311>;
2087 max-frequency = <200000000>;
2088 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2089 resets = <&cpg 311>;
2090 status = "disabled";
2091 };
2092
2093 gic: interrupt-controller@f1010000 {
2094 compatible = "arm,gic-400";
2095 #interrupt-cells = <3>;
2096 #address-cells = <0>;
2097 interrupt-controller;
2098 reg = <0x0 0xf1010000 0 0x1000>,
2099 <0x0 0xf1020000 0 0x20000>,
2100 <0x0 0xf1040000 0 0x20000>,
2101 <0x0 0xf1060000 0 0x20000>;
2102 interrupts = <GIC_PPI 9
2103 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
2104 clocks = <&cpg CPG_MOD 408>;
2105 clock-names = "clk";
2106 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2107 resets = <&cpg 408>;
1851 }; 2108 };
1852 2109
1853 pciec0: pcie@fe000000 { 2110 pciec0: pcie@fe000000 {
@@ -1860,6 +2117,26 @@
1860 /* placeholder */ 2117 /* placeholder */
1861 }; 2118 };
1862 2119
2120 imr-lx4@fe860000 {
2121 compatible = "renesas,r8a7796-imr-lx4",
2122 "renesas,imr-lx4";
2123 reg = <0 0xfe860000 0 0x2000>;
2124 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
2125 clocks = <&cpg CPG_MOD 823>;
2126 power-domains = <&sysc R8A7796_PD_A3VC>;
2127 resets = <&cpg 823>;
2128 };
2129
2130 imr-lx4@fe870000 {
2131 compatible = "renesas,r8a7796-imr-lx4",
2132 "renesas,imr-lx4";
2133 reg = <0 0xfe870000 0 0x2000>;
2134 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
2135 clocks = <&cpg CPG_MOD 822>;
2136 power-domains = <&sysc R8A7796_PD_A3VC>;
2137 resets = <&cpg 822>;
2138 };
2139
1863 fdp1@fe940000 { 2140 fdp1@fe940000 {
1864 compatible = "renesas,fdp1"; 2141 compatible = "renesas,fdp1";
1865 reg = <0 0xfe940000 0 0x2400>; 2142 reg = <0 0xfe940000 0 0x2400>;
@@ -1878,17 +2155,6 @@
1878 resets = <&cpg 615>; 2155 resets = <&cpg 615>;
1879 }; 2156 };
1880 2157
1881 vspb: vsp@fe960000 {
1882 compatible = "renesas,vsp2";
1883 reg = <0 0xfe960000 0 0x8000>;
1884 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
1885 clocks = <&cpg CPG_MOD 626>;
1886 power-domains = <&sysc R8A7796_PD_A3VC>;
1887 resets = <&cpg 626>;
1888
1889 renesas,fcp = <&fcpvb0>;
1890 };
1891
1892 fcpvb0: fcp@fe96f000 { 2158 fcpvb0: fcp@fe96f000 {
1893 compatible = "renesas,fcpv"; 2159 compatible = "renesas,fcpv";
1894 reg = <0 0xfe96f000 0 0x200>; 2160 reg = <0 0xfe96f000 0 0x200>;
@@ -1897,17 +2163,6 @@
1897 resets = <&cpg 607>; 2163 resets = <&cpg 607>;
1898 }; 2164 };
1899 2165
1900 vspi0: vsp@fe9a0000 {
1901 compatible = "renesas,vsp2";
1902 reg = <0 0xfe9a0000 0 0x8000>;
1903 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
1904 clocks = <&cpg CPG_MOD 631>;
1905 power-domains = <&sysc R8A7796_PD_A3VC>;
1906 resets = <&cpg 631>;
1907
1908 renesas,fcp = <&fcpvi0>;
1909 };
1910
1911 fcpvi0: fcp@fe9af000 { 2166 fcpvi0: fcp@fe9af000 {
1912 compatible = "renesas,fcpv"; 2167 compatible = "renesas,fcpv";
1913 reg = <0 0xfe9af000 0 0x200>; 2168 reg = <0 0xfe9af000 0 0x200>;
@@ -1917,6 +2172,44 @@
1917 iommus = <&ipmmu_vc0 19>; 2172 iommus = <&ipmmu_vc0 19>;
1918 }; 2173 };
1919 2174
2175 fcpvd0: fcp@fea27000 {
2176 compatible = "renesas,fcpv";
2177 reg = <0 0xfea27000 0 0x200>;
2178 clocks = <&cpg CPG_MOD 603>;
2179 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2180 resets = <&cpg 603>;
2181 iommus = <&ipmmu_vi0 8>;
2182 };
2183
2184 fcpvd1: fcp@fea2f000 {
2185 compatible = "renesas,fcpv";
2186 reg = <0 0xfea2f000 0 0x200>;
2187 clocks = <&cpg CPG_MOD 602>;
2188 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2189 resets = <&cpg 602>;
2190 iommus = <&ipmmu_vi0 9>;
2191 };
2192
2193 fcpvd2: fcp@fea37000 {
2194 compatible = "renesas,fcpv";
2195 reg = <0 0xfea37000 0 0x200>;
2196 clocks = <&cpg CPG_MOD 601>;
2197 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2198 resets = <&cpg 601>;
2199 iommus = <&ipmmu_vi0 10>;
2200 };
2201
2202 vspb: vsp@fe960000 {
2203 compatible = "renesas,vsp2";
2204 reg = <0 0xfe960000 0 0x8000>;
2205 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
2206 clocks = <&cpg CPG_MOD 626>;
2207 power-domains = <&sysc R8A7796_PD_A3VC>;
2208 resets = <&cpg 626>;
2209
2210 renesas,fcp = <&fcpvb0>;
2211 };
2212
1920 vspd0: vsp@fea20000 { 2213 vspd0: vsp@fea20000 {
1921 compatible = "renesas,vsp2"; 2214 compatible = "renesas,vsp2";
1922 reg = <0 0xfea20000 0 0x8000>; 2215 reg = <0 0xfea20000 0 0x8000>;
@@ -1928,15 +2221,6 @@
1928 renesas,fcp = <&fcpvd0>; 2221 renesas,fcp = <&fcpvd0>;
1929 }; 2222 };
1930 2223
1931 fcpvd0: fcp@fea27000 {
1932 compatible = "renesas,fcpv";
1933 reg = <0 0xfea27000 0 0x200>;
1934 clocks = <&cpg CPG_MOD 603>;
1935 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1936 resets = <&cpg 603>;
1937 iommus = <&ipmmu_vi0 8>;
1938 };
1939
1940 vspd1: vsp@fea28000 { 2224 vspd1: vsp@fea28000 {
1941 compatible = "renesas,vsp2"; 2225 compatible = "renesas,vsp2";
1942 reg = <0 0xfea28000 0 0x8000>; 2226 reg = <0 0xfea28000 0 0x8000>;
@@ -1948,15 +2232,6 @@
1948 renesas,fcp = <&fcpvd1>; 2232 renesas,fcp = <&fcpvd1>;
1949 }; 2233 };
1950 2234
1951 fcpvd1: fcp@fea2f000 {
1952 compatible = "renesas,fcpv";
1953 reg = <0 0xfea2f000 0 0x200>;
1954 clocks = <&cpg CPG_MOD 602>;
1955 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1956 resets = <&cpg 602>;
1957 iommus = <&ipmmu_vi0 9>;
1958 };
1959
1960 vspd2: vsp@fea30000 { 2235 vspd2: vsp@fea30000 {
1961 compatible = "renesas,vsp2"; 2236 compatible = "renesas,vsp2";
1962 reg = <0 0xfea30000 0 0x8000>; 2237 reg = <0 0xfea30000 0 0x8000>;
@@ -1968,13 +2243,126 @@
1968 renesas,fcp = <&fcpvd2>; 2243 renesas,fcp = <&fcpvd2>;
1969 }; 2244 };
1970 2245
1971 fcpvd2: fcp@fea37000 { 2246 vspi0: vsp@fe9a0000 {
1972 compatible = "renesas,fcpv"; 2247 compatible = "renesas,vsp2";
1973 reg = <0 0xfea37000 0 0x200>; 2248 reg = <0 0xfe9a0000 0 0x8000>;
1974 clocks = <&cpg CPG_MOD 601>; 2249 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
2250 clocks = <&cpg CPG_MOD 631>;
2251 power-domains = <&sysc R8A7796_PD_A3VC>;
2252 resets = <&cpg 631>;
2253
2254 renesas,fcp = <&fcpvi0>;
2255 };
2256
2257 csi20: csi2@fea80000 {
2258 compatible = "renesas,r8a7796-csi2";
2259 reg = <0 0xfea80000 0 0x10000>;
2260 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
2261 clocks = <&cpg CPG_MOD 714>;
1975 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 2262 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1976 resets = <&cpg 601>; 2263 resets = <&cpg 714>;
1977 iommus = <&ipmmu_vi0 10>; 2264 status = "disabled";
2265
2266 ports {
2267 #address-cells = <1>;
2268 #size-cells = <0>;
2269
2270 port@1 {
2271 #address-cells = <1>;
2272 #size-cells = <0>;
2273
2274 reg = <1>;
2275
2276 csi20vin0: endpoint@0 {
2277 reg = <0>;
2278 remote-endpoint = <&vin0csi20>;
2279 };
2280 csi20vin1: endpoint@1 {
2281 reg = <1>;
2282 remote-endpoint = <&vin1csi20>;
2283 };
2284 csi20vin2: endpoint@2 {
2285 reg = <2>;
2286 remote-endpoint = <&vin2csi20>;
2287 };
2288 csi20vin3: endpoint@3 {
2289 reg = <3>;
2290 remote-endpoint = <&vin3csi20>;
2291 };
2292 csi20vin4: endpoint@4 {
2293 reg = <4>;
2294 remote-endpoint = <&vin4csi20>;
2295 };
2296 csi20vin5: endpoint@5 {
2297 reg = <5>;
2298 remote-endpoint = <&vin5csi20>;
2299 };
2300 csi20vin6: endpoint@6 {
2301 reg = <6>;
2302 remote-endpoint = <&vin6csi20>;
2303 };
2304 csi20vin7: endpoint@7 {
2305 reg = <7>;
2306 remote-endpoint = <&vin7csi20>;
2307 };
2308 };
2309 };
2310 };
2311
2312 csi40: csi2@feaa0000 {
2313 compatible = "renesas,r8a7796-csi2";
2314 reg = <0 0xfeaa0000 0 0x10000>;
2315 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
2316 clocks = <&cpg CPG_MOD 716>;
2317 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2318 resets = <&cpg 716>;
2319 status = "disabled";
2320
2321 ports {
2322 #address-cells = <1>;
2323 #size-cells = <0>;
2324
2325 port@1 {
2326 #address-cells = <1>;
2327 #size-cells = <0>;
2328
2329 reg = <1>;
2330
2331 csi40vin0: endpoint@0 {
2332 reg = <0>;
2333 remote-endpoint = <&vin0csi40>;
2334 };
2335 csi40vin1: endpoint@1 {
2336 reg = <1>;
2337 remote-endpoint = <&vin1csi40>;
2338 };
2339 csi40vin2: endpoint@2 {
2340 reg = <2>;
2341 remote-endpoint = <&vin2csi40>;
2342 };
2343 csi40vin3: endpoint@3 {
2344 reg = <3>;
2345 remote-endpoint = <&vin3csi40>;
2346 };
2347 csi40vin4: endpoint@4 {
2348 reg = <4>;
2349 remote-endpoint = <&vin4csi40>;
2350 };
2351 csi40vin5: endpoint@5 {
2352 reg = <5>;
2353 remote-endpoint = <&vin5csi40>;
2354 };
2355 csi40vin6: endpoint@6 {
2356 reg = <6>;
2357 remote-endpoint = <&vin6csi40>;
2358 };
2359 csi40vin7: endpoint@7 {
2360 reg = <7>;
2361 remote-endpoint = <&vin7csi40>;
2362 };
2363 };
2364
2365 };
1978 }; 2366 };
1979 2367
1980 hdmi0: hdmi@fead0000 { 2368 hdmi0: hdmi@fead0000 {
@@ -1999,6 +2387,10 @@
1999 port@1 { 2387 port@1 {
2000 reg = <1>; 2388 reg = <1>;
2001 }; 2389 };
2390 port@2 {
2391 /* HDMI sound */
2392 reg = <2>;
2393 };
2002 }; 2394 };
2003 }; 2395 };
2004 2396
@@ -2042,35 +2434,12 @@
2042 }; 2434 };
2043 }; 2435 };
2044 2436
2045 imr-lx4@fe860000 { 2437 prr: chipid@fff00044 {
2046 compatible = "renesas,r8a7796-imr-lx4", 2438 compatible = "renesas,prr";
2047 "renesas,imr-lx4"; 2439 reg = <0 0xfff00044 0 4>;
2048 reg = <0 0xfe860000 0 0x2000>;
2049 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
2050 clocks = <&cpg CPG_MOD 823>;
2051 power-domains = <&sysc R8A7796_PD_A3VC>;
2052 resets = <&cpg 823>;
2053 };
2054
2055 imr-lx4@fe870000 {
2056 compatible = "renesas,r8a7796-imr-lx4",
2057 "renesas,imr-lx4";
2058 reg = <0 0xfe870000 0 0x2000>;
2059 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
2060 clocks = <&cpg CPG_MOD 822>;
2061 power-domains = <&sysc R8A7796_PD_A3VC>;
2062 resets = <&cpg 822>;
2063 }; 2440 };
2064 }; 2441 };
2065 2442
2066 timer {
2067 compatible = "arm,armv8-timer";
2068 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
2069 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
2070 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
2071 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
2072 };
2073
2074 thermal-zones { 2443 thermal-zones {
2075 sensor_thermal1: sensor-thermal1 { 2444 sensor_thermal1: sensor-thermal1 {
2076 polling-delay-passive = <250>; 2445 polling-delay-passive = <250>;
@@ -2080,12 +2449,12 @@
2080 trips { 2449 trips {
2081 sensor1_passive: sensor1-passive { 2450 sensor1_passive: sensor1-passive {
2082 temperature = <95000>; 2451 temperature = <95000>;
2083 hysteresis = <2000>; 2452 hysteresis = <1000>;
2084 type = "passive"; 2453 type = "passive";
2085 }; 2454 };
2086 sensor1_crit: sensor1-crit { 2455 sensor1_crit: sensor1-crit {
2087 temperature = <120000>; 2456 temperature = <120000>;
2088 hysteresis = <2000>; 2457 hysteresis = <1000>;
2089 type = "critical"; 2458 type = "critical";
2090 }; 2459 };
2091 }; 2460 };
@@ -2106,12 +2475,12 @@
2106 trips { 2475 trips {
2107 sensor2_passive: sensor2-passive { 2476 sensor2_passive: sensor2-passive {
2108 temperature = <95000>; 2477 temperature = <95000>;
2109 hysteresis = <2000>; 2478 hysteresis = <1000>;
2110 type = "passive"; 2479 type = "passive";
2111 }; 2480 };
2112 sensor2_crit: sensor2-crit { 2481 sensor2_crit: sensor2-crit {
2113 temperature = <120000>; 2482 temperature = <120000>;
2114 hysteresis = <2000>; 2483 hysteresis = <1000>;
2115 type = "critical"; 2484 type = "critical";
2116 }; 2485 };
2117 }; 2486 };
@@ -2132,12 +2501,12 @@
2132 trips { 2501 trips {
2133 sensor3_passive: sensor3-passive { 2502 sensor3_passive: sensor3-passive {
2134 temperature = <95000>; 2503 temperature = <95000>;
2135 hysteresis = <2000>; 2504 hysteresis = <1000>;
2136 type = "passive"; 2505 type = "passive";
2137 }; 2506 };
2138 sensor3_crit: sensor3-crit { 2507 sensor3_crit: sensor3-crit {
2139 temperature = <120000>; 2508 temperature = <120000>;
2140 hysteresis = <2000>; 2509 hysteresis = <1000>;
2141 type = "critical"; 2510 type = "critical";
2142 }; 2511 };
2143 }; 2512 };
@@ -2151,6 +2520,14 @@
2151 }; 2520 };
2152 }; 2521 };
2153 2522
2523 timer {
2524 compatible = "arm,armv8-timer";
2525 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
2526 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
2527 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
2528 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
2529 };
2530
2154 /* External USB clocks - can be overridden by the board */ 2531 /* External USB clocks - can be overridden by the board */
2155 usb3s0_clk: usb3s0 { 2532 usb3s0_clk: usb3s0 {
2156 compatible = "fixed-clock"; 2533 compatible = "fixed-clock";
diff --git a/arch/arm64/boot/dts/renesas/r8a77965-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a77965-salvator-x.dts
index 75d890d91df9..340a3c72b65a 100644
--- a/arch/arm64/boot/dts/renesas/r8a77965-salvator-x.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77965-salvator-x.dts
@@ -19,3 +19,31 @@
19 reg = <0x0 0x48000000 0x0 0x78000000>; 19 reg = <0x0 0x48000000 0x0 0x78000000>;
20 }; 20 };
21}; 21};
22
23&du {
24 clocks = <&cpg CPG_MOD 724>,
25 <&cpg CPG_MOD 723>,
26 <&cpg CPG_MOD 721>,
27 <&versaclock5 1>,
28 <&x21_clk>,
29 <&versaclock5 2>;
30 clock-names = "du.0", "du.1", "du.3",
31 "dclkin.0", "dclkin.1", "dclkin.3";
32};
33
34&hdmi0 {
35 status = "okay";
36
37 ports {
38 port@1 {
39 reg = <1>;
40 rcar_dw_hdmi0_out: endpoint {
41 remote-endpoint = <&hdmi0_con>;
42 };
43 };
44 };
45};
46
47&hdmi0_con {
48 remote-endpoint = <&rcar_dw_hdmi0_out>;
49};
diff --git a/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts b/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts
index a83a00deed9e..9de4e3db1621 100644
--- a/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts
@@ -19,3 +19,31 @@
19 reg = <0x0 0x48000000 0x0 0x78000000>; 19 reg = <0x0 0x48000000 0x0 0x78000000>;
20 }; 20 };
21}; 21};
22
23&du {
24 clocks = <&cpg CPG_MOD 724>,
25 <&cpg CPG_MOD 723>,
26 <&cpg CPG_MOD 721>,
27 <&versaclock6 1>,
28 <&x21_clk>,
29 <&versaclock6 2>;
30 clock-names = "du.0", "du.1", "du.3",
31 "dclkin.0", "dclkin.1", "dclkin.3";
32};
33
34&hdmi0 {
35 status = "okay";
36
37 ports {
38 port@1 {
39 reg = <1>;
40 rcar_dw_hdmi0_out: endpoint {
41 remote-endpoint = <&hdmi0_con>;
42 };
43 };
44 };
45};
46
47&hdmi0_con {
48 remote-endpoint = <&rcar_dw_hdmi0_out>;
49};
diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
index f0871fcdd984..486aecacb22a 100644
--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
@@ -8,8 +8,9 @@
8 * Copyright (C) 2016 Renesas Electronics Corp. 8 * Copyright (C) 2016 Renesas Electronics Corp.
9 */ 9 */
10 10
11#include <dt-bindings/clock/renesas-cpg-mssr.h> 11#include <dt-bindings/clock/r8a77965-cpg-mssr.h>
12#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h>
13#include <dt-bindings/power/r8a77965-sysc.h>
13 14
14#define CPG_AUDIO_CLK_I 10 15#define CPG_AUDIO_CLK_I 10
15 16
@@ -19,12 +20,44 @@
19 #size-cells = <2>; 20 #size-cells = <2>;
20 21
21 aliases { 22 aliases {
23 i2c0 = &i2c0;
24 i2c1 = &i2c1;
25 i2c2 = &i2c2;
26 i2c3 = &i2c3;
27 i2c4 = &i2c4;
28 i2c5 = &i2c5;
29 i2c6 = &i2c6;
22 i2c7 = &i2c_dvfs; 30 i2c7 = &i2c_dvfs;
23 }; 31 };
24 32
25 psci { 33 /*
26 compatible = "arm,psci-1.0", "arm,psci-0.2"; 34 * The external audio clocks are configured as 0 Hz fixed frequency
27 method = "smc"; 35 * clocks by default.
36 * Boards that provide audio clocks should override them.
37 */
38 audio_clk_a: audio_clk_a {
39 compatible = "fixed-clock";
40 #clock-cells = <0>;
41 clock-frequency = <0>;
42 };
43
44 audio_clk_b: audio_clk_b {
45 compatible = "fixed-clock";
46 #clock-cells = <0>;
47 clock-frequency = <0>;
48 };
49
50 audio_clk_c: audio_clk_c {
51 compatible = "fixed-clock";
52 #clock-cells = <0>;
53 clock-frequency = <0>;
54 };
55
56 /* External CAN clock - to be overridden by boards that provide it */
57 can_clk: can {
58 compatible = "fixed-clock";
59 #clock-cells = <0>;
60 clock-frequency = <0>;
28 }; 61 };
29 62
30 cpus { 63 cpus {
@@ -35,23 +68,23 @@
35 compatible = "arm,cortex-a57", "arm,armv8"; 68 compatible = "arm,cortex-a57", "arm,armv8";
36 reg = <0x0>; 69 reg = <0x0>;
37 device_type = "cpu"; 70 device_type = "cpu";
38 power-domains = <&sysc 0>; 71 power-domains = <&sysc R8A77965_PD_CA57_CPU0>;
39 next-level-cache = <&L2_CA57>; 72 next-level-cache = <&L2_CA57>;
40 enable-method = "psci"; 73 enable-method = "psci";
41 }; 74 };
42 75
43 a57_1: cpu@1 { 76 a57_1: cpu@1 {
44 compatible = "arm,cortex-a57","arm,armv8"; 77 compatible = "arm,cortex-a57", "arm,armv8";
45 reg = <0x1>; 78 reg = <0x1>;
46 device_type = "cpu"; 79 device_type = "cpu";
47 power-domains = <&sysc 1>; 80 power-domains = <&sysc R8A77965_PD_CA57_CPU1>;
48 next-level-cache = <&L2_CA57>; 81 next-level-cache = <&L2_CA57>;
49 enable-method = "psci"; 82 enable-method = "psci";
50 }; 83 };
51 84
52 L2_CA57: cache-controller-0 { 85 L2_CA57: cache-controller-0 {
53 compatible = "cache"; 86 compatible = "cache";
54 power-domains = <&sysc 12>; 87 power-domains = <&sysc R8A77965_PD_CA57_SCU>;
55 cache-unified; 88 cache-unified;
56 cache-level = <2>; 89 cache-level = <2>;
57 }; 90 };
@@ -71,34 +104,24 @@
71 clock-frequency = <0>; 104 clock-frequency = <0>;
72 }; 105 };
73 106
74 /* 107 /* External PCIe clock - can be overridden by the board */
75 * The external audio clocks are configured as 0 Hz fixed frequency 108 pcie_bus_clk: pcie_bus {
76 * clocks by default.
77 * Boards that provide audio clocks should override them.
78 */
79 audio_clk_a: audio_clk_a {
80 compatible = "fixed-clock";
81 #clock-cells = <0>;
82 clock-frequency = <0>;
83 };
84
85 audio_clk_b: audio_clk_b {
86 compatible = "fixed-clock"; 109 compatible = "fixed-clock";
87 #clock-cells = <0>; 110 #clock-cells = <0>;
88 clock-frequency = <0>; 111 clock-frequency = <0>;
89 }; 112 };
90 113
91 audio_clk_c: audio_clk_c { 114 pmu_a57 {
92 compatible = "fixed-clock"; 115 compatible = "arm,cortex-a57-pmu";
93 #clock-cells = <0>; 116 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
94 clock-frequency = <0>; 117 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
118 interrupt-affinity = <&a57_0>,
119 <&a57_1>;
95 }; 120 };
96 121
97 /* External CAN clock - to be overridden by boards that provide it */ 122 psci {
98 can_clk: can { 123 compatible = "arm,psci-1.0", "arm,psci-0.2";
99 compatible = "fixed-clock"; 124 method = "smc";
100 #clock-cells = <0>;
101 clock-frequency = <0>;
102 }; 125 };
103 126
104 /* External SCIF clock - to be overridden by boards that provide it */ 127 /* External SCIF clock - to be overridden by boards that provide it */
@@ -108,42 +131,6 @@
108 clock-frequency = <0>; 131 clock-frequency = <0>;
109 }; 132 };
110 133
111 /* External PCIe clock - can be overridden by the board */
112 pcie_bus_clk: pcie_bus {
113 compatible = "fixed-clock";
114 #clock-cells = <0>;
115 clock-frequency = <0>;
116 };
117
118 /* External USB clocks - can be overridden by the board */
119 usb3s0_clk: usb3s0 {
120 compatible = "fixed-clock";
121 #clock-cells = <0>;
122 clock-frequency = <0>;
123 };
124
125 usb_extal_clk: usb_extal {
126 compatible = "fixed-clock";
127 #clock-cells = <0>;
128 clock-frequency = <0>;
129 };
130
131 timer {
132 compatible = "arm,armv8-timer";
133 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
134 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
135 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
136 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
137 };
138
139 pmu_a57 {
140 compatible = "arm,cortex-a57-pmu";
141 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
142 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
143 interrupt-affinity = <&a57_0>,
144 <&a57_1>;
145 };
146
147 soc { 134 soc {
148 compatible = "simple-bus"; 135 compatible = "simple-bus";
149 interrupt-parent = <&gic>; 136 interrupt-parent = <&gic>;
@@ -151,52 +138,9 @@
151 #size-cells = <2>; 138 #size-cells = <2>;
152 ranges; 139 ranges;
153 140
154 gic: interrupt-controller@f1010000 { 141 wdt0: watchdog@e6020000 {
155 compatible = "arm,gic-400"; 142 reg = <0 0xe6020000 0 0x0c>;
156 #interrupt-cells = <3>; 143 /* placeholder */
157 #address-cells = <0>;
158 interrupt-controller;
159 reg = <0x0 0xf1010000 0 0x1000>,
160 <0x0 0xf1020000 0 0x20000>,
161 <0x0 0xf1040000 0 0x20000>,
162 <0x0 0xf1060000 0 0x20000>;
163 interrupts = <GIC_PPI 9
164 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
165 clocks = <&cpg CPG_MOD 408>;
166 clock-names = "clk";
167 power-domains = <&sysc 32>;
168 resets = <&cpg 408>;
169 };
170
171 pfc: pin-controller@e6060000 {
172 compatible = "renesas,pfc-r8a77965";
173 reg = <0 0xe6060000 0 0x50c>;
174 };
175
176 cpg: clock-controller@e6150000 {
177 compatible = "renesas,r8a77965-cpg-mssr";
178 reg = <0 0xe6150000 0 0x1000>;
179 clocks = <&extal_clk>, <&extalr_clk>;
180 clock-names = "extal", "extalr";
181 #clock-cells = <2>;
182 #power-domain-cells = <0>;
183 #reset-cells = <1>;
184 };
185
186 rst: reset-controller@e6160000 {
187 compatible = "renesas,r8a77965-rst";
188 reg = <0 0xe6160000 0 0x0200>;
189 };
190
191 prr: chipid@fff00044 {
192 compatible = "renesas,prr";
193 reg = <0 0xfff00044 0 4>;
194 };
195
196 sysc: system-controller@e6180000 {
197 compatible = "renesas,r8a77965-sysc";
198 reg = <0 0xe6180000 0 0x0400>;
199 #power-domain-cells = <1>;
200 }; 144 };
201 145
202 gpio0: gpio@e6050000 { 146 gpio0: gpio@e6050000 {
@@ -210,7 +154,7 @@
210 #interrupt-cells = <2>; 154 #interrupt-cells = <2>;
211 interrupt-controller; 155 interrupt-controller;
212 clocks = <&cpg CPG_MOD 912>; 156 clocks = <&cpg CPG_MOD 912>;
213 power-domains = <&sysc 32>; 157 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
214 resets = <&cpg 912>; 158 resets = <&cpg 912>;
215 }; 159 };
216 160
@@ -225,7 +169,7 @@
225 #interrupt-cells = <2>; 169 #interrupt-cells = <2>;
226 interrupt-controller; 170 interrupt-controller;
227 clocks = <&cpg CPG_MOD 911>; 171 clocks = <&cpg CPG_MOD 911>;
228 power-domains = <&sysc 32>; 172 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
229 resets = <&cpg 911>; 173 resets = <&cpg 911>;
230 }; 174 };
231 175
@@ -240,7 +184,7 @@
240 #interrupt-cells = <2>; 184 #interrupt-cells = <2>;
241 interrupt-controller; 185 interrupt-controller;
242 clocks = <&cpg CPG_MOD 910>; 186 clocks = <&cpg CPG_MOD 910>;
243 power-domains = <&sysc 32>; 187 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
244 resets = <&cpg 910>; 188 resets = <&cpg 910>;
245 }; 189 };
246 190
@@ -255,7 +199,7 @@
255 #interrupt-cells = <2>; 199 #interrupt-cells = <2>;
256 interrupt-controller; 200 interrupt-controller;
257 clocks = <&cpg CPG_MOD 909>; 201 clocks = <&cpg CPG_MOD 909>;
258 power-domains = <&sysc 32>; 202 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
259 resets = <&cpg 909>; 203 resets = <&cpg 909>;
260 }; 204 };
261 205
@@ -270,7 +214,7 @@
270 #interrupt-cells = <2>; 214 #interrupt-cells = <2>;
271 interrupt-controller; 215 interrupt-controller;
272 clocks = <&cpg CPG_MOD 908>; 216 clocks = <&cpg CPG_MOD 908>;
273 power-domains = <&sysc 32>; 217 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
274 resets = <&cpg 908>; 218 resets = <&cpg 908>;
275 }; 219 };
276 220
@@ -285,7 +229,7 @@
285 #interrupt-cells = <2>; 229 #interrupt-cells = <2>;
286 interrupt-controller; 230 interrupt-controller;
287 clocks = <&cpg CPG_MOD 907>; 231 clocks = <&cpg CPG_MOD 907>;
288 power-domains = <&sysc 32>; 232 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
289 resets = <&cpg 907>; 233 resets = <&cpg 907>;
290 }; 234 };
291 235
@@ -300,7 +244,7 @@
300 #interrupt-cells = <2>; 244 #interrupt-cells = <2>;
301 interrupt-controller; 245 interrupt-controller;
302 clocks = <&cpg CPG_MOD 906>; 246 clocks = <&cpg CPG_MOD 906>;
303 power-domains = <&sysc 32>; 247 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
304 resets = <&cpg 906>; 248 resets = <&cpg 906>;
305 }; 249 };
306 250
@@ -315,10 +259,51 @@
315 #interrupt-cells = <2>; 259 #interrupt-cells = <2>;
316 interrupt-controller; 260 interrupt-controller;
317 clocks = <&cpg CPG_MOD 905>; 261 clocks = <&cpg CPG_MOD 905>;
318 power-domains = <&sysc 32>; 262 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
319 resets = <&cpg 905>; 263 resets = <&cpg 905>;
320 }; 264 };
321 265
266 pfc: pin-controller@e6060000 {
267 compatible = "renesas,pfc-r8a77965";
268 reg = <0 0xe6060000 0 0x50c>;
269 };
270
271 cpg: clock-controller@e6150000 {
272 compatible = "renesas,r8a77965-cpg-mssr";
273 reg = <0 0xe6150000 0 0x1000>;
274 clocks = <&extal_clk>, <&extalr_clk>;
275 clock-names = "extal", "extalr";
276 #clock-cells = <2>;
277 #power-domain-cells = <0>;
278 #reset-cells = <1>;
279 };
280
281 rst: reset-controller@e6160000 {
282 compatible = "renesas,r8a77965-rst";
283 reg = <0 0xe6160000 0 0x0200>;
284 };
285
286 sysc: system-controller@e6180000 {
287 compatible = "renesas,r8a77965-sysc";
288 reg = <0 0xe6180000 0 0x0400>;
289 #power-domain-cells = <1>;
290 };
291
292 tsc: thermal@e6198000 {
293 compatible = "renesas,r8a77965-thermal";
294 reg = <0 0xe6198000 0 0x100>,
295 <0 0xe61a0000 0 0x100>,
296 <0 0xe61a8000 0 0x100>;
297 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
298 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
299 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
300 clocks = <&cpg CPG_MOD 522>;
301 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
302 resets = <&cpg 522>;
303 #thermal-sensor-cells = <1>;
304 status = "okay";
305 };
306
322 intc_ex: interrupt-controller@e61c0000 { 307 intc_ex: interrupt-controller@e61c0000 {
323 compatible = "renesas,intc-ex-r8a77965", "renesas,irqc"; 308 compatible = "renesas,intc-ex-r8a77965", "renesas,irqc";
324 #interrupt-cells = <2>; 309 #interrupt-cells = <2>;
@@ -331,10 +316,199 @@
331 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 316 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
332 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 317 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
333 clocks = <&cpg CPG_MOD 407>; 318 clocks = <&cpg CPG_MOD 407>;
334 power-domains = <&sysc 32>; 319 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
335 resets = <&cpg 407>; 320 resets = <&cpg 407>;
336 }; 321 };
337 322
323 i2c0: i2c@e6500000 {
324 #address-cells = <1>;
325 #size-cells = <0>;
326 compatible = "renesas,i2c-r8a77965",
327 "renesas,rcar-gen3-i2c";
328 reg = <0 0xe6500000 0 0x40>;
329 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
330 clocks = <&cpg CPG_MOD 931>;
331 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
332 resets = <&cpg 931>;
333 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
334 <&dmac2 0x91>, <&dmac2 0x90>;
335 dma-names = "tx", "rx", "tx", "rx";
336 i2c-scl-internal-delay-ns = <110>;
337 status = "disabled";
338 };
339
340 i2c1: i2c@e6508000 {
341 #address-cells = <1>;
342 #size-cells = <0>;
343 compatible = "renesas,i2c-r8a77965",
344 "renesas,rcar-gen3-i2c";
345 reg = <0 0xe6508000 0 0x40>;
346 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
347 clocks = <&cpg CPG_MOD 930>;
348 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
349 resets = <&cpg 930>;
350 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
351 <&dmac2 0x93>, <&dmac2 0x92>;
352 dma-names = "tx", "rx", "tx", "rx";
353 i2c-scl-internal-delay-ns = <6>;
354 status = "disabled";
355 };
356
357 i2c2: i2c@e6510000 {
358 #address-cells = <1>;
359 #size-cells = <0>;
360 compatible = "renesas,i2c-r8a77965",
361 "renesas,rcar-gen3-i2c";
362 reg = <0 0xe6510000 0 0x40>;
363 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
364 clocks = <&cpg CPG_MOD 929>;
365 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
366 resets = <&cpg 929>;
367 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
368 <&dmac2 0x95>, <&dmac2 0x94>;
369 dma-names = "tx", "rx", "tx", "rx";
370 i2c-scl-internal-delay-ns = <6>;
371 status = "disabled";
372 };
373
374 i2c3: i2c@e66d0000 {
375 #address-cells = <1>;
376 #size-cells = <0>;
377 compatible = "renesas,i2c-r8a77965",
378 "renesas,rcar-gen3-i2c";
379 reg = <0 0xe66d0000 0 0x40>;
380 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
381 clocks = <&cpg CPG_MOD 928>;
382 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
383 resets = <&cpg 928>;
384 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
385 dma-names = "tx", "rx";
386 i2c-scl-internal-delay-ns = <110>;
387 status = "disabled";
388 };
389
390 i2c4: i2c@e66d8000 {
391 #address-cells = <1>;
392 #size-cells = <0>;
393 compatible = "renesas,i2c-r8a77965",
394 "renesas,rcar-gen3-i2c";
395 reg = <0 0xe66d8000 0 0x40>;
396 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
397 clocks = <&cpg CPG_MOD 927>;
398 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
399 resets = <&cpg 927>;
400 dmas = <&dmac0 0x99>, <&dmac0 0x98>;
401 dma-names = "tx", "rx";
402 i2c-scl-internal-delay-ns = <110>;
403 status = "disabled";
404 };
405
406 i2c5: i2c@e66e0000 {
407 #address-cells = <1>;
408 #size-cells = <0>;
409 compatible = "renesas,i2c-r8a77965",
410 "renesas,rcar-gen3-i2c";
411 reg = <0 0xe66e0000 0 0x40>;
412 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
413 clocks = <&cpg CPG_MOD 919>;
414 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
415 resets = <&cpg 919>;
416 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
417 dma-names = "tx", "rx";
418 i2c-scl-internal-delay-ns = <110>;
419 status = "disabled";
420 };
421
422 i2c6: i2c@e66e8000 {
423 #address-cells = <1>;
424 #size-cells = <0>;
425 compatible = "renesas,i2c-r8a77965",
426 "renesas,rcar-gen3-i2c";
427 reg = <0 0xe66e8000 0 0x40>;
428 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
429 clocks = <&cpg CPG_MOD 918>;
430 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
431 resets = <&cpg 918>;
432 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
433 dma-names = "tx", "rx";
434 i2c-scl-internal-delay-ns = <6>;
435 status = "disabled";
436 };
437
438 i2c_dvfs: i2c@e60b0000 {
439 #address-cells = <1>;
440 #size-cells = <0>;
441 compatible = "renesas,iic-r8a77965",
442 "renesas,rcar-gen3-iic",
443 "renesas,rmobile-iic";
444 reg = <0 0xe60b0000 0 0x425>;
445 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
446 clocks = <&cpg CPG_MOD 926>;
447 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
448 resets = <&cpg 926>;
449 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
450 dma-names = "tx", "rx";
451 status = "disabled";
452 };
453
454 hsusb: usb@e6590000 {
455 compatible = "renesas,usbhs-r8a7796",
456 "renesas,rcar-gen3-usbhs";
457 reg = <0 0xe6590000 0 0x100>;
458 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
459 clocks = <&cpg CPG_MOD 704>;
460 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
461 <&usb_dmac1 0>, <&usb_dmac1 1>;
462 dma-names = "ch0", "ch1", "ch2", "ch3";
463 renesas,buswait = <11>;
464 phys = <&usb2_phy0>;
465 phy-names = "usb";
466 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
467 resets = <&cpg 704>;
468 status = "disabled";
469 };
470
471 usb_dmac0: dma-controller@e65a0000 {
472 compatible = "renesas,r8a77965-usb-dmac",
473 "renesas,usb-dmac";
474 reg = <0 0xe65a0000 0 0x100>;
475 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
476 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
477 interrupt-names = "ch0", "ch1";
478 clocks = <&cpg CPG_MOD 330>;
479 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
480 resets = <&cpg 330>;
481 #dma-cells = <1>;
482 dma-channels = <2>;
483 };
484
485 usb_dmac1: dma-controller@e65b0000 {
486 compatible = "renesas,r8a77965-usb-dmac",
487 "renesas,usb-dmac";
488 reg = <0 0xe65b0000 0 0x100>;
489 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
490 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
491 interrupt-names = "ch0", "ch1";
492 clocks = <&cpg CPG_MOD 331>;
493 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
494 resets = <&cpg 331>;
495 #dma-cells = <1>;
496 dma-channels = <2>;
497 };
498
499 usb3_phy0: usb-phy@e65ee000 {
500 compatible = "renesas,r8a77965-usb3-phy",
501 "renesas,rcar-gen3-usb3-phy";
502 reg = <0 0xe65ee000 0 0x90>;
503 clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>,
504 <&usb_extal_clk>;
505 clock-names = "usb3-if", "usb3s_clk", "usb_extal";
506 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
507 resets = <&cpg 328>;
508 #phy-cells = <0>;
509 status = "disabled";
510 };
511
338 dmac0: dma-controller@e6700000 { 512 dmac0: dma-controller@e6700000 {
339 compatible = "renesas,dmac-r8a77965", 513 compatible = "renesas,dmac-r8a77965",
340 "renesas,rcar-dmac"; 514 "renesas,rcar-dmac";
@@ -363,7 +537,7 @@
363 "ch12", "ch13", "ch14", "ch15"; 537 "ch12", "ch13", "ch14", "ch15";
364 clocks = <&cpg CPG_MOD 219>; 538 clocks = <&cpg CPG_MOD 219>;
365 clock-names = "fck"; 539 clock-names = "fck";
366 power-domains = <&sysc 32>; 540 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
367 resets = <&cpg 219>; 541 resets = <&cpg 219>;
368 #dma-cells = <1>; 542 #dma-cells = <1>;
369 dma-channels = <16>; 543 dma-channels = <16>;
@@ -397,7 +571,7 @@
397 "ch12", "ch13", "ch14", "ch15"; 571 "ch12", "ch13", "ch14", "ch15";
398 clocks = <&cpg CPG_MOD 218>; 572 clocks = <&cpg CPG_MOD 218>;
399 clock-names = "fck"; 573 clock-names = "fck";
400 power-domains = <&sysc 32>; 574 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
401 resets = <&cpg 218>; 575 resets = <&cpg 218>;
402 #dma-cells = <1>; 576 #dma-cells = <1>;
403 dma-channels = <16>; 577 dma-channels = <16>;
@@ -431,12 +605,127 @@
431 "ch12", "ch13", "ch14", "ch15"; 605 "ch12", "ch13", "ch14", "ch15";
432 clocks = <&cpg CPG_MOD 217>; 606 clocks = <&cpg CPG_MOD 217>;
433 clock-names = "fck"; 607 clock-names = "fck";
434 power-domains = <&sysc 32>; 608 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
435 resets = <&cpg 217>; 609 resets = <&cpg 217>;
436 #dma-cells = <1>; 610 #dma-cells = <1>;
437 dma-channels = <16>; 611 dma-channels = <16>;
438 }; 612 };
439 613
614 avb: ethernet@e6800000 {
615 compatible = "renesas,etheravb-r8a77965",
616 "renesas,etheravb-rcar-gen3";
617 reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
618 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
619 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
620 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
621 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
622 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
623 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
624 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
625 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
626 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
627 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
628 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
629 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
630 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
631 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
632 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
633 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
634 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
635 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
636 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
637 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
638 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
639 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
640 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
641 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
642 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
643 interrupt-names = "ch0", "ch1", "ch2", "ch3",
644 "ch4", "ch5", "ch6", "ch7",
645 "ch8", "ch9", "ch10", "ch11",
646 "ch12", "ch13", "ch14", "ch15",
647 "ch16", "ch17", "ch18", "ch19",
648 "ch20", "ch21", "ch22", "ch23",
649 "ch24";
650 clocks = <&cpg CPG_MOD 812>;
651 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
652 resets = <&cpg 812>;
653 phy-mode = "rgmii";
654 #address-cells = <1>;
655 #size-cells = <0>;
656 status = "disabled";
657 };
658
659 pwm0: pwm@e6e30000 {
660 compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar";
661 reg = <0 0xe6e30000 0 8>;
662 #pwm-cells = <2>;
663 clocks = <&cpg CPG_MOD 523>;
664 resets = <&cpg 523>;
665 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
666 status = "disabled";
667 };
668
669 pwm1: pwm@e6e31000 {
670 compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar";
671 reg = <0 0xe6e31000 0 8>;
672 #pwm-cells = <2>;
673 clocks = <&cpg CPG_MOD 523>;
674 resets = <&cpg 523>;
675 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
676 status = "disabled";
677 };
678
679 pwm2: pwm@e6e32000 {
680 compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar";
681 reg = <0 0xe6e32000 0 8>;
682 #pwm-cells = <2>;
683 clocks = <&cpg CPG_MOD 523>;
684 resets = <&cpg 523>;
685 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
686 status = "disabled";
687 };
688
689 pwm3: pwm@e6e33000 {
690 compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar";
691 reg = <0 0xe6e33000 0 8>;
692 #pwm-cells = <2>;
693 clocks = <&cpg CPG_MOD 523>;
694 resets = <&cpg 523>;
695 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
696 status = "disabled";
697 };
698
699 pwm4: pwm@e6e34000 {
700 compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar";
701 reg = <0 0xe6e34000 0 8>;
702 #pwm-cells = <2>;
703 clocks = <&cpg CPG_MOD 523>;
704 resets = <&cpg 523>;
705 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
706 status = "disabled";
707 };
708
709 pwm5: pwm@e6e35000 {
710 compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar";
711 reg = <0 0xe6e35000 0 8>;
712 #pwm-cells = <2>;
713 clocks = <&cpg CPG_MOD 523>;
714 resets = <&cpg 523>;
715 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
716 status = "disabled";
717 };
718
719 pwm6: pwm@e6e36000 {
720 compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar";
721 reg = <0 0xe6e36000 0 8>;
722 #pwm-cells = <2>;
723 clocks = <&cpg CPG_MOD 523>;
724 resets = <&cpg 523>;
725 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
726 status = "disabled";
727 };
728
440 scif0: serial@e6e60000 { 729 scif0: serial@e6e60000 {
441 compatible = "renesas,scif-r8a77965", 730 compatible = "renesas,scif-r8a77965",
442 "renesas,rcar-gen3-scif", "renesas,scif"; 731 "renesas,rcar-gen3-scif", "renesas,scif";
@@ -449,7 +738,7 @@
449 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 738 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
450 <&dmac2 0x51>, <&dmac2 0x50>; 739 <&dmac2 0x51>, <&dmac2 0x50>;
451 dma-names = "tx", "rx", "tx", "rx"; 740 dma-names = "tx", "rx", "tx", "rx";
452 power-domains = <&sysc 32>; 741 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
453 resets = <&cpg 207>; 742 resets = <&cpg 207>;
454 status = "disabled"; 743 status = "disabled";
455 }; 744 };
@@ -466,7 +755,7 @@
466 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 755 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
467 <&dmac2 0x53>, <&dmac2 0x52>; 756 <&dmac2 0x53>, <&dmac2 0x52>;
468 dma-names = "tx", "rx", "tx", "rx"; 757 dma-names = "tx", "rx", "tx", "rx";
469 power-domains = <&sysc 32>; 758 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
470 resets = <&cpg 206>; 759 resets = <&cpg 206>;
471 status = "disabled"; 760 status = "disabled";
472 }; 761 };
@@ -480,7 +769,7 @@
480 <&cpg CPG_CORE 20>, 769 <&cpg CPG_CORE 20>,
481 <&scif_clk>; 770 <&scif_clk>;
482 clock-names = "fck", "brg_int", "scif_clk"; 771 clock-names = "fck", "brg_int", "scif_clk";
483 power-domains = <&sysc 32>; 772 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
484 resets = <&cpg 310>; 773 resets = <&cpg 310>;
485 status = "disabled"; 774 status = "disabled";
486 }; 775 };
@@ -496,7 +785,7 @@
496 clock-names = "fck", "brg_int", "scif_clk"; 785 clock-names = "fck", "brg_int", "scif_clk";
497 dmas = <&dmac0 0x57>, <&dmac0 0x56>; 786 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
498 dma-names = "tx", "rx"; 787 dma-names = "tx", "rx";
499 power-domains = <&sysc 32>; 788 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
500 resets = <&cpg 204>; 789 resets = <&cpg 204>;
501 status = "disabled"; 790 status = "disabled";
502 }; 791 };
@@ -512,7 +801,7 @@
512 clock-names = "fck", "brg_int", "scif_clk"; 801 clock-names = "fck", "brg_int", "scif_clk";
513 dmas = <&dmac0 0x59>, <&dmac0 0x58>; 802 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
514 dma-names = "tx", "rx"; 803 dma-names = "tx", "rx";
515 power-domains = <&sysc 32>; 804 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
516 resets = <&cpg 203>; 805 resets = <&cpg 203>;
517 status = "disabled"; 806 status = "disabled";
518 }; 807 };
@@ -529,243 +818,772 @@
529 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, 818 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
530 <&dmac2 0x5b>, <&dmac2 0x5a>; 819 <&dmac2 0x5b>, <&dmac2 0x5a>;
531 dma-names = "tx", "rx", "tx", "rx"; 820 dma-names = "tx", "rx", "tx", "rx";
532 power-domains = <&sysc 32>; 821 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
533 resets = <&cpg 202>; 822 resets = <&cpg 202>;
534 status = "disabled"; 823 status = "disabled";
535 }; 824 };
536 825
537 avb: ethernet@e6800000 { 826 msiof0: spi@e6e90000 {
538 compatible = "renesas,etheravb-r8a77965", 827 compatible = "renesas,msiof-r8a77965",
539 "renesas,etheravb-rcar-gen3"; 828 "renesas,rcar-gen3-msiof";
540 reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; 829 reg = <0 0xe6e90000 0 0x0064>;
541 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 830 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
542 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 831 clocks = <&cpg CPG_MOD 211>;
543 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 832 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
544 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 833 <&dmac2 0x41>, <&dmac2 0x40>;
545 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 834 dma-names = "tx", "rx", "tx", "rx";
546 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 835 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
547 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 836 resets = <&cpg 211>;
548 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
549 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
550 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
551 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
552 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
553 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
554 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
555 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
556 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
557 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
558 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
559 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
560 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
561 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
562 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
563 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
564 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
565 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
566 interrupt-names = "ch0", "ch1", "ch2", "ch3",
567 "ch4", "ch5", "ch6", "ch7",
568 "ch8", "ch9", "ch10", "ch11",
569 "ch12", "ch13", "ch14", "ch15",
570 "ch16", "ch17", "ch18", "ch19",
571 "ch20", "ch21", "ch22", "ch23",
572 "ch24";
573 clocks = <&cpg CPG_MOD 812>;
574 power-domains = <&sysc 32>;
575 resets = <&cpg 812>;
576 phy-mode = "rgmii";
577 #address-cells = <1>; 837 #address-cells = <1>;
578 #size-cells = <0>; 838 #size-cells = <0>;
579 status = "disabled"; 839 status = "disabled";
580 }; 840 };
581 841
582 csi20: csi2@fea80000 { 842 msiof1: spi@e6ea0000 {
583 reg = <0 0xfea80000 0 0x10000>; 843 compatible = "renesas,msiof-r8a77965",
584 /* placeholder */ 844 "renesas,rcar-gen3-msiof";
845 reg = <0 0xe6ea0000 0 0x0064>;
846 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
847 clocks = <&cpg CPG_MOD 210>;
848 dmas = <&dmac1 0x43>, <&dmac1 0x42>,
849 <&dmac2 0x43>, <&dmac2 0x42>;
850 dma-names = "tx", "rx", "tx", "rx";
851 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
852 resets = <&cpg 210>;
853 #address-cells = <1>;
854 #size-cells = <0>;
855 status = "disabled";
856 };
857
858 msiof2: spi@e6c00000 {
859 compatible = "renesas,msiof-r8a77965",
860 "renesas,rcar-gen3-msiof";
861 reg = <0 0xe6c00000 0 0x0064>;
862 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
863 clocks = <&cpg CPG_MOD 209>;
864 dmas = <&dmac0 0x45>, <&dmac0 0x44>;
865 dma-names = "tx", "rx";
866 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
867 resets = <&cpg 209>;
868 #address-cells = <1>;
869 #size-cells = <0>;
870 status = "disabled";
871 };
872
873 msiof3: spi@e6c10000 {
874 compatible = "renesas,msiof-r8a77965",
875 "renesas,rcar-gen3-msiof";
876 reg = <0 0xe6c10000 0 0x0064>;
877 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
878 clocks = <&cpg CPG_MOD 208>;
879 dmas = <&dmac0 0x47>, <&dmac0 0x46>;
880 dma-names = "tx", "rx";
881 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
882 resets = <&cpg 208>;
883 #address-cells = <1>;
884 #size-cells = <0>;
885 status = "disabled";
886 };
887
888 vin0: video@e6ef0000 {
889 compatible = "renesas,vin-r8a77965";
890 reg = <0 0xe6ef0000 0 0x1000>;
891 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
892 clocks = <&cpg CPG_MOD 811>;
893 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
894 resets = <&cpg 811>;
895 renesas,id = <0>;
896 status = "disabled";
585 897
586 ports { 898 ports {
587 #address-cells = <1>; 899 #address-cells = <1>;
588 #size-cells = <0>; 900 #size-cells = <0>;
901
902 port@1 {
903 #address-cells = <1>;
904 #size-cells = <0>;
905
906 reg = <1>;
907
908 vin0csi20: endpoint@0 {
909 reg = <0>;
910 remote-endpoint= <&csi20vin0>;
911 };
912 vin0csi40: endpoint@2 {
913 reg = <2>;
914 remote-endpoint= <&csi40vin0>;
915 };
916 };
589 }; 917 };
590 }; 918 };
591 919
592 csi40: csi2@feaa0000 { 920 vin1: video@e6ef1000 {
593 reg = <0 0xfeaa0000 0 0x10000>; 921 compatible = "renesas,vin-r8a77965";
594 /* placeholder */ 922 reg = <0 0xe6ef1000 0 0x1000>;
923 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
924 clocks = <&cpg CPG_MOD 810>;
925 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
926 resets = <&cpg 810>;
927 renesas,id = <1>;
928 status = "disabled";
595 929
596 ports { 930 ports {
597 #address-cells = <1>; 931 #address-cells = <1>;
598 #size-cells = <0>; 932 #size-cells = <0>;
599 };
600 };
601 933
602 vin0: video@e6ef0000 { 934 port@1 {
603 reg = <0 0xe6ef0000 0 0x1000>; 935 #address-cells = <1>;
604 /* placeholder */ 936 #size-cells = <0>;
605 };
606 937
607 vin1: video@e6ef1000 { 938 reg = <1>;
608 reg = <0 0xe6ef1000 0 0x1000>; 939
609 /* placeholder */ 940 vin1csi20: endpoint@0 {
941 reg = <0>;
942 remote-endpoint= <&csi20vin1>;
943 };
944 vin1csi40: endpoint@2 {
945 reg = <2>;
946 remote-endpoint= <&csi40vin1>;
947 };
948 };
949 };
610 }; 950 };
611 951
612 vin2: video@e6ef2000 { 952 vin2: video@e6ef2000 {
953 compatible = "renesas,vin-r8a77965";
613 reg = <0 0xe6ef2000 0 0x1000>; 954 reg = <0 0xe6ef2000 0 0x1000>;
614 /* placeholder */ 955 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
956 clocks = <&cpg CPG_MOD 809>;
957 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
958 resets = <&cpg 809>;
959 renesas,id = <2>;
960 status = "disabled";
961
962 ports {
963 #address-cells = <1>;
964 #size-cells = <0>;
965
966 port@1 {
967 #address-cells = <1>;
968 #size-cells = <0>;
969
970 reg = <1>;
971
972 vin2csi20: endpoint@0 {
973 reg = <0>;
974 remote-endpoint= <&csi20vin2>;
975 };
976 vin2csi40: endpoint@2 {
977 reg = <2>;
978 remote-endpoint= <&csi40vin2>;
979 };
980 };
981 };
615 }; 982 };
616 983
617 vin3: video@e6ef3000 { 984 vin3: video@e6ef3000 {
985 compatible = "renesas,vin-r8a77965";
618 reg = <0 0xe6ef3000 0 0x1000>; 986 reg = <0 0xe6ef3000 0 0x1000>;
619 /* placeholder */ 987 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
988 clocks = <&cpg CPG_MOD 808>;
989 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
990 resets = <&cpg 808>;
991 renesas,id = <3>;
992 status = "disabled";
993
994 ports {
995 #address-cells = <1>;
996 #size-cells = <0>;
997
998 port@1 {
999 #address-cells = <1>;
1000 #size-cells = <0>;
1001
1002 reg = <1>;
1003
1004 vin3csi20: endpoint@0 {
1005 reg = <0>;
1006 remote-endpoint= <&csi20vin3>;
1007 };
1008 vin3csi40: endpoint@2 {
1009 reg = <2>;
1010 remote-endpoint= <&csi40vin3>;
1011 };
1012 };
1013 };
620 }; 1014 };
621 1015
622 vin4: video@e6ef4000 { 1016 vin4: video@e6ef4000 {
1017 compatible = "renesas,vin-r8a77965";
623 reg = <0 0xe6ef4000 0 0x1000>; 1018 reg = <0 0xe6ef4000 0 0x1000>;
624 /* placeholder */ 1019 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
1020 clocks = <&cpg CPG_MOD 807>;
1021 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
1022 resets = <&cpg 807>;
1023 renesas,id = <4>;
1024 status = "disabled";
1025
1026 ports {
1027 #address-cells = <1>;
1028 #size-cells = <0>;
1029
1030 port@1 {
1031 #address-cells = <1>;
1032 #size-cells = <0>;
1033
1034 reg = <1>;
1035
1036 vin4csi20: endpoint@0 {
1037 reg = <0>;
1038 remote-endpoint= <&csi20vin4>;
1039 };
1040 vin4csi40: endpoint@2 {
1041 reg = <2>;
1042 remote-endpoint= <&csi40vin4>;
1043 };
1044 };
1045 };
625 }; 1046 };
626 1047
627 vin5: video@e6ef5000 { 1048 vin5: video@e6ef5000 {
1049 compatible = "renesas,vin-r8a77965";
628 reg = <0 0xe6ef5000 0 0x1000>; 1050 reg = <0 0xe6ef5000 0 0x1000>;
629 /* placeholder */ 1051 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
1052 clocks = <&cpg CPG_MOD 806>;
1053 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
1054 resets = <&cpg 806>;
1055 renesas,id = <5>;
1056 status = "disabled";
1057
1058 ports {
1059 #address-cells = <1>;
1060 #size-cells = <0>;
1061
1062 port@1 {
1063 #address-cells = <1>;
1064 #size-cells = <0>;
1065
1066 reg = <1>;
1067
1068 vin5csi20: endpoint@0 {
1069 reg = <0>;
1070 remote-endpoint= <&csi20vin5>;
1071 };
1072 vin5csi40: endpoint@2 {
1073 reg = <2>;
1074 remote-endpoint= <&csi40vin5>;
1075 };
1076 };
1077 };
630 }; 1078 };
631 1079
632 vin6: video@e6ef6000 { 1080 vin6: video@e6ef6000 {
1081 compatible = "renesas,vin-r8a77965";
633 reg = <0 0xe6ef6000 0 0x1000>; 1082 reg = <0 0xe6ef6000 0 0x1000>;
634 /* placeholder */ 1083 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
1084 clocks = <&cpg CPG_MOD 805>;
1085 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
1086 resets = <&cpg 805>;
1087 renesas,id = <6>;
1088 status = "disabled";
1089
1090 ports {
1091 #address-cells = <1>;
1092 #size-cells = <0>;
1093
1094 port@1 {
1095 #address-cells = <1>;
1096 #size-cells = <0>;
1097
1098 reg = <1>;
1099
1100 vin6csi20: endpoint@0 {
1101 reg = <0>;
1102 remote-endpoint= <&csi20vin6>;
1103 };
1104 vin6csi40: endpoint@2 {
1105 reg = <2>;
1106 remote-endpoint= <&csi40vin6>;
1107 };
1108 };
1109 };
635 }; 1110 };
636 1111
637 vin7: video@e6ef7000 { 1112 vin7: video@e6ef7000 {
1113 compatible = "renesas,vin-r8a77965";
638 reg = <0 0xe6ef7000 0 0x1000>; 1114 reg = <0 0xe6ef7000 0 0x1000>;
1115 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
1116 clocks = <&cpg CPG_MOD 804>;
1117 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
1118 resets = <&cpg 804>;
1119 renesas,id = <7>;
1120 status = "disabled";
1121
1122 ports {
1123 #address-cells = <1>;
1124 #size-cells = <0>;
1125
1126 port@1 {
1127 #address-cells = <1>;
1128 #size-cells = <0>;
1129
1130 reg = <1>;
1131
1132 vin7csi20: endpoint@0 {
1133 reg = <0>;
1134 remote-endpoint= <&csi20vin7>;
1135 };
1136 vin7csi40: endpoint@2 {
1137 reg = <2>;
1138 remote-endpoint= <&csi40vin7>;
1139 };
1140 };
1141 };
1142 };
1143
1144 rcar_sound: sound@ec500000 {
1145 reg = <0 0xec500000 0 0x1000>, /* SCU */
1146 <0 0xec5a0000 0 0x100>, /* ADG */
1147 <0 0xec540000 0 0x1000>, /* SSIU */
1148 <0 0xec541000 0 0x280>, /* SSI */
1149 <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
639 /* placeholder */ 1150 /* placeholder */
1151
1152 rcar_sound,dvc {
1153 dvc0: dvc-0 {
1154 };
1155 dvc1: dvc-1 {
1156 };
1157 };
1158
1159 rcar_sound,src {
1160 src0: src-0 {
1161 };
1162 src1: src-1 {
1163 };
1164 };
1165
1166 rcar_sound,ssi {
1167 ssi0: ssi-0 {
1168 };
1169 ssi1: ssi-1 {
1170 };
1171 };
1172
1173 ports {
1174 #address-cells = <1>;
1175 #size-cells = <0>;
1176 port@0 {
1177 reg = <0>;
1178 };
1179 };
1180 };
1181
1182 xhci0: usb@ee000000 {
1183 compatible = "renesas,xhci-r8a77965",
1184 "renesas,rcar-gen3-xhci";
1185 reg = <0 0xee000000 0 0xc00>;
1186 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1187 clocks = <&cpg CPG_MOD 328>;
1188 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
1189 resets = <&cpg 328>;
1190 status = "disabled";
1191 };
1192
1193 usb3_peri0: usb@ee020000 {
1194 compatible = "renesas,r8a77965-usb3-peri",
1195 "renesas,rcar-gen3-usb3-peri";
1196 reg = <0 0xee020000 0 0x400>;
1197 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1198 clocks = <&cpg CPG_MOD 328>;
1199 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
1200 resets = <&cpg 328>;
1201 status = "disabled";
640 }; 1202 };
641 1203
642 ohci0: usb@ee080000 { 1204 ohci0: usb@ee080000 {
1205 compatible = "generic-ohci";
643 reg = <0 0xee080000 0 0x100>; 1206 reg = <0 0xee080000 0 0x100>;
644 /* placeholder */ 1207 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1208 clocks = <&cpg CPG_MOD 703>;
1209 phys = <&usb2_phy0>;
1210 phy-names = "usb";
1211 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
1212 resets = <&cpg 703>;
1213 status = "disabled";
1214 };
1215
1216 ohci1: usb@ee0a0000 {
1217 compatible = "generic-ohci";
1218 reg = <0 0xee0a0000 0 0x100>;
1219 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1220 clocks = <&cpg CPG_MOD 702>;
1221 phys = <&usb2_phy1>;
1222 phy-names = "usb";
1223 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
1224 resets = <&cpg 702>;
1225 status = "disabled";
645 }; 1226 };
646 1227
647 ehci0: usb@ee080100 { 1228 ehci0: usb@ee080100 {
1229 compatible = "generic-ehci";
648 reg = <0 0xee080100 0 0x100>; 1230 reg = <0 0xee080100 0 0x100>;
649 /* placeholder */ 1231 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1232 clocks = <&cpg CPG_MOD 703>;
1233 phys = <&usb2_phy0>;
1234 phy-names = "usb";
1235 companion = <&ohci0>;
1236 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
1237 resets = <&cpg 703>;
1238 status = "disabled";
1239 };
1240
1241 ehci1: usb@ee0a0100 {
1242 compatible = "generic-ehci";
1243 reg = <0 0xee0a0100 0 0x100>;
1244 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1245 clocks = <&cpg CPG_MOD 702>;
1246 phys = <&usb2_phy1>;
1247 phy-names = "usb";
1248 companion = <&ohci1>;
1249 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
1250 resets = <&cpg 702>;
1251 status = "disabled";
650 }; 1252 };
651 1253
652 usb2_phy0: usb-phy@ee080200 { 1254 usb2_phy0: usb-phy@ee080200 {
1255 compatible = "renesas,usb2-phy-r8a77965",
1256 "renesas,rcar-gen3-usb2-phy";
653 reg = <0 0xee080200 0 0x700>; 1257 reg = <0 0xee080200 0 0x700>;
654 /* placeholder */ 1258 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1259 clocks = <&cpg CPG_MOD 703>;
1260 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
1261 resets = <&cpg 703>;
1262 #phy-cells = <0>;
1263 status = "disabled";
655 }; 1264 };
656 1265
657 usb2_phy1: usb-phy@ee0a0200 { 1266 usb2_phy1: usb-phy@ee0a0200 {
1267 compatible = "renesas,usb2-phy-r8a77965",
1268 "renesas,rcar-gen3-usb2-phy";
658 reg = <0 0xee0a0200 0 0x700>; 1269 reg = <0 0xee0a0200 0 0x700>;
659 /* placeholder */ 1270 clocks = <&cpg CPG_MOD 703>;
1271 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
1272 resets = <&cpg 703>;
1273 #phy-cells = <0>;
1274 status = "disabled";
660 }; 1275 };
661 1276
662 ohci1: usb@ee0a0000 { 1277 sdhi0: sd@ee100000 {
663 reg = <0 0xee0a0000 0 0x100>; 1278 compatible = "renesas,sdhi-r8a77965",
664 /* placeholder */ 1279 "renesas,rcar-gen3-sdhi";
1280 reg = <0 0xee100000 0 0x2000>;
1281 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
1282 clocks = <&cpg CPG_MOD 314>;
1283 max-frequency = <200000000>;
1284 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
1285 resets = <&cpg 314>;
1286 status = "disabled";
665 }; 1287 };
666 1288
667 ehci1: usb@ee0a0100 { 1289 sdhi1: sd@ee120000 {
668 reg = <0 0xee0a0100 0 0x100>; 1290 compatible = "renesas,sdhi-r8a77965",
669 /* placeholder */ 1291 "renesas,rcar-gen3-sdhi";
1292 reg = <0 0xee120000 0 0x2000>;
1293 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
1294 clocks = <&cpg CPG_MOD 313>;
1295 max-frequency = <200000000>;
1296 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
1297 resets = <&cpg 313>;
1298 status = "disabled";
670 }; 1299 };
671 1300
672 i2c0: i2c@e6500000 { 1301 sdhi2: sd@ee140000 {
673 reg = <0 0xe6500000 0 0x40>; 1302 compatible = "renesas,sdhi-r8a77965",
674 /* placeholder */ 1303 "renesas,rcar-gen3-sdhi";
1304 reg = <0 0xee140000 0 0x2000>;
1305 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
1306 clocks = <&cpg CPG_MOD 312>;
1307 max-frequency = <200000000>;
1308 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
1309 resets = <&cpg 312>;
1310 status = "disabled";
675 }; 1311 };
676 1312
677 i2c1: i2c@e6508000 { 1313 sdhi3: sd@ee160000 {
678 reg = <0 0xe6508000 0 0x40>; 1314 compatible = "renesas,sdhi-r8a77965",
679 /* placeholder */ 1315 "renesas,rcar-gen3-sdhi";
1316 reg = <0 0xee160000 0 0x2000>;
1317 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
1318 clocks = <&cpg CPG_MOD 311>;
1319 max-frequency = <200000000>;
1320 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
1321 resets = <&cpg 311>;
1322 status = "disabled";
680 }; 1323 };
681 1324
682 i2c2: i2c@e6510000 { 1325 gic: interrupt-controller@f1010000 {
683 #address-cells = <1>; 1326 compatible = "arm,gic-400";
684 #size-cells = <0>; 1327 #interrupt-cells = <3>;
1328 #address-cells = <0>;
1329 interrupt-controller;
1330 reg = <0x0 0xf1010000 0 0x1000>,
1331 <0x0 0xf1020000 0 0x20000>,
1332 <0x0 0xf1040000 0 0x20000>,
1333 <0x0 0xf1060000 0 0x20000>;
1334 interrupts = <GIC_PPI 9
1335 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
1336 clocks = <&cpg CPG_MOD 408>;
1337 clock-names = "clk";
1338 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
1339 resets = <&cpg 408>;
1340 };
685 1341
686 reg = <0 0xe6510000 0 0x40>; 1342 pciec0: pcie@fe000000 {
1343 reg = <0 0xfe000000 0 0x80000>;
687 /* placeholder */ 1344 /* placeholder */
688 }; 1345 };
689 1346
690 i2c3: i2c@e66d0000 { 1347 pciec1: pcie@ee800000 {
691 reg = <0 0xe66d0000 0 0x40>; 1348 reg = <0 0xee800000 0 0x80000>;
692 /* placeholder */ 1349 /* placeholder */
693 }; 1350 };
694 1351
695 i2c4: i2c@e66d8000 { 1352 fcpf0: fcp@fe950000 {
696 #address-cells = <1>; 1353 compatible = "renesas,fcpf";
697 #size-cells = <0>; 1354 reg = <0 0xfe950000 0 0x200>;
1355 clocks = <&cpg CPG_MOD 615>;
1356 power-domains = <&sysc R8A77965_PD_A3VP>;
1357 resets = <&cpg 615>;
1358 };
698 1359
699 reg = <0 0xe66d8000 0 0x40>; 1360 vspb: vsp@fe960000 {
700 /* placeholder */ 1361 compatible = "renesas,vsp2";
1362 reg = <0 0xfe960000 0 0x8000>;
1363 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
1364 clocks = <&cpg CPG_MOD 626>;
1365 power-domains = <&sysc R8A77965_PD_A3VP>;
1366 resets = <&cpg 626>;
1367
1368 renesas,fcp = <&fcpvb0>;
701 }; 1369 };
702 1370
703 i2c5: i2c@e66e0000 { 1371 fcpvb0: fcp@fe96f000 {
704 reg = <0 0xe66e0000 0 0x40>; 1372 compatible = "renesas,fcpv";
705 /* placeholder */ 1373 reg = <0 0xfe96f000 0 0x200>;
1374 clocks = <&cpg CPG_MOD 607>;
1375 power-domains = <&sysc R8A77965_PD_A3VP>;
1376 resets = <&cpg 607>;
706 }; 1377 };
707 1378
708 i2c6: i2c@e66e8000 { 1379 vspi0: vsp@fe9a0000 {
709 reg = <0 0xe66e8000 0 0x40>; 1380 compatible = "renesas,vsp2";
710 /* placeholder */ 1381 reg = <0 0xfe9a0000 0 0x8000>;
1382 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
1383 clocks = <&cpg CPG_MOD 631>;
1384 power-domains = <&sysc R8A77965_PD_A3VP>;
1385 resets = <&cpg 631>;
1386
1387 renesas,fcp = <&fcpvi0>;
711 }; 1388 };
712 1389
713 i2c_dvfs: i2c@e60b0000 { 1390 fcpvi0: fcp@fe9af000 {
714 #address-cells = <1>; 1391 compatible = "renesas,fcpv";
715 #size-cells = <0>; 1392 reg = <0 0xfe9af000 0 0x200>;
716 compatible = "renesas,iic-r8a77965", 1393 clocks = <&cpg CPG_MOD 611>;
717 "renesas,rcar-gen3-iic", 1394 power-domains = <&sysc R8A77965_PD_A3VP>;
718 "renesas,rmobile-iic"; 1395 resets = <&cpg 611>;
719 reg = <0 0xe60b0000 0 0x425>;
720 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
721 clocks = <&cpg CPG_MOD 926>;
722 power-domains = <&sysc 32>;
723 resets = <&cpg 926>;
724 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
725 dma-names = "tx", "rx";
726 status = "disabled";
727 }; 1396 };
728 1397
729 pwm0: pwm@e6e30000 { 1398 vspd0: vsp@fea20000 {
730 reg = <0 0xe6e30000 0 8>; 1399 compatible = "renesas,vsp2";
731 /* placeholder */ 1400 reg = <0 0xfea20000 0 0x8000>;
1401 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
1402 clocks = <&cpg CPG_MOD 623>;
1403 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
1404 resets = <&cpg 623>;
1405
1406 renesas,fcp = <&fcpvd0>;
732 }; 1407 };
733 1408
734 pwm1: pwm@e6e31000 { 1409 fcpvd0: fcp@fea27000 {
735 reg = <0 0xe6e31000 0 8>; 1410 compatible = "renesas,fcpv";
736 #pwm-cells = <2>; 1411 reg = <0 0xfea27000 0 0x200>;
737 /* placeholder */ 1412 clocks = <&cpg CPG_MOD 603>;
1413 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
1414 resets = <&cpg 603>;
738 }; 1415 };
739 1416
740 pwm2: pwm@e6e32000 { 1417 vspd1: vsp@fea28000 {
741 reg = <0 0xe6e32000 0 8>; 1418 compatible = "renesas,vsp2";
742 /* placeholder */ 1419 reg = <0 0xfea28000 0 0x8000>;
1420 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
1421 clocks = <&cpg CPG_MOD 622>;
1422 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
1423 resets = <&cpg 622>;
1424
1425 renesas,fcp = <&fcpvd1>;
743 }; 1426 };
744 1427
745 pwm3: pwm@e6e33000 { 1428 fcpvd1: fcp@fea2f000 {
746 reg = <0 0xe6e33000 0 8>; 1429 compatible = "renesas,fcpv";
747 /* placeholder */ 1430 reg = <0 0xfea2f000 0 0x200>;
1431 clocks = <&cpg CPG_MOD 602>;
1432 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
1433 resets = <&cpg 602>;
748 }; 1434 };
749 1435
750 pwm4: pwm@e6e34000 { 1436 csi20: csi2@fea80000 {
751 reg = <0 0xe6e34000 0 8>; 1437 compatible = "renesas,r8a77965-csi2";
752 /* placeholder */ 1438 reg = <0 0xfea80000 0 0x10000>;
1439 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
1440 clocks = <&cpg CPG_MOD 714>;
1441 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
1442 resets = <&cpg 714>;
1443 status = "disabled";
1444
1445 ports {
1446 #address-cells = <1>;
1447 #size-cells = <0>;
1448
1449 port@1 {
1450 #address-cells = <1>;
1451 #size-cells = <0>;
1452
1453 reg = <1>;
1454
1455 csi20vin0: endpoint@0 {
1456 reg = <0>;
1457 remote-endpoint = <&vin0csi20>;
1458 };
1459 csi20vin1: endpoint@1 {
1460 reg = <1>;
1461 remote-endpoint = <&vin1csi20>;
1462 };
1463 csi20vin2: endpoint@2 {
1464 reg = <2>;
1465 remote-endpoint = <&vin2csi20>;
1466 };
1467 csi20vin3: endpoint@3 {
1468 reg = <3>;
1469 remote-endpoint = <&vin3csi20>;
1470 };
1471 csi20vin4: endpoint@4 {
1472 reg = <4>;
1473 remote-endpoint = <&vin4csi20>;
1474 };
1475 csi20vin5: endpoint@5 {
1476 reg = <5>;
1477 remote-endpoint = <&vin5csi20>;
1478 };
1479 csi20vin6: endpoint@6 {
1480 reg = <6>;
1481 remote-endpoint = <&vin6csi20>;
1482 };
1483 csi20vin7: endpoint@7 {
1484 reg = <7>;
1485 remote-endpoint = <&vin7csi20>;
1486 };
1487 };
1488 };
753 }; 1489 };
754 1490
755 pwm5: pwm@e6e35000 { 1491 csi40: csi2@feaa0000 {
756 reg = <0 0xe6e35000 0 8>; 1492 compatible = "renesas,r8a77965-csi2";
757 /* placeholder */ 1493 reg = <0 0xfeaa0000 0 0x10000>;
1494 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
1495 clocks = <&cpg CPG_MOD 716>;
1496 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
1497 resets = <&cpg 716>;
1498 status = "disabled";
1499
1500 ports {
1501 #address-cells = <1>;
1502 #size-cells = <0>;
1503
1504 port@1 {
1505 #address-cells = <1>;
1506 #size-cells = <0>;
1507
1508 reg = <1>;
1509
1510 csi40vin0: endpoint@0 {
1511 reg = <0>;
1512 remote-endpoint = <&vin0csi40>;
1513 };
1514 csi40vin1: endpoint@1 {
1515 reg = <1>;
1516 remote-endpoint = <&vin1csi40>;
1517 };
1518 csi40vin2: endpoint@2 {
1519 reg = <2>;
1520 remote-endpoint = <&vin2csi40>;
1521 };
1522 csi40vin3: endpoint@3 {
1523 reg = <3>;
1524 remote-endpoint = <&vin3csi40>;
1525 };
1526 csi40vin4: endpoint@4 {
1527 reg = <4>;
1528 remote-endpoint = <&vin4csi40>;
1529 };
1530 csi40vin5: endpoint@5 {
1531 reg = <5>;
1532 remote-endpoint = <&vin5csi40>;
1533 };
1534 csi40vin6: endpoint@6 {
1535 reg = <6>;
1536 remote-endpoint = <&vin6csi40>;
1537 };
1538 csi40vin7: endpoint@7 {
1539 reg = <7>;
1540 remote-endpoint = <&vin7csi40>;
1541 };
1542 };
1543 };
758 }; 1544 };
759 1545
760 pwm6: pwm@e6e36000 { 1546 hdmi0: hdmi@fead0000 {
761 reg = <0 0xe6e36000 0 8>; 1547 compatible = "renesas,r8a77965-hdmi",
762 /* placeholder */ 1548 "renesas,rcar-gen3-hdmi";
1549 reg = <0 0xfead0000 0 0x10000>;
1550 interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
1551 clocks = <&cpg CPG_MOD 729>,
1552 <&cpg CPG_CORE R8A77965_CLK_HDMI>;
1553 clock-names = "iahb", "isfr";
1554 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
1555 resets = <&cpg 729>;
1556 status = "disabled";
1557
1558 ports {
1559 #address-cells = <1>;
1560 #size-cells = <0>;
1561 port@0 {
1562 reg = <0>;
1563 dw_hdmi0_in: endpoint {
1564 remote-endpoint = <&du_out_hdmi0>;
1565 };
1566 };
1567 port@1 {
1568 reg = <1>;
1569 };
1570 };
763 }; 1571 };
764 1572
765 du: display@feb00000 { 1573 du: display@feb00000 {
766 reg = <0 0xfeb00000 0 0x80000>, 1574 compatible = "renesas,du-r8a77965";
767 <0 0xfeb90000 0 0x14>; 1575 reg = <0 0xfeb00000 0 0x80000>;
768 /* placeholder */ 1576 reg-names = "du";
1577 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
1578 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
1579 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
1580 clocks = <&cpg CPG_MOD 724>,
1581 <&cpg CPG_MOD 723>,
1582 <&cpg CPG_MOD 721>;
1583 clock-names = "du.0", "du.1", "du.3";
1584 status = "disabled";
1585
1586 vsps = <&vspd0 0 &vspd1 0 &vspd0 1>;
769 1587
770 ports { 1588 ports {
771 #address-cells = <1>; 1589 #address-cells = <1>;
@@ -779,6 +1597,7 @@
779 port@1 { 1597 port@1 {
780 reg = <1>; 1598 reg = <1>;
781 du_out_hdmi0: endpoint { 1599 du_out_hdmi0: endpoint {
1600 remote-endpoint = <&dw_hdmi0_in>;
782 }; 1601 };
783 }; 1602 };
784 port@2 { 1603 port@2 {
@@ -789,90 +1608,74 @@
789 }; 1608 };
790 }; 1609 };
791 1610
792 hsusb: usb@e6590000 { 1611 prr: chipid@fff00044 {
793 reg = <0 0xe6590000 0 0x100>; 1612 compatible = "renesas,prr";
794 /* placeholder */ 1613 reg = <0 0xfff00044 0 4>;
795 };
796
797 pciec0: pcie@fe000000 {
798 reg = <0 0xfe000000 0 0x80000>;
799 /* placeholder */
800 };
801
802 pciec1: pcie@ee800000 {
803 reg = <0 0xee800000 0 0x80000>;
804 /* placeholder */
805 }; 1614 };
1615 };
806 1616
807 rcar_sound: sound@ec500000 { 1617 timer {
808 reg = <0 0xec500000 0 0x1000>, /* SCU */ 1618 compatible = "arm,armv8-timer";
809 <0 0xec5a0000 0 0x100>, /* ADG */ 1619 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
810 <0 0xec540000 0 0x1000>, /* SSIU */ 1620 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
811 <0 0xec541000 0 0x280>, /* SSI */ 1621 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
812 <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ 1622 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
813 /* placeholder */ 1623 };
814 1624
815 rcar_sound,dvc { 1625 thermal-zones {
816 dvc0: dvc-0 { 1626 sensor_thermal1: sensor-thermal1 {
817 }; 1627 polling-delay-passive = <250>;
818 dvc1: dvc-1 { 1628 polling-delay = <1000>;
1629 thermal-sensors = <&tsc 0>;
1630
1631 trips {
1632 sensor1_crit: sensor1-crit {
1633 temperature = <120000>;
1634 hysteresis = <1000>;
1635 type = "critical";
819 }; 1636 };
820 }; 1637 };
1638 };
821 1639
822 rcar_sound,src { 1640 sensor_thermal2: sensor-thermal2 {
823 src0: src-0 { 1641 polling-delay-passive = <250>;
824 }; 1642 polling-delay = <1000>;
825 src1: src-1 { 1643 thermal-sensors = <&tsc 1>;
826 };
827 };
828 1644
829 rcar_sound,ssi { 1645 trips {
830 ssi0: ssi-0 { 1646 sensor2_crit: sensor2-crit {
831 }; 1647 temperature = <120000>;
832 ssi1: ssi-1 { 1648 hysteresis = <1000>;
1649 type = "critical";
833 }; 1650 };
834 }; 1651 };
835 }; 1652 };
836 1653
837 sdhi0: sd@ee100000 { 1654 sensor_thermal3: sensor-thermal3 {
838 reg = <0 0xee100000 0 0x2000>; 1655 polling-delay-passive = <250>;
839 /* placeholder */ 1656 polling-delay = <1000>;
840 }; 1657 thermal-sensors = <&tsc 2>;
841
842 sdhi1: sd@ee120000 {
843 reg = <0 0xee120000 0 0x2000>;
844 /* placeholder */
845 };
846 1658
847 sdhi2: sd@ee140000 { 1659 trips {
848 reg = <0 0xee140000 0 0x2000>; 1660 sensor3_crit: sensor3-crit {
849 /* placeholder */ 1661 temperature = <120000>;
850 }; 1662 hysteresis = <1000>;
851 1663 type = "critical";
852 sdhi3: sd@ee160000 { 1664 };
853 reg = <0 0xee160000 0 0x2000>; 1665 };
854 /* placeholder */
855 };
856
857 usb3_phy0: usb-phy@e65ee000 {
858 reg = <0 0xe65ee000 0 0x90>;
859 #phy-cells = <0>;
860 /* placeholder */
861 };
862
863 usb3_peri0: usb@ee020000 {
864 reg = <0 0xee020000 0 0x400>;
865 /* placeholder */
866 }; 1666 };
1667 };
867 1668
868 xhci0: usb@ee000000 { 1669 /* External USB clocks - can be overridden by the board */
869 reg = <0 0xee000000 0 0xc00>; 1670 usb3s0_clk: usb3s0 {
870 /* placeholder */ 1671 compatible = "fixed-clock";
871 }; 1672 #clock-cells = <0>;
1673 clock-frequency = <0>;
1674 };
872 1675
873 wdt0: watchdog@e6020000 { 1676 usb_extal_clk: usb_extal {
874 reg = <0 0xe6020000 0 0x0c>; 1677 compatible = "fixed-clock";
875 /* placeholder */ 1678 #clock-cells = <0>;
876 }; 1679 clock-frequency = <0>;
877 }; 1680 };
878}; 1681};
diff --git a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
index 3c5f598c9766..21f9cf5c6e84 100644
--- a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
@@ -31,9 +31,57 @@
31 /* first 128MB is reserved for secure area. */ 31 /* first 128MB is reserved for secure area. */
32 reg = <0x0 0x48000000 0x0 0x38000000>; 32 reg = <0x0 0x48000000 0x0 0x38000000>;
33 }; 33 };
34
35 hdmi-out {
36 compatible = "hdmi-connector";
37 type = "a";
38
39 port {
40 hdmi_con_out: endpoint {
41 remote-endpoint = <&adv7511_out>;
42 };
43 };
44 };
45
46 d3p3: regulator-fixed {
47 compatible = "regulator-fixed";
48 regulator-name = "fixed-3.3V";
49 regulator-min-microvolt = <3300000>;
50 regulator-max-microvolt = <3300000>;
51 regulator-boot-on;
52 regulator-always-on;
53 };
54
55 lvds-decoder {
56 compatible = "thine,thc63lvd1024";
57
58 vcc-supply = <&d3p3>;
59
60 ports {
61 #address-cells = <1>;
62 #size-cells = <0>;
63
64 port@0 {
65 reg = <0>;
66 thc63lvd1024_in: endpoint {
67 remote-endpoint = <&lvds0_out>;
68 };
69 };
70
71 port@2 {
72 reg = <2>;
73 thc63lvd1024_out: endpoint {
74 remote-endpoint = <&adv7511_in>;
75 };
76 };
77 };
78 };
34}; 79};
35 80
36&avb { 81&avb {
82 pinctrl-0 = <&avb_pins>;
83 pinctrl-names = "default";
84
37 renesas,no-ether-link; 85 renesas,no-ether-link;
38 phy-handle = <&phy0>; 86 phy-handle = <&phy0>;
39 phy-mode = "rgmii-id"; 87 phy-mode = "rgmii-id";
@@ -47,6 +95,16 @@
47 }; 95 };
48}; 96};
49 97
98&canfd {
99 pinctrl-0 = <&canfd0_pins>;
100 pinctrl-names = "default";
101 status = "okay";
102
103 channel0 {
104 status = "okay";
105 };
106};
107
50&extal_clk { 108&extal_clk {
51 clock-frequency = <16666666>; 109 clock-frequency = <16666666>;
52}; 110};
@@ -68,9 +126,51 @@
68 gpio-controller; 126 gpio-controller;
69 #gpio-cells = <2>; 127 #gpio-cells = <2>;
70 }; 128 };
129
130 hdmi@39 {
131 compatible = "adi,adv7511w";
132 reg = <0x39>;
133 interrupt-parent = <&gpio1>;
134 interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
135
136 adi,input-depth = <8>;
137 adi,input-colorspace = "rgb";
138 adi,input-clock = "1x";
139 adi,input-style = <1>;
140 adi,input-justification = "evenly";
141
142 ports {
143 #address-cells = <1>;
144 #size-cells = <0>;
145
146 port@0 {
147 reg = <0>;
148 adv7511_in: endpoint {
149 remote-endpoint = <&thc63lvd1024_out>;
150 };
151 };
152
153 port@1 {
154 reg = <1>;
155 adv7511_out: endpoint {
156 remote-endpoint = <&hdmi_con_out>;
157 };
158 };
159 };
160 };
71}; 161};
72 162
73&pfc { 163&pfc {
164 avb_pins: avb0 {
165 groups = "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk";
166 function = "avb0";
167 };
168
169 canfd0_pins: canfd0 {
170 groups = "canfd0_data_a";
171 function = "canfd0";
172 };
173
74 i2c0_pins: i2c0 { 174 i2c0_pins: i2c0 {
75 groups = "i2c0"; 175 groups = "i2c0";
76 function = "i2c0"; 176 function = "i2c0";
@@ -93,3 +193,19 @@
93 193
94 status = "okay"; 194 status = "okay";
95}; 195};
196
197&du {
198 status = "okay";
199};
200
201&lvds0 {
202 status = "okay";
203
204 ports {
205 port@1 {
206 lvds0_out: endpoint {
207 remote-endpoint = <&thc63lvd1024_in>;
208 };
209 };
210 };
211};
diff --git a/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts b/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts
index a8ceeac77992..9fce031a596f 100644
--- a/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts
@@ -29,9 +29,71 @@
29 /* first 128MB is reserved for secure area. */ 29 /* first 128MB is reserved for secure area. */
30 reg = <0x0 0x48000000 0x0 0x38000000>; 30 reg = <0x0 0x48000000 0x0 0x38000000>;
31 }; 31 };
32
33 osc5_clk: osc5-clock {
34 compatible = "fixed-clock";
35 #clock-cells = <0>;
36 clock-frequency = <148500000>;
37 };
38
39 vcc_d1_8v: regulator-0 {
40 compatible = "regulator-fixed";
41 regulator-name = "VCC_D1.8V";
42 regulator-min-microvolt = <1800000>;
43 regulator-max-microvolt = <1800000>;
44 regulator-boot-on;
45 regulator-always-on;
46 };
47
48 vcc_d3_3v: regulator-1 {
49 compatible = "regulator-fixed";
50 regulator-name = "VCC_D3.3V";
51 regulator-min-microvolt = <3300000>;
52 regulator-max-microvolt = <3300000>;
53 regulator-boot-on;
54 regulator-always-on;
55 };
56
57 lvds-decoder {
58 compatible = "thine,thc63lvd1024";
59 vcc-supply = <&vcc_d3_3v>;
60
61 ports {
62 #address-cells = <1>;
63 #size-cells = <0>;
64
65 port@0 {
66 reg = <0>;
67 thc63lvd1024_in: endpoint {
68 remote-endpoint = <&lvds0_out>;
69 };
70 };
71
72 port@2 {
73 reg = <2>;
74 thc63lvd1024_out: endpoint {
75 remote-endpoint = <&adv7511_in>;
76 };
77 };
78 };
79 };
80
81 hdmi-out {
82 compatible = "hdmi-connector";
83 type = "a";
84
85 port {
86 hdmi_con: endpoint {
87 remote-endpoint = <&adv7511_out>;
88 };
89 };
90 };
32}; 91};
33 92
34&avb { 93&avb {
94 pinctrl-0 = <&avb_pins>;
95 pinctrl-names = "default";
96
35 renesas,no-ether-link; 97 renesas,no-ether-link;
36 phy-handle = <&phy0>; 98 phy-handle = <&phy0>;
37 phy-mode = "rgmii-id"; 99 phy-mode = "rgmii-id";
@@ -43,6 +105,13 @@
43 }; 105 };
44}; 106};
45 107
108&du {
109 clocks = <&cpg CPG_MOD 724>,
110 <&osc5_clk>;
111 clock-names = "du.0", "dclkin.0";
112 status = "okay";
113};
114
46&extal_clk { 115&extal_clk {
47 clock-frequency = <16666666>; 116 clock-frequency = <16666666>;
48}; 117};
@@ -52,12 +121,80 @@
52}; 121};
53 122
54&pfc { 123&pfc {
124 avb_pins: avb0 {
125 groups = "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk";
126 function = "avb0";
127 };
128
129 i2c0_pins: i2c0 {
130 groups = "i2c0";
131 function = "i2c0";
132 };
133
55 scif0_pins: scif0 { 134 scif0_pins: scif0 {
56 groups = "scif0_data"; 135 groups = "scif0_data";
57 function = "scif0"; 136 function = "scif0";
58 }; 137 };
59}; 138};
60 139
140&i2c0 {
141 pinctrl-0 = <&i2c0_pins>;
142 pinctrl-names = "default";
143
144 status = "okay";
145 clock-frequency = <400000>;
146
147 hdmi@39{
148 compatible = "adi,adv7511w";
149 #sound-dai-cells = <0>;
150 reg = <0x39>;
151 interrupt-parent = <&gpio1>;
152 interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
153 avdd-supply = <&vcc_d1_8v>;
154 dvdd-supply = <&vcc_d1_8v>;
155 pvdd-supply = <&vcc_d1_8v>;
156 bgvdd-supply = <&vcc_d1_8v>;
157 dvdd-3v-supply = <&vcc_d3_3v>;
158
159 adi,input-depth = <8>;
160 adi,input-colorspace = "rgb";
161 adi,input-clock = "1x";
162 adi,input-style = <1>;
163 adi,input-justification = "evenly";
164
165 ports {
166 #address-cells = <1>;
167 #size-cells = <0>;
168
169 port@0 {
170 reg = <0>;
171 adv7511_in: endpoint {
172 remote-endpoint = <&thc63lvd1024_out>;
173 };
174 };
175
176 port@1 {
177 reg = <1>;
178 adv7511_out: endpoint {
179 remote-endpoint = <&hdmi_con>;
180 };
181 };
182 };
183 };
184};
185
186&lvds0 {
187 status = "okay";
188
189 ports {
190 port@1 {
191 lvds0_out: endpoint {
192 remote-endpoint = <&thc63lvd1024_in>;
193 };
194 };
195 };
196};
197
61&scif0 { 198&scif0 {
62 pinctrl-0 = <&scif0_pins>; 199 pinctrl-0 = <&scif0_pins>;
63 pinctrl-names = "default"; 200 pinctrl-names = "default";
diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
index c6db8ea43906..98a2317a16c4 100644
--- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
@@ -41,6 +41,16 @@
41 enable-method = "psci"; 41 enable-method = "psci";
42 }; 42 };
43 43
44 a53_1: cpu@1 {
45 device_type = "cpu";
46 compatible = "arm,cortex-a53", "arm,armv8";
47 reg = <1>;
48 clocks = <&cpg CPG_CORE R8A77970_CLK_Z2>;
49 power-domains = <&sysc R8A77970_PD_CA53_CPU1>;
50 next-level-cache = <&L2_CA53>;
51 enable-method = "psci";
52 };
53
44 L2_CA53: cache-controller { 54 L2_CA53: cache-controller {
45 compatible = "cache"; 55 compatible = "cache";
46 power-domains = <&sysc R8A77970_PD_CA53_SCU>; 56 power-domains = <&sysc R8A77970_PD_CA53_SCU>;
@@ -63,11 +73,25 @@
63 clock-frequency = <0>; 73 clock-frequency = <0>;
64 }; 74 };
65 75
76 pmu_a53 {
77 compatible = "arm,cortex-a53-pmu";
78 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
79 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
80 interrupt-affinity = <&a53_0>, <&a53_1>;
81 };
82
66 psci { 83 psci {
67 compatible = "arm,psci-1.0", "arm,psci-0.2"; 84 compatible = "arm,psci-1.0", "arm,psci-0.2";
68 method = "smc"; 85 method = "smc";
69 }; 86 };
70 87
88 /* External CAN clock - to be overridden by boards that provide it */
89 can_clk: can {
90 compatible = "fixed-clock";
91 #clock-cells = <0>;
92 clock-frequency = <0>;
93 };
94
71 /* External SCIF clock - to be overridden by boards that provide it */ 95 /* External SCIF clock - to be overridden by boards that provide it */
72 scif_clk: scif { 96 scif_clk: scif {
73 compatible = "fixed-clock"; 97 compatible = "fixed-clock";
@@ -83,23 +107,6 @@
83 #size-cells = <2>; 107 #size-cells = <2>;
84 ranges; 108 ranges;
85 109
86 gic: interrupt-controller@f1010000 {
87 compatible = "arm,gic-400";
88 #interrupt-cells = <3>;
89 #address-cells = <0>;
90 interrupt-controller;
91 reg = <0 0xf1010000 0 0x1000>,
92 <0 0xf1020000 0 0x20000>,
93 <0 0xf1040000 0 0x20000>,
94 <0 0xf1060000 0 0x20000>;
95 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) |
96 IRQ_TYPE_LEVEL_HIGH)>;
97 clocks = <&cpg CPG_MOD 408>;
98 clock-names = "clk";
99 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
100 resets = <&cpg 408>;
101 };
102
103 rwdt: watchdog@e6020000 { 110 rwdt: watchdog@e6020000 {
104 compatible = "renesas,r8a77970-wdt", 111 compatible = "renesas,r8a77970-wdt",
105 "renesas,rcar-gen3-wdt"; 112 "renesas,rcar-gen3-wdt";
@@ -110,75 +117,6 @@
110 status = "disabled"; 117 status = "disabled";
111 }; 118 };
112 119
113 cpg: clock-controller@e6150000 {
114 compatible = "renesas,r8a77970-cpg-mssr";
115 reg = <0 0xe6150000 0 0x1000>;
116 clocks = <&extal_clk>, <&extalr_clk>;
117 clock-names = "extal", "extalr";
118 #clock-cells = <2>;
119 #power-domain-cells = <0>;
120 #reset-cells = <1>;
121 };
122
123 rst: reset-controller@e6160000 {
124 compatible = "renesas,r8a77970-rst";
125 reg = <0 0xe6160000 0 0x200>;
126 };
127
128 sysc: system-controller@e6180000 {
129 compatible = "renesas,r8a77970-sysc";
130 reg = <0 0xe6180000 0 0x440>;
131 #power-domain-cells = <1>;
132 };
133
134 ipmmu_vi0: mmu@febd0000 {
135 compatible = "renesas,ipmmu-r8a77970";
136 reg = <0 0xfebd0000 0 0x1000>;
137 renesas,ipmmu-main = <&ipmmu_mm 9>;
138 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
139 #iommu-cells = <1>;
140 status = "disabled";
141 };
142
143 ipmmu_ir: mmu@ff8b0000 {
144 compatible = "renesas,ipmmu-r8a77970";
145 reg = <0 0xff8b0000 0 0x1000>;
146 renesas,ipmmu-main = <&ipmmu_mm 3>;
147 power-domains = <&sysc R8A77970_PD_A3IR>;
148 #iommu-cells = <1>;
149 status = "disabled";
150 };
151
152 ipmmu_rt: mmu@ffc80000 {
153 compatible = "renesas,ipmmu-r8a77970";
154 reg = <0 0xffc80000 0 0x1000>;
155 renesas,ipmmu-main = <&ipmmu_mm 7>;
156 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
157 #iommu-cells = <1>;
158 };
159
160 ipmmu_ds1: mmu@e7740000 {
161 compatible = "renesas,ipmmu-r8a77970";
162 reg = <0 0xe7740000 0 0x1000>;
163 renesas,ipmmu-main = <&ipmmu_mm 1>;
164 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
165 #iommu-cells = <1>;
166 };
167
168 ipmmu_mm: mmu@e67b0000 {
169 compatible = "renesas,ipmmu-r8a77970";
170 reg = <0 0xe67b0000 0 0x1000>;
171 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
172 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
173 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
174 #iommu-cells = <1>;
175 };
176
177 pfc: pin-controller@e6060000 {
178 compatible = "renesas,pfc-r8a77970";
179 reg = <0 0xe6060000 0 0x504>;
180 };
181
182 gpio0: gpio@e6050000 { 120 gpio0: gpio@e6050000 {
183 compatible = "renesas,gpio-r8a77970", 121 compatible = "renesas,gpio-r8a77970",
184 "renesas,rcar-gen3-gpio"; 122 "renesas,rcar-gen3-gpio";
@@ -269,6 +207,32 @@
269 resets = <&cpg 907>; 207 resets = <&cpg 907>;
270 }; 208 };
271 209
210 pfc: pin-controller@e6060000 {
211 compatible = "renesas,pfc-r8a77970";
212 reg = <0 0xe6060000 0 0x504>;
213 };
214
215 cpg: clock-controller@e6150000 {
216 compatible = "renesas,r8a77970-cpg-mssr";
217 reg = <0 0xe6150000 0 0x1000>;
218 clocks = <&extal_clk>, <&extalr_clk>;
219 clock-names = "extal", "extalr";
220 #clock-cells = <2>;
221 #power-domain-cells = <0>;
222 #reset-cells = <1>;
223 };
224
225 rst: reset-controller@e6160000 {
226 compatible = "renesas,r8a77970-rst";
227 reg = <0 0xe6160000 0 0x200>;
228 };
229
230 sysc: system-controller@e6180000 {
231 compatible = "renesas,r8a77970-sysc";
232 reg = <0 0xe6180000 0 0x440>;
233 #power-domain-cells = <1>;
234 };
235
272 intc_ex: interrupt-controller@e61c0000 { 236 intc_ex: interrupt-controller@e61c0000 {
273 compatible = "renesas,intc-ex-r8a77970", "renesas,irqc"; 237 compatible = "renesas,intc-ex-r8a77970", "renesas,irqc";
274 #interrupt-cells = <2>; 238 #interrupt-cells = <2>;
@@ -285,67 +249,6 @@
285 resets = <&cpg 407>; 249 resets = <&cpg 407>;
286 }; 250 };
287 251
288 prr: chipid@fff00044 {
289 compatible = "renesas,prr";
290 reg = <0 0xfff00044 0 4>;
291 };
292
293 dmac1: dma-controller@e7300000 {
294 compatible = "renesas,dmac-r8a77970",
295 "renesas,rcar-dmac";
296 reg = <0 0xe7300000 0 0x10000>;
297 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
298 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
299 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
300 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
301 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
302 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
303 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
304 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
305 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
306 interrupt-names = "error",
307 "ch0", "ch1", "ch2", "ch3",
308 "ch4", "ch5", "ch6", "ch7";
309 clocks = <&cpg CPG_MOD 218>;
310 clock-names = "fck";
311 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
312 resets = <&cpg 218>;
313 #dma-cells = <1>;
314 dma-channels = <8>;
315 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
316 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
317 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
318 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>;
319 };
320
321 dmac2: dma-controller@e7310000 {
322 compatible = "renesas,dmac-r8a77970",
323 "renesas,rcar-dmac";
324 reg = <0 0xe7310000 0 0x10000>;
325 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH
326 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
327 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
328 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
329 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
330 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
331 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
332 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH
333 GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
334 interrupt-names = "error",
335 "ch0", "ch1", "ch2", "ch3",
336 "ch4", "ch5", "ch6", "ch7";
337 clocks = <&cpg CPG_MOD 217>;
338 clock-names = "fck";
339 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
340 resets = <&cpg 217>;
341 #dma-cells = <1>;
342 dma-channels = <8>;
343 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
344 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
345 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
346 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>;
347 };
348
349 i2c0: i2c@e6500000 { 252 i2c0: i2c@e6500000 {
350 compatible = "renesas,i2c-r8a77970", 253 compatible = "renesas,i2c-r8a77970",
351 "renesas,rcar-gen3-i2c"; 254 "renesas,rcar-gen3-i2c";
@@ -502,6 +405,77 @@
502 status = "disabled"; 405 status = "disabled";
503 }; 406 };
504 407
408 canfd: can@e66c0000 {
409 compatible = "renesas,r8a77970-canfd",
410 "renesas,rcar-gen3-canfd";
411 reg = <0 0xe66c0000 0 0x8000>;
412 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
413 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
414 clocks = <&cpg CPG_MOD 914>,
415 <&cpg CPG_CORE R8A77970_CLK_CANFD>,
416 <&can_clk>;
417 clock-names = "fck", "canfd", "can_clk";
418 assigned-clocks = <&cpg CPG_CORE R8A77970_CLK_CANFD>;
419 assigned-clock-rates = <40000000>;
420 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
421 resets = <&cpg 914>;
422 status = "disabled";
423
424 channel0 {
425 status = "disabled";
426 };
427
428 channel1 {
429 status = "disabled";
430 };
431 };
432
433 avb: ethernet@e6800000 {
434 compatible = "renesas,etheravb-r8a77970",
435 "renesas,etheravb-rcar-gen3";
436 reg = <0 0xe6800000 0 0x800>;
437 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
438 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
439 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
440 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
441 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
442 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
443 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
444 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
445 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
446 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
447 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
448 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
449 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
450 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
451 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
452 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
453 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
454 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
455 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
456 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
457 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
458 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
459 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
460 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
461 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
462 interrupt-names = "ch0", "ch1", "ch2", "ch3",
463 "ch4", "ch5", "ch6", "ch7",
464 "ch8", "ch9", "ch10", "ch11",
465 "ch12", "ch13", "ch14", "ch15",
466 "ch16", "ch17", "ch18", "ch19",
467 "ch20", "ch21", "ch22", "ch23",
468 "ch24";
469 clocks = <&cpg CPG_MOD 812>;
470 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
471 resets = <&cpg 812>;
472 phy-mode = "rgmii";
473 iommus = <&ipmmu_rt 3>;
474 #address-cells = <1>;
475 #size-cells = <0>;
476 status = "disabled";
477 };
478
505 scif0: serial@e6e60000 { 479 scif0: serial@e6e60000 {
506 compatible = "renesas,scif-r8a77970", 480 compatible = "renesas,scif-r8a77970",
507 "renesas,rcar-gen3-scif", 481 "renesas,rcar-gen3-scif",
@@ -573,57 +547,358 @@
573 status = "disabled"; 547 status = "disabled";
574 }; 548 };
575 549
576 avb: ethernet@e6800000 { 550
577 compatible = "renesas,etheravb-r8a77970", 551 vin0: video@e6ef0000 {
578 "renesas,etheravb-rcar-gen3"; 552 compatible = "renesas,vin-r8a77970";
579 reg = <0 0xe6800000 0 0x800>; 553 reg = <0 0xe6ef0000 0 0x1000>;
580 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 554 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
581 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 555 clocks = <&cpg CPG_MOD 811>;
582 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
583 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
584 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
585 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
586 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
587 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
588 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
589 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
590 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
591 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
592 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
593 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
594 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
595 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
596 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
597 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
598 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
599 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
600 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
601 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
602 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
603 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
604 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
605 interrupt-names = "ch0", "ch1", "ch2", "ch3",
606 "ch4", "ch5", "ch6", "ch7",
607 "ch8", "ch9", "ch10", "ch11",
608 "ch12", "ch13", "ch14", "ch15",
609 "ch16", "ch17", "ch18", "ch19",
610 "ch20", "ch21", "ch22", "ch23",
611 "ch24";
612 clocks = <&cpg CPG_MOD 812>;
613 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 556 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
614 resets = <&cpg 812>; 557 resets = <&cpg 811>;
615 phy-mode = "rgmii"; 558 renesas,id = <0>;
616 iommus = <&ipmmu_rt 3>; 559 status = "disabled";
617 #address-cells = <1>; 560
618 #size-cells = <0>; 561 ports {
562 #address-cells = <1>;
563 #size-cells = <0>;
564
565 port@1 {
566 #address-cells = <1>;
567 #size-cells = <0>;
568
569 reg = <1>;
570
571 vin0csi40: endpoint@2 {
572 reg = <2>;
573 remote-endpoint= <&csi40vin0>;
574 };
575 };
576 };
577 };
578
579 vin1: video@e6ef1000 {
580 compatible = "renesas,vin-r8a77970";
581 reg = <0 0xe6ef1000 0 0x1000>;
582 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
583 clocks = <&cpg CPG_MOD 810>;
584 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
585 resets = <&cpg 810>;
586 renesas,id = <1>;
587 status = "disabled";
588
589 ports {
590 #address-cells = <1>;
591 #size-cells = <0>;
592
593 port@1 {
594 #address-cells = <1>;
595 #size-cells = <0>;
596
597 reg = <1>;
598
599 vin1csi40: endpoint@2 {
600 reg = <2>;
601 remote-endpoint= <&csi40vin1>;
602 };
603 };
604 };
605 };
606
607 vin2: video@e6ef2000 {
608 compatible = "renesas,vin-r8a77970";
609 reg = <0 0xe6ef2000 0 0x1000>;
610 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
611 clocks = <&cpg CPG_MOD 809>;
612 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
613 resets = <&cpg 809>;
614 renesas,id = <2>;
615 status = "disabled";
616
617 ports {
618 #address-cells = <1>;
619 #size-cells = <0>;
620
621 port@1 {
622 #address-cells = <1>;
623 #size-cells = <0>;
624
625 reg = <1>;
626
627 vin2csi40: endpoint@2 {
628 reg = <2>;
629 remote-endpoint= <&csi40vin2>;
630 };
631 };
632 };
633 };
634
635 vin3: video@e6ef3000 {
636 compatible = "renesas,vin-r8a77970";
637 reg = <0 0xe6ef3000 0 0x1000>;
638 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
639 clocks = <&cpg CPG_MOD 808>;
640 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
641 resets = <&cpg 808>;
642 renesas,id = <3>;
643 status = "disabled";
644
645 ports {
646 #address-cells = <1>;
647 #size-cells = <0>;
648
649 port@1 {
650 #address-cells = <1>;
651 #size-cells = <0>;
652
653 reg = <1>;
654
655 vin3csi40: endpoint@2 {
656 reg = <2>;
657 remote-endpoint= <&csi40vin3>;
658 };
659 };
660 };
661 };
662
663 dmac1: dma-controller@e7300000 {
664 compatible = "renesas,dmac-r8a77970",
665 "renesas,rcar-dmac";
666 reg = <0 0xe7300000 0 0x10000>;
667 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
668 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
669 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
670 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
671 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
672 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
673 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
674 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
675 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
676 interrupt-names = "error",
677 "ch0", "ch1", "ch2", "ch3",
678 "ch4", "ch5", "ch6", "ch7";
679 clocks = <&cpg CPG_MOD 218>;
680 clock-names = "fck";
681 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
682 resets = <&cpg 218>;
683 #dma-cells = <1>;
684 dma-channels = <8>;
685 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
686 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
687 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
688 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>;
689 };
690
691 dmac2: dma-controller@e7310000 {
692 compatible = "renesas,dmac-r8a77970",
693 "renesas,rcar-dmac";
694 reg = <0 0xe7310000 0 0x10000>;
695 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH
696 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
697 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
698 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
699 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
700 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
701 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
702 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH
703 GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
704 interrupt-names = "error",
705 "ch0", "ch1", "ch2", "ch3",
706 "ch4", "ch5", "ch6", "ch7";
707 clocks = <&cpg CPG_MOD 217>;
708 clock-names = "fck";
709 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
710 resets = <&cpg 217>;
711 #dma-cells = <1>;
712 dma-channels = <8>;
713 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
714 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
715 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
716 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>;
717 };
718
719 ipmmu_ds1: mmu@e7740000 {
720 compatible = "renesas,ipmmu-r8a77970";
721 reg = <0 0xe7740000 0 0x1000>;
722 renesas,ipmmu-main = <&ipmmu_mm 0>;
723 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
724 #iommu-cells = <1>;
725 };
726
727 ipmmu_ir: mmu@ff8b0000 {
728 compatible = "renesas,ipmmu-r8a77970";
729 reg = <0 0xff8b0000 0 0x1000>;
730 renesas,ipmmu-main = <&ipmmu_mm 3>;
731 power-domains = <&sysc R8A77970_PD_A3IR>;
732 #iommu-cells = <1>;
733 };
734
735 ipmmu_mm: mmu@e67b0000 {
736 compatible = "renesas,ipmmu-r8a77970";
737 reg = <0 0xe67b0000 0 0x1000>;
738 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
739 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
740 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
741 #iommu-cells = <1>;
742 };
743
744 ipmmu_rt: mmu@ffc80000 {
745 compatible = "renesas,ipmmu-r8a77970";
746 reg = <0 0xffc80000 0 0x1000>;
747 renesas,ipmmu-main = <&ipmmu_mm 7>;
748 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
749 #iommu-cells = <1>;
750 };
751
752 ipmmu_vi0: mmu@febd0000 {
753 compatible = "renesas,ipmmu-r8a77970";
754 reg = <0 0xfebd0000 0 0x1000>;
755 renesas,ipmmu-main = <&ipmmu_mm 9>;
756 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
757 #iommu-cells = <1>;
758 };
759
760 gic: interrupt-controller@f1010000 {
761 compatible = "arm,gic-400";
762 #interrupt-cells = <3>;
763 #address-cells = <0>;
764 interrupt-controller;
765 reg = <0 0xf1010000 0 0x1000>,
766 <0 0xf1020000 0 0x20000>,
767 <0 0xf1040000 0 0x20000>,
768 <0 0xf1060000 0 0x20000>;
769 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
770 IRQ_TYPE_LEVEL_HIGH)>;
771 clocks = <&cpg CPG_MOD 408>;
772 clock-names = "clk";
773 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
774 resets = <&cpg 408>;
775 };
776
777 vspd0: vsp@fea20000 {
778 compatible = "renesas,vsp2";
779 reg = <0 0xfea20000 0 0x8000>;
780 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
781 clocks = <&cpg CPG_MOD 623>;
782 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
783 resets = <&cpg 623>;
784 renesas,fcp = <&fcpvd0>;
785 };
786
787 fcpvd0: fcp@fea27000 {
788 compatible = "renesas,fcpv";
789 reg = <0 0xfea27000 0 0x200>;
790 clocks = <&cpg CPG_MOD 603>;
791 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
792 resets = <&cpg 603>;
793 };
794
795 csi40: csi2@feaa0000 {
796 compatible = "renesas,r8a77970-csi2";
797 reg = <0 0xfeaa0000 0 0x10000>;
798 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
799 clocks = <&cpg CPG_MOD 716>;
800 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
801 resets = <&cpg 716>;
802 status = "disabled";
803
804 ports {
805 #address-cells = <1>;
806 #size-cells = <0>;
807
808 port@1 {
809 #address-cells = <1>;
810 #size-cells = <0>;
811
812 reg = <1>;
813
814 csi40vin0: endpoint@0 {
815 reg = <0>;
816 remote-endpoint = <&vin0csi40>;
817 };
818 csi40vin1: endpoint@1 {
819 reg = <1>;
820 remote-endpoint = <&vin1csi40>;
821 };
822 csi40vin2: endpoint@2 {
823 reg = <2>;
824 remote-endpoint = <&vin2csi40>;
825 };
826 csi40vin3: endpoint@3 {
827 reg = <3>;
828 remote-endpoint = <&vin3csi40>;
829 };
830 };
831 };
832 };
833
834 du: display@feb00000 {
835 compatible = "renesas,du-r8a77970";
836 reg = <0 0xfeb00000 0 0x80000>;
837 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
838 clocks = <&cpg CPG_MOD 724>;
839 clock-names = "du.0";
840 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
841 resets = <&cpg 724>;
842 vsps = <&vspd0>;
843 status = "disabled";
844
845 ports {
846 #address-cells = <1>;
847 #size-cells = <0>;
848
849 port@0 {
850 reg = <0>;
851 du_out_rgb: endpoint {
852 };
853 };
854
855 port@1 {
856 reg = <1>;
857 du_out_lvds0: endpoint {
858 remote-endpoint = <&lvds0_in>;
859 };
860 };
861 };
862 };
863
864 lvds0: lvds-encoder@feb90000 {
865 compatible = "renesas,r8a77970-lvds";
866 reg = <0 0xfeb90000 0 0x14>;
867 clocks = <&cpg CPG_MOD 727>;
868 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
869 resets = <&cpg 727>;
870 status = "disabled";
871
872 ports {
873 #address-cells = <1>;
874 #size-cells = <0>;
875
876 port@0 {
877 reg = <0>;
878 lvds0_in: endpoint {
879 remote-endpoint =
880 <&du_out_lvds0>;
881 };
882 };
883 port@1 {
884 reg = <1>;
885 lvds0_out: endpoint {
886 };
887 };
888 };
889 };
890
891 prr: chipid@fff00044 {
892 compatible = "renesas,prr";
893 reg = <0 0xfff00044 0 4>;
619 }; 894 };
620 }; 895 };
621 896
622 timer { 897 timer {
623 compatible = "arm,armv8-timer"; 898 compatible = "arm,armv8-timer";
624 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 899 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
625 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 900 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
626 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 901 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
627 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 902 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
628 }; 903 };
629}; 904};
diff --git a/arch/arm64/boot/dts/renesas/r8a77980-condor.dts b/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
index 06cf6845765a..0b93a7d76585 100644
--- a/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
@@ -27,9 +27,30 @@
27 /* first 128MB is reserved for secure area. */ 27 /* first 128MB is reserved for secure area. */
28 reg = <0 0x48000000 0 0x78000000>; 28 reg = <0 0x48000000 0 0x78000000>;
29 }; 29 };
30
31 d3_3v: regulator-0 {
32 compatible = "regulator-fixed";
33 regulator-name = "D3.3V";
34 regulator-min-microvolt = <3300000>;
35 regulator-max-microvolt = <3300000>;
36 regulator-boot-on;
37 regulator-always-on;
38 };
39
40 vddq_vin01: regulator-1 {
41 compatible = "regulator-fixed";
42 regulator-name = "VDDQ_VIN01";
43 regulator-min-microvolt = <1800000>;
44 regulator-max-microvolt = <1800000>;
45 regulator-boot-on;
46 regulator-always-on;
47 };
30}; 48};
31 49
32&avb { 50&avb {
51 pinctrl-0 = <&avb_pins>;
52 pinctrl-names = "default";
53
33 phy-mode = "rgmii-id"; 54 phy-mode = "rgmii-id";
34 phy-handle = <&phy0>; 55 phy-handle = <&phy0>;
35 renesas,no-ether-link; 56 renesas,no-ether-link;
@@ -41,6 +62,16 @@
41 }; 62 };
42}; 63};
43 64
65&canfd {
66 pinctrl-0 = <&canfd0_pins>;
67 pinctrl-names = "default";
68 status = "okay";
69
70 channel0 {
71 status = "okay";
72 };
73};
74
44&extal_clk { 75&extal_clk {
45 clock-frequency = <16666666>; 76 clock-frequency = <16666666>;
46}; 77};
@@ -49,7 +80,57 @@
49 clock-frequency = <32768>; 80 clock-frequency = <32768>;
50}; 81};
51 82
83&mmc0 {
84 pinctrl-0 = <&mmc_pins>;
85 pinctrl-1 = <&mmc_pins_uhs>;
86 pinctrl-names = "default", "state_uhs";
87
88 vmmc-supply = <&d3_3v>;
89 vqmmc-supply = <&vddq_vin01>;
90 mmc-hs200-1_8v;
91 bus-width = <8>;
92 non-removable;
93 status = "okay";
94};
95
96&pfc {
97 avb_pins: avb {
98 groups = "avb_mdio", "avb_rgmii";
99 function = "avb";
100 };
101
102 canfd0_pins: canfd0 {
103 groups = "canfd0_data_a";
104 function = "canfd0";
105 };
106
107 mmc_pins: mmc {
108 groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
109 function = "mmc";
110 power-source = <3300>;
111 };
112
113 mmc_pins_uhs: mmc_uhs {
114 groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
115 function = "mmc";
116 power-source = <1800>;
117 };
118
119 scif0_pins: scif0 {
120 groups = "scif0_data";
121 function = "scif0";
122 };
123
124 scif_clk_pins: scif_clk {
125 groups = "scif_clk_b";
126 function = "scif_clk";
127 };
128};
129
52&scif0 { 130&scif0 {
131 pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>;
132 pinctrl-names = "default";
133
53 status = "okay"; 134 status = "okay";
54}; 135};
55 136
diff --git a/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts b/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts
new file mode 100644
index 000000000000..c9680994555d
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts
@@ -0,0 +1,60 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the V3H Starter Kit board
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 * Copyright (C) 2018 Cogent Embedded, Inc.
7 */
8
9/dts-v1/;
10#include "r8a77980.dtsi"
11
12/ {
13 model = "Renesas V3H Starter Kit board";
14 compatible = "renesas,v3hsk", "renesas,r8a77980";
15
16 aliases {
17 serial0 = &scif0;
18 };
19
20 chosen {
21 stdout-path = "serial0:115200n8";
22 };
23
24 memory@48000000 {
25 device_type = "memory";
26 /* first 128MB is reserved for secure area. */
27 reg = <0 0x48000000 0 0x78000000>;
28 };
29};
30
31&extal_clk {
32 clock-frequency = <16666666>;
33};
34
35&extalr_clk {
36 clock-frequency = <32768>;
37};
38
39&pfc {
40 scif0_pins: scif0 {
41 groups = "scif0_data";
42 function = "scif0";
43 };
44
45 scif_clk_pins: scif_clk {
46 groups = "scif_clk_b";
47 function = "scif_clk";
48 };
49};
50
51&scif0 {
52 pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>;
53 pinctrl-names = "default";
54
55 status = "okay";
56};
57
58&scif_clk {
59 clock-frequency = <14745600>;
60};
diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
index 03845fd74996..4c40f9f0ebc9 100644
--- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
@@ -6,9 +6,10 @@
6 * Copyright (C) 2018 Cogent Embedded, Inc. 6 * Copyright (C) 2018 Cogent Embedded, Inc.
7 */ 7 */
8 8
9#include <dt-bindings/clock/r8a77980-cpg-mssr.h>
9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/interrupt-controller/irq.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include <dt-bindings/clock/renesas-cpg-mssr.h> 12#include <dt-bindings/power/r8a77980-sysc.h>
12 13
13/ { 14/ {
14 compatible = "renesas,r8a77980"; 15 compatible = "renesas,r8a77980";
@@ -23,20 +24,27 @@
23 device_type = "cpu"; 24 device_type = "cpu";
24 compatible = "arm,cortex-a53", "arm,armv8"; 25 compatible = "arm,cortex-a53", "arm,armv8";
25 reg = <0>; 26 reg = <0>;
26 clocks = <&cpg CPG_CORE 0>; 27 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
27 power-domains = <&sysc 5>; 28 power-domains = <&sysc R8A77980_PD_CA53_CPU0>;
28 next-level-cache = <&L2_CA53>; 29 next-level-cache = <&L2_CA53>;
29 enable-method = "psci"; 30 enable-method = "psci";
30 }; 31 };
31 32
32 L2_CA53: cache-controller { 33 L2_CA53: cache-controller {
33 compatible = "cache"; 34 compatible = "cache";
34 power-domains = <&sysc 21>; 35 power-domains = <&sysc R8A77980_PD_CA53_SCU>;
35 cache-unified; 36 cache-unified;
36 cache-level = <2>; 37 cache-level = <2>;
37 }; 38 };
38 }; 39 };
39 40
41 /* External CAN clock - to be overridden by boards that provide it */
42 can_clk: can {
43 compatible = "fixed-clock";
44 #clock-cells = <0>;
45 clock-frequency = <0>;
46 };
47
40 extal_clk: extal { 48 extal_clk: extal {
41 compatible = "fixed-clock"; 49 compatible = "fixed-clock";
42 #clock-cells = <0>; 50 #clock-cells = <0>;
@@ -71,6 +79,11 @@
71 #size-cells = <2>; 79 #size-cells = <2>;
72 ranges; 80 ranges;
73 81
82 pfc: pin-controller@e6060000 {
83 compatible = "renesas,pfc-r8a77980";
84 reg = <0 0xe6060000 0 0x50c>;
85 };
86
74 cpg: clock-controller@e6150000 { 87 cpg: clock-controller@e6150000 {
75 compatible = "renesas,r8a77980-cpg-mssr"; 88 compatible = "renesas,r8a77980-cpg-mssr";
76 reg = <0 0xe6150000 0 0x1000>; 89 reg = <0 0xe6150000 0 0x1000>;
@@ -99,13 +112,13 @@
99 reg = <0 0xe6540000 0 0x60>; 112 reg = <0 0xe6540000 0 0x60>;
100 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 113 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
101 clocks = <&cpg CPG_MOD 520>, 114 clocks = <&cpg CPG_MOD 520>,
102 <&cpg CPG_CORE 19>, 115 <&cpg CPG_CORE R8A77980_CLK_S3D1>,
103 <&scif_clk>; 116 <&scif_clk>;
104 clock-names = "fck", "brg_int", "scif_clk"; 117 clock-names = "fck", "brg_int", "scif_clk";
105 dmas = <&dmac1 0x31>, <&dmac1 0x30>, 118 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
106 <&dmac2 0x31>, <&dmac2 0x30>; 119 <&dmac2 0x31>, <&dmac2 0x30>;
107 dma-names = "tx", "rx", "tx", "rx"; 120 dma-names = "tx", "rx", "tx", "rx";
108 power-domains = <&sysc 32>; 121 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
109 resets = <&cpg 520>; 122 resets = <&cpg 520>;
110 status = "disabled"; 123 status = "disabled";
111 }; 124 };
@@ -117,13 +130,13 @@
117 reg = <0 0xe6550000 0 0x60>; 130 reg = <0 0xe6550000 0 0x60>;
118 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 131 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
119 clocks = <&cpg CPG_MOD 519>, 132 clocks = <&cpg CPG_MOD 519>,
120 <&cpg CPG_CORE 19>, 133 <&cpg CPG_CORE R8A77980_CLK_S3D1>,
121 <&scif_clk>; 134 <&scif_clk>;
122 clock-names = "fck", "brg_int", "scif_clk"; 135 clock-names = "fck", "brg_int", "scif_clk";
123 dmas = <&dmac1 0x33>, <&dmac1 0x32>, 136 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
124 <&dmac2 0x33>, <&dmac2 0x32>; 137 <&dmac2 0x33>, <&dmac2 0x32>;
125 dma-names = "tx", "rx", "tx", "rx"; 138 dma-names = "tx", "rx", "tx", "rx";
126 power-domains = <&sysc 32>; 139 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
127 resets = <&cpg 519>; 140 resets = <&cpg 519>;
128 status = "disabled"; 141 status = "disabled";
129 }; 142 };
@@ -135,13 +148,13 @@
135 reg = <0 0xe6560000 0 0x60>; 148 reg = <0 0xe6560000 0 0x60>;
136 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 149 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
137 clocks = <&cpg CPG_MOD 518>, 150 clocks = <&cpg CPG_MOD 518>,
138 <&cpg CPG_CORE 19>, 151 <&cpg CPG_CORE R8A77980_CLK_S3D1>,
139 <&scif_clk>; 152 <&scif_clk>;
140 clock-names = "fck", "brg_int", "scif_clk"; 153 clock-names = "fck", "brg_int", "scif_clk";
141 dmas = <&dmac1 0x35>, <&dmac1 0x34>, 154 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
142 <&dmac2 0x35>, <&dmac2 0x34>; 155 <&dmac2 0x35>, <&dmac2 0x34>;
143 dma-names = "tx", "rx", "tx", "rx"; 156 dma-names = "tx", "rx", "tx", "rx";
144 power-domains = <&sysc 32>; 157 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
145 resets = <&cpg 518>; 158 resets = <&cpg 518>;
146 status = "disabled"; 159 status = "disabled";
147 }; 160 };
@@ -153,17 +166,42 @@
153 reg = <0 0xe66a0000 0 0x60>; 166 reg = <0 0xe66a0000 0 0x60>;
154 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 167 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
155 clocks = <&cpg CPG_MOD 517>, 168 clocks = <&cpg CPG_MOD 517>,
156 <&cpg CPG_CORE 19>, 169 <&cpg CPG_CORE R8A77980_CLK_S3D1>,
157 <&scif_clk>; 170 <&scif_clk>;
158 clock-names = "fck", "brg_int", "scif_clk"; 171 clock-names = "fck", "brg_int", "scif_clk";
159 dmas = <&dmac1 0x37>, <&dmac1 0x36>, 172 dmas = <&dmac1 0x37>, <&dmac1 0x36>,
160 <&dmac2 0x37>, <&dmac2 0x36>; 173 <&dmac2 0x37>, <&dmac2 0x36>;
161 dma-names = "tx", "rx", "tx", "rx"; 174 dma-names = "tx", "rx", "tx", "rx";
162 power-domains = <&sysc 32>; 175 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
163 resets = <&cpg 517>; 176 resets = <&cpg 517>;
164 status = "disabled"; 177 status = "disabled";
165 }; 178 };
166 179
180 canfd: can@e66c0000 {
181 compatible = "renesas,r8a77980-canfd",
182 "renesas,rcar-gen3-canfd";
183 reg = <0 0xe66c0000 0 0x8000>;
184 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
185 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
186 clocks = <&cpg CPG_MOD 914>,
187 <&cpg CPG_CORE R8A77980_CLK_CANFD>,
188 <&can_clk>;
189 clock-names = "fck", "canfd", "can_clk";
190 assigned-clocks = <&cpg CPG_CORE R8A77980_CLK_CANFD>;
191 assigned-clock-rates = <40000000>;
192 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
193 resets = <&cpg 914>;
194 status = "disabled";
195
196 channel0 {
197 status = "disabled";
198 };
199
200 channel1 {
201 status = "disabled";
202 };
203 };
204
167 avb: ethernet@e6800000 { 205 avb: ethernet@e6800000 {
168 compatible = "renesas,etheravb-r8a77980", 206 compatible = "renesas,etheravb-r8a77980",
169 "renesas,etheravb-rcar-gen3"; 207 "renesas,etheravb-rcar-gen3";
@@ -201,11 +239,12 @@
201 "ch20", "ch21", "ch22", "ch23", 239 "ch20", "ch21", "ch22", "ch23",
202 "ch24"; 240 "ch24";
203 clocks = <&cpg CPG_MOD 812>; 241 clocks = <&cpg CPG_MOD 812>;
204 power-domains = <&sysc 32>; 242 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
205 resets = <&cpg 812>; 243 resets = <&cpg 812>;
206 phy-mode = "rgmii"; 244 phy-mode = "rgmii";
207 #address-cells = <1>; 245 #address-cells = <1>;
208 #size-cells = <0>; 246 #size-cells = <0>;
247 status = "disabled";
209 }; 248 };
210 249
211 scif0: serial@e6e60000 { 250 scif0: serial@e6e60000 {
@@ -215,13 +254,13 @@
215 reg = <0 0xe6e60000 0 0x40>; 254 reg = <0 0xe6e60000 0 0x40>;
216 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 255 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
217 clocks = <&cpg CPG_MOD 207>, 256 clocks = <&cpg CPG_MOD 207>,
218 <&cpg CPG_CORE 19>, 257 <&cpg CPG_CORE R8A77980_CLK_S3D1>,
219 <&scif_clk>; 258 <&scif_clk>;
220 clock-names = "fck", "brg_int", "scif_clk"; 259 clock-names = "fck", "brg_int", "scif_clk";
221 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 260 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
222 <&dmac2 0x51>, <&dmac2 0x50>; 261 <&dmac2 0x51>, <&dmac2 0x50>;
223 dma-names = "tx", "rx", "tx", "rx"; 262 dma-names = "tx", "rx", "tx", "rx";
224 power-domains = <&sysc 32>; 263 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
225 resets = <&cpg 207>; 264 resets = <&cpg 207>;
226 status = "disabled"; 265 status = "disabled";
227 }; 266 };
@@ -233,13 +272,13 @@
233 reg = <0 0xe6e68000 0 0x40>; 272 reg = <0 0xe6e68000 0 0x40>;
234 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 273 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
235 clocks = <&cpg CPG_MOD 206>, 274 clocks = <&cpg CPG_MOD 206>,
236 <&cpg CPG_CORE 19>, 275 <&cpg CPG_CORE R8A77980_CLK_S3D1>,
237 <&scif_clk>; 276 <&scif_clk>;
238 clock-names = "fck", "brg_int", "scif_clk"; 277 clock-names = "fck", "brg_int", "scif_clk";
239 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 278 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
240 <&dmac2 0x53>, <&dmac2 0x52>; 279 <&dmac2 0x53>, <&dmac2 0x52>;
241 dma-names = "tx", "rx", "tx", "rx"; 280 dma-names = "tx", "rx", "tx", "rx";
242 power-domains = <&sysc 32>; 281 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
243 resets = <&cpg 206>; 282 resets = <&cpg 206>;
244 status = "disabled"; 283 status = "disabled";
245 }; 284 };
@@ -251,13 +290,13 @@
251 reg = <0 0xe6c50000 0 0x40>; 290 reg = <0 0xe6c50000 0 0x40>;
252 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 291 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
253 clocks = <&cpg CPG_MOD 204>, 292 clocks = <&cpg CPG_MOD 204>,
254 <&cpg CPG_CORE 19>, 293 <&cpg CPG_CORE R8A77980_CLK_S3D1>,
255 <&scif_clk>; 294 <&scif_clk>;
256 clock-names = "fck", "brg_int", "scif_clk"; 295 clock-names = "fck", "brg_int", "scif_clk";
257 dmas = <&dmac1 0x57>, <&dmac1 0x56>, 296 dmas = <&dmac1 0x57>, <&dmac1 0x56>,
258 <&dmac2 0x57>, <&dmac2 0x56>; 297 <&dmac2 0x57>, <&dmac2 0x56>;
259 dma-names = "tx", "rx", "tx", "rx"; 298 dma-names = "tx", "rx", "tx", "rx";
260 power-domains = <&sysc 32>; 299 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
261 resets = <&cpg 204>; 300 resets = <&cpg 204>;
262 status = "disabled"; 301 status = "disabled";
263 }; 302 };
@@ -269,13 +308,13 @@
269 reg = <0 0xe6c40000 0 0x40>; 308 reg = <0 0xe6c40000 0 0x40>;
270 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 309 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
271 clocks = <&cpg CPG_MOD 203>, 310 clocks = <&cpg CPG_MOD 203>,
272 <&cpg CPG_CORE 19>, 311 <&cpg CPG_CORE R8A77980_CLK_S3D1>,
273 <&scif_clk>; 312 <&scif_clk>;
274 clock-names = "fck", "brg_int", "scif_clk"; 313 clock-names = "fck", "brg_int", "scif_clk";
275 dmas = <&dmac1 0x59>, <&dmac1 0x58>, 314 dmas = <&dmac1 0x59>, <&dmac1 0x58>,
276 <&dmac2 0x59>, <&dmac2 0x58>; 315 <&dmac2 0x59>, <&dmac2 0x58>;
277 dma-names = "tx", "rx", "tx", "rx"; 316 dma-names = "tx", "rx", "tx", "rx";
278 power-domains = <&sysc 32>; 317 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
279 resets = <&cpg 203>; 318 resets = <&cpg 203>;
280 status = "disabled"; 319 status = "disabled";
281 }; 320 };
@@ -308,7 +347,7 @@
308 "ch12", "ch13", "ch14", "ch15"; 347 "ch12", "ch13", "ch14", "ch15";
309 clocks = <&cpg CPG_MOD 218>; 348 clocks = <&cpg CPG_MOD 218>;
310 clock-names = "fck"; 349 clock-names = "fck";
311 power-domains = <&sysc 32>; 350 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
312 resets = <&cpg 218>; 351 resets = <&cpg 218>;
313 #dma-cells = <1>; 352 #dma-cells = <1>;
314 dma-channels = <16>; 353 dma-channels = <16>;
@@ -342,12 +381,24 @@
342 "ch12", "ch13", "ch14", "ch15"; 381 "ch12", "ch13", "ch14", "ch15";
343 clocks = <&cpg CPG_MOD 217>; 382 clocks = <&cpg CPG_MOD 217>;
344 clock-names = "fck"; 383 clock-names = "fck";
345 power-domains = <&sysc 32>; 384 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
346 resets = <&cpg 217>; 385 resets = <&cpg 217>;
347 #dma-cells = <1>; 386 #dma-cells = <1>;
348 dma-channels = <16>; 387 dma-channels = <16>;
349 }; 388 };
350 389
390 mmc0: mmc@ee140000 {
391 compatible = "renesas,sdhi-r8a77980",
392 "renesas,rcar-gen3-sdhi";
393 reg = <0 0xee140000 0 0x2000>;
394 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
395 clocks = <&cpg CPG_MOD 314>;
396 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
397 resets = <&cpg 314>;
398 max-frequency = <200000000>;
399 status = "disabled";
400 };
401
351 gic: interrupt-controller@f1010000 { 402 gic: interrupt-controller@f1010000 {
352 compatible = "arm,gic-400"; 403 compatible = "arm,gic-400";
353 #interrupt-cells = <3>; 404 #interrupt-cells = <3>;
@@ -361,7 +412,7 @@
361 IRQ_TYPE_LEVEL_HIGH)>; 412 IRQ_TYPE_LEVEL_HIGH)>;
362 clocks = <&cpg CPG_MOD 408>; 413 clocks = <&cpg CPG_MOD 408>;
363 clock-names = "clk"; 414 clock-names = "clk";
364 power-domains = <&sysc 32>; 415 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
365 resets = <&cpg 408>; 416 resets = <&cpg 408>;
366 }; 417 };
367 418
diff --git a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
new file mode 100644
index 000000000000..7a09d0524f9b
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
@@ -0,0 +1,65 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Device Tree Source for the ebisu board
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 */
7
8/dts-v1/;
9#include "r8a77990.dtsi"
10#include <dt-bindings/gpio/gpio.h>
11
12/ {
13 model = "Renesas Ebisu board based on r8a77990";
14 compatible = "renesas,ebisu", "renesas,r8a77990";
15
16 aliases {
17 serial0 = &scif2;
18 ethernet0 = &avb;
19 };
20
21 chosen {
22 bootargs = "ignore_loglevel";
23 stdout-path = "serial0:115200n8";
24 };
25
26 memory@48000000 {
27 device_type = "memory";
28 /* first 128MB is reserved for secure area. */
29 reg = <0x0 0x48000000 0x0 0x38000000>;
30 };
31};
32
33&avb {
34 pinctrl-0 = <&avb_pins>;
35 pinctrl-names = "default";
36 renesas,no-ether-link;
37 phy-handle = <&phy0>;
38 phy-mode = "rgmii-txid";
39 status = "okay";
40
41 phy0: ethernet-phy@0 {
42 rxc-skew-ps = <1500>;
43 reg = <0>;
44 interrupt-parent = <&gpio2>;
45 interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
46 reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
47 };
48};
49
50&extal_clk {
51 clock-frequency = <48000000>;
52};
53
54&pfc {
55 avb_pins: avb {
56 mux {
57 groups = "avb_link", "avb_mii";
58 function = "avb";
59 };
60 };
61};
62
63&scif2 {
64 status = "okay";
65};
diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
new file mode 100644
index 000000000000..be4f519711a1
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
@@ -0,0 +1,281 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Device Tree Source for the r8a77990 SoC
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/renesas-cpg-mssr.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10
11/ {
12 compatible = "renesas,r8a77990";
13 #address-cells = <2>;
14 #size-cells = <2>;
15
16 cpus {
17 #address-cells = <1>;
18 #size-cells = <0>;
19
20 /* 1 core only at this point */
21 a53_0: cpu@0 {
22 compatible = "arm,cortex-a53", "arm,armv8";
23 reg = <0x0>;
24 device_type = "cpu";
25 power-domains = <&sysc 5>;
26 next-level-cache = <&L2_CA53>;
27 enable-method = "psci";
28 };
29
30 L2_CA53: cache-controller-0 {
31 compatible = "cache";
32 power-domains = <&sysc 21>;
33 cache-unified;
34 cache-level = <2>;
35 };
36 };
37
38 extal_clk: extal {
39 compatible = "fixed-clock";
40 #clock-cells = <0>;
41 /* This value must be overridden by the board */
42 clock-frequency = <0>;
43 };
44
45 pmu_a53 {
46 compatible = "arm,cortex-a53-pmu";
47 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
48 interrupt-affinity = <&a53_0>;
49 };
50
51 psci {
52 compatible = "arm,psci-1.0", "arm,psci-0.2";
53 method = "smc";
54 };
55
56 soc: soc {
57 compatible = "simple-bus";
58 interrupt-parent = <&gic>;
59 #address-cells = <2>;
60 #size-cells = <2>;
61 ranges;
62
63 gpio0: gpio@e6050000 {
64 compatible = "renesas,gpio-r8a77990",
65 "renesas,rcar-gen3-gpio";
66 reg = <0 0xe6050000 0 0x50>;
67 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
68 #gpio-cells = <2>;
69 gpio-controller;
70 gpio-ranges = <&pfc 0 0 18>;
71 #interrupt-cells = <2>;
72 interrupt-controller;
73 clocks = <&cpg CPG_MOD 912>;
74 power-domains = <&sysc 32>;
75 resets = <&cpg 912>;
76 };
77
78 gpio1: gpio@e6051000 {
79 compatible = "renesas,gpio-r8a77990",
80 "renesas,rcar-gen3-gpio";
81 reg = <0 0xe6051000 0 0x50>;
82 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
83 #gpio-cells = <2>;
84 gpio-controller;
85 gpio-ranges = <&pfc 0 32 23>;
86 #interrupt-cells = <2>;
87 interrupt-controller;
88 clocks = <&cpg CPG_MOD 911>;
89 power-domains = <&sysc 32>;
90 resets = <&cpg 911>;
91 };
92
93 gpio2: gpio@e6052000 {
94 compatible = "renesas,gpio-r8a77990",
95 "renesas,rcar-gen3-gpio";
96 reg = <0 0xe6052000 0 0x50>;
97 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
98 #gpio-cells = <2>;
99 gpio-controller;
100 gpio-ranges = <&pfc 0 64 26>;
101 #interrupt-cells = <2>;
102 interrupt-controller;
103 clocks = <&cpg CPG_MOD 910>;
104 power-domains = <&sysc 32>;
105 resets = <&cpg 910>;
106 };
107
108 gpio3: gpio@e6053000 {
109 compatible = "renesas,gpio-r8a77990",
110 "renesas,rcar-gen3-gpio";
111 reg = <0 0xe6053000 0 0x50>;
112 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
113 #gpio-cells = <2>;
114 gpio-controller;
115 gpio-ranges = <&pfc 0 96 16>;
116 #interrupt-cells = <2>;
117 interrupt-controller;
118 clocks = <&cpg CPG_MOD 909>;
119 power-domains = <&sysc 32>;
120 resets = <&cpg 909>;
121 };
122
123 gpio4: gpio@e6054000 {
124 compatible = "renesas,gpio-r8a77990",
125 "renesas,rcar-gen3-gpio";
126 reg = <0 0xe6054000 0 0x50>;
127 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
128 #gpio-cells = <2>;
129 gpio-controller;
130 gpio-ranges = <&pfc 0 128 11>;
131 #interrupt-cells = <2>;
132 interrupt-controller;
133 clocks = <&cpg CPG_MOD 908>;
134 power-domains = <&sysc 32>;
135 resets = <&cpg 908>;
136 };
137
138 gpio5: gpio@e6055000 {
139 compatible = "renesas,gpio-r8a77990",
140 "renesas,rcar-gen3-gpio";
141 reg = <0 0xe6055000 0 0x50>;
142 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
143 #gpio-cells = <2>;
144 gpio-controller;
145 gpio-ranges = <&pfc 0 160 20>;
146 #interrupt-cells = <2>;
147 interrupt-controller;
148 clocks = <&cpg CPG_MOD 907>;
149 power-domains = <&sysc 32>;
150 resets = <&cpg 907>;
151 };
152
153 gpio6: gpio@e6055400 {
154 compatible = "renesas,gpio-r8a77990",
155 "renesas,rcar-gen3-gpio";
156 reg = <0 0xe6055400 0 0x50>;
157 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
158 #gpio-cells = <2>;
159 gpio-controller;
160 gpio-ranges = <&pfc 0 192 18>;
161 #interrupt-cells = <2>;
162 interrupt-controller;
163 clocks = <&cpg CPG_MOD 906>;
164 power-domains = <&sysc 32>;
165 resets = <&cpg 906>;
166 };
167
168 pfc: pin-controller@e6060000 {
169 compatible = "renesas,pfc-r8a77990";
170 reg = <0 0xe6060000 0 0x508>;
171 };
172
173 cpg: clock-controller@e6150000 {
174 compatible = "renesas,r8a77990-cpg-mssr";
175 reg = <0 0xe6150000 0 0x1000>;
176 clocks = <&extal_clk>;
177 clock-names = "extal";
178 #clock-cells = <2>;
179 #power-domain-cells = <0>;
180 #reset-cells = <1>;
181 };
182
183 rst: reset-controller@e6160000 {
184 compatible = "renesas,r8a77990-rst";
185 reg = <0 0xe6160000 0 0x0200>;
186 };
187
188 sysc: system-controller@e6180000 {
189 compatible = "renesas,r8a77990-sysc";
190 reg = <0 0xe6180000 0 0x0400>;
191 #power-domain-cells = <1>;
192 };
193
194 avb: ethernet@e6800000 {
195 compatible = "renesas,etheravb-r8a77990",
196 "renesas,etheravb-rcar-gen3";
197 reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
198 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
199 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
200 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
201 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
202 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
203 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
204 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
205 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
206 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
207 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
208 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
209 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
210 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
211 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
212 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
213 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
214 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
215 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
216 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
217 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
218 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
219 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
220 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
221 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
222 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
223 interrupt-names = "ch0", "ch1", "ch2", "ch3",
224 "ch4", "ch5", "ch6", "ch7",
225 "ch8", "ch9", "ch10", "ch11",
226 "ch12", "ch13", "ch14", "ch15",
227 "ch16", "ch17", "ch18", "ch19",
228 "ch20", "ch21", "ch22", "ch23",
229 "ch24";
230 clocks = <&cpg CPG_MOD 812>;
231 power-domains = <&sysc 32>;
232 resets = <&cpg 812>;
233 phy-mode = "rgmii";
234 #address-cells = <1>;
235 #size-cells = <0>;
236 status = "disabled";
237 };
238
239 scif2: serial@e6e88000 {
240 compatible = "renesas,scif-r8a77990",
241 "renesas,rcar-gen3-scif", "renesas,scif";
242 reg = <0 0xe6e88000 0 64>;
243 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
244 clocks = <&cpg CPG_MOD 310>;
245 clock-names = "fck";
246 power-domains = <&sysc 32>;
247 resets = <&cpg 310>;
248 status = "disabled";
249 };
250
251 gic: interrupt-controller@f1010000 {
252 compatible = "arm,gic-400";
253 #interrupt-cells = <3>;
254 #address-cells = <0>;
255 interrupt-controller;
256 reg = <0x0 0xf1010000 0 0x1000>,
257 <0x0 0xf1020000 0 0x20000>,
258 <0x0 0xf1040000 0 0x20000>,
259 <0x0 0xf1060000 0 0x20000>;
260 interrupts = <GIC_PPI 9
261 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
262 clocks = <&cpg CPG_MOD 408>;
263 clock-names = "clk";
264 power-domains = <&sysc 32>;
265 resets = <&cpg 408>;
266 };
267
268 prr: chipid@fff00044 {
269 compatible = "renesas,prr";
270 reg = <0 0xfff00044 0 4>;
271 };
272 };
273
274 timer {
275 compatible = "arm,armv8-timer";
276 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
277 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
278 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
279 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
280 };
281};
diff --git a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
index d03f19414028..9d73de8bc94d 100644
--- a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
@@ -91,7 +91,7 @@
91&pfc { 91&pfc {
92 avb0_pins: avb { 92 avb0_pins: avb {
93 mux { 93 mux {
94 groups = "avb0_link", "avb0_mdc", "avb0_mii"; 94 groups = "avb0_link", "avb0_mdio", "avb0_mii";
95 function = "avb0"; 95 function = "avb0";
96 }; 96 };
97 }; 97 };
diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
index 82aed7ee984c..2506f46293e8 100644
--- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
@@ -18,9 +18,11 @@
18 #address-cells = <2>; 18 #address-cells = <2>;
19 #size-cells = <2>; 19 #size-cells = <2>;
20 20
21 psci { 21 /* External CAN clock - to be overridden by boards that provide it */
22 compatible = "arm,psci-1.0", "arm,psci-0.2"; 22 can_clk: can {
23 method = "smc"; 23 compatible = "fixed-clock";
24 #clock-cells = <0>;
25 clock-frequency = <0>;
24 }; 26 };
25 27
26 cpus { 28 cpus {
@@ -51,18 +53,16 @@
51 clock-frequency = <0>; 53 clock-frequency = <0>;
52 }; 54 };
53 55
54 /* External CAN clock - to be overridden by boards that provide it */
55 can_clk: can {
56 compatible = "fixed-clock";
57 #clock-cells = <0>;
58 clock-frequency = <0>;
59 };
60
61 pmu_a53 { 56 pmu_a53 {
62 compatible = "arm,cortex-a53-pmu"; 57 compatible = "arm,cortex-a53-pmu";
63 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 58 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
64 }; 59 };
65 60
61 psci {
62 compatible = "arm,psci-1.0", "arm,psci-0.2";
63 method = "smc";
64 };
65
66 scif_clk: scif { 66 scif_clk: scif {
67 compatible = "fixed-clock"; 67 compatible = "fixed-clock";
68 #clock-cells = <0>; 68 #clock-cells = <0>;
@@ -76,23 +76,6 @@
76 #size-cells = <2>; 76 #size-cells = <2>;
77 ranges; 77 ranges;
78 78
79 gic: interrupt-controller@f1010000 {
80 compatible = "arm,gic-400";
81 #interrupt-cells = <3>;
82 #address-cells = <0>;
83 interrupt-controller;
84 reg = <0x0 0xf1010000 0 0x1000>,
85 <0x0 0xf1020000 0 0x20000>,
86 <0x0 0xf1040000 0 0x20000>,
87 <0x0 0xf1060000 0 0x20000>;
88 interrupts = <GIC_PPI 9
89 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
90 clocks = <&cpg CPG_MOD 408>;
91 clock-names = "clk";
92 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
93 resets = <&cpg 408>;
94 };
95
96 rwdt: watchdog@e6020000 { 79 rwdt: watchdog@e6020000 {
97 compatible = "renesas,r8a77995-wdt", 80 compatible = "renesas,r8a77995-wdt",
98 "renesas,rcar-gen3-wdt"; 81 "renesas,rcar-gen3-wdt";
@@ -103,207 +86,6 @@
103 status = "disabled"; 86 status = "disabled";
104 }; 87 };
105 88
106 ipmmu_vi0: mmu@febd0000 {
107 compatible = "renesas,ipmmu-r8a77995";
108 reg = <0 0xfebd0000 0 0x1000>;
109 renesas,ipmmu-main = <&ipmmu_mm 14>;
110 #iommu-cells = <1>;
111 status = "disabled";
112 };
113
114 ipmmu_vp0: mmu@fe990000 {
115 compatible = "renesas,ipmmu-r8a77995";
116 reg = <0 0xfe990000 0 0x1000>;
117 renesas,ipmmu-main = <&ipmmu_mm 16>;
118 #iommu-cells = <1>;
119 status = "disabled";
120 };
121
122 ipmmu_vc0: mmu@fe6b0000 {
123 compatible = "renesas,ipmmu-r8a77995";
124 reg = <0 0xfe6b0000 0 0x1000>;
125 renesas,ipmmu-main = <&ipmmu_mm 12>;
126 #iommu-cells = <1>;
127 status = "disabled";
128 };
129
130 ipmmu_pv0: mmu@fd800000 {
131 compatible = "renesas,ipmmu-r8a77995";
132 reg = <0 0xfd800000 0 0x1000>;
133 renesas,ipmmu-main = <&ipmmu_mm 6>;
134 #iommu-cells = <1>;
135 status = "disabled";
136 };
137
138 ipmmu_hc: mmu@e6570000 {
139 compatible = "renesas,ipmmu-r8a77995";
140 reg = <0 0xe6570000 0 0x1000>;
141 renesas,ipmmu-main = <&ipmmu_mm 2>;
142 #iommu-cells = <1>;
143 status = "disabled";
144 };
145
146 ipmmu_rt: mmu@ffc80000 {
147 compatible = "renesas,ipmmu-r8a77995";
148 reg = <0 0xffc80000 0 0x1000>;
149 renesas,ipmmu-main = <&ipmmu_mm 10>;
150 #iommu-cells = <1>;
151 status = "disabled";
152 };
153
154 ipmmu_mp: mmu@ec670000 {
155 compatible = "renesas,ipmmu-r8a77995";
156 reg = <0 0xec670000 0 0x1000>;
157 renesas,ipmmu-main = <&ipmmu_mm 4>;
158 #iommu-cells = <1>;
159 status = "disabled";
160 };
161
162 ipmmu_ds0: mmu@e6740000 {
163 compatible = "renesas,ipmmu-r8a77995";
164 reg = <0 0xe6740000 0 0x1000>;
165 renesas,ipmmu-main = <&ipmmu_mm 0>;
166 #iommu-cells = <1>;
167 status = "disabled";
168 };
169
170 ipmmu_ds1: mmu@e7740000 {
171 compatible = "renesas,ipmmu-r8a77995";
172 reg = <0 0xe7740000 0 0x1000>;
173 renesas,ipmmu-main = <&ipmmu_mm 1>;
174 #iommu-cells = <1>;
175 status = "disabled";
176 };
177
178 ipmmu_mm: mmu@e67b0000 {
179 compatible = "renesas,ipmmu-r8a77995";
180 reg = <0 0xe67b0000 0 0x1000>;
181 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
182 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
183 #iommu-cells = <1>;
184 status = "disabled";
185 };
186
187
188 cpg: clock-controller@e6150000 {
189 compatible = "renesas,r8a77995-cpg-mssr";
190 reg = <0 0xe6150000 0 0x1000>;
191 clocks = <&extal_clk>;
192 clock-names = "extal";
193 #clock-cells = <2>;
194 #power-domain-cells = <0>;
195 #reset-cells = <1>;
196 };
197
198 rst: reset-controller@e6160000 {
199 compatible = "renesas,r8a77995-rst";
200 reg = <0 0xe6160000 0 0x0200>;
201 };
202
203 pfc: pin-controller@e6060000 {
204 compatible = "renesas,pfc-r8a77995";
205 reg = <0 0xe6060000 0 0x508>;
206 };
207
208 prr: chipid@fff00044 {
209 compatible = "renesas,prr";
210 reg = <0 0xfff00044 0 4>;
211 };
212
213 sysc: system-controller@e6180000 {
214 compatible = "renesas,r8a77995-sysc";
215 reg = <0 0xe6180000 0 0x0400>;
216 #power-domain-cells = <1>;
217 };
218
219 intc_ex: interrupt-controller@e61c0000 {
220 compatible = "renesas,intc-ex-r8a77995", "renesas,irqc";
221 #interrupt-cells = <2>;
222 interrupt-controller;
223 reg = <0 0xe61c0000 0 0x200>;
224 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
225 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
226 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
227 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
228 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
229 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
230 clocks = <&cpg CPG_MOD 407>;
231 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
232 resets = <&cpg 407>;
233 };
234
235 dmac0: dma-controller@e6700000 {
236 compatible = "renesas,dmac-r8a77995",
237 "renesas,rcar-dmac";
238 reg = <0 0xe6700000 0 0x10000>;
239 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH
240 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
241 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
242 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
243 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
244 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
245 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
246 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
247 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
248 interrupt-names = "error",
249 "ch0", "ch1", "ch2", "ch3",
250 "ch4", "ch5", "ch6", "ch7";
251 clocks = <&cpg CPG_MOD 219>;
252 clock-names = "fck";
253 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
254 resets = <&cpg 219>;
255 #dma-cells = <1>;
256 dma-channels = <8>;
257 };
258
259 dmac1: dma-controller@e7300000 {
260 compatible = "renesas,dmac-r8a77995",
261 "renesas,rcar-dmac";
262 reg = <0 0xe7300000 0 0x10000>;
263 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
264 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
265 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
266 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
267 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
268 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
269 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
270 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
271 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
272 interrupt-names = "error",
273 "ch0", "ch1", "ch2", "ch3",
274 "ch4", "ch5", "ch6", "ch7";
275 clocks = <&cpg CPG_MOD 218>;
276 clock-names = "fck";
277 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
278 resets = <&cpg 218>;
279 #dma-cells = <1>;
280 dma-channels = <8>;
281 };
282
283 dmac2: dma-controller@e7310000 {
284 compatible = "renesas,dmac-r8a77995",
285 "renesas,rcar-dmac";
286 reg = <0 0xe7310000 0 0x10000>;
287 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH
288 GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH
289 GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH
290 GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH
291 GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH
292 GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH
293 GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH
294 GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH
295 GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>;
296 interrupt-names = "error",
297 "ch0", "ch1", "ch2", "ch3",
298 "ch4", "ch5", "ch6", "ch7";
299 clocks = <&cpg CPG_MOD 217>;
300 clock-names = "fck";
301 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
302 resets = <&cpg 217>;
303 #dma-cells = <1>;
304 dma-channels = <8>;
305 };
306
307 gpio0: gpio@e6050000 { 89 gpio0: gpio@e6050000 {
308 compatible = "renesas,gpio-r8a77995", 90 compatible = "renesas,gpio-r8a77995",
309 "renesas,rcar-gen3-gpio", 91 "renesas,rcar-gen3-gpio",
@@ -416,35 +198,112 @@
416 resets = <&cpg 906>; 198 resets = <&cpg 906>;
417 }; 199 };
418 200
419 can0: can@e6c30000 { 201 pfc: pin-controller@e6060000 {
420 compatible = "renesas,can-r8a77995", 202 compatible = "renesas,pfc-r8a77995";
421 "renesas,rcar-gen3-can"; 203 reg = <0 0xe6060000 0 0x508>;
422 reg = <0 0xe6c30000 0 0x1000>; 204 };
423 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 205
424 clocks = <&cpg CPG_MOD 916>, 206 cpg: clock-controller@e6150000 {
425 <&cpg CPG_CORE R8A77995_CLK_CANFD>, 207 compatible = "renesas,r8a77995-cpg-mssr";
426 <&can_clk>; 208 reg = <0 0xe6150000 0 0x1000>;
427 clock-names = "clkp1", "clkp2", "can_clk"; 209 clocks = <&extal_clk>;
428 assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>; 210 clock-names = "extal";
429 assigned-clock-rates = <40000000>; 211 #clock-cells = <2>;
212 #power-domain-cells = <0>;
213 #reset-cells = <1>;
214 };
215
216 rst: reset-controller@e6160000 {
217 compatible = "renesas,r8a77995-rst";
218 reg = <0 0xe6160000 0 0x0200>;
219 };
220
221 sysc: system-controller@e6180000 {
222 compatible = "renesas,r8a77995-sysc";
223 reg = <0 0xe6180000 0 0x0400>;
224 #power-domain-cells = <1>;
225 };
226
227 intc_ex: interrupt-controller@e61c0000 {
228 compatible = "renesas,intc-ex-r8a77995", "renesas,irqc";
229 #interrupt-cells = <2>;
230 interrupt-controller;
231 reg = <0 0xe61c0000 0 0x200>;
232 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
233 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
234 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
235 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
236 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
237 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
238 clocks = <&cpg CPG_MOD 407>;
430 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 239 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
431 resets = <&cpg 916>; 240 resets = <&cpg 407>;
241 };
242
243 i2c0: i2c@e6500000 {
244 #address-cells = <1>;
245 #size-cells = <0>;
246 compatible = "renesas,i2c-r8a77995",
247 "renesas,rcar-gen3-i2c";
248 reg = <0 0xe6500000 0 0x40>;
249 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
250 clocks = <&cpg CPG_MOD 931>;
251 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
252 resets = <&cpg 931>;
253 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
254 <&dmac2 0x91>, <&dmac2 0x90>;
255 dma-names = "tx", "rx", "tx", "rx";
256 i2c-scl-internal-delay-ns = <6>;
432 status = "disabled"; 257 status = "disabled";
433 }; 258 };
434 259
435 can1: can@e6c38000 { 260 i2c1: i2c@e6508000 {
436 compatible = "renesas,can-r8a77995", 261 #address-cells = <1>;
437 "renesas,rcar-gen3-can"; 262 #size-cells = <0>;
438 reg = <0 0xe6c38000 0 0x1000>; 263 compatible = "renesas,i2c-r8a77995",
439 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 264 "renesas,rcar-gen3-i2c";
440 clocks = <&cpg CPG_MOD 915>, 265 reg = <0 0xe6508000 0 0x40>;
441 <&cpg CPG_CORE R8A77995_CLK_CANFD>, 266 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
442 <&can_clk>; 267 clocks = <&cpg CPG_MOD 930>;
443 clock-names = "clkp1", "clkp2", "can_clk";
444 assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
445 assigned-clock-rates = <40000000>;
446 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 268 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
447 resets = <&cpg 915>; 269 resets = <&cpg 930>;
270 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
271 <&dmac2 0x93>, <&dmac2 0x92>;
272 dma-names = "tx", "rx", "tx", "rx";
273 i2c-scl-internal-delay-ns = <6>;
274 status = "disabled";
275 };
276
277 i2c2: i2c@e6510000 {
278 #address-cells = <1>;
279 #size-cells = <0>;
280 compatible = "renesas,i2c-r8a77995",
281 "renesas,rcar-gen3-i2c";
282 reg = <0 0xe6510000 0 0x40>;
283 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
284 clocks = <&cpg CPG_MOD 929>;
285 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
286 resets = <&cpg 929>;
287 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
288 <&dmac2 0x95>, <&dmac2 0x94>;
289 dma-names = "tx", "rx", "tx", "rx";
290 i2c-scl-internal-delay-ns = <6>;
291 status = "disabled";
292 };
293
294 i2c3: i2c@e66d0000 {
295 #address-cells = <1>;
296 #size-cells = <0>;
297 compatible = "renesas,i2c-r8a77995",
298 "renesas,rcar-gen3-i2c";
299 reg = <0 0xe66d0000 0 0x40>;
300 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
301 clocks = <&cpg CPG_MOD 928>;
302 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
303 resets = <&cpg 928>;
304 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
305 dma-names = "tx", "rx";
306 i2c-scl-internal-delay-ns = <6>;
448 status = "disabled"; 307 status = "disabled";
449 }; 308 };
450 309
@@ -473,6 +332,149 @@
473 }; 332 };
474 }; 333 };
475 334
335 dmac0: dma-controller@e6700000 {
336 compatible = "renesas,dmac-r8a77995",
337 "renesas,rcar-dmac";
338 reg = <0 0xe6700000 0 0x10000>;
339 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH
340 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
341 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
342 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
343 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
344 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
345 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
346 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
347 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
348 interrupt-names = "error",
349 "ch0", "ch1", "ch2", "ch3",
350 "ch4", "ch5", "ch6", "ch7";
351 clocks = <&cpg CPG_MOD 219>;
352 clock-names = "fck";
353 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
354 resets = <&cpg 219>;
355 #dma-cells = <1>;
356 dma-channels = <8>;
357 };
358
359 dmac1: dma-controller@e7300000 {
360 compatible = "renesas,dmac-r8a77995",
361 "renesas,rcar-dmac";
362 reg = <0 0xe7300000 0 0x10000>;
363 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
364 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
365 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
366 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
367 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
368 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
369 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
370 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
371 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
372 interrupt-names = "error",
373 "ch0", "ch1", "ch2", "ch3",
374 "ch4", "ch5", "ch6", "ch7";
375 clocks = <&cpg CPG_MOD 218>;
376 clock-names = "fck";
377 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
378 resets = <&cpg 218>;
379 #dma-cells = <1>;
380 dma-channels = <8>;
381 };
382
383 dmac2: dma-controller@e7310000 {
384 compatible = "renesas,dmac-r8a77995",
385 "renesas,rcar-dmac";
386 reg = <0 0xe7310000 0 0x10000>;
387 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH
388 GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH
389 GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH
390 GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH
391 GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH
392 GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH
393 GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH
394 GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH
395 GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>;
396 interrupt-names = "error",
397 "ch0", "ch1", "ch2", "ch3",
398 "ch4", "ch5", "ch6", "ch7";
399 clocks = <&cpg CPG_MOD 217>;
400 clock-names = "fck";
401 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
402 resets = <&cpg 217>;
403 #dma-cells = <1>;
404 dma-channels = <8>;
405 };
406
407 ipmmu_ds0: mmu@e6740000 {
408 compatible = "renesas,ipmmu-r8a77995";
409 reg = <0 0xe6740000 0 0x1000>;
410 renesas,ipmmu-main = <&ipmmu_mm 0>;
411 #iommu-cells = <1>;
412 };
413
414 ipmmu_ds1: mmu@e7740000 {
415 compatible = "renesas,ipmmu-r8a77995";
416 reg = <0 0xe7740000 0 0x1000>;
417 renesas,ipmmu-main = <&ipmmu_mm 1>;
418 #iommu-cells = <1>;
419 };
420
421 ipmmu_hc: mmu@e6570000 {
422 compatible = "renesas,ipmmu-r8a77995";
423 reg = <0 0xe6570000 0 0x1000>;
424 renesas,ipmmu-main = <&ipmmu_mm 2>;
425 #iommu-cells = <1>;
426 };
427
428 ipmmu_mm: mmu@e67b0000 {
429 compatible = "renesas,ipmmu-r8a77995";
430 reg = <0 0xe67b0000 0 0x1000>;
431 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
432 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
433 #iommu-cells = <1>;
434 };
435
436 ipmmu_mp: mmu@ec670000 {
437 compatible = "renesas,ipmmu-r8a77995";
438 reg = <0 0xec670000 0 0x1000>;
439 renesas,ipmmu-main = <&ipmmu_mm 4>;
440 #iommu-cells = <1>;
441 };
442
443 ipmmu_pv0: mmu@fd800000 {
444 compatible = "renesas,ipmmu-r8a77995";
445 reg = <0 0xfd800000 0 0x1000>;
446 renesas,ipmmu-main = <&ipmmu_mm 6>;
447 #iommu-cells = <1>;
448 };
449
450 ipmmu_rt: mmu@ffc80000 {
451 compatible = "renesas,ipmmu-r8a77995";
452 reg = <0 0xffc80000 0 0x1000>;
453 renesas,ipmmu-main = <&ipmmu_mm 10>;
454 #iommu-cells = <1>;
455 };
456
457 ipmmu_vc0: mmu@fe6b0000 {
458 compatible = "renesas,ipmmu-r8a77995";
459 reg = <0 0xfe6b0000 0 0x1000>;
460 renesas,ipmmu-main = <&ipmmu_mm 12>;
461 #iommu-cells = <1>;
462 };
463
464 ipmmu_vi0: mmu@febd0000 {
465 compatible = "renesas,ipmmu-r8a77995";
466 reg = <0 0xfebd0000 0 0x1000>;
467 renesas,ipmmu-main = <&ipmmu_mm 14>;
468 #iommu-cells = <1>;
469 };
470
471 ipmmu_vp0: mmu@fe990000 {
472 compatible = "renesas,ipmmu-r8a77995";
473 reg = <0 0xfe990000 0 0x1000>;
474 renesas,ipmmu-main = <&ipmmu_mm 16>;
475 #iommu-cells = <1>;
476 };
477
476 avb: ethernet@e6800000 { 478 avb: ethernet@e6800000 {
477 compatible = "renesas,etheravb-r8a77995", 479 compatible = "renesas,etheravb-r8a77995",
478 "renesas,etheravb-rcar-gen3"; 480 "renesas,etheravb-rcar-gen3";
@@ -519,87 +521,35 @@
519 status = "disabled"; 521 status = "disabled";
520 }; 522 };
521 523
522 scif2: serial@e6e88000 { 524 can0: can@e6c30000 {
523 compatible = "renesas,scif-r8a77995", 525 compatible = "renesas,can-r8a77995",
524 "renesas,rcar-gen3-scif", "renesas,scif"; 526 "renesas,rcar-gen3-can";
525 reg = <0 0xe6e88000 0 64>; 527 reg = <0 0xe6c30000 0 0x1000>;
526 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 528 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
527 clocks = <&cpg CPG_MOD 310>, 529 clocks = <&cpg CPG_MOD 916>,
528 <&cpg CPG_CORE R8A77995_CLK_S3D1C>, 530 <&cpg CPG_CORE R8A77995_CLK_CANFD>,
529 <&scif_clk>; 531 <&can_clk>;
530 clock-names = "fck", "brg_int", "scif_clk"; 532 clock-names = "clkp1", "clkp2", "can_clk";
531 dmas = <&dmac1 0x13>, <&dmac1 0x12>, 533 assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
532 <&dmac2 0x13>, <&dmac2 0x12>; 534 assigned-clock-rates = <40000000>;
533 dma-names = "tx", "rx", "tx", "rx";
534 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
535 resets = <&cpg 310>;
536 status = "disabled";
537 };
538
539 i2c0: i2c@e6500000 {
540 #address-cells = <1>;
541 #size-cells = <0>;
542 compatible = "renesas,i2c-r8a77995",
543 "renesas,rcar-gen3-i2c";
544 reg = <0 0xe6500000 0 0x40>;
545 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
546 clocks = <&cpg CPG_MOD 931>;
547 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
548 resets = <&cpg 931>;
549 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
550 <&dmac2 0x91>, <&dmac2 0x90>;
551 dma-names = "tx", "rx", "tx", "rx";
552 i2c-scl-internal-delay-ns = <6>;
553 status = "disabled";
554 };
555
556 i2c1: i2c@e6508000 {
557 #address-cells = <1>;
558 #size-cells = <0>;
559 compatible = "renesas,i2c-r8a77995",
560 "renesas,rcar-gen3-i2c";
561 reg = <0 0xe6508000 0 0x40>;
562 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
563 clocks = <&cpg CPG_MOD 930>;
564 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
565 resets = <&cpg 930>;
566 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
567 <&dmac2 0x93>, <&dmac2 0x92>;
568 dma-names = "tx", "rx", "tx", "rx";
569 i2c-scl-internal-delay-ns = <6>;
570 status = "disabled";
571 };
572
573 i2c2: i2c@e6510000 {
574 #address-cells = <1>;
575 #size-cells = <0>;
576 compatible = "renesas,i2c-r8a77995",
577 "renesas,rcar-gen3-i2c";
578 reg = <0 0xe6510000 0 0x40>;
579 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
580 clocks = <&cpg CPG_MOD 929>;
581 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 535 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
582 resets = <&cpg 929>; 536 resets = <&cpg 916>;
583 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
584 <&dmac2 0x95>, <&dmac2 0x94>;
585 dma-names = "tx", "rx", "tx", "rx";
586 i2c-scl-internal-delay-ns = <6>;
587 status = "disabled"; 537 status = "disabled";
588 }; 538 };
589 539
590 i2c3: i2c@e66d0000 { 540 can1: can@e6c38000 {
591 #address-cells = <1>; 541 compatible = "renesas,can-r8a77995",
592 #size-cells = <0>; 542 "renesas,rcar-gen3-can";
593 compatible = "renesas,i2c-r8a77995", 543 reg = <0 0xe6c38000 0 0x1000>;
594 "renesas,rcar-gen3-i2c"; 544 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
595 reg = <0 0xe66d0000 0 0x40>; 545 clocks = <&cpg CPG_MOD 915>,
596 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 546 <&cpg CPG_CORE R8A77995_CLK_CANFD>,
597 clocks = <&cpg CPG_MOD 928>; 547 <&can_clk>;
548 clock-names = "clkp1", "clkp2", "can_clk";
549 assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
550 assigned-clock-rates = <40000000>;
598 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 551 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
599 resets = <&cpg 928>; 552 resets = <&cpg 915>;
600 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
601 dma-names = "tx", "rx";
602 i2c-scl-internal-delay-ns = <6>;
603 status = "disabled"; 553 status = "disabled";
604 }; 554 };
605 555
@@ -643,38 +593,54 @@
643 status = "disabled"; 593 status = "disabled";
644 }; 594 };
645 595
646 sdhi2: sd@ee140000 { 596 scif2: serial@e6e88000 {
647 compatible = "renesas,sdhi-r8a77995", 597 compatible = "renesas,scif-r8a77995",
648 "renesas,rcar-gen3-sdhi"; 598 "renesas,rcar-gen3-scif", "renesas,scif";
649 reg = <0 0xee140000 0 0x2000>; 599 reg = <0 0xe6e88000 0 64>;
650 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 600 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
651 clocks = <&cpg CPG_MOD 312>; 601 clocks = <&cpg CPG_MOD 310>,
652 max-frequency = <200000000>; 602 <&cpg CPG_CORE R8A77995_CLK_S3D1C>,
603 <&scif_clk>;
604 clock-names = "fck", "brg_int", "scif_clk";
605 dmas = <&dmac1 0x13>, <&dmac1 0x12>,
606 <&dmac2 0x13>, <&dmac2 0x12>;
607 dma-names = "tx", "rx", "tx", "rx";
653 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 608 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
654 resets = <&cpg 312>; 609 resets = <&cpg 310>;
655 status = "disabled"; 610 status = "disabled";
656 }; 611 };
657 612
658 ehci0: usb@ee080100 { 613 vin4: video@e6ef4000 {
659 compatible = "generic-ehci"; 614 compatible = "renesas,vin-r8a77995";
660 reg = <0 0xee080100 0 0x100>; 615 reg = <0 0xe6ef4000 0 0x1000>;
616 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
617 clocks = <&cpg CPG_MOD 807>;
618 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
619 resets = <&cpg 807>;
620 renesas,id = <4>;
621 status = "disabled";
622 };
623
624 ohci0: usb@ee080000 {
625 compatible = "generic-ohci";
626 reg = <0 0xee080000 0 0x100>;
661 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 627 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
662 clocks = <&cpg CPG_MOD 703>; 628 clocks = <&cpg CPG_MOD 703>;
663 phys = <&usb2_phy0>; 629 phys = <&usb2_phy0>;
664 phy-names = "usb"; 630 phy-names = "usb";
665 companion = <&ohci0>;
666 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 631 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
667 resets = <&cpg 703>; 632 resets = <&cpg 703>;
668 status = "disabled"; 633 status = "disabled";
669 }; 634 };
670 635
671 ohci0: usb@ee080000 { 636 ehci0: usb@ee080100 {
672 compatible = "generic-ohci"; 637 compatible = "generic-ehci";
673 reg = <0 0xee080000 0 0x100>; 638 reg = <0 0xee080100 0 0x100>;
674 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 639 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
675 clocks = <&cpg CPG_MOD 703>; 640 clocks = <&cpg CPG_MOD 703>;
676 phys = <&usb2_phy0>; 641 phys = <&usb2_phy0>;
677 phy-names = "usb"; 642 phy-names = "usb";
643 companion = <&ohci0>;
678 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 644 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
679 resets = <&cpg 703>; 645 resets = <&cpg 703>;
680 status = "disabled"; 646 status = "disabled";
@@ -692,6 +658,35 @@
692 status = "disabled"; 658 status = "disabled";
693 }; 659 };
694 660
661 sdhi2: sd@ee140000 {
662 compatible = "renesas,sdhi-r8a77995",
663 "renesas,rcar-gen3-sdhi";
664 reg = <0 0xee140000 0 0x2000>;
665 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
666 clocks = <&cpg CPG_MOD 312>;
667 max-frequency = <200000000>;
668 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
669 resets = <&cpg 312>;
670 status = "disabled";
671 };
672
673 gic: interrupt-controller@f1010000 {
674 compatible = "arm,gic-400";
675 #interrupt-cells = <3>;
676 #address-cells = <0>;
677 interrupt-controller;
678 reg = <0x0 0xf1010000 0 0x1000>,
679 <0x0 0xf1020000 0 0x20000>,
680 <0x0 0xf1040000 0 0x20000>,
681 <0x0 0xf1060000 0 0x20000>;
682 interrupts = <GIC_PPI 9
683 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
684 clocks = <&cpg CPG_MOD 408>;
685 clock-names = "clk";
686 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
687 resets = <&cpg 408>;
688 };
689
695 vspbs: vsp@fe960000 { 690 vspbs: vsp@fe960000 {
696 compatible = "renesas,vsp2"; 691 compatible = "renesas,vsp2";
697 reg = <0 0xfe960000 0 0x8000>; 692 reg = <0 0xfe960000 0 0x8000>;
@@ -702,15 +697,6 @@
702 renesas,fcp = <&fcpvb0>; 697 renesas,fcp = <&fcpvb0>;
703 }; 698 };
704 699
705 fcpvb0: fcp@fe96f000 {
706 compatible = "renesas,fcpv";
707 reg = <0 0xfe96f000 0 0x200>;
708 clocks = <&cpg CPG_MOD 607>;
709 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
710 resets = <&cpg 607>;
711 iommus = <&ipmmu_vp0 5>;
712 };
713
714 vspd0: vsp@fea20000 { 700 vspd0: vsp@fea20000 {
715 compatible = "renesas,vsp2"; 701 compatible = "renesas,vsp2";
716 reg = <0 0xfea20000 0 0x8000>; 702 reg = <0 0xfea20000 0 0x8000>;
@@ -721,15 +707,6 @@
721 renesas,fcp = <&fcpvd0>; 707 renesas,fcp = <&fcpvd0>;
722 }; 708 };
723 709
724 fcpvd0: fcp@fea27000 {
725 compatible = "renesas,fcpv";
726 reg = <0 0xfea27000 0 0x200>;
727 clocks = <&cpg CPG_MOD 603>;
728 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
729 resets = <&cpg 603>;
730 iommus = <&ipmmu_vi0 8>;
731 };
732
733 vspd1: vsp@fea28000 { 710 vspd1: vsp@fea28000 {
734 compatible = "renesas,vsp2"; 711 compatible = "renesas,vsp2";
735 reg = <0 0xfea28000 0 0x8000>; 712 reg = <0 0xfea28000 0 0x8000>;
@@ -740,6 +717,24 @@
740 renesas,fcp = <&fcpvd1>; 717 renesas,fcp = <&fcpvd1>;
741 }; 718 };
742 719
720 fcpvb0: fcp@fe96f000 {
721 compatible = "renesas,fcpv";
722 reg = <0 0xfe96f000 0 0x200>;
723 clocks = <&cpg CPG_MOD 607>;
724 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
725 resets = <&cpg 607>;
726 iommus = <&ipmmu_vp0 5>;
727 };
728
729 fcpvd0: fcp@fea27000 {
730 compatible = "renesas,fcpv";
731 reg = <0 0xfea27000 0 0x200>;
732 clocks = <&cpg CPG_MOD 603>;
733 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
734 resets = <&cpg 603>;
735 iommus = <&ipmmu_vi0 8>;
736 };
737
743 fcpvd1: fcp@fea2f000 { 738 fcpvd1: fcp@fea2f000 {
744 compatible = "renesas,fcpv"; 739 compatible = "renesas,fcpv";
745 reg = <0 0xfea2f000 0 0x200>; 740 reg = <0 0xfea2f000 0 0x200>;
@@ -783,6 +778,11 @@
783 }; 778 };
784 }; 779 };
785 }; 780 };
781
782 prr: chipid@fff00044 {
783 compatible = "renesas,prr";
784 reg = <0 0xfff00044 0 4>;
785 };
786 }; 786 };
787 787
788 timer { 788 timer {
diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi b/arch/arm64/boot/dts/renesas/salvator-common.dtsi
index 2a7f36abd2dd..9256fbaaab7f 100644
--- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi
+++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi
@@ -66,6 +66,29 @@
66 enable-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; 66 enable-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
67 }; 67 };
68 68
69 cvbs-in {
70 compatible = "composite-video-connector";
71 label = "CVBS IN";
72
73 port {
74 cvbs_con: endpoint {
75 remote-endpoint = <&adv7482_ain7>;
76 };
77 };
78 };
79
80 hdmi-in {
81 compatible = "hdmi-connector";
82 label = "HDMI IN";
83 type = "a";
84
85 port {
86 hdmi_in_con: endpoint {
87 remote-endpoint = <&adv7482_hdmi>;
88 };
89 };
90 };
91
69 reg_1p8v: regulator0 { 92 reg_1p8v: regulator0 {
70 compatible = "regulator-fixed"; 93 compatible = "regulator-fixed";
71 regulator-name = "fixed-1.8V"; 94 regulator-name = "fixed-1.8V";
@@ -93,20 +116,12 @@
93 regulator-always-on; 116 regulator-always-on;
94 }; 117 };
95 118
96 rsnd_ak4613: sound { 119 sound_card: sound {
97 compatible = "simple-audio-card"; 120 compatible = "audio-graph-card";
98
99 simple-audio-card,format = "left_j";
100 simple-audio-card,bitclock-master = <&sndcpu>;
101 simple-audio-card,frame-master = <&sndcpu>;
102 121
103 sndcpu: simple-audio-card,cpu { 122 label = "rcar-sound";
104 sound-dai = <&rcar_sound>;
105 };
106 123
107 sndcodec: simple-audio-card,codec { 124 dais = <&rsnd_port0>;
108 sound-dai = <&ak4613>;
109 };
110 }; 125 };
111 126
112 vbus0_usb2: regulator-vbus0-usb2 { 127 vbus0_usb2: regulator-vbus0-usb2 {
@@ -268,6 +283,37 @@
268 }; 283 };
269}; 284};
270 285
286&csi20 {
287 status = "okay";
288
289 ports {
290 port@0 {
291 reg = <0>;
292 csi20_in: endpoint {
293 clock-lanes = <0>;
294 data-lanes = <1>;
295 remote-endpoint = <&adv7482_txb>;
296 };
297 };
298 };
299};
300
301&csi40 {
302 status = "okay";
303
304 ports {
305 port@0 {
306 reg = <0>;
307
308 csi40_in: endpoint {
309 clock-lanes = <0>;
310 data-lanes = <1 2 3 4>;
311 remote-endpoint = <&adv7482_txa>;
312 };
313 };
314 };
315};
316
271&du { 317&du {
272 pinctrl-0 = <&du_pins>; 318 pinctrl-0 = <&du_pins>;
273 pinctrl-names = "default"; 319 pinctrl-names = "default";
@@ -322,6 +368,12 @@
322 asahi-kasei,out4-single-end; 368 asahi-kasei,out4-single-end;
323 asahi-kasei,out5-single-end; 369 asahi-kasei,out5-single-end;
324 asahi-kasei,out6-single-end; 370 asahi-kasei,out6-single-end;
371
372 port {
373 ak4613_endpoint: endpoint {
374 remote-endpoint = <&rsnd_endpoint0>;
375 };
376 };
325 }; 377 };
326 378
327 cs2000: clk_multiplier@4f { 379 cs2000: clk_multiplier@4f {
@@ -359,6 +411,55 @@
359 411
360 shunt-resistor-micro-ohms = <5000>; 412 shunt-resistor-micro-ohms = <5000>;
361 }; 413 };
414
415 video-receiver@70 {
416 compatible = "adi,adv7482";
417 reg = <0x70>;
418
419 #address-cells = <1>;
420 #size-cells = <0>;
421
422 interrupt-parent = <&gpio6>;
423 interrupt-names = "intrq1", "intrq2";
424 interrupts = <30 IRQ_TYPE_LEVEL_LOW>,
425 <31 IRQ_TYPE_LEVEL_LOW>;
426
427 port@7 {
428 reg = <7>;
429
430 adv7482_ain7: endpoint {
431 remote-endpoint = <&cvbs_con>;
432 };
433 };
434
435 port@8 {
436 reg = <8>;
437
438 adv7482_hdmi: endpoint {
439 remote-endpoint = <&hdmi_in_con>;
440 };
441 };
442
443 port@10 {
444 reg = <10>;
445
446 adv7482_txa: endpoint {
447 clock-lanes = <0>;
448 data-lanes = <1 2 3 4>;
449 remote-endpoint = <&csi40_in>;
450 };
451 };
452
453 port@11 {
454 reg = <11>;
455
456 adv7482_txb: endpoint {
457 clock-lanes = <0>;
458 data-lanes = <1>;
459 remote-endpoint = <&csi20_in>;
460 };
461 };
462 };
362}; 463};
363 464
364&i2c_dvfs { 465&i2c_dvfs {
@@ -376,6 +477,8 @@
376 #interrupt-cells = <2>; 477 #interrupt-cells = <2>;
377 gpio-controller; 478 gpio-controller;
378 #gpio-cells = <2>; 479 #gpio-cells = <2>;
480 rohm,ddr-backup-power = <0xf>;
481 rohm,rstbmode-level;
379 482
380 regulators { 483 regulators {
381 dvfs: dvfs { 484 dvfs: dvfs {
@@ -387,6 +490,12 @@
387 }; 490 };
388 }; 491 };
389 }; 492 };
493
494 eeprom@50 {
495 compatible = "rohm,br24t01", "atmel,24c01";
496 reg = <0x50>;
497 pagesize = <8>;
498 };
390}; 499};
391 500
392&ohci0 { 501&ohci0 {
@@ -416,12 +525,12 @@
416 525
417 avb_pins: avb { 526 avb_pins: avb {
418 mux { 527 mux {
419 groups = "avb_link", "avb_mdc", "avb_mii"; 528 groups = "avb_link", "avb_mdio", "avb_mii";
420 function = "avb"; 529 function = "avb";
421 }; 530 };
422 531
423 pins_mdc { 532 pins_mdio {
424 groups = "avb_mdc"; 533 groups = "avb_mdio";
425 drive-strength = <24>; 534 drive-strength = <24>;
426 }; 535 };
427 536
@@ -581,10 +690,18 @@
581 <&audio_clk_c>, 690 <&audio_clk_c>,
582 <&cpg CPG_CORE CPG_AUDIO_CLK_I>; 691 <&cpg CPG_CORE CPG_AUDIO_CLK_I>;
583 692
584 rcar_sound,dai { 693 ports {
585 dai0 { 694 rsnd_port0: port@0 {
586 playback = <&ssi0 &src0 &dvc0>; 695 rsnd_endpoint0: endpoint {
587 capture = <&ssi1 &src1 &dvc1>; 696 remote-endpoint = <&ak4613_endpoint>;
697
698 dai-format = "left_j";
699 bitclock-master = <&rsnd_endpoint0>;
700 frame-master = <&rsnd_endpoint0>;
701
702 playback = <&ssi0 &src0 &dvc0>;
703 capture = <&ssi1 &src1 &dvc1>;
704 };
588 }; 705 };
589 }; 706 };
590}; 707};
@@ -689,6 +806,38 @@
689 clock-frequency = <100000000>; 806 clock-frequency = <100000000>;
690}; 807};
691 808
809&vin0 {
810 status = "okay";
811};
812
813&vin1 {
814 status = "okay";
815};
816
817&vin2 {
818 status = "okay";
819};
820
821&vin3 {
822 status = "okay";
823};
824
825&vin4 {
826 status = "okay";
827};
828
829&vin5 {
830 status = "okay";
831};
832
833&vin6 {
834 status = "okay";
835};
836
837&vin7 {
838 status = "okay";
839};
840
692&wdt0 { 841&wdt0 {
693 timeout-sec = <60>; 842 timeout-sec = <60>;
694 status = "okay"; 843 status = "okay";
diff --git a/arch/arm64/boot/dts/renesas/ulcb.dtsi b/arch/arm64/boot/dts/renesas/ulcb.dtsi
index 6f814845f8b6..0edb16e6b372 100644
--- a/arch/arm64/boot/dts/renesas/ulcb.dtsi
+++ b/arch/arm64/boot/dts/renesas/ulcb.dtsi
@@ -243,6 +243,32 @@
243 243
244&i2c_dvfs { 244&i2c_dvfs {
245 status = "okay"; 245 status = "okay";
246
247 pmic: pmic@30 {
248 pinctrl-0 = <&irq0_pins>;
249 pinctrl-names = "default";
250
251 compatible = "rohm,bd9571mwv";
252 reg = <0x30>;
253 interrupt-parent = <&intc_ex>;
254 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
255 interrupt-controller;
256 #interrupt-cells = <2>;
257 gpio-controller;
258 #gpio-cells = <2>;
259 rohm,ddr-backup-power = <0xf>;
260 rohm,rstbmode-pulse;
261
262 regulators {
263 dvfs: dvfs {
264 regulator-name = "dvfs";
265 regulator-min-microvolt = <750000>;
266 regulator-max-microvolt = <1030000>;
267 regulator-boot-on;
268 regulator-always-on;
269 };
270 };
271 };
246}; 272};
247 273
248&ohci1 { 274&ohci1 {
@@ -255,12 +281,12 @@
255 281
256 avb_pins: avb { 282 avb_pins: avb {
257 mux { 283 mux {
258 groups = "avb_link", "avb_mdc", "avb_mii"; 284 groups = "avb_link", "avb_mdio", "avb_mii";
259 function = "avb"; 285 function = "avb";
260 }; 286 };
261 287
262 pins_mdc { 288 pins_mdio {
263 groups = "avb_mdc"; 289 groups = "avb_mdio";
264 drive-strength = <24>; 290 drive-strength = <24>;
265 }; 291 };
266 292
@@ -276,6 +302,11 @@
276 function = "i2c2"; 302 function = "i2c2";
277 }; 303 };
278 304
305 irq0_pins: irq0 {
306 groups = "intc_ex_irq0";
307 function = "intc_ex";
308 };
309
279 scif2_pins: scif2 { 310 scif2_pins: scif2 {
280 groups = "scif2_data_a"; 311 groups = "scif2_data_a";
281 function = "scif2"; 312 function = "scif2";
diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c
index 5a7d693009ef..e778af766fae 100644
--- a/drivers/firmware/qcom_scm.c
+++ b/drivers/firmware/qcom_scm.c
@@ -603,6 +603,9 @@ static const struct of_device_id qcom_scm_dt_match[] = {
603 { .compatible = "qcom,scm-msm8996", 603 { .compatible = "qcom,scm-msm8996",
604 .data = NULL, /* no clocks */ 604 .data = NULL, /* no clocks */
605 }, 605 },
606 { .compatible = "qcom,scm-ipq4019",
607 .data = NULL, /* no clocks */
608 },
606 { .compatible = "qcom,scm", 609 { .compatible = "qcom,scm",
607 .data = (void *)(SCM_HAS_CORE_CLK 610 .data = (void *)(SCM_HAS_CORE_CLK
608 | SCM_HAS_IFACE_CLK 611 | SCM_HAS_IFACE_CLK
diff --git a/drivers/of/platform.c b/drivers/of/platform.c
index 0b49a62b38a3..59731a950c1f 100644
--- a/drivers/of/platform.c
+++ b/drivers/of/platform.c
@@ -505,6 +505,7 @@ EXPORT_SYMBOL_GPL(of_platform_default_populate);
505#ifndef CONFIG_PPC 505#ifndef CONFIG_PPC
506static const struct of_device_id reserved_mem_matches[] = { 506static const struct of_device_id reserved_mem_matches[] = {
507 { .compatible = "qcom,rmtfs-mem" }, 507 { .compatible = "qcom,rmtfs-mem" },
508 { .compatible = "qcom,cmd-db" },
508 { .compatible = "ramoops" }, 509 { .compatible = "ramoops" },
509 {} 510 {}
510}; 511};
diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
index 40523577bdaa..113e884697fd 100644
--- a/drivers/soc/Makefile
+++ b/drivers/soc/Makefile
@@ -14,7 +14,7 @@ obj-$(CONFIG_ARCH_MXC) += imx/
14obj-$(CONFIG_SOC_XWAY) += lantiq/ 14obj-$(CONFIG_SOC_XWAY) += lantiq/
15obj-y += mediatek/ 15obj-y += mediatek/
16obj-$(CONFIG_ARCH_MESON) += amlogic/ 16obj-$(CONFIG_ARCH_MESON) += amlogic/
17obj-$(CONFIG_ARCH_QCOM) += qcom/ 17obj-y += qcom/
18obj-y += renesas/ 18obj-y += renesas/
19obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ 19obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
20obj-$(CONFIG_SOC_SAMSUNG) += samsung/ 20obj-$(CONFIG_SOC_SAMSUNG) += samsung/
diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig
index d053f2634c67..9dc02f390ba3 100644
--- a/drivers/soc/qcom/Kconfig
+++ b/drivers/soc/qcom/Kconfig
@@ -3,6 +3,24 @@
3# 3#
4menu "Qualcomm SoC drivers" 4menu "Qualcomm SoC drivers"
5 5
6config QCOM_COMMAND_DB
7 bool "Qualcomm Command DB"
8 depends on (ARCH_QCOM && OF) || COMPILE_TEST
9 help
10 Command DB queries shared memory by key string for shared system
11 resources. Platform drivers that require to set state of a shared
12 resource on a RPM-hardened platform must use this database to get
13 SoC specific identifier and information for the shared resources.
14
15config QCOM_GENI_SE
16 tristate "QCOM GENI Serial Engine Driver"
17 depends on ARCH_QCOM || COMPILE_TEST
18 help
19 This driver is used to manage Generic Interface (GENI) firmware based
20 Qualcomm Technologies, Inc. Universal Peripheral (QUP) Wrapper. This
21 driver is also used to manage the common aspects of multiple Serial
22 Engines present in the QUP.
23
6config QCOM_GLINK_SSR 24config QCOM_GLINK_SSR
7 tristate "Qualcomm Glink SSR driver" 25 tristate "Qualcomm Glink SSR driver"
8 depends on RPMSG 26 depends on RPMSG
diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile
index 39de5dee55d9..19dcf957cb3a 100644
--- a/drivers/soc/qcom/Makefile
+++ b/drivers/soc/qcom/Makefile
@@ -1,4 +1,6 @@
1# SPDX-License-Identifier: GPL-2.0 1# SPDX-License-Identifier: GPL-2.0
2obj-$(CONFIG_QCOM_GENI_SE) += qcom-geni-se.o
3obj-$(CONFIG_QCOM_COMMAND_DB) += cmd-db.o
2obj-$(CONFIG_QCOM_GLINK_SSR) += glink_ssr.o 4obj-$(CONFIG_QCOM_GLINK_SSR) += glink_ssr.o
3obj-$(CONFIG_QCOM_GSBI) += qcom_gsbi.o 5obj-$(CONFIG_QCOM_GSBI) += qcom_gsbi.o
4obj-$(CONFIG_QCOM_MDT_LOADER) += mdt_loader.o 6obj-$(CONFIG_QCOM_MDT_LOADER) += mdt_loader.o
diff --git a/drivers/soc/qcom/cmd-db.c b/drivers/soc/qcom/cmd-db.c
new file mode 100644
index 000000000000..a6f646295f06
--- /dev/null
+++ b/drivers/soc/qcom/cmd-db.c
@@ -0,0 +1,317 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. */
3
4#include <linux/kernel.h>
5#include <linux/of.h>
6#include <linux/of_address.h>
7#include <linux/of_platform.h>
8#include <linux/of_reserved_mem.h>
9#include <linux/platform_device.h>
10#include <linux/types.h>
11
12#include <soc/qcom/cmd-db.h>
13
14#define NUM_PRIORITY 2
15#define MAX_SLV_ID 8
16#define SLAVE_ID_MASK 0x7
17#define SLAVE_ID_SHIFT 16
18
19/**
20 * struct entry_header: header for each entry in cmddb
21 *
22 * @id: resource's identifier
23 * @priority: unused
24 * @addr: the address of the resource
25 * @len: length of the data
26 * @offset: offset from :@data_offset, start of the data
27 */
28struct entry_header {
29 u8 id[8];
30 __le32 priority[NUM_PRIORITY];
31 __le32 addr;
32 __le16 len;
33 __le16 offset;
34};
35
36/**
37 * struct rsc_hdr: resource header information
38 *
39 * @slv_id: id for the resource
40 * @header_offset: entry's header at offset from the end of the cmd_db_header
41 * @data_offset: entry's data at offset from the end of the cmd_db_header
42 * @cnt: number of entries for HW type
43 * @version: MSB is major, LSB is minor
44 * @reserved: reserved for future use.
45 */
46struct rsc_hdr {
47 __le16 slv_id;
48 __le16 header_offset;
49 __le16 data_offset;
50 __le16 cnt;
51 __le16 version;
52 __le16 reserved[3];
53};
54
55/**
56 * struct cmd_db_header: The DB header information
57 *
58 * @version: The cmd db version
59 * @magic: constant expected in the database
60 * @header: array of resources
61 * @checksum: checksum for the header. Unused.
62 * @reserved: reserved memory
63 * @data: driver specific data
64 */
65struct cmd_db_header {
66 __le32 version;
67 u8 magic[4];
68 struct rsc_hdr header[MAX_SLV_ID];
69 __le32 checksum;
70 __le32 reserved;
71 u8 data[];
72};
73
74/**
75 * DOC: Description of the Command DB database.
76 *
77 * At the start of the command DB memory is the cmd_db_header structure.
78 * The cmd_db_header holds the version, checksum, magic key as well as an
79 * array for header for each slave (depicted by the rsc_header). Each h/w
80 * based accelerator is a 'slave' (shared resource) and has slave id indicating
81 * the type of accelerator. The rsc_header is the header for such individual
82 * slaves of a given type. The entries for each of these slaves begin at the
83 * rsc_hdr.header_offset. In addition each slave could have auxiliary data
84 * that may be needed by the driver. The data for the slave starts at the
85 * entry_header.offset to the location pointed to by the rsc_hdr.data_offset.
86 *
87 * Drivers have a stringified key to a slave/resource. They can query the slave
88 * information and get the slave id and the auxiliary data and the length of the
89 * data. Using this information, they can format the request to be sent to the
90 * h/w accelerator and request a resource state.
91 */
92
93static const u8 CMD_DB_MAGIC[] = { 0xdb, 0x30, 0x03, 0x0c };
94
95static bool cmd_db_magic_matches(const struct cmd_db_header *header)
96{
97 const u8 *magic = header->magic;
98
99 return memcmp(magic, CMD_DB_MAGIC, ARRAY_SIZE(CMD_DB_MAGIC)) == 0;
100}
101
102static struct cmd_db_header *cmd_db_header;
103
104
105static inline void *rsc_to_entry_header(struct rsc_hdr *hdr)
106{
107 u16 offset = le16_to_cpu(hdr->header_offset);
108
109 return cmd_db_header->data + offset;
110}
111
112static inline void *
113rsc_offset(struct rsc_hdr *hdr, struct entry_header *ent)
114{
115 u16 offset = le16_to_cpu(hdr->data_offset);
116 u16 loffset = le16_to_cpu(ent->offset);
117
118 return cmd_db_header->data + offset + loffset;
119}
120
121/**
122 * cmd_db_ready - Indicates if command DB is available
123 *
124 * Return: 0 on success, errno otherwise
125 */
126int cmd_db_ready(void)
127{
128 if (cmd_db_header == NULL)
129 return -EPROBE_DEFER;
130 else if (!cmd_db_magic_matches(cmd_db_header))
131 return -EINVAL;
132
133 return 0;
134}
135EXPORT_SYMBOL(cmd_db_ready);
136
137static int cmd_db_get_header(const char *id, struct entry_header *eh,
138 struct rsc_hdr *rh)
139{
140 struct rsc_hdr *rsc_hdr;
141 struct entry_header *ent;
142 int ret, i, j;
143 u8 query[8];
144
145 ret = cmd_db_ready();
146 if (ret)
147 return ret;
148
149 if (!eh || !rh)
150 return -EINVAL;
151
152 /* Pad out query string to same length as in DB */
153 strncpy(query, id, sizeof(query));
154
155 for (i = 0; i < MAX_SLV_ID; i++) {
156 rsc_hdr = &cmd_db_header->header[i];
157 if (!rsc_hdr->slv_id)
158 break;
159
160 ent = rsc_to_entry_header(rsc_hdr);
161 for (j = 0; j < le16_to_cpu(rsc_hdr->cnt); j++, ent++) {
162 if (memcmp(ent->id, query, sizeof(ent->id)) == 0)
163 break;
164 }
165
166 if (j < le16_to_cpu(rsc_hdr->cnt)) {
167 memcpy(eh, ent, sizeof(*ent));
168 memcpy(rh, rsc_hdr, sizeof(*rh));
169 return 0;
170 }
171 }
172
173 return -ENODEV;
174}
175
176/**
177 * cmd_db_read_addr() - Query command db for resource id address.
178 *
179 * @id: resource id to query for address
180 *
181 * Return: resource address on success, 0 on error
182 *
183 * This is used to retrieve resource address based on resource
184 * id.
185 */
186u32 cmd_db_read_addr(const char *id)
187{
188 int ret;
189 struct entry_header ent;
190 struct rsc_hdr rsc_hdr;
191
192 ret = cmd_db_get_header(id, &ent, &rsc_hdr);
193
194 return ret < 0 ? 0 : le32_to_cpu(ent.addr);
195}
196EXPORT_SYMBOL(cmd_db_read_addr);
197
198/**
199 * cmd_db_read_aux_data() - Query command db for aux data.
200 *
201 * @id: Resource to retrieve AUX Data on.
202 * @data: Data buffer to copy returned aux data to. Returns size on NULL
203 * @len: Caller provides size of data buffer passed in.
204 *
205 * Return: size of data on success, errno otherwise
206 */
207int cmd_db_read_aux_data(const char *id, u8 *data, size_t len)
208{
209 int ret;
210 struct entry_header ent;
211 struct rsc_hdr rsc_hdr;
212 u16 ent_len;
213
214 if (!data)
215 return -EINVAL;
216
217 ret = cmd_db_get_header(id, &ent, &rsc_hdr);
218 if (ret)
219 return ret;
220
221 ent_len = le16_to_cpu(ent.len);
222 if (len < ent_len)
223 return -EINVAL;
224
225 len = min_t(u16, ent_len, len);
226 memcpy(data, rsc_offset(&rsc_hdr, &ent), len);
227
228 return len;
229}
230EXPORT_SYMBOL(cmd_db_read_aux_data);
231
232/**
233 * cmd_db_read_aux_data_len - Get the length of the auxiliary data stored in DB.
234 *
235 * @id: Resource to retrieve AUX Data.
236 *
237 * Return: size on success, 0 on error
238 */
239size_t cmd_db_read_aux_data_len(const char *id)
240{
241 int ret;
242 struct entry_header ent;
243 struct rsc_hdr rsc_hdr;
244
245 ret = cmd_db_get_header(id, &ent, &rsc_hdr);
246
247 return ret < 0 ? 0 : le16_to_cpu(ent.len);
248}
249EXPORT_SYMBOL(cmd_db_read_aux_data_len);
250
251/**
252 * cmd_db_read_slave_id - Get the slave ID for a given resource address
253 *
254 * @id: Resource id to query the DB for version
255 *
256 * Return: cmd_db_hw_type enum on success, CMD_DB_HW_INVALID on error
257 */
258enum cmd_db_hw_type cmd_db_read_slave_id(const char *id)
259{
260 int ret;
261 struct entry_header ent;
262 struct rsc_hdr rsc_hdr;
263 u32 addr;
264
265 ret = cmd_db_get_header(id, &ent, &rsc_hdr);
266 if (ret < 0)
267 return CMD_DB_HW_INVALID;
268
269 addr = le32_to_cpu(ent.addr);
270 return (addr >> SLAVE_ID_SHIFT) & SLAVE_ID_MASK;
271}
272EXPORT_SYMBOL(cmd_db_read_slave_id);
273
274static int cmd_db_dev_probe(struct platform_device *pdev)
275{
276 struct reserved_mem *rmem;
277 int ret = 0;
278
279 rmem = of_reserved_mem_lookup(pdev->dev.of_node);
280 if (!rmem) {
281 dev_err(&pdev->dev, "failed to acquire memory region\n");
282 return -EINVAL;
283 }
284
285 cmd_db_header = memremap(rmem->base, rmem->size, MEMREMAP_WB);
286 if (IS_ERR_OR_NULL(cmd_db_header)) {
287 ret = PTR_ERR(cmd_db_header);
288 cmd_db_header = NULL;
289 return ret;
290 }
291
292 if (!cmd_db_magic_matches(cmd_db_header)) {
293 dev_err(&pdev->dev, "Invalid Command DB Magic\n");
294 return -EINVAL;
295 }
296
297 return 0;
298}
299
300static const struct of_device_id cmd_db_match_table[] = {
301 { .compatible = "qcom,cmd-db" },
302 { },
303};
304
305static struct platform_driver cmd_db_dev_driver = {
306 .probe = cmd_db_dev_probe,
307 .driver = {
308 .name = "cmd-db",
309 .of_match_table = cmd_db_match_table,
310 },
311};
312
313static int __init cmd_db_device_init(void)
314{
315 return platform_driver_register(&cmd_db_dev_driver);
316}
317arch_initcall(cmd_db_device_init);
diff --git a/drivers/soc/qcom/qcom-geni-se.c b/drivers/soc/qcom/qcom-geni-se.c
new file mode 100644
index 000000000000..feed3db21c10
--- /dev/null
+++ b/drivers/soc/qcom/qcom-geni-se.c
@@ -0,0 +1,748 @@
1// SPDX-License-Identifier: GPL-2.0
2// Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
3
4#include <linux/clk.h>
5#include <linux/slab.h>
6#include <linux/dma-mapping.h>
7#include <linux/io.h>
8#include <linux/module.h>
9#include <linux/of.h>
10#include <linux/of_platform.h>
11#include <linux/pinctrl/consumer.h>
12#include <linux/platform_device.h>
13#include <linux/qcom-geni-se.h>
14
15/**
16 * DOC: Overview
17 *
18 * Generic Interface (GENI) Serial Engine (SE) Wrapper driver is introduced
19 * to manage GENI firmware based Qualcomm Universal Peripheral (QUP) Wrapper
20 * controller. QUP Wrapper is designed to support various serial bus protocols
21 * like UART, SPI, I2C, I3C, etc.
22 */
23
24/**
25 * DOC: Hardware description
26 *
27 * GENI based QUP is a highly-flexible and programmable module for supporting
28 * a wide range of serial interfaces like UART, SPI, I2C, I3C, etc. A single
29 * QUP module can provide upto 8 serial interfaces, using its internal
30 * serial engines. The actual configuration is determined by the target
31 * platform configuration. The protocol supported by each interface is
32 * determined by the firmware loaded to the serial engine. Each SE consists
33 * of a DMA Engine and GENI sub modules which enable serial engines to
34 * support FIFO and DMA modes of operation.
35 *
36 *
37 * +-----------------------------------------+
38 * |QUP Wrapper |
39 * | +----------------------------+ |
40 * --QUP & SE Clocks--> | Serial Engine N | +-IO------>
41 * | | ... | | Interface
42 * <---Clock Perf.----+ +----+-----------------------+ | |
43 * State Interface | | Serial Engine 1 | | |
44 * | | | | |
45 * | | | | |
46 * <--------AHB-------> | | | |
47 * | | +----+ |
48 * | | | |
49 * | | | |
50 * <------SE IRQ------+ +----------------------------+ |
51 * | |
52 * +-----------------------------------------+
53 *
54 * Figure 1: GENI based QUP Wrapper
55 *
56 * The GENI submodules include primary and secondary sequencers which are
57 * used to drive TX & RX operations. On serial interfaces that operate using
58 * master-slave model, primary sequencer drives both TX & RX operations. On
59 * serial interfaces that operate using peer-to-peer model, primary sequencer
60 * drives TX operation and secondary sequencer drives RX operation.
61 */
62
63/**
64 * DOC: Software description
65 *
66 * GENI SE Wrapper driver is structured into 2 parts:
67 *
68 * geni_wrapper represents QUP Wrapper controller. This part of the driver
69 * manages QUP Wrapper information such as hardware version, clock
70 * performance table that is common to all the internal serial engines.
71 *
72 * geni_se represents serial engine. This part of the driver manages serial
73 * engine information such as clocks, containing QUP Wrapper, etc. This part
74 * of driver also supports operations (eg. initialize the concerned serial
75 * engine, select between FIFO and DMA mode of operation etc.) that are
76 * common to all the serial engines and are independent of serial interfaces.
77 */
78
79#define MAX_CLK_PERF_LEVEL 32
80#define NUM_AHB_CLKS 2
81
82/**
83 * @struct geni_wrapper - Data structure to represent the QUP Wrapper Core
84 * @dev: Device pointer of the QUP wrapper core
85 * @base: Base address of this instance of QUP wrapper core
86 * @ahb_clks: Handle to the primary & secondary AHB clocks
87 */
88struct geni_wrapper {
89 struct device *dev;
90 void __iomem *base;
91 struct clk_bulk_data ahb_clks[NUM_AHB_CLKS];
92};
93
94#define QUP_HW_VER_REG 0x4
95
96/* Common SE registers */
97#define GENI_INIT_CFG_REVISION 0x0
98#define GENI_S_INIT_CFG_REVISION 0x4
99#define GENI_OUTPUT_CTRL 0x24
100#define GENI_CGC_CTRL 0x28
101#define GENI_CLK_CTRL_RO 0x60
102#define GENI_IF_DISABLE_RO 0x64
103#define GENI_FW_S_REVISION_RO 0x6c
104#define SE_GENI_BYTE_GRAN 0x254
105#define SE_GENI_TX_PACKING_CFG0 0x260
106#define SE_GENI_TX_PACKING_CFG1 0x264
107#define SE_GENI_RX_PACKING_CFG0 0x284
108#define SE_GENI_RX_PACKING_CFG1 0x288
109#define SE_GENI_M_GP_LENGTH 0x910
110#define SE_GENI_S_GP_LENGTH 0x914
111#define SE_DMA_TX_PTR_L 0xc30
112#define SE_DMA_TX_PTR_H 0xc34
113#define SE_DMA_TX_ATTR 0xc38
114#define SE_DMA_TX_LEN 0xc3c
115#define SE_DMA_TX_IRQ_EN 0xc48
116#define SE_DMA_TX_IRQ_EN_SET 0xc4c
117#define SE_DMA_TX_IRQ_EN_CLR 0xc50
118#define SE_DMA_TX_LEN_IN 0xc54
119#define SE_DMA_TX_MAX_BURST 0xc5c
120#define SE_DMA_RX_PTR_L 0xd30
121#define SE_DMA_RX_PTR_H 0xd34
122#define SE_DMA_RX_ATTR 0xd38
123#define SE_DMA_RX_LEN 0xd3c
124#define SE_DMA_RX_IRQ_EN 0xd48
125#define SE_DMA_RX_IRQ_EN_SET 0xd4c
126#define SE_DMA_RX_IRQ_EN_CLR 0xd50
127#define SE_DMA_RX_LEN_IN 0xd54
128#define SE_DMA_RX_MAX_BURST 0xd5c
129#define SE_DMA_RX_FLUSH 0xd60
130#define SE_GSI_EVENT_EN 0xe18
131#define SE_IRQ_EN 0xe1c
132#define SE_DMA_GENERAL_CFG 0xe30
133
134/* GENI_OUTPUT_CTRL fields */
135#define DEFAULT_IO_OUTPUT_CTRL_MSK GENMASK(6, 0)
136
137/* GENI_CGC_CTRL fields */
138#define CFG_AHB_CLK_CGC_ON BIT(0)
139#define CFG_AHB_WR_ACLK_CGC_ON BIT(1)
140#define DATA_AHB_CLK_CGC_ON BIT(2)
141#define SCLK_CGC_ON BIT(3)
142#define TX_CLK_CGC_ON BIT(4)
143#define RX_CLK_CGC_ON BIT(5)
144#define EXT_CLK_CGC_ON BIT(6)
145#define PROG_RAM_HCLK_OFF BIT(8)
146#define PROG_RAM_SCLK_OFF BIT(9)
147#define DEFAULT_CGC_EN GENMASK(6, 0)
148
149/* SE_GSI_EVENT_EN fields */
150#define DMA_RX_EVENT_EN BIT(0)
151#define DMA_TX_EVENT_EN BIT(1)
152#define GENI_M_EVENT_EN BIT(2)
153#define GENI_S_EVENT_EN BIT(3)
154
155/* SE_IRQ_EN fields */
156#define DMA_RX_IRQ_EN BIT(0)
157#define DMA_TX_IRQ_EN BIT(1)
158#define GENI_M_IRQ_EN BIT(2)
159#define GENI_S_IRQ_EN BIT(3)
160
161/* SE_DMA_GENERAL_CFG */
162#define DMA_RX_CLK_CGC_ON BIT(0)
163#define DMA_TX_CLK_CGC_ON BIT(1)
164#define DMA_AHB_SLV_CFG_ON BIT(2)
165#define AHB_SEC_SLV_CLK_CGC_ON BIT(3)
166#define DUMMY_RX_NON_BUFFERABLE BIT(4)
167#define RX_DMA_ZERO_PADDING_EN BIT(5)
168#define RX_DMA_IRQ_DELAY_MSK GENMASK(8, 6)
169#define RX_DMA_IRQ_DELAY_SHFT 6
170
171/**
172 * geni_se_get_qup_hw_version() - Read the QUP wrapper Hardware version
173 * @se: Pointer to the corresponding serial engine.
174 *
175 * Return: Hardware Version of the wrapper.
176 */
177u32 geni_se_get_qup_hw_version(struct geni_se *se)
178{
179 struct geni_wrapper *wrapper = se->wrapper;
180
181 return readl_relaxed(wrapper->base + QUP_HW_VER_REG);
182}
183EXPORT_SYMBOL(geni_se_get_qup_hw_version);
184
185static void geni_se_io_set_mode(void __iomem *base)
186{
187 u32 val;
188
189 val = readl_relaxed(base + SE_IRQ_EN);
190 val |= GENI_M_IRQ_EN | GENI_S_IRQ_EN;
191 val |= DMA_TX_IRQ_EN | DMA_RX_IRQ_EN;
192 writel_relaxed(val, base + SE_IRQ_EN);
193
194 val = readl_relaxed(base + SE_GENI_DMA_MODE_EN);
195 val &= ~GENI_DMA_MODE_EN;
196 writel_relaxed(val, base + SE_GENI_DMA_MODE_EN);
197
198 writel_relaxed(0, base + SE_GSI_EVENT_EN);
199}
200
201static void geni_se_io_init(void __iomem *base)
202{
203 u32 val;
204
205 val = readl_relaxed(base + GENI_CGC_CTRL);
206 val |= DEFAULT_CGC_EN;
207 writel_relaxed(val, base + GENI_CGC_CTRL);
208
209 val = readl_relaxed(base + SE_DMA_GENERAL_CFG);
210 val |= AHB_SEC_SLV_CLK_CGC_ON | DMA_AHB_SLV_CFG_ON;
211 val |= DMA_TX_CLK_CGC_ON | DMA_RX_CLK_CGC_ON;
212 writel_relaxed(val, base + SE_DMA_GENERAL_CFG);
213
214 writel_relaxed(DEFAULT_IO_OUTPUT_CTRL_MSK, base + GENI_OUTPUT_CTRL);
215 writel_relaxed(FORCE_DEFAULT, base + GENI_FORCE_DEFAULT_REG);
216}
217
218/**
219 * geni_se_init() - Initialize the GENI serial engine
220 * @se: Pointer to the concerned serial engine.
221 * @rx_wm: Receive watermark, in units of FIFO words.
222 * @rx_rfr_wm: Ready-for-receive watermark, in units of FIFO words.
223 *
224 * This function is used to initialize the GENI serial engine, configure
225 * receive watermark and ready-for-receive watermarks.
226 */
227void geni_se_init(struct geni_se *se, u32 rx_wm, u32 rx_rfr)
228{
229 u32 val;
230
231 geni_se_io_init(se->base);
232 geni_se_io_set_mode(se->base);
233
234 writel_relaxed(rx_wm, se->base + SE_GENI_RX_WATERMARK_REG);
235 writel_relaxed(rx_rfr, se->base + SE_GENI_RX_RFR_WATERMARK_REG);
236
237 val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN);
238 val |= M_COMMON_GENI_M_IRQ_EN;
239 writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN);
240
241 val = readl_relaxed(se->base + SE_GENI_S_IRQ_EN);
242 val |= S_COMMON_GENI_S_IRQ_EN;
243 writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN);
244}
245EXPORT_SYMBOL(geni_se_init);
246
247static void geni_se_select_fifo_mode(struct geni_se *se)
248{
249 u32 proto = geni_se_read_proto(se);
250 u32 val;
251
252 writel_relaxed(0, se->base + SE_GSI_EVENT_EN);
253 writel_relaxed(0xffffffff, se->base + SE_GENI_M_IRQ_CLEAR);
254 writel_relaxed(0xffffffff, se->base + SE_GENI_S_IRQ_CLEAR);
255 writel_relaxed(0xffffffff, se->base + SE_DMA_TX_IRQ_CLR);
256 writel_relaxed(0xffffffff, se->base + SE_DMA_RX_IRQ_CLR);
257 writel_relaxed(0xffffffff, se->base + SE_IRQ_EN);
258
259 val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN);
260 if (proto != GENI_SE_UART) {
261 val |= M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN;
262 val |= M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN;
263 }
264 writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN);
265
266 val = readl_relaxed(se->base + SE_GENI_S_IRQ_EN);
267 if (proto != GENI_SE_UART)
268 val |= S_CMD_DONE_EN;
269 writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN);
270
271 val = readl_relaxed(se->base + SE_GENI_DMA_MODE_EN);
272 val &= ~GENI_DMA_MODE_EN;
273 writel_relaxed(val, se->base + SE_GENI_DMA_MODE_EN);
274}
275
276static void geni_se_select_dma_mode(struct geni_se *se)
277{
278 u32 val;
279
280 writel_relaxed(0, se->base + SE_GSI_EVENT_EN);
281 writel_relaxed(0xffffffff, se->base + SE_GENI_M_IRQ_CLEAR);
282 writel_relaxed(0xffffffff, se->base + SE_GENI_S_IRQ_CLEAR);
283 writel_relaxed(0xffffffff, se->base + SE_DMA_TX_IRQ_CLR);
284 writel_relaxed(0xffffffff, se->base + SE_DMA_RX_IRQ_CLR);
285 writel_relaxed(0xffffffff, se->base + SE_IRQ_EN);
286
287 val = readl_relaxed(se->base + SE_GENI_DMA_MODE_EN);
288 val |= GENI_DMA_MODE_EN;
289 writel_relaxed(val, se->base + SE_GENI_DMA_MODE_EN);
290}
291
292/**
293 * geni_se_select_mode() - Select the serial engine transfer mode
294 * @se: Pointer to the concerned serial engine.
295 * @mode: Transfer mode to be selected.
296 */
297void geni_se_select_mode(struct geni_se *se, enum geni_se_xfer_mode mode)
298{
299 WARN_ON(mode != GENI_SE_FIFO && mode != GENI_SE_DMA);
300
301 switch (mode) {
302 case GENI_SE_FIFO:
303 geni_se_select_fifo_mode(se);
304 break;
305 case GENI_SE_DMA:
306 geni_se_select_dma_mode(se);
307 break;
308 case GENI_SE_INVALID:
309 default:
310 break;
311 }
312}
313EXPORT_SYMBOL(geni_se_select_mode);
314
315/**
316 * DOC: Overview
317 *
318 * GENI FIFO packing is highly configurable. TX/RX packing/unpacking consist
319 * of up to 4 operations, each operation represented by 4 configuration vectors
320 * of 10 bits programmed in GENI_TX_PACKING_CFG0 and GENI_TX_PACKING_CFG1 for
321 * TX FIFO and in GENI_RX_PACKING_CFG0 and GENI_RX_PACKING_CFG1 for RX FIFO.
322 * Refer to below examples for detailed bit-field description.
323 *
324 * Example 1: word_size = 7, packing_mode = 4 x 8, msb_to_lsb = 1
325 *
326 * +-----------+-------+-------+-------+-------+
327 * | | vec_0 | vec_1 | vec_2 | vec_3 |
328 * +-----------+-------+-------+-------+-------+
329 * | start | 0x6 | 0xe | 0x16 | 0x1e |
330 * | direction | 1 | 1 | 1 | 1 |
331 * | length | 6 | 6 | 6 | 6 |
332 * | stop | 0 | 0 | 0 | 1 |
333 * +-----------+-------+-------+-------+-------+
334 *
335 * Example 2: word_size = 15, packing_mode = 2 x 16, msb_to_lsb = 0
336 *
337 * +-----------+-------+-------+-------+-------+
338 * | | vec_0 | vec_1 | vec_2 | vec_3 |
339 * +-----------+-------+-------+-------+-------+
340 * | start | 0x0 | 0x8 | 0x10 | 0x18 |
341 * | direction | 0 | 0 | 0 | 0 |
342 * | length | 7 | 6 | 7 | 6 |
343 * | stop | 0 | 0 | 0 | 1 |
344 * +-----------+-------+-------+-------+-------+
345 *
346 * Example 3: word_size = 23, packing_mode = 1 x 32, msb_to_lsb = 1
347 *
348 * +-----------+-------+-------+-------+-------+
349 * | | vec_0 | vec_1 | vec_2 | vec_3 |
350 * +-----------+-------+-------+-------+-------+
351 * | start | 0x16 | 0xe | 0x6 | 0x0 |
352 * | direction | 1 | 1 | 1 | 1 |
353 * | length | 7 | 7 | 6 | 0 |
354 * | stop | 0 | 0 | 1 | 0 |
355 * +-----------+-------+-------+-------+-------+
356 *
357 */
358
359#define NUM_PACKING_VECTORS 4
360#define PACKING_START_SHIFT 5
361#define PACKING_DIR_SHIFT 4
362#define PACKING_LEN_SHIFT 1
363#define PACKING_STOP_BIT BIT(0)
364#define PACKING_VECTOR_SHIFT 10
365/**
366 * geni_se_config_packing() - Packing configuration of the serial engine
367 * @se: Pointer to the concerned serial engine
368 * @bpw: Bits of data per transfer word.
369 * @pack_words: Number of words per fifo element.
370 * @msb_to_lsb: Transfer from MSB to LSB or vice-versa.
371 * @tx_cfg: Flag to configure the TX Packing.
372 * @rx_cfg: Flag to configure the RX Packing.
373 *
374 * This function is used to configure the packing rules for the current
375 * transfer.
376 */
377void geni_se_config_packing(struct geni_se *se, int bpw, int pack_words,
378 bool msb_to_lsb, bool tx_cfg, bool rx_cfg)
379{
380 u32 cfg0, cfg1, cfg[NUM_PACKING_VECTORS] = {0};
381 int len;
382 int temp_bpw = bpw;
383 int idx_start = msb_to_lsb ? bpw - 1 : 0;
384 int idx = idx_start;
385 int idx_delta = msb_to_lsb ? -BITS_PER_BYTE : BITS_PER_BYTE;
386 int ceil_bpw = ALIGN(bpw, BITS_PER_BYTE);
387 int iter = (ceil_bpw * pack_words) / BITS_PER_BYTE;
388 int i;
389
390 if (iter <= 0 || iter > NUM_PACKING_VECTORS)
391 return;
392
393 for (i = 0; i < iter; i++) {
394 len = min_t(int, temp_bpw, BITS_PER_BYTE) - 1;
395 cfg[i] = idx << PACKING_START_SHIFT;
396 cfg[i] |= msb_to_lsb << PACKING_DIR_SHIFT;
397 cfg[i] |= len << PACKING_LEN_SHIFT;
398
399 if (temp_bpw <= BITS_PER_BYTE) {
400 idx = ((i + 1) * BITS_PER_BYTE) + idx_start;
401 temp_bpw = bpw;
402 } else {
403 idx = idx + idx_delta;
404 temp_bpw = temp_bpw - BITS_PER_BYTE;
405 }
406 }
407 cfg[iter - 1] |= PACKING_STOP_BIT;
408 cfg0 = cfg[0] | (cfg[1] << PACKING_VECTOR_SHIFT);
409 cfg1 = cfg[2] | (cfg[3] << PACKING_VECTOR_SHIFT);
410
411 if (tx_cfg) {
412 writel_relaxed(cfg0, se->base + SE_GENI_TX_PACKING_CFG0);
413 writel_relaxed(cfg1, se->base + SE_GENI_TX_PACKING_CFG1);
414 }
415 if (rx_cfg) {
416 writel_relaxed(cfg0, se->base + SE_GENI_RX_PACKING_CFG0);
417 writel_relaxed(cfg1, se->base + SE_GENI_RX_PACKING_CFG1);
418 }
419
420 /*
421 * Number of protocol words in each FIFO entry
422 * 0 - 4x8, four words in each entry, max word size of 8 bits
423 * 1 - 2x16, two words in each entry, max word size of 16 bits
424 * 2 - 1x32, one word in each entry, max word size of 32 bits
425 * 3 - undefined
426 */
427 if (pack_words || bpw == 32)
428 writel_relaxed(bpw / 16, se->base + SE_GENI_BYTE_GRAN);
429}
430EXPORT_SYMBOL(geni_se_config_packing);
431
432static void geni_se_clks_off(struct geni_se *se)
433{
434 struct geni_wrapper *wrapper = se->wrapper;
435
436 clk_disable_unprepare(se->clk);
437 clk_bulk_disable_unprepare(ARRAY_SIZE(wrapper->ahb_clks),
438 wrapper->ahb_clks);
439}
440
441/**
442 * geni_se_resources_off() - Turn off resources associated with the serial
443 * engine
444 * @se: Pointer to the concerned serial engine.
445 *
446 * Return: 0 on success, standard Linux error codes on failure/error.
447 */
448int geni_se_resources_off(struct geni_se *se)
449{
450 int ret;
451
452 ret = pinctrl_pm_select_sleep_state(se->dev);
453 if (ret)
454 return ret;
455
456 geni_se_clks_off(se);
457 return 0;
458}
459EXPORT_SYMBOL(geni_se_resources_off);
460
461static int geni_se_clks_on(struct geni_se *se)
462{
463 int ret;
464 struct geni_wrapper *wrapper = se->wrapper;
465
466 ret = clk_bulk_prepare_enable(ARRAY_SIZE(wrapper->ahb_clks),
467 wrapper->ahb_clks);
468 if (ret)
469 return ret;
470
471 ret = clk_prepare_enable(se->clk);
472 if (ret)
473 clk_bulk_disable_unprepare(ARRAY_SIZE(wrapper->ahb_clks),
474 wrapper->ahb_clks);
475 return ret;
476}
477
478/**
479 * geni_se_resources_on() - Turn on resources associated with the serial
480 * engine
481 * @se: Pointer to the concerned serial engine.
482 *
483 * Return: 0 on success, standard Linux error codes on failure/error.
484 */
485int geni_se_resources_on(struct geni_se *se)
486{
487 int ret;
488
489 ret = geni_se_clks_on(se);
490 if (ret)
491 return ret;
492
493 ret = pinctrl_pm_select_default_state(se->dev);
494 if (ret)
495 geni_se_clks_off(se);
496
497 return ret;
498}
499EXPORT_SYMBOL(geni_se_resources_on);
500
501/**
502 * geni_se_clk_tbl_get() - Get the clock table to program DFS
503 * @se: Pointer to the concerned serial engine.
504 * @tbl: Table in which the output is returned.
505 *
506 * This function is called by the protocol drivers to determine the different
507 * clock frequencies supported by serial engine core clock. The protocol
508 * drivers use the output to determine the clock frequency index to be
509 * programmed into DFS.
510 *
511 * Return: number of valid performance levels in the table on success,
512 * standard Linux error codes on failure.
513 */
514int geni_se_clk_tbl_get(struct geni_se *se, unsigned long **tbl)
515{
516 unsigned long freq = 0;
517 int i;
518
519 if (se->clk_perf_tbl) {
520 *tbl = se->clk_perf_tbl;
521 return se->num_clk_levels;
522 }
523
524 se->clk_perf_tbl = devm_kcalloc(se->dev, MAX_CLK_PERF_LEVEL,
525 sizeof(*se->clk_perf_tbl),
526 GFP_KERNEL);
527 if (!se->clk_perf_tbl)
528 return -ENOMEM;
529
530 for (i = 0; i < MAX_CLK_PERF_LEVEL; i++) {
531 freq = clk_round_rate(se->clk, freq + 1);
532 if (!freq || freq == se->clk_perf_tbl[i - 1])
533 break;
534 se->clk_perf_tbl[i] = freq;
535 }
536 se->num_clk_levels = i;
537 *tbl = se->clk_perf_tbl;
538 return se->num_clk_levels;
539}
540EXPORT_SYMBOL(geni_se_clk_tbl_get);
541
542/**
543 * geni_se_clk_freq_match() - Get the matching or closest SE clock frequency
544 * @se: Pointer to the concerned serial engine.
545 * @req_freq: Requested clock frequency.
546 * @index: Index of the resultant frequency in the table.
547 * @res_freq: Resultant frequency which matches or is closer to the
548 * requested frequency.
549 * @exact: Flag to indicate exact multiple requirement of the requested
550 * frequency.
551 *
552 * This function is called by the protocol drivers to determine the matching
553 * or exact multiple of the requested frequency, as provided by the serial
554 * engine clock in order to meet the performance requirements. If there is
555 * no matching or exact multiple of the requested frequency found, then it
556 * selects the closest floor frequency, if exact flag is not set.
557 *
558 * Return: 0 on success, standard Linux error codes on failure.
559 */
560int geni_se_clk_freq_match(struct geni_se *se, unsigned long req_freq,
561 unsigned int *index, unsigned long *res_freq,
562 bool exact)
563{
564 unsigned long *tbl;
565 int num_clk_levels;
566 int i;
567
568 num_clk_levels = geni_se_clk_tbl_get(se, &tbl);
569 if (num_clk_levels < 0)
570 return num_clk_levels;
571
572 if (num_clk_levels == 0)
573 return -EINVAL;
574
575 *res_freq = 0;
576 for (i = 0; i < num_clk_levels; i++) {
577 if (!(tbl[i] % req_freq)) {
578 *index = i;
579 *res_freq = tbl[i];
580 return 0;
581 }
582
583 if (!(*res_freq) || ((tbl[i] > *res_freq) &&
584 (tbl[i] < req_freq))) {
585 *index = i;
586 *res_freq = tbl[i];
587 }
588 }
589
590 if (exact)
591 return -EINVAL;
592
593 return 0;
594}
595EXPORT_SYMBOL(geni_se_clk_freq_match);
596
597#define GENI_SE_DMA_DONE_EN BIT(0)
598#define GENI_SE_DMA_EOT_EN BIT(1)
599#define GENI_SE_DMA_AHB_ERR_EN BIT(2)
600#define GENI_SE_DMA_EOT_BUF BIT(0)
601/**
602 * geni_se_tx_dma_prep() - Prepare the serial engine for TX DMA transfer
603 * @se: Pointer to the concerned serial engine.
604 * @buf: Pointer to the TX buffer.
605 * @len: Length of the TX buffer.
606 * @iova: Pointer to store the mapped DMA address.
607 *
608 * This function is used to prepare the buffers for DMA TX.
609 *
610 * Return: 0 on success, standard Linux error codes on failure.
611 */
612int geni_se_tx_dma_prep(struct geni_se *se, void *buf, size_t len,
613 dma_addr_t *iova)
614{
615 struct geni_wrapper *wrapper = se->wrapper;
616 u32 val;
617
618 *iova = dma_map_single(wrapper->dev, buf, len, DMA_TO_DEVICE);
619 if (dma_mapping_error(wrapper->dev, *iova))
620 return -EIO;
621
622 val = GENI_SE_DMA_DONE_EN;
623 val |= GENI_SE_DMA_EOT_EN;
624 val |= GENI_SE_DMA_AHB_ERR_EN;
625 writel_relaxed(val, se->base + SE_DMA_TX_IRQ_EN_SET);
626 writel_relaxed(lower_32_bits(*iova), se->base + SE_DMA_TX_PTR_L);
627 writel_relaxed(upper_32_bits(*iova), se->base + SE_DMA_TX_PTR_H);
628 writel_relaxed(GENI_SE_DMA_EOT_BUF, se->base + SE_DMA_TX_ATTR);
629 writel_relaxed(len, se->base + SE_DMA_TX_LEN);
630 return 0;
631}
632EXPORT_SYMBOL(geni_se_tx_dma_prep);
633
634/**
635 * geni_se_rx_dma_prep() - Prepare the serial engine for RX DMA transfer
636 * @se: Pointer to the concerned serial engine.
637 * @buf: Pointer to the RX buffer.
638 * @len: Length of the RX buffer.
639 * @iova: Pointer to store the mapped DMA address.
640 *
641 * This function is used to prepare the buffers for DMA RX.
642 *
643 * Return: 0 on success, standard Linux error codes on failure.
644 */
645int geni_se_rx_dma_prep(struct geni_se *se, void *buf, size_t len,
646 dma_addr_t *iova)
647{
648 struct geni_wrapper *wrapper = se->wrapper;
649 u32 val;
650
651 *iova = dma_map_single(wrapper->dev, buf, len, DMA_FROM_DEVICE);
652 if (dma_mapping_error(wrapper->dev, *iova))
653 return -EIO;
654
655 val = GENI_SE_DMA_DONE_EN;
656 val |= GENI_SE_DMA_EOT_EN;
657 val |= GENI_SE_DMA_AHB_ERR_EN;
658 writel_relaxed(val, se->base + SE_DMA_RX_IRQ_EN_SET);
659 writel_relaxed(lower_32_bits(*iova), se->base + SE_DMA_RX_PTR_L);
660 writel_relaxed(upper_32_bits(*iova), se->base + SE_DMA_RX_PTR_H);
661 /* RX does not have EOT buffer type bit. So just reset RX_ATTR */
662 writel_relaxed(0, se->base + SE_DMA_RX_ATTR);
663 writel_relaxed(len, se->base + SE_DMA_RX_LEN);
664 return 0;
665}
666EXPORT_SYMBOL(geni_se_rx_dma_prep);
667
668/**
669 * geni_se_tx_dma_unprep() - Unprepare the serial engine after TX DMA transfer
670 * @se: Pointer to the concerned serial engine.
671 * @iova: DMA address of the TX buffer.
672 * @len: Length of the TX buffer.
673 *
674 * This function is used to unprepare the DMA buffers after DMA TX.
675 */
676void geni_se_tx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len)
677{
678 struct geni_wrapper *wrapper = se->wrapper;
679
680 if (iova && !dma_mapping_error(wrapper->dev, iova))
681 dma_unmap_single(wrapper->dev, iova, len, DMA_TO_DEVICE);
682}
683EXPORT_SYMBOL(geni_se_tx_dma_unprep);
684
685/**
686 * geni_se_rx_dma_unprep() - Unprepare the serial engine after RX DMA transfer
687 * @se: Pointer to the concerned serial engine.
688 * @iova: DMA address of the RX buffer.
689 * @len: Length of the RX buffer.
690 *
691 * This function is used to unprepare the DMA buffers after DMA RX.
692 */
693void geni_se_rx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len)
694{
695 struct geni_wrapper *wrapper = se->wrapper;
696
697 if (iova && !dma_mapping_error(wrapper->dev, iova))
698 dma_unmap_single(wrapper->dev, iova, len, DMA_FROM_DEVICE);
699}
700EXPORT_SYMBOL(geni_se_rx_dma_unprep);
701
702static int geni_se_probe(struct platform_device *pdev)
703{
704 struct device *dev = &pdev->dev;
705 struct resource *res;
706 struct geni_wrapper *wrapper;
707 int ret;
708
709 wrapper = devm_kzalloc(dev, sizeof(*wrapper), GFP_KERNEL);
710 if (!wrapper)
711 return -ENOMEM;
712
713 wrapper->dev = dev;
714 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
715 wrapper->base = devm_ioremap_resource(dev, res);
716 if (IS_ERR(wrapper->base))
717 return PTR_ERR(wrapper->base);
718
719 wrapper->ahb_clks[0].id = "m-ahb";
720 wrapper->ahb_clks[1].id = "s-ahb";
721 ret = devm_clk_bulk_get(dev, NUM_AHB_CLKS, wrapper->ahb_clks);
722 if (ret) {
723 dev_err(dev, "Err getting AHB clks %d\n", ret);
724 return ret;
725 }
726
727 dev_set_drvdata(dev, wrapper);
728 dev_dbg(dev, "GENI SE Driver probed\n");
729 return devm_of_platform_populate(dev);
730}
731
732static const struct of_device_id geni_se_dt_match[] = {
733 { .compatible = "qcom,geni-se-qup", },
734 {}
735};
736MODULE_DEVICE_TABLE(of, geni_se_dt_match);
737
738static struct platform_driver geni_se_driver = {
739 .driver = {
740 .name = "geni_se_qup",
741 .of_match_table = geni_se_dt_match,
742 },
743 .probe = geni_se_probe,
744};
745module_platform_driver(geni_se_driver);
746
747MODULE_DESCRIPTION("GENI Serial Engine Driver");
748MODULE_LICENSE("GPL v2");
diff --git a/drivers/soc/qcom/qmi_interface.c b/drivers/soc/qcom/qmi_interface.c
index 321982277697..938ca41c56cd 100644
--- a/drivers/soc/qcom/qmi_interface.c
+++ b/drivers/soc/qcom/qmi_interface.c
@@ -639,10 +639,11 @@ int qmi_handle_init(struct qmi_handle *qmi, size_t recv_buf_size,
639 if (ops) 639 if (ops)
640 qmi->ops = *ops; 640 qmi->ops = *ops;
641 641
642 /* Make room for the header */
643 recv_buf_size += sizeof(struct qmi_header);
644 /* Must also be sufficient to hold a control packet */
642 if (recv_buf_size < sizeof(struct qrtr_ctrl_pkt)) 645 if (recv_buf_size < sizeof(struct qrtr_ctrl_pkt))
643 recv_buf_size = sizeof(struct qrtr_ctrl_pkt); 646 recv_buf_size = sizeof(struct qrtr_ctrl_pkt);
644 else
645 recv_buf_size += sizeof(struct qmi_header);
646 647
647 qmi->recv_buf_size = recv_buf_size; 648 qmi->recv_buf_size = recv_buf_size;
648 qmi->recv_buf = kzalloc(recv_buf_size, GFP_KERNEL); 649 qmi->recv_buf = kzalloc(recv_buf_size, GFP_KERNEL);
diff --git a/drivers/soc/qcom/smd-rpm.c b/drivers/soc/qcom/smd-rpm.c
index c2346752b3ea..93517ed83355 100644
--- a/drivers/soc/qcom/smd-rpm.c
+++ b/drivers/soc/qcom/smd-rpm.c
@@ -226,6 +226,7 @@ static const struct of_device_id qcom_smd_rpm_of_match[] = {
226 { .compatible = "qcom,rpm-msm8916" }, 226 { .compatible = "qcom,rpm-msm8916" },
227 { .compatible = "qcom,rpm-msm8974" }, 227 { .compatible = "qcom,rpm-msm8974" },
228 { .compatible = "qcom,rpm-msm8996" }, 228 { .compatible = "qcom,rpm-msm8996" },
229 { .compatible = "qcom,rpm-msm8998" },
229 {} 230 {}
230}; 231};
231MODULE_DEVICE_TABLE(of, qcom_smd_rpm_of_match); 232MODULE_DEVICE_TABLE(of, qcom_smd_rpm_of_match);
diff --git a/drivers/soc/qcom/smem.c b/drivers/soc/qcom/smem.c
index 0b94d62fad2b..70b2ee80d6bd 100644
--- a/drivers/soc/qcom/smem.c
+++ b/drivers/soc/qcom/smem.c
@@ -280,7 +280,7 @@ struct qcom_smem {
280 struct smem_region regions[0]; 280 struct smem_region regions[0];
281}; 281};
282 282
283static struct smem_private_entry * 283static void *
284phdr_to_last_uncached_entry(struct smem_partition_header *phdr) 284phdr_to_last_uncached_entry(struct smem_partition_header *phdr)
285{ 285{
286 void *p = phdr; 286 void *p = phdr;
@@ -288,15 +288,18 @@ phdr_to_last_uncached_entry(struct smem_partition_header *phdr)
288 return p + le32_to_cpu(phdr->offset_free_uncached); 288 return p + le32_to_cpu(phdr->offset_free_uncached);
289} 289}
290 290
291static void *phdr_to_first_cached_entry(struct smem_partition_header *phdr, 291static struct smem_private_entry *
292phdr_to_first_cached_entry(struct smem_partition_header *phdr,
292 size_t cacheline) 293 size_t cacheline)
293{ 294{
294 void *p = phdr; 295 void *p = phdr;
296 struct smem_private_entry *e;
295 297
296 return p + le32_to_cpu(phdr->size) - ALIGN(sizeof(*phdr), cacheline); 298 return p + le32_to_cpu(phdr->size) - ALIGN(sizeof(*e), cacheline);
297} 299}
298 300
299static void *phdr_to_last_cached_entry(struct smem_partition_header *phdr) 301static void *
302phdr_to_last_cached_entry(struct smem_partition_header *phdr)
300{ 303{
301 void *p = phdr; 304 void *p = phdr;
302 305
@@ -361,14 +364,14 @@ static int qcom_smem_alloc_private(struct qcom_smem *smem,
361 end = phdr_to_last_uncached_entry(phdr); 364 end = phdr_to_last_uncached_entry(phdr);
362 cached = phdr_to_last_cached_entry(phdr); 365 cached = phdr_to_last_cached_entry(phdr);
363 366
364 while (hdr < end) { 367 if (smem->global_partition) {
365 if (hdr->canary != SMEM_PRIVATE_CANARY) { 368 dev_err(smem->dev, "Already found the global partition\n");
366 dev_err(smem->dev, 369 return -EINVAL;
367 "Found invalid canary in hosts %d:%d partition\n", 370 }
368 phdr->host0, phdr->host1);
369 return -EINVAL;
370 }
371 371
372 while (hdr < end) {
373 if (hdr->canary != SMEM_PRIVATE_CANARY)
374 goto bad_canary;
372 if (le16_to_cpu(hdr->item) == item) 375 if (le16_to_cpu(hdr->item) == item)
373 return -EEXIST; 376 return -EEXIST;
374 377
@@ -377,7 +380,7 @@ static int qcom_smem_alloc_private(struct qcom_smem *smem,
377 380
378 /* Check that we don't grow into the cached region */ 381 /* Check that we don't grow into the cached region */
379 alloc_size = sizeof(*hdr) + ALIGN(size, 8); 382 alloc_size = sizeof(*hdr) + ALIGN(size, 8);
380 if ((void *)hdr + alloc_size >= cached) { 383 if ((void *)hdr + alloc_size > cached) {
381 dev_err(smem->dev, "Out of memory\n"); 384 dev_err(smem->dev, "Out of memory\n");
382 return -ENOSPC; 385 return -ENOSPC;
383 } 386 }
@@ -397,6 +400,11 @@ static int qcom_smem_alloc_private(struct qcom_smem *smem,
397 le32_add_cpu(&phdr->offset_free_uncached, alloc_size); 400 le32_add_cpu(&phdr->offset_free_uncached, alloc_size);
398 401
399 return 0; 402 return 0;
403bad_canary:
404 dev_err(smem->dev, "Found invalid canary in hosts %hu:%hu partition\n",
405 le16_to_cpu(phdr->host0), le16_to_cpu(phdr->host1));
406
407 return -EINVAL;
400} 408}
401 409
402static int qcom_smem_alloc_global(struct qcom_smem *smem, 410static int qcom_smem_alloc_global(struct qcom_smem *smem,
@@ -560,8 +568,8 @@ static void *qcom_smem_get_private(struct qcom_smem *smem,
560 return ERR_PTR(-ENOENT); 568 return ERR_PTR(-ENOENT);
561 569
562invalid_canary: 570invalid_canary:
563 dev_err(smem->dev, "Found invalid canary in hosts %d:%d partition\n", 571 dev_err(smem->dev, "Found invalid canary in hosts %hu:%hu partition\n",
564 phdr->host0, phdr->host1); 572 le16_to_cpu(phdr->host0), le16_to_cpu(phdr->host1));
565 573
566 return ERR_PTR(-EINVAL); 574 return ERR_PTR(-EINVAL);
567} 575}
@@ -647,6 +655,33 @@ int qcom_smem_get_free_space(unsigned host)
647} 655}
648EXPORT_SYMBOL(qcom_smem_get_free_space); 656EXPORT_SYMBOL(qcom_smem_get_free_space);
649 657
658/**
659 * qcom_smem_virt_to_phys() - return the physical address associated
660 * with an smem item pointer (previously returned by qcom_smem_get()
661 * @p: the virtual address to convert
662 *
663 * Returns 0 if the pointer provided is not within any smem region.
664 */
665phys_addr_t qcom_smem_virt_to_phys(void *p)
666{
667 unsigned i;
668
669 for (i = 0; i < __smem->num_regions; i++) {
670 struct smem_region *region = &__smem->regions[i];
671
672 if (p < region->virt_base)
673 continue;
674 if (p < region->virt_base + region->size) {
675 u64 offset = p - region->virt_base;
676
677 return (phys_addr_t)region->aux_base + offset;
678 }
679 }
680
681 return 0;
682}
683EXPORT_SYMBOL(qcom_smem_virt_to_phys);
684
650static int qcom_smem_get_sbl_version(struct qcom_smem *smem) 685static int qcom_smem_get_sbl_version(struct qcom_smem *smem)
651{ 686{
652 struct smem_header *header; 687 struct smem_header *header;
@@ -695,9 +730,10 @@ static u32 qcom_smem_get_item_count(struct qcom_smem *smem)
695static int qcom_smem_set_global_partition(struct qcom_smem *smem) 730static int qcom_smem_set_global_partition(struct qcom_smem *smem)
696{ 731{
697 struct smem_partition_header *header; 732 struct smem_partition_header *header;
698 struct smem_ptable_entry *entry = NULL; 733 struct smem_ptable_entry *entry;
699 struct smem_ptable *ptable; 734 struct smem_ptable *ptable;
700 u32 host0, host1, size; 735 u32 host0, host1, size;
736 bool found = false;
701 int i; 737 int i;
702 738
703 ptable = qcom_smem_get_ptable(smem); 739 ptable = qcom_smem_get_ptable(smem);
@@ -709,11 +745,13 @@ static int qcom_smem_set_global_partition(struct qcom_smem *smem)
709 host0 = le16_to_cpu(entry->host0); 745 host0 = le16_to_cpu(entry->host0);
710 host1 = le16_to_cpu(entry->host1); 746 host1 = le16_to_cpu(entry->host1);
711 747
712 if (host0 == SMEM_GLOBAL_HOST && host0 == host1) 748 if (host0 == SMEM_GLOBAL_HOST && host0 == host1) {
749 found = true;
713 break; 750 break;
751 }
714 } 752 }
715 753
716 if (!entry) { 754 if (!found) {
717 dev_err(smem->dev, "Missing entry for global partition\n"); 755 dev_err(smem->dev, "Missing entry for global partition\n");
718 return -EINVAL; 756 return -EINVAL;
719 } 757 }
@@ -723,11 +761,6 @@ static int qcom_smem_set_global_partition(struct qcom_smem *smem)
723 return -EINVAL; 761 return -EINVAL;
724 } 762 }
725 763
726 if (smem->global_partition) {
727 dev_err(smem->dev, "Already found the global partition\n");
728 return -EINVAL;
729 }
730
731 header = smem->regions[0].virt_base + le32_to_cpu(entry->offset); 764 header = smem->regions[0].virt_base + le32_to_cpu(entry->offset);
732 host0 = le16_to_cpu(header->host0); 765 host0 = le16_to_cpu(header->host0);
733 host1 = le16_to_cpu(header->host1); 766 host1 = le16_to_cpu(header->host1);
diff --git a/include/linux/qcom-geni-se.h b/include/linux/qcom-geni-se.h
new file mode 100644
index 000000000000..5d6144977828
--- /dev/null
+++ b/include/linux/qcom-geni-se.h
@@ -0,0 +1,425 @@
1/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2/*
3 * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
4 */
5
6#ifndef _LINUX_QCOM_GENI_SE
7#define _LINUX_QCOM_GENI_SE
8
9/* Transfer mode supported by GENI Serial Engines */
10enum geni_se_xfer_mode {
11 GENI_SE_INVALID,
12 GENI_SE_FIFO,
13 GENI_SE_DMA,
14};
15
16/* Protocols supported by GENI Serial Engines */
17enum geni_se_protocol_type {
18 GENI_SE_NONE,
19 GENI_SE_SPI,
20 GENI_SE_UART,
21 GENI_SE_I2C,
22 GENI_SE_I3C,
23};
24
25struct geni_wrapper;
26struct clk;
27
28/**
29 * struct geni_se - GENI Serial Engine
30 * @base: Base Address of the Serial Engine's register block
31 * @dev: Pointer to the Serial Engine device
32 * @wrapper: Pointer to the parent QUP Wrapper core
33 * @clk: Handle to the core serial engine clock
34 * @num_clk_levels: Number of valid clock levels in clk_perf_tbl
35 * @clk_perf_tbl: Table of clock frequency input to serial engine clock
36 */
37struct geni_se {
38 void __iomem *base;
39 struct device *dev;
40 struct geni_wrapper *wrapper;
41 struct clk *clk;
42 unsigned int num_clk_levels;
43 unsigned long *clk_perf_tbl;
44};
45
46/* Common SE registers */
47#define GENI_FORCE_DEFAULT_REG 0x20
48#define SE_GENI_STATUS 0x40
49#define GENI_SER_M_CLK_CFG 0x48
50#define GENI_SER_S_CLK_CFG 0x4c
51#define GENI_FW_REVISION_RO 0x68
52#define SE_GENI_CLK_SEL 0x7c
53#define SE_GENI_DMA_MODE_EN 0x258
54#define SE_GENI_M_CMD0 0x600
55#define SE_GENI_M_CMD_CTRL_REG 0x604
56#define SE_GENI_M_IRQ_STATUS 0x610
57#define SE_GENI_M_IRQ_EN 0x614
58#define SE_GENI_M_IRQ_CLEAR 0x618
59#define SE_GENI_S_CMD0 0x630
60#define SE_GENI_S_CMD_CTRL_REG 0x634
61#define SE_GENI_S_IRQ_STATUS 0x640
62#define SE_GENI_S_IRQ_EN 0x644
63#define SE_GENI_S_IRQ_CLEAR 0x648
64#define SE_GENI_TX_FIFOn 0x700
65#define SE_GENI_RX_FIFOn 0x780
66#define SE_GENI_TX_FIFO_STATUS 0x800
67#define SE_GENI_RX_FIFO_STATUS 0x804
68#define SE_GENI_TX_WATERMARK_REG 0x80c
69#define SE_GENI_RX_WATERMARK_REG 0x810
70#define SE_GENI_RX_RFR_WATERMARK_REG 0x814
71#define SE_GENI_IOS 0x908
72#define SE_DMA_TX_IRQ_STAT 0xc40
73#define SE_DMA_TX_IRQ_CLR 0xc44
74#define SE_DMA_TX_FSM_RST 0xc58
75#define SE_DMA_RX_IRQ_STAT 0xd40
76#define SE_DMA_RX_IRQ_CLR 0xd44
77#define SE_DMA_RX_FSM_RST 0xd58
78#define SE_HW_PARAM_0 0xe24
79#define SE_HW_PARAM_1 0xe28
80
81/* GENI_FORCE_DEFAULT_REG fields */
82#define FORCE_DEFAULT BIT(0)
83
84/* GENI_STATUS fields */
85#define M_GENI_CMD_ACTIVE BIT(0)
86#define S_GENI_CMD_ACTIVE BIT(12)
87
88/* GENI_SER_M_CLK_CFG/GENI_SER_S_CLK_CFG */
89#define SER_CLK_EN BIT(0)
90#define CLK_DIV_MSK GENMASK(15, 4)
91#define CLK_DIV_SHFT 4
92
93/* GENI_FW_REVISION_RO fields */
94#define FW_REV_PROTOCOL_MSK GENMASK(15, 8)
95#define FW_REV_PROTOCOL_SHFT 8
96
97/* GENI_CLK_SEL fields */
98#define CLK_SEL_MSK GENMASK(2, 0)
99
100/* SE_GENI_DMA_MODE_EN */
101#define GENI_DMA_MODE_EN BIT(0)
102
103/* GENI_M_CMD0 fields */
104#define M_OPCODE_MSK GENMASK(31, 27)
105#define M_OPCODE_SHFT 27
106#define M_PARAMS_MSK GENMASK(26, 0)
107
108/* GENI_M_CMD_CTRL_REG */
109#define M_GENI_CMD_CANCEL BIT(2)
110#define M_GENI_CMD_ABORT BIT(1)
111#define M_GENI_DISABLE BIT(0)
112
113/* GENI_S_CMD0 fields */
114#define S_OPCODE_MSK GENMASK(31, 27)
115#define S_OPCODE_SHFT 27
116#define S_PARAMS_MSK GENMASK(26, 0)
117
118/* GENI_S_CMD_CTRL_REG */
119#define S_GENI_CMD_CANCEL BIT(2)
120#define S_GENI_CMD_ABORT BIT(1)
121#define S_GENI_DISABLE BIT(0)
122
123/* GENI_M_IRQ_EN fields */
124#define M_CMD_DONE_EN BIT(0)
125#define M_CMD_OVERRUN_EN BIT(1)
126#define M_ILLEGAL_CMD_EN BIT(2)
127#define M_CMD_FAILURE_EN BIT(3)
128#define M_CMD_CANCEL_EN BIT(4)
129#define M_CMD_ABORT_EN BIT(5)
130#define M_TIMESTAMP_EN BIT(6)
131#define M_RX_IRQ_EN BIT(7)
132#define M_GP_SYNC_IRQ_0_EN BIT(8)
133#define M_GP_IRQ_0_EN BIT(9)
134#define M_GP_IRQ_1_EN BIT(10)
135#define M_GP_IRQ_2_EN BIT(11)
136#define M_GP_IRQ_3_EN BIT(12)
137#define M_GP_IRQ_4_EN BIT(13)
138#define M_GP_IRQ_5_EN BIT(14)
139#define M_IO_DATA_DEASSERT_EN BIT(22)
140#define M_IO_DATA_ASSERT_EN BIT(23)
141#define M_RX_FIFO_RD_ERR_EN BIT(24)
142#define M_RX_FIFO_WR_ERR_EN BIT(25)
143#define M_RX_FIFO_WATERMARK_EN BIT(26)
144#define M_RX_FIFO_LAST_EN BIT(27)
145#define M_TX_FIFO_RD_ERR_EN BIT(28)
146#define M_TX_FIFO_WR_ERR_EN BIT(29)
147#define M_TX_FIFO_WATERMARK_EN BIT(30)
148#define M_SEC_IRQ_EN BIT(31)
149#define M_COMMON_GENI_M_IRQ_EN (GENMASK(6, 1) | \
150 M_IO_DATA_DEASSERT_EN | \
151 M_IO_DATA_ASSERT_EN | M_RX_FIFO_RD_ERR_EN | \
152 M_RX_FIFO_WR_ERR_EN | M_TX_FIFO_RD_ERR_EN | \
153 M_TX_FIFO_WR_ERR_EN)
154
155/* GENI_S_IRQ_EN fields */
156#define S_CMD_DONE_EN BIT(0)
157#define S_CMD_OVERRUN_EN BIT(1)
158#define S_ILLEGAL_CMD_EN BIT(2)
159#define S_CMD_FAILURE_EN BIT(3)
160#define S_CMD_CANCEL_EN BIT(4)
161#define S_CMD_ABORT_EN BIT(5)
162#define S_GP_SYNC_IRQ_0_EN BIT(8)
163#define S_GP_IRQ_0_EN BIT(9)
164#define S_GP_IRQ_1_EN BIT(10)
165#define S_GP_IRQ_2_EN BIT(11)
166#define S_GP_IRQ_3_EN BIT(12)
167#define S_GP_IRQ_4_EN BIT(13)
168#define S_GP_IRQ_5_EN BIT(14)
169#define S_IO_DATA_DEASSERT_EN BIT(22)
170#define S_IO_DATA_ASSERT_EN BIT(23)
171#define S_RX_FIFO_RD_ERR_EN BIT(24)
172#define S_RX_FIFO_WR_ERR_EN BIT(25)
173#define S_RX_FIFO_WATERMARK_EN BIT(26)
174#define S_RX_FIFO_LAST_EN BIT(27)
175#define S_COMMON_GENI_S_IRQ_EN (GENMASK(5, 1) | GENMASK(13, 9) | \
176 S_RX_FIFO_RD_ERR_EN | S_RX_FIFO_WR_ERR_EN)
177
178/* GENI_/TX/RX/RX_RFR/_WATERMARK_REG fields */
179#define WATERMARK_MSK GENMASK(5, 0)
180
181/* GENI_TX_FIFO_STATUS fields */
182#define TX_FIFO_WC GENMASK(27, 0)
183
184/* GENI_RX_FIFO_STATUS fields */
185#define RX_LAST BIT(31)
186#define RX_LAST_BYTE_VALID_MSK GENMASK(30, 28)
187#define RX_LAST_BYTE_VALID_SHFT 28
188#define RX_FIFO_WC_MSK GENMASK(24, 0)
189
190/* SE_GENI_IOS fields */
191#define IO2_DATA_IN BIT(1)
192#define RX_DATA_IN BIT(0)
193
194/* SE_DMA_TX_IRQ_STAT Register fields */
195#define TX_DMA_DONE BIT(0)
196#define TX_EOT BIT(1)
197#define TX_SBE BIT(2)
198#define TX_RESET_DONE BIT(3)
199
200/* SE_DMA_RX_IRQ_STAT Register fields */
201#define RX_DMA_DONE BIT(0)
202#define RX_EOT BIT(1)
203#define RX_SBE BIT(2)
204#define RX_RESET_DONE BIT(3)
205#define RX_FLUSH_DONE BIT(4)
206#define RX_GENI_GP_IRQ GENMASK(10, 5)
207#define RX_GENI_CANCEL_IRQ BIT(11)
208#define RX_GENI_GP_IRQ_EXT GENMASK(13, 12)
209
210/* SE_HW_PARAM_0 fields */
211#define TX_FIFO_WIDTH_MSK GENMASK(29, 24)
212#define TX_FIFO_WIDTH_SHFT 24
213#define TX_FIFO_DEPTH_MSK GENMASK(21, 16)
214#define TX_FIFO_DEPTH_SHFT 16
215
216/* SE_HW_PARAM_1 fields */
217#define RX_FIFO_WIDTH_MSK GENMASK(29, 24)
218#define RX_FIFO_WIDTH_SHFT 24
219#define RX_FIFO_DEPTH_MSK GENMASK(21, 16)
220#define RX_FIFO_DEPTH_SHFT 16
221
222#define HW_VER_MAJOR_MASK GENMASK(31, 28)
223#define HW_VER_MAJOR_SHFT 28
224#define HW_VER_MINOR_MASK GENMASK(27, 16)
225#define HW_VER_MINOR_SHFT 16
226#define HW_VER_STEP_MASK GENMASK(15, 0)
227
228#if IS_ENABLED(CONFIG_QCOM_GENI_SE)
229
230u32 geni_se_get_qup_hw_version(struct geni_se *se);
231
232#define geni_se_get_wrapper_version(se, major, minor, step) do { \
233 u32 ver; \
234\
235 ver = geni_se_get_qup_hw_version(se); \
236 major = (ver & HW_VER_MAJOR_MASK) >> HW_VER_MAJOR_SHFT; \
237 minor = (ver & HW_VER_MINOR_MASK) >> HW_VER_MINOR_SHFT; \
238 step = version & HW_VER_STEP_MASK; \
239} while (0)
240
241/**
242 * geni_se_read_proto() - Read the protocol configured for a serial engine
243 * @se: Pointer to the concerned serial engine.
244 *
245 * Return: Protocol value as configured in the serial engine.
246 */
247static inline u32 geni_se_read_proto(struct geni_se *se)
248{
249 u32 val;
250
251 val = readl_relaxed(se->base + GENI_FW_REVISION_RO);
252
253 return (val & FW_REV_PROTOCOL_MSK) >> FW_REV_PROTOCOL_SHFT;
254}
255
256/**
257 * geni_se_setup_m_cmd() - Setup the primary sequencer
258 * @se: Pointer to the concerned serial engine.
259 * @cmd: Command/Operation to setup in the primary sequencer.
260 * @params: Parameter for the sequencer command.
261 *
262 * This function is used to configure the primary sequencer with the
263 * command and its associated parameters.
264 */
265static inline void geni_se_setup_m_cmd(struct geni_se *se, u32 cmd, u32 params)
266{
267 u32 m_cmd;
268
269 m_cmd = (cmd << M_OPCODE_SHFT) | (params & M_PARAMS_MSK);
270 writel_relaxed(m_cmd, se->base + SE_GENI_M_CMD0);
271}
272
273/**
274 * geni_se_setup_s_cmd() - Setup the secondary sequencer
275 * @se: Pointer to the concerned serial engine.
276 * @cmd: Command/Operation to setup in the secondary sequencer.
277 * @params: Parameter for the sequencer command.
278 *
279 * This function is used to configure the secondary sequencer with the
280 * command and its associated parameters.
281 */
282static inline void geni_se_setup_s_cmd(struct geni_se *se, u32 cmd, u32 params)
283{
284 u32 s_cmd;
285
286 s_cmd = readl_relaxed(se->base + SE_GENI_S_CMD0);
287 s_cmd &= ~(S_OPCODE_MSK | S_PARAMS_MSK);
288 s_cmd |= (cmd << S_OPCODE_SHFT);
289 s_cmd |= (params & S_PARAMS_MSK);
290 writel_relaxed(s_cmd, se->base + SE_GENI_S_CMD0);
291}
292
293/**
294 * geni_se_cancel_m_cmd() - Cancel the command configured in the primary
295 * sequencer
296 * @se: Pointer to the concerned serial engine.
297 *
298 * This function is used to cancel the currently configured command in the
299 * primary sequencer.
300 */
301static inline void geni_se_cancel_m_cmd(struct geni_se *se)
302{
303 writel_relaxed(M_GENI_CMD_CANCEL, se->base + SE_GENI_M_CMD_CTRL_REG);
304}
305
306/**
307 * geni_se_cancel_s_cmd() - Cancel the command configured in the secondary
308 * sequencer
309 * @se: Pointer to the concerned serial engine.
310 *
311 * This function is used to cancel the currently configured command in the
312 * secondary sequencer.
313 */
314static inline void geni_se_cancel_s_cmd(struct geni_se *se)
315{
316 writel_relaxed(S_GENI_CMD_CANCEL, se->base + SE_GENI_S_CMD_CTRL_REG);
317}
318
319/**
320 * geni_se_abort_m_cmd() - Abort the command configured in the primary sequencer
321 * @se: Pointer to the concerned serial engine.
322 *
323 * This function is used to force abort the currently configured command in the
324 * primary sequencer.
325 */
326static inline void geni_se_abort_m_cmd(struct geni_se *se)
327{
328 writel_relaxed(M_GENI_CMD_ABORT, se->base + SE_GENI_M_CMD_CTRL_REG);
329}
330
331/**
332 * geni_se_abort_s_cmd() - Abort the command configured in the secondary
333 * sequencer
334 * @se: Pointer to the concerned serial engine.
335 *
336 * This function is used to force abort the currently configured command in the
337 * secondary sequencer.
338 */
339static inline void geni_se_abort_s_cmd(struct geni_se *se)
340{
341 writel_relaxed(S_GENI_CMD_ABORT, se->base + SE_GENI_S_CMD_CTRL_REG);
342}
343
344/**
345 * geni_se_get_tx_fifo_depth() - Get the TX fifo depth of the serial engine
346 * @se: Pointer to the concerned serial engine.
347 *
348 * This function is used to get the depth i.e. number of elements in the
349 * TX fifo of the serial engine.
350 *
351 * Return: TX fifo depth in units of FIFO words.
352 */
353static inline u32 geni_se_get_tx_fifo_depth(struct geni_se *se)
354{
355 u32 val;
356
357 val = readl_relaxed(se->base + SE_HW_PARAM_0);
358
359 return (val & TX_FIFO_DEPTH_MSK) >> TX_FIFO_DEPTH_SHFT;
360}
361
362/**
363 * geni_se_get_tx_fifo_width() - Get the TX fifo width of the serial engine
364 * @se: Pointer to the concerned serial engine.
365 *
366 * This function is used to get the width i.e. word size per element in the
367 * TX fifo of the serial engine.
368 *
369 * Return: TX fifo width in bits
370 */
371static inline u32 geni_se_get_tx_fifo_width(struct geni_se *se)
372{
373 u32 val;
374
375 val = readl_relaxed(se->base + SE_HW_PARAM_0);
376
377 return (val & TX_FIFO_WIDTH_MSK) >> TX_FIFO_WIDTH_SHFT;
378}
379
380/**
381 * geni_se_get_rx_fifo_depth() - Get the RX fifo depth of the serial engine
382 * @se: Pointer to the concerned serial engine.
383 *
384 * This function is used to get the depth i.e. number of elements in the
385 * RX fifo of the serial engine.
386 *
387 * Return: RX fifo depth in units of FIFO words
388 */
389static inline u32 geni_se_get_rx_fifo_depth(struct geni_se *se)
390{
391 u32 val;
392
393 val = readl_relaxed(se->base + SE_HW_PARAM_1);
394
395 return (val & RX_FIFO_DEPTH_MSK) >> RX_FIFO_DEPTH_SHFT;
396}
397
398void geni_se_init(struct geni_se *se, u32 rx_wm, u32 rx_rfr);
399
400void geni_se_select_mode(struct geni_se *se, enum geni_se_xfer_mode mode);
401
402void geni_se_config_packing(struct geni_se *se, int bpw, int pack_words,
403 bool msb_to_lsb, bool tx_cfg, bool rx_cfg);
404
405int geni_se_resources_off(struct geni_se *se);
406
407int geni_se_resources_on(struct geni_se *se);
408
409int geni_se_clk_tbl_get(struct geni_se *se, unsigned long **tbl);
410
411int geni_se_clk_freq_match(struct geni_se *se, unsigned long req_freq,
412 unsigned int *index, unsigned long *res_freq,
413 bool exact);
414
415int geni_se_tx_dma_prep(struct geni_se *se, void *buf, size_t len,
416 dma_addr_t *iova);
417
418int geni_se_rx_dma_prep(struct geni_se *se, void *buf, size_t len,
419 dma_addr_t *iova);
420
421void geni_se_tx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len);
422
423void geni_se_rx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len);
424#endif
425#endif
diff --git a/include/linux/soc/qcom/smem.h b/include/linux/soc/qcom/smem.h
index c1657ed27b30..86e1b358688a 100644
--- a/include/linux/soc/qcom/smem.h
+++ b/include/linux/soc/qcom/smem.h
@@ -9,4 +9,6 @@ void *qcom_smem_get(unsigned host, unsigned item, size_t *size);
9 9
10int qcom_smem_get_free_space(unsigned host); 10int qcom_smem_get_free_space(unsigned host);
11 11
12phys_addr_t qcom_smem_virt_to_phys(void *p);
13
12#endif 14#endif
diff --git a/include/soc/qcom/cmd-db.h b/include/soc/qcom/cmd-db.h
new file mode 100644
index 000000000000..578180cbc134
--- /dev/null
+++ b/include/soc/qcom/cmd-db.h
@@ -0,0 +1,45 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. */
3
4#ifndef __QCOM_COMMAND_DB_H__
5#define __QCOM_COMMAND_DB_H__
6
7
8enum cmd_db_hw_type {
9 CMD_DB_HW_INVALID = 0,
10 CMD_DB_HW_MIN = 3,
11 CMD_DB_HW_ARC = CMD_DB_HW_MIN,
12 CMD_DB_HW_VRM = 4,
13 CMD_DB_HW_BCM = 5,
14 CMD_DB_HW_MAX = CMD_DB_HW_BCM,
15 CMD_DB_HW_ALL = 0xff,
16};
17
18#if IS_ENABLED(CONFIG_QCOM_COMMAND_DB)
19u32 cmd_db_read_addr(const char *resource_id);
20
21int cmd_db_read_aux_data(const char *resource_id, u8 *data, size_t len);
22
23size_t cmd_db_read_aux_data_len(const char *resource_id);
24
25enum cmd_db_hw_type cmd_db_read_slave_id(const char *resource_id);
26
27int cmd_db_ready(void);
28#else
29static inline u32 cmd_db_read_addr(const char *resource_id)
30{ return 0; }
31
32static inline int cmd_db_read_aux_data(const char *resource_id, u8 *data,
33 size_t len)
34{ return -ENODEV; }
35
36static inline size_t cmd_db_read_aux_data_len(const char *resource_id)
37{ return -ENODEV; }
38
39static inline enum cmd_db_hw_type cmd_db_read_slave_id(const char *resource_id)
40{ return -ENODEV; }
41
42static inline int cmd_db_ready(void)
43{ return -ENODEV; }
44#endif /* CONFIG_QCOM_COMMAND_DB */
45#endif /* __QCOM_COMMAND_DB_H__ */
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-24 22:37:58 -0400