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authorOlof Johansson <olof@lixom.net>2018-06-02 04:32:38 -0400
committerOlof Johansson <olof@lixom.net>2018-06-02 04:32:38 -0400
commit14321604c82c5415a72e894b83b587a345f5bdf2 (patch)
treee98889b4c2e3ee96a0f6fd9fe57e9e1774925b0e
parent171d429a1df9ea9deeab24bd623f14c8006da466 (diff)
parent7fad92d05887319998b8d2bb40082b8b224d5ef5 (diff)
Merge tag 'renesas-dt-for-v4.18' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/late
Renesas ARM Based SoC DT Updates for v4.18 * R-Mobile A1 (r8a7740) SoC - Describe CEU, IRQC, SYS-DMAC and USB devices - Cleanup for consistency with other Renesas SoCs and enhanced maintainability * RZ/A1H (r7s72100) SoC - Describe CEU device * R-Car Gen2, RZ/G1 and RZ/A1H SoCs - Add PMU device nodes * RZ/A1H (r7s72100) SoC - Correct interrupt types * R-Mobile APE6 (r8a73a4) APE4EVM board and SH-Mobile AG5 (sh73a0) SoC - Use generic disable-wp instead of now deprecated toshiba,mmc-wrprotect-disable property * EMMA Mobile EV2 (emev2) and SH-Mobile AG5 (sh73a0) SoCs - Add missing interrupt-affinity to PMU * R-Car H2 (r8a7790) and R-Mobile APE6 (r8a73a4) SoCs - Correct mask for GIC PPI interrupts * R-Car H2 (r8a7790), M2-W (r8a7791), M2-N (r8a7793) and E2 (r8a7794) SoCs - Describe FDP1 instances * R-Car Gen2 and RZ/G1 SoCs - Describe watchdog devices - For R-Car Gen2 this involves updating the SMP routine side as it is changed by a driver updated to allow watchdog device support * Alt board for R-Car E2 (r8a7794) SoC * RBoards for -Car Gen2 SoCs and kzm9d board for EMMA Mobile EV2 (emev2) SoC * iW-RainboW-G23S board for RZ/G1C (r8a77470) SoC - Initial SoC and board support - Enable EtherAVB - Describe all SCIF devices * Boards for R-Car Gen2 SoCs - Enable watchdog support * Wheat board for V2H (r8a7792) SoC - Correct ADV7513 address usage * tag 'renesas-dt-for-v4.18' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (69 commits) ARM: dts: r8a7740: Add CEU1 ARM: dts: r8a7740: Add CEU0 ARM: dts: r8a7745: Add PMU device node ARM: dts: r8a7743: Add PMU device node ARM: dts: r8a7794: Add PMU device node ARM: dts: r8a7793: Add PMU device node ARM: dts: r8a7792: Add PMU device node ARM: dts: r8a7791: Add PMU device node ARM: dts: r8a7790: Add PMU device nodes ARM: dts: r7s72100: Add PMU device node ARM: dts: r7s72100: Correct RTC interrupt types ARM: dts: r7s72100: Correct watchdog timer interrupt type ARM: dts: emev2: Add missing interrupt-affinity to PMU node ARM: dts: sh73a0: Add missing interrupt-affinity to PMU node ARM: dts: r8a73a4: Correct mask for GIC PPI interrupts ARM: dts: r8a7790: Correct mask for GIC PPI interrupts ARM: shmobile: r8a7794: alt: add EEPROM to DTS ARM: dts: kzm9d: Drop unnecessary address properties from gpio_keys node ARM: dts: silk: Drop unnecessary address properties from vin port node ARM: dts: alt: Drop unnecessary address properties from vin port node ... Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat
-rw-r--r--arch/arm/boot/dts/Makefile1
-rw-r--r--arch/arm/boot/dts/emev2-kzm9d.dts3
-rw-r--r--arch/arm/boot/dts/emev2.dtsi5
-rw-r--r--arch/arm/boot/dts/r7s72100.dtsi1038
-rw-r--r--arch/arm/boot/dts/r8a73a4-ape6evm.dts4
-rw-r--r--arch/arm/boot/dts/r8a73a4.dtsi10
-rw-r--r--arch/arm/boot/dts/r8a7740.dtsi18
-rw-r--r--arch/arm/boot/dts/r8a7743-iwg20m.dtsi5
-rw-r--r--arch/arm/boot/dts/r8a7743.dtsi19
-rw-r--r--arch/arm/boot/dts/r8a7745-iwg22m.dtsi5
-rw-r--r--arch/arm/boot/dts/r8a7745.dtsi19
-rw-r--r--arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts48
-rw-r--r--arch/arm/boot/dts/r8a77470.dtsi336
-rw-r--r--arch/arm/boot/dts/r8a7790-lager.dts8
-rw-r--r--arch/arm/boot/dts/r8a7790.dtsi67
-rw-r--r--arch/arm/boot/dts/r8a7791-koelsch.dts11
-rw-r--r--arch/arm/boot/dts/r8a7791-porter.dts8
-rw-r--r--arch/arm/boot/dts/r8a7791.dtsi37
-rw-r--r--arch/arm/boot/dts/r8a7792-blanche.dts5
-rw-r--r--arch/arm/boot/dts/r8a7792-wheat.dts16
-rw-r--r--arch/arm/boot/dts/r8a7792.dtsi19
-rw-r--r--arch/arm/boot/dts/r8a7793-gose.dts11
-rw-r--r--arch/arm/boot/dts/r8a7793.dtsi37
-rw-r--r--arch/arm/boot/dts/r8a7794-alt.dts14
-rw-r--r--arch/arm/boot/dts/r8a7794-silk.dts8
-rw-r--r--arch/arm/boot/dts/r8a7794.dtsi28
-rw-r--r--arch/arm/boot/dts/sh73a0.dtsi9
27 files changed, 1235 insertions, 554 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 7e2424957809..17e781285a88 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -795,6 +795,7 @@ dtb-$(CONFIG_ARCH_RENESAS) += \
795 r8a7745-iwg22d-sodimm.dtb \ 795 r8a7745-iwg22d-sodimm.dtb \
796 r8a7745-iwg22d-sodimm-dbhd-ca.dtb \ 796 r8a7745-iwg22d-sodimm-dbhd-ca.dtb \
797 r8a7745-sk-rzg1e.dtb \ 797 r8a7745-sk-rzg1e.dtb \
798 r8a77470-iwg23s-sbc.dtb \
798 r8a7778-bockw.dtb \ 799 r8a7778-bockw.dtb \
799 r8a7779-marzen.dtb \ 800 r8a7779-marzen.dtb \
800 r8a7790-lager.dtb \ 801 r8a7790-lager.dtb \
diff --git a/arch/arm/boot/dts/emev2-kzm9d.dts b/arch/arm/boot/dts/emev2-kzm9d.dts
index c238407133bf..0af44b7eadb9 100644
--- a/arch/arm/boot/dts/emev2-kzm9d.dts
+++ b/arch/arm/boot/dts/emev2-kzm9d.dts
@@ -34,9 +34,6 @@
34 34
35 gpio_keys { 35 gpio_keys {
36 compatible = "gpio-keys"; 36 compatible = "gpio-keys";
37 #address-cells = <1>;
38 #size-cells = <0>;
39
40 one { 37 one {
41 debounce-interval = <50>; 38 debounce-interval = <50>;
42 wakeup-source; 39 wakeup-source;
diff --git a/arch/arm/boot/dts/emev2.dtsi b/arch/arm/boot/dts/emev2.dtsi
index 42ea246e71cb..fec1241b858f 100644
--- a/arch/arm/boot/dts/emev2.dtsi
+++ b/arch/arm/boot/dts/emev2.dtsi
@@ -31,13 +31,13 @@
31 #address-cells = <1>; 31 #address-cells = <1>;
32 #size-cells = <0>; 32 #size-cells = <0>;
33 33
34 cpu@0 { 34 cpu0: cpu@0 {
35 device_type = "cpu"; 35 device_type = "cpu";
36 compatible = "arm,cortex-a9"; 36 compatible = "arm,cortex-a9";
37 reg = <0>; 37 reg = <0>;
38 clock-frequency = <533000000>; 38 clock-frequency = <533000000>;
39 }; 39 };
40 cpu@1 { 40 cpu1: cpu@1 {
41 device_type = "cpu"; 41 device_type = "cpu";
42 compatible = "arm,cortex-a9"; 42 compatible = "arm,cortex-a9";
43 reg = <1>; 43 reg = <1>;
@@ -57,6 +57,7 @@
57 compatible = "arm,cortex-a9-pmu"; 57 compatible = "arm,cortex-a9-pmu";
58 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 58 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
59 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 59 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
60 interrupt-affinity = <&cpu0>, <&cpu1>;
60 }; 61 };
61 62
62 clocks@e0110000 { 63 clocks@e0110000 {
diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi
index ab9645a42eca..a54822e97bac 100644
--- a/arch/arm/boot/dts/r7s72100.dtsi
+++ b/arch/arm/boot/dts/r7s72100.dtsi
@@ -15,7 +15,6 @@
15 15
16/ { 16/ {
17 compatible = "renesas,r7s72100"; 17 compatible = "renesas,r7s72100";
18 interrupt-parent = <&gic>;
19 #address-cells = <1>; 18 #address-cells = <1>;
20 #size-cells = <1>; 19 #size-cells = <1>;
21 20
@@ -31,61 +30,370 @@
31 spi4 = &spi4; 30 spi4 = &spi4;
32 }; 31 };
33 32
34 clocks { 33 /* Fixed factor clocks */
35 ranges; 34 b_clk: b {
35 #clock-cells = <0>;
36 compatible = "fixed-factor-clock";
37 clocks = <&cpg_clocks R7S72100_CLK_PLL>;
38 clock-mult = <1>;
39 clock-div = <3>;
40 };
41
42 cpus {
43 #address-cells = <1>;
44 #size-cells = <0>;
45
46 cpu@0 {
47 device_type = "cpu";
48 compatible = "arm,cortex-a9";
49 reg = <0>;
50 clock-frequency = <400000000>;
51 clocks = <&cpg_clocks R7S72100_CLK_I>;
52 next-level-cache = <&L2>;
53 };
54 };
55
56 /* External clocks */
57 extal_clk: extal {
58 #clock-cells = <0>;
59 compatible = "fixed-clock";
60 /* If clk present, value must be set by board */
61 clock-frequency = <0>;
62 };
63
64 p0_clk: p0 {
65 #clock-cells = <0>;
66 compatible = "fixed-factor-clock";
67 clocks = <&cpg_clocks R7S72100_CLK_PLL>;
68 clock-mult = <1>;
69 clock-div = <12>;
70 };
71
72 p1_clk: p1 {
73 #clock-cells = <0>;
74 compatible = "fixed-factor-clock";
75 clocks = <&cpg_clocks R7S72100_CLK_PLL>;
76 clock-mult = <1>;
77 clock-div = <6>;
78 };
79
80 pmu {
81 compatible = "arm,cortex-a9-pmu";
82 interrupts-extended = <&gic GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>;
83 };
84
85 rtc_x1_clk: rtc_x1 {
86 #clock-cells = <0>;
87 compatible = "fixed-clock";
88 /* If clk present, value must be set by board to 32678 */
89 clock-frequency = <0>;
90 };
91
92 rtc_x3_clk: rtc_x3 {
93 #clock-cells = <0>;
94 compatible = "fixed-clock";
95 /* If clk present, value must be set by board to 4000000 */
96 clock-frequency = <0>;
97 };
98
99 soc {
100 compatible = "simple-bus";
101 interrupt-parent = <&gic>;
102
36 #address-cells = <1>; 103 #address-cells = <1>;
37 #size-cells = <1>; 104 #size-cells = <1>;
105 ranges;
106
107 L2: cache-controller@3ffff000 {
108 compatible = "arm,pl310-cache";
109 reg = <0x3ffff000 0x1000>;
110 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
111 arm,early-bresp-disable;
112 arm,full-line-zero-disable;
113 cache-unified;
114 cache-level = <2>;
115 };
116
117 scif0: serial@e8007000 {
118 compatible = "renesas,scif-r7s72100", "renesas,scif";
119 reg = <0xe8007000 64>;
120 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
121 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
122 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
123 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
124 clocks = <&mstp4_clks R7S72100_CLK_SCIF0>;
125 clock-names = "fck";
126 power-domains = <&cpg_clocks>;
127 status = "disabled";
128 };
129
130 scif1: serial@e8007800 {
131 compatible = "renesas,scif-r7s72100", "renesas,scif";
132 reg = <0xe8007800 64>;
133 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
134 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
135 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
136 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
137 clocks = <&mstp4_clks R7S72100_CLK_SCIF1>;
138 clock-names = "fck";
139 power-domains = <&cpg_clocks>;
140 status = "disabled";
141 };
142
143 scif2: serial@e8008000 {
144 compatible = "renesas,scif-r7s72100", "renesas,scif";
145 reg = <0xe8008000 64>;
146 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
147 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
148 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
149 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
150 clocks = <&mstp4_clks R7S72100_CLK_SCIF2>;
151 clock-names = "fck";
152 power-domains = <&cpg_clocks>;
153 status = "disabled";
154 };
155
156 scif3: serial@e8008800 {
157 compatible = "renesas,scif-r7s72100", "renesas,scif";
158 reg = <0xe8008800 64>;
159 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
160 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
161 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
162 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
163 clocks = <&mstp4_clks R7S72100_CLK_SCIF3>;
164 clock-names = "fck";
165 power-domains = <&cpg_clocks>;
166 status = "disabled";
167 };
38 168
39 /* External clocks */ 169 scif4: serial@e8009000 {
40 extal_clk: extal { 170 compatible = "renesas,scif-r7s72100", "renesas,scif";
41 #clock-cells = <0>; 171 reg = <0xe8009000 64>;
42 compatible = "fixed-clock"; 172 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
43 /* If clk present, value must be set by board */ 173 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
44 clock-frequency = <0>; 174 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
175 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
176 clocks = <&mstp4_clks R7S72100_CLK_SCIF4>;
177 clock-names = "fck";
178 power-domains = <&cpg_clocks>;
179 status = "disabled";
45 }; 180 };
46 181
47 usb_x1_clk: usb_x1 { 182 scif5: serial@e8009800 {
48 #clock-cells = <0>; 183 compatible = "renesas,scif-r7s72100", "renesas,scif";
49 compatible = "fixed-clock"; 184 reg = <0xe8009800 64>;
50 /* If clk present, value must be set by board */ 185 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
51 clock-frequency = <0>; 186 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
187 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
188 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
189 clocks = <&mstp4_clks R7S72100_CLK_SCIF5>;
190 clock-names = "fck";
191 power-domains = <&cpg_clocks>;
192 status = "disabled";
52 }; 193 };
53 194
54 rtc_x1_clk: rtc_x1 { 195 scif6: serial@e800a000 {
55 #clock-cells = <0>; 196 compatible = "renesas,scif-r7s72100", "renesas,scif";
56 compatible = "fixed-clock"; 197 reg = <0xe800a000 64>;
57 /* If clk present, value must be set by board to 32678 */ 198 interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
58 clock-frequency = <0>; 199 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
200 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
201 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
202 clocks = <&mstp4_clks R7S72100_CLK_SCIF6>;
203 clock-names = "fck";
204 power-domains = <&cpg_clocks>;
205 status = "disabled";
59 }; 206 };
60 207
61 rtc_x3_clk: rtc_x3 { 208 scif7: serial@e800a800 {
62 #clock-cells = <0>; 209 compatible = "renesas,scif-r7s72100", "renesas,scif";
63 compatible = "fixed-clock"; 210 reg = <0xe800a800 64>;
64 /* If clk present, value must be set by board to 4000000 */ 211 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
65 clock-frequency = <0>; 212 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
213 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
214 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
215 clocks = <&mstp4_clks R7S72100_CLK_SCIF7>;
216 clock-names = "fck";
217 power-domains = <&cpg_clocks>;
218 status = "disabled";
66 }; 219 };
67 220
68 /* Fixed factor clocks */ 221 spi0: spi@e800c800 {
69 b_clk: b { 222 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
70 #clock-cells = <0>; 223 reg = <0xe800c800 0x24>;
71 compatible = "fixed-factor-clock"; 224 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
72 clocks = <&cpg_clocks R7S72100_CLK_PLL>; 225 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
73 clock-mult = <1>; 226 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
74 clock-div = <3>; 227 interrupt-names = "error", "rx", "tx";
228 clocks = <&mstp10_clks R7S72100_CLK_SPI0>;
229 power-domains = <&cpg_clocks>;
230 num-cs = <1>;
231 #address-cells = <1>;
232 #size-cells = <0>;
233 status = "disabled";
75 }; 234 };
76 p1_clk: p1 { 235
77 #clock-cells = <0>; 236 spi1: spi@e800d000 {
78 compatible = "fixed-factor-clock"; 237 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
79 clocks = <&cpg_clocks R7S72100_CLK_PLL>; 238 reg = <0xe800d000 0x24>;
80 clock-mult = <1>; 239 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
81 clock-div = <6>; 240 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
241 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
242 interrupt-names = "error", "rx", "tx";
243 clocks = <&mstp10_clks R7S72100_CLK_SPI1>;
244 power-domains = <&cpg_clocks>;
245 num-cs = <1>;
246 #address-cells = <1>;
247 #size-cells = <0>;
248 status = "disabled";
249 };
250
251 spi2: spi@e800d800 {
252 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
253 reg = <0xe800d800 0x24>;
254 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
255 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
256 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
257 interrupt-names = "error", "rx", "tx";
258 clocks = <&mstp10_clks R7S72100_CLK_SPI2>;
259 power-domains = <&cpg_clocks>;
260 num-cs = <1>;
261 #address-cells = <1>;
262 #size-cells = <0>;
263 status = "disabled";
82 }; 264 };
83 p0_clk: p0 { 265
84 #clock-cells = <0>; 266 spi3: spi@e800e000 {
85 compatible = "fixed-factor-clock"; 267 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
86 clocks = <&cpg_clocks R7S72100_CLK_PLL>; 268 reg = <0xe800e000 0x24>;
87 clock-mult = <1>; 269 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
88 clock-div = <12>; 270 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
271 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
272 interrupt-names = "error", "rx", "tx";
273 clocks = <&mstp10_clks R7S72100_CLK_SPI3>;
274 power-domains = <&cpg_clocks>;
275 num-cs = <1>;
276 #address-cells = <1>;
277 #size-cells = <0>;
278 status = "disabled";
279 };
280
281 spi4: spi@e800e800 {
282 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
283 reg = <0xe800e800 0x24>;
284 interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
285 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
286 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
287 interrupt-names = "error", "rx", "tx";
288 clocks = <&mstp10_clks R7S72100_CLK_SPI4>;
289 power-domains = <&cpg_clocks>;
290 num-cs = <1>;
291 #address-cells = <1>;
292 #size-cells = <0>;
293 status = "disabled";
294 };
295
296 usbhs0: usb@e8010000 {
297 compatible = "renesas,usbhs-r7s72100", "renesas,rza1-usbhs";
298 reg = <0xe8010000 0x1a0>;
299 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
300 clocks = <&mstp7_clks R7S72100_CLK_USB0>;
301 renesas,buswait = <4>;
302 power-domains = <&cpg_clocks>;
303 status = "disabled";
304 };
305
306 usbhs1: usb@e8207000 {
307 compatible = "renesas,usbhs-r7s72100", "renesas,rza1-usbhs";
308 reg = <0xe8207000 0x1a0>;
309 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
310 clocks = <&mstp7_clks R7S72100_CLK_USB1>;
311 renesas,buswait = <4>;
312 power-domains = <&cpg_clocks>;
313 status = "disabled";
314 };
315
316 mmcif: mmc@e804c800 {
317 compatible = "renesas,mmcif-r7s72100", "renesas,sh-mmcif";
318 reg = <0xe804c800 0x80>;
319 interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH
320 GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH
321 GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
322 clocks = <&mstp8_clks R7S72100_CLK_MMCIF>;
323 power-domains = <&cpg_clocks>;
324 reg-io-width = <4>;
325 bus-width = <8>;
326 status = "disabled";
327 };
328
329 sdhi0: sd@e804e000 {
330 compatible = "renesas,sdhi-r7s72100";
331 reg = <0xe804e000 0x100>;
332 interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH
333 GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH
334 GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
335
336 clocks = <&mstp12_clks R7S72100_CLK_SDHI00>,
337 <&mstp12_clks R7S72100_CLK_SDHI01>;
338 clock-names = "core", "cd";
339 power-domains = <&cpg_clocks>;
340 cap-sd-highspeed;
341 cap-sdio-irq;
342 status = "disabled";
343 };
344
345 sdhi1: sd@e804e800 {
346 compatible = "renesas,sdhi-r7s72100";
347 reg = <0xe804e800 0x100>;
348 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH
349 GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH
350 GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>;
351
352 clocks = <&mstp12_clks R7S72100_CLK_SDHI10>,
353 <&mstp12_clks R7S72100_CLK_SDHI11>;
354 clock-names = "core", "cd";
355 power-domains = <&cpg_clocks>;
356 cap-sd-highspeed;
357 cap-sdio-irq;
358 status = "disabled";
359 };
360
361 gic: interrupt-controller@e8201000 {
362 compatible = "arm,pl390";
363 #interrupt-cells = <3>;
364 #address-cells = <0>;
365 interrupt-controller;
366 reg = <0xe8201000 0x1000>,
367 <0xe8202000 0x1000>;
368 };
369
370 ether: ethernet@e8203000 {
371 compatible = "renesas,ether-r7s72100";
372 reg = <0xe8203000 0x800>,
373 <0xe8204800 0x200>;
374 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
375 clocks = <&mstp7_clks R7S72100_CLK_ETHER>;
376 power-domains = <&cpg_clocks>;
377 phy-mode = "mii";
378 #address-cells = <1>;
379 #size-cells = <0>;
380 status = "disabled";
381 };
382
383 ceu: camera@e8210000 {
384 reg = <0xe8210000 0x3000>;
385 compatible = "renesas,r7s72100-ceu";
386 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
387 clocks = <&mstp6_clks R7S72100_CLK_CEU>;
388 power-domains = <&cpg_clocks>;
389 status = "disabled";
390 };
391
392 wdt: watchdog@fcfe0000 {
393 compatible = "renesas,r7s72100-wdt", "renesas,rza-wdt";
394 reg = <0xfcfe0000 0x6>;
395 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
396 clocks = <&p0_clk>;
89 }; 397 };
90 398
91 /* Special CPG clocks */ 399 /* Special CPG clocks */
@@ -135,9 +443,9 @@
135 #clock-cells = <1>; 443 #clock-cells = <1>;
136 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; 444 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
137 reg = <0xfcfe042c 4>; 445 reg = <0xfcfe042c 4>;
138 clocks = <&p0_clk>; 446 clocks = <&b_clk>, <&p0_clk>;
139 clock-indices = <R7S72100_CLK_RTC>; 447 clock-indices = <R7S72100_CLK_CEU R7S72100_CLK_RTC>;
140 clock-output-names = "rtc"; 448 clock-output-names = "ceu", "rtc";
141 }; 449 };
142 450
143 mstp7_clks: mstp7_clks@fcfe0430 { 451 mstp7_clks: mstp7_clks@fcfe0430 {
@@ -192,479 +500,209 @@
192 >; 500 >;
193 clock-output-names = "sdhi00", "sdhi01", "sdhi10", "sdhi11"; 501 clock-output-names = "sdhi00", "sdhi01", "sdhi10", "sdhi11";
194 }; 502 };
195 };
196
197 cpus {
198 #address-cells = <1>;
199 #size-cells = <0>;
200
201 cpu@0 {
202 device_type = "cpu";
203 compatible = "arm,cortex-a9";
204 reg = <0>;
205 clock-frequency = <400000000>;
206 clocks = <&cpg_clocks R7S72100_CLK_I>;
207 next-level-cache = <&L2>;
208 };
209 };
210
211 pinctrl: pin-controller@fcfe3000 {
212 compatible = "renesas,r7s72100-ports";
213
214 reg = <0xfcfe3000 0x4230>;
215
216 port0: gpio-0 {
217 gpio-controller;
218 #gpio-cells = <2>;
219 gpio-ranges = <&pinctrl 0 0 6>;
220 };
221
222 port1: gpio-1 {
223 gpio-controller;
224 #gpio-cells = <2>;
225 gpio-ranges = <&pinctrl 0 16 16>;
226 };
227 503
228 port2: gpio-2 { 504 pinctrl: pin-controller@fcfe3000 {
229 gpio-controller; 505 compatible = "renesas,r7s72100-ports";
230 #gpio-cells = <2>; 506
231 gpio-ranges = <&pinctrl 0 32 16>; 507 reg = <0xfcfe3000 0x4230>;
508
509 port0: gpio-0 {
510 gpio-controller;
511 #gpio-cells = <2>;
512 gpio-ranges = <&pinctrl 0 0 6>;
513 };
514
515 port1: gpio-1 {
516 gpio-controller;
517 #gpio-cells = <2>;
518 gpio-ranges = <&pinctrl 0 16 16>;
519 };
520
521 port2: gpio-2 {
522 gpio-controller;
523 #gpio-cells = <2>;
524 gpio-ranges = <&pinctrl 0 32 16>;
525 };
526
527 port3: gpio-3 {
528 gpio-controller;
529 #gpio-cells = <2>;
530 gpio-ranges = <&pinctrl 0 48 16>;
531 };
532
533 port4: gpio-4 {
534 gpio-controller;
535 #gpio-cells = <2>;
536 gpio-ranges = <&pinctrl 0 64 16>;
537 };
538
539 port5: gpio-5 {
540 gpio-controller;
541 #gpio-cells = <2>;
542 gpio-ranges = <&pinctrl 0 80 11>;
543 };
544
545 port6: gpio-6 {
546 gpio-controller;
547 #gpio-cells = <2>;
548 gpio-ranges = <&pinctrl 0 96 16>;
549 };
550
551 port7: gpio-7 {
552 gpio-controller;
553 #gpio-cells = <2>;
554 gpio-ranges = <&pinctrl 0 112 16>;
555 };
556
557 port8: gpio-8 {
558 gpio-controller;
559 #gpio-cells = <2>;
560 gpio-ranges = <&pinctrl 0 128 16>;
561 };
562
563 port9: gpio-9 {
564 gpio-controller;
565 #gpio-cells = <2>;
566 gpio-ranges = <&pinctrl 0 144 8>;
567 };
568
569 port10: gpio-10 {
570 gpio-controller;
571 #gpio-cells = <2>;
572 gpio-ranges = <&pinctrl 0 160 16>;
573 };
574
575 port11: gpio-11 {
576 gpio-controller;
577 #gpio-cells = <2>;
578 gpio-ranges = <&pinctrl 0 176 16>;
579 };
232 }; 580 };
233 581
234 port3: gpio-3 { 582 ostm0: timer@fcfec000 {
235 gpio-controller; 583 compatible = "renesas,r7s72100-ostm", "renesas,ostm";
236 #gpio-cells = <2>; 584 reg = <0xfcfec000 0x30>;
237 gpio-ranges = <&pinctrl 0 48 16>; 585 interrupts = <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>;
586 clocks = <&mstp5_clks R7S72100_CLK_OSTM0>;
587 power-domains = <&cpg_clocks>;
588 status = "disabled";
238 }; 589 };
239 590
240 port4: gpio-4 { 591 ostm1: timer@fcfec400 {
241 gpio-controller; 592 compatible = "renesas,r7s72100-ostm", "renesas,ostm";
242 #gpio-cells = <2>; 593 reg = <0xfcfec400 0x30>;
243 gpio-ranges = <&pinctrl 0 64 16>; 594 interrupts = <GIC_SPI 103 IRQ_TYPE_EDGE_RISING>;
595 clocks = <&mstp5_clks R7S72100_CLK_OSTM1>;
596 power-domains = <&cpg_clocks>;
597 status = "disabled";
244 }; 598 };
245 599
246 port5: gpio-5 { 600 i2c0: i2c@fcfee000 {
247 gpio-controller; 601 #address-cells = <1>;
248 #gpio-cells = <2>; 602 #size-cells = <0>;
249 gpio-ranges = <&pinctrl 0 80 11>; 603 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
604 reg = <0xfcfee000 0x44>;
605 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
606 <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>,
607 <GIC_SPI 159 IRQ_TYPE_EDGE_RISING>,
608 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
609 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
610 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
611 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
612 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
613 clocks = <&mstp9_clks R7S72100_CLK_I2C0>;
614 clock-frequency = <100000>;
615 power-domains = <&cpg_clocks>;
616 status = "disabled";
250 }; 617 };
251 618
252 port6: gpio-6 { 619 i2c1: i2c@fcfee400 {
253 gpio-controller; 620 #address-cells = <1>;
254 #gpio-cells = <2>; 621 #size-cells = <0>;
255 gpio-ranges = <&pinctrl 0 96 16>; 622 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
623 reg = <0xfcfee400 0x44>;
624 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
625 <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>,
626 <GIC_SPI 167 IRQ_TYPE_EDGE_RISING>,
627 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
628 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
629 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
630 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
631 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
632 clocks = <&mstp9_clks R7S72100_CLK_I2C1>;
633 clock-frequency = <100000>;
634 power-domains = <&cpg_clocks>;
635 status = "disabled";
256 }; 636 };
257 637
258 port7: gpio-7 { 638 i2c2: i2c@fcfee800 {
259 gpio-controller; 639 #address-cells = <1>;
260 #gpio-cells = <2>; 640 #size-cells = <0>;
261 gpio-ranges = <&pinctrl 0 112 16>; 641 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
642 reg = <0xfcfee800 0x44>;
643 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
644 <GIC_SPI 174 IRQ_TYPE_EDGE_RISING>,
645 <GIC_SPI 175 IRQ_TYPE_EDGE_RISING>,
646 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
647 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
648 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
649 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
650 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
651 clocks = <&mstp9_clks R7S72100_CLK_I2C2>;
652 clock-frequency = <100000>;
653 power-domains = <&cpg_clocks>;
654 status = "disabled";
262 }; 655 };
263 656
264 port8: gpio-8 { 657 i2c3: i2c@fcfeec00 {
265 gpio-controller; 658 #address-cells = <1>;
266 #gpio-cells = <2>; 659 #size-cells = <0>;
267 gpio-ranges = <&pinctrl 0 128 16>; 660 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
661 reg = <0xfcfeec00 0x44>;
662 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
663 <GIC_SPI 182 IRQ_TYPE_EDGE_RISING>,
664 <GIC_SPI 183 IRQ_TYPE_EDGE_RISING>,
665 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
666 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
667 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
668 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
669 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
670 clocks = <&mstp9_clks R7S72100_CLK_I2C3>;
671 clock-frequency = <100000>;
672 power-domains = <&cpg_clocks>;
673 status = "disabled";
268 }; 674 };
269 675
270 port9: gpio-9 { 676 mtu2: timer@fcff0000 {
271 gpio-controller; 677 compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
272 #gpio-cells = <2>; 678 reg = <0xfcff0000 0x400>;
273 gpio-ranges = <&pinctrl 0 144 8>; 679 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
680 interrupt-names = "tgi0a";
681 clocks = <&mstp3_clks R7S72100_CLK_MTU2>;
682 clock-names = "fck";
683 power-domains = <&cpg_clocks>;
684 status = "disabled";
274 }; 685 };
275 686
276 port10: gpio-10 { 687 rtc: rtc@fcff1000 {
277 gpio-controller; 688 compatible = "renesas,r7s72100-rtc", "renesas,sh-rtc";
278 #gpio-cells = <2>; 689 reg = <0xfcff1000 0x2e>;
279 gpio-ranges = <&pinctrl 0 160 16>; 690 interrupts = <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
691 <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
692 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>;
693 interrupt-names = "alarm", "period", "carry";
694 clocks = <&mstp6_clks R7S72100_CLK_RTC>, <&rtc_x1_clk>,
695 <&rtc_x3_clk>, <&extal_clk>;
696 clock-names = "fck", "rtc_x1", "rtc_x3", "extal";
697 power-domains = <&cpg_clocks>;
698 status = "disabled";
280 }; 699 };
281
282 port11: gpio-11 {
283 gpio-controller;
284 #gpio-cells = <2>;
285 gpio-ranges = <&pinctrl 0 176 16>;
286 };
287 };
288
289 scif0: serial@e8007000 {
290 compatible = "renesas,scif-r7s72100", "renesas,scif";
291 reg = <0xe8007000 64>;
292 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
293 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
294 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
295 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
296 clocks = <&mstp4_clks R7S72100_CLK_SCIF0>;
297 clock-names = "fck";
298 power-domains = <&cpg_clocks>;
299 status = "disabled";
300 };
301
302 scif1: serial@e8007800 {
303 compatible = "renesas,scif-r7s72100", "renesas,scif";
304 reg = <0xe8007800 64>;
305 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
306 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
307 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
308 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
309 clocks = <&mstp4_clks R7S72100_CLK_SCIF1>;
310 clock-names = "fck";
311 power-domains = <&cpg_clocks>;
312 status = "disabled";
313 };
314
315 scif2: serial@e8008000 {
316 compatible = "renesas,scif-r7s72100", "renesas,scif";
317 reg = <0xe8008000 64>;
318 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
319 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
320 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
321 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
322 clocks = <&mstp4_clks R7S72100_CLK_SCIF2>;
323 clock-names = "fck";
324 power-domains = <&cpg_clocks>;
325 status = "disabled";
326 };
327
328 scif3: serial@e8008800 {
329 compatible = "renesas,scif-r7s72100", "renesas,scif";
330 reg = <0xe8008800 64>;
331 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
332 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
333 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
334 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
335 clocks = <&mstp4_clks R7S72100_CLK_SCIF3>;
336 clock-names = "fck";
337 power-domains = <&cpg_clocks>;
338 status = "disabled";
339 };
340
341 scif4: serial@e8009000 {
342 compatible = "renesas,scif-r7s72100", "renesas,scif";
343 reg = <0xe8009000 64>;
344 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
345 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
346 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
347 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
348 clocks = <&mstp4_clks R7S72100_CLK_SCIF4>;
349 clock-names = "fck";
350 power-domains = <&cpg_clocks>;
351 status = "disabled";
352 };
353
354 scif5: serial@e8009800 {
355 compatible = "renesas,scif-r7s72100", "renesas,scif";
356 reg = <0xe8009800 64>;
357 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
358 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
359 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
360 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
361 clocks = <&mstp4_clks R7S72100_CLK_SCIF5>;
362 clock-names = "fck";
363 power-domains = <&cpg_clocks>;
364 status = "disabled";
365 };
366
367 scif6: serial@e800a000 {
368 compatible = "renesas,scif-r7s72100", "renesas,scif";
369 reg = <0xe800a000 64>;
370 interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
371 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
372 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
373 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
374 clocks = <&mstp4_clks R7S72100_CLK_SCIF6>;
375 clock-names = "fck";
376 power-domains = <&cpg_clocks>;
377 status = "disabled";
378 };
379
380 scif7: serial@e800a800 {
381 compatible = "renesas,scif-r7s72100", "renesas,scif";
382 reg = <0xe800a800 64>;
383 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
384 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
385 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
386 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
387 clocks = <&mstp4_clks R7S72100_CLK_SCIF7>;
388 clock-names = "fck";
389 power-domains = <&cpg_clocks>;
390 status = "disabled";
391 };
392
393 spi0: spi@e800c800 {
394 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
395 reg = <0xe800c800 0x24>;
396 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
397 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
398 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
399 interrupt-names = "error", "rx", "tx";
400 clocks = <&mstp10_clks R7S72100_CLK_SPI0>;
401 power-domains = <&cpg_clocks>;
402 num-cs = <1>;
403 #address-cells = <1>;
404 #size-cells = <0>;
405 status = "disabled";
406 };
407
408 spi1: spi@e800d000 {
409 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
410 reg = <0xe800d000 0x24>;
411 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
412 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
413 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
414 interrupt-names = "error", "rx", "tx";
415 clocks = <&mstp10_clks R7S72100_CLK_SPI1>;
416 power-domains = <&cpg_clocks>;
417 num-cs = <1>;
418 #address-cells = <1>;
419 #size-cells = <0>;
420 status = "disabled";
421 };
422
423 spi2: spi@e800d800 {
424 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
425 reg = <0xe800d800 0x24>;
426 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
427 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
428 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
429 interrupt-names = "error", "rx", "tx";
430 clocks = <&mstp10_clks R7S72100_CLK_SPI2>;
431 power-domains = <&cpg_clocks>;
432 num-cs = <1>;
433 #address-cells = <1>;
434 #size-cells = <0>;
435 status = "disabled";
436 };
437
438 spi3: spi@e800e000 {
439 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
440 reg = <0xe800e000 0x24>;
441 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
442 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
443 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
444 interrupt-names = "error", "rx", "tx";
445 clocks = <&mstp10_clks R7S72100_CLK_SPI3>;
446 power-domains = <&cpg_clocks>;
447 num-cs = <1>;
448 #address-cells = <1>;
449 #size-cells = <0>;
450 status = "disabled";
451 };
452
453 spi4: spi@e800e800 {
454 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
455 reg = <0xe800e800 0x24>;
456 interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
457 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
458 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
459 interrupt-names = "error", "rx", "tx";
460 clocks = <&mstp10_clks R7S72100_CLK_SPI4>;
461 power-domains = <&cpg_clocks>;
462 num-cs = <1>;
463 #address-cells = <1>;
464 #size-cells = <0>;
465 status = "disabled";
466 };
467
468 gic: interrupt-controller@e8201000 {
469 compatible = "arm,pl390";
470 #interrupt-cells = <3>;
471 #address-cells = <0>;
472 interrupt-controller;
473 reg = <0xe8201000 0x1000>,
474 <0xe8202000 0x1000>;
475 };
476
477 L2: cache-controller@3ffff000 {
478 compatible = "arm,pl310-cache";
479 reg = <0x3ffff000 0x1000>;
480 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
481 arm,early-bresp-disable;
482 arm,full-line-zero-disable;
483 cache-unified;
484 cache-level = <2>;
485 };
486
487 wdt: watchdog@fcfe0000 {
488 compatible = "renesas,r7s72100-wdt", "renesas,rza-wdt";
489 reg = <0xfcfe0000 0x6>;
490 interrupts = <GIC_SPI 106 IRQ_TYPE_EDGE_RISING>;
491 clocks = <&p0_clk>;
492 };
493
494 i2c0: i2c@fcfee000 {
495 #address-cells = <1>;
496 #size-cells = <0>;
497 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
498 reg = <0xfcfee000 0x44>;
499 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
500 <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>,
501 <GIC_SPI 159 IRQ_TYPE_EDGE_RISING>,
502 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
503 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
504 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
505 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
506 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
507 clocks = <&mstp9_clks R7S72100_CLK_I2C0>;
508 clock-frequency = <100000>;
509 power-domains = <&cpg_clocks>;
510 status = "disabled";
511 };
512
513 i2c1: i2c@fcfee400 {
514 #address-cells = <1>;
515 #size-cells = <0>;
516 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
517 reg = <0xfcfee400 0x44>;
518 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
519 <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>,
520 <GIC_SPI 167 IRQ_TYPE_EDGE_RISING>,
521 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
522 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
523 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
524 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
525 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
526 clocks = <&mstp9_clks R7S72100_CLK_I2C1>;
527 clock-frequency = <100000>;
528 power-domains = <&cpg_clocks>;
529 status = "disabled";
530 };
531
532 i2c2: i2c@fcfee800 {
533 #address-cells = <1>;
534 #size-cells = <0>;
535 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
536 reg = <0xfcfee800 0x44>;
537 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
538 <GIC_SPI 174 IRQ_TYPE_EDGE_RISING>,
539 <GIC_SPI 175 IRQ_TYPE_EDGE_RISING>,
540 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
541 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
542 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
543 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
544 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
545 clocks = <&mstp9_clks R7S72100_CLK_I2C2>;
546 clock-frequency = <100000>;
547 power-domains = <&cpg_clocks>;
548 status = "disabled";
549 };
550
551 i2c3: i2c@fcfeec00 {
552 #address-cells = <1>;
553 #size-cells = <0>;
554 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
555 reg = <0xfcfeec00 0x44>;
556 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
557 <GIC_SPI 182 IRQ_TYPE_EDGE_RISING>,
558 <GIC_SPI 183 IRQ_TYPE_EDGE_RISING>,
559 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
560 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
561 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
562 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
563 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
564 clocks = <&mstp9_clks R7S72100_CLK_I2C3>;
565 clock-frequency = <100000>;
566 power-domains = <&cpg_clocks>;
567 status = "disabled";
568 };
569
570 mtu2: timer@fcff0000 {
571 compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
572 reg = <0xfcff0000 0x400>;
573 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
574 interrupt-names = "tgi0a";
575 clocks = <&mstp3_clks R7S72100_CLK_MTU2>;
576 clock-names = "fck";
577 power-domains = <&cpg_clocks>;
578 status = "disabled";
579 };
580
581 ether: ethernet@e8203000 {
582 compatible = "renesas,ether-r7s72100";
583 reg = <0xe8203000 0x800>,
584 <0xe8204800 0x200>;
585 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
586 clocks = <&mstp7_clks R7S72100_CLK_ETHER>;
587 power-domains = <&cpg_clocks>;
588 phy-mode = "mii";
589 #address-cells = <1>;
590 #size-cells = <0>;
591 status = "disabled";
592 };
593
594 mmcif: mmc@e804c800 {
595 compatible = "renesas,mmcif-r7s72100", "renesas,sh-mmcif";
596 reg = <0xe804c800 0x80>;
597 interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH
598 GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH
599 GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
600 clocks = <&mstp8_clks R7S72100_CLK_MMCIF>;
601 power-domains = <&cpg_clocks>;
602 reg-io-width = <4>;
603 bus-width = <8>;
604 status = "disabled";
605 };
606
607 sdhi0: sd@e804e000 {
608 compatible = "renesas,sdhi-r7s72100";
609 reg = <0xe804e000 0x100>;
610 interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH
611 GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH
612 GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
613
614 clocks = <&mstp12_clks R7S72100_CLK_SDHI00>,
615 <&mstp12_clks R7S72100_CLK_SDHI01>;
616 clock-names = "core", "cd";
617 power-domains = <&cpg_clocks>;
618 cap-sd-highspeed;
619 cap-sdio-irq;
620 status = "disabled";
621 };
622
623 sdhi1: sd@e804e800 {
624 compatible = "renesas,sdhi-r7s72100";
625 reg = <0xe804e800 0x100>;
626 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH
627 GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH
628 GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>;
629
630 clocks = <&mstp12_clks R7S72100_CLK_SDHI10>,
631 <&mstp12_clks R7S72100_CLK_SDHI11>;
632 clock-names = "core", "cd";
633 power-domains = <&cpg_clocks>;
634 cap-sd-highspeed;
635 cap-sdio-irq;
636 status = "disabled";
637 };
638
639 ostm0: timer@fcfec000 {
640 compatible = "renesas,r7s72100-ostm", "renesas,ostm";
641 reg = <0xfcfec000 0x30>;
642 interrupts = <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>;
643 clocks = <&mstp5_clks R7S72100_CLK_OSTM0>;
644 power-domains = <&cpg_clocks>;
645 status = "disabled";
646 };
647
648 ostm1: timer@fcfec400 {
649 compatible = "renesas,r7s72100-ostm", "renesas,ostm";
650 reg = <0xfcfec400 0x30>;
651 interrupts = <GIC_SPI 103 IRQ_TYPE_EDGE_RISING>;
652 clocks = <&mstp5_clks R7S72100_CLK_OSTM1>;
653 power-domains = <&cpg_clocks>;
654 status = "disabled";
655 }; 700 };
656 701
657 rtc: rtc@fcff1000 { 702 usb_x1_clk: usb_x1 {
658 compatible = "renesas,r7s72100-rtc", "renesas,sh-rtc"; 703 #clock-cells = <0>;
659 reg = <0xfcff1000 0x2e>; 704 compatible = "fixed-clock";
660 interrupts = <GIC_SPI 276 IRQ_TYPE_EDGE_RISING 705 /* If clk present, value must be set by board */
661 GIC_SPI 277 IRQ_TYPE_EDGE_RISING 706 clock-frequency = <0>;
662 GIC_SPI 278 IRQ_TYPE_EDGE_RISING>;
663 interrupt-names = "alarm", "period", "carry";
664 clocks = <&mstp6_clks R7S72100_CLK_RTC>, <&rtc_x1_clk>,
665 <&rtc_x3_clk>, <&extal_clk>;
666 clock-names = "fck", "rtc_x1", "rtc_x3", "extal";
667 power-domains = <&cpg_clocks>;
668 status = "disabled";
669 }; 707 };
670}; 708};
diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm.dts b/arch/arm/boot/dts/r8a73a4-ape6evm.dts
index ec7c86e06538..125c39c0222f 100644
--- a/arch/arm/boot/dts/r8a73a4-ape6evm.dts
+++ b/arch/arm/boot/dts/r8a73a4-ape6evm.dts
@@ -234,7 +234,7 @@
234&sdhi0 { 234&sdhi0 {
235 vmmc-supply = <&vcc_sdhi0>; 235 vmmc-supply = <&vcc_sdhi0>;
236 bus-width = <4>; 236 bus-width = <4>;
237 toshiba,mmc-wrprotect-disable; 237 disable-wp;
238 pinctrl-names = "default"; 238 pinctrl-names = "default";
239 pinctrl-0 = <&sdhi0_pins>; 239 pinctrl-0 = <&sdhi0_pins>;
240 status = "okay"; 240 status = "okay";
@@ -244,7 +244,7 @@
244 vmmc-supply = <&ape6evm_fixed_3v3>; 244 vmmc-supply = <&ape6evm_fixed_3v3>;
245 bus-width = <4>; 245 bus-width = <4>;
246 broken-cd; 246 broken-cd;
247 toshiba,mmc-wrprotect-disable; 247 disable-wp;
248 pinctrl-names = "default"; 248 pinctrl-names = "default";
249 pinctrl-0 = <&sdhi1_pins>; 249 pinctrl-0 = <&sdhi1_pins>;
250 status = "okay"; 250 status = "okay";
diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi
index 8e48090e4fdc..080d037f5733 100644
--- a/arch/arm/boot/dts/r8a73a4.dtsi
+++ b/arch/arm/boot/dts/r8a73a4.dtsi
@@ -57,10 +57,10 @@
57 57
58 timer { 58 timer {
59 compatible = "arm,armv7-timer"; 59 compatible = "arm,armv7-timer";
60 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 60 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
61 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 61 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
62 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 62 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
63 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 63 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
64 }; 64 };
65 65
66 dbsc1: memory-controller@e6790000 { 66 dbsc1: memory-controller@e6790000 {
@@ -464,7 +464,7 @@
464 <0 0xf1002000 0 0x2000>, 464 <0 0xf1002000 0 0x2000>,
465 <0 0xf1004000 0 0x2000>, 465 <0 0xf1004000 0 0x2000>,
466 <0 0xf1006000 0 0x2000>; 466 <0 0xf1006000 0 0x2000>;
467 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 467 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
468 clocks = <&mstp4_clks R8A73A4_CLK_INTC_SYS>; 468 clocks = <&mstp4_clks R8A73A4_CLK_INTC_SYS>;
469 clock-names = "clk"; 469 clock-names = "clk";
470 power-domains = <&pd_c4>; 470 power-domains = <&pd_c4>;
diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi
index afd3bc5e6cf2..eb9a911deefb 100644
--- a/arch/arm/boot/dts/r8a7740.dtsi
+++ b/arch/arm/boot/dts/r8a7740.dtsi
@@ -67,6 +67,24 @@
67 power-domains = <&pd_d4>; 67 power-domains = <&pd_d4>;
68 }; 68 };
69 69
70 ceu0: ceu@fe910000 {
71 reg = <0xfe910000 0x3000>;
72 compatible = "renesas,r8a7740-ceu";
73 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
74 clocks = <&mstp1_clks R8A7740_CLK_CEU20>;
75 power-domains = <&pd_a4r>;
76 status = "disabled";
77 };
78
79 ceu1: ceu@fe914000 {
80 reg = <0xfe914000 0x3000>;
81 compatible = "renesas,r8a7740-ceu";
82 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
83 clocks = <&mstp1_clks R8A7740_CLK_CEU21>;
84 power-domains = <&pd_a4r>;
85 status = "disabled";
86 };
87
70 cmt1: timer@e6138000 { 88 cmt1: timer@e6138000 {
71 compatible = "renesas,cmt-48-r8a7740", "renesas,cmt-48"; 89 compatible = "renesas,cmt-48-r8a7740", "renesas,cmt-48";
72 reg = <0xe6138000 0x170>; 90 reg = <0xe6138000 0x170>;
diff --git a/arch/arm/boot/dts/r8a7743-iwg20m.dtsi b/arch/arm/boot/dts/r8a7743-iwg20m.dtsi
index 1d3e9503c5bd..d364685d9184 100644
--- a/arch/arm/boot/dts/r8a7743-iwg20m.dtsi
+++ b/arch/arm/boot/dts/r8a7743-iwg20m.dtsi
@@ -91,6 +91,11 @@
91 }; 91 };
92}; 92};
93 93
94&rwdt {
95 timeout-sec = <60>;
96 status = "okay";
97};
98
94&sdhi0 { 99&sdhi0 {
95 pinctrl-0 = <&sdhi0_pins>; 100 pinctrl-0 = <&sdhi0_pins>;
96 pinctrl-names = "default"; 101 pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
index 1d9073ba0ce0..142949d7066f 100644
--- a/arch/arm/boot/dts/r8a7743.dtsi
+++ b/arch/arm/boot/dts/r8a7743.dtsi
@@ -125,6 +125,13 @@
125 clock-frequency = <0>; 125 clock-frequency = <0>;
126 }; 126 };
127 127
128 pmu {
129 compatible = "arm,cortex-a15-pmu";
130 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
131 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
132 interrupt-affinity = <&cpu0>, <&cpu1>;
133 };
134
128 /* External SCIF clock */ 135 /* External SCIF clock */
129 scif_clk: scif { 136 scif_clk: scif {
130 compatible = "fixed-clock"; 137 compatible = "fixed-clock";
@@ -297,6 +304,16 @@
297 reg = <0 0xe6160000 0 0x100>; 304 reg = <0 0xe6160000 0 0x100>;
298 }; 305 };
299 306
307 rwdt: watchdog@e6020000 {
308 compatible = "renesas,r8a7743-wdt",
309 "renesas,rcar-gen2-wdt";
310 reg = <0 0xe6020000 0 0x0c>;
311 clocks = <&cpg CPG_MOD 402>;
312 power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
313 resets = <&cpg 402>;
314 status = "disabled";
315 };
316
300 sysc: system-controller@e6180000 { 317 sysc: system-controller@e6180000 {
301 compatible = "renesas,r8a7743-sysc"; 318 compatible = "renesas,r8a7743-sysc";
302 reg = <0 0xe6180000 0 0x200>; 319 reg = <0 0xe6180000 0 0x200>;
@@ -407,7 +424,7 @@
407 424
408 smp-sram@0 { 425 smp-sram@0 {
409 compatible = "renesas,smp-sram"; 426 compatible = "renesas,smp-sram";
410 reg = <0 0x10>; 427 reg = <0 0x100>;
411 }; 428 };
412 }; 429 };
413 430
diff --git a/arch/arm/boot/dts/r8a7745-iwg22m.dtsi b/arch/arm/boot/dts/r8a7745-iwg22m.dtsi
index 8d0a392b6811..29b6e10fdf96 100644
--- a/arch/arm/boot/dts/r8a7745-iwg22m.dtsi
+++ b/arch/arm/boot/dts/r8a7745-iwg22m.dtsi
@@ -91,6 +91,11 @@
91 }; 91 };
92}; 92};
93 93
94&rwdt {
95 timeout-sec = <60>;
96 status = "okay";
97};
98
94&sdhi1 { 99&sdhi1 {
95 pinctrl-0 = <&sdhi1_pins>; 100 pinctrl-0 = <&sdhi1_pins>;
96 pinctrl-names = "default"; 101 pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
index dd49a8b48f3e..1cb7a7ab0418 100644
--- a/arch/arm/boot/dts/r8a7745.dtsi
+++ b/arch/arm/boot/dts/r8a7745.dtsi
@@ -105,6 +105,13 @@
105 clock-frequency = <0>; 105 clock-frequency = <0>;
106 }; 106 };
107 107
108 pmu {
109 compatible = "arm,cortex-a7-pmu";
110 interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
111 <&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
112 interrupt-affinity = <&cpu0>, <&cpu1>;
113 };
114
108 /* External SCIF clock */ 115 /* External SCIF clock */
109 scif_clk: scif { 116 scif_clk: scif {
110 compatible = "fixed-clock"; 117 compatible = "fixed-clock";
@@ -262,6 +269,16 @@
262 reg = <0 0xe6160000 0 0x100>; 269 reg = <0 0xe6160000 0 0x100>;
263 }; 270 };
264 271
272 rwdt: watchdog@e6020000 {
273 compatible = "renesas,r8a7745-wdt",
274 "renesas,rcar-gen2-wdt";
275 reg = <0 0xe6020000 0 0x0c>;
276 clocks = <&cpg CPG_MOD 402>;
277 power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
278 resets = <&cpg 402>;
279 status = "disabled";
280 };
281
265 sysc: system-controller@e6180000 { 282 sysc: system-controller@e6180000 {
266 compatible = "renesas,r8a7745-sysc"; 283 compatible = "renesas,r8a7745-sysc";
267 reg = <0 0xe6180000 0 0x200>; 284 reg = <0 0xe6180000 0 0x200>;
@@ -360,7 +377,7 @@
360 377
361 smp-sram@0 { 378 smp-sram@0 {
362 compatible = "renesas,smp-sram"; 379 compatible = "renesas,smp-sram";
363 reg = <0 0x10>; 380 reg = <0 0x100>;
364 }; 381 };
365 }; 382 };
366 383
diff --git a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
new file mode 100644
index 000000000000..e3585daafdd6
--- /dev/null
+++ b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
@@ -0,0 +1,48 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the iWave-RZ/G1C single board computer
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 */
7
8/dts-v1/;
9#include "r8a77470.dtsi"
10/ {
11 model = "iWave iW-RainboW-G23S single board computer based on RZ/G1C";
12 compatible = "iwave,g23s", "renesas,r8a77470";
13
14 aliases {
15 ethernet0 = &avb;
16 serial1 = &scif1;
17 };
18
19 chosen {
20 bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
21 stdout-path = "serial1:115200n8";
22 };
23
24 memory@40000000 {
25 device_type = "memory";
26 reg = <0 0x40000000 0 0x20000000>;
27 };
28};
29
30&avb {
31 phy-handle = <&phy3>;
32 phy-mode = "gmii";
33 renesas,no-ether-link;
34 status = "okay";
35
36 phy3: ethernet-phy@3 {
37 reg = <3>;
38 micrel,led-mode = <1>;
39 };
40};
41
42&extal_clk {
43 clock-frequency = <20000000>;
44};
45
46&scif1 {
47 status = "okay";
48};
diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi
new file mode 100644
index 000000000000..c85032f9605b
--- /dev/null
+++ b/arch/arm/boot/dts/r8a77470.dtsi
@@ -0,0 +1,336 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the r8a77470 SoC
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/irq.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/clock/renesas-cpg-mssr.h>
11/ {
12 compatible = "renesas,r8a77470";
13 #address-cells = <2>;
14 #size-cells = <2>;
15
16 cpus {
17 #address-cells = <1>;
18 #size-cells = <0>;
19
20 cpu0: cpu@0 {
21 device_type = "cpu";
22 compatible = "arm,cortex-a7";
23 reg = <0>;
24 clock-frequency = <1000000000>;
25 clocks = <&cpg CPG_CORE 0>;
26 power-domains = <&sysc 5>;
27 next-level-cache = <&L2_CA7>;
28 };
29
30
31 L2_CA7: cache-controller-0 {
32 compatible = "cache";
33 cache-unified;
34 cache-level = <2>;
35 power-domains = <&sysc 21>;
36 };
37 };
38
39 /* External root clock */
40 extal_clk: extal {
41 compatible = "fixed-clock";
42 #clock-cells = <0>;
43 /* This value must be overridden by the board. */
44 clock-frequency = <0>;
45 };
46
47 /* External SCIF clock */
48 scif_clk: scif {
49 compatible = "fixed-clock";
50 #clock-cells = <0>;
51 /* This value must be overridden by the board. */
52 clock-frequency = <0>;
53 };
54
55 soc {
56 compatible = "simple-bus";
57 interrupt-parent = <&gic>;
58
59 #address-cells = <2>;
60 #size-cells = <2>;
61 ranges;
62
63 cpg: clock-controller@e6150000 {
64 compatible = "renesas,r8a77470-cpg-mssr";
65 reg = <0 0xe6150000 0 0x1000>;
66 clocks = <&extal_clk>, <&usb_extal_clk>;
67 clock-names = "extal", "usb_extal";
68 #clock-cells = <2>;
69 #power-domain-cells = <0>;
70 #reset-cells = <1>;
71 };
72
73 rst: reset-controller@e6160000 {
74 compatible = "renesas,r8a77470-rst";
75 reg = <0 0xe6160000 0 0x100>;
76 };
77
78 sysc: system-controller@e6180000 {
79 compatible = "renesas,r8a77470-sysc";
80 reg = <0 0xe6180000 0 0x200>;
81 #power-domain-cells = <1>;
82 };
83
84 irqc: interrupt-controller@e61c0000 {
85 compatible = "renesas,irqc-r8a77470", "renesas,irqc";
86 #interrupt-cells = <2>;
87 interrupt-controller;
88 reg = <0 0xe61c0000 0 0x200>;
89 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
90 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
91 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
92 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
93 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
94 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
95 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
96 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
97 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
98 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
99 clocks = <&cpg CPG_MOD 407>;
100 power-domains = <&sysc 32>;
101 resets = <&cpg 407>;
102 };
103
104 icram0: sram@e63a0000 {
105 compatible = "mmio-sram";
106 reg = <0 0xe63a0000 0 0x12000>;
107 };
108
109 icram1: sram@e63c0000 {
110 compatible = "mmio-sram";
111 reg = <0 0xe63c0000 0 0x1000>;
112 #address-cells = <1>;
113 #size-cells = <1>;
114 ranges = <0 0 0xe63c0000 0x1000>;
115
116 smp-sram@0 {
117 compatible = "renesas,smp-sram";
118 reg = <0 0x100>;
119 };
120 };
121
122 icram2: sram@e6300000 {
123 compatible = "mmio-sram";
124 reg = <0 0xe6300000 0 0x20000>;
125 };
126
127 dmac0: dma-controller@e6700000 {
128 compatible = "renesas,dmac-r8a77470",
129 "renesas,rcar-dmac";
130 reg = <0 0xe6700000 0 0x20000>;
131 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
132 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
133 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
134 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
135 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
136 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
137 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
138 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
139 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
140 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
141 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
142 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
143 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
144 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
145 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
146 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
147 interrupt-names = "error",
148 "ch0", "ch1", "ch2", "ch3",
149 "ch4", "ch5", "ch6", "ch7",
150 "ch8", "ch9", "ch10", "ch11",
151 "ch12", "ch13", "ch14";
152 clocks = <&cpg CPG_MOD 219>;
153 clock-names = "fck";
154 power-domains = <&sysc 32>;
155 resets = <&cpg 219>;
156 #dma-cells = <1>;
157 dma-channels = <15>;
158 };
159
160 dmac1: dma-controller@e6720000 {
161 compatible = "renesas,dmac-r8a77470",
162 "renesas,rcar-dmac";
163 reg = <0 0xe6720000 0 0x20000>;
164 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
165 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
166 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
167 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
168 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
169 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
170 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
171 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
172 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
173 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
174 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
175 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
176 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
177 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
178 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
179 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
180 interrupt-names = "error",
181 "ch0", "ch1", "ch2", "ch3",
182 "ch4", "ch5", "ch6", "ch7",
183 "ch8", "ch9", "ch10", "ch11",
184 "ch12", "ch13", "ch14";
185 clocks = <&cpg CPG_MOD 218>;
186 clock-names = "fck";
187 power-domains = <&sysc 32>;
188 resets = <&cpg 218>;
189 #dma-cells = <1>;
190 dma-channels = <15>;
191 };
192
193 avb: ethernet@e6800000 {
194 compatible = "renesas,etheravb-r8a77470",
195 "renesas,etheravb-rcar-gen2";
196 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
197 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
198 clocks = <&cpg CPG_MOD 812>;
199 power-domains = <&sysc 32>;
200 resets = <&cpg 812>;
201 #address-cells = <1>;
202 #size-cells = <0>;
203 status = "disabled";
204 };
205
206 scif0: serial@e6e60000 {
207 compatible = "renesas,scif-r8a77470",
208 "renesas,rcar-gen2-scif", "renesas,scif";
209 reg = <0 0xe6e60000 0 0x40>;
210 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
211 clocks = <&cpg CPG_MOD 721>,
212 <&cpg CPG_CORE 5>, <&scif_clk>;
213 clock-names = "fck", "brg_int", "scif_clk";
214 dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
215 <&dmac1 0x29>, <&dmac1 0x2a>;
216 dma-names = "tx", "rx", "tx", "rx";
217 power-domains = <&sysc 32>;
218 resets = <&cpg 721>;
219 status = "disabled";
220 };
221
222 scif1: serial@e6e68000 {
223 compatible = "renesas,scif-r8a77470",
224 "renesas,rcar-gen2-scif", "renesas,scif";
225 reg = <0 0xe6e68000 0 0x40>;
226 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
227 clocks = <&cpg CPG_MOD 720>,
228 <&cpg CPG_CORE 5>, <&scif_clk>;
229 clock-names = "fck", "brg_int", "scif_clk";
230 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
231 <&dmac1 0x2d>, <&dmac1 0x2e>;
232 dma-names = "tx", "rx", "tx", "rx";
233 power-domains = <&sysc 32>;
234 resets = <&cpg 720>;
235 status = "disabled";
236 };
237
238 scif2: serial@e6e58000 {
239 compatible = "renesas,scif-r8a77470",
240 "renesas,rcar-gen2-scif", "renesas,scif";
241 reg = <0 0xe6e58000 0 0x40>;
242 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
243 clocks = <&cpg CPG_MOD 719>,
244 <&cpg CPG_CORE 5>, <&scif_clk>;
245 clock-names = "fck", "brg_int", "scif_clk";
246 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
247 <&dmac1 0x2b>, <&dmac1 0x2c>;
248 dma-names = "tx", "rx", "tx", "rx";
249 power-domains = <&sysc 32>;
250 resets = <&cpg 719>;
251 status = "disabled";
252 };
253
254 scif3: serial@e6ea8000 {
255 compatible = "renesas,scif-r8a77470",
256 "renesas,rcar-gen2-scif", "renesas,scif";
257 reg = <0 0xe6ea8000 0 0x40>;
258 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
259 clocks = <&cpg CPG_MOD 718>,
260 <&cpg CPG_CORE 5>, <&scif_clk>;
261 clock-names = "fck", "brg_int", "scif_clk";
262 dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
263 <&dmac1 0x2f>, <&dmac1 0x30>;
264 dma-names = "tx", "rx", "tx", "rx";
265 power-domains = <&sysc 32>;
266 resets = <&cpg 718>;
267 status = "disabled";
268 };
269
270 scif4: serial@e6ee0000 {
271 compatible = "renesas,scif-r8a77470",
272 "renesas,rcar-gen2-scif", "renesas,scif";
273 reg = <0 0xe6ee0000 0 0x40>;
274 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
275 clocks = <&cpg CPG_MOD 715>,
276 <&cpg CPG_CORE 5>, <&scif_clk>;
277 clock-names = "fck", "brg_int", "scif_clk";
278 dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
279 <&dmac1 0xfb>, <&dmac1 0xfc>;
280 dma-names = "tx", "rx", "tx", "rx";
281 power-domains = <&sysc 32>;
282 resets = <&cpg 715>;
283 status = "disabled";
284 };
285
286 scif5: serial@e6ee8000 {
287 compatible = "renesas,scif-r8a77470",
288 "renesas,rcar-gen2-scif", "renesas,scif";
289 reg = <0 0xe6ee8000 0 0x40>;
290 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
291 clocks = <&cpg CPG_MOD 714>,
292 <&cpg CPG_CORE 5>, <&scif_clk>;
293 clock-names = "fck", "brg_int", "scif_clk";
294 dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
295 <&dmac1 0xfd>, <&dmac1 0xfe>;
296 dma-names = "tx", "rx", "tx", "rx";
297 power-domains = <&sysc 32>;
298 resets = <&cpg 714>;
299 status = "disabled";
300 };
301
302 gic: interrupt-controller@f1001000 {
303 compatible = "arm,gic-400";
304 #interrupt-cells = <3>;
305 #address-cells = <0>;
306 interrupt-controller;
307 reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>,
308 <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>;
309 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
310 clocks = <&cpg CPG_MOD 408>;
311 clock-names = "clk";
312 power-domains = <&sysc 32>;
313 resets = <&cpg 408>;
314 };
315
316 prr: chipid@ff000044 {
317 compatible = "renesas,prr";
318 reg = <0 0xff000044 0 4>;
319 };
320 };
321
322 timer {
323 compatible = "arm,armv7-timer";
324 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
325 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
326 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
327 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
328 };
329
330 /* External USB clock - can be overridden by the board */
331 usb_extal_clk: usb_extal {
332 compatible = "fixed-clock";
333 #clock-cells = <0>;
334 clock-frequency = <48000000>;
335 };
336};
diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts
index 063fdb65dc60..d1e582b0ab66 100644
--- a/arch/arm/boot/dts/r8a7790-lager.dts
+++ b/arch/arm/boot/dts/r8a7790-lager.dts
@@ -890,9 +890,6 @@
890 status = "okay"; 890 status = "okay";
891 891
892 port { 892 port {
893 #address-cells = <1>;
894 #size-cells = <0>;
895
896 vin1ep0: endpoint { 893 vin1ep0: endpoint {
897 remote-endpoint = <&adv7180>; 894 remote-endpoint = <&adv7180>;
898 bus-width = <8>; 895 bus-width = <8>;
@@ -917,6 +914,11 @@
917 }; 914 };
918}; 915};
919 916
917&rwdt {
918 timeout-sec = <60>;
919 status = "okay";
920};
921
920&ssi1 { 922&ssi1 {
921 shared-pin; 923 shared-pin;
922}; 924};
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index e4367cecad18..ae97ec146260 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -202,6 +202,24 @@
202 clock-frequency = <0>; 202 clock-frequency = <0>;
203 }; 203 };
204 204
205 pmu-0 {
206 compatible = "arm,cortex-a15-pmu";
207 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
208 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
209 <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
210 <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
211 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
212 };
213
214 pmu-1 {
215 compatible = "arm,cortex-a7-pmu";
216 interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
217 <&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
218 <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
219 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
220 interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
221 };
222
205 /* External SCIF clock */ 223 /* External SCIF clock */
206 scif_clk: scif { 224 scif_clk: scif {
207 compatible = "fixed-clock"; 225 compatible = "fixed-clock";
@@ -218,6 +236,16 @@
218 #size-cells = <2>; 236 #size-cells = <2>;
219 ranges; 237 ranges;
220 238
239 rwdt: watchdog@e6020000 {
240 compatible = "renesas,r8a7790-wdt",
241 "renesas,rcar-gen2-wdt";
242 reg = <0 0xe6020000 0 0x0c>;
243 clocks = <&cpg CPG_MOD 402>;
244 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
245 resets = <&cpg 402>;
246 status = "disabled";
247 };
248
221 gpio0: gpio@e6050000 { 249 gpio0: gpio@e6050000 {
222 compatible = "renesas,gpio-r8a7790", 250 compatible = "renesas,gpio-r8a7790",
223 "renesas,rcar-gen2-gpio"; 251 "renesas,rcar-gen2-gpio";
@@ -443,7 +471,7 @@
443 471
444 smp-sram@0 { 472 smp-sram@0 {
445 compatible = "renesas,smp-sram"; 473 compatible = "renesas,smp-sram";
446 reg = <0 0x10>; 474 reg = <0 0x100>;
447 }; 475 };
448 }; 476 };
449 477
@@ -1544,7 +1572,7 @@
1544 interrupt-controller; 1572 interrupt-controller;
1545 reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>, 1573 reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>,
1546 <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; 1574 <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>;
1547 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1575 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
1548 clocks = <&cpg CPG_MOD 408>; 1576 clocks = <&cpg CPG_MOD 408>;
1549 clock-names = "clk"; 1577 clock-names = "clk";
1550 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; 1578 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
@@ -1615,6 +1643,33 @@
1615 resets = <&cpg 127>; 1643 resets = <&cpg 127>;
1616 }; 1644 };
1617 1645
1646 fdp1@fe940000 {
1647 compatible = "renesas,fdp1";
1648 reg = <0 0xfe940000 0 0x2400>;
1649 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
1650 clocks = <&cpg CPG_MOD 119>;
1651 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1652 resets = <&cpg 119>;
1653 };
1654
1655 fdp1@fe944000 {
1656 compatible = "renesas,fdp1";
1657 reg = <0 0xfe944000 0 0x2400>;
1658 interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
1659 clocks = <&cpg CPG_MOD 118>;
1660 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1661 resets = <&cpg 118>;
1662 };
1663
1664 fdp1@fe948000 {
1665 compatible = "renesas,fdp1";
1666 reg = <0 0xfe948000 0 0x2400>;
1667 interrupts = <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
1668 clocks = <&cpg CPG_MOD 117>;
1669 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1670 resets = <&cpg 117>;
1671 };
1672
1618 jpu: jpeg-codec@fe980000 { 1673 jpu: jpeg-codec@fe980000 {
1619 compatible = "renesas,jpu-r8a7790", 1674 compatible = "renesas,jpu-r8a7790",
1620 "renesas,rcar-gen2-jpu"; 1675 "renesas,rcar-gen2-jpu";
@@ -1724,10 +1779,10 @@
1724 1779
1725 timer { 1780 timer {
1726 compatible = "arm,armv7-timer"; 1781 compatible = "arm,armv7-timer";
1727 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1782 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1728 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1783 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1729 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1784 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1730 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1785 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
1731 }; 1786 };
1732 1787
1733 /* External USB clock - can be overridden by the board */ 1788 /* External USB clock - can be overridden by the board */
diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts
index f40321a1c917..68e8272cb90e 100644
--- a/arch/arm/boot/dts/r8a7791-koelsch.dts
+++ b/arch/arm/boot/dts/r8a7791-koelsch.dts
@@ -637,6 +637,11 @@
637 status = "okay"; 637 status = "okay";
638}; 638};
639 639
640&rwdt {
641 timeout-sec = <60>;
642 status = "okay";
643};
644
640&sata0 { 645&sata0 {
641 status = "okay"; 646 status = "okay";
642}; 647};
@@ -844,9 +849,6 @@
844 pinctrl-names = "default"; 849 pinctrl-names = "default";
845 850
846 port { 851 port {
847 #address-cells = <1>;
848 #size-cells = <0>;
849
850 vin0ep2: endpoint { 852 vin0ep2: endpoint {
851 remote-endpoint = <&adv7612_out>; 853 remote-endpoint = <&adv7612_out>;
852 bus-width = <24>; 854 bus-width = <24>;
@@ -865,9 +867,6 @@
865 pinctrl-names = "default"; 867 pinctrl-names = "default";
866 868
867 port { 869 port {
868 #address-cells = <1>;
869 #size-cells = <0>;
870
871 vin1ep: endpoint { 870 vin1ep: endpoint {
872 remote-endpoint = <&adv7180>; 871 remote-endpoint = <&adv7180>;
873 bus-width = <8>; 872 bus-width = <8>;
diff --git a/arch/arm/boot/dts/r8a7791-porter.dts b/arch/arm/boot/dts/r8a7791-porter.dts
index c14e6fe9e4f6..876d38f46367 100644
--- a/arch/arm/boot/dts/r8a7791-porter.dts
+++ b/arch/arm/boot/dts/r8a7791-porter.dts
@@ -386,9 +386,6 @@
386 pinctrl-names = "default"; 386 pinctrl-names = "default";
387 387
388 port { 388 port {
389 #address-cells = <1>;
390 #size-cells = <0>;
391
392 vin0ep: endpoint { 389 vin0ep: endpoint {
393 remote-endpoint = <&adv7180>; 390 remote-endpoint = <&adv7180>;
394 bus-width = <8>; 391 bus-width = <8>;
@@ -471,6 +468,11 @@
471 }; 468 };
472}; 469};
473 470
471&rwdt {
472 timeout-sec = <60>;
473 status = "okay";
474};
475
474&ssi1 { 476&ssi1 {
475 shared-pin; 477 shared-pin;
476}; 478};
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index f11dab71b03a..828ad78c3337 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -126,6 +126,13 @@
126 clock-frequency = <0>; 126 clock-frequency = <0>;
127 }; 127 };
128 128
129 pmu {
130 compatible = "arm,cortex-a15-pmu";
131 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
132 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
133 interrupt-affinity = <&cpu0>, <&cpu1>;
134 };
135
129 /* External SCIF clock */ 136 /* External SCIF clock */
130 scif_clk: scif { 137 scif_clk: scif {
131 compatible = "fixed-clock"; 138 compatible = "fixed-clock";
@@ -142,6 +149,16 @@
142 #size-cells = <2>; 149 #size-cells = <2>;
143 ranges; 150 ranges;
144 151
152 rwdt: watchdog@e6020000 {
153 compatible = "renesas,r8a7791-wdt",
154 "renesas,rcar-gen2-wdt";
155 reg = <0 0xe6020000 0 0x0c>;
156 clocks = <&cpg CPG_MOD 402>;
157 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
158 resets = <&cpg 402>;
159 status = "disabled";
160 };
161
145 gpio0: gpio@e6050000 { 162 gpio0: gpio@e6050000 {
146 compatible = "renesas,gpio-r8a7791", 163 compatible = "renesas,gpio-r8a7791",
147 "renesas,rcar-gen2-gpio"; 164 "renesas,rcar-gen2-gpio";
@@ -407,7 +424,7 @@
407 424
408 smp-sram@0 { 425 smp-sram@0 {
409 compatible = "renesas,smp-sram"; 426 compatible = "renesas,smp-sram";
410 reg = <0 0x10>; 427 reg = <0 0x100>;
411 }; 428 };
412 }; 429 };
413 430
@@ -1621,6 +1638,24 @@
1621 resets = <&cpg 127>; 1638 resets = <&cpg 127>;
1622 }; 1639 };
1623 1640
1641 fdp1@fe940000 {
1642 compatible = "renesas,fdp1";
1643 reg = <0 0xfe940000 0 0x2400>;
1644 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
1645 clocks = <&cpg CPG_MOD 119>;
1646 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
1647 resets = <&cpg 119>;
1648 };
1649
1650 fdp1@fe944000 {
1651 compatible = "renesas,fdp1";
1652 reg = <0 0xfe944000 0 0x2400>;
1653 interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
1654 clocks = <&cpg CPG_MOD 118>;
1655 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
1656 resets = <&cpg 118>;
1657 };
1658
1624 jpu: jpeg-codec@fe980000 { 1659 jpu: jpeg-codec@fe980000 {
1625 compatible = "renesas,jpu-r8a7791", 1660 compatible = "renesas,jpu-r8a7791",
1626 "renesas,rcar-gen2-jpu"; 1661 "renesas,rcar-gen2-jpu";
diff --git a/arch/arm/boot/dts/r8a7792-blanche.dts b/arch/arm/boot/dts/r8a7792-blanche.dts
index 9b67dca6c9ef..04fb70931b3b 100644
--- a/arch/arm/boot/dts/r8a7792-blanche.dts
+++ b/arch/arm/boot/dts/r8a7792-blanche.dts
@@ -239,6 +239,11 @@
239 }; 239 };
240}; 240};
241 241
242&rwdt {
243 timeout-sec = <60>;
244 status = "okay";
245};
246
242&scif0 { 247&scif0 {
243 pinctrl-0 = <&scif0_pins>; 248 pinctrl-0 = <&scif0_pins>;
244 pinctrl-names = "default"; 249 pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/r8a7792-wheat.dts b/arch/arm/boot/dts/r8a7792-wheat.dts
index b9471b67b728..db01de7a3811 100644
--- a/arch/arm/boot/dts/r8a7792-wheat.dts
+++ b/arch/arm/boot/dts/r8a7792-wheat.dts
@@ -168,6 +168,11 @@
168 }; 168 };
169}; 169};
170 170
171&rwdt {
172 timeout-sec = <60>;
173 status = "okay";
174};
175
171&scif0 { 176&scif0 {
172 pinctrl-0 = <&scif0_pins>; 177 pinctrl-0 = <&scif0_pins>;
173 pinctrl-names = "default"; 178 pinctrl-names = "default";
@@ -240,9 +245,15 @@
240 status = "okay"; 245 status = "okay";
241 clock-frequency = <400000>; 246 clock-frequency = <400000>;
242 247
248 /*
249 * The adv75xx resets its addresses to defaults during low power mode.
250 * Because we have two ADV7513 devices on the same bus, we must change
251 * both of them away from the defaults so that they do not conflict.
252 */
243 hdmi@3d { 253 hdmi@3d {
244 compatible = "adi,adv7513"; 254 compatible = "adi,adv7513";
245 reg = <0x3d>; 255 reg = <0x3d>, <0x2d>, <0x4d>, <0x5d>;
256 reg-names = "main", "cec", "edid", "packet";
246 257
247 adi,input-depth = <8>; 258 adi,input-depth = <8>;
248 adi,input-colorspace = "rgb"; 259 adi,input-colorspace = "rgb";
@@ -272,7 +283,8 @@
272 283
273 hdmi@39 { 284 hdmi@39 {
274 compatible = "adi,adv7513"; 285 compatible = "adi,adv7513";
275 reg = <0x39>; 286 reg = <0x39>, <0x29>, <0x49>, <0x59>;
287 reg-names = "main", "cec", "edid", "packet";
276 288
277 adi,input-depth = <8>; 289 adi,input-depth = <8>;
278 adi,input-colorspace = "rgb"; 290 adi,input-colorspace = "rgb";
diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi
index 268987ff0201..f44257dd86f6 100644
--- a/arch/arm/boot/dts/r8a7792.dtsi
+++ b/arch/arm/boot/dts/r8a7792.dtsi
@@ -85,6 +85,13 @@
85 clock-frequency = <0>; 85 clock-frequency = <0>;
86 }; 86 };
87 87
88 pmu {
89 compatible = "arm,cortex-a15-pmu";
90 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
91 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
92 interrupt-affinity = <&cpu0>, <&cpu1>;
93 };
94
88 /* External SCIF clock */ 95 /* External SCIF clock */
89 scif_clk: scif { 96 scif_clk: scif {
90 compatible = "fixed-clock"; 97 compatible = "fixed-clock";
@@ -101,6 +108,16 @@
101 #size-cells = <2>; 108 #size-cells = <2>;
102 ranges; 109 ranges;
103 110
111 rwdt: watchdog@e6020000 {
112 compatible = "renesas,r8a7792-wdt",
113 "renesas,rcar-gen2-wdt";
114 reg = <0 0xe6020000 0 0x0c>;
115 clocks = <&cpg CPG_MOD 402>;
116 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
117 resets = <&cpg 402>;
118 status = "disabled";
119 };
120
104 gpio0: gpio@e6050000 { 121 gpio0: gpio@e6050000 {
105 compatible = "renesas,gpio-r8a7792", 122 compatible = "renesas,gpio-r8a7792",
106 "renesas,rcar-gen2-gpio"; 123 "renesas,rcar-gen2-gpio";
@@ -341,7 +358,7 @@
341 358
342 smp-sram@0 { 359 smp-sram@0 {
343 compatible = "renesas,smp-sram"; 360 compatible = "renesas,smp-sram";
344 reg = <0 0x10>; 361 reg = <0 0x100>;
345 }; 362 };
346 }; 363 };
347 364
diff --git a/arch/arm/boot/dts/r8a7793-gose.dts b/arch/arm/boot/dts/r8a7793-gose.dts
index 9ed6961f2d9a..ec94e2402bdf 100644
--- a/arch/arm/boot/dts/r8a7793-gose.dts
+++ b/arch/arm/boot/dts/r8a7793-gose.dts
@@ -595,6 +595,11 @@
595 status = "okay"; 595 status = "okay";
596}; 596};
597 597
598&rwdt {
599 timeout-sec = <60>;
600 status = "okay";
601};
602
598&scif0 { 603&scif0 {
599 pinctrl-0 = <&scif0_pins>; 604 pinctrl-0 = <&scif0_pins>;
600 pinctrl-names = "default"; 605 pinctrl-names = "default";
@@ -754,9 +759,6 @@
754 pinctrl-names = "default"; 759 pinctrl-names = "default";
755 760
756 port { 761 port {
757 #address-cells = <1>;
758 #size-cells = <0>;
759
760 vin0ep2: endpoint { 762 vin0ep2: endpoint {
761 remote-endpoint = <&adv7612_out>; 763 remote-endpoint = <&adv7612_out>;
762 bus-width = <24>; 764 bus-width = <24>;
@@ -776,9 +778,6 @@
776 status = "okay"; 778 status = "okay";
777 779
778 port { 780 port {
779 #address-cells = <1>;
780 #size-cells = <0>;
781
782 vin1ep: endpoint { 781 vin1ep: endpoint {
783 remote-endpoint = <&adv7180_out>; 782 remote-endpoint = <&adv7180_out>;
784 bus-width = <8>; 783 bus-width = <8>;
diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi
index f9c5a557107d..4c29de510481 100644
--- a/arch/arm/boot/dts/r8a7793.dtsi
+++ b/arch/arm/boot/dts/r8a7793.dtsi
@@ -110,6 +110,13 @@
110 clock-frequency = <0>; 110 clock-frequency = <0>;
111 }; 111 };
112 112
113 pmu {
114 compatible = "arm,cortex-a15-pmu";
115 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
116 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
117 interrupt-affinity = <&cpu0>, <&cpu1>;
118 };
119
113 /* External SCIF clock */ 120 /* External SCIF clock */
114 scif_clk: scif { 121 scif_clk: scif {
115 compatible = "fixed-clock"; 122 compatible = "fixed-clock";
@@ -126,6 +133,16 @@
126 #size-cells = <2>; 133 #size-cells = <2>;
127 ranges; 134 ranges;
128 135
136 rwdt: watchdog@e6020000 {
137 compatible = "renesas,r8a7793-wdt",
138 "renesas,rcar-gen2-wdt";
139 reg = <0 0xe6020000 0 0x0c>;
140 clocks = <&cpg CPG_MOD 402>;
141 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
142 resets = <&cpg 402>;
143 status = "disabled";
144 };
145
129 gpio0: gpio@e6050000 { 146 gpio0: gpio@e6050000 {
130 compatible = "renesas,gpio-r8a7793", 147 compatible = "renesas,gpio-r8a7793",
131 "renesas,rcar-gen2-gpio"; 148 "renesas,rcar-gen2-gpio";
@@ -392,7 +409,7 @@
392 409
393 smp-sram@0 { 410 smp-sram@0 {
394 compatible = "renesas,smp-sram"; 411 compatible = "renesas,smp-sram";
395 reg = <0 0x10>; 412 reg = <0 0x100>;
396 }; 413 };
397 }; 414 };
398 415
@@ -1290,6 +1307,24 @@
1290 resets = <&cpg 408>; 1307 resets = <&cpg 408>;
1291 }; 1308 };
1292 1309
1310 fdp1@fe940000 {
1311 compatible = "renesas,fdp1";
1312 reg = <0 0xfe940000 0 0x2400>;
1313 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
1314 clocks = <&cpg CPG_MOD 119>;
1315 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
1316 resets = <&cpg 119>;
1317 };
1318
1319 fdp1@fe944000 {
1320 compatible = "renesas,fdp1";
1321 reg = <0 0xfe944000 0 0x2400>;
1322 interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
1323 clocks = <&cpg CPG_MOD 118>;
1324 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
1325 resets = <&cpg 118>;
1326 };
1327
1293 du: display@feb00000 { 1328 du: display@feb00000 {
1294 compatible = "renesas,du-r8a7793"; 1329 compatible = "renesas,du-r8a7793";
1295 reg = <0 0xfeb00000 0 0x40000>, 1330 reg = <0 0xfeb00000 0 0x40000>,
diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts
index 26a883484ea8..e17027532941 100644
--- a/arch/arm/boot/dts/r8a7794-alt.dts
+++ b/arch/arm/boot/dts/r8a7794-alt.dts
@@ -181,6 +181,12 @@
181 }; 181 };
182 }; 182 };
183 }; 183 };
184
185 eeprom@50 {
186 compatible = "renesas,r1ex24002", "atmel,24c02";
187 reg = <0x50>;
188 pagesize = <16>;
189 };
184 }; 190 };
185 191
186 /* 192 /*
@@ -330,6 +336,11 @@
330 status = "okay"; 336 status = "okay";
331}; 337};
332 338
339&rwdt {
340 timeout-sec = <60>;
341 status = "okay";
342};
343
333&sdhi0 { 344&sdhi0 {
334 pinctrl-0 = <&sdhi0_pins>; 345 pinctrl-0 = <&sdhi0_pins>;
335 pinctrl-1 = <&sdhi0_pins_uhs>; 346 pinctrl-1 = <&sdhi0_pins_uhs>;
@@ -375,9 +386,6 @@
375 pinctrl-names = "default"; 386 pinctrl-names = "default";
376 387
377 port { 388 port {
378 #address-cells = <1>;
379 #size-cells = <0>;
380
381 vin0ep: endpoint { 389 vin0ep: endpoint {
382 remote-endpoint = <&adv7180>; 390 remote-endpoint = <&adv7180>;
383 bus-width = <8>; 391 bus-width = <8>;
diff --git a/arch/arm/boot/dts/r8a7794-silk.dts b/arch/arm/boot/dts/r8a7794-silk.dts
index 351cb3b3d966..7808aaee6644 100644
--- a/arch/arm/boot/dts/r8a7794-silk.dts
+++ b/arch/arm/boot/dts/r8a7794-silk.dts
@@ -475,9 +475,6 @@
475 pinctrl-names = "default"; 475 pinctrl-names = "default";
476 476
477 port { 477 port {
478 #address-cells = <1>;
479 #size-cells = <0>;
480
481 vin0ep: endpoint { 478 vin0ep: endpoint {
482 remote-endpoint = <&adv7180>; 479 remote-endpoint = <&adv7180>;
483 bus-width = <8>; 480 bus-width = <8>;
@@ -540,6 +537,11 @@
540 }; 537 };
541}; 538};
542 539
540&rwdt {
541 timeout-sec = <60>;
542 status = "okay";
543};
544
543&ssi1 { 545&ssi1 {
544 shared-pin; 546 shared-pin;
545}; 547};
diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
index d588efa6aeaa..736196903d22 100644
--- a/arch/arm/boot/dts/r8a7794.dtsi
+++ b/arch/arm/boot/dts/r8a7794.dtsi
@@ -103,6 +103,13 @@
103 clock-frequency = <0>; 103 clock-frequency = <0>;
104 }; 104 };
105 105
106 pmu {
107 compatible = "arm,cortex-a7-pmu";
108 interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
109 <&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
110 interrupt-affinity = <&cpu0>, <&cpu1>;
111 };
112
106 /* External SCIF clock */ 113 /* External SCIF clock */
107 scif_clk: scif { 114 scif_clk: scif {
108 compatible = "fixed-clock"; 115 compatible = "fixed-clock";
@@ -119,6 +126,16 @@
119 #size-cells = <2>; 126 #size-cells = <2>;
120 ranges; 127 ranges;
121 128
129 rwdt: watchdog@e6020000 {
130 compatible = "renesas,r8a7794-wdt",
131 "renesas,rcar-gen2-wdt";
132 reg = <0 0xe6020000 0 0x0c>;
133 clocks = <&cpg CPG_MOD 402>;
134 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
135 resets = <&cpg 402>;
136 status = "disabled";
137 };
138
122 gpio0: gpio@e6050000 { 139 gpio0: gpio@e6050000 {
123 compatible = "renesas,gpio-r8a7794", 140 compatible = "renesas,gpio-r8a7794",
124 "renesas,rcar-gen2-gpio"; 141 "renesas,rcar-gen2-gpio";
@@ -348,7 +365,7 @@
348 365
349 smp-sram@0 { 366 smp-sram@0 {
350 compatible = "renesas,smp-sram"; 367 compatible = "renesas,smp-sram";
351 reg = <0 0x10>; 368 reg = <0 0x100>;
352 }; 369 };
353 }; 370 };
354 371
@@ -1323,6 +1340,15 @@
1323 resets = <&cpg 128>; 1340 resets = <&cpg 128>;
1324 }; 1341 };
1325 1342
1343 fdp1@fe940000 {
1344 compatible = "renesas,fdp1";
1345 reg = <0 0xfe940000 0 0x2400>;
1346 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
1347 clocks = <&cpg CPG_MOD 119>;
1348 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
1349 resets = <&cpg 119>;
1350 };
1351
1326 du: display@feb00000 { 1352 du: display@feb00000 {
1327 compatible = "renesas,du-r8a7794"; 1353 compatible = "renesas,du-r8a7794";
1328 reg = <0 0xfeb00000 0 0x40000>; 1354 reg = <0 0xfeb00000 0 0x40000>;
diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi
index 914a7c2a584f..c953648a5f41 100644
--- a/arch/arm/boot/dts/sh73a0.dtsi
+++ b/arch/arm/boot/dts/sh73a0.dtsi
@@ -22,7 +22,7 @@
22 #address-cells = <1>; 22 #address-cells = <1>;
23 #size-cells = <0>; 23 #size-cells = <0>;
24 24
25 cpu@0 { 25 cpu0: cpu@0 {
26 device_type = "cpu"; 26 device_type = "cpu";
27 compatible = "arm,cortex-a9"; 27 compatible = "arm,cortex-a9";
28 reg = <0>; 28 reg = <0>;
@@ -31,7 +31,7 @@
31 power-domains = <&pd_a2sl>; 31 power-domains = <&pd_a2sl>;
32 next-level-cache = <&L2>; 32 next-level-cache = <&L2>;
33 }; 33 };
34 cpu@1 { 34 cpu1: cpu@1 {
35 device_type = "cpu"; 35 device_type = "cpu";
36 compatible = "arm,cortex-a9"; 36 compatible = "arm,cortex-a9";
37 reg = <1>; 37 reg = <1>;
@@ -91,6 +91,7 @@
91 compatible = "arm,cortex-a9-pmu"; 91 compatible = "arm,cortex-a9-pmu";
92 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 92 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
93 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 93 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
94 interrupt-affinity = <&cpu0>, <&cpu1>;
94 }; 95 };
95 96
96 cmt1: timer@e6138000 { 97 cmt1: timer@e6138000 {
@@ -336,7 +337,7 @@
336 GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 337 GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
337 clocks = <&mstp3_clks SH73A0_CLK_SDHI1>; 338 clocks = <&mstp3_clks SH73A0_CLK_SDHI1>;
338 power-domains = <&pd_a3sp>; 339 power-domains = <&pd_a3sp>;
339 toshiba,mmc-wrprotect-disable; 340 disable-wp;
340 cap-sd-highspeed; 341 cap-sd-highspeed;
341 status = "disabled"; 342 status = "disabled";
342 }; 343 };
@@ -348,7 +349,7 @@
348 GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 349 GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
349 clocks = <&mstp3_clks SH73A0_CLK_SDHI2>; 350 clocks = <&mstp3_clks SH73A0_CLK_SDHI2>;
350 power-domains = <&pd_a3sp>; 351 power-domains = <&pd_a3sp>;
351 toshiba,mmc-wrprotect-disable; 352 disable-wp;
352 cap-sd-highspeed; 353 cap-sd-highspeed;
353 status = "disabled"; 354 status = "disabled";
354 }; 355 };
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-25 05:55:11 -0400