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authorOlof Johansson <olof@lixom.net>2016-02-24 16:40:18 -0500
committerOlof Johansson <olof@lixom.net>2016-02-24 16:40:18 -0500
commit7fa12181b01d2dfa7ae02df14df85c08d151919c (patch)
treefb3e6b29901fb5c506cf627b4b9a9463374e7cc3
parent9a9f182606cb2fa4bd10a5a893623d44d5c8e11b (diff)
parent9fd9288ed0899f9e318a97d73e777d6d3357265e (diff)
Merge tag 'vexpress-for-v4.6/dt-updates' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into next/dt
Few updates for ARM VExpress/Juno platforms 1. GICv3 support on Foundation models 2. Support for Juno R2 board 3. Support for ARM HDLCD on all Juno platforms * tag 'vexpress-for-v4.6/dt-updates' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux: arm64: dts: Add HDLCD support on Juno platforms Documentation: drm: Add DT bindings for ARM HDLCD arm64: dts: Add support for Juno r2 board arm64: dts: move juno pcie-controller to base file arm64: dts: add .dts for GICv3 Foundation model arm64: dts: split Foundation model dts to put the GIC separately arm64: dts: Foundation model: increase GICC region to allow EOImode=1 arm64: dts: prepare foundation-v8.dts to cope with GICv3 Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat
-rw-r--r--Documentation/devicetree/bindings/arm/arm-boards1
-rw-r--r--Documentation/devicetree/bindings/display/arm,hdlcd.txt79
-rw-r--r--arch/arm64/boot/dts/arm/Makefile4
-rw-r--r--arch/arm64/boot/dts/arm/foundation-v8-gicv3.dts30
-rw-r--r--arch/arm64/boot/dts/arm/foundation-v8.dts227
-rw-r--r--arch/arm64/boot/dts/arm/foundation-v8.dtsi228
-rw-r--r--arch/arm64/boot/dts/arm/juno-base.dtsi68
-rw-r--r--arch/arm64/boot/dts/arm/juno-r1.dts25
-rw-r--r--arch/arm64/boot/dts/arm/juno-r2.dts183
9 files changed, 595 insertions, 250 deletions
diff --git a/Documentation/devicetree/bindings/arm/arm-boards b/Documentation/devicetree/bindings/arm/arm-boards
index 1a709970e7f7..70601a58c433 100644
--- a/Documentation/devicetree/bindings/arm/arm-boards
+++ b/Documentation/devicetree/bindings/arm/arm-boards
@@ -180,6 +180,7 @@ described under the RS1 memory mapping.
180Required properties (in root node): 180Required properties (in root node):
181 compatible = "arm,juno"; /* For Juno r0 board */ 181 compatible = "arm,juno"; /* For Juno r0 board */
182 compatible = "arm,juno-r1"; /* For Juno r1 board */ 182 compatible = "arm,juno-r1"; /* For Juno r1 board */
183 compatible = "arm,juno-r2"; /* For Juno r2 board */
183 184
184Required nodes: 185Required nodes:
185The description for the board must include: 186The description for the board must include:
diff --git a/Documentation/devicetree/bindings/display/arm,hdlcd.txt b/Documentation/devicetree/bindings/display/arm,hdlcd.txt
new file mode 100644
index 000000000000..78bc24296f3e
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/arm,hdlcd.txt
@@ -0,0 +1,79 @@
1ARM HDLCD
2
3This is a display controller found on several development platforms produced
4by ARM Ltd and in more modern of its' Fast Models. The HDLCD is an RGB
5streamer that reads the data from a framebuffer and sends it to a single
6digital encoder (DVI or HDMI).
7
8Required properties:
9 - compatible: "arm,hdlcd"
10 - reg: Physical base address and length of the controller's registers.
11 - interrupts: One interrupt used by the display controller to notify the
12 interrupt controller when any of the interrupt sources programmed in
13 the interrupt mask register have activated.
14 - clocks: A list of phandle + clock-specifier pairs, one for each
15 entry in 'clock-names'.
16 - clock-names: A list of clock names. For HDLCD it should contain:
17 - "pxlclk" for the clock feeding the output PLL of the controller.
18
19Required sub-nodes:
20 - port: The HDLCD connection to an encoder chip. The connection is modeled
21 using the OF graph bindings specified in
22 Documentation/devicetree/bindings/graph.txt.
23
24Optional properties:
25 - memory-region: phandle to a node describing memory (see
26 Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt) to be
27 used for the framebuffer; if not present, the framebuffer may be located
28 anywhere in memory.
29
30
31Example:
32
33/ {
34 ...
35
36 hdlcd@2b000000 {
37 compatible = "arm,hdlcd";
38 reg = <0 0x2b000000 0 0x1000>;
39 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
40 clocks = <&oscclk5>;
41 clock-names = "pxlclk";
42 port {
43 hdlcd_output: endpoint@0 {
44 remote-endpoint = <&hdmi_enc_input>;
45 };
46 };
47 };
48
49 /* HDMI encoder on I2C bus */
50 i2c@7ffa0000 {
51 ....
52 hdmi-transmitter@70 {
53 compatible = ".....";
54 reg = <0x70>;
55 port@0 {
56 hdmi_enc_input: endpoint {
57 remote-endpoint = <&hdlcd_output>;
58 };
59
60 hdmi_enc_output: endpoint {
61 remote-endpoint = <&hdmi_1_port>;
62 };
63 };
64 };
65
66 };
67
68 hdmi1: connector@1 {
69 compatible = "hdmi-connector";
70 type = "a";
71 port {
72 hdmi_1_port: endpoint {
73 remote-endpoint = <&hdmi_enc_output>;
74 };
75 };
76 };
77
78 ...
79};
diff --git a/arch/arm64/boot/dts/arm/Makefile b/arch/arm64/boot/dts/arm/Makefile
index bb3c07209676..75cc2aa10101 100644
--- a/arch/arm64/boot/dts/arm/Makefile
+++ b/arch/arm64/boot/dts/arm/Makefile
@@ -1,5 +1,5 @@
1dtb-$(CONFIG_ARCH_VEXPRESS) += foundation-v8.dtb 1dtb-$(CONFIG_ARCH_VEXPRESS) += foundation-v8.dtb foundation-v8-gicv3.dtb
2dtb-$(CONFIG_ARCH_VEXPRESS) += juno.dtb juno-r1.dtb 2dtb-$(CONFIG_ARCH_VEXPRESS) += juno.dtb juno-r1.dtb juno-r2.dtb
3dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb 3dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb
4dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2f-1xv7-ca53x2.dtb 4dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2f-1xv7-ca53x2.dtb
5 5
diff --git a/arch/arm64/boot/dts/arm/foundation-v8-gicv3.dts b/arch/arm64/boot/dts/arm/foundation-v8-gicv3.dts
new file mode 100644
index 000000000000..35588dfa095c
--- /dev/null
+++ b/arch/arm64/boot/dts/arm/foundation-v8-gicv3.dts
@@ -0,0 +1,30 @@
1/*
2 * ARM Ltd.
3 *
4 * ARMv8 Foundation model DTS (GICv3 configuration)
5 */
6
7#include "foundation-v8.dtsi"
8
9/ {
10 gic: interrupt-controller@2f000000 {
11 compatible = "arm,gic-v3";
12 #interrupt-cells = <3>;
13 #address-cells = <2>;
14 #size-cells = <2>;
15 ranges;
16 interrupt-controller;
17 reg = <0x0 0x2f000000 0x0 0x10000>,
18 <0x0 0x2f100000 0x0 0x200000>,
19 <0x0 0x2c000000 0x0 0x2000>,
20 <0x0 0x2c010000 0x0 0x2000>,
21 <0x0 0x2c02f000 0x0 0x2000>;
22 interrupts = <1 9 4>;
23
24 its: its@2f020000 {
25 compatible = "arm,gic-v3-its";
26 msi-controller;
27 reg = <0x0 0x2f020000 0x0 0x20000>;
28 };
29 };
30};
diff --git a/arch/arm64/boot/dts/arm/foundation-v8.dts b/arch/arm64/boot/dts/arm/foundation-v8.dts
index 4eac8dcea423..71168077312d 100644
--- a/arch/arm64/boot/dts/arm/foundation-v8.dts
+++ b/arch/arm64/boot/dts/arm/foundation-v8.dts
@@ -1,240 +1,21 @@
1/* 1/*
2 * ARM Ltd. 2 * ARM Ltd.
3 * 3 *
4 * ARMv8 Foundation model DTS 4 * ARMv8 Foundation model DTS (GICv2 configuration)
5 */ 5 */
6 6
7/dts-v1/; 7#include "foundation-v8.dtsi"
8
9/memreserve/ 0x80000000 0x00010000;
10 8
11/ { 9/ {
12 model = "Foundation-v8A";
13 compatible = "arm,foundation-aarch64", "arm,vexpress";
14 interrupt-parent = <&gic>;
15 #address-cells = <2>;
16 #size-cells = <2>;
17
18 chosen { };
19
20 aliases {
21 serial0 = &v2m_serial0;
22 serial1 = &v2m_serial1;
23 serial2 = &v2m_serial2;
24 serial3 = &v2m_serial3;
25 };
26
27 cpus {
28 #address-cells = <2>;
29 #size-cells = <0>;
30
31 cpu@0 {
32 device_type = "cpu";
33 compatible = "arm,armv8";
34 reg = <0x0 0x0>;
35 enable-method = "spin-table";
36 cpu-release-addr = <0x0 0x8000fff8>;
37 next-level-cache = <&L2_0>;
38 };
39 cpu@1 {
40 device_type = "cpu";
41 compatible = "arm,armv8";
42 reg = <0x0 0x1>;
43 enable-method = "spin-table";
44 cpu-release-addr = <0x0 0x8000fff8>;
45 next-level-cache = <&L2_0>;
46 };
47 cpu@2 {
48 device_type = "cpu";
49 compatible = "arm,armv8";
50 reg = <0x0 0x2>;
51 enable-method = "spin-table";
52 cpu-release-addr = <0x0 0x8000fff8>;
53 next-level-cache = <&L2_0>;
54 };
55 cpu@3 {
56 device_type = "cpu";
57 compatible = "arm,armv8";
58 reg = <0x0 0x3>;
59 enable-method = "spin-table";
60 cpu-release-addr = <0x0 0x8000fff8>;
61 next-level-cache = <&L2_0>;
62 };
63
64 L2_0: l2-cache0 {
65 compatible = "cache";
66 };
67 };
68
69 memory@80000000 {
70 device_type = "memory";
71 reg = <0x00000000 0x80000000 0 0x80000000>,
72 <0x00000008 0x80000000 0 0x80000000>;
73 };
74
75 gic: interrupt-controller@2c001000 { 10 gic: interrupt-controller@2c001000 {
76 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; 11 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
77 #interrupt-cells = <3>; 12 #interrupt-cells = <3>;
78 #address-cells = <0>; 13 #address-cells = <2>;
79 interrupt-controller; 14 interrupt-controller;
80 reg = <0x0 0x2c001000 0 0x1000>, 15 reg = <0x0 0x2c001000 0 0x1000>,
81 <0x0 0x2c002000 0 0x1000>, 16 <0x0 0x2c002000 0 0x2000>,
82 <0x0 0x2c004000 0 0x2000>, 17 <0x0 0x2c004000 0 0x2000>,
83 <0x0 0x2c006000 0 0x2000>; 18 <0x0 0x2c006000 0 0x2000>;
84 interrupts = <1 9 0xf04>; 19 interrupts = <1 9 0xf04>;
85 }; 20 };
86
87 timer {
88 compatible = "arm,armv8-timer";
89 interrupts = <1 13 0xf08>,
90 <1 14 0xf08>,
91 <1 11 0xf08>,
92 <1 10 0xf08>;
93 clock-frequency = <100000000>;
94 };
95
96 pmu {
97 compatible = "arm,armv8-pmuv3";
98 interrupts = <0 60 4>,
99 <0 61 4>,
100 <0 62 4>,
101 <0 63 4>;
102 };
103
104 smb {
105 compatible = "arm,vexpress,v2m-p1", "simple-bus";
106 arm,v2m-memory-map = "rs1";
107 #address-cells = <2>; /* SMB chipselect number and offset */
108 #size-cells = <1>;
109
110 ranges = <0 0 0 0x08000000 0x04000000>,
111 <1 0 0 0x14000000 0x04000000>,
112 <2 0 0 0x18000000 0x04000000>,
113 <3 0 0 0x1c000000 0x04000000>,
114 <4 0 0 0x0c000000 0x04000000>,
115 <5 0 0 0x10000000 0x04000000>;
116
117 #interrupt-cells = <1>;
118 interrupt-map-mask = <0 0 63>;
119 interrupt-map = <0 0 0 &gic 0 0 4>,
120 <0 0 1 &gic 0 1 4>,
121 <0 0 2 &gic 0 2 4>,
122 <0 0 3 &gic 0 3 4>,
123 <0 0 4 &gic 0 4 4>,
124 <0 0 5 &gic 0 5 4>,
125 <0 0 6 &gic 0 6 4>,
126 <0 0 7 &gic 0 7 4>,
127 <0 0 8 &gic 0 8 4>,
128 <0 0 9 &gic 0 9 4>,
129 <0 0 10 &gic 0 10 4>,
130 <0 0 11 &gic 0 11 4>,
131 <0 0 12 &gic 0 12 4>,
132 <0 0 13 &gic 0 13 4>,
133 <0 0 14 &gic 0 14 4>,
134 <0 0 15 &gic 0 15 4>,
135 <0 0 16 &gic 0 16 4>,
136 <0 0 17 &gic 0 17 4>,
137 <0 0 18 &gic 0 18 4>,
138 <0 0 19 &gic 0 19 4>,
139 <0 0 20 &gic 0 20 4>,
140 <0 0 21 &gic 0 21 4>,
141 <0 0 22 &gic 0 22 4>,
142 <0 0 23 &gic 0 23 4>,
143 <0 0 24 &gic 0 24 4>,
144 <0 0 25 &gic 0 25 4>,
145 <0 0 26 &gic 0 26 4>,
146 <0 0 27 &gic 0 27 4>,
147 <0 0 28 &gic 0 28 4>,
148 <0 0 29 &gic 0 29 4>,
149 <0 0 30 &gic 0 30 4>,
150 <0 0 31 &gic 0 31 4>,
151 <0 0 32 &gic 0 32 4>,
152 <0 0 33 &gic 0 33 4>,
153 <0 0 34 &gic 0 34 4>,
154 <0 0 35 &gic 0 35 4>,
155 <0 0 36 &gic 0 36 4>,
156 <0 0 37 &gic 0 37 4>,
157 <0 0 38 &gic 0 38 4>,
158 <0 0 39 &gic 0 39 4>,
159 <0 0 40 &gic 0 40 4>,
160 <0 0 41 &gic 0 41 4>,
161 <0 0 42 &gic 0 42 4>;
162
163 ethernet@2,02000000 {
164 compatible = "smsc,lan91c111";
165 reg = <2 0x02000000 0x10000>;
166 interrupts = <15>;
167 };
168
169 v2m_clk24mhz: clk24mhz {
170 compatible = "fixed-clock";
171 #clock-cells = <0>;
172 clock-frequency = <24000000>;
173 clock-output-names = "v2m:clk24mhz";
174 };
175
176 v2m_refclk1mhz: refclk1mhz {
177 compatible = "fixed-clock";
178 #clock-cells = <0>;
179 clock-frequency = <1000000>;
180 clock-output-names = "v2m:refclk1mhz";
181 };
182
183 v2m_refclk32khz: refclk32khz {
184 compatible = "fixed-clock";
185 #clock-cells = <0>;
186 clock-frequency = <32768>;
187 clock-output-names = "v2m:refclk32khz";
188 };
189
190 iofpga@3,00000000 {
191 compatible = "arm,amba-bus", "simple-bus";
192 #address-cells = <1>;
193 #size-cells = <1>;
194 ranges = <0 3 0 0x200000>;
195
196 v2m_sysreg: sysreg@010000 {
197 compatible = "arm,vexpress-sysreg";
198 reg = <0x010000 0x1000>;
199 };
200
201 v2m_serial0: uart@090000 {
202 compatible = "arm,pl011", "arm,primecell";
203 reg = <0x090000 0x1000>;
204 interrupts = <5>;
205 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
206 clock-names = "uartclk", "apb_pclk";
207 };
208
209 v2m_serial1: uart@0a0000 {
210 compatible = "arm,pl011", "arm,primecell";
211 reg = <0x0a0000 0x1000>;
212 interrupts = <6>;
213 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
214 clock-names = "uartclk", "apb_pclk";
215 };
216
217 v2m_serial2: uart@0b0000 {
218 compatible = "arm,pl011", "arm,primecell";
219 reg = <0x0b0000 0x1000>;
220 interrupts = <7>;
221 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
222 clock-names = "uartclk", "apb_pclk";
223 };
224
225 v2m_serial3: uart@0c0000 {
226 compatible = "arm,pl011", "arm,primecell";
227 reg = <0x0c0000 0x1000>;
228 interrupts = <8>;
229 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
230 clock-names = "uartclk", "apb_pclk";
231 };
232
233 virtio_block@0130000 {
234 compatible = "virtio,mmio";
235 reg = <0x130000 0x200>;
236 interrupts = <42>;
237 };
238 };
239 };
240}; 21};
diff --git a/arch/arm64/boot/dts/arm/foundation-v8.dtsi b/arch/arm64/boot/dts/arm/foundation-v8.dtsi
new file mode 100644
index 000000000000..9314f3943269
--- /dev/null
+++ b/arch/arm64/boot/dts/arm/foundation-v8.dtsi
@@ -0,0 +1,228 @@
1/*
2 * ARM Ltd.
3 *
4 * ARMv8 Foundation model DTS
5 */
6
7/dts-v1/;
8
9/memreserve/ 0x80000000 0x00010000;
10
11/ {
12 model = "Foundation-v8A";
13 compatible = "arm,foundation-aarch64", "arm,vexpress";
14 interrupt-parent = <&gic>;
15 #address-cells = <2>;
16 #size-cells = <2>;
17
18 chosen { };
19
20 aliases {
21 serial0 = &v2m_serial0;
22 serial1 = &v2m_serial1;
23 serial2 = &v2m_serial2;
24 serial3 = &v2m_serial3;
25 };
26
27 cpus {
28 #address-cells = <2>;
29 #size-cells = <0>;
30
31 cpu@0 {
32 device_type = "cpu";
33 compatible = "arm,armv8";
34 reg = <0x0 0x0>;
35 enable-method = "spin-table";
36 cpu-release-addr = <0x0 0x8000fff8>;
37 next-level-cache = <&L2_0>;
38 };
39 cpu@1 {
40 device_type = "cpu";
41 compatible = "arm,armv8";
42 reg = <0x0 0x1>;
43 enable-method = "spin-table";
44 cpu-release-addr = <0x0 0x8000fff8>;
45 next-level-cache = <&L2_0>;
46 };
47 cpu@2 {
48 device_type = "cpu";
49 compatible = "arm,armv8";
50 reg = <0x0 0x2>;
51 enable-method = "spin-table";
52 cpu-release-addr = <0x0 0x8000fff8>;
53 next-level-cache = <&L2_0>;
54 };
55 cpu@3 {
56 device_type = "cpu";
57 compatible = "arm,armv8";
58 reg = <0x0 0x3>;
59 enable-method = "spin-table";
60 cpu-release-addr = <0x0 0x8000fff8>;
61 next-level-cache = <&L2_0>;
62 };
63
64 L2_0: l2-cache0 {
65 compatible = "cache";
66 };
67 };
68
69 memory@80000000 {
70 device_type = "memory";
71 reg = <0x00000000 0x80000000 0 0x80000000>,
72 <0x00000008 0x80000000 0 0x80000000>;
73 };
74
75 timer {
76 compatible = "arm,armv8-timer";
77 interrupts = <1 13 0xf08>,
78 <1 14 0xf08>,
79 <1 11 0xf08>,
80 <1 10 0xf08>;
81 clock-frequency = <100000000>;
82 };
83
84 pmu {
85 compatible = "arm,armv8-pmuv3";
86 interrupts = <0 60 4>,
87 <0 61 4>,
88 <0 62 4>,
89 <0 63 4>;
90 };
91
92 smb {
93 compatible = "arm,vexpress,v2m-p1", "simple-bus";
94 arm,v2m-memory-map = "rs1";
95 #address-cells = <2>; /* SMB chipselect number and offset */
96 #size-cells = <1>;
97
98 ranges = <0 0 0 0x08000000 0x04000000>,
99 <1 0 0 0x14000000 0x04000000>,
100 <2 0 0 0x18000000 0x04000000>,
101 <3 0 0 0x1c000000 0x04000000>,
102 <4 0 0 0x0c000000 0x04000000>,
103 <5 0 0 0x10000000 0x04000000>;
104
105 #interrupt-cells = <1>;
106 interrupt-map-mask = <0 0 63>;
107 interrupt-map = <0 0 0 &gic 0 0 0 0 4>,
108 <0 0 1 &gic 0 0 0 1 4>,
109 <0 0 2 &gic 0 0 0 2 4>,
110 <0 0 3 &gic 0 0 0 3 4>,
111 <0 0 4 &gic 0 0 0 4 4>,
112 <0 0 5 &gic 0 0 0 5 4>,
113 <0 0 6 &gic 0 0 0 6 4>,
114 <0 0 7 &gic 0 0 0 7 4>,
115 <0 0 8 &gic 0 0 0 8 4>,
116 <0 0 9 &gic 0 0 0 9 4>,
117 <0 0 10 &gic 0 0 0 10 4>,
118 <0 0 11 &gic 0 0 0 11 4>,
119 <0 0 12 &gic 0 0 0 12 4>,
120 <0 0 13 &gic 0 0 0 13 4>,
121 <0 0 14 &gic 0 0 0 14 4>,
122 <0 0 15 &gic 0 0 0 15 4>,
123 <0 0 16 &gic 0 0 0 16 4>,
124 <0 0 17 &gic 0 0 0 17 4>,
125 <0 0 18 &gic 0 0 0 18 4>,
126 <0 0 19 &gic 0 0 0 19 4>,
127 <0 0 20 &gic 0 0 0 20 4>,
128 <0 0 21 &gic 0 0 0 21 4>,
129 <0 0 22 &gic 0 0 0 22 4>,
130 <0 0 23 &gic 0 0 0 23 4>,
131 <0 0 24 &gic 0 0 0 24 4>,
132 <0 0 25 &gic 0 0 0 25 4>,
133 <0 0 26 &gic 0 0 0 26 4>,
134 <0 0 27 &gic 0 0 0 27 4>,
135 <0 0 28 &gic 0 0 0 28 4>,
136 <0 0 29 &gic 0 0 0 29 4>,
137 <0 0 30 &gic 0 0 0 30 4>,
138 <0 0 31 &gic 0 0 0 31 4>,
139 <0 0 32 &gic 0 0 0 32 4>,
140 <0 0 33 &gic 0 0 0 33 4>,
141 <0 0 34 &gic 0 0 0 34 4>,
142 <0 0 35 &gic 0 0 0 35 4>,
143 <0 0 36 &gic 0 0 0 36 4>,
144 <0 0 37 &gic 0 0 0 37 4>,
145 <0 0 38 &gic 0 0 0 38 4>,
146 <0 0 39 &gic 0 0 0 39 4>,
147 <0 0 40 &gic 0 0 0 40 4>,
148 <0 0 41 &gic 0 0 0 41 4>,
149 <0 0 42 &gic 0 0 0 42 4>;
150
151 ethernet@2,02000000 {
152 compatible = "smsc,lan91c111";
153 reg = <2 0x02000000 0x10000>;
154 interrupts = <15>;
155 };
156
157 v2m_clk24mhz: clk24mhz {
158 compatible = "fixed-clock";
159 #clock-cells = <0>;
160 clock-frequency = <24000000>;
161 clock-output-names = "v2m:clk24mhz";
162 };
163
164 v2m_refclk1mhz: refclk1mhz {
165 compatible = "fixed-clock";
166 #clock-cells = <0>;
167 clock-frequency = <1000000>;
168 clock-output-names = "v2m:refclk1mhz";
169 };
170
171 v2m_refclk32khz: refclk32khz {
172 compatible = "fixed-clock";
173 #clock-cells = <0>;
174 clock-frequency = <32768>;
175 clock-output-names = "v2m:refclk32khz";
176 };
177
178 iofpga@3,00000000 {
179 compatible = "arm,amba-bus", "simple-bus";
180 #address-cells = <1>;
181 #size-cells = <1>;
182 ranges = <0 3 0 0x200000>;
183
184 v2m_sysreg: sysreg@010000 {
185 compatible = "arm,vexpress-sysreg";
186 reg = <0x010000 0x1000>;
187 };
188
189 v2m_serial0: uart@090000 {
190 compatible = "arm,pl011", "arm,primecell";
191 reg = <0x090000 0x1000>;
192 interrupts = <5>;
193 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
194 clock-names = "uartclk", "apb_pclk";
195 };
196
197 v2m_serial1: uart@0a0000 {
198 compatible = "arm,pl011", "arm,primecell";
199 reg = <0x0a0000 0x1000>;
200 interrupts = <6>;
201 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
202 clock-names = "uartclk", "apb_pclk";
203 };
204
205 v2m_serial2: uart@0b0000 {
206 compatible = "arm,pl011", "arm,primecell";
207 reg = <0x0b0000 0x1000>;
208 interrupts = <7>;
209 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
210 clock-names = "uartclk", "apb_pclk";
211 };
212
213 v2m_serial3: uart@0c0000 {
214 compatible = "arm,pl011", "arm,primecell";
215 reg = <0x0c0000 0x1000>;
216 interrupts = <8>;
217 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
218 clock-names = "uartclk", "apb_pclk";
219 };
220
221 virtio_block@0130000 {
222 compatible = "virtio,mmio";
223 reg = <0x130000 0x200>;
224 interrupts = <42>;
225 };
226 };
227 };
228};
diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi
index e5b59ca9debb..4b6172b0f2cb 100644
--- a/arch/arm64/boot/dts/arm/juno-base.dtsi
+++ b/arch/arm64/boot/dts/arm/juno-base.dtsi
@@ -75,6 +75,28 @@
75 }; 75 };
76 }; 76 };
77 77
78 pcie_ctlr: pcie-controller@40000000 {
79 compatible = "arm,juno-r1-pcie", "plda,xpressrich3-axi", "pci-host-ecam-generic";
80 device_type = "pci";
81 reg = <0 0x40000000 0 0x10000000>; /* ECAM config space */
82 bus-range = <0 255>;
83 linux,pci-domain = <0>;
84 #address-cells = <3>;
85 #size-cells = <2>;
86 dma-coherent;
87 ranges = <0x01000000 0x00 0x5f800000 0x00 0x5f800000 0x0 0x00800000>,
88 <0x02000000 0x00 0x50000000 0x00 0x50000000 0x0 0x08000000>,
89 <0x42000000 0x40 0x00000000 0x40 0x00000000 0x1 0x00000000>;
90 #interrupt-cells = <1>;
91 interrupt-map-mask = <0 0 0 7>;
92 interrupt-map = <0 0 0 1 &gic 0 0 0 136 4>,
93 <0 0 0 2 &gic 0 0 0 137 4>,
94 <0 0 0 3 &gic 0 0 0 138 4>,
95 <0 0 0 4 &gic 0 0 0 139 4>;
96 msi-parent = <&v2m_0>;
97 status = "disabled";
98 };
99
78 scpi { 100 scpi {
79 compatible = "arm,scpi"; 101 compatible = "arm,scpi";
80 mboxes = <&mailbox 1>; 102 mboxes = <&mailbox 1>;
@@ -92,8 +114,8 @@
92 scpi_clk: scpi_clocks@3 { 114 scpi_clk: scpi_clocks@3 {
93 compatible = "arm,scpi-variable-clocks"; 115 compatible = "arm,scpi-variable-clocks";
94 #clock-cells = <1>; 116 #clock-cells = <1>;
95 clock-indices = <3>, <4>; 117 clock-indices = <3>;
96 clock-output-names = "pxlclk0", "pxlclk1"; 118 clock-output-names = "pxlclk";
97 }; 119 };
98 }; 120 };
99 121
@@ -124,6 +146,34 @@
124 clock-names = "apb_pclk"; 146 clock-names = "apb_pclk";
125 }; 147 };
126 148
149 hdlcd@7ff50000 {
150 compatible = "arm,hdlcd";
151 reg = <0 0x7ff50000 0 0x1000>;
152 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
153 clocks = <&scpi_clk 3>;
154 clock-names = "pxlclk";
155
156 port {
157 hdlcd1_output: endpoint@0 {
158 remote-endpoint = <&tda998x_1_input>;
159 };
160 };
161 };
162
163 hdlcd@7ff60000 {
164 compatible = "arm,hdlcd";
165 reg = <0 0x7ff60000 0 0x1000>;
166 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
167 clocks = <&scpi_clk 3>;
168 clock-names = "pxlclk";
169
170 port {
171 hdlcd0_output: endpoint@0 {
172 remote-endpoint = <&tda998x_0_input>;
173 };
174 };
175 };
176
127 soc_uart0: uart@7ff80000 { 177 soc_uart0: uart@7ff80000 {
128 compatible = "arm,pl011", "arm,primecell"; 178 compatible = "arm,pl011", "arm,primecell";
129 reg = <0x0 0x7ff80000 0x0 0x1000>; 179 reg = <0x0 0x7ff80000 0x0 0x1000>;
@@ -142,14 +192,24 @@
142 i2c-sda-hold-time-ns = <500>; 192 i2c-sda-hold-time-ns = <500>;
143 clocks = <&soc_smc50mhz>; 193 clocks = <&soc_smc50mhz>;
144 194
145 dvi0: dvi-transmitter@70 { 195 hdmi-transmitter@70 {
146 compatible = "nxp,tda998x"; 196 compatible = "nxp,tda998x";
147 reg = <0x70>; 197 reg = <0x70>;
198 port {
199 tda998x_0_input: endpoint@0 {
200 remote-endpoint = <&hdlcd0_output>;
201 };
202 };
148 }; 203 };
149 204
150 dvi1: dvi-transmitter@71 { 205 hdmi-transmitter@71 {
151 compatible = "nxp,tda998x"; 206 compatible = "nxp,tda998x";
152 reg = <0x71>; 207 reg = <0x71>;
208 port {
209 tda998x_1_input: endpoint@0 {
210 remote-endpoint = <&hdlcd1_output>;
211 };
212 };
153 }; 213 };
154 }; 214 };
155 215
diff --git a/arch/arm64/boot/dts/arm/juno-r1.dts b/arch/arm64/boot/dts/arm/juno-r1.dts
index 8826f834f54f..d95d9e7e2dc0 100644
--- a/arch/arm64/boot/dts/arm/juno-r1.dts
+++ b/arch/arm64/boot/dts/arm/juno-r1.dts
@@ -172,29 +172,12 @@
172 }; 172 };
173 173
174 #include "juno-base.dtsi" 174 #include "juno-base.dtsi"
175
176 pcie-controller@40000000 {
177 compatible = "arm,juno-r1-pcie", "plda,xpressrich3-axi", "pci-host-ecam-generic";
178 device_type = "pci";
179 reg = <0 0x40000000 0 0x10000000>; /* ECAM config space */
180 bus-range = <0 255>;
181 linux,pci-domain = <0>;
182 #address-cells = <3>;
183 #size-cells = <2>;
184 dma-coherent;
185 ranges = <0x01000000 0x00 0x5f800000 0x00 0x5f800000 0x0 0x00800000>,
186 <0x02000000 0x00 0x50000000 0x00 0x50000000 0x0 0x08000000>,
187 <0x42000000 0x40 0x00000000 0x40 0x00000000 0x1 0x00000000>;
188 #interrupt-cells = <1>;
189 interrupt-map-mask = <0 0 0 7>;
190 interrupt-map = <0 0 0 1 &gic 0 0 0 136 4>,
191 <0 0 0 2 &gic 0 0 0 137 4>,
192 <0 0 0 3 &gic 0 0 0 138 4>,
193 <0 0 0 4 &gic 0 0 0 139 4>;
194 msi-parent = <&v2m_0>;
195 };
196}; 175};
197 176
198&memtimer { 177&memtimer {
199 status = "okay"; 178 status = "okay";
200}; 179};
180
181&pcie_ctlr {
182 status = "okay";
183};
diff --git a/arch/arm64/boot/dts/arm/juno-r2.dts b/arch/arm64/boot/dts/arm/juno-r2.dts
new file mode 100644
index 000000000000..88ecd6182b67
--- /dev/null
+++ b/arch/arm64/boot/dts/arm/juno-r2.dts
@@ -0,0 +1,183 @@
1/*
2 * ARM Ltd. Juno Platform
3 *
4 * Copyright (c) 2015 ARM Ltd.
5 *
6 * This file is licensed under a dual GPLv2 or BSD license.
7 */
8
9/dts-v1/;
10
11#include <dt-bindings/interrupt-controller/arm-gic.h>
12
13/ {
14 model = "ARM Juno development board (r2)";
15 compatible = "arm,juno-r2", "arm,juno", "arm,vexpress";
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
19
20 aliases {
21 serial0 = &soc_uart0;
22 };
23
24 chosen {
25 stdout-path = "serial0:115200n8";
26 };
27
28 psci {
29 compatible = "arm,psci-0.2";
30 method = "smc";
31 };
32
33 cpus {
34 #address-cells = <2>;
35 #size-cells = <0>;
36
37 cpu-map {
38 cluster0 {
39 core0 {
40 cpu = <&A72_0>;
41 };
42 core1 {
43 cpu = <&A72_1>;
44 };
45 };
46
47 cluster1 {
48 core0 {
49 cpu = <&A53_0>;
50 };
51 core1 {
52 cpu = <&A53_1>;
53 };
54 core2 {
55 cpu = <&A53_2>;
56 };
57 core3 {
58 cpu = <&A53_3>;
59 };
60 };
61 };
62
63 idle-states {
64 entry-method = "arm,psci";
65
66 CPU_SLEEP_0: cpu-sleep-0 {
67 compatible = "arm,idle-state";
68 arm,psci-suspend-param = <0x0010000>;
69 local-timer-stop;
70 entry-latency-us = <300>;
71 exit-latency-us = <1200>;
72 min-residency-us = <2000>;
73 };
74
75 CLUSTER_SLEEP_0: cluster-sleep-0 {
76 compatible = "arm,idle-state";
77 arm,psci-suspend-param = <0x1010000>;
78 local-timer-stop;
79 entry-latency-us = <300>;
80 exit-latency-us = <1200>;
81 min-residency-us = <2500>;
82 };
83 };
84
85 A72_0: cpu@0 {
86 compatible = "arm,cortex-a72","arm,armv8";
87 reg = <0x0 0x0>;
88 device_type = "cpu";
89 enable-method = "psci";
90 next-level-cache = <&A72_L2>;
91 clocks = <&scpi_dvfs 0>;
92 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
93 };
94
95 A72_1: cpu@1 {
96 compatible = "arm,cortex-a72","arm,armv8";
97 reg = <0x0 0x1>;
98 device_type = "cpu";
99 enable-method = "psci";
100 next-level-cache = <&A72_L2>;
101 clocks = <&scpi_dvfs 0>;
102 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
103 };
104
105 A53_0: cpu@100 {
106 compatible = "arm,cortex-a53","arm,armv8";
107 reg = <0x0 0x100>;
108 device_type = "cpu";
109 enable-method = "psci";
110 next-level-cache = <&A53_L2>;
111 clocks = <&scpi_dvfs 1>;
112 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
113 };
114
115 A53_1: cpu@101 {
116 compatible = "arm,cortex-a53","arm,armv8";
117 reg = <0x0 0x101>;
118 device_type = "cpu";
119 enable-method = "psci";
120 next-level-cache = <&A53_L2>;
121 clocks = <&scpi_dvfs 1>;
122 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
123 };
124
125 A53_2: cpu@102 {
126 compatible = "arm,cortex-a53","arm,armv8";
127 reg = <0x0 0x102>;
128 device_type = "cpu";
129 enable-method = "psci";
130 next-level-cache = <&A53_L2>;
131 clocks = <&scpi_dvfs 1>;
132 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
133 };
134
135 A53_3: cpu@103 {
136 compatible = "arm,cortex-a53","arm,armv8";
137 reg = <0x0 0x103>;
138 device_type = "cpu";
139 enable-method = "psci";
140 next-level-cache = <&A53_L2>;
141 clocks = <&scpi_dvfs 1>;
142 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
143 };
144
145 A72_L2: l2-cache0 {
146 compatible = "cache";
147 };
148
149 A53_L2: l2-cache1 {
150 compatible = "cache";
151 };
152 };
153
154 pmu_a72 {
155 compatible = "arm,cortex-a72-pmu";
156 interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>,
157 <GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>;
158 interrupt-affinity = <&A72_0>,
159 <&A72_1>;
160 };
161
162 pmu_a53 {
163 compatible = "arm,cortex-a53-pmu";
164 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
165 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
166 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
167 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
168 interrupt-affinity = <&A53_0>,
169 <&A53_1>,
170 <&A53_2>,
171 <&A53_3>;
172 };
173
174 #include "juno-base.dtsi"
175};
176
177&memtimer {
178 status = "okay";
179};
180
181&pcie_ctlr {
182 status = "okay";
183};
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-20 11:09:57 -0400