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authorArnd Bergmann <arnd@arndb.de>2017-12-21 10:21:10 -0500
committerArnd Bergmann <arnd@arndb.de>2017-12-21 10:21:10 -0500
commit7d44cc2082e2cb2c5ef34b6536d6699f0510a554 (patch)
treef24501bc3e429d589c966ce991f05d555b71000d
parent2c2529176236c870693290d314c06652f5f3fe47 (diff)
parent8aba250d7800702bbd2f6a91174e01b9a84ed2dd (diff)
Merge tag 'renesas-arm64-dt-for-v4.16' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt
Pull "Renesas ARM64 Based SoC DT Updates for v4.16" from Simon Horman: * Use r8a77970 (V3M) CPG core clock and SYSC power domain macros These may be used in place of numeric constants now that they are present in Linus's tree. * Add r8a77970 (V3M) Starter Kit board support This includes basic support to bring up the board with a serial console and EtherAVB support * Add IPMMU nodes and connections to on-chip devices on r8a7795 (H3), r8a7796 (M3-W), r8a77970 (V3M) and r8a77995 (D3) SoCs Simon Horman says "With these patches applied a white list enabled IPMMU driver may be used to check silicon revision and then enable IPMMU in the known working cases." * Enable DMA for SCIF2 on r8a77995 (D2) SoC * Increase the number of GPIO bank 1 ports to 29 on r8a7795 (H3) SoC This adds support for the GP-1-28 port pin of the r8a7795 (H3) ES2.0 SoC * Add support for CAN to r8a77995 (D3) SoC Ulrich Hecht says "This is a by-the-datasheet implementation, with the datasheet missing some bits, namely the pin map. I filled in the gaps... by deducing the information from pin numbers already in the PFC driver, so careful scrutiny is advised." * Add support for SDHI to r8a77995 (D3) SoC * Add SoC name to file header of r8a7795 (H3) and r8a7796 (M3-W) Salvator-X and Salvator-XS board files Geert Uytterhoeven says "With the proliferation of Salvator-X and Salvator-XS boards carrying different R-Car Gen3 SoCs variants, several DTS files ended up having the same file headers. Add the SoC names to the file headers to avoid confusion." * Add device note for ROHM BD9571MWV PMIC to r8a7795 (H3) and r8a7796 (M3-W) Salvator-X and Salvator-XS boards. Geert Uytterhoeven says "This was based on the example in the DT binding documentation, but using IRQ0 instead of a GPIO interrupt, as that matches the schematics, and because INTC-EX is a simpler block." * Enable USB2.0 channel 0 on r8a77970 (V3M) ULCB Kingfisher board Vladimir Barinov says "The dedicated USB0_PWEN pin is used to control CN13 VBUS source from U43 power supply. MAX3355 can also provide VBUS, hence it should be disabled via OTG_OFFVBUSn node coming from gpio expander TCA9539. Set MAX3355 enabled using OTG_EXTLPn node to be able to read OTG ID of CN13." * Add support for r8a7795 (M3-W) Salvator-XS board Geert Uytterhoeven says "This patch series adds support for the version of the Salvator-XS development board equipped with an R-Car M3-W SiP. The DT was based on work for the Salvator-X and -XS boards with M3-W resp. H3 SiPs." * Add watchdog timer support to r8a77970 (V3M) eagle board Geert Uytterhoven says "This allows to use the watchdog timer to reset the board, until PSCI is enhanced to include such functionality." * Use Use R-Car SDHI Gen3 fallback on r8a7795 (H3) and r8a7796 (M3-W) SoCs * Set driver type for MMC on r8a7795 (H3) and r8a7796 (M3-W) Salvator-X and Salvator-XS boards. Wolfram Sang says "These boards are known to have eMMC issues with the default driver type. Specify a working one." * tag 'renesas-arm64-dt-for-v4.16' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (54 commits) arm64: dts: renesas: r8a77970: use SYSC power domain macros arm64: dts: renesas: r8a77970: use CPG core clock macros arm64: dts: renesas: v3msk: add EtherAVB support arm64: dts: renesas: initial V3MSK board device tree arm64: dts: renesas: r8a77995: Connect Ethernet-AVB to IPMMU-RT arm64: dts: renesas: r8a77995: Add IPMMU device nodes arm64: dts: renesas: r8a77970: Enable IPMMU-DS1, RT and MM arm64: dts: renesas: r8a77970: Connect Ethernet-AVB to IPMMU-RT arm64: dts: renesas: r8a77970: Tie SYS-DMAC to IPMMU-DS1 arm64: dts: renesas: r8a77970: Add IPMMU device nodes arm64: dts: renesas: r8a77995: add DMA for SCIF2 arm64: dts: renesas: r8a77970: sort includes arm64: dts: renesas: r8a7795: Increase the number of GPIO bank 1 ports to 29 arm64: dts: renesas: r8a77995: Add CAN FD support arm64: dts: renesas: r8a77995: Add CAN support arm64: dts: renesas: r8a77995: Add CAN external clock support arm64: dts: renesas: r8a7795-salvator-xs: Add SoC name to file header arm64: dts: renesas: r8a7796-salvator-x: Add SoC name to file header arm64: dts: renesas: r8a7795-salvator-x: Add SoC name to file header arm64: dts: renesas: r8a7795-es1-salvator-x: Add SoC name to file header ...
Diffstat
-rw-r--r--arch/arm64/boot/dts/renesas/Makefile3
-rw-r--r--arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts2
-rw-r--r--arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi85
-rw-r--r--arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts2
-rw-r--r--arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts2
-rw-r--r--arch/arm64/boot/dts/renesas/r8a7795.dtsi205
-rw-r--r--arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts2
-rw-r--r--arch/arm64/boot/dts/renesas/r8a7796-salvator-xs.dts58
-rw-r--r--arch/arm64/boot/dts/renesas/r8a7796.dtsi151
-rw-r--r--arch/arm64/boot/dts/renesas/r8a77970-eagle.dts23
-rw-r--r--arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts55
-rw-r--r--arch/arm64/boot/dts/renesas/r8a77970.dtsi115
-rw-r--r--arch/arm64/boot/dts/renesas/r8a77995.dtsi234
-rw-r--r--arch/arm64/boot/dts/renesas/salvator-common.dtsi30
-rw-r--r--arch/arm64/boot/dts/renesas/ulcb-kf.dtsi29
15 files changed, 947 insertions, 49 deletions
diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
index 646198d82903..2186d0193b73 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -6,5 +6,6 @@ dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-es1-salvator-x.dtb r8a7795-es1-h3ulcb.dtb
6dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-es1-h3ulcb-kf.dtb 6dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-es1-h3ulcb-kf.dtb
7dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-x.dtb r8a7796-m3ulcb.dtb 7dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-x.dtb r8a7796-m3ulcb.dtb
8dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-m3ulcb-kf.dtb 8dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-m3ulcb-kf.dtb
9dtb-$(CONFIG_ARCH_R8A77970) += r8a77970-eagle.dtb 9dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-xs.dtb
10dtb-$(CONFIG_ARCH_R8A77970) += r8a77970-eagle.dtb r8a77970-v3msk.dtb
10dtb-$(CONFIG_ARCH_R8A77995) += r8a77995-draak.dtb 11dtb-$(CONFIG_ARCH_R8A77995) += r8a77995-draak.dtb
diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts
index 3f7d5f51e428..7f2a3d923f21 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts
@@ -1,5 +1,5 @@
1/* 1/*
2 * Device Tree Source for the Salvator-X board 2 * Device Tree Source for the Salvator-X board with R-Car H3 ES1.x
3 * 3 *
4 * Copyright (C) 2015 Renesas Electronics Corp. 4 * Copyright (C) 2015 Renesas Electronics Corp.
5 * 5 *
diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
index 655dd30639c5..26769a11a190 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
@@ -21,6 +21,26 @@
21 status = "disabled"; 21 status = "disabled";
22 }; 22 };
23 23
24 /delete-node/ mmu@febe0000;
25 /delete-node/ mmu@fe980000;
26 /delete-node/ mmu@fd960000;
27 /delete-node/ mmu@fd970000;
28
29 ipmmu_mp1: mmu@ec680000 {
30 compatible = "renesas,ipmmu-r8a7795";
31 reg = <0 0xec680000 0 0x1000>;
32 renesas,ipmmu-main = <&ipmmu_mm 5>;
33 #iommu-cells = <1>;
34 };
35
36 ipmmu_sy: mmu@e7730000 {
37 compatible = "renesas,ipmmu-r8a7795";
38 reg = <0 0xe7730000 0 0x1000>;
39 renesas,ipmmu-main = <&ipmmu_mm 8>;
40 #iommu-cells = <1>;
41 status = "disabled";
42 };
43
24 /delete-node/ usb-phy@ee0e0200; 44 /delete-node/ usb-phy@ee0e0200;
25 /delete-node/ usb@ee0e0100; 45 /delete-node/ usb@ee0e0100;
26 /delete-node/ usb@ee0e0000; 46 /delete-node/ usb@ee0e0000;
@@ -35,6 +55,7 @@
35 clocks = <&cpg CPG_MOD 613>; 55 clocks = <&cpg CPG_MOD 613>;
36 power-domains = <&sysc R8A7795_PD_A3VP>; 56 power-domains = <&sysc R8A7795_PD_A3VP>;
37 resets = <&cpg 613>; 57 resets = <&cpg 613>;
58 iommus = <&ipmmu_vp0 2>;
38 }; 59 };
39 60
40 vspi2: vsp@fe9c0000 { 61 vspi2: vsp@fe9c0000 {
@@ -54,6 +75,7 @@
54 clocks = <&cpg CPG_MOD 609>; 75 clocks = <&cpg CPG_MOD 609>;
55 power-domains = <&sysc R8A7795_PD_A3VP>; 76 power-domains = <&sysc R8A7795_PD_A3VP>;
56 resets = <&cpg 609>; 77 resets = <&cpg 609>;
78 iommus = <&ipmmu_vp0 10>;
57 }; 79 };
58 80
59 vspd3: vsp@fea38000 { 81 vspd3: vsp@fea38000 {
@@ -73,6 +95,7 @@
73 clocks = <&cpg CPG_MOD 600>; 95 clocks = <&cpg CPG_MOD 600>;
74 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 96 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
75 resets = <&cpg 600>; 97 resets = <&cpg 600>;
98 iommus = <&ipmmu_vi0 11>;
76 }; 99 };
77 100
78 fdp1@fe948000 { 101 fdp1@fe948000 {
@@ -86,6 +109,68 @@
86 }; 109 };
87}; 110};
88 111
112&gpio1 {
113 gpio-ranges = <&pfc 0 32 28>;
114};
115
116&ipmmu_vi0 {
117 renesas,ipmmu-main = <&ipmmu_mm 11>;
118};
119
120&ipmmu_vp0 {
121 renesas,ipmmu-main = <&ipmmu_mm 12>;
122};
123
124&ipmmu_vc0 {
125 renesas,ipmmu-main = <&ipmmu_mm 9>;
126};
127
128&ipmmu_vc1 {
129 renesas,ipmmu-main = <&ipmmu_mm 10>;
130};
131
132&ipmmu_rt {
133 renesas,ipmmu-main = <&ipmmu_mm 7>;
134};
135
136&audma0 {
137 iommus = <&ipmmu_mp1 0>, <&ipmmu_mp1 1>,
138 <&ipmmu_mp1 2>, <&ipmmu_mp1 3>,
139 <&ipmmu_mp1 4>, <&ipmmu_mp1 5>,
140 <&ipmmu_mp1 6>, <&ipmmu_mp1 7>,
141 <&ipmmu_mp1 8>, <&ipmmu_mp1 9>,
142 <&ipmmu_mp1 10>, <&ipmmu_mp1 11>,
143 <&ipmmu_mp1 12>, <&ipmmu_mp1 13>,
144 <&ipmmu_mp1 14>, <&ipmmu_mp1 15>;
145};
146
147&audma1 {
148 iommus = <&ipmmu_mp1 16>, <&ipmmu_mp1 17>,
149 <&ipmmu_mp1 18>, <&ipmmu_mp1 19>,
150 <&ipmmu_mp1 20>, <&ipmmu_mp1 21>,
151 <&ipmmu_mp1 22>, <&ipmmu_mp1 23>,
152 <&ipmmu_mp1 24>, <&ipmmu_mp1 25>,
153 <&ipmmu_mp1 26>, <&ipmmu_mp1 27>,
154 <&ipmmu_mp1 28>, <&ipmmu_mp1 29>,
155 <&ipmmu_mp1 30>, <&ipmmu_mp1 31>;
156};
157
158&fcpvb1 {
159 iommus = <&ipmmu_vp0 7>;
160};
161
162&fcpf1 {
163 iommus = <&ipmmu_vp0 1>;
164};
165
166&fcpvi1 {
167 iommus = <&ipmmu_vp0 9>;
168};
169
170&fcpvd2 {
171 iommus = <&ipmmu_vi0 10>;
172};
173
89&du { 174&du {
90 vsps = <&vspd0 &vspd1 &vspd2 &vspd3>; 175 vsps = <&vspd0 &vspd1 &vspd2 &vspd3>;
91}; 176};
diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
index 17953070f38d..af467419266a 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
@@ -1,5 +1,5 @@
1/* 1/*
2 * Device Tree Source for the Salvator-X board 2 * Device Tree Source for the Salvator-X board with R-Car H3 ES2.0
3 * 3 *
4 * Copyright (C) 2015 Renesas Electronics Corp. 4 * Copyright (C) 2015 Renesas Electronics Corp.
5 * 5 *
diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts
index 7675de5d4f2c..8b50ceb746e8 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts
@@ -1,5 +1,5 @@
1/* 1/*
2 * Device Tree Source for the Salvator-X 2nd version board 2 * Device Tree Source for the Salvator-X 2nd version board with R-Car H3 ES2.0
3 * 3 *
4 * Copyright (C) 2015-2017 Renesas Electronics Corp. 4 * Copyright (C) 2015-2017 Renesas Electronics Corp.
5 * 5 *
diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index 15ef292a8d9f..6db4f10376a1 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -240,7 +240,7 @@
240 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 240 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
241 #gpio-cells = <2>; 241 #gpio-cells = <2>;
242 gpio-controller; 242 gpio-controller;
243 gpio-ranges = <&pfc 0 32 28>; 243 gpio-ranges = <&pfc 0 32 29>;
244 #interrupt-cells = <2>; 244 #interrupt-cells = <2>;
245 interrupt-controller; 245 interrupt-controller;
246 clocks = <&cpg CPG_MOD 911>; 246 clocks = <&cpg CPG_MOD 911>;
@@ -421,6 +421,146 @@
421 resets = <&cpg 407>; 421 resets = <&cpg 407>;
422 }; 422 };
423 423
424 ipmmu_vi0: mmu@febd0000 {
425 compatible = "renesas,ipmmu-r8a7795";
426 reg = <0 0xfebd0000 0 0x1000>;
427 renesas,ipmmu-main = <&ipmmu_mm 14>;
428 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
429 #iommu-cells = <1>;
430 };
431
432 ipmmu_vi1: mmu@febe0000 {
433 compatible = "renesas,ipmmu-r8a7795";
434 reg = <0 0xfebe0000 0 0x1000>;
435 renesas,ipmmu-main = <&ipmmu_mm 15>;
436 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
437 #iommu-cells = <1>;
438 status = "disabled";
439 };
440
441 ipmmu_vp0: mmu@fe990000 {
442 compatible = "renesas,ipmmu-r8a7795";
443 reg = <0 0xfe990000 0 0x1000>;
444 renesas,ipmmu-main = <&ipmmu_mm 16>;
445 power-domains = <&sysc R8A7795_PD_A3VP>;
446 #iommu-cells = <1>;
447 status = "disabled";
448 };
449
450 ipmmu_vp1: mmu@fe980000 {
451 compatible = "renesas,ipmmu-r8a7795";
452 reg = <0 0xfe980000 0 0x1000>;
453 renesas,ipmmu-main = <&ipmmu_mm 17>;
454 power-domains = <&sysc R8A7795_PD_A3VP>;
455 #iommu-cells = <1>;
456 };
457
458 ipmmu_vc0: mmu@fe6b0000 {
459 compatible = "renesas,ipmmu-r8a7795";
460 reg = <0 0xfe6b0000 0 0x1000>;
461 renesas,ipmmu-main = <&ipmmu_mm 12>;
462 power-domains = <&sysc R8A7795_PD_A3VC>;
463 #iommu-cells = <1>;
464 status = "disabled";
465 };
466
467 ipmmu_vc1: mmu@fe6f0000 {
468 compatible = "renesas,ipmmu-r8a7795";
469 reg = <0 0xfe6f0000 0 0x1000>;
470 renesas,ipmmu-main = <&ipmmu_mm 13>;
471 power-domains = <&sysc R8A7795_PD_A3VC>;
472 #iommu-cells = <1>;
473 status = "disabled";
474 };
475
476 ipmmu_pv0: mmu@fd800000 {
477 compatible = "renesas,ipmmu-r8a7795";
478 reg = <0 0xfd800000 0 0x1000>;
479 renesas,ipmmu-main = <&ipmmu_mm 6>;
480 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
481 #iommu-cells = <1>;
482 status = "disabled";
483 };
484
485 ipmmu_pv2: mmu@fd960000 {
486 compatible = "renesas,ipmmu-r8a7795";
487 reg = <0 0xfd960000 0 0x1000>;
488 renesas,ipmmu-main = <&ipmmu_mm 8>;
489 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
490 #iommu-cells = <1>;
491 status = "disabled";
492 };
493
494 ipmmu_pv3: mmu@fd970000 {
495 compatible = "renesas,ipmmu-r8a7795";
496 reg = <0 0xfd970000 0 0x1000>;
497 renesas,ipmmu-main = <&ipmmu_mm 9>;
498 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
499 #iommu-cells = <1>;
500 status = "disabled";
501 };
502
503 ipmmu_ir: mmu@ff8b0000 {
504 compatible = "renesas,ipmmu-r8a7795";
505 reg = <0 0xff8b0000 0 0x1000>;
506 renesas,ipmmu-main = <&ipmmu_mm 3>;
507 power-domains = <&sysc R8A7795_PD_A3IR>;
508 #iommu-cells = <1>;
509 status = "disabled";
510 };
511
512 ipmmu_hc: mmu@e6570000 {
513 compatible = "renesas,ipmmu-r8a7795";
514 reg = <0 0xe6570000 0 0x1000>;
515 renesas,ipmmu-main = <&ipmmu_mm 2>;
516 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
517 #iommu-cells = <1>;
518 status = "disabled";
519 };
520
521 ipmmu_rt: mmu@ffc80000 {
522 compatible = "renesas,ipmmu-r8a7795";
523 reg = <0 0xffc80000 0 0x1000>;
524 renesas,ipmmu-main = <&ipmmu_mm 10>;
525 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
526 #iommu-cells = <1>;
527 status = "disabled";
528 };
529
530 ipmmu_mp0: mmu@ec670000 {
531 compatible = "renesas,ipmmu-r8a7795";
532 reg = <0 0xec670000 0 0x1000>;
533 renesas,ipmmu-main = <&ipmmu_mm 4>;
534 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
535 #iommu-cells = <1>;
536 status = "disabled";
537 };
538
539 ipmmu_ds0: mmu@e6740000 {
540 compatible = "renesas,ipmmu-r8a7795";
541 reg = <0 0xe6740000 0 0x1000>;
542 renesas,ipmmu-main = <&ipmmu_mm 0>;
543 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
544 #iommu-cells = <1>;
545 };
546
547 ipmmu_ds1: mmu@e7740000 {
548 compatible = "renesas,ipmmu-r8a7795";
549 reg = <0 0xe7740000 0 0x1000>;
550 renesas,ipmmu-main = <&ipmmu_mm 1>;
551 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
552 #iommu-cells = <1>;
553 };
554
555 ipmmu_mm: mmu@e67b0000 {
556 compatible = "renesas,ipmmu-r8a7795";
557 reg = <0 0xe67b0000 0 0x1000>;
558 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
559 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
560 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
561 #iommu-cells = <1>;
562 };
563
424 dmac0: dma-controller@e6700000 { 564 dmac0: dma-controller@e6700000 {
425 compatible = "renesas,dmac-r8a7795", 565 compatible = "renesas,dmac-r8a7795",
426 "renesas,rcar-dmac"; 566 "renesas,rcar-dmac";
@@ -453,6 +593,14 @@
453 resets = <&cpg 219>; 593 resets = <&cpg 219>;
454 #dma-cells = <1>; 594 #dma-cells = <1>;
455 dma-channels = <16>; 595 dma-channels = <16>;
596 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
597 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
598 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
599 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
600 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
601 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
602 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
603 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
456 }; 604 };
457 605
458 dmac1: dma-controller@e7300000 { 606 dmac1: dma-controller@e7300000 {
@@ -487,6 +635,14 @@
487 resets = <&cpg 218>; 635 resets = <&cpg 218>;
488 #dma-cells = <1>; 636 #dma-cells = <1>;
489 dma-channels = <16>; 637 dma-channels = <16>;
638 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
639 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
640 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
641 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
642 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
643 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
644 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
645 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
490 }; 646 };
491 647
492 dmac2: dma-controller@e7310000 { 648 dmac2: dma-controller@e7310000 {
@@ -521,6 +677,14 @@
521 resets = <&cpg 217>; 677 resets = <&cpg 217>;
522 #dma-cells = <1>; 678 #dma-cells = <1>;
523 dma-channels = <16>; 679 dma-channels = <16>;
680 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
681 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
682 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
683 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
684 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
685 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
686 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
687 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
524 }; 688 };
525 689
526 audma0: dma-controller@ec700000 { 690 audma0: dma-controller@ec700000 {
@@ -555,6 +719,14 @@
555 resets = <&cpg 502>; 719 resets = <&cpg 502>;
556 #dma-cells = <1>; 720 #dma-cells = <1>;
557 dma-channels = <16>; 721 dma-channels = <16>;
722 iommus = <&ipmmu_mp0 0>, <&ipmmu_mp0 1>,
723 <&ipmmu_mp0 2>, <&ipmmu_mp0 3>,
724 <&ipmmu_mp0 4>, <&ipmmu_mp0 5>,
725 <&ipmmu_mp0 6>, <&ipmmu_mp0 7>,
726 <&ipmmu_mp0 8>, <&ipmmu_mp0 9>,
727 <&ipmmu_mp0 10>, <&ipmmu_mp0 11>,
728 <&ipmmu_mp0 12>, <&ipmmu_mp0 13>,
729 <&ipmmu_mp0 14>, <&ipmmu_mp0 15>;
558 }; 730 };
559 731
560 audma1: dma-controller@ec720000 { 732 audma1: dma-controller@ec720000 {
@@ -589,6 +761,14 @@
589 resets = <&cpg 501>; 761 resets = <&cpg 501>;
590 #dma-cells = <1>; 762 #dma-cells = <1>;
591 dma-channels = <16>; 763 dma-channels = <16>;
764 iommus = <&ipmmu_mp0 16>, <&ipmmu_mp0 17>,
765 <&ipmmu_mp0 18>, <&ipmmu_mp0 19>,
766 <&ipmmu_mp0 20>, <&ipmmu_mp0 21>,
767 <&ipmmu_mp0 22>, <&ipmmu_mp0 23>,
768 <&ipmmu_mp0 24>, <&ipmmu_mp0 25>,
769 <&ipmmu_mp0 26>, <&ipmmu_mp0 27>,
770 <&ipmmu_mp0 28>, <&ipmmu_mp0 29>,
771 <&ipmmu_mp0 30>, <&ipmmu_mp0 31>;
592 }; 772 };
593 773
594 avb: ethernet@e6800000 { 774 avb: ethernet@e6800000 {
@@ -631,6 +811,7 @@
631 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 811 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
632 resets = <&cpg 812>; 812 resets = <&cpg 812>;
633 phy-mode = "rgmii-txid"; 813 phy-mode = "rgmii-txid";
814 iommus = <&ipmmu_ds0 16>;
634 #address-cells = <1>; 815 #address-cells = <1>;
635 #size-cells = <0>; 816 #size-cells = <0>;
636 status = "disabled"; 817 status = "disabled";
@@ -1459,6 +1640,7 @@
1459 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1640 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1460 resets = <&cpg 815>; 1641 resets = <&cpg 815>;
1461 status = "disabled"; 1642 status = "disabled";
1643 iommus = <&ipmmu_hc 2>;
1462 }; 1644 };
1463 1645
1464 xhci0: usb@ee000000 { 1646 xhci0: usb@ee000000 {
@@ -1539,7 +1721,8 @@
1539 }; 1721 };
1540 1722
1541 sdhi0: sd@ee100000 { 1723 sdhi0: sd@ee100000 {
1542 compatible = "renesas,sdhi-r8a7795"; 1724 compatible = "renesas,sdhi-r8a7795",
1725 "renesas,rcar-gen3-sdhi";
1543 reg = <0 0xee100000 0 0x2000>; 1726 reg = <0 0xee100000 0 0x2000>;
1544 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 1727 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
1545 clocks = <&cpg CPG_MOD 314>; 1728 clocks = <&cpg CPG_MOD 314>;
@@ -1550,7 +1733,8 @@
1550 }; 1733 };
1551 1734
1552 sdhi1: sd@ee120000 { 1735 sdhi1: sd@ee120000 {
1553 compatible = "renesas,sdhi-r8a7795"; 1736 compatible = "renesas,sdhi-r8a7795",
1737 "renesas,rcar-gen3-sdhi";
1554 reg = <0 0xee120000 0 0x2000>; 1738 reg = <0 0xee120000 0 0x2000>;
1555 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1739 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
1556 clocks = <&cpg CPG_MOD 313>; 1740 clocks = <&cpg CPG_MOD 313>;
@@ -1561,7 +1745,8 @@
1561 }; 1745 };
1562 1746
1563 sdhi2: sd@ee140000 { 1747 sdhi2: sd@ee140000 {
1564 compatible = "renesas,sdhi-r8a7795"; 1748 compatible = "renesas,sdhi-r8a7795",
1749 "renesas,rcar-gen3-sdhi";
1565 reg = <0 0xee140000 0 0x2000>; 1750 reg = <0 0xee140000 0 0x2000>;
1566 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 1751 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
1567 clocks = <&cpg CPG_MOD 312>; 1752 clocks = <&cpg CPG_MOD 312>;
@@ -1572,7 +1757,8 @@
1572 }; 1757 };
1573 1758
1574 sdhi3: sd@ee160000 { 1759 sdhi3: sd@ee160000 {
1575 compatible = "renesas,sdhi-r8a7795"; 1760 compatible = "renesas,sdhi-r8a7795",
1761 "renesas,rcar-gen3-sdhi";
1576 reg = <0 0xee160000 0 0x2000>; 1762 reg = <0 0xee160000 0 0x2000>;
1577 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 1763 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
1578 clocks = <&cpg CPG_MOD 311>; 1764 clocks = <&cpg CPG_MOD 311>;
@@ -1873,6 +2059,7 @@
1873 clocks = <&cpg CPG_MOD 606>; 2059 clocks = <&cpg CPG_MOD 606>;
1874 power-domains = <&sysc R8A7795_PD_A3VP>; 2060 power-domains = <&sysc R8A7795_PD_A3VP>;
1875 resets = <&cpg 606>; 2061 resets = <&cpg 606>;
2062 iommus = <&ipmmu_vp1 7>;
1876 }; 2063 };
1877 2064
1878 fcpf0: fcp@fe950000 { 2065 fcpf0: fcp@fe950000 {
@@ -1881,6 +2068,7 @@
1881 clocks = <&cpg CPG_MOD 615>; 2068 clocks = <&cpg CPG_MOD 615>;
1882 power-domains = <&sysc R8A7795_PD_A3VP>; 2069 power-domains = <&sysc R8A7795_PD_A3VP>;
1883 resets = <&cpg 615>; 2070 resets = <&cpg 615>;
2071 iommus = <&ipmmu_vp0 0>;
1884 }; 2072 };
1885 2073
1886 fcpf1: fcp@fe951000 { 2074 fcpf1: fcp@fe951000 {
@@ -1889,6 +2077,7 @@
1889 clocks = <&cpg CPG_MOD 614>; 2077 clocks = <&cpg CPG_MOD 614>;
1890 power-domains = <&sysc R8A7795_PD_A3VP>; 2078 power-domains = <&sysc R8A7795_PD_A3VP>;
1891 resets = <&cpg 614>; 2079 resets = <&cpg 614>;
2080 iommus = <&ipmmu_vp1 1>;
1892 }; 2081 };
1893 2082
1894 vspbd: vsp@fe960000 { 2083 vspbd: vsp@fe960000 {
@@ -1908,6 +2097,7 @@
1908 clocks = <&cpg CPG_MOD 607>; 2097 clocks = <&cpg CPG_MOD 607>;
1909 power-domains = <&sysc R8A7795_PD_A3VP>; 2098 power-domains = <&sysc R8A7795_PD_A3VP>;
1910 resets = <&cpg 607>; 2099 resets = <&cpg 607>;
2100 iommus = <&ipmmu_vp0 5>;
1911 }; 2101 };
1912 2102
1913 vspi0: vsp@fe9a0000 { 2103 vspi0: vsp@fe9a0000 {
@@ -1927,6 +2117,7 @@
1927 clocks = <&cpg CPG_MOD 611>; 2117 clocks = <&cpg CPG_MOD 611>;
1928 power-domains = <&sysc R8A7795_PD_A3VP>; 2118 power-domains = <&sysc R8A7795_PD_A3VP>;
1929 resets = <&cpg 611>; 2119 resets = <&cpg 611>;
2120 iommus = <&ipmmu_vp0 8>;
1930 }; 2121 };
1931 2122
1932 vspi1: vsp@fe9b0000 { 2123 vspi1: vsp@fe9b0000 {
@@ -1946,6 +2137,7 @@
1946 clocks = <&cpg CPG_MOD 610>; 2137 clocks = <&cpg CPG_MOD 610>;
1947 power-domains = <&sysc R8A7795_PD_A3VP>; 2138 power-domains = <&sysc R8A7795_PD_A3VP>;
1948 resets = <&cpg 610>; 2139 resets = <&cpg 610>;
2140 iommus = <&ipmmu_vp1 9>;
1949 }; 2141 };
1950 2142
1951 vspd0: vsp@fea20000 { 2143 vspd0: vsp@fea20000 {
@@ -1965,6 +2157,7 @@
1965 clocks = <&cpg CPG_MOD 603>; 2157 clocks = <&cpg CPG_MOD 603>;
1966 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2158 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1967 resets = <&cpg 603>; 2159 resets = <&cpg 603>;
2160 iommus = <&ipmmu_vi0 8>;
1968 }; 2161 };
1969 2162
1970 vspd1: vsp@fea28000 { 2163 vspd1: vsp@fea28000 {
@@ -1984,6 +2177,7 @@
1984 clocks = <&cpg CPG_MOD 602>; 2177 clocks = <&cpg CPG_MOD 602>;
1985 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2178 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1986 resets = <&cpg 602>; 2179 resets = <&cpg 602>;
2180 iommus = <&ipmmu_vi0 9>;
1987 }; 2181 };
1988 2182
1989 vspd2: vsp@fea30000 { 2183 vspd2: vsp@fea30000 {
@@ -2003,6 +2197,7 @@
2003 clocks = <&cpg CPG_MOD 601>; 2197 clocks = <&cpg CPG_MOD 601>;
2004 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2198 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
2005 resets = <&cpg 601>; 2199 resets = <&cpg 601>;
2200 iommus = <&ipmmu_vi1 10>;
2006 }; 2201 };
2007 2202
2008 fdp1@fe940000 { 2203 fdp1@fe940000 {
diff --git a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts
index b317be03306e..498c9e807dc4 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts
@@ -1,5 +1,5 @@
1/* 1/*
2 * Device Tree Source for the Salvator-X board 2 * Device Tree Source for the Salvator-X board with R-Car M3-W
3 * 3 *
4 * Copyright (C) 2016 Renesas Electronics Corp. 4 * Copyright (C) 2016 Renesas Electronics Corp.
5 * 5 *
diff --git a/arch/arm64/boot/dts/renesas/r8a7796-salvator-xs.dts b/arch/arm64/boot/dts/renesas/r8a7796-salvator-xs.dts
new file mode 100644
index 000000000000..2c37055efa94
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a7796-salvator-xs.dts
@@ -0,0 +1,58 @@
1/*
2 * Device Tree Source for the Salvator-X 2nd version board with R-Car M3-W
3 *
4 * Copyright (C) 2015-2017 Renesas Electronics Corp.
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11/dts-v1/;
12#include "r8a7796.dtsi"
13#include "salvator-xs.dtsi"
14
15/ {
16 model = "Renesas Salvator-X 2nd version board based on r8a7796";
17 compatible = "renesas,salvator-xs", "renesas,r8a7796";
18
19 memory@48000000 {
20 device_type = "memory";
21 /* first 128MB is reserved for secure area. */
22 reg = <0x0 0x48000000 0x0 0x78000000>;
23 };
24
25 memory@600000000 {
26 device_type = "memory";
27 reg = <0x6 0x00000000 0x0 0x80000000>;
28 };
29};
30
31&du {
32 clocks = <&cpg CPG_MOD 724>,
33 <&cpg CPG_MOD 723>,
34 <&cpg CPG_MOD 722>,
35 <&cpg CPG_MOD 727>,
36 <&versaclock6 1>,
37 <&x21_clk>,
38 <&versaclock6 2>;
39 clock-names = "du.0", "du.1", "du.2", "lvds.0",
40 "dclkin.0", "dclkin.1", "dclkin.2";
41};
42
43&hdmi0 {
44 status = "okay";
45
46 ports {
47 port@1 {
48 reg = <1>;
49 rcar_dw_hdmi0_out: endpoint {
50 remote-endpoint = <&hdmi0_con>;
51 };
52 };
53 };
54};
55
56&hdmi0_con {
57 remote-endpoint = <&rcar_dw_hdmi0_out>;
58};
diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
index f2b2e40c655e..cc0cca7c0494 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
@@ -357,6 +357,100 @@
357 <&a53_3>; 357 <&a53_3>;
358 }; 358 };
359 359
360 ipmmu_vi0: mmu@febd0000 {
361 compatible = "renesas,ipmmu-r8a7796";
362 reg = <0 0xfebd0000 0 0x1000>;
363 renesas,ipmmu-main = <&ipmmu_mm 9>;
364 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
365 #iommu-cells = <1>;
366 };
367
368 ipmmu_vc0: mmu@fe6b0000 {
369 compatible = "renesas,ipmmu-r8a7796";
370 reg = <0 0xfe6b0000 0 0x1000>;
371 renesas,ipmmu-main = <&ipmmu_mm 8>;
372 power-domains = <&sysc R8A7796_PD_A3VC>;
373 #iommu-cells = <1>;
374 status = "disabled";
375 };
376
377 ipmmu_pv0: mmu@fd800000 {
378 compatible = "renesas,ipmmu-r8a7796";
379 reg = <0 0xfd800000 0 0x1000>;
380 renesas,ipmmu-main = <&ipmmu_mm 5>;
381 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
382 #iommu-cells = <1>;
383 };
384
385 ipmmu_pv1: mmu@fd950000 {
386 compatible = "renesas,ipmmu-r8a7796";
387 reg = <0 0xfd950000 0 0x1000>;
388 renesas,ipmmu-main = <&ipmmu_mm 6>;
389 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
390 #iommu-cells = <1>;
391 status = "disabled";
392 };
393
394 ipmmu_ir: mmu@ff8b0000 {
395 compatible = "renesas,ipmmu-r8a7796";
396 reg = <0 0xff8b0000 0 0x1000>;
397 renesas,ipmmu-main = <&ipmmu_mm 3>;
398 power-domains = <&sysc R8A7796_PD_A3IR>;
399 #iommu-cells = <1>;
400 status = "disabled";
401 };
402
403 ipmmu_hc: mmu@e6570000 {
404 compatible = "renesas,ipmmu-r8a7796";
405 reg = <0 0xe6570000 0 0x1000>;
406 renesas,ipmmu-main = <&ipmmu_mm 2>;
407 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
408 #iommu-cells = <1>;
409 status = "disabled";
410 };
411
412 ipmmu_rt: mmu@ffc80000 {
413 compatible = "renesas,ipmmu-r8a7796";
414 reg = <0 0xffc80000 0 0x1000>;
415 renesas,ipmmu-main = <&ipmmu_mm 7>;
416 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
417 #iommu-cells = <1>;
418 status = "disabled";
419 };
420
421 ipmmu_mp: mmu@ec670000 {
422 compatible = "renesas,ipmmu-r8a7796";
423 reg = <0 0xec670000 0 0x1000>;
424 renesas,ipmmu-main = <&ipmmu_mm 4>;
425 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
426 #iommu-cells = <1>;
427 };
428
429 ipmmu_ds0: mmu@e6740000 {
430 compatible = "renesas,ipmmu-r8a7796";
431 reg = <0 0xe6740000 0 0x1000>;
432 renesas,ipmmu-main = <&ipmmu_mm 0>;
433 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
434 #iommu-cells = <1>;
435 };
436
437 ipmmu_ds1: mmu@e7740000 {
438 compatible = "renesas,ipmmu-r8a7796";
439 reg = <0 0xe7740000 0 0x1000>;
440 renesas,ipmmu-main = <&ipmmu_mm 1>;
441 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
442 #iommu-cells = <1>;
443 };
444
445 ipmmu_mm: mmu@e67b0000 {
446 compatible = "renesas,ipmmu-r8a7796";
447 reg = <0 0xe67b0000 0 0x1000>;
448 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
449 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
450 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
451 #iommu-cells = <1>;
452 };
453
360 cpg: clock-controller@e6150000 { 454 cpg: clock-controller@e6150000 {
361 compatible = "renesas,r8a7796-cpg-mssr"; 455 compatible = "renesas,r8a7796-cpg-mssr";
362 reg = <0 0xe6150000 0 0x1000>; 456 reg = <0 0xe6150000 0 0x1000>;
@@ -817,6 +911,7 @@
817 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 911 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
818 resets = <&cpg 812>; 912 resets = <&cpg 812>;
819 phy-mode = "rgmii-txid"; 913 phy-mode = "rgmii-txid";
914 iommus = <&ipmmu_ds0 16>;
820 #address-cells = <1>; 915 #address-cells = <1>;
821 #size-cells = <0>; 916 #size-cells = <0>;
822 status = "disabled"; 917 status = "disabled";
@@ -1101,6 +1196,14 @@
1101 resets = <&cpg 219>; 1196 resets = <&cpg 219>;
1102 #dma-cells = <1>; 1197 #dma-cells = <1>;
1103 dma-channels = <16>; 1198 dma-channels = <16>;
1199 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
1200 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
1201 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
1202 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
1203 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
1204 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
1205 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
1206 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
1104 }; 1207 };
1105 1208
1106 dmac1: dma-controller@e7300000 { 1209 dmac1: dma-controller@e7300000 {
@@ -1135,6 +1238,14 @@
1135 resets = <&cpg 218>; 1238 resets = <&cpg 218>;
1136 #dma-cells = <1>; 1239 #dma-cells = <1>;
1137 dma-channels = <16>; 1240 dma-channels = <16>;
1241 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
1242 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
1243 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
1244 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
1245 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
1246 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
1247 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
1248 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
1138 }; 1249 };
1139 1250
1140 dmac2: dma-controller@e7310000 { 1251 dmac2: dma-controller@e7310000 {
@@ -1169,6 +1280,14 @@
1169 resets = <&cpg 217>; 1280 resets = <&cpg 217>;
1170 #dma-cells = <1>; 1281 #dma-cells = <1>;
1171 dma-channels = <16>; 1282 dma-channels = <16>;
1283 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
1284 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
1285 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
1286 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
1287 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
1288 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
1289 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
1290 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
1172 }; 1291 };
1173 1292
1174 audma0: dma-controller@ec700000 { 1293 audma0: dma-controller@ec700000 {
@@ -1203,6 +1322,14 @@
1203 resets = <&cpg 502>; 1322 resets = <&cpg 502>;
1204 #dma-cells = <1>; 1323 #dma-cells = <1>;
1205 dma-channels = <16>; 1324 dma-channels = <16>;
1325 iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>,
1326 <&ipmmu_mp 2>, <&ipmmu_mp 3>,
1327 <&ipmmu_mp 4>, <&ipmmu_mp 5>,
1328 <&ipmmu_mp 6>, <&ipmmu_mp 7>,
1329 <&ipmmu_mp 8>, <&ipmmu_mp 9>,
1330 <&ipmmu_mp 10>, <&ipmmu_mp 11>,
1331 <&ipmmu_mp 12>, <&ipmmu_mp 13>,
1332 <&ipmmu_mp 14>, <&ipmmu_mp 15>;
1206 }; 1333 };
1207 1334
1208 audma1: dma-controller@ec720000 { 1335 audma1: dma-controller@ec720000 {
@@ -1237,6 +1364,14 @@
1237 resets = <&cpg 501>; 1364 resets = <&cpg 501>;
1238 #dma-cells = <1>; 1365 #dma-cells = <1>;
1239 dma-channels = <16>; 1366 dma-channels = <16>;
1367 iommus = <&ipmmu_mp 16>, <&ipmmu_mp 17>,
1368 <&ipmmu_mp 18>, <&ipmmu_mp 19>,
1369 <&ipmmu_mp 20>, <&ipmmu_mp 21>,
1370 <&ipmmu_mp 22>, <&ipmmu_mp 23>,
1371 <&ipmmu_mp 24>, <&ipmmu_mp 25>,
1372 <&ipmmu_mp 26>, <&ipmmu_mp 27>,
1373 <&ipmmu_mp 28>, <&ipmmu_mp 29>,
1374 <&ipmmu_mp 30>, <&ipmmu_mp 31>;
1240 }; 1375 };
1241 1376
1242 usb_dmac0: dma-controller@e65a0000 { 1377 usb_dmac0: dma-controller@e65a0000 {
@@ -1380,7 +1515,8 @@
1380 }; 1515 };
1381 1516
1382 sdhi0: sd@ee100000 { 1517 sdhi0: sd@ee100000 {
1383 compatible = "renesas,sdhi-r8a7796"; 1518 compatible = "renesas,sdhi-r8a7796",
1519 "renesas,rcar-gen3-sdhi";
1384 reg = <0 0xee100000 0 0x2000>; 1520 reg = <0 0xee100000 0 0x2000>;
1385 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 1521 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
1386 clocks = <&cpg CPG_MOD 314>; 1522 clocks = <&cpg CPG_MOD 314>;
@@ -1391,7 +1527,8 @@
1391 }; 1527 };
1392 1528
1393 sdhi1: sd@ee120000 { 1529 sdhi1: sd@ee120000 {
1394 compatible = "renesas,sdhi-r8a7796"; 1530 compatible = "renesas,sdhi-r8a7796",
1531 "renesas,rcar-gen3-sdhi";
1395 reg = <0 0xee120000 0 0x2000>; 1532 reg = <0 0xee120000 0 0x2000>;
1396 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1533 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
1397 clocks = <&cpg CPG_MOD 313>; 1534 clocks = <&cpg CPG_MOD 313>;
@@ -1402,7 +1539,8 @@
1402 }; 1539 };
1403 1540
1404 sdhi2: sd@ee140000 { 1541 sdhi2: sd@ee140000 {
1405 compatible = "renesas,sdhi-r8a7796"; 1542 compatible = "renesas,sdhi-r8a7796",
1543 "renesas,rcar-gen3-sdhi";
1406 reg = <0 0xee140000 0 0x2000>; 1544 reg = <0 0xee140000 0 0x2000>;
1407 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 1545 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
1408 clocks = <&cpg CPG_MOD 312>; 1546 clocks = <&cpg CPG_MOD 312>;
@@ -1413,7 +1551,8 @@
1413 }; 1551 };
1414 1552
1415 sdhi3: sd@ee160000 { 1553 sdhi3: sd@ee160000 {
1416 compatible = "renesas,sdhi-r8a7796"; 1554 compatible = "renesas,sdhi-r8a7796",
1555 "renesas,rcar-gen3-sdhi";
1417 reg = <0 0xee160000 0 0x2000>; 1556 reg = <0 0xee160000 0 0x2000>;
1418 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 1557 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
1419 clocks = <&cpg CPG_MOD 311>; 1558 clocks = <&cpg CPG_MOD 311>;
@@ -1740,6 +1879,7 @@
1740 clocks = <&cpg CPG_MOD 611>; 1879 clocks = <&cpg CPG_MOD 611>;
1741 power-domains = <&sysc R8A7796_PD_A3VC>; 1880 power-domains = <&sysc R8A7796_PD_A3VC>;
1742 resets = <&cpg 611>; 1881 resets = <&cpg 611>;
1882 iommus = <&ipmmu_vc0 19>;
1743 }; 1883 };
1744 1884
1745 vspd0: vsp@fea20000 { 1885 vspd0: vsp@fea20000 {
@@ -1759,6 +1899,7 @@
1759 clocks = <&cpg CPG_MOD 603>; 1899 clocks = <&cpg CPG_MOD 603>;
1760 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 1900 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1761 resets = <&cpg 603>; 1901 resets = <&cpg 603>;
1902 iommus = <&ipmmu_vi0 8>;
1762 }; 1903 };
1763 1904
1764 vspd1: vsp@fea28000 { 1905 vspd1: vsp@fea28000 {
@@ -1778,6 +1919,7 @@
1778 clocks = <&cpg CPG_MOD 602>; 1919 clocks = <&cpg CPG_MOD 602>;
1779 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 1920 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1780 resets = <&cpg 602>; 1921 resets = <&cpg 602>;
1922 iommus = <&ipmmu_vi0 9>;
1781 }; 1923 };
1782 1924
1783 vspd2: vsp@fea30000 { 1925 vspd2: vsp@fea30000 {
@@ -1797,6 +1939,7 @@
1797 clocks = <&cpg CPG_MOD 601>; 1939 clocks = <&cpg CPG_MOD 601>;
1798 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; 1940 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1799 resets = <&cpg 601>; 1941 resets = <&cpg 601>;
1942 iommus = <&ipmmu_vi0 10>;
1800 }; 1943 };
1801 1944
1802 hdmi0: hdmi@fead0000 { 1945 hdmi0: hdmi@fead0000 {
diff --git a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
index a711e77cc6a5..8fe5c193e049 100644
--- a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
@@ -33,6 +33,17 @@
33 }; 33 };
34}; 34};
35 35
36&avb {
37 renesas,no-ether-link;
38 phy-handle = <&phy0>;
39 status = "okay";
40
41 phy0: ethernet-phy@0 {
42 rxc-skew-ps = <1500>;
43 reg = <0>;
44 };
45};
46
36&extal_clk { 47&extal_clk {
37 clock-frequency = <16666666>; 48 clock-frequency = <16666666>;
38}; 49};
@@ -41,17 +52,11 @@
41 clock-frequency = <32768>; 52 clock-frequency = <32768>;
42}; 53};
43 54
44&scif0 { 55&rwdt {
56 timeout-sec = <60>;
45 status = "okay"; 57 status = "okay";
46}; 58};
47 59
48&avb { 60&scif0 {
49 renesas,no-ether-link;
50 phy-handle = <&phy0>;
51 status = "okay"; 61 status = "okay";
52
53 phy0: ethernet-phy@0 {
54 rxc-skew-ps = <1500>;
55 reg = <0>;
56 };
57}; 62};
diff --git a/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts b/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts
new file mode 100644
index 000000000000..8624ca87d6b2
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts
@@ -0,0 +1,55 @@
1/*
2 * Device Tree Source for the V3M Starter Kit board
3 *
4 * Copyright (C) 2017 Renesas Electronics Corp.
5 * Copyright (C) 2017 Cogent Embedded, Inc.
6 *
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
10 */
11
12/dts-v1/;
13#include "r8a77970.dtsi"
14
15/ {
16 model = "Renesas V3M Starter Kit board";
17 compatible = "renesas,v3msk", "renesas,r8a77970";
18
19 aliases {
20 serial0 = &scif0;
21 };
22
23 chosen {
24 stdout-path = "serial0:115200n8";
25 };
26
27 memory@48000000 {
28 device_type = "memory";
29 /* first 128MB is reserved for secure area. */
30 reg = <0x0 0x48000000 0x0 0x38000000>;
31 };
32};
33
34&avb {
35 renesas,no-ether-link;
36 phy-handle = <&phy0>;
37 status = "okay";
38
39 phy0: ethernet-phy@0 {
40 rxc-skew-ps = <1500>;
41 reg = <0>;
42 };
43};
44
45&extal_clk {
46 clock-frequency = <16666666>;
47};
48
49&extalr_clk {
50 clock-frequency = <32768>;
51};
52
53&scif0 {
54 status = "okay";
55};
diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
index 97e6981938e7..c35a117fc447 100644
--- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
@@ -9,9 +9,10 @@
9 * kind, whether express or implied. 9 * kind, whether express or implied.
10 */ 10 */
11 11
12#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/clock/r8a77970-cpg-mssr.h>
13#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/interrupt-controller/arm-gic.h>
14#include <dt-bindings/clock/renesas-cpg-mssr.h> 14#include <dt-bindings/interrupt-controller/irq.h>
15#include <dt-bindings/power/r8a77970-sysc.h>
15 16
16/ { 17/ {
17 compatible = "renesas,r8a77970"; 18 compatible = "renesas,r8a77970";
@@ -31,15 +32,15 @@
31 device_type = "cpu"; 32 device_type = "cpu";
32 compatible = "arm,cortex-a53", "arm,armv8"; 33 compatible = "arm,cortex-a53", "arm,armv8";
33 reg = <0>; 34 reg = <0>;
34 clocks = <&cpg CPG_CORE 0>; 35 clocks = <&cpg CPG_CORE R8A77970_CLK_Z2>;
35 power-domains = <&sysc 5>; 36 power-domains = <&sysc R8A77970_PD_CA53_CPU0>;
36 next-level-cache = <&L2_CA53>; 37 next-level-cache = <&L2_CA53>;
37 enable-method = "psci"; 38 enable-method = "psci";
38 }; 39 };
39 40
40 L2_CA53: cache-controller { 41 L2_CA53: cache-controller {
41 compatible = "cache"; 42 compatible = "cache";
42 power-domains = <&sysc 21>; 43 power-domains = <&sysc R8A77970_PD_CA53_SCU>;
43 cache-unified; 44 cache-unified;
44 cache-level = <2>; 45 cache-level = <2>;
45 }; 46 };
@@ -87,7 +88,7 @@
87 IRQ_TYPE_LEVEL_HIGH)>; 88 IRQ_TYPE_LEVEL_HIGH)>;
88 clocks = <&cpg CPG_MOD 408>; 89 clocks = <&cpg CPG_MOD 408>;
89 clock-names = "clk"; 90 clock-names = "clk";
90 power-domains = <&sysc 32>; 91 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
91 resets = <&cpg 408>; 92 resets = <&cpg 408>;
92 }; 93 };
93 94
@@ -103,6 +104,16 @@
103 IRQ_TYPE_LEVEL_LOW)>; 104 IRQ_TYPE_LEVEL_LOW)>;
104 }; 105 };
105 106
107 rwdt: watchdog@e6020000 {
108 compatible = "renesas,r8a77970-wdt",
109 "renesas,rcar-gen3-wdt";
110 reg = <0 0xe6020000 0 0x0c>;
111 clocks = <&cpg CPG_MOD 402>;
112 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
113 resets = <&cpg 402>;
114 status = "disabled";
115 };
116
106 cpg: clock-controller@e6150000 { 117 cpg: clock-controller@e6150000 {
107 compatible = "renesas,r8a77970-cpg-mssr"; 118 compatible = "renesas,r8a77970-cpg-mssr";
108 reg = <0 0xe6150000 0 0x1000>; 119 reg = <0 0xe6150000 0 0x1000>;
@@ -124,6 +135,49 @@
124 #power-domain-cells = <1>; 135 #power-domain-cells = <1>;
125 }; 136 };
126 137
138 ipmmu_vi0: mmu@febd0000 {
139 compatible = "renesas,ipmmu-r8a77970";
140 reg = <0 0xfebd0000 0 0x1000>;
141 renesas,ipmmu-main = <&ipmmu_mm 9>;
142 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
143 #iommu-cells = <1>;
144 status = "disabled";
145 };
146
147 ipmmu_ir: mmu@ff8b0000 {
148 compatible = "renesas,ipmmu-r8a77970";
149 reg = <0 0xff8b0000 0 0x1000>;
150 renesas,ipmmu-main = <&ipmmu_mm 3>;
151 power-domains = <&sysc R8A77970_PD_A3IR>;
152 #iommu-cells = <1>;
153 status = "disabled";
154 };
155
156 ipmmu_rt: mmu@ffc80000 {
157 compatible = "renesas,ipmmu-r8a77970";
158 reg = <0 0xffc80000 0 0x1000>;
159 renesas,ipmmu-main = <&ipmmu_mm 7>;
160 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
161 #iommu-cells = <1>;
162 };
163
164 ipmmu_ds1: mmu@e7740000 {
165 compatible = "renesas,ipmmu-r8a77970";
166 reg = <0 0xe7740000 0 0x1000>;
167 renesas,ipmmu-main = <&ipmmu_mm 1>;
168 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
169 #iommu-cells = <1>;
170 };
171
172 ipmmu_mm: mmu@e67b0000 {
173 compatible = "renesas,ipmmu-r8a77970";
174 reg = <0 0xe67b0000 0 0x1000>;
175 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
176 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
177 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
178 #iommu-cells = <1>;
179 };
180
127 intc_ex: interrupt-controller@e61c0000 { 181 intc_ex: interrupt-controller@e61c0000 {
128 compatible = "renesas,intc-ex-r8a77970", "renesas,irqc"; 182 compatible = "renesas,intc-ex-r8a77970", "renesas,irqc";
129 #interrupt-cells = <2>; 183 #interrupt-cells = <2>;
@@ -136,7 +190,7 @@
136 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 190 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
137 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 191 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
138 clocks = <&cpg CPG_MOD 407>; 192 clocks = <&cpg CPG_MOD 407>;
139 power-domains = <&sysc 32>; 193 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
140 resets = <&cpg 407>; 194 resets = <&cpg 407>;
141 }; 195 };
142 196
@@ -163,10 +217,14 @@
163 "ch4", "ch5", "ch6", "ch7"; 217 "ch4", "ch5", "ch6", "ch7";
164 clocks = <&cpg CPG_MOD 218>; 218 clocks = <&cpg CPG_MOD 218>;
165 clock-names = "fck"; 219 clock-names = "fck";
166 power-domains = <&sysc 32>; 220 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
167 resets = <&cpg 218>; 221 resets = <&cpg 218>;
168 #dma-cells = <1>; 222 #dma-cells = <1>;
169 dma-channels = <8>; 223 dma-channels = <8>;
224 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
225 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
226 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
227 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>;
170 }; 228 };
171 229
172 dmac2: dma-controller@e7310000 { 230 dmac2: dma-controller@e7310000 {
@@ -187,10 +245,14 @@
187 "ch4", "ch5", "ch6", "ch7"; 245 "ch4", "ch5", "ch6", "ch7";
188 clocks = <&cpg CPG_MOD 217>; 246 clocks = <&cpg CPG_MOD 217>;
189 clock-names = "fck"; 247 clock-names = "fck";
190 power-domains = <&sysc 32>; 248 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
191 resets = <&cpg 217>; 249 resets = <&cpg 217>;
192 #dma-cells = <1>; 250 #dma-cells = <1>;
193 dma-channels = <8>; 251 dma-channels = <8>;
252 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
253 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
254 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
255 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>;
194 }; 256 };
195 257
196 hscif0: serial@e6540000 { 258 hscif0: serial@e6540000 {
@@ -200,13 +262,13 @@
200 reg = <0 0xe6540000 0 96>; 262 reg = <0 0xe6540000 0 96>;
201 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 263 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
202 clocks = <&cpg CPG_MOD 520>, 264 clocks = <&cpg CPG_MOD 520>,
203 <&cpg CPG_CORE 9>, 265 <&cpg CPG_CORE R8A77970_CLK_S2D1>,
204 <&scif_clk>; 266 <&scif_clk>;
205 clock-names = "fck", "brg_int", "scif_clk"; 267 clock-names = "fck", "brg_int", "scif_clk";
206 dmas = <&dmac1 0x31>, <&dmac1 0x30>, 268 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
207 <&dmac2 0x31>, <&dmac2 0x30>; 269 <&dmac2 0x31>, <&dmac2 0x30>;
208 dma-names = "tx", "rx", "tx", "rx"; 270 dma-names = "tx", "rx", "tx", "rx";
209 power-domains = <&sysc 32>; 271 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
210 resets = <&cpg 520>; 272 resets = <&cpg 520>;
211 status = "disabled"; 273 status = "disabled";
212 }; 274 };
@@ -218,13 +280,13 @@
218 reg = <0 0xe6550000 0 96>; 280 reg = <0 0xe6550000 0 96>;
219 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 281 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
220 clocks = <&cpg CPG_MOD 519>, 282 clocks = <&cpg CPG_MOD 519>,
221 <&cpg CPG_CORE 9>, 283 <&cpg CPG_CORE R8A77970_CLK_S2D1>,
222 <&scif_clk>; 284 <&scif_clk>;
223 clock-names = "fck", "brg_int", "scif_clk"; 285 clock-names = "fck", "brg_int", "scif_clk";
224 dmas = <&dmac1 0x33>, <&dmac1 0x32>, 286 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
225 <&dmac2 0x33>, <&dmac2 0x32>; 287 <&dmac2 0x33>, <&dmac2 0x32>;
226 dma-names = "tx", "rx", "tx", "rx"; 288 dma-names = "tx", "rx", "tx", "rx";
227 power-domains = <&sysc 32>; 289 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
228 resets = <&cpg 519>; 290 resets = <&cpg 519>;
229 status = "disabled"; 291 status = "disabled";
230 }; 292 };
@@ -236,13 +298,13 @@
236 reg = <0 0xe6560000 0 96>; 298 reg = <0 0xe6560000 0 96>;
237 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 299 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
238 clocks = <&cpg CPG_MOD 518>, 300 clocks = <&cpg CPG_MOD 518>,
239 <&cpg CPG_CORE 9>, 301 <&cpg CPG_CORE R8A77970_CLK_S2D1>,
240 <&scif_clk>; 302 <&scif_clk>;
241 clock-names = "fck", "brg_int", "scif_clk"; 303 clock-names = "fck", "brg_int", "scif_clk";
242 dmas = <&dmac1 0x35>, <&dmac1 0x34>, 304 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
243 <&dmac2 0x35>, <&dmac2 0x34>; 305 <&dmac2 0x35>, <&dmac2 0x34>;
244 dma-names = "tx", "rx", "tx", "rx"; 306 dma-names = "tx", "rx", "tx", "rx";
245 power-domains = <&sysc 32>; 307 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
246 resets = <&cpg 518>; 308 resets = <&cpg 518>;
247 status = "disabled"; 309 status = "disabled";
248 }; 310 };
@@ -253,13 +315,13 @@
253 reg = <0 0xe66a0000 0 96>; 315 reg = <0 0xe66a0000 0 96>;
254 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 316 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
255 clocks = <&cpg CPG_MOD 517>, 317 clocks = <&cpg CPG_MOD 517>,
256 <&cpg CPG_CORE 9>, 318 <&cpg CPG_CORE R8A77970_CLK_S2D1>,
257 <&scif_clk>; 319 <&scif_clk>;
258 clock-names = "fck", "brg_int", "scif_clk"; 320 clock-names = "fck", "brg_int", "scif_clk";
259 dmas = <&dmac1 0x37>, <&dmac1 0x36>, 321 dmas = <&dmac1 0x37>, <&dmac1 0x36>,
260 <&dmac2 0x37>, <&dmac2 0x36>; 322 <&dmac2 0x37>, <&dmac2 0x36>;
261 dma-names = "tx", "rx", "tx", "rx"; 323 dma-names = "tx", "rx", "tx", "rx";
262 power-domains = <&sysc 32>; 324 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
263 resets = <&cpg 517>; 325 resets = <&cpg 517>;
264 status = "disabled"; 326 status = "disabled";
265 }; 327 };
@@ -271,13 +333,13 @@
271 reg = <0 0xe6e60000 0 64>; 333 reg = <0 0xe6e60000 0 64>;
272 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 334 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
273 clocks = <&cpg CPG_MOD 207>, 335 clocks = <&cpg CPG_MOD 207>,
274 <&cpg CPG_CORE 9>, 336 <&cpg CPG_CORE R8A77970_CLK_S2D1>,
275 <&scif_clk>; 337 <&scif_clk>;
276 clock-names = "fck", "brg_int", "scif_clk"; 338 clock-names = "fck", "brg_int", "scif_clk";
277 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 339 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
278 <&dmac2 0x51>, <&dmac2 0x50>; 340 <&dmac2 0x51>, <&dmac2 0x50>;
279 dma-names = "tx", "rx", "tx", "rx"; 341 dma-names = "tx", "rx", "tx", "rx";
280 power-domains = <&sysc 32>; 342 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
281 resets = <&cpg 207>; 343 resets = <&cpg 207>;
282 status = "disabled"; 344 status = "disabled";
283 }; 345 };
@@ -289,13 +351,13 @@
289 reg = <0 0xe6e68000 0 64>; 351 reg = <0 0xe6e68000 0 64>;
290 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 352 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
291 clocks = <&cpg CPG_MOD 206>, 353 clocks = <&cpg CPG_MOD 206>,
292 <&cpg CPG_CORE 9>, 354 <&cpg CPG_CORE R8A77970_CLK_S2D1>,
293 <&scif_clk>; 355 <&scif_clk>;
294 clock-names = "fck", "brg_int", "scif_clk"; 356 clock-names = "fck", "brg_int", "scif_clk";
295 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 357 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
296 <&dmac2 0x53>, <&dmac2 0x52>; 358 <&dmac2 0x53>, <&dmac2 0x52>;
297 dma-names = "tx", "rx", "tx", "rx"; 359 dma-names = "tx", "rx", "tx", "rx";
298 power-domains = <&sysc 32>; 360 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
299 resets = <&cpg 206>; 361 resets = <&cpg 206>;
300 status = "disabled"; 362 status = "disabled";
301 }; 363 };
@@ -307,13 +369,13 @@
307 reg = <0 0xe6c50000 0 64>; 369 reg = <0 0xe6c50000 0 64>;
308 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 370 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
309 clocks = <&cpg CPG_MOD 204>, 371 clocks = <&cpg CPG_MOD 204>,
310 <&cpg CPG_CORE 9>, 372 <&cpg CPG_CORE R8A77970_CLK_S2D1>,
311 <&scif_clk>; 373 <&scif_clk>;
312 clock-names = "fck", "brg_int", "scif_clk"; 374 clock-names = "fck", "brg_int", "scif_clk";
313 dmas = <&dmac1 0x57>, <&dmac1 0x56>, 375 dmas = <&dmac1 0x57>, <&dmac1 0x56>,
314 <&dmac2 0x57>, <&dmac2 0x56>; 376 <&dmac2 0x57>, <&dmac2 0x56>;
315 dma-names = "tx", "rx", "tx", "rx"; 377 dma-names = "tx", "rx", "tx", "rx";
316 power-domains = <&sysc 32>; 378 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
317 resets = <&cpg 204>; 379 resets = <&cpg 204>;
318 status = "disabled"; 380 status = "disabled";
319 }; 381 };
@@ -324,13 +386,13 @@
324 reg = <0 0xe6c40000 0 64>; 386 reg = <0 0xe6c40000 0 64>;
325 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 387 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
326 clocks = <&cpg CPG_MOD 203>, 388 clocks = <&cpg CPG_MOD 203>,
327 <&cpg CPG_CORE 9>, 389 <&cpg CPG_CORE R8A77970_CLK_S2D1>,
328 <&scif_clk>; 390 <&scif_clk>;
329 clock-names = "fck", "brg_int", "scif_clk"; 391 clock-names = "fck", "brg_int", "scif_clk";
330 dmas = <&dmac1 0x59>, <&dmac1 0x58>, 392 dmas = <&dmac1 0x59>, <&dmac1 0x58>,
331 <&dmac2 0x59>, <&dmac2 0x58>; 393 <&dmac2 0x59>, <&dmac2 0x58>;
332 dma-names = "tx", "rx", "tx", "rx"; 394 dma-names = "tx", "rx", "tx", "rx";
333 power-domains = <&sysc 32>; 395 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
334 resets = <&cpg 203>; 396 resets = <&cpg 203>;
335 status = "disabled"; 397 status = "disabled";
336 }; 398 };
@@ -372,9 +434,10 @@
372 "ch20", "ch21", "ch22", "ch23", 434 "ch20", "ch21", "ch22", "ch23",
373 "ch24"; 435 "ch24";
374 clocks = <&cpg CPG_MOD 812>; 436 clocks = <&cpg CPG_MOD 812>;
375 power-domains = <&sysc 32>; 437 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
376 resets = <&cpg 812>; 438 resets = <&cpg 812>;
377 phy-mode = "rgmii-id"; 439 phy-mode = "rgmii-id";
440 iommus = <&ipmmu_rt 3>;
378 #address-cells = <1>; 441 #address-cells = <1>;
379 #size-cells = <0>; 442 #size-cells = <0>;
380 }; 443 };
diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
index 788e3afae6e3..cff42cd1a6c8 100644
--- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
@@ -51,6 +51,13 @@
51 clock-frequency = <0>; 51 clock-frequency = <0>;
52 }; 52 };
53 53
54 /* External CAN clock - to be overridden by boards that provide it */
55 can_clk: can {
56 compatible = "fixed-clock";
57 #clock-cells = <0>;
58 clock-frequency = <0>;
59 };
60
54 scif_clk: scif { 61 scif_clk: scif {
55 compatible = "fixed-clock"; 62 compatible = "fixed-clock";
56 #clock-cells = <0>; 63 #clock-cells = <0>;
@@ -108,6 +115,88 @@
108 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 115 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
109 }; 116 };
110 117
118 ipmmu_vi0: mmu@febd0000 {
119 compatible = "renesas,ipmmu-r8a77995";
120 reg = <0 0xfebd0000 0 0x1000>;
121 renesas,ipmmu-main = <&ipmmu_mm 14>;
122 #iommu-cells = <1>;
123 status = "disabled";
124 };
125
126 ipmmu_vp0: mmu@fe990000 {
127 compatible = "renesas,ipmmu-r8a77995";
128 reg = <0 0xfe990000 0 0x1000>;
129 renesas,ipmmu-main = <&ipmmu_mm 16>;
130 #iommu-cells = <1>;
131 status = "disabled";
132 };
133
134 ipmmu_vc0: mmu@fe6b0000 {
135 compatible = "renesas,ipmmu-r8a77995";
136 reg = <0 0xfe6b0000 0 0x1000>;
137 renesas,ipmmu-main = <&ipmmu_mm 12>;
138 #iommu-cells = <1>;
139 status = "disabled";
140 };
141
142 ipmmu_pv0: mmu@fd800000 {
143 compatible = "renesas,ipmmu-r8a77995";
144 reg = <0 0xfd800000 0 0x1000>;
145 renesas,ipmmu-main = <&ipmmu_mm 6>;
146 #iommu-cells = <1>;
147 status = "disabled";
148 };
149
150 ipmmu_hc: mmu@e6570000 {
151 compatible = "renesas,ipmmu-r8a77995";
152 reg = <0 0xe6570000 0 0x1000>;
153 renesas,ipmmu-main = <&ipmmu_mm 2>;
154 #iommu-cells = <1>;
155 status = "disabled";
156 };
157
158 ipmmu_rt: mmu@ffc80000 {
159 compatible = "renesas,ipmmu-r8a77995";
160 reg = <0 0xffc80000 0 0x1000>;
161 renesas,ipmmu-main = <&ipmmu_mm 10>;
162 #iommu-cells = <1>;
163 status = "disabled";
164 };
165
166 ipmmu_mp: mmu@ec670000 {
167 compatible = "renesas,ipmmu-r8a77995";
168 reg = <0 0xec670000 0 0x1000>;
169 renesas,ipmmu-main = <&ipmmu_mm 4>;
170 #iommu-cells = <1>;
171 status = "disabled";
172 };
173
174 ipmmu_ds0: mmu@e6740000 {
175 compatible = "renesas,ipmmu-r8a77995";
176 reg = <0 0xe6740000 0 0x1000>;
177 renesas,ipmmu-main = <&ipmmu_mm 0>;
178 #iommu-cells = <1>;
179 status = "disabled";
180 };
181
182 ipmmu_ds1: mmu@e7740000 {
183 compatible = "renesas,ipmmu-r8a77995";
184 reg = <0 0xe7740000 0 0x1000>;
185 renesas,ipmmu-main = <&ipmmu_mm 1>;
186 #iommu-cells = <1>;
187 status = "disabled";
188 };
189
190 ipmmu_mm: mmu@e67b0000 {
191 compatible = "renesas,ipmmu-r8a77995";
192 reg = <0 0xe67b0000 0 0x1000>;
193 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
194 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
195 #iommu-cells = <1>;
196 status = "disabled";
197 };
198
199
111 cpg: clock-controller@e6150000 { 200 cpg: clock-controller@e6150000 {
112 compatible = "renesas,r8a77995-cpg-mssr"; 201 compatible = "renesas,r8a77995-cpg-mssr";
113 reg = <0 0xe6150000 0 0x1000>; 202 reg = <0 0xe6150000 0 0x1000>;
@@ -155,6 +244,78 @@
155 resets = <&cpg 407>; 244 resets = <&cpg 407>;
156 }; 245 };
157 246
247 dmac0: dma-controller@e6700000 {
248 compatible = "renesas,dmac-r8a77995",
249 "renesas,rcar-dmac";
250 reg = <0 0xe6700000 0 0x10000>;
251 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH
252 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
253 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
254 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
255 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
256 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
257 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
258 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
259 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
260 interrupt-names = "error",
261 "ch0", "ch1", "ch2", "ch3",
262 "ch4", "ch5", "ch6", "ch7";
263 clocks = <&cpg CPG_MOD 219>;
264 clock-names = "fck";
265 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
266 resets = <&cpg 219>;
267 #dma-cells = <1>;
268 dma-channels = <8>;
269 };
270
271 dmac1: dma-controller@e7300000 {
272 compatible = "renesas,dmac-r8a77995",
273 "renesas,rcar-dmac";
274 reg = <0 0xe7300000 0 0x10000>;
275 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
276 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
277 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
278 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
279 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
280 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
281 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
282 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
283 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
284 interrupt-names = "error",
285 "ch0", "ch1", "ch2", "ch3",
286 "ch4", "ch5", "ch6", "ch7";
287 clocks = <&cpg CPG_MOD 218>;
288 clock-names = "fck";
289 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
290 resets = <&cpg 218>;
291 #dma-cells = <1>;
292 dma-channels = <8>;
293 };
294
295 dmac2: dma-controller@e7310000 {
296 compatible = "renesas,dmac-r8a77995",
297 "renesas,rcar-dmac";
298 reg = <0 0xe7310000 0 0x10000>;
299 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH
300 GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH
301 GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH
302 GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH
303 GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH
304 GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH
305 GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH
306 GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH
307 GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>;
308 interrupt-names = "error",
309 "ch0", "ch1", "ch2", "ch3",
310 "ch4", "ch5", "ch6", "ch7";
311 clocks = <&cpg CPG_MOD 217>;
312 clock-names = "fck";
313 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
314 resets = <&cpg 217>;
315 #dma-cells = <1>;
316 dma-channels = <8>;
317 };
318
158 gpio0: gpio@e6050000 { 319 gpio0: gpio@e6050000 {
159 compatible = "renesas,gpio-r8a77995", 320 compatible = "renesas,gpio-r8a77995",
160 "renesas,rcar-gen3-gpio", 321 "renesas,rcar-gen3-gpio",
@@ -267,6 +428,63 @@
267 resets = <&cpg 906>; 428 resets = <&cpg 906>;
268 }; 429 };
269 430
431 can0: can@e6c30000 {
432 compatible = "renesas,can-r8a77995",
433 "renesas,rcar-gen3-can";
434 reg = <0 0xe6c30000 0 0x1000>;
435 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
436 clocks = <&cpg CPG_MOD 916>,
437 <&cpg CPG_CORE R8A77995_CLK_CANFD>,
438 <&can_clk>;
439 clock-names = "clkp1", "clkp2", "can_clk";
440 assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
441 assigned-clock-rates = <40000000>;
442 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
443 resets = <&cpg 916>;
444 status = "disabled";
445 };
446
447 can1: can@e6c38000 {
448 compatible = "renesas,can-r8a77995",
449 "renesas,rcar-gen3-can";
450 reg = <0 0xe6c38000 0 0x1000>;
451 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
452 clocks = <&cpg CPG_MOD 915>,
453 <&cpg CPG_CORE R8A77995_CLK_CANFD>,
454 <&can_clk>;
455 clock-names = "clkp1", "clkp2", "can_clk";
456 assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
457 assigned-clock-rates = <40000000>;
458 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
459 resets = <&cpg 915>;
460 status = "disabled";
461 };
462
463 canfd: can@e66c0000 {
464 compatible = "renesas,r8a77995-canfd",
465 "renesas,rcar-gen3-canfd";
466 reg = <0 0xe66c0000 0 0x8000>;
467 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
468 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
469 clocks = <&cpg CPG_MOD 914>,
470 <&cpg CPG_CORE R8A77995_CLK_CANFD>,
471 <&can_clk>;
472 clock-names = "fck", "canfd", "can_clk";
473 assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
474 assigned-clock-rates = <40000000>;
475 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
476 resets = <&cpg 914>;
477 status = "disabled";
478
479 channel0 {
480 status = "disabled";
481 };
482
483 channel1 {
484 status = "disabled";
485 };
486 };
487
270 avb: ethernet@e6800000 { 488 avb: ethernet@e6800000 {
271 compatible = "renesas,etheravb-r8a77995", 489 compatible = "renesas,etheravb-r8a77995",
272 "renesas,etheravb-rcar-gen3"; 490 "renesas,etheravb-rcar-gen3";
@@ -307,6 +525,7 @@
307 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 525 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
308 resets = <&cpg 812>; 526 resets = <&cpg 812>;
309 phy-mode = "rgmii-txid"; 527 phy-mode = "rgmii-txid";
528 iommus = <&ipmmu_ds0 16>;
310 #address-cells = <1>; 529 #address-cells = <1>;
311 #size-cells = <0>; 530 #size-cells = <0>;
312 status = "disabled"; 531 status = "disabled";
@@ -321,6 +540,9 @@
321 <&cpg CPG_CORE R8A77995_CLK_S3D1C>, 540 <&cpg CPG_CORE R8A77995_CLK_S3D1C>,
322 <&scif_clk>; 541 <&scif_clk>;
323 clock-names = "fck", "brg_int", "scif_clk"; 542 clock-names = "fck", "brg_int", "scif_clk";
543 dmas = <&dmac1 0x13>, <&dmac1 0x12>,
544 <&dmac2 0x13>, <&dmac2 0x12>;
545 dma-names = "tx", "rx", "tx", "rx";
324 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 546 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
325 resets = <&cpg 310>; 547 resets = <&cpg 310>;
326 status = "disabled"; 548 status = "disabled";
@@ -366,6 +588,18 @@
366 status = "disabled"; 588 status = "disabled";
367 }; 589 };
368 590
591 sdhi2: sd@ee140000 {
592 compatible = "renesas,sdhi-r8a77995",
593 "renesas,rcar-gen3-sdhi";
594 reg = <0 0xee140000 0 0x2000>;
595 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
596 clocks = <&cpg CPG_MOD 312>;
597 max-frequency = <200000000>;
598 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
599 resets = <&cpg 312>;
600 status = "disabled";
601 };
602
369 ehci0: usb@ee080100 { 603 ehci0: usb@ee080100 {
370 compatible = "generic-ehci"; 604 compatible = "generic-ehci";
371 reg = <0 0xee080100 0 0x100>; 605 reg = <0 0xee080100 0 0x100>;
diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi b/arch/arm64/boot/dts/renesas/salvator-common.dtsi
index a298df74ca6c..b9505a65a793 100644
--- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi
+++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi
@@ -355,6 +355,30 @@
355 355
356&i2c_dvfs { 356&i2c_dvfs {
357 status = "okay"; 357 status = "okay";
358
359 pmic: pmic@30 {
360 pinctrl-0 = <&irq0_pins>;
361 pinctrl-names = "default";
362
363 compatible = "rohm,bd9571mwv";
364 reg = <0x30>;
365 interrupt-parent = <&intc_ex>;
366 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
367 interrupt-controller;
368 #interrupt-cells = <2>;
369 gpio-controller;
370 #gpio-cells = <2>;
371
372 regulators {
373 dvfs: dvfs {
374 regulator-name = "dvfs";
375 regulator-min-microvolt = <750000>;
376 regulator-max-microvolt = <1030000>;
377 regulator-boot-on;
378 regulator-always-on;
379 };
380 };
381 };
358}; 382};
359 383
360&ohci0 { 384&ohci0 {
@@ -410,6 +434,11 @@
410 function = "i2c2"; 434 function = "i2c2";
411 }; 435 };
412 436
437 irq0_pins: irq0 {
438 groups = "intc_ex_irq0";
439 function = "intc_ex";
440 };
441
413 pwm1_pins: pwm1 { 442 pwm1_pins: pwm1 {
414 groups = "pwm1_a"; 443 groups = "pwm1_a";
415 function = "pwm1"; 444 function = "pwm1";
@@ -596,6 +625,7 @@
596 bus-width = <8>; 625 bus-width = <8>;
597 mmc-hs200-1_8v; 626 mmc-hs200-1_8v;
598 non-removable; 627 non-removable;
628 fixed-emmc-driver-type = <1>;
599 status = "okay"; 629 status = "okay";
600}; 630};
601 631
diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
index 657ad1041965..a4e715cbde87 100644
--- a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
+++ b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
@@ -29,6 +29,7 @@
29}; 29};
30 30
31&ehci0 { 31&ehci0 {
32 dr_mode = "otg";
32 status = "okay"; 33 status = "okay";
33}; 34};
34 35
@@ -41,6 +42,7 @@
41}; 42};
42 43
43&hsusb { 44&hsusb {
45 dr_mode = "otg";
44 status = "okay"; 46 status = "okay";
45}; 47};
46 48
@@ -67,6 +69,20 @@
67 output-high; 69 output-high;
68 line-name = "HUB rst"; 70 line-name = "HUB rst";
69 }; 71 };
72
73 otg_offvbusn {
74 gpio-hog;
75 gpios = <8 GPIO_ACTIVE_HIGH>;
76 output-low;
77 line-name = "OTG OFFVBUSn";
78 };
79
80 otg_extlpn {
81 gpio-hog;
82 gpios = <9 GPIO_ACTIVE_HIGH>;
83 output-high;
84 line-name = "OTG EXTLPn";
85 };
70 }; 86 };
71 87
72 gpio_exp_75: gpio@75 { 88 gpio_exp_75: gpio@75 {
@@ -119,6 +135,7 @@
119}; 135};
120 136
121&ohci0 { 137&ohci0 {
138 dr_mode = "otg";
122 status = "okay"; 139 status = "okay";
123}; 140};
124 141
@@ -154,6 +171,11 @@
154 groups = "scif1_data_b", "scif1_ctrl"; 171 groups = "scif1_data_b", "scif1_ctrl";
155 function = "scif1"; 172 function = "scif1";
156 }; 173 };
174
175 usb0_pins: usb0 {
176 groups = "usb0";
177 function = "usb0";
178 };
157}; 179};
158 180
159&scif1 { 181&scif1 {
@@ -164,6 +186,13 @@
164 status = "okay"; 186 status = "okay";
165}; 187};
166 188
189&usb2_phy0 {
190 pinctrl-0 = <&usb0_pins>;
191 pinctrl-names = "default";
192
193 status = "okay";
194};
195
167&xhci0 { 196&xhci0 {
168 status = "okay"; 197 status = "okay";
169}; 198};
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-22 10:50:02 -0400