aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorOlof Johansson <olof@lixom.net>2016-11-18 19:49:09 -0500
committerOlof Johansson <olof@lixom.net>2016-11-18 19:49:23 -0500
commit6d1e66bb4e4126718091c097e4a1275b0a95bd3d (patch)
tree2d10b74288a02e081018eff08ba4ff14be183d21
parenta9fa1f7c18e22223026f151f563f9770d6923a75 (diff)
parent19944b3a4a30163656b26e9d2ca659657113ac3e (diff)
Merge tag 'omap-for-v4.10/legacy-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/soc
Legacy platform_data removal for omaps for v4.10 merge window. We've dropped the last legacy boot board-*.c files for mach-omap2 for v4.9 so now we can start removing the unused platform_data. All of the below has been unused since v4.9 merge window: - Drop legacy pmic init code - Apply seq_puts() fixes for legacy mux code, then drop it - Drop legacy serial init - Drop legacy i2c init - Drop legacy PM init - Drop legacy twl4030 platform init - Drop legacy USB host init - Drop legacy muxing for tusb6010, n8x0 is still using it's platform init via pdata-quirks.c - Drop legacy musb init - Drop hwmod related legacy mux code - Drop legacy hwmod data for omap3 - Drop legacy smsc911x and smc91x init - Drop legacy board flash init - Drop legacy ads7846 init - Drop legacy sdram timings * tag 'omap-for-v4.10/legacy-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (21 commits) ARM: OMAP2+: Drop legacy sdram timings ARM: OMAP2+: Drop legacy ads7846 init ARM: OMAP2+: Remove legacy board-flash.c ARM: OMAP2+: Remove legacy smsc911x and smc91x GPMC support ARM: OMAP2+: Remove legacy data from hwmod for omap3 ARM: OMAP2+: Remove legacy mux code ARM: OMAP2+: Remove legacy hwmod mux code ARM: OMAP2+: Remove legacy usb-musb.c platform init code ARM: OMAP2+: Remove legacy muxing for usb-tusb6010.c ARM: OMAP2+: Remove legacy usb-host.c platform init code ARM: OMAP2+: Remove legacy twl4030 platform init code ARM: OMAP2+: Remove legacy PM init ARM: OMAP2+: Remove legacy i2c.c platform init code ARM: OMAP2+: Remove legacy serial.c ARM: OMAP2+: mux: Use seq_putc() in omap_mux_dbg_signal_show() ARM: OMAP2+: mux: Replace three seq_printf() calls by seq_puts() ARM: OMAP: kill omap_pmic_init ARM: OMAP2: kill omap2_pmic_init ARM: OMAP3: kill omap3_pmic_init ARM: OMAP3: kill omap3_pmic_get_config and twl_{get,set}_voltage ... Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat
-rw-r--r--arch/arm/mach-omap1/Kconfig26
-rw-r--r--arch/arm/mach-omap1/i2c.c83
-rw-r--r--arch/arm/mach-omap2/Makefile16
-rw-r--r--arch/arm/mach-omap2/board-flash.c242
-rw-r--r--arch/arm/mach-omap2/board-flash.h56
-rw-r--r--arch/arm/mach-omap2/common-board-devices.c102
-rw-r--r--arch/arm/mach-omap2/common-board-devices.h8
-rw-r--r--arch/arm/mach-omap2/common.h9
-rw-r--r--arch/arm/mach-omap2/devices.c1
-rw-r--r--arch/arm/mach-omap2/dss-common.c37
-rw-r--r--arch/arm/mach-omap2/dss-common.h13
-rw-r--r--arch/arm/mach-omap2/gpmc-smsc911x.c100
-rw-r--r--arch/arm/mach-omap2/gpmc-smsc911x.h35
-rw-r--r--arch/arm/mach-omap2/hsmmc.c88
-rw-r--r--arch/arm/mach-omap2/i2c.c97
-rw-r--r--arch/arm/mach-omap2/io.c1
-rw-r--r--arch/arm/mach-omap2/msdi.c1
-rw-r--r--arch/arm/mach-omap2/mux.c1153
-rw-r--r--arch/arm/mach-omap2/mux.h352
-rw-r--r--arch/arm/mach-omap2/mux34xx.c2061
-rw-r--r--arch/arm/mach-omap2/mux34xx.h402
-rw-r--r--arch/arm/mach-omap2/omap_hwmod.c107
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c149
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c201
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c4
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c1
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_3xxx_data.c787
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_common_data.h15
-rw-r--r--arch/arm/mach-omap2/pdata-quirks.c1
-rw-r--r--arch/arm/mach-omap2/pm.c66
-rw-r--r--arch/arm/mach-omap2/sdram-hynix-h8mbx00u0mer-0em.h51
-rw-r--r--arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h55
-rw-r--r--arch/arm/mach-omap2/sdram-nokia.c299
-rw-r--r--arch/arm/mach-omap2/sdram-nokia.h12
-rw-r--r--arch/arm/mach-omap2/sdram-numonyx-m65kxxxxam.h51
-rw-r--r--arch/arm/mach-omap2/sdram-qimonda-hyb18m512160af-6.h54
-rw-r--r--arch/arm/mach-omap2/serial.c332
-rw-r--r--arch/arm/mach-omap2/twl-common.c564
-rw-r--r--arch/arm/mach-omap2/twl-common.h66
-rw-r--r--arch/arm/mach-omap2/usb-host.c496
-rw-r--r--arch/arm/mach-omap2/usb-musb.c106
-rw-r--r--arch/arm/mach-omap2/usb-tusb6010.c21
-rw-r--r--arch/arm/plat-omap/Kconfig26
-rw-r--r--arch/arm/plat-omap/Makefile3
-rw-r--r--arch/arm/plat-omap/i2c.c116
45 files changed, 160 insertions, 8306 deletions
diff --git a/arch/arm/mach-omap1/Kconfig b/arch/arm/mach-omap1/Kconfig
index afb809509140..45c6b733c881 100644
--- a/arch/arm/mach-omap1/Kconfig
+++ b/arch/arm/mach-omap1/Kconfig
@@ -31,6 +31,32 @@ config ARCH_OMAP16XX
31 select ARCH_OMAP_OTG 31 select ARCH_OMAP_OTG
32 select CPU_ARM926T 32 select CPU_ARM926T
33 33
34config OMAP_MUX
35 bool "OMAP multiplexing support"
36 depends on ARCH_OMAP
37 default y
38 help
39 Pin multiplexing support for OMAP boards. If your bootloader
40 sets the multiplexing correctly, say N. Otherwise, or if unsure,
41 say Y.
42
43config OMAP_MUX_DEBUG
44 bool "Multiplexing debug output"
45 depends on OMAP_MUX
46 help
47 Makes the multiplexing functions print out a lot of debug info.
48 This is useful if you want to find out the correct values of the
49 multiplexing registers.
50
51config OMAP_MUX_WARNINGS
52 bool "Warn about pins the bootloader didn't set up"
53 depends on OMAP_MUX
54 default y
55 help
56 Choose Y here to warn whenever driver initialization logic needs
57 to change the pin multiplexing setup. When there are no warnings
58 printed, it's safe to deselect OMAP_MUX for your product.
59
34comment "OMAP Board Type" 60comment "OMAP Board Type"
35 depends on ARCH_OMAP1 61 depends on ARCH_OMAP1
36 62
diff --git a/arch/arm/mach-omap1/i2c.c b/arch/arm/mach-omap1/i2c.c
index 82887d645a6a..32f6c53367bf 100644
--- a/arch/arm/mach-omap1/i2c.c
+++ b/arch/arm/mach-omap1/i2c.c
@@ -19,6 +19,7 @@
19 * 19 *
20 */ 20 */
21 21
22#include <linux/i2c.h>
22#include <linux/i2c-omap.h> 23#include <linux/i2c-omap.h>
23#include <mach/mux.h> 24#include <mach/mux.h>
24#include "soc.h" 25#include "soc.h"
@@ -91,6 +92,88 @@ int __init omap_i2c_add_bus(struct omap_i2c_bus_platform_data *pdata,
91 return platform_device_register(pdev); 92 return platform_device_register(pdev);
92} 93}
93 94
95#define OMAP_I2C_MAX_CONTROLLERS 4
96static struct omap_i2c_bus_platform_data i2c_pdata[OMAP_I2C_MAX_CONTROLLERS];
97
98#define OMAP_I2C_CMDLINE_SETUP (BIT(31))
99
100/**
101 * omap_i2c_bus_setup - Process command line options for the I2C bus speed
102 * @str: String of options
103 *
104 * This function allow to override the default I2C bus speed for given I2C
105 * bus with a command line option.
106 *
107 * Format: i2c_bus=bus_id,clkrate (in kHz)
108 *
109 * Returns 1 on success, 0 otherwise.
110 */
111static int __init omap_i2c_bus_setup(char *str)
112{
113 int ints[3];
114
115 get_options(str, 3, ints);
116 if (ints[0] < 2 || ints[1] < 1 ||
117 ints[1] > OMAP_I2C_MAX_CONTROLLERS)
118 return 0;
119 i2c_pdata[ints[1] - 1].clkrate = ints[2];
120 i2c_pdata[ints[1] - 1].clkrate |= OMAP_I2C_CMDLINE_SETUP;
121
122 return 1;
123}
124__setup("i2c_bus=", omap_i2c_bus_setup);
125
126/*
127 * Register busses defined in command line but that are not registered with
128 * omap_register_i2c_bus from board initialization code.
129 */
130int __init omap_register_i2c_bus_cmdline(void)
131{
132 int i, err = 0;
133
134 for (i = 0; i < ARRAY_SIZE(i2c_pdata); i++)
135 if (i2c_pdata[i].clkrate & OMAP_I2C_CMDLINE_SETUP) {
136 i2c_pdata[i].clkrate &= ~OMAP_I2C_CMDLINE_SETUP;
137 err = omap_i2c_add_bus(&i2c_pdata[i], i + 1);
138 if (err)
139 goto out;
140 }
141
142out:
143 return err;
144}
145
146/**
147 * omap_register_i2c_bus - register I2C bus with device descriptors
148 * @bus_id: bus id counting from number 1
149 * @clkrate: clock rate of the bus in kHz
150 * @info: pointer into I2C device descriptor table or NULL
151 * @len: number of descriptors in the table
152 *
153 * Returns 0 on success or an error code.
154 */
155int __init omap_register_i2c_bus(int bus_id, u32 clkrate,
156 struct i2c_board_info const *info,
157 unsigned len)
158{
159 int err;
160
161 BUG_ON(bus_id < 1 || bus_id > OMAP_I2C_MAX_CONTROLLERS);
162
163 if (info) {
164 err = i2c_register_board_info(bus_id, info, len);
165 if (err)
166 return err;
167 }
168
169 if (!i2c_pdata[bus_id - 1].clkrate)
170 i2c_pdata[bus_id - 1].clkrate = clkrate;
171
172 i2c_pdata[bus_id - 1].clkrate &= ~OMAP_I2C_CMDLINE_SETUP;
173
174 return omap_i2c_add_bus(&i2c_pdata[bus_id - 1], bus_id);
175}
176
94static int __init omap_i2c_cmdline(void) 177static int __init omap_i2c_cmdline(void)
95{ 178{
96 return omap_register_i2c_bus_cmdline(); 179 return omap_register_i2c_bus_cmdline();
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index e37ceb81a379..469894082fea 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -6,7 +6,7 @@ ccflags-y := -I$(srctree)/$(src)/include \
6 -I$(srctree)/arch/arm/plat-omap/include 6 -I$(srctree)/arch/arm/plat-omap/include
7 7
8# Common support 8# Common support
9obj-y := id.o io.o control.o mux.o devices.o fb.o serial.o timer.o pm.o \ 9obj-y := id.o io.o control.o devices.o fb.o timer.o pm.o \
10 common.o gpio.o dma.o wd_timer.o display.o i2c.o hdq1w.o omap_hwmod.o \ 10 common.o gpio.o dma.o wd_timer.o display.o i2c.o hdq1w.o omap_hwmod.o \
11 omap_device.o omap-headsmp.o sram.o drm.o 11 omap_device.o omap-headsmp.o sram.o drm.o
12 12
@@ -63,9 +63,6 @@ obj-$(CONFIG_ARCH_OMAP4) += omap4-restart.o
63obj-$(CONFIG_SOC_OMAP5) += omap4-restart.o 63obj-$(CONFIG_SOC_OMAP5) += omap4-restart.o
64obj-$(CONFIG_SOC_DRA7XX) += omap4-restart.o 64obj-$(CONFIG_SOC_DRA7XX) += omap4-restart.o
65 65
66# Pin multiplexing
67obj-$(CONFIG_ARCH_OMAP3) += mux34xx.o
68
69# SMS/SDRC 66# SMS/SDRC
70obj-$(CONFIG_ARCH_OMAP2) += sdrc2xxx.o 67obj-$(CONFIG_ARCH_OMAP2) += sdrc2xxx.o
71# obj-$(CONFIG_ARCH_OMAP3) += sdrc3xxx.o 68# obj-$(CONFIG_ARCH_OMAP3) += sdrc3xxx.o
@@ -235,26 +232,15 @@ obj-$(CONFIG_MACH_NOKIA_N8X0) += board-n8x0.o
235 232
236# Platform specific device init code 233# Platform specific device init code
237 234
238omap-flash-$(CONFIG_MTD_NAND_OMAP2) := board-flash.o
239omap-flash-$(CONFIG_MTD_ONENAND_OMAP2) := board-flash.o
240obj-y += $(omap-flash-y) $(omap-flash-m)
241
242omap-hsmmc-$(CONFIG_MMC_OMAP_HS) := hsmmc.o 235omap-hsmmc-$(CONFIG_MMC_OMAP_HS) := hsmmc.o
243obj-y += $(omap-hsmmc-m) $(omap-hsmmc-y) 236obj-y += $(omap-hsmmc-m) $(omap-hsmmc-y)
244 237
245obj-y += usb-musb.o
246obj-y += omap_phy_internal.o 238obj-y += omap_phy_internal.o
247 239
248obj-$(CONFIG_MACH_OMAP2_TUSB6010) += usb-tusb6010.o 240obj-$(CONFIG_MACH_OMAP2_TUSB6010) += usb-tusb6010.o
249obj-y += usb-host.o
250 241
251onenand-$(CONFIG_MTD_ONENAND_OMAP2) := gpmc-onenand.o 242onenand-$(CONFIG_MTD_ONENAND_OMAP2) := gpmc-onenand.o
252obj-y += $(onenand-m) $(onenand-y) 243obj-y += $(onenand-m) $(onenand-y)
253 244
254nand-$(CONFIG_MTD_NAND_OMAP2) := gpmc-nand.o 245nand-$(CONFIG_MTD_NAND_OMAP2) := gpmc-nand.o
255obj-y += $(nand-m) $(nand-y) 246obj-y += $(nand-m) $(nand-y)
256
257smsc911x-$(CONFIG_SMSC911X) := gpmc-smsc911x.o
258obj-y += $(smsc911x-m) $(smsc911x-y)
259
260obj-y += common-board-devices.o twl-common.o dss-common.o
diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c
deleted file mode 100644
index 2188dc30e232..000000000000
--- a/arch/arm/mach-omap2/board-flash.c
+++ /dev/null
@@ -1,242 +0,0 @@
1/*
2 * board-flash.c
3 * Modified from mach-omap2/board-3430sdp-flash.c
4 *
5 * Copyright (C) 2009 Nokia Corporation
6 * Copyright (C) 2009 Texas Instruments
7 *
8 * Vimal Singh <vimalsingh@ti.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/kernel.h>
16#include <linux/omap-gpmc.h>
17#include <linux/platform_device.h>
18#include <linux/mtd/physmap.h>
19#include <linux/io.h>
20
21#include <linux/platform_data/mtd-nand-omap2.h>
22#include <linux/platform_data/mtd-onenand-omap2.h>
23
24#include "soc.h"
25#include "common.h"
26#include "board-flash.h"
27
28#define REG_FPGA_REV 0x10
29#define REG_FPGA_DIP_SWITCH_INPUT2 0x60
30#define MAX_SUPPORTED_GPMC_CONFIG 3
31
32#define DEBUG_BASE 0x08000000 /* debug board */
33
34/* various memory sizes */
35#define FLASH_SIZE_SDPV1 SZ_64M /* NOR flash (64 Meg aligned) */
36#define FLASH_SIZE_SDPV2 SZ_128M /* NOR flash (256 Meg aligned) */
37
38static struct physmap_flash_data board_nor_data = {
39 .width = 2,
40};
41
42static struct resource board_nor_resource = {
43 .flags = IORESOURCE_MEM,
44};
45
46static struct platform_device board_nor_device = {
47 .name = "physmap-flash",
48 .id = 0,
49 .dev = {
50 .platform_data = &board_nor_data,
51 },
52 .num_resources = 1,
53 .resource = &board_nor_resource,
54};
55
56static void
57__init board_nor_init(struct mtd_partition *nor_parts, u8 nr_parts, u8 cs)
58{
59 int err;
60
61 board_nor_data.parts = nor_parts;
62 board_nor_data.nr_parts = nr_parts;
63
64 /* Configure start address and size of NOR device */
65 if (omap_rev() >= OMAP3430_REV_ES1_0) {
66 err = gpmc_cs_request(cs, FLASH_SIZE_SDPV2 - 1,
67 (unsigned long *)&board_nor_resource.start);
68 board_nor_resource.end = board_nor_resource.start
69 + FLASH_SIZE_SDPV2 - 1;
70 } else {
71 err = gpmc_cs_request(cs, FLASH_SIZE_SDPV1 - 1,
72 (unsigned long *)&board_nor_resource.start);
73 board_nor_resource.end = board_nor_resource.start
74 + FLASH_SIZE_SDPV1 - 1;
75 }
76 if (err < 0) {
77 pr_err("NOR: Can't request GPMC CS\n");
78 return;
79 }
80 if (platform_device_register(&board_nor_device) < 0)
81 pr_err("Unable to register NOR device\n");
82}
83
84#if IS_ENABLED(CONFIG_MTD_ONENAND_OMAP2)
85static struct omap_onenand_platform_data board_onenand_data = {
86 .dma_channel = -1, /* disable DMA in OMAP OneNAND driver */
87};
88
89void
90__init board_onenand_init(struct mtd_partition *onenand_parts,
91 u8 nr_parts, u8 cs)
92{
93 board_onenand_data.cs = cs;
94 board_onenand_data.parts = onenand_parts;
95 board_onenand_data.nr_parts = nr_parts;
96
97 gpmc_onenand_init(&board_onenand_data);
98}
99#endif /* IS_ENABLED(CONFIG_MTD_ONENAND_OMAP2) */
100
101#if IS_ENABLED(CONFIG_MTD_NAND_OMAP2)
102
103/* Note that all values in this struct are in nanoseconds */
104struct gpmc_timings nand_default_timings[1] = {
105 {
106 .sync_clk = 0,
107
108 .cs_on = 0,
109 .cs_rd_off = 36,
110 .cs_wr_off = 36,
111
112 .we_on = 6,
113 .oe_on = 6,
114
115 .adv_on = 6,
116 .adv_rd_off = 24,
117 .adv_wr_off = 36,
118
119 .we_off = 30,
120 .oe_off = 48,
121
122 .access = 54,
123 .rd_cycle = 72,
124 .wr_cycle = 72,
125
126 .wr_access = 30,
127 .wr_data_mux_bus = 0,
128 },
129};
130
131static struct omap_nand_platform_data board_nand_data;
132
133void
134__init board_nand_init(struct mtd_partition *nand_parts, u8 nr_parts, u8 cs,
135 int nand_type, struct gpmc_timings *gpmc_t)
136{
137 board_nand_data.cs = cs;
138 board_nand_data.parts = nand_parts;
139 board_nand_data.nr_parts = nr_parts;
140 board_nand_data.devsize = nand_type;
141
142 board_nand_data.ecc_opt = OMAP_ECC_HAM1_CODE_SW;
143 gpmc_nand_init(&board_nand_data, gpmc_t);
144}
145#endif /* IS_ENABLED(CONFIG_MTD_NAND_OMAP2) */
146
147/**
148 * get_gpmc0_type - Reads the FPGA DIP_SWITCH_INPUT_REGISTER2 to get
149 * the various cs values.
150 */
151static u8 get_gpmc0_type(void)
152{
153 u8 cs = 0;
154 void __iomem *fpga_map_addr;
155
156 fpga_map_addr = ioremap(DEBUG_BASE, 4096);
157 if (!fpga_map_addr)
158 return -ENOMEM;
159
160 if (!(readw_relaxed(fpga_map_addr + REG_FPGA_REV)))
161 /* we dont have an DEBUG FPGA??? */
162 /* Depend on #defines!! default to strata boot return param */
163 goto unmap;
164
165 /* S8-DIP-OFF = 1, S8-DIP-ON = 0 */
166 cs = readw_relaxed(fpga_map_addr + REG_FPGA_DIP_SWITCH_INPUT2) & 0xf;
167
168 /* ES2.0 SDP's onwards 4 dip switches are provided for CS */
169 if (omap_rev() >= OMAP3430_REV_ES1_0)
170 /* change (S8-1:4=DS-2:0) to (S8-4:1=DS-2:0) */
171 cs = ((cs & 8) >> 3) | ((cs & 4) >> 1) |
172 ((cs & 2) << 1) | ((cs & 1) << 3);
173 else
174 /* change (S8-1:3=DS-2:0) to (S8-3:1=DS-2:0) */
175 cs = ((cs & 4) >> 2) | (cs & 2) | ((cs & 1) << 2);
176unmap:
177 iounmap(fpga_map_addr);
178 return cs;
179}
180
181/**
182 * board_flash_init - Identify devices connected to GPMC and register.
183 *
184 * @return - void.
185 */
186void __init board_flash_init(struct flash_partitions partition_info[],
187 char chip_sel_board[][GPMC_CS_NUM], int nand_type)
188{
189 u8 cs = 0;
190 u8 norcs = GPMC_CS_NUM + 1;
191 u8 nandcs = GPMC_CS_NUM + 1;
192 u8 onenandcs = GPMC_CS_NUM + 1;
193 u8 idx;
194 unsigned char *config_sel = NULL;
195
196 /* REVISIT: Is this return correct idx for 2430 SDP?
197 * for which cs configuration matches for 2430 SDP?
198 */
199 idx = get_gpmc0_type();
200 if (idx >= MAX_SUPPORTED_GPMC_CONFIG) {
201 pr_err("%s: Invalid chip select: %d\n", __func__, cs);
202 return;
203 }
204 config_sel = (unsigned char *)(chip_sel_board[idx]);
205
206 while (cs < GPMC_CS_NUM) {
207 switch (config_sel[cs]) {
208 case PDC_NOR:
209 if (norcs > GPMC_CS_NUM)
210 norcs = cs;
211 break;
212 case PDC_NAND:
213 if (nandcs > GPMC_CS_NUM)
214 nandcs = cs;
215 break;
216 case PDC_ONENAND:
217 if (onenandcs > GPMC_CS_NUM)
218 onenandcs = cs;
219 break;
220 }
221 cs++;
222 }
223
224 if (norcs > GPMC_CS_NUM)
225 pr_err("NOR: Unable to find configuration in GPMC\n");
226 else
227 board_nor_init(partition_info[0].parts,
228 partition_info[0].nr_parts, norcs);
229
230 if (onenandcs > GPMC_CS_NUM)
231 pr_err("OneNAND: Unable to find configuration in GPMC\n");
232 else
233 board_onenand_init(partition_info[1].parts,
234 partition_info[1].nr_parts, onenandcs);
235
236 if (nandcs > GPMC_CS_NUM)
237 pr_err("NAND: Unable to find configuration in GPMC\n");
238 else
239 board_nand_init(partition_info[2].parts,
240 partition_info[2].nr_parts, nandcs,
241 nand_type, nand_default_timings);
242}
diff --git a/arch/arm/mach-omap2/board-flash.h b/arch/arm/mach-omap2/board-flash.h
deleted file mode 100644
index 8b39eec07318..000000000000
--- a/arch/arm/mach-omap2/board-flash.h
+++ /dev/null
@@ -1,56 +0,0 @@
1/*
2 * board-sdp.h
3 *
4 * Information structures for SDP-specific board config data
5 *
6 * Copyright (C) 2009 Nokia Corporation
7 * Copyright (C) 2009 Texas Instruments
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13#include <linux/mtd/mtd.h>
14#include <linux/mtd/partitions.h>
15
16#define PDC_NOR 1
17#define PDC_NAND 2
18#define PDC_ONENAND 3
19#define DBG_MPDB 4
20
21struct flash_partitions {
22 struct mtd_partition *parts;
23 int nr_parts;
24};
25
26#if IS_ENABLED(CONFIG_MTD_NAND_OMAP2) || IS_ENABLED(CONFIG_MTD_ONENAND_OMAP2)
27extern void board_flash_init(struct flash_partitions [],
28 char chip_sel[][GPMC_CS_NUM], int nand_type);
29#else
30static inline void board_flash_init(struct flash_partitions part[],
31 char chip_sel[][GPMC_CS_NUM], int nand_type)
32{
33}
34#endif
35
36#if IS_ENABLED(CONFIG_MTD_NAND_OMAP2)
37extern void board_nand_init(struct mtd_partition *nand_parts,
38 u8 nr_parts, u8 cs, int nand_type, struct gpmc_timings *gpmc_t);
39extern struct gpmc_timings nand_default_timings[];
40#else
41static inline void board_nand_init(struct mtd_partition *nand_parts,
42 u8 nr_parts, u8 cs, int nand_type, struct gpmc_timings *gpmc_t)
43{
44}
45#define nand_default_timings NULL
46#endif
47
48#if IS_ENABLED(CONFIG_MTD_ONENAND_OMAP2)
49extern void board_onenand_init(struct mtd_partition *nand_parts,
50 u8 nr_parts, u8 cs);
51#else
52static inline void board_onenand_init(struct mtd_partition *nand_parts,
53 u8 nr_parts, u8 cs)
54{
55}
56#endif
diff --git a/arch/arm/mach-omap2/common-board-devices.c b/arch/arm/mach-omap2/common-board-devices.c
deleted file mode 100644
index 5388fcd3de72..000000000000
--- a/arch/arm/mach-omap2/common-board-devices.c
+++ /dev/null
@@ -1,102 +0,0 @@
1/*
2 * common-board-devices.c
3 *
4 * Copyright (C) 2011 CompuLab, Ltd.
5 * Author: Mike Rapoport <mike@compulab.co.il>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * version 2 as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
19 * 02110-1301 USA
20 *
21 */
22
23#include <linux/gpio.h>
24#include <linux/spi/spi.h>
25#include <linux/spi/ads7846.h>
26
27#include <linux/platform_data/spi-omap2-mcspi.h>
28
29#include "common.h"
30#include "common-board-devices.h"
31
32#if IS_ENABLED(CONFIG_TOUCHSCREEN_ADS7846)
33static struct omap2_mcspi_device_config ads7846_mcspi_config = {
34 .turbo_mode = 0,
35};
36
37static struct ads7846_platform_data ads7846_config = {
38 .x_max = 0x0fff,
39 .y_max = 0x0fff,
40 .x_plate_ohms = 180,
41 .pressure_max = 255,
42 .debounce_max = 10,
43 .debounce_tol = 3,
44 .debounce_rep = 1,
45 .gpio_pendown = -EINVAL,
46 .keep_vref_on = 1,
47};
48
49static struct spi_board_info ads7846_spi_board_info __initdata = {
50 .modalias = "ads7846",
51 .bus_num = -EINVAL,
52 .chip_select = 0,
53 .max_speed_hz = 1500000,
54 .controller_data = &ads7846_mcspi_config,
55 .irq = -EINVAL,
56 .platform_data = &ads7846_config,
57};
58
59void __init omap_ads7846_init(int bus_num, int gpio_pendown, int gpio_debounce,
60 struct ads7846_platform_data *board_pdata)
61{
62 struct spi_board_info *spi_bi = &ads7846_spi_board_info;
63 int err;
64
65 /*
66 * If a board defines get_pendown_state() function, request the pendown
67 * GPIO and set the GPIO debounce time.
68 * If a board does not define the get_pendown_state() function, then
69 * the ads7846 driver will setup the pendown GPIO itself.
70 */
71 if (board_pdata && board_pdata->get_pendown_state) {
72 err = gpio_request_one(gpio_pendown, GPIOF_IN, "TSPenDown");
73 if (err) {
74 pr_err("Couldn't obtain gpio for TSPenDown: %d\n", err);
75 return;
76 }
77
78 if (gpio_debounce)
79 gpio_set_debounce(gpio_pendown, gpio_debounce);
80
81 gpio_export(gpio_pendown, 0);
82 }
83
84 spi_bi->bus_num = bus_num;
85 spi_bi->irq = gpio_to_irq(gpio_pendown);
86
87 ads7846_config.gpio_pendown = gpio_pendown;
88
89 if (board_pdata) {
90 board_pdata->gpio_pendown = gpio_pendown;
91 board_pdata->gpio_pendown_debounce = gpio_debounce;
92 spi_bi->platform_data = board_pdata;
93 }
94
95 spi_register_board_info(&ads7846_spi_board_info, 1);
96}
97#else
98void __init omap_ads7846_init(int bus_num, int gpio_pendown, int gpio_debounce,
99 struct ads7846_platform_data *board_pdata)
100{
101}
102#endif
diff --git a/arch/arm/mach-omap2/common-board-devices.h b/arch/arm/mach-omap2/common-board-devices.h
index 07c88ae083fb..335c7822fea1 100644
--- a/arch/arm/mach-omap2/common-board-devices.h
+++ b/arch/arm/mach-omap2/common-board-devices.h
@@ -3,15 +3,7 @@
3 3
4#include <sound/tlv320aic3x.h> 4#include <sound/tlv320aic3x.h>
5#include <linux/mfd/menelaus.h> 5#include <linux/mfd/menelaus.h>
6#include "twl-common.h"
7 6
8#define NAND_BLOCK_SIZE SZ_128K
9
10struct mtd_partition;
11struct ads7846_platform_data;
12
13void omap_ads7846_init(int bus_num, int gpio_pendown, int gpio_debounce,
14 struct ads7846_platform_data *board_pdata);
15void *n8x0_legacy_init(void); 7void *n8x0_legacy_init(void);
16 8
17extern struct menelaus_platform_data n8x0_menelaus_platform_data; 9extern struct menelaus_platform_data n8x0_menelaus_platform_data;
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index 6dcca2957e23..14652e78bde7 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -77,15 +77,6 @@ static inline int omap4_pm_init_early(void)
77} 77}
78#endif 78#endif
79 79
80#ifdef CONFIG_OMAP_MUX
81int omap_mux_late_init(void);
82#else
83static inline int omap_mux_late_init(void)
84{
85 return 0;
86}
87#endif
88
89extern void omap2_init_common_infrastructure(void); 80extern void omap2_init_common_infrastructure(void);
90 81
91extern void omap_init_time(void); 82extern void omap_init_time(void);
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 60a20f3b44de..3fdb94599184 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -30,7 +30,6 @@
30 30
31#include "soc.h" 31#include "soc.h"
32#include "common.h" 32#include "common.h"
33#include "mux.h"
34#include "control.h" 33#include "control.h"
35#include "display.h" 34#include "display.h"
36 35
diff --git a/arch/arm/mach-omap2/dss-common.c b/arch/arm/mach-omap2/dss-common.c
deleted file mode 100644
index 1d583bc0b1a9..000000000000
--- a/arch/arm/mach-omap2/dss-common.c
+++ /dev/null
@@ -1,37 +0,0 @@
1/*
2 * Copyright (C) 2012 Texas Instruments, Inc..
3 * Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * version 2 as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
17 * 02110-1301 USA
18 *
19 */
20
21/*
22 * NOTE: this is a transitional file to help with DT adaptation.
23 * This file will be removed when DSS supports DT.
24 */
25
26#include <linux/kernel.h>
27#include <linux/gpio.h>
28#include <linux/platform_device.h>
29
30#include <linux/platform_data/omapdss.h>
31#include <video/omap-panel-data.h>
32
33#include "soc.h"
34#include "dss-common.h"
35#include "mux.h"
36#include "display.h"
37
diff --git a/arch/arm/mach-omap2/dss-common.h b/arch/arm/mach-omap2/dss-common.h
deleted file mode 100644
index a9becf0d5be8..000000000000
--- a/arch/arm/mach-omap2/dss-common.h
+++ /dev/null
@@ -1,13 +0,0 @@
1#ifndef __OMAP_DSS_COMMON__
2#define __OMAP_DSS_COMMON__
3
4/*
5 * NOTE: this is a transitional file to help with DT adaptation.
6 * This file will be removed when DSS supports DT.
7 */
8
9void __init omap4_panda_display_init_of(void);
10void __init omap_4430sdp_display_init_of(void);
11void __init omap3_igep2_display_init_of(void);
12
13#endif
diff --git a/arch/arm/mach-omap2/gpmc-smsc911x.c b/arch/arm/mach-omap2/gpmc-smsc911x.c
deleted file mode 100644
index 2757504a13c4..000000000000
--- a/arch/arm/mach-omap2/gpmc-smsc911x.c
+++ /dev/null
@@ -1,100 +0,0 @@
1/*
2 * linux/arch/arm/mach-omap2/gpmc-smsc911x.c
3 *
4 * Copyright (C) 2009 Li-Pro.Net
5 * Stephan Linz <linz@li-pro.net>
6 *
7 * Modified from linux/arch/arm/mach-omap2/gpmc-smc91x.c
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13#define pr_fmt(fmt) "%s: " fmt, __func__
14
15#include <linux/kernel.h>
16#include <linux/platform_device.h>
17#include <linux/gpio.h>
18#include <linux/delay.h>
19#include <linux/interrupt.h>
20#include <linux/io.h>
21#include <linux/smsc911x.h>
22
23#include "gpmc.h"
24#include "gpmc-smsc911x.h"
25
26static struct resource gpmc_smsc911x_resources[] = {
27 [0] = {
28 .flags = IORESOURCE_MEM,
29 },
30 [1] = {
31 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
32 },
33};
34
35static struct smsc911x_platform_config gpmc_smsc911x_config = {
36 .phy_interface = PHY_INTERFACE_MODE_MII,
37 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
38 .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
39};
40
41/*
42 * Initialize smsc911x device connected to the GPMC. Note that we
43 * assume that pin multiplexing is done in the board-*.c file,
44 * or in the bootloader.
45 */
46void __init gpmc_smsc911x_init(struct omap_smsc911x_platform_data *gpmc_cfg)
47{
48 struct platform_device *pdev;
49 unsigned long cs_mem_base;
50 int ret;
51
52 if (gpmc_cs_request(gpmc_cfg->cs, SZ_16M, &cs_mem_base) < 0) {
53 pr_err("Failed to request GPMC mem region\n");
54 return;
55 }
56
57 gpmc_smsc911x_resources[0].start = cs_mem_base + 0x0;
58 gpmc_smsc911x_resources[0].end = cs_mem_base + 0xff;
59
60 if (gpio_request_one(gpmc_cfg->gpio_irq, GPIOF_IN, "smsc911x irq")) {
61 pr_err("Failed to request IRQ GPIO%d\n", gpmc_cfg->gpio_irq);
62 goto free1;
63 }
64
65 gpmc_smsc911x_resources[1].start = gpio_to_irq(gpmc_cfg->gpio_irq);
66
67 if (gpio_is_valid(gpmc_cfg->gpio_reset)) {
68 ret = gpio_request_one(gpmc_cfg->gpio_reset,
69 GPIOF_OUT_INIT_HIGH, "smsc911x reset");
70 if (ret) {
71 pr_err("Failed to request reset GPIO%d\n",
72 gpmc_cfg->gpio_reset);
73 goto free2;
74 }
75
76 gpio_set_value(gpmc_cfg->gpio_reset, 0);
77 msleep(100);
78 gpio_set_value(gpmc_cfg->gpio_reset, 1);
79 }
80
81 gpmc_smsc911x_config.flags = gpmc_cfg->flags ? : SMSC911X_USE_16BIT;
82
83 pdev = platform_device_register_resndata(NULL, "smsc911x", gpmc_cfg->id,
84 gpmc_smsc911x_resources, ARRAY_SIZE(gpmc_smsc911x_resources),
85 &gpmc_smsc911x_config, sizeof(gpmc_smsc911x_config));
86 if (IS_ERR(pdev)) {
87 pr_err("Unable to register platform device\n");
88 gpio_free(gpmc_cfg->gpio_reset);
89 goto free2;
90 }
91
92 return;
93
94free2:
95 gpio_free(gpmc_cfg->gpio_irq);
96free1:
97 gpmc_cs_free(gpmc_cfg->cs);
98
99 pr_err("Could not initialize smsc911x device\n");
100}
diff --git a/arch/arm/mach-omap2/gpmc-smsc911x.h b/arch/arm/mach-omap2/gpmc-smsc911x.h
deleted file mode 100644
index 99a05b8412fa..000000000000
--- a/arch/arm/mach-omap2/gpmc-smsc911x.h
+++ /dev/null
@@ -1,35 +0,0 @@
1/*
2 * arch/arm/plat-omap/include/plat/gpmc-smsc911x.h
3 *
4 * Copyright (C) 2009 Li-Pro.Net
5 * Stephan Linz <linz@li-pro.net>
6 *
7 * Modified from arch/arm/plat-omap/include/plat/gpmc-smc91x.h
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#ifndef __ASM_ARCH_OMAP_GPMC_SMSC911X_H__
15
16struct omap_smsc911x_platform_data {
17 int id;
18 int cs;
19 int gpio_irq;
20 int gpio_reset;
21 u32 flags;
22};
23
24#if IS_ENABLED(CONFIG_SMSC911X)
25
26extern void gpmc_smsc911x_init(struct omap_smsc911x_platform_data *d);
27
28#else
29
30static inline void gpmc_smsc911x_init(struct omap_smsc911x_platform_data *d)
31{
32}
33
34#endif
35#endif
diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c
index 478097741bce..cb754c46747e 100644
--- a/arch/arm/mach-omap2/hsmmc.c
+++ b/arch/arm/mach-omap2/hsmmc.c
@@ -22,7 +22,6 @@
22#include "omap_device.h" 22#include "omap_device.h"
23#include "omap-pm.h" 23#include "omap-pm.h"
24 24
25#include "mux.h"
26#include "hsmmc.h" 25#include "hsmmc.h"
27#include "control.h" 26#include "control.h"
28 27
@@ -147,91 +146,6 @@ static int nop_mmc_set_power(struct device *dev, int power_on, int vdd)
147 return 0; 146 return 0;
148} 147}
149 148
150static inline void omap_hsmmc_mux(struct omap_hsmmc_platform_data
151 *mmc_controller, int controller_nr)
152{
153 if (gpio_is_valid(mmc_controller->gpio_cd) &&
154 (mmc_controller->gpio_cd < OMAP_MAX_GPIO_LINES))
155 omap_mux_init_gpio(mmc_controller->gpio_cd,
156 OMAP_PIN_INPUT_PULLUP);
157 if (gpio_is_valid(mmc_controller->gpio_cod) &&
158 (mmc_controller->gpio_cod < OMAP_MAX_GPIO_LINES))
159 omap_mux_init_gpio(mmc_controller->gpio_cod,
160 OMAP_PIN_INPUT_PULLUP);
161 if (gpio_is_valid(mmc_controller->gpio_wp) &&
162 (mmc_controller->gpio_wp < OMAP_MAX_GPIO_LINES))
163 omap_mux_init_gpio(mmc_controller->gpio_wp,
164 OMAP_PIN_INPUT_PULLUP);
165 if (cpu_is_omap34xx()) {
166 if (controller_nr == 0) {
167 omap_mux_init_signal("sdmmc1_clk",
168 OMAP_PIN_INPUT_PULLUP);
169 omap_mux_init_signal("sdmmc1_cmd",
170 OMAP_PIN_INPUT_PULLUP);
171 omap_mux_init_signal("sdmmc1_dat0",
172 OMAP_PIN_INPUT_PULLUP);
173 if (mmc_controller->caps &
174 (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
175 omap_mux_init_signal("sdmmc1_dat1",
176 OMAP_PIN_INPUT_PULLUP);
177 omap_mux_init_signal("sdmmc1_dat2",
178 OMAP_PIN_INPUT_PULLUP);
179 omap_mux_init_signal("sdmmc1_dat3",
180 OMAP_PIN_INPUT_PULLUP);
181 }
182 if (mmc_controller->caps &
183 MMC_CAP_8_BIT_DATA) {
184 omap_mux_init_signal("sdmmc1_dat4",
185 OMAP_PIN_INPUT_PULLUP);
186 omap_mux_init_signal("sdmmc1_dat5",
187 OMAP_PIN_INPUT_PULLUP);
188 omap_mux_init_signal("sdmmc1_dat6",
189 OMAP_PIN_INPUT_PULLUP);
190 omap_mux_init_signal("sdmmc1_dat7",
191 OMAP_PIN_INPUT_PULLUP);
192 }
193 }
194 if (controller_nr == 1) {
195 /* MMC2 */
196 omap_mux_init_signal("sdmmc2_clk",
197 OMAP_PIN_INPUT_PULLUP);
198 omap_mux_init_signal("sdmmc2_cmd",
199 OMAP_PIN_INPUT_PULLUP);
200 omap_mux_init_signal("sdmmc2_dat0",
201 OMAP_PIN_INPUT_PULLUP);
202
203 /*
204 * For 8 wire configurations, Lines DAT4, 5, 6 and 7
205 * need to be muxed in the board-*.c files
206 */
207 if (mmc_controller->caps &
208 (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
209 omap_mux_init_signal("sdmmc2_dat1",
210 OMAP_PIN_INPUT_PULLUP);
211 omap_mux_init_signal("sdmmc2_dat2",
212 OMAP_PIN_INPUT_PULLUP);
213 omap_mux_init_signal("sdmmc2_dat3",
214 OMAP_PIN_INPUT_PULLUP);
215 }
216 if (mmc_controller->caps &
217 MMC_CAP_8_BIT_DATA) {
218 omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4",
219 OMAP_PIN_INPUT_PULLUP);
220 omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5",
221 OMAP_PIN_INPUT_PULLUP);
222 omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6",
223 OMAP_PIN_INPUT_PULLUP);
224 omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7",
225 OMAP_PIN_INPUT_PULLUP);
226 }
227 }
228
229 /*
230 * For MMC3 the pins need to be muxed in the board-*.c files
231 */
232 }
233}
234
235static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c, 149static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
236 struct omap_hsmmc_platform_data *mmc) 150 struct omap_hsmmc_platform_data *mmc)
237{ 151{
@@ -410,8 +324,6 @@ static void __init omap_hsmmc_init_one(struct omap2_hsmmc_info *hsmmcinfo,
410 if (res < 0) 324 if (res < 0)
411 goto free_mmc; 325 goto free_mmc;
412 326
413 omap_hsmmc_mux(mmc_data, (ctrl_nr - 1));
414
415 name = "omap_hsmmc"; 327 name = "omap_hsmmc";
416 res = snprintf(oh_name, MAX_OMAP_MMC_HWMOD_NAME_LEN, 328 res = snprintf(oh_name, MAX_OMAP_MMC_HWMOD_NAME_LEN,
417 "mmc%d", ctrl_nr); 329 "mmc%d", ctrl_nr);
diff --git a/arch/arm/mach-omap2/i2c.c b/arch/arm/mach-omap2/i2c.c
index b9d8e47ffe8e..91a21c3923b2 100644
--- a/arch/arm/mach-omap2/i2c.c
+++ b/arch/arm/mach-omap2/i2c.c
@@ -26,7 +26,6 @@
26 26
27#include "prm.h" 27#include "prm.h"
28#include "common.h" 28#include "common.h"
29#include "mux.h"
30#include "i2c.h" 29#include "i2c.h"
31 30
32/* In register I2C_CON, Bit 15 is the I2C enable bit */ 31/* In register I2C_CON, Bit 15 is the I2C enable bit */
@@ -36,20 +35,6 @@
36 35
37#define MAX_OMAP_I2C_HWMOD_NAME_LEN 16 36#define MAX_OMAP_I2C_HWMOD_NAME_LEN 16
38 37
39static void __init omap2_i2c_mux_pins(int bus_id)
40{
41 char mux_name[sizeof("i2c2_scl.i2c2_scl")];
42
43 /* First I2C bus is not muxable */
44 if (bus_id == 1)
45 return;
46
47 sprintf(mux_name, "i2c%i_scl.i2c%i_scl", bus_id, bus_id);
48 omap_mux_init_signal(mux_name, OMAP_PIN_INPUT);
49 sprintf(mux_name, "i2c%i_sda.i2c%i_sda", bus_id, bus_id);
50 omap_mux_init_signal(mux_name, OMAP_PIN_INPUT);
51}
52
53/** 38/**
54 * omap_i2c_reset - reset the omap i2c module. 39 * omap_i2c_reset - reset the omap i2c module.
55 * @oh: struct omap_hwmod * 40 * @oh: struct omap_hwmod *
@@ -107,85 +92,3 @@ int omap_i2c_reset(struct omap_hwmod *oh)
107 92
108 return 0; 93 return 0;
109} 94}
110
111static int __init omap_i2c_nr_ports(void)
112{
113 int ports = 0;
114
115 if (cpu_is_omap24xx())
116 ports = 2;
117 else if (cpu_is_omap34xx())
118 ports = 3;
119 else if (cpu_is_omap44xx())
120 ports = 4;
121 return ports;
122}
123
124/*
125 * XXX This function is a temporary compatibility wrapper - only
126 * needed until the I2C driver can be converted to call
127 * omap_pm_set_max_dev_wakeup_lat() and handle a return code.
128 */
129static void omap_pm_set_max_mpu_wakeup_lat_compat(struct device *dev, long t)
130{
131 omap_pm_set_max_mpu_wakeup_lat(dev, t);
132}
133
134static const char name[] = "omap_i2c";
135
136int __init omap_i2c_add_bus(struct omap_i2c_bus_platform_data *i2c_pdata,
137 int bus_id)
138{
139 int l;
140 struct omap_hwmod *oh;
141 struct platform_device *pdev;
142 char oh_name[MAX_OMAP_I2C_HWMOD_NAME_LEN];
143 struct omap_i2c_bus_platform_data *pdata;
144 struct omap_i2c_dev_attr *dev_attr;
145
146 if (bus_id > omap_i2c_nr_ports())
147 return -EINVAL;
148
149 omap2_i2c_mux_pins(bus_id);
150
151 l = snprintf(oh_name, MAX_OMAP_I2C_HWMOD_NAME_LEN, "i2c%d", bus_id);
152 WARN(l >= MAX_OMAP_I2C_HWMOD_NAME_LEN,
153 "String buffer overflow in I2C%d device setup\n", bus_id);
154 oh = omap_hwmod_lookup(oh_name);
155 if (!oh) {
156 pr_err("Could not look up %s\n", oh_name);
157 return -EEXIST;
158 }
159
160 pdata = i2c_pdata;
161 /*
162 * pass the hwmod class's CPU-specific knowledge of I2C IP revision in
163 * use, and functionality implementation flags, up to the OMAP I2C
164 * driver via platform data
165 */
166 pdata->rev = oh->class->rev;
167
168 dev_attr = (struct omap_i2c_dev_attr *)oh->dev_attr;
169 pdata->flags = dev_attr->flags;
170
171 /*
172 * When waiting for completion of a i2c transfer, we need to
173 * set a wake up latency constraint for the MPU. This is to
174 * ensure quick enough wakeup from idle, when transfer
175 * completes.
176 * Only omap3 has support for constraints
177 */
178 if (cpu_is_omap34xx())
179 pdata->set_mpu_wkup_lat = omap_pm_set_max_mpu_wakeup_lat_compat;
180 pdev = omap_device_build(name, bus_id, oh, pdata,
181 sizeof(struct omap_i2c_bus_platform_data));
182 WARN(IS_ERR(pdev), "Could not build omap_device for %s\n", name);
183
184 return PTR_ERR_OR_ZERO(pdev);
185}
186
187static int __init omap_i2c_cmdline(void)
188{
189 return omap_register_i2c_bus_cmdline();
190}
191omap_subsys_initcall(omap_i2c_cmdline);
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index f0da5259762a..5aafb8449c40 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -427,7 +427,6 @@ static void __init omap_hwmod_init_postsetup(void)
427 427
428static void __init __maybe_unused omap_common_late_init(void) 428static void __init __maybe_unused omap_common_late_init(void)
429{ 429{
430 omap_mux_late_init();
431 omap2_common_pm_late_init(); 430 omap2_common_pm_late_init();
432 omap_soc_device_init(); 431 omap_soc_device_init();
433} 432}
diff --git a/arch/arm/mach-omap2/msdi.c b/arch/arm/mach-omap2/msdi.c
index 8bdf182422bd..5a3bc3de58d0 100644
--- a/arch/arm/mach-omap2/msdi.c
+++ b/arch/arm/mach-omap2/msdi.c
@@ -30,7 +30,6 @@
30#include "control.h" 30#include "control.h"
31#include "omap_hwmod.h" 31#include "omap_hwmod.h"
32#include "omap_device.h" 32#include "omap_device.h"
33#include "mux.h"
34#include "mmc.h" 33#include "mmc.h"
35 34
36/* 35/*
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
deleted file mode 100644
index 176eef6ef338..000000000000
--- a/arch/arm/mach-omap2/mux.c
+++ /dev/null
@@ -1,1153 +0,0 @@
1/*
2 * linux/arch/arm/mach-omap2/mux.c
3 *
4 * OMAP2, OMAP3 and OMAP4 pin multiplexing configurations
5 *
6 * Copyright (C) 2004 - 2010 Texas Instruments Inc.
7 * Copyright (C) 2003 - 2008 Nokia Corporation
8 *
9 * Written by Tony Lindgren
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 *
25 */
26#include <linux/kernel.h>
27#include <linux/init.h>
28#include <linux/io.h>
29#include <linux/list.h>
30#include <linux/slab.h>
31#include <linux/ctype.h>
32#include <linux/debugfs.h>
33#include <linux/seq_file.h>
34#include <linux/uaccess.h>
35#include <linux/irq.h>
36#include <linux/interrupt.h>
37
38
39#include "omap_hwmod.h"
40
41#include "soc.h"
42#include "control.h"
43#include "mux.h"
44#include "prm.h"
45#include "common.h"
46
47#define OMAP_MUX_BASE_OFFSET 0x30 /* Offset from CTRL_BASE */
48#define OMAP_MUX_BASE_SZ 0x5ca
49
50struct omap_mux_entry {
51 struct omap_mux mux;
52 struct list_head node;
53};
54
55static LIST_HEAD(mux_partitions);
56static DEFINE_MUTEX(muxmode_mutex);
57
58struct omap_mux_partition *omap_mux_get(const char *name)
59{
60 struct omap_mux_partition *partition;
61
62 list_for_each_entry(partition, &mux_partitions, node) {
63 if (!strcmp(name, partition->name))
64 return partition;
65 }
66
67 return NULL;
68}
69
70u16 omap_mux_read(struct omap_mux_partition *partition, u16 reg)
71{
72 if (partition->flags & OMAP_MUX_REG_8BIT)
73 return readb_relaxed(partition->base + reg);
74 else
75 return readw_relaxed(partition->base + reg);
76}
77
78void omap_mux_write(struct omap_mux_partition *partition, u16 val,
79 u16 reg)
80{
81 if (partition->flags & OMAP_MUX_REG_8BIT)
82 writeb_relaxed(val, partition->base + reg);
83 else
84 writew_relaxed(val, partition->base + reg);
85}
86
87void omap_mux_write_array(struct omap_mux_partition *partition,
88 struct omap_board_mux *board_mux)
89{
90 if (!board_mux)
91 return;
92
93 while (board_mux->reg_offset != OMAP_MUX_TERMINATOR) {
94 omap_mux_write(partition, board_mux->value,
95 board_mux->reg_offset);
96 board_mux++;
97 }
98}
99
100#ifdef CONFIG_OMAP_MUX
101
102static char *omap_mux_options;
103
104static int __init _omap_mux_init_gpio(struct omap_mux_partition *partition,
105 int gpio, int val)
106{
107 struct omap_mux_entry *e;
108 struct omap_mux *gpio_mux = NULL;
109 u16 old_mode;
110 u16 mux_mode;
111 int found = 0;
112 struct list_head *muxmodes = &partition->muxmodes;
113
114 if (!gpio)
115 return -EINVAL;
116
117 list_for_each_entry(e, muxmodes, node) {
118 struct omap_mux *m = &e->mux;
119 if (gpio == m->gpio) {
120 gpio_mux = m;
121 found++;
122 }
123 }
124
125 if (found == 0) {
126 pr_err("%s: Could not set gpio%i\n", __func__, gpio);
127 return -ENODEV;
128 }
129
130 if (found > 1) {
131 pr_info("%s: Multiple gpio paths (%d) for gpio%i\n", __func__,
132 found, gpio);
133 return -EINVAL;
134 }
135
136 old_mode = omap_mux_read(partition, gpio_mux->reg_offset);
137 mux_mode = val & ~(OMAP_MUX_NR_MODES - 1);
138 mux_mode |= partition->gpio;
139 pr_debug("%s: Setting signal %s.gpio%i 0x%04x -> 0x%04x\n", __func__,
140 gpio_mux->muxnames[0], gpio, old_mode, mux_mode);
141 omap_mux_write(partition, mux_mode, gpio_mux->reg_offset);
142
143 return 0;
144}
145
146int __init omap_mux_init_gpio(int gpio, int val)
147{
148 struct omap_mux_partition *partition;
149 int ret;
150
151 list_for_each_entry(partition, &mux_partitions, node) {
152 ret = _omap_mux_init_gpio(partition, gpio, val);
153 if (!ret)
154 return ret;
155 }
156
157 return -ENODEV;
158}
159
160static int __init _omap_mux_get_by_name(struct omap_mux_partition *partition,
161 const char *muxname,
162 struct omap_mux **found_mux)
163{
164 struct omap_mux *mux = NULL;
165 struct omap_mux_entry *e;
166 const char *mode_name;
167 int found = 0, found_mode = 0, mode0_len = 0;
168 struct list_head *muxmodes = &partition->muxmodes;
169
170 mode_name = strchr(muxname, '.');
171 if (mode_name) {
172 mode0_len = strlen(muxname) - strlen(mode_name);
173 mode_name++;
174 } else {
175 mode_name = muxname;
176 }
177
178 list_for_each_entry(e, muxmodes, node) {
179 char *m0_entry;
180 int i;
181
182 mux = &e->mux;
183 m0_entry = mux->muxnames[0];
184
185 /* First check for full name in mode0.muxmode format */
186 if (mode0_len)
187 if (strncmp(muxname, m0_entry, mode0_len) ||
188 (strlen(m0_entry) != mode0_len))
189 continue;
190
191 /* Then check for muxmode only */
192 for (i = 0; i < OMAP_MUX_NR_MODES; i++) {
193 char *mode_cur = mux->muxnames[i];
194
195 if (!mode_cur)
196 continue;
197
198 if (!strcmp(mode_name, mode_cur)) {
199 *found_mux = mux;
200 found++;
201 found_mode = i;
202 }
203 }
204 }
205
206 if (found == 1) {
207 return found_mode;
208 }
209
210 if (found > 1) {
211 pr_err("%s: Multiple signal paths (%i) for %s\n", __func__,
212 found, muxname);
213 return -EINVAL;
214 }
215
216 return -ENODEV;
217}
218
219int __init omap_mux_get_by_name(const char *muxname,
220 struct omap_mux_partition **found_partition,
221 struct omap_mux **found_mux)
222{
223 struct omap_mux_partition *partition;
224
225 list_for_each_entry(partition, &mux_partitions, node) {
226 struct omap_mux *mux = NULL;
227 int mux_mode = _omap_mux_get_by_name(partition, muxname, &mux);
228 if (mux_mode < 0)
229 continue;
230
231 *found_partition = partition;
232 *found_mux = mux;
233
234 return mux_mode;
235 }
236
237 pr_err("%s: Could not find signal %s\n", __func__, muxname);
238
239 return -ENODEV;
240}
241
242int __init omap_mux_init_signal(const char *muxname, int val)
243{
244 struct omap_mux_partition *partition = NULL;
245 struct omap_mux *mux = NULL;
246 u16 old_mode;
247 int mux_mode;
248
249 mux_mode = omap_mux_get_by_name(muxname, &partition, &mux);
250 if (mux_mode < 0 || !mux)
251 return mux_mode;
252
253 old_mode = omap_mux_read(partition, mux->reg_offset);
254 mux_mode |= val;
255 pr_debug("%s: Setting signal %s 0x%04x -> 0x%04x\n",
256 __func__, muxname, old_mode, mux_mode);
257 omap_mux_write(partition, mux_mode, mux->reg_offset);
258
259 return 0;
260}
261
262struct omap_hwmod_mux_info * __init
263omap_hwmod_mux_init(struct omap_device_pad *bpads, int nr_pads)
264{
265 struct omap_hwmod_mux_info *hmux;
266 int i, nr_pads_dynamic = 0;
267
268 if (!bpads || nr_pads < 1)
269 return NULL;
270
271 hmux = kzalloc(sizeof(struct omap_hwmod_mux_info), GFP_KERNEL);
272 if (!hmux)
273 goto err1;
274
275 hmux->nr_pads = nr_pads;
276
277 hmux->pads = kzalloc(sizeof(struct omap_device_pad) *
278 nr_pads, GFP_KERNEL);
279 if (!hmux->pads)
280 goto err2;
281
282 for (i = 0; i < hmux->nr_pads; i++) {
283 struct omap_mux_partition *partition;
284 struct omap_device_pad *bpad = &bpads[i], *pad = &hmux->pads[i];
285 struct omap_mux *mux;
286 int mux_mode;
287
288 mux_mode = omap_mux_get_by_name(bpad->name, &partition, &mux);
289 if (mux_mode < 0)
290 goto err3;
291 if (!pad->partition)
292 pad->partition = partition;
293 if (!pad->mux)
294 pad->mux = mux;
295
296 pad->name = kzalloc(strlen(bpad->name) + 1, GFP_KERNEL);
297 if (!pad->name) {
298 int j;
299
300 for (j = i - 1; j >= 0; j--)
301 kfree(hmux->pads[j].name);
302 goto err3;
303 }
304 strcpy(pad->name, bpad->name);
305
306 pad->flags = bpad->flags;
307 pad->enable = bpad->enable;
308 pad->idle = bpad->idle;
309 pad->off = bpad->off;
310
311 if (pad->flags &
312 (OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP))
313 nr_pads_dynamic++;
314
315 pr_debug("%s: Initialized %s\n", __func__, pad->name);
316 }
317
318 if (!nr_pads_dynamic)
319 return hmux;
320
321 /*
322 * Add pads that need dynamic muxing into a separate list
323 */
324
325 hmux->nr_pads_dynamic = nr_pads_dynamic;
326 hmux->pads_dynamic = kzalloc(sizeof(struct omap_device_pad *) *
327 nr_pads_dynamic, GFP_KERNEL);
328 if (!hmux->pads_dynamic) {
329 pr_err("%s: Could not allocate dynamic pads\n", __func__);
330 return hmux;
331 }
332
333 nr_pads_dynamic = 0;
334 for (i = 0; i < hmux->nr_pads; i++) {
335 struct omap_device_pad *pad = &hmux->pads[i];
336
337 if (pad->flags &
338 (OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP)) {
339 pr_debug("%s: pad %s tagged dynamic\n",
340 __func__, pad->name);
341 hmux->pads_dynamic[nr_pads_dynamic] = pad;
342 nr_pads_dynamic++;
343 }
344 }
345
346 return hmux;
347
348err3:
349 kfree(hmux->pads);
350err2:
351 kfree(hmux);
352err1:
353 pr_err("%s: Could not allocate device mux entry\n", __func__);
354
355 return NULL;
356}
357
358/**
359 * omap_hwmod_mux_scan_wakeups - omap hwmod scan wakeup pads
360 * @hmux: Pads for a hwmod
361 * @mpu_irqs: MPU irq array for a hwmod
362 *
363 * Scans the wakeup status of pads for a single hwmod. If an irq
364 * array is defined for this mux, the parser will call the registered
365 * ISRs for corresponding pads, otherwise the parser will stop at the
366 * first wakeup active pad and return. Returns true if there is a
367 * pending and non-served wakeup event for the mux, otherwise false.
368 */
369static bool omap_hwmod_mux_scan_wakeups(struct omap_hwmod_mux_info *hmux,
370 struct omap_hwmod_irq_info *mpu_irqs)
371{
372 int i, irq;
373 unsigned int val;
374 u32 handled_irqs = 0;
375
376 for (i = 0; i < hmux->nr_pads_dynamic; i++) {
377 struct omap_device_pad *pad = hmux->pads_dynamic[i];
378
379 if (!(pad->flags & OMAP_DEVICE_PAD_WAKEUP) ||
380 !(pad->idle & OMAP_WAKEUP_EN))
381 continue;
382
383 val = omap_mux_read(pad->partition, pad->mux->reg_offset);
384 if (!(val & OMAP_WAKEUP_EVENT))
385 continue;
386
387 if (!hmux->irqs)
388 return true;
389
390 irq = hmux->irqs[i];
391 /* make sure we only handle each irq once */
392 if (handled_irqs & 1 << irq)
393 continue;
394
395 handled_irqs |= 1 << irq;
396
397 generic_handle_irq(mpu_irqs[irq].irq);
398 }
399
400 return false;
401}
402
403/**
404 * _omap_hwmod_mux_handle_irq - Process wakeup events for a single hwmod
405 *
406 * Checks a single hwmod for every wakeup capable pad to see if there is an
407 * active wakeup event. If this is the case, call the corresponding ISR.
408 */
409static int _omap_hwmod_mux_handle_irq(struct omap_hwmod *oh, void *data)
410{
411 if (!oh->mux || !oh->mux->enabled)
412 return 0;
413 if (omap_hwmod_mux_scan_wakeups(oh->mux, oh->mpu_irqs))
414 generic_handle_irq(oh->mpu_irqs[0].irq);
415 return 0;
416}
417
418/**
419 * omap_hwmod_mux_handle_irq - Process pad wakeup irqs.
420 *
421 * Calls a function for each registered omap_hwmod to check
422 * pad wakeup statuses.
423 */
424static irqreturn_t omap_hwmod_mux_handle_irq(int irq, void *unused)
425{
426 omap_hwmod_for_each(_omap_hwmod_mux_handle_irq, NULL);
427 return IRQ_HANDLED;
428}
429
430/* Assumes the calling function takes care of locking */
431void omap_hwmod_mux(struct omap_hwmod_mux_info *hmux, u8 state)
432{
433 int i;
434
435 /* Runtime idling of dynamic pads */
436 if (state == _HWMOD_STATE_IDLE && hmux->enabled) {
437 for (i = 0; i < hmux->nr_pads_dynamic; i++) {
438 struct omap_device_pad *pad = hmux->pads_dynamic[i];
439 int val = -EINVAL;
440
441 val = pad->idle;
442 omap_mux_write(pad->partition, val,
443 pad->mux->reg_offset);
444 }
445
446 return;
447 }
448
449 /* Runtime enabling of dynamic pads */
450 if ((state == _HWMOD_STATE_ENABLED) && hmux->pads_dynamic
451 && hmux->enabled) {
452 for (i = 0; i < hmux->nr_pads_dynamic; i++) {
453 struct omap_device_pad *pad = hmux->pads_dynamic[i];
454 int val = -EINVAL;
455
456 val = pad->enable;
457 omap_mux_write(pad->partition, val,
458 pad->mux->reg_offset);
459 }
460
461 return;
462 }
463
464 /* Enabling or disabling of all pads */
465 for (i = 0; i < hmux->nr_pads; i++) {
466 struct omap_device_pad *pad = &hmux->pads[i];
467 int flags, val = -EINVAL;
468
469 flags = pad->flags;
470
471 switch (state) {
472 case _HWMOD_STATE_ENABLED:
473 val = pad->enable;
474 pr_debug("%s: Enabling %s %x\n", __func__,
475 pad->name, val);
476 break;
477 case _HWMOD_STATE_DISABLED:
478 /* Use safe mode unless OMAP_DEVICE_PAD_REMUX */
479 if (flags & OMAP_DEVICE_PAD_REMUX)
480 val = pad->off;
481 else
482 val = OMAP_MUX_MODE7;
483 pr_debug("%s: Disabling %s %x\n", __func__,
484 pad->name, val);
485 break;
486 default:
487 /* Nothing to be done */
488 break;
489 }
490
491 if (val >= 0) {
492 omap_mux_write(pad->partition, val,
493 pad->mux->reg_offset);
494 pad->flags = flags;
495 }
496 }
497
498 if (state == _HWMOD_STATE_ENABLED)
499 hmux->enabled = true;
500 else
501 hmux->enabled = false;
502}
503
504#ifdef CONFIG_DEBUG_FS
505
506#define OMAP_MUX_MAX_NR_FLAGS 10
507#define OMAP_MUX_TEST_FLAG(val, mask) \
508 if (((val) & (mask)) == (mask)) { \
509 i++; \
510 flags[i] = #mask; \
511 }
512
513/* REVISIT: Add checking for non-optimal mux settings */
514static inline void omap_mux_decode(struct seq_file *s, u16 val)
515{
516 char *flags[OMAP_MUX_MAX_NR_FLAGS];
517 char mode[sizeof("OMAP_MUX_MODE") + 1];
518 int i = -1;
519
520 sprintf(mode, "OMAP_MUX_MODE%d", val & 0x7);
521 i++;
522 flags[i] = mode;
523
524 OMAP_MUX_TEST_FLAG(val, OMAP_PIN_OFF_WAKEUPENABLE);
525 if (val & OMAP_OFF_EN) {
526 if (!(val & OMAP_OFFOUT_EN)) {
527 if (!(val & OMAP_OFF_PULL_UP)) {
528 OMAP_MUX_TEST_FLAG(val,
529 OMAP_PIN_OFF_INPUT_PULLDOWN);
530 } else {
531 OMAP_MUX_TEST_FLAG(val,
532 OMAP_PIN_OFF_INPUT_PULLUP);
533 }
534 } else {
535 if (!(val & OMAP_OFFOUT_VAL)) {
536 OMAP_MUX_TEST_FLAG(val,
537 OMAP_PIN_OFF_OUTPUT_LOW);
538 } else {
539 OMAP_MUX_TEST_FLAG(val,
540 OMAP_PIN_OFF_OUTPUT_HIGH);
541 }
542 }
543 }
544
545 if (val & OMAP_INPUT_EN) {
546 if (val & OMAP_PULL_ENA) {
547 if (!(val & OMAP_PULL_UP)) {
548 OMAP_MUX_TEST_FLAG(val,
549 OMAP_PIN_INPUT_PULLDOWN);
550 } else {
551 OMAP_MUX_TEST_FLAG(val, OMAP_PIN_INPUT_PULLUP);
552 }
553 } else {
554 OMAP_MUX_TEST_FLAG(val, OMAP_PIN_INPUT);
555 }
556 } else {
557 i++;
558 flags[i] = "OMAP_PIN_OUTPUT";
559 }
560
561 do {
562 seq_printf(s, "%s", flags[i]);
563 if (i > 0)
564 seq_printf(s, " | ");
565 } while (i-- > 0);
566}
567
568#define OMAP_MUX_DEFNAME_LEN 32
569
570static int omap_mux_dbg_board_show(struct seq_file *s, void *unused)
571{
572 struct omap_mux_partition *partition = s->private;
573 struct omap_mux_entry *e;
574 u8 omap_gen = omap_rev() >> 28;
575
576 list_for_each_entry(e, &partition->muxmodes, node) {
577 struct omap_mux *m = &e->mux;
578 char m0_def[OMAP_MUX_DEFNAME_LEN];
579 char *m0_name = m->muxnames[0];
580 u16 val;
581 int i, mode;
582
583 if (!m0_name)
584 continue;
585
586 /* REVISIT: Needs to be updated if mode0 names get longer */
587 for (i = 0; i < OMAP_MUX_DEFNAME_LEN; i++) {
588 if (m0_name[i] == '\0') {
589 m0_def[i] = m0_name[i];
590 break;
591 }
592 m0_def[i] = toupper(m0_name[i]);
593 }
594 val = omap_mux_read(partition, m->reg_offset);
595 mode = val & OMAP_MUX_MODE7;
596 if (mode != 0)
597 seq_printf(s, "/* %s */\n", m->muxnames[mode]);
598
599 /*
600 * XXX: Might be revisited to support differences across
601 * same OMAP generation.
602 */
603 seq_printf(s, "OMAP%d_MUX(%s, ", omap_gen, m0_def);
604 omap_mux_decode(s, val);
605 seq_printf(s, "),\n");
606 }
607
608 return 0;
609}
610
611static int omap_mux_dbg_board_open(struct inode *inode, struct file *file)
612{
613 return single_open(file, omap_mux_dbg_board_show, inode->i_private);
614}
615
616static const struct file_operations omap_mux_dbg_board_fops = {
617 .open = omap_mux_dbg_board_open,
618 .read = seq_read,
619 .llseek = seq_lseek,
620 .release = single_release,
621};
622
623static struct omap_mux_partition *omap_mux_get_partition(struct omap_mux *mux)
624{
625 struct omap_mux_partition *partition;
626
627 list_for_each_entry(partition, &mux_partitions, node) {
628 struct list_head *muxmodes = &partition->muxmodes;
629 struct omap_mux_entry *e;
630
631 list_for_each_entry(e, muxmodes, node) {
632 struct omap_mux *m = &e->mux;
633
634 if (m == mux)
635 return partition;
636 }
637 }
638
639 return NULL;
640}
641
642static int omap_mux_dbg_signal_show(struct seq_file *s, void *unused)
643{
644 struct omap_mux *m = s->private;
645 struct omap_mux_partition *partition;
646 const char *none = "NA";
647 u16 val;
648 int mode;
649
650 partition = omap_mux_get_partition(m);
651 if (!partition)
652 return 0;
653
654 val = omap_mux_read(partition, m->reg_offset);
655 mode = val & OMAP_MUX_MODE7;
656
657 seq_printf(s, "name: %s.%s (0x%08x/0x%03x = 0x%04x), b %s, t %s\n",
658 m->muxnames[0], m->muxnames[mode],
659 partition->phys + m->reg_offset, m->reg_offset, val,
660 m->balls[0] ? m->balls[0] : none,
661 m->balls[1] ? m->balls[1] : none);
662 seq_printf(s, "mode: ");
663 omap_mux_decode(s, val);
664 seq_printf(s, "\n");
665 seq_printf(s, "signals: %s | %s | %s | %s | %s | %s | %s | %s\n",
666 m->muxnames[0] ? m->muxnames[0] : none,
667 m->muxnames[1] ? m->muxnames[1] : none,
668 m->muxnames[2] ? m->muxnames[2] : none,
669 m->muxnames[3] ? m->muxnames[3] : none,
670 m->muxnames[4] ? m->muxnames[4] : none,
671 m->muxnames[5] ? m->muxnames[5] : none,
672 m->muxnames[6] ? m->muxnames[6] : none,
673 m->muxnames[7] ? m->muxnames[7] : none);
674
675 return 0;
676}
677
678#define OMAP_MUX_MAX_ARG_CHAR 7
679
680static ssize_t omap_mux_dbg_signal_write(struct file *file,
681 const char __user *user_buf,
682 size_t count, loff_t *ppos)
683{
684 struct seq_file *seqf;
685 struct omap_mux *m;
686 u16 val;
687 int ret;
688 struct omap_mux_partition *partition;
689
690 if (count > OMAP_MUX_MAX_ARG_CHAR)
691 return -EINVAL;
692
693 ret = kstrtou16_from_user(user_buf, count, 0x10, &val);
694 if (ret < 0)
695 return ret;
696
697 seqf = file->private_data;
698 m = seqf->private;
699
700 partition = omap_mux_get_partition(m);
701 if (!partition)
702 return -ENODEV;
703
704 omap_mux_write(partition, val, m->reg_offset);
705 *ppos += count;
706
707 return count;
708}
709
710static int omap_mux_dbg_signal_open(struct inode *inode, struct file *file)
711{
712 return single_open(file, omap_mux_dbg_signal_show, inode->i_private);
713}
714
715static const struct file_operations omap_mux_dbg_signal_fops = {
716 .open = omap_mux_dbg_signal_open,
717 .read = seq_read,
718 .write = omap_mux_dbg_signal_write,
719 .llseek = seq_lseek,
720 .release = single_release,
721};
722
723static struct dentry *mux_dbg_dir;
724
725static void __init omap_mux_dbg_create_entry(
726 struct omap_mux_partition *partition,
727 struct dentry *mux_dbg_dir)
728{
729 struct omap_mux_entry *e;
730
731 list_for_each_entry(e, &partition->muxmodes, node) {
732 struct omap_mux *m = &e->mux;
733
734 (void)debugfs_create_file(m->muxnames[0], S_IWUSR | S_IRUGO,
735 mux_dbg_dir, m,
736 &omap_mux_dbg_signal_fops);
737 }
738}
739
740static void __init omap_mux_dbg_init(void)
741{
742 struct omap_mux_partition *partition;
743 static struct dentry *mux_dbg_board_dir;
744
745 mux_dbg_dir = debugfs_create_dir("omap_mux", NULL);
746 if (!mux_dbg_dir)
747 return;
748
749 mux_dbg_board_dir = debugfs_create_dir("board", mux_dbg_dir);
750 if (!mux_dbg_board_dir)
751 return;
752
753 list_for_each_entry(partition, &mux_partitions, node) {
754 omap_mux_dbg_create_entry(partition, mux_dbg_dir);
755 (void)debugfs_create_file(partition->name, S_IRUGO,
756 mux_dbg_board_dir, partition,
757 &omap_mux_dbg_board_fops);
758 }
759}
760
761#else
762static inline void omap_mux_dbg_init(void)
763{
764}
765#endif /* CONFIG_DEBUG_FS */
766
767static void __init omap_mux_free_names(struct omap_mux *m)
768{
769 int i;
770
771 for (i = 0; i < OMAP_MUX_NR_MODES; i++)
772 kfree(m->muxnames[i]);
773
774#ifdef CONFIG_DEBUG_FS
775 for (i = 0; i < OMAP_MUX_NR_SIDES; i++)
776 kfree(m->balls[i]);
777#endif
778
779}
780
781/* Free all data except for GPIO pins unless CONFIG_DEBUG_FS is set */
782int __init omap_mux_late_init(void)
783{
784 struct omap_mux_partition *partition;
785 int ret;
786
787 list_for_each_entry(partition, &mux_partitions, node) {
788 struct omap_mux_entry *e, *tmp;
789 list_for_each_entry_safe(e, tmp, &partition->muxmodes, node) {
790 struct omap_mux *m = &e->mux;
791 u16 mode = omap_mux_read(partition, m->reg_offset);
792
793 if (OMAP_MODE_GPIO(partition, mode))
794 continue;
795
796#ifndef CONFIG_DEBUG_FS
797 mutex_lock(&muxmode_mutex);
798 list_del(&e->node);
799 mutex_unlock(&muxmode_mutex);
800 omap_mux_free_names(m);
801 kfree(m);
802#endif
803 }
804 }
805
806 omap_mux_dbg_init();
807
808 /* see pinctrl-single-omap for the wake-up interrupt handling */
809 if (of_have_populated_dt())
810 return 0;
811
812 ret = request_irq(omap_prcm_event_to_irq("io"),
813 omap_hwmod_mux_handle_irq, IRQF_SHARED | IRQF_NO_SUSPEND,
814 "hwmod_io", omap_mux_late_init);
815
816 if (ret)
817 pr_warn("mux: Failed to setup hwmod io irq %d\n", ret);
818
819 return 0;
820}
821
822static void __init omap_mux_package_fixup(struct omap_mux *p,
823 struct omap_mux *superset)
824{
825 while (p->reg_offset != OMAP_MUX_TERMINATOR) {
826 struct omap_mux *s = superset;
827 int found = 0;
828
829 while (s->reg_offset != OMAP_MUX_TERMINATOR) {
830 if (s->reg_offset == p->reg_offset) {
831 *s = *p;
832 found++;
833 break;
834 }
835 s++;
836 }
837 if (!found)
838 pr_err("%s: Unknown entry offset 0x%x\n", __func__,
839 p->reg_offset);
840 p++;
841 }
842}
843
844#ifdef CONFIG_DEBUG_FS
845
846static void __init omap_mux_package_init_balls(struct omap_ball *b,
847 struct omap_mux *superset)
848{
849 while (b->reg_offset != OMAP_MUX_TERMINATOR) {
850 struct omap_mux *s = superset;
851 int found = 0;
852
853 while (s->reg_offset != OMAP_MUX_TERMINATOR) {
854 if (s->reg_offset == b->reg_offset) {
855 s->balls[0] = b->balls[0];
856 s->balls[1] = b->balls[1];
857 found++;
858 break;
859 }
860 s++;
861 }
862 if (!found)
863 pr_err("%s: Unknown ball offset 0x%x\n", __func__,
864 b->reg_offset);
865 b++;
866 }
867}
868
869#else /* CONFIG_DEBUG_FS */
870
871static inline void omap_mux_package_init_balls(struct omap_ball *b,
872 struct omap_mux *superset)
873{
874}
875
876#endif /* CONFIG_DEBUG_FS */
877
878static int __init omap_mux_setup(char *options)
879{
880 if (!options)
881 return 0;
882
883 omap_mux_options = options;
884
885 return 1;
886}
887__setup("omap_mux=", omap_mux_setup);
888
889/*
890 * Note that the omap_mux=some.signal1=0x1234,some.signal2=0x1234
891 * cmdline options only override the bootloader values.
892 * During development, please enable CONFIG_DEBUG_FS, and use the
893 * signal specific entries under debugfs.
894 */
895static void __init omap_mux_set_cmdline_signals(void)
896{
897 char *options, *next_opt, *token;
898
899 if (!omap_mux_options)
900 return;
901
902 options = kstrdup(omap_mux_options, GFP_KERNEL);
903 if (!options)
904 return;
905
906 next_opt = options;
907
908 while ((token = strsep(&next_opt, ",")) != NULL) {
909 char *keyval, *name;
910 u16 val;
911
912 keyval = token;
913 name = strsep(&keyval, "=");
914 if (name) {
915 int res;
916
917 res = kstrtou16(keyval, 0x10, &val);
918 if (res < 0)
919 continue;
920
921 omap_mux_init_signal(name, (u16)val);
922 }
923 }
924
925 kfree(options);
926}
927
928static int __init omap_mux_copy_names(struct omap_mux *src,
929 struct omap_mux *dst)
930{
931 int i;
932
933 for (i = 0; i < OMAP_MUX_NR_MODES; i++) {
934 if (src->muxnames[i]) {
935 dst->muxnames[i] = kstrdup(src->muxnames[i],
936 GFP_KERNEL);
937 if (!dst->muxnames[i])
938 goto free;
939 }
940 }
941
942#ifdef CONFIG_DEBUG_FS
943 for (i = 0; i < OMAP_MUX_NR_SIDES; i++) {
944 if (src->balls[i]) {
945 dst->balls[i] = kstrdup(src->balls[i], GFP_KERNEL);
946 if (!dst->balls[i])
947 goto free;
948 }
949 }
950#endif
951
952 return 0;
953
954free:
955 omap_mux_free_names(dst);
956 return -ENOMEM;
957
958}
959
960#endif /* CONFIG_OMAP_MUX */
961
962static struct omap_mux *omap_mux_get_by_gpio(
963 struct omap_mux_partition *partition,
964 int gpio)
965{
966 struct omap_mux_entry *e;
967 struct omap_mux *ret = NULL;
968
969 list_for_each_entry(e, &partition->muxmodes, node) {
970 struct omap_mux *m = &e->mux;
971 if (m->gpio == gpio) {
972 ret = m;
973 break;
974 }
975 }
976
977 return ret;
978}
979
980/* Needed for dynamic muxing of GPIO pins for off-idle */
981u16 omap_mux_get_gpio(int gpio)
982{
983 struct omap_mux_partition *partition;
984 struct omap_mux *m = NULL;
985
986 list_for_each_entry(partition, &mux_partitions, node) {
987 m = omap_mux_get_by_gpio(partition, gpio);
988 if (m)
989 return omap_mux_read(partition, m->reg_offset);
990 }
991
992 if (!m || m->reg_offset == OMAP_MUX_TERMINATOR)
993 pr_err("%s: Could not get gpio%i\n", __func__, gpio);
994
995 return OMAP_MUX_TERMINATOR;
996}
997
998/* Needed for dynamic muxing of GPIO pins for off-idle */
999void omap_mux_set_gpio(u16 val, int gpio)
1000{
1001 struct omap_mux_partition *partition;
1002 struct omap_mux *m = NULL;
1003
1004 list_for_each_entry(partition, &mux_partitions, node) {
1005 m = omap_mux_get_by_gpio(partition, gpio);
1006 if (m) {
1007 omap_mux_write(partition, val, m->reg_offset);
1008 return;
1009 }
1010 }
1011
1012 if (!m || m->reg_offset == OMAP_MUX_TERMINATOR)
1013 pr_err("%s: Could not set gpio%i\n", __func__, gpio);
1014}
1015
1016static struct omap_mux * __init omap_mux_list_add(
1017 struct omap_mux_partition *partition,
1018 struct omap_mux *src)
1019{
1020 struct omap_mux_entry *entry;
1021 struct omap_mux *m;
1022
1023 entry = kzalloc(sizeof(struct omap_mux_entry), GFP_KERNEL);
1024 if (!entry)
1025 return NULL;
1026
1027 m = &entry->mux;
1028 entry->mux = *src;
1029
1030#ifdef CONFIG_OMAP_MUX
1031 if (omap_mux_copy_names(src, m)) {
1032 kfree(entry);
1033 return NULL;
1034 }
1035#endif
1036
1037 mutex_lock(&muxmode_mutex);
1038 list_add_tail(&entry->node, &partition->muxmodes);
1039 mutex_unlock(&muxmode_mutex);
1040
1041 return m;
1042}
1043
1044/*
1045 * Note if CONFIG_OMAP_MUX is not selected, we will only initialize
1046 * the GPIO to mux offset mapping that is needed for dynamic muxing
1047 * of GPIO pins for off-idle.
1048 */
1049static void __init omap_mux_init_list(struct omap_mux_partition *partition,
1050 struct omap_mux *superset)
1051{
1052 while (superset->reg_offset != OMAP_MUX_TERMINATOR) {
1053 struct omap_mux *entry;
1054
1055#ifdef CONFIG_OMAP_MUX
1056 if (!superset->muxnames[0]) {
1057 superset++;
1058 continue;
1059 }
1060#else
1061 /* Skip pins that are not muxed as GPIO by bootloader */
1062 if (!OMAP_MODE_GPIO(partition, omap_mux_read(partition,
1063 superset->reg_offset))) {
1064 superset++;
1065 continue;
1066 }
1067#endif
1068
1069 entry = omap_mux_list_add(partition, superset);
1070 if (!entry) {
1071 pr_err("%s: Could not add entry\n", __func__);
1072 return;
1073 }
1074 superset++;
1075 }
1076}
1077
1078#ifdef CONFIG_OMAP_MUX
1079
1080static void omap_mux_init_package(struct omap_mux *superset,
1081 struct omap_mux *package_subset,
1082 struct omap_ball *package_balls)
1083{
1084 if (package_subset)
1085 omap_mux_package_fixup(package_subset, superset);
1086 if (package_balls)
1087 omap_mux_package_init_balls(package_balls, superset);
1088}
1089
1090static void __init omap_mux_init_signals(struct omap_mux_partition *partition,
1091 struct omap_board_mux *board_mux)
1092{
1093 omap_mux_set_cmdline_signals();
1094 omap_mux_write_array(partition, board_mux);
1095}
1096
1097#else
1098
1099static void omap_mux_init_package(struct omap_mux *superset,
1100 struct omap_mux *package_subset,
1101 struct omap_ball *package_balls)
1102{
1103}
1104
1105static void __init omap_mux_init_signals(struct omap_mux_partition *partition,
1106 struct omap_board_mux *board_mux)
1107{
1108}
1109
1110#endif
1111
1112static u32 mux_partitions_cnt;
1113
1114int __init omap_mux_init(const char *name, u32 flags,
1115 u32 mux_pbase, u32 mux_size,
1116 struct omap_mux *superset,
1117 struct omap_mux *package_subset,
1118 struct omap_board_mux *board_mux,
1119 struct omap_ball *package_balls)
1120{
1121 struct omap_mux_partition *partition;
1122
1123 partition = kzalloc(sizeof(struct omap_mux_partition), GFP_KERNEL);
1124 if (!partition)
1125 return -ENOMEM;
1126
1127 partition->name = name;
1128 partition->flags = flags;
1129 partition->gpio = flags & OMAP_MUX_MODE7;
1130 partition->size = mux_size;
1131 partition->phys = mux_pbase;
1132 partition->base = ioremap(mux_pbase, mux_size);
1133 if (!partition->base) {
1134 pr_err("%s: Could not ioremap mux partition at 0x%08x\n",
1135 __func__, partition->phys);
1136 kfree(partition);
1137 return -ENODEV;
1138 }
1139
1140 INIT_LIST_HEAD(&partition->muxmodes);
1141
1142 list_add_tail(&partition->node, &mux_partitions);
1143 mux_partitions_cnt++;
1144 pr_info("%s: Add partition: #%d: %s, flags: %x\n", __func__,
1145 mux_partitions_cnt, partition->name, partition->flags);
1146
1147 omap_mux_init_package(superset, package_subset, package_balls);
1148 omap_mux_init_list(partition, superset);
1149 omap_mux_init_signals(partition, board_mux);
1150
1151 return 0;
1152}
1153
diff --git a/arch/arm/mach-omap2/mux.h b/arch/arm/mach-omap2/mux.h
deleted file mode 100644
index d121fb6df4e6..000000000000
--- a/arch/arm/mach-omap2/mux.h
+++ /dev/null
@@ -1,352 +0,0 @@
1/*
2 * Copyright (C) 2009 Nokia
3 * Copyright (C) 2009-2010 Texas Instruments
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#include "mux34xx.h"
11
12#define OMAP_MUX_TERMINATOR 0xffff
13
14/* 34xx mux mode options for each pin. See TRM for options */
15#define OMAP_MUX_MODE0 0
16#define OMAP_MUX_MODE1 1
17#define OMAP_MUX_MODE2 2
18#define OMAP_MUX_MODE3 3
19#define OMAP_MUX_MODE4 4
20#define OMAP_MUX_MODE5 5
21#define OMAP_MUX_MODE6 6
22#define OMAP_MUX_MODE7 7
23
24/* 24xx/34xx mux bit defines */
25#define OMAP_PULL_ENA (1 << 3)
26#define OMAP_PULL_UP (1 << 4)
27#define OMAP_ALTELECTRICALSEL (1 << 5)
28
29/* omap3/4/5 specific mux bit defines */
30#define OMAP_INPUT_EN (1 << 8)
31#define OMAP_OFF_EN (1 << 9)
32#define OMAP_OFFOUT_EN (1 << 10)
33#define OMAP_OFFOUT_VAL (1 << 11)
34#define OMAP_OFF_PULL_EN (1 << 12)
35#define OMAP_OFF_PULL_UP (1 << 13)
36#define OMAP_WAKEUP_EN (1 << 14)
37#define OMAP_WAKEUP_EVENT (1 << 15)
38
39/* Active pin states */
40#define OMAP_PIN_OUTPUT 0
41#define OMAP_PIN_INPUT OMAP_INPUT_EN
42#define OMAP_PIN_INPUT_PULLUP (OMAP_PULL_ENA | OMAP_INPUT_EN \
43 | OMAP_PULL_UP)
44#define OMAP_PIN_INPUT_PULLDOWN (OMAP_PULL_ENA | OMAP_INPUT_EN)
45
46/* Off mode states */
47#define OMAP_PIN_OFF_NONE 0
48#define OMAP_PIN_OFF_OUTPUT_HIGH (OMAP_OFF_EN | OMAP_OFFOUT_EN \
49 | OMAP_OFFOUT_VAL)
50#define OMAP_PIN_OFF_OUTPUT_LOW (OMAP_OFF_EN | OMAP_OFFOUT_EN)
51#define OMAP_PIN_OFF_INPUT_PULLUP (OMAP_OFF_EN | OMAP_OFF_PULL_EN \
52 | OMAP_OFF_PULL_UP)
53#define OMAP_PIN_OFF_INPUT_PULLDOWN (OMAP_OFF_EN | OMAP_OFF_PULL_EN)
54#define OMAP_PIN_OFF_WAKEUPENABLE OMAP_WAKEUP_EN
55
56#define OMAP_MODE_GPIO(partition, x) (((x) & OMAP_MUX_MODE7) == \
57 partition->gpio)
58#define OMAP_MODE_UART(x) (((x) & OMAP_MUX_MODE7) == OMAP_MUX_MODE0)
59
60/* Flags for omapX_mux_init */
61#define OMAP_PACKAGE_MASK 0xffff
62#define OMAP_PACKAGE_CBP 6 /* 515-pin 0.40 0.50 */
63#define OMAP_PACKAGE_CUS 5 /* 423-pin 0.65 */
64#define OMAP_PACKAGE_CBB 4 /* 515-pin 0.40 0.50 */
65#define OMAP_PACKAGE_CBC 3 /* 515-pin 0.50 0.65 */
66
67#define OMAP_MUX_NR_MODES 8 /* Available modes */
68#define OMAP_MUX_NR_SIDES 2 /* Bottom & top */
69
70/*
71 * omap_mux_init flags definition:
72 *
73 * OMAP_GPIO_MUX_MODE, bits 0-2: gpio muxing mode, same like pad control
74 * register which includes values from 0-7.
75 * OMAP_MUX_REG_8BIT: Ensure that access to padconf is done in 8 bits.
76 * The default value is 16 bits.
77 */
78#define OMAP_MUX_GPIO_IN_MODE0 OMAP_MUX_MODE0
79#define OMAP_MUX_GPIO_IN_MODE1 OMAP_MUX_MODE1
80#define OMAP_MUX_GPIO_IN_MODE2 OMAP_MUX_MODE2
81#define OMAP_MUX_GPIO_IN_MODE3 OMAP_MUX_MODE3
82#define OMAP_MUX_GPIO_IN_MODE4 OMAP_MUX_MODE4
83#define OMAP_MUX_GPIO_IN_MODE5 OMAP_MUX_MODE5
84#define OMAP_MUX_GPIO_IN_MODE6 OMAP_MUX_MODE6
85#define OMAP_MUX_GPIO_IN_MODE7 OMAP_MUX_MODE7
86#define OMAP_MUX_REG_8BIT (1 << 3)
87
88/**
89 * struct omap_board_data - board specific device data
90 * @id: instance id
91 * @flags: additional flags for platform init code
92 * @pads: array of device specific pads
93 * @pads_cnt: ARRAY_SIZE() of pads
94 */
95struct omap_board_data {
96 int id;
97 u32 flags;
98 struct omap_device_pad *pads;
99 int pads_cnt;
100};
101
102/**
103 * struct mux_partition - contain partition related information
104 * @name: name of the current partition
105 * @flags: flags specific to this partition
106 * @gpio: gpio mux mode
107 * @phys: physical address
108 * @size: partition size
109 * @base: virtual address after ioremap
110 * @muxmodes: list of nodes that belong to a partition
111 * @node: list node for the partitions linked list
112 */
113struct omap_mux_partition {
114 const char *name;
115 u32 flags;
116 u32 gpio;
117 u32 phys;
118 u32 size;
119 void __iomem *base;
120 struct list_head muxmodes;
121 struct list_head node;
122};
123
124/**
125 * struct omap_mux - data for omap mux register offset and it's value
126 * @reg_offset: mux register offset from the mux base
127 * @gpio: GPIO number
128 * @muxnames: available signal modes for a ball
129 * @balls: available balls on the package
130 */
131struct omap_mux {
132 u16 reg_offset;
133 u16 gpio;
134#ifdef CONFIG_OMAP_MUX
135 char *muxnames[OMAP_MUX_NR_MODES];
136#ifdef CONFIG_DEBUG_FS
137 char *balls[OMAP_MUX_NR_SIDES];
138#endif
139#endif
140};
141
142/**
143 * struct omap_ball - data for balls on omap package
144 * @reg_offset: mux register offset from the mux base
145 * @balls: available balls on the package
146 */
147struct omap_ball {
148 u16 reg_offset;
149 char *balls[OMAP_MUX_NR_SIDES];
150};
151
152/**
153 * struct omap_board_mux - data for initializing mux registers
154 * @reg_offset: mux register offset from the mux base
155 * @mux_value: desired mux value to set
156 */
157struct omap_board_mux {
158 u16 reg_offset;
159 u16 value;
160};
161
162#define OMAP_DEVICE_PAD_REMUX BIT(1) /* Dynamically remux a pad,
163 needs enable, idle and off
164 values */
165#define OMAP_DEVICE_PAD_WAKEUP BIT(0) /* Pad is wake-up capable */
166
167/**
168 * struct omap_device_pad - device specific pad configuration
169 * @name: signal name
170 * @flags: pad specific runtime flags
171 * @enable: runtime value for a pad
172 * @idle: idle value for a pad
173 * @off: off value for a pad, defaults to safe mode
174 * @partition: mux partition
175 * @mux: mux register
176 */
177struct omap_device_pad {
178 char *name;
179 u8 flags;
180 u16 enable;
181 u16 idle;
182 u16 off;
183 struct omap_mux_partition *partition;
184 struct omap_mux *mux;
185};
186
187struct omap_hwmod_mux_info;
188
189#define OMAP_MUX_STATIC(signal, mode) \
190{ \
191 .name = (signal), \
192 .enable = (mode), \
193}
194
195#if defined(CONFIG_OMAP_MUX)
196
197/**
198 * omap_mux_init_gpio - initialize a signal based on the GPIO number
199 * @gpio: GPIO number
200 * @val: Options for the mux register value
201 */
202int omap_mux_init_gpio(int gpio, int val);
203
204/**
205 * omap_mux_init_signal - initialize a signal based on the signal name
206 * @muxname: Mux name in mode0_name.signal_name format
207 * @val: Options for the mux register value
208 */
209int omap_mux_init_signal(const char *muxname, int val);
210
211/**
212 * omap_hwmod_mux_init - initialize hwmod specific mux data
213 * @bpads: Board specific device signal names
214 * @nr_pads: Number of signal names for the device
215 */
216extern struct omap_hwmod_mux_info *
217omap_hwmod_mux_init(struct omap_device_pad *bpads, int nr_pads);
218
219/**
220 * omap_hwmod_mux - omap hwmod specific pin muxing
221 * @hmux: Pads for a hwmod
222 * @state: Desired _HWMOD_STATE
223 *
224 * Called only from omap_hwmod.c, do not use.
225 */
226void omap_hwmod_mux(struct omap_hwmod_mux_info *hmux, u8 state);
227
228int omap_mux_get_by_name(const char *muxname,
229 struct omap_mux_partition **found_partition,
230 struct omap_mux **found_mux);
231#else
232
233static inline int omap_mux_get_by_name(const char *muxname,
234 struct omap_mux_partition **found_partition,
235 struct omap_mux **found_mux)
236{
237 return 0;
238}
239
240static inline int omap_mux_init_gpio(int gpio, int val)
241{
242 return 0;
243}
244static inline int omap_mux_init_signal(char *muxname, int val)
245{
246 return 0;
247}
248
249static inline struct omap_hwmod_mux_info *
250omap_hwmod_mux_init(struct omap_device_pad *bpads, int nr_pads)
251{
252 return NULL;
253}
254
255static inline void omap_hwmod_mux(struct omap_hwmod_mux_info *hmux, u8 state)
256{
257}
258
259static struct omap_board_mux *board_mux __maybe_unused;
260
261#endif
262
263/**
264 * omap_mux_get_gpio() - get mux register value based on GPIO number
265 * @gpio: GPIO number
266 *
267 */
268u16 omap_mux_get_gpio(int gpio);
269
270/**
271 * omap_mux_set_gpio() - set mux register value based on GPIO number
272 * @val: New mux register value
273 * @gpio: GPIO number
274 *
275 */
276void omap_mux_set_gpio(u16 val, int gpio);
277
278/**
279 * omap_mux_get() - get a mux partition by name
280 * @name: Name of the mux partition
281 *
282 */
283struct omap_mux_partition *omap_mux_get(const char *name);
284
285/**
286 * omap_mux_read() - read mux register
287 * @partition: Mux partition
288 * @mux_offset: Offset of the mux register
289 *
290 */
291u16 omap_mux_read(struct omap_mux_partition *p, u16 mux_offset);
292
293/**
294 * omap_mux_write() - write mux register
295 * @partition: Mux partition
296 * @val: New mux register value
297 * @mux_offset: Offset of the mux register
298 *
299 * This should be only needed for dynamic remuxing of non-gpio signals.
300 */
301void omap_mux_write(struct omap_mux_partition *p, u16 val, u16 mux_offset);
302
303/**
304 * omap_mux_write_array() - write an array of mux registers
305 * @partition: Mux partition
306 * @board_mux: Array of mux registers terminated by MAP_MUX_TERMINATOR
307 *
308 * This should be only needed for dynamic remuxing of non-gpio signals.
309 */
310void omap_mux_write_array(struct omap_mux_partition *p,
311 struct omap_board_mux *board_mux);
312
313/**
314 * omap2420_mux_init() - initialize mux system with board specific set
315 * @board_mux: Board specific mux table
316 * @flags: OMAP package type used for the board
317 */
318int omap2420_mux_init(struct omap_board_mux *board_mux, int flags);
319
320/**
321 * omap2430_mux_init() - initialize mux system with board specific set
322 * @board_mux: Board specific mux table
323 * @flags: OMAP package type used for the board
324 */
325int omap2430_mux_init(struct omap_board_mux *board_mux, int flags);
326
327/**
328 * omap3_mux_init() - initialize mux system with board specific set
329 * @board_mux: Board specific mux table
330 * @flags: OMAP package type used for the board
331 */
332int omap3_mux_init(struct omap_board_mux *board_mux, int flags);
333
334/**
335 * omap4_mux_init() - initialize mux system with board specific set
336 * @board_subset: Board specific mux table
337 * @board_wkup_subset: Board specific mux table for wakeup instance
338 * @flags: OMAP package type used for the board
339 */
340int omap4_mux_init(struct omap_board_mux *board_subset,
341 struct omap_board_mux *board_wkup_subset, int flags);
342
343/**
344 * omap_mux_init - private mux init function, do not call
345 */
346int omap_mux_init(const char *name, u32 flags,
347 u32 mux_pbase, u32 mux_size,
348 struct omap_mux *superset,
349 struct omap_mux *package_subset,
350 struct omap_board_mux *board_mux,
351 struct omap_ball *package_balls);
352
diff --git a/arch/arm/mach-omap2/mux34xx.c b/arch/arm/mach-omap2/mux34xx.c
deleted file mode 100644
index 393e687f99e2..000000000000
--- a/arch/arm/mach-omap2/mux34xx.c
+++ /dev/null
@@ -1,2061 +0,0 @@
1/*
2 * Copyright (C) 2009 Nokia
3 * Copyright (C) 2009 Texas Instruments
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#include <linux/module.h>
11#include <linux/init.h>
12
13#include "mux.h"
14
15#ifdef CONFIG_OMAP_MUX
16
17#define _OMAP3_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7) \
18{ \
19 .reg_offset = (OMAP3_CONTROL_PADCONF_##M0##_OFFSET), \
20 .gpio = (g), \
21 .muxnames = { m0, m1, m2, m3, m4, m5, m6, m7 }, \
22}
23
24#else
25
26#define _OMAP3_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7) \
27{ \
28 .reg_offset = (OMAP3_CONTROL_PADCONF_##M0##_OFFSET), \
29 .gpio = (g), \
30}
31
32#endif
33
34#define _OMAP3_BALLENTRY(M0, bb, bt) \
35{ \
36 .reg_offset = (OMAP3_CONTROL_PADCONF_##M0##_OFFSET), \
37 .balls = { bb, bt }, \
38}
39
40/*
41 * Superset of all mux modes for omap3
42 */
43static struct omap_mux __initdata omap3_muxmodes[] = {
44 _OMAP3_MUXENTRY(CAM_D0, 99,
45 "cam_d0", NULL, NULL, NULL,
46 "gpio_99", NULL, NULL, "safe_mode"),
47 _OMAP3_MUXENTRY(CAM_D1, 100,
48 "cam_d1", NULL, NULL, NULL,
49 "gpio_100", NULL, NULL, "safe_mode"),
50 _OMAP3_MUXENTRY(CAM_D10, 109,
51 "cam_d10", NULL, NULL, NULL,
52 "gpio_109", "hw_dbg8", NULL, "safe_mode"),
53 _OMAP3_MUXENTRY(CAM_D11, 110,
54 "cam_d11", NULL, NULL, NULL,
55 "gpio_110", "hw_dbg9", NULL, "safe_mode"),
56 _OMAP3_MUXENTRY(CAM_D2, 101,
57 "cam_d2", NULL, NULL, NULL,
58 "gpio_101", "hw_dbg4", NULL, "safe_mode"),
59 _OMAP3_MUXENTRY(CAM_D3, 102,
60 "cam_d3", NULL, NULL, NULL,
61 "gpio_102", "hw_dbg5", NULL, "safe_mode"),
62 _OMAP3_MUXENTRY(CAM_D4, 103,
63 "cam_d4", NULL, NULL, NULL,
64 "gpio_103", "hw_dbg6", NULL, "safe_mode"),
65 _OMAP3_MUXENTRY(CAM_D5, 104,
66 "cam_d5", NULL, NULL, NULL,
67 "gpio_104", "hw_dbg7", NULL, "safe_mode"),
68 _OMAP3_MUXENTRY(CAM_D6, 105,
69 "cam_d6", NULL, NULL, NULL,
70 "gpio_105", NULL, NULL, "safe_mode"),
71 _OMAP3_MUXENTRY(CAM_D7, 106,
72 "cam_d7", NULL, NULL, NULL,
73 "gpio_106", NULL, NULL, "safe_mode"),
74 _OMAP3_MUXENTRY(CAM_D8, 107,
75 "cam_d8", NULL, NULL, NULL,
76 "gpio_107", NULL, NULL, "safe_mode"),
77 _OMAP3_MUXENTRY(CAM_D9, 108,
78 "cam_d9", NULL, NULL, NULL,
79 "gpio_108", NULL, NULL, "safe_mode"),
80 _OMAP3_MUXENTRY(CAM_FLD, 98,
81 "cam_fld", NULL, "cam_global_reset", NULL,
82 "gpio_98", "hw_dbg3", NULL, "safe_mode"),
83 _OMAP3_MUXENTRY(CAM_HS, 94,
84 "cam_hs", NULL, NULL, NULL,
85 "gpio_94", "hw_dbg0", NULL, "safe_mode"),
86 _OMAP3_MUXENTRY(CAM_PCLK, 97,
87 "cam_pclk", NULL, NULL, NULL,
88 "gpio_97", "hw_dbg2", NULL, "safe_mode"),
89 _OMAP3_MUXENTRY(CAM_STROBE, 126,
90 "cam_strobe", NULL, NULL, NULL,
91 "gpio_126", "hw_dbg11", NULL, "safe_mode"),
92 _OMAP3_MUXENTRY(CAM_VS, 95,
93 "cam_vs", NULL, NULL, NULL,
94 "gpio_95", "hw_dbg1", NULL, "safe_mode"),
95 _OMAP3_MUXENTRY(CAM_WEN, 167,
96 "cam_wen", NULL, "cam_shutter", NULL,
97 "gpio_167", "hw_dbg10", NULL, "safe_mode"),
98 _OMAP3_MUXENTRY(CAM_XCLKA, 96,
99 "cam_xclka", NULL, NULL, NULL,
100 "gpio_96", NULL, NULL, "safe_mode"),
101 _OMAP3_MUXENTRY(CAM_XCLKB, 111,
102 "cam_xclkb", NULL, NULL, NULL,
103 "gpio_111", NULL, NULL, "safe_mode"),
104 _OMAP3_MUXENTRY(CSI2_DX0, 112,
105 "csi2_dx0", NULL, NULL, NULL,
106 "gpio_112", NULL, NULL, "safe_mode"),
107 _OMAP3_MUXENTRY(CSI2_DX1, 114,
108 "csi2_dx1", NULL, NULL, NULL,
109 "gpio_114", NULL, NULL, "safe_mode"),
110 _OMAP3_MUXENTRY(CSI2_DY0, 113,
111 "csi2_dy0", NULL, NULL, NULL,
112 "gpio_113", NULL, NULL, "safe_mode"),
113 _OMAP3_MUXENTRY(CSI2_DY1, 115,
114 "csi2_dy1", NULL, NULL, NULL,
115 "gpio_115", NULL, NULL, "safe_mode"),
116 _OMAP3_MUXENTRY(DSS_ACBIAS, 69,
117 "dss_acbias", NULL, NULL, NULL,
118 "gpio_69", NULL, NULL, "safe_mode"),
119 _OMAP3_MUXENTRY(DSS_DATA0, 70,
120 "dss_data0", NULL, "uart1_cts", NULL,
121 "gpio_70", NULL, NULL, "safe_mode"),
122 _OMAP3_MUXENTRY(DSS_DATA1, 71,
123 "dss_data1", NULL, "uart1_rts", NULL,
124 "gpio_71", NULL, NULL, "safe_mode"),
125 _OMAP3_MUXENTRY(DSS_DATA10, 80,
126 "dss_data10", NULL, NULL, NULL,
127 "gpio_80", NULL, NULL, "safe_mode"),
128 _OMAP3_MUXENTRY(DSS_DATA11, 81,
129 "dss_data11", NULL, NULL, NULL,
130 "gpio_81", NULL, NULL, "safe_mode"),
131 _OMAP3_MUXENTRY(DSS_DATA12, 82,
132 "dss_data12", NULL, NULL, NULL,
133 "gpio_82", NULL, NULL, "safe_mode"),
134 _OMAP3_MUXENTRY(DSS_DATA13, 83,
135 "dss_data13", NULL, NULL, NULL,
136 "gpio_83", NULL, NULL, "safe_mode"),
137 _OMAP3_MUXENTRY(DSS_DATA14, 84,
138 "dss_data14", NULL, NULL, NULL,
139 "gpio_84", NULL, NULL, "safe_mode"),
140 _OMAP3_MUXENTRY(DSS_DATA15, 85,
141 "dss_data15", NULL, NULL, NULL,
142 "gpio_85", NULL, NULL, "safe_mode"),
143 _OMAP3_MUXENTRY(DSS_DATA16, 86,
144 "dss_data16", NULL, NULL, NULL,
145 "gpio_86", NULL, NULL, "safe_mode"),
146 _OMAP3_MUXENTRY(DSS_DATA17, 87,
147 "dss_data17", NULL, NULL, NULL,
148 "gpio_87", NULL, NULL, "safe_mode"),
149 _OMAP3_MUXENTRY(DSS_DATA18, 88,
150 "dss_data18", NULL, "mcspi3_clk", "dss_data0",
151 "gpio_88", NULL, NULL, "safe_mode"),
152 _OMAP3_MUXENTRY(DSS_DATA19, 89,
153 "dss_data19", NULL, "mcspi3_simo", "dss_data1",
154 "gpio_89", NULL, NULL, "safe_mode"),
155 _OMAP3_MUXENTRY(DSS_DATA20, 90,
156 "dss_data20", NULL, "mcspi3_somi", "dss_data2",
157 "gpio_90", NULL, NULL, "safe_mode"),
158 _OMAP3_MUXENTRY(DSS_DATA21, 91,
159 "dss_data21", NULL, "mcspi3_cs0", "dss_data3",
160 "gpio_91", NULL, NULL, "safe_mode"),
161 _OMAP3_MUXENTRY(DSS_DATA22, 92,
162 "dss_data22", NULL, "mcspi3_cs1", "dss_data4",
163 "gpio_92", NULL, NULL, "safe_mode"),
164 _OMAP3_MUXENTRY(DSS_DATA23, 93,
165 "dss_data23", NULL, NULL, "dss_data5",
166 "gpio_93", NULL, NULL, "safe_mode"),
167 _OMAP3_MUXENTRY(DSS_DATA2, 72,
168 "dss_data2", NULL, NULL, NULL,
169 "gpio_72", NULL, NULL, "safe_mode"),
170 _OMAP3_MUXENTRY(DSS_DATA3, 73,
171 "dss_data3", NULL, NULL, NULL,
172 "gpio_73", NULL, NULL, "safe_mode"),
173 _OMAP3_MUXENTRY(DSS_DATA4, 74,
174 "dss_data4", NULL, "uart3_rx_irrx", NULL,
175 "gpio_74", NULL, NULL, "safe_mode"),
176 _OMAP3_MUXENTRY(DSS_DATA5, 75,
177 "dss_data5", NULL, "uart3_tx_irtx", NULL,
178 "gpio_75", NULL, NULL, "safe_mode"),
179 _OMAP3_MUXENTRY(DSS_DATA6, 76,
180 "dss_data6", NULL, "uart1_tx", NULL,
181 "gpio_76", "hw_dbg14", NULL, "safe_mode"),
182 _OMAP3_MUXENTRY(DSS_DATA7, 77,
183 "dss_data7", NULL, "uart1_rx", NULL,
184 "gpio_77", "hw_dbg15", NULL, "safe_mode"),
185 _OMAP3_MUXENTRY(DSS_DATA8, 78,
186 "dss_data8", NULL, NULL, NULL,
187 "gpio_78", "hw_dbg16", NULL, "safe_mode"),
188 _OMAP3_MUXENTRY(DSS_DATA9, 79,
189 "dss_data9", NULL, NULL, NULL,
190 "gpio_79", "hw_dbg17", NULL, "safe_mode"),
191 _OMAP3_MUXENTRY(DSS_HSYNC, 67,
192 "dss_hsync", NULL, NULL, NULL,
193 "gpio_67", "hw_dbg13", NULL, "safe_mode"),
194 _OMAP3_MUXENTRY(DSS_PCLK, 66,
195 "dss_pclk", NULL, NULL, NULL,
196 "gpio_66", "hw_dbg12", NULL, "safe_mode"),
197 _OMAP3_MUXENTRY(DSS_VSYNC, 68,
198 "dss_vsync", NULL, NULL, NULL,
199 "gpio_68", NULL, NULL, "safe_mode"),
200 _OMAP3_MUXENTRY(ETK_CLK, 12,
201 "etk_clk", "mcbsp5_clkx", "sdmmc3_clk", "hsusb1_stp",
202 "gpio_12", "mm1_rxdp", "hsusb1_tll_stp", "hw_dbg0"),
203 _OMAP3_MUXENTRY(ETK_CTL, 13,
204 "etk_ctl", NULL, "sdmmc3_cmd", "hsusb1_clk",
205 "gpio_13", NULL, "hsusb1_tll_clk", "hw_dbg1"),
206 _OMAP3_MUXENTRY(ETK_D0, 14,
207 "etk_d0", "mcspi3_simo", "sdmmc3_dat4", "hsusb1_data0",
208 "gpio_14", "mm1_rxrcv", "hsusb1_tll_data0", "hw_dbg2"),
209 _OMAP3_MUXENTRY(ETK_D1, 15,
210 "etk_d1", "mcspi3_somi", NULL, "hsusb1_data1",
211 "gpio_15", "mm1_txse0", "hsusb1_tll_data1", "hw_dbg3"),
212 _OMAP3_MUXENTRY(ETK_D10, 24,
213 "etk_d10", NULL, "uart1_rx", "hsusb2_clk",
214 "gpio_24", NULL, "hsusb2_tll_clk", "hw_dbg12"),
215 _OMAP3_MUXENTRY(ETK_D11, 25,
216 "etk_d11", NULL, NULL, "hsusb2_stp",
217 "gpio_25", "mm2_rxdp", "hsusb2_tll_stp", "hw_dbg13"),
218 _OMAP3_MUXENTRY(ETK_D12, 26,
219 "etk_d12", NULL, NULL, "hsusb2_dir",
220 "gpio_26", NULL, "hsusb2_tll_dir", "hw_dbg14"),
221 _OMAP3_MUXENTRY(ETK_D13, 27,
222 "etk_d13", NULL, NULL, "hsusb2_nxt",
223 "gpio_27", "mm2_rxdm", "hsusb2_tll_nxt", "hw_dbg15"),
224 _OMAP3_MUXENTRY(ETK_D14, 28,
225 "etk_d14", NULL, NULL, "hsusb2_data0",
226 "gpio_28", "mm2_rxrcv", "hsusb2_tll_data0", "hw_dbg16"),
227 _OMAP3_MUXENTRY(ETK_D15, 29,
228 "etk_d15", NULL, NULL, "hsusb2_data1",
229 "gpio_29", "mm2_txse0", "hsusb2_tll_data1", "hw_dbg17"),
230 _OMAP3_MUXENTRY(ETK_D2, 16,
231 "etk_d2", "mcspi3_cs0", NULL, "hsusb1_data2",
232 "gpio_16", "mm1_txdat", "hsusb1_tll_data2", "hw_dbg4"),
233 _OMAP3_MUXENTRY(ETK_D3, 17,
234 "etk_d3", "mcspi3_clk", "sdmmc3_dat3", "hsusb1_data7",
235 "gpio_17", NULL, "hsusb1_tll_data7", "hw_dbg5"),
236 _OMAP3_MUXENTRY(ETK_D4, 18,
237 "etk_d4", "mcbsp5_dr", "sdmmc3_dat0", "hsusb1_data4",
238 "gpio_18", NULL, "hsusb1_tll_data4", "hw_dbg6"),
239 _OMAP3_MUXENTRY(ETK_D5, 19,
240 "etk_d5", "mcbsp5_fsx", "sdmmc3_dat1", "hsusb1_data5",
241 "gpio_19", NULL, "hsusb1_tll_data5", "hw_dbg7"),
242 _OMAP3_MUXENTRY(ETK_D6, 20,
243 "etk_d6", "mcbsp5_dx", "sdmmc3_dat2", "hsusb1_data6",
244 "gpio_20", NULL, "hsusb1_tll_data6", "hw_dbg8"),
245 _OMAP3_MUXENTRY(ETK_D7, 21,
246 "etk_d7", "mcspi3_cs1", "sdmmc3_dat7", "hsusb1_data3",
247 "gpio_21", "mm1_txen_n", "hsusb1_tll_data3", "hw_dbg9"),
248 _OMAP3_MUXENTRY(ETK_D8, 22,
249 "etk_d8", "sys_drm_msecure", "sdmmc3_dat6", "hsusb1_dir",
250 "gpio_22", NULL, "hsusb1_tll_dir", "hw_dbg10"),
251 _OMAP3_MUXENTRY(ETK_D9, 23,
252 "etk_d9", "sys_secure_indicator", "sdmmc3_dat5", "hsusb1_nxt",
253 "gpio_23", "mm1_rxdm", "hsusb1_tll_nxt", "hw_dbg11"),
254 _OMAP3_MUXENTRY(GPMC_A1, 34,
255 "gpmc_a1", NULL, NULL, NULL,
256 "gpio_34", NULL, NULL, "safe_mode"),
257 _OMAP3_MUXENTRY(GPMC_A10, 43,
258 "gpmc_a10", "sys_ndmareq3", NULL, NULL,
259 "gpio_43", NULL, NULL, "safe_mode"),
260 _OMAP3_MUXENTRY(GPMC_A2, 35,
261 "gpmc_a2", NULL, NULL, NULL,
262 "gpio_35", NULL, NULL, "safe_mode"),
263 _OMAP3_MUXENTRY(GPMC_A3, 36,
264 "gpmc_a3", NULL, NULL, NULL,
265 "gpio_36", NULL, NULL, "safe_mode"),
266 _OMAP3_MUXENTRY(GPMC_A4, 37,
267 "gpmc_a4", NULL, NULL, NULL,
268 "gpio_37", NULL, NULL, "safe_mode"),
269 _OMAP3_MUXENTRY(GPMC_A5, 38,
270 "gpmc_a5", NULL, NULL, NULL,
271 "gpio_38", NULL, NULL, "safe_mode"),
272 _OMAP3_MUXENTRY(GPMC_A6, 39,
273 "gpmc_a6", NULL, NULL, NULL,
274 "gpio_39", NULL, NULL, "safe_mode"),
275 _OMAP3_MUXENTRY(GPMC_A7, 40,
276 "gpmc_a7", NULL, NULL, NULL,
277 "gpio_40", NULL, NULL, "safe_mode"),
278 _OMAP3_MUXENTRY(GPMC_A8, 41,
279 "gpmc_a8", NULL, NULL, NULL,
280 "gpio_41", NULL, NULL, "safe_mode"),
281 _OMAP3_MUXENTRY(GPMC_A9, 42,
282 "gpmc_a9", "sys_ndmareq2", NULL, NULL,
283 "gpio_42", NULL, NULL, "safe_mode"),
284 _OMAP3_MUXENTRY(GPMC_CLK, 59,
285 "gpmc_clk", NULL, NULL, NULL,
286 "gpio_59", NULL, NULL, "safe_mode"),
287 _OMAP3_MUXENTRY(GPMC_D10, 46,
288 "gpmc_d10", NULL, NULL, NULL,
289 "gpio_46", NULL, NULL, "safe_mode"),
290 _OMAP3_MUXENTRY(GPMC_D11, 47,
291 "gpmc_d11", NULL, NULL, NULL,
292 "gpio_47", NULL, NULL, "safe_mode"),
293 _OMAP3_MUXENTRY(GPMC_D12, 48,
294 "gpmc_d12", NULL, NULL, NULL,
295 "gpio_48", NULL, NULL, "safe_mode"),
296 _OMAP3_MUXENTRY(GPMC_D13, 49,
297 "gpmc_d13", NULL, NULL, NULL,
298 "gpio_49", NULL, NULL, "safe_mode"),
299 _OMAP3_MUXENTRY(GPMC_D14, 50,
300 "gpmc_d14", NULL, NULL, NULL,
301 "gpio_50", NULL, NULL, "safe_mode"),
302 _OMAP3_MUXENTRY(GPMC_D15, 51,
303 "gpmc_d15", NULL, NULL, NULL,
304 "gpio_51", NULL, NULL, "safe_mode"),
305 _OMAP3_MUXENTRY(GPMC_D8, 44,
306 "gpmc_d8", NULL, NULL, NULL,
307 "gpio_44", NULL, NULL, "safe_mode"),
308 _OMAP3_MUXENTRY(GPMC_D9, 45,
309 "gpmc_d9", NULL, NULL, NULL,
310 "gpio_45", NULL, NULL, "safe_mode"),
311 _OMAP3_MUXENTRY(GPMC_NBE0_CLE, 60,
312 "gpmc_nbe0_cle", NULL, NULL, NULL,
313 "gpio_60", NULL, NULL, "safe_mode"),
314 _OMAP3_MUXENTRY(GPMC_NBE1, 61,
315 "gpmc_nbe1", NULL, NULL, NULL,
316 "gpio_61", NULL, NULL, "safe_mode"),
317 _OMAP3_MUXENTRY(GPMC_NCS1, 52,
318 "gpmc_ncs1", NULL, NULL, NULL,
319 "gpio_52", NULL, NULL, "safe_mode"),
320 _OMAP3_MUXENTRY(GPMC_NCS2, 53,
321 "gpmc_ncs2", NULL, NULL, NULL,
322 "gpio_53", NULL, NULL, "safe_mode"),
323 _OMAP3_MUXENTRY(GPMC_NCS3, 54,
324 "gpmc_ncs3", "sys_ndmareq0", NULL, NULL,
325 "gpio_54", NULL, NULL, "safe_mode"),
326 _OMAP3_MUXENTRY(GPMC_NCS4, 55,
327 "gpmc_ncs4", "sys_ndmareq1", "mcbsp4_clkx", "gpt9_pwm_evt",
328 "gpio_55", NULL, NULL, "safe_mode"),
329 _OMAP3_MUXENTRY(GPMC_NCS5, 56,
330 "gpmc_ncs5", "sys_ndmareq2", "mcbsp4_dr", "gpt10_pwm_evt",
331 "gpio_56", NULL, NULL, "safe_mode"),
332 _OMAP3_MUXENTRY(GPMC_NCS6, 57,
333 "gpmc_ncs6", "sys_ndmareq3", "mcbsp4_dx", "gpt11_pwm_evt",
334 "gpio_57", NULL, NULL, "safe_mode"),
335 _OMAP3_MUXENTRY(GPMC_NCS7, 58,
336 "gpmc_ncs7", "gpmc_io_dir", "mcbsp4_fsx", "gpt8_pwm_evt",
337 "gpio_58", NULL, NULL, "safe_mode"),
338 _OMAP3_MUXENTRY(GPMC_NWP, 62,
339 "gpmc_nwp", NULL, NULL, NULL,
340 "gpio_62", NULL, NULL, "safe_mode"),
341 _OMAP3_MUXENTRY(GPMC_WAIT1, 63,
342 "gpmc_wait1", NULL, NULL, NULL,
343 "gpio_63", NULL, NULL, "safe_mode"),
344 _OMAP3_MUXENTRY(GPMC_WAIT2, 64,
345 "gpmc_wait2", NULL, NULL, NULL,
346 "gpio_64", NULL, NULL, "safe_mode"),
347 _OMAP3_MUXENTRY(GPMC_WAIT3, 65,
348 "gpmc_wait3", "sys_ndmareq1", NULL, NULL,
349 "gpio_65", NULL, NULL, "safe_mode"),
350 _OMAP3_MUXENTRY(HDQ_SIO, 170,
351 "hdq_sio", "sys_altclk", "i2c2_sccbe", "i2c3_sccbe",
352 "gpio_170", NULL, NULL, "safe_mode"),
353 _OMAP3_MUXENTRY(HSUSB0_CLK, 120,
354 "hsusb0_clk", NULL, NULL, NULL,
355 "gpio_120", NULL, NULL, "safe_mode"),
356 _OMAP3_MUXENTRY(HSUSB0_DATA0, 125,
357 "hsusb0_data0", NULL, "uart3_tx_irtx", NULL,
358 "gpio_125", NULL, NULL, "safe_mode"),
359 _OMAP3_MUXENTRY(HSUSB0_DATA1, 130,
360 "hsusb0_data1", NULL, "uart3_rx_irrx", NULL,
361 "gpio_130", NULL, NULL, "safe_mode"),
362 _OMAP3_MUXENTRY(HSUSB0_DATA2, 131,
363 "hsusb0_data2", NULL, "uart3_rts_sd", NULL,
364 "gpio_131", NULL, NULL, "safe_mode"),
365 _OMAP3_MUXENTRY(HSUSB0_DATA3, 169,
366 "hsusb0_data3", NULL, "uart3_cts_rctx", NULL,
367 "gpio_169", NULL, NULL, "safe_mode"),
368 _OMAP3_MUXENTRY(HSUSB0_DATA4, 188,
369 "hsusb0_data4", NULL, NULL, NULL,
370 "gpio_188", NULL, NULL, "safe_mode"),
371 _OMAP3_MUXENTRY(HSUSB0_DATA5, 189,
372 "hsusb0_data5", NULL, NULL, NULL,
373 "gpio_189", NULL, NULL, "safe_mode"),
374 _OMAP3_MUXENTRY(HSUSB0_DATA6, 190,
375 "hsusb0_data6", NULL, NULL, NULL,
376 "gpio_190", NULL, NULL, "safe_mode"),
377 _OMAP3_MUXENTRY(HSUSB0_DATA7, 191,
378 "hsusb0_data7", NULL, NULL, NULL,
379 "gpio_191", NULL, NULL, "safe_mode"),
380 _OMAP3_MUXENTRY(HSUSB0_DIR, 122,
381 "hsusb0_dir", NULL, NULL, NULL,
382 "gpio_122", NULL, NULL, "safe_mode"),
383 _OMAP3_MUXENTRY(HSUSB0_NXT, 124,
384 "hsusb0_nxt", NULL, NULL, NULL,
385 "gpio_124", NULL, NULL, "safe_mode"),
386 _OMAP3_MUXENTRY(HSUSB0_STP, 121,
387 "hsusb0_stp", NULL, NULL, NULL,
388 "gpio_121", NULL, NULL, "safe_mode"),
389 _OMAP3_MUXENTRY(I2C2_SCL, 168,
390 "i2c2_scl", NULL, NULL, NULL,
391 "gpio_168", NULL, NULL, "safe_mode"),
392 _OMAP3_MUXENTRY(I2C2_SDA, 183,
393 "i2c2_sda", NULL, NULL, NULL,
394 "gpio_183", NULL, NULL, "safe_mode"),
395 _OMAP3_MUXENTRY(I2C3_SCL, 184,
396 "i2c3_scl", NULL, NULL, NULL,
397 "gpio_184", NULL, NULL, "safe_mode"),
398 _OMAP3_MUXENTRY(I2C3_SDA, 185,
399 "i2c3_sda", NULL, NULL, NULL,
400 "gpio_185", NULL, NULL, "safe_mode"),
401 _OMAP3_MUXENTRY(I2C4_SCL, 0,
402 "i2c4_scl", "sys_nvmode1", NULL, NULL,
403 NULL, NULL, NULL, "safe_mode"),
404 _OMAP3_MUXENTRY(I2C4_SDA, 0,
405 "i2c4_sda", "sys_nvmode2", NULL, NULL,
406 NULL, NULL, NULL, "safe_mode"),
407 _OMAP3_MUXENTRY(JTAG_EMU0, 11,
408 "jtag_emu0", NULL, NULL, NULL,
409 "gpio_11", NULL, NULL, "safe_mode"),
410 _OMAP3_MUXENTRY(JTAG_EMU1, 31,
411 "jtag_emu1", NULL, NULL, NULL,
412 "gpio_31", NULL, NULL, "safe_mode"),
413 _OMAP3_MUXENTRY(MCBSP1_CLKR, 156,
414 "mcbsp1_clkr", "mcspi4_clk", NULL, NULL,
415 "gpio_156", NULL, NULL, "safe_mode"),
416 _OMAP3_MUXENTRY(MCBSP1_CLKX, 162,
417 "mcbsp1_clkx", NULL, "mcbsp3_clkx", NULL,
418 "gpio_162", NULL, NULL, "safe_mode"),
419 _OMAP3_MUXENTRY(MCBSP1_DR, 159,
420 "mcbsp1_dr", "mcspi4_somi", "mcbsp3_dr", NULL,
421 "gpio_159", NULL, NULL, "safe_mode"),
422 _OMAP3_MUXENTRY(MCBSP1_DX, 158,
423 "mcbsp1_dx", "mcspi4_simo", "mcbsp3_dx", NULL,
424 "gpio_158", NULL, NULL, "safe_mode"),
425 _OMAP3_MUXENTRY(MCBSP1_FSR, 157,
426 "mcbsp1_fsr", NULL, "cam_global_reset", NULL,
427 "gpio_157", NULL, NULL, "safe_mode"),
428 _OMAP3_MUXENTRY(MCBSP1_FSX, 161,
429 "mcbsp1_fsx", "mcspi4_cs0", "mcbsp3_fsx", NULL,
430 "gpio_161", NULL, NULL, "safe_mode"),
431 _OMAP3_MUXENTRY(MCBSP2_CLKX, 117,
432 "mcbsp2_clkx", NULL, NULL, NULL,
433 "gpio_117", NULL, NULL, "safe_mode"),
434 _OMAP3_MUXENTRY(MCBSP2_DR, 118,
435 "mcbsp2_dr", NULL, NULL, NULL,
436 "gpio_118", NULL, NULL, "safe_mode"),
437 _OMAP3_MUXENTRY(MCBSP2_DX, 119,
438 "mcbsp2_dx", NULL, NULL, NULL,
439 "gpio_119", NULL, NULL, "safe_mode"),
440 _OMAP3_MUXENTRY(MCBSP2_FSX, 116,
441 "mcbsp2_fsx", NULL, NULL, NULL,
442 "gpio_116", NULL, NULL, "safe_mode"),
443 _OMAP3_MUXENTRY(MCBSP3_CLKX, 142,
444 "mcbsp3_clkx", "uart2_tx", NULL, NULL,
445 "gpio_142", "hsusb3_tll_data6", NULL, "safe_mode"),
446 _OMAP3_MUXENTRY(MCBSP3_DR, 141,
447 "mcbsp3_dr", "uart2_rts", NULL, NULL,
448 "gpio_141", "hsusb3_tll_data5", NULL, "safe_mode"),
449 _OMAP3_MUXENTRY(MCBSP3_DX, 140,
450 "mcbsp3_dx", "uart2_cts", NULL, NULL,
451 "gpio_140", "hsusb3_tll_data4", NULL, "safe_mode"),
452 _OMAP3_MUXENTRY(MCBSP3_FSX, 143,
453 "mcbsp3_fsx", "uart2_rx", NULL, NULL,
454 "gpio_143", "hsusb3_tll_data7", NULL, "safe_mode"),
455 _OMAP3_MUXENTRY(MCBSP4_CLKX, 152,
456 "mcbsp4_clkx", NULL, NULL, NULL,
457 "gpio_152", "hsusb3_tll_data1", "mm3_txse0", "safe_mode"),
458 _OMAP3_MUXENTRY(MCBSP4_DR, 153,
459 "mcbsp4_dr", NULL, NULL, NULL,
460 "gpio_153", "hsusb3_tll_data0", "mm3_rxrcv", "safe_mode"),
461 _OMAP3_MUXENTRY(MCBSP4_DX, 154,
462 "mcbsp4_dx", NULL, NULL, NULL,
463 "gpio_154", "hsusb3_tll_data2", "mm3_txdat", "safe_mode"),
464 _OMAP3_MUXENTRY(MCBSP4_FSX, 155,
465 "mcbsp4_fsx", NULL, NULL, NULL,
466 "gpio_155", "hsusb3_tll_data3", "mm3_txen_n", "safe_mode"),
467 _OMAP3_MUXENTRY(MCBSP_CLKS, 160,
468 "mcbsp_clks", NULL, "cam_shutter", NULL,
469 "gpio_160", "uart1_cts", NULL, "safe_mode"),
470 _OMAP3_MUXENTRY(MCSPI1_CLK, 171,
471 "mcspi1_clk", "sdmmc2_dat4", NULL, NULL,
472 "gpio_171", NULL, NULL, "safe_mode"),
473 _OMAP3_MUXENTRY(MCSPI1_CS0, 174,
474 "mcspi1_cs0", "sdmmc2_dat7", NULL, NULL,
475 "gpio_174", NULL, NULL, "safe_mode"),
476 _OMAP3_MUXENTRY(MCSPI1_CS1, 175,
477 "mcspi1_cs1", NULL, NULL, "sdmmc3_cmd",
478 "gpio_175", NULL, NULL, "safe_mode"),
479 _OMAP3_MUXENTRY(MCSPI1_CS2, 176,
480 "mcspi1_cs2", NULL, NULL, "sdmmc3_clk",
481 "gpio_176", NULL, NULL, "safe_mode"),
482 _OMAP3_MUXENTRY(MCSPI1_CS3, 177,
483 "mcspi1_cs3", NULL, "hsusb2_tll_data2", "hsusb2_data2",
484 "gpio_177", "mm2_txdat", NULL, "safe_mode"),
485 _OMAP3_MUXENTRY(MCSPI1_SIMO, 172,
486 "mcspi1_simo", "sdmmc2_dat5", NULL, NULL,
487 "gpio_172", NULL, NULL, "safe_mode"),
488 _OMAP3_MUXENTRY(MCSPI1_SOMI, 173,
489 "mcspi1_somi", "sdmmc2_dat6", NULL, NULL,
490 "gpio_173", NULL, NULL, "safe_mode"),
491 _OMAP3_MUXENTRY(MCSPI2_CLK, 178,
492 "mcspi2_clk", NULL, "hsusb2_tll_data7", "hsusb2_data7",
493 "gpio_178", NULL, NULL, "safe_mode"),
494 _OMAP3_MUXENTRY(MCSPI2_CS0, 181,
495 "mcspi2_cs0", "gpt11_pwm_evt",
496 "hsusb2_tll_data6", "hsusb2_data6",
497 "gpio_181", NULL, NULL, "safe_mode"),
498 _OMAP3_MUXENTRY(MCSPI2_CS1, 182,
499 "mcspi2_cs1", "gpt8_pwm_evt",
500 "hsusb2_tll_data3", "hsusb2_data3",
501 "gpio_182", "mm2_txen_n", NULL, "safe_mode"),
502 _OMAP3_MUXENTRY(MCSPI2_SIMO, 179,
503 "mcspi2_simo", "gpt9_pwm_evt",
504 "hsusb2_tll_data4", "hsusb2_data4",
505 "gpio_179", NULL, NULL, "safe_mode"),
506 _OMAP3_MUXENTRY(MCSPI2_SOMI, 180,
507 "mcspi2_somi", "gpt10_pwm_evt",
508 "hsusb2_tll_data5", "hsusb2_data5",
509 "gpio_180", NULL, NULL, "safe_mode"),
510 _OMAP3_MUXENTRY(SDMMC1_CLK, 120,
511 "sdmmc1_clk", NULL, NULL, NULL,
512 "gpio_120", NULL, NULL, "safe_mode"),
513 _OMAP3_MUXENTRY(SDMMC1_CMD, 121,
514 "sdmmc1_cmd", NULL, NULL, NULL,
515 "gpio_121", NULL, NULL, "safe_mode"),
516 _OMAP3_MUXENTRY(SDMMC1_DAT0, 122,
517 "sdmmc1_dat0", NULL, NULL, NULL,
518 "gpio_122", NULL, NULL, "safe_mode"),
519 _OMAP3_MUXENTRY(SDMMC1_DAT1, 123,
520 "sdmmc1_dat1", NULL, NULL, NULL,
521 "gpio_123", NULL, NULL, "safe_mode"),
522 _OMAP3_MUXENTRY(SDMMC1_DAT2, 124,
523 "sdmmc1_dat2", NULL, NULL, NULL,
524 "gpio_124", NULL, NULL, "safe_mode"),
525 _OMAP3_MUXENTRY(SDMMC1_DAT3, 125,
526 "sdmmc1_dat3", NULL, NULL, NULL,
527 "gpio_125", NULL, NULL, "safe_mode"),
528 _OMAP3_MUXENTRY(SDMMC1_DAT4, 126,
529 "sdmmc1_dat4", NULL, "sim_io", NULL,
530 "gpio_126", NULL, NULL, "safe_mode"),
531 _OMAP3_MUXENTRY(SDMMC1_DAT5, 127,
532 "sdmmc1_dat5", NULL, "sim_clk", NULL,
533 "gpio_127", NULL, NULL, "safe_mode"),
534 _OMAP3_MUXENTRY(SDMMC1_DAT6, 128,
535 "sdmmc1_dat6", NULL, "sim_pwrctrl", NULL,
536 "gpio_128", NULL, NULL, "safe_mode"),
537 _OMAP3_MUXENTRY(SDMMC1_DAT7, 129,
538 "sdmmc1_dat7", NULL, "sim_rst", NULL,
539 "gpio_129", NULL, NULL, "safe_mode"),
540 _OMAP3_MUXENTRY(SDMMC2_CLK, 130,
541 "sdmmc2_clk", "mcspi3_clk", NULL, NULL,
542 "gpio_130", NULL, NULL, "safe_mode"),
543 _OMAP3_MUXENTRY(SDMMC2_CMD, 131,
544 "sdmmc2_cmd", "mcspi3_simo", NULL, NULL,
545 "gpio_131", NULL, NULL, "safe_mode"),
546 _OMAP3_MUXENTRY(SDMMC2_DAT0, 132,
547 "sdmmc2_dat0", "mcspi3_somi", NULL, NULL,
548 "gpio_132", NULL, NULL, "safe_mode"),
549 _OMAP3_MUXENTRY(SDMMC2_DAT1, 133,
550 "sdmmc2_dat1", NULL, NULL, NULL,
551 "gpio_133", NULL, NULL, "safe_mode"),
552 _OMAP3_MUXENTRY(SDMMC2_DAT2, 134,
553 "sdmmc2_dat2", "mcspi3_cs1", NULL, NULL,
554 "gpio_134", NULL, NULL, "safe_mode"),
555 _OMAP3_MUXENTRY(SDMMC2_DAT3, 135,
556 "sdmmc2_dat3", "mcspi3_cs0", NULL, NULL,
557 "gpio_135", NULL, NULL, "safe_mode"),
558 _OMAP3_MUXENTRY(SDMMC2_DAT4, 136,
559 "sdmmc2_dat4", "sdmmc2_dir_dat0", NULL, "sdmmc3_dat0",
560 "gpio_136", NULL, NULL, "safe_mode"),
561 _OMAP3_MUXENTRY(SDMMC2_DAT5, 137,
562 "sdmmc2_dat5", "sdmmc2_dir_dat1",
563 "cam_global_reset", "sdmmc3_dat1",
564 "gpio_137", "hsusb3_tll_stp", "mm3_rxdp", "safe_mode"),
565 _OMAP3_MUXENTRY(SDMMC2_DAT6, 138,
566 "sdmmc2_dat6", "sdmmc2_dir_cmd", "cam_shutter", "sdmmc3_dat2",
567 "gpio_138", "hsusb3_tll_dir", NULL, "safe_mode"),
568 _OMAP3_MUXENTRY(SDMMC2_DAT7, 139,
569 "sdmmc2_dat7", "sdmmc2_clkin", NULL, "sdmmc3_dat3",
570 "gpio_139", "hsusb3_tll_nxt", "mm3_rxdm", "safe_mode"),
571 _OMAP3_MUXENTRY(SDRC_CKE0, 0,
572 "sdrc_cke0", NULL, NULL, NULL,
573 NULL, NULL, NULL, "safe_mode"),
574 _OMAP3_MUXENTRY(SDRC_CKE1, 0,
575 "sdrc_cke1", NULL, NULL, NULL,
576 NULL, NULL, NULL, "safe_mode"),
577 _OMAP3_MUXENTRY(SYS_BOOT0, 2,
578 "sys_boot0", NULL, NULL, NULL,
579 "gpio_2", NULL, NULL, "safe_mode"),
580 _OMAP3_MUXENTRY(SYS_BOOT1, 3,
581 "sys_boot1", NULL, NULL, NULL,
582 "gpio_3", NULL, NULL, "safe_mode"),
583 _OMAP3_MUXENTRY(SYS_BOOT2, 4,
584 "sys_boot2", NULL, NULL, NULL,
585 "gpio_4", NULL, NULL, "safe_mode"),
586 _OMAP3_MUXENTRY(SYS_BOOT3, 5,
587 "sys_boot3", NULL, NULL, NULL,
588 "gpio_5", NULL, NULL, "safe_mode"),
589 _OMAP3_MUXENTRY(SYS_BOOT4, 6,
590 "sys_boot4", "sdmmc2_dir_dat2", NULL, NULL,
591 "gpio_6", NULL, NULL, "safe_mode"),
592 _OMAP3_MUXENTRY(SYS_BOOT5, 7,
593 "sys_boot5", "sdmmc2_dir_dat3", NULL, NULL,
594 "gpio_7", NULL, NULL, "safe_mode"),
595 _OMAP3_MUXENTRY(SYS_BOOT6, 8,
596 "sys_boot6", NULL, NULL, NULL,
597 "gpio_8", NULL, NULL, "safe_mode"),
598 _OMAP3_MUXENTRY(SYS_CLKOUT1, 10,
599 "sys_clkout1", NULL, NULL, NULL,
600 "gpio_10", NULL, NULL, "safe_mode"),
601 _OMAP3_MUXENTRY(SYS_CLKOUT2, 186,
602 "sys_clkout2", NULL, NULL, NULL,
603 "gpio_186", NULL, NULL, "safe_mode"),
604 _OMAP3_MUXENTRY(SYS_CLKREQ, 1,
605 "sys_clkreq", NULL, NULL, NULL,
606 "gpio_1", NULL, NULL, "safe_mode"),
607 _OMAP3_MUXENTRY(SYS_NIRQ, 0,
608 "sys_nirq", NULL, NULL, NULL,
609 "gpio_0", NULL, NULL, "safe_mode"),
610 _OMAP3_MUXENTRY(SYS_NRESWARM, 30,
611 "sys_nreswarm", NULL, NULL, NULL,
612 "gpio_30", NULL, NULL, "safe_mode"),
613 _OMAP3_MUXENTRY(SYS_OFF_MODE, 9,
614 "sys_off_mode", NULL, NULL, NULL,
615 "gpio_9", NULL, NULL, "safe_mode"),
616 _OMAP3_MUXENTRY(UART1_CTS, 150,
617 "uart1_cts", "ssi1_rdy_tx", NULL, NULL,
618 "gpio_150", "hsusb3_tll_clk", NULL, "safe_mode"),
619 _OMAP3_MUXENTRY(UART1_RTS, 149,
620 "uart1_rts", "ssi1_flag_tx", NULL, NULL,
621 "gpio_149", NULL, NULL, "safe_mode"),
622 _OMAP3_MUXENTRY(UART1_RX, 151,
623 "uart1_rx", "ssi1_wake_tx", "mcbsp1_clkr", "mcspi4_clk",
624 "gpio_151", NULL, NULL, "safe_mode"),
625 _OMAP3_MUXENTRY(UART1_TX, 148,
626 "uart1_tx", "ssi1_dat_tx", NULL, NULL,
627 "gpio_148", NULL, NULL, "safe_mode"),
628 _OMAP3_MUXENTRY(UART2_CTS, 144,
629 "uart2_cts", "mcbsp3_dx", "gpt9_pwm_evt", NULL,
630 "gpio_144", NULL, NULL, "safe_mode"),
631 _OMAP3_MUXENTRY(UART2_RTS, 145,
632 "uart2_rts", "mcbsp3_dr", "gpt10_pwm_evt", NULL,
633 "gpio_145", NULL, NULL, "safe_mode"),
634 _OMAP3_MUXENTRY(UART2_RX, 147,
635 "uart2_rx", "mcbsp3_fsx", "gpt8_pwm_evt", NULL,
636 "gpio_147", NULL, NULL, "safe_mode"),
637 _OMAP3_MUXENTRY(UART2_TX, 146,
638 "uart2_tx", "mcbsp3_clkx", "gpt11_pwm_evt", NULL,
639 "gpio_146", NULL, NULL, "safe_mode"),
640 _OMAP3_MUXENTRY(UART3_CTS_RCTX, 163,
641 "uart3_cts_rctx", NULL, NULL, NULL,
642 "gpio_163", NULL, NULL, "safe_mode"),
643 _OMAP3_MUXENTRY(UART3_RTS_SD, 164,
644 "uart3_rts_sd", NULL, NULL, NULL,
645 "gpio_164", NULL, NULL, "safe_mode"),
646 _OMAP3_MUXENTRY(UART3_RX_IRRX, 165,
647 "uart3_rx_irrx", NULL, NULL, NULL,
648 "gpio_165", NULL, NULL, "safe_mode"),
649 _OMAP3_MUXENTRY(UART3_TX_IRTX, 166,
650 "uart3_tx_irtx", NULL, NULL, NULL,
651 "gpio_166", NULL, NULL, "safe_mode"),
652
653 /* Only on 3630, see omap36xx_cbp_subset for the signals */
654 _OMAP3_MUXENTRY(GPMC_A11, 0,
655 NULL, NULL, NULL, NULL,
656 NULL, NULL, NULL, NULL),
657 _OMAP3_MUXENTRY(SAD2D_MBUSFLAG, 0,
658 NULL, NULL, NULL, NULL,
659 NULL, NULL, NULL, NULL),
660 _OMAP3_MUXENTRY(SAD2D_MREAD, 0,
661 NULL, NULL, NULL, NULL,
662 NULL, NULL, NULL, NULL),
663 _OMAP3_MUXENTRY(SAD2D_MWRITE, 0,
664 NULL, NULL, NULL, NULL,
665 NULL, NULL, NULL, NULL),
666 _OMAP3_MUXENTRY(SAD2D_SBUSFLAG, 0,
667 NULL, NULL, NULL, NULL,
668 NULL, NULL, NULL, NULL),
669 _OMAP3_MUXENTRY(SAD2D_SREAD, 0,
670 NULL, NULL, NULL, NULL,
671 NULL, NULL, NULL, NULL),
672 _OMAP3_MUXENTRY(SAD2D_SWRITE, 0,
673 NULL, NULL, NULL, NULL,
674 NULL, NULL, NULL, NULL),
675 _OMAP3_MUXENTRY(GPMC_A11, 0,
676 NULL, NULL, NULL, NULL,
677 NULL, NULL, NULL, NULL),
678 _OMAP3_MUXENTRY(SAD2D_MCAD28, 0,
679 NULL, NULL, NULL, NULL,
680 NULL, NULL, NULL, NULL),
681 _OMAP3_MUXENTRY(SAD2D_MCAD29, 0,
682 NULL, NULL, NULL, NULL,
683 NULL, NULL, NULL, NULL),
684 _OMAP3_MUXENTRY(SAD2D_MCAD32, 0,
685 NULL, NULL, NULL, NULL,
686 NULL, NULL, NULL, NULL),
687 _OMAP3_MUXENTRY(SAD2D_MCAD33, 0,
688 NULL, NULL, NULL, NULL,
689 NULL, NULL, NULL, NULL),
690 _OMAP3_MUXENTRY(SAD2D_MCAD34, 0,
691 NULL, NULL, NULL, NULL,
692 NULL, NULL, NULL, NULL),
693 _OMAP3_MUXENTRY(SAD2D_MCAD35, 0,
694 NULL, NULL, NULL, NULL,
695 NULL, NULL, NULL, NULL),
696 _OMAP3_MUXENTRY(SAD2D_MCAD36, 0,
697 NULL, NULL, NULL, NULL,
698 NULL, NULL, NULL, NULL),
699 { .reg_offset = OMAP_MUX_TERMINATOR },
700};
701
702/*
703 * Signals different on CBC package compared to the superset
704 */
705#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_OMAP_PACKAGE_CBC)
706static struct omap_mux __initdata omap3_cbc_subset[] = {
707 { .reg_offset = OMAP_MUX_TERMINATOR },
708};
709#else
710#define omap3_cbc_subset NULL
711#endif
712
713/*
714 * Balls for CBC package
715 * 515-pin s-PBGA Package, 0.65mm Ball Pitch (Top), 0.50mm Ball Pitch (Bottom)
716 *
717 * FIXME: What's up with the outdated TI documentation? See:
718 *
719 * http://wiki.davincidsp.com/index.php/Datasheet_Errata_for_OMAP35x_CBC_Package
720 * http://community.ti.com/forums/t/10982.aspx
721 */
722#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \
723 && defined(CONFIG_OMAP_PACKAGE_CBC)
724static struct omap_ball __initdata omap3_cbc_ball[] = {
725 _OMAP3_BALLENTRY(CAM_D0, "ae16", NULL),
726 _OMAP3_BALLENTRY(CAM_D1, "ae15", NULL),
727 _OMAP3_BALLENTRY(CAM_D10, "d25", NULL),
728 _OMAP3_BALLENTRY(CAM_D11, "e26", NULL),
729 _OMAP3_BALLENTRY(CAM_D2, "a24", NULL),
730 _OMAP3_BALLENTRY(CAM_D3, "b24", NULL),
731 _OMAP3_BALLENTRY(CAM_D4, "d24", NULL),
732 _OMAP3_BALLENTRY(CAM_D5, "c24", NULL),
733 _OMAP3_BALLENTRY(CAM_D6, "p25", NULL),
734 _OMAP3_BALLENTRY(CAM_D7, "p26", NULL),
735 _OMAP3_BALLENTRY(CAM_D8, "n25", NULL),
736 _OMAP3_BALLENTRY(CAM_D9, "n26", NULL),
737 _OMAP3_BALLENTRY(CAM_FLD, "b23", NULL),
738 _OMAP3_BALLENTRY(CAM_HS, "c23", NULL),
739 _OMAP3_BALLENTRY(CAM_PCLK, "c26", NULL),
740 _OMAP3_BALLENTRY(CAM_STROBE, "d26", NULL),
741 _OMAP3_BALLENTRY(CAM_VS, "d23", NULL),
742 _OMAP3_BALLENTRY(CAM_WEN, "a23", NULL),
743 _OMAP3_BALLENTRY(CAM_XCLKA, "c25", NULL),
744 _OMAP3_BALLENTRY(CAM_XCLKB, "e25", NULL),
745 _OMAP3_BALLENTRY(CSI2_DX0, "ad17", NULL),
746 _OMAP3_BALLENTRY(CSI2_DX1, "ae18", NULL),
747 _OMAP3_BALLENTRY(CSI2_DY0, "ad16", NULL),
748 _OMAP3_BALLENTRY(CSI2_DY1, "ae17", NULL),
749 _OMAP3_BALLENTRY(DSS_ACBIAS, "f26", NULL),
750 _OMAP3_BALLENTRY(DSS_DATA0, "ae21", NULL),
751 _OMAP3_BALLENTRY(DSS_DATA1, "ae22", NULL),
752 _OMAP3_BALLENTRY(DSS_DATA10, "ac26", NULL),
753 _OMAP3_BALLENTRY(DSS_DATA11, "ad26", NULL),
754 _OMAP3_BALLENTRY(DSS_DATA12, "aa25", NULL),
755 _OMAP3_BALLENTRY(DSS_DATA13, "y25", NULL),
756 _OMAP3_BALLENTRY(DSS_DATA14, "aa26", NULL),
757 _OMAP3_BALLENTRY(DSS_DATA15, "ab26", NULL),
758 _OMAP3_BALLENTRY(DSS_DATA16, "l25", NULL),
759 _OMAP3_BALLENTRY(DSS_DATA17, "l26", NULL),
760 _OMAP3_BALLENTRY(DSS_DATA18, "m24", NULL),
761 _OMAP3_BALLENTRY(DSS_DATA19, "m26", NULL),
762 _OMAP3_BALLENTRY(DSS_DATA2, "ae23", NULL),
763 _OMAP3_BALLENTRY(DSS_DATA20, "f25", NULL),
764 _OMAP3_BALLENTRY(DSS_DATA21, "n24", NULL),
765 _OMAP3_BALLENTRY(DSS_DATA22, "ac25", NULL),
766 _OMAP3_BALLENTRY(DSS_DATA23, "ab25", NULL),
767 _OMAP3_BALLENTRY(DSS_DATA3, "ae24", NULL),
768 _OMAP3_BALLENTRY(DSS_DATA4, "ad23", NULL),
769 _OMAP3_BALLENTRY(DSS_DATA5, "ad24", NULL),
770 _OMAP3_BALLENTRY(DSS_DATA6, "g26", NULL),
771 _OMAP3_BALLENTRY(DSS_DATA7, "h25", NULL),
772 _OMAP3_BALLENTRY(DSS_DATA8, "h26", NULL),
773 _OMAP3_BALLENTRY(DSS_DATA9, "j26", NULL),
774 _OMAP3_BALLENTRY(DSS_HSYNC, "k24", NULL),
775 _OMAP3_BALLENTRY(DSS_PCLK, "g25", NULL),
776 _OMAP3_BALLENTRY(DSS_VSYNC, "m25", NULL),
777 _OMAP3_BALLENTRY(ETK_CLK, "ab2", NULL),
778 _OMAP3_BALLENTRY(ETK_CTL, "ab3", NULL),
779 _OMAP3_BALLENTRY(ETK_D0, "ac3", NULL),
780 _OMAP3_BALLENTRY(ETK_D1, "ad4", NULL),
781 _OMAP3_BALLENTRY(ETK_D10, "ae4", NULL),
782 _OMAP3_BALLENTRY(ETK_D11, "af6", NULL),
783 _OMAP3_BALLENTRY(ETK_D12, "ae6", NULL),
784 _OMAP3_BALLENTRY(ETK_D13, "af7", NULL),
785 _OMAP3_BALLENTRY(ETK_D14, "af9", NULL),
786 _OMAP3_BALLENTRY(ETK_D15, "ae9", NULL),
787 _OMAP3_BALLENTRY(ETK_D2, "ad3", NULL),
788 _OMAP3_BALLENTRY(ETK_D3, "aa3", NULL),
789 _OMAP3_BALLENTRY(ETK_D4, "y3", NULL),
790 _OMAP3_BALLENTRY(ETK_D5, "ab1", NULL),
791 _OMAP3_BALLENTRY(ETK_D6, "ae3", NULL),
792 _OMAP3_BALLENTRY(ETK_D7, "ad2", NULL),
793 _OMAP3_BALLENTRY(ETK_D8, "aa4", NULL),
794 _OMAP3_BALLENTRY(ETK_D9, "v2", NULL),
795 _OMAP3_BALLENTRY(GPMC_A1, "j2", NULL),
796 _OMAP3_BALLENTRY(GPMC_A10, "d2", NULL),
797 _OMAP3_BALLENTRY(GPMC_A2, "h1", NULL),
798 _OMAP3_BALLENTRY(GPMC_A3, "h2", NULL),
799 _OMAP3_BALLENTRY(GPMC_A4, "g2", NULL),
800 _OMAP3_BALLENTRY(GPMC_A5, "f1", NULL),
801 _OMAP3_BALLENTRY(GPMC_A6, "f2", NULL),
802 _OMAP3_BALLENTRY(GPMC_A7, "e1", NULL),
803 _OMAP3_BALLENTRY(GPMC_A8, "e2", NULL),
804 _OMAP3_BALLENTRY(GPMC_A9, "d1", NULL),
805 _OMAP3_BALLENTRY(GPMC_CLK, "n1", "l1"),
806 _OMAP3_BALLENTRY(GPMC_D10, "t1", "n1"),
807 _OMAP3_BALLENTRY(GPMC_D11, "u2", "p2"),
808 _OMAP3_BALLENTRY(GPMC_D12, "u1", "p1"),
809 _OMAP3_BALLENTRY(GPMC_D13, "p1", "m1"),
810 _OMAP3_BALLENTRY(GPMC_D14, "l2", "j2"),
811 _OMAP3_BALLENTRY(GPMC_D15, "m2", "k2"),
812 _OMAP3_BALLENTRY(GPMC_D8, "v1", "r1"),
813 _OMAP3_BALLENTRY(GPMC_D9, "y1", "t1"),
814 _OMAP3_BALLENTRY(GPMC_NBE0_CLE, "k2", NULL),
815 _OMAP3_BALLENTRY(GPMC_NBE1, "j1", NULL),
816 _OMAP3_BALLENTRY(GPMC_NCS1, "ad1", "w1"),
817 _OMAP3_BALLENTRY(GPMC_NCS2, "a3", NULL),
818 _OMAP3_BALLENTRY(GPMC_NCS3, "b6", NULL),
819 _OMAP3_BALLENTRY(GPMC_NCS4, "b4", NULL),
820 _OMAP3_BALLENTRY(GPMC_NCS5, "c4", NULL),
821 _OMAP3_BALLENTRY(GPMC_NCS6, "b5", NULL),
822 _OMAP3_BALLENTRY(GPMC_NCS7, "c5", NULL),
823 _OMAP3_BALLENTRY(GPMC_NWP, "ac6", "y5"),
824 _OMAP3_BALLENTRY(GPMC_WAIT1, "ac8", "y8"),
825 _OMAP3_BALLENTRY(GPMC_WAIT2, "b3", NULL),
826 _OMAP3_BALLENTRY(GPMC_WAIT3, "c6", NULL),
827 _OMAP3_BALLENTRY(HDQ_SIO, "j23", NULL),
828 _OMAP3_BALLENTRY(HSUSB0_CLK, "w19", NULL),
829 _OMAP3_BALLENTRY(HSUSB0_DATA0, "v20", NULL),
830 _OMAP3_BALLENTRY(HSUSB0_DATA1, "y20", NULL),
831 _OMAP3_BALLENTRY(HSUSB0_DATA2, "v18", NULL),
832 _OMAP3_BALLENTRY(HSUSB0_DATA3, "w20", NULL),
833 _OMAP3_BALLENTRY(HSUSB0_DATA4, "w17", NULL),
834 _OMAP3_BALLENTRY(HSUSB0_DATA5, "y18", NULL),
835 _OMAP3_BALLENTRY(HSUSB0_DATA6, "y19", NULL),
836 _OMAP3_BALLENTRY(HSUSB0_DATA7, "y17", NULL),
837 _OMAP3_BALLENTRY(HSUSB0_DIR, "v19", NULL),
838 _OMAP3_BALLENTRY(HSUSB0_NXT, "w18", NULL),
839 _OMAP3_BALLENTRY(HSUSB0_STP, "u20", NULL),
840 _OMAP3_BALLENTRY(I2C2_SCL, "c2", NULL),
841 _OMAP3_BALLENTRY(I2C2_SDA, "c1", NULL),
842 _OMAP3_BALLENTRY(I2C3_SCL, "ab4", NULL),
843 _OMAP3_BALLENTRY(I2C3_SDA, "ac4", NULL),
844 _OMAP3_BALLENTRY(I2C4_SCL, "ad15", NULL),
845 _OMAP3_BALLENTRY(I2C4_SDA, "w16", NULL),
846 _OMAP3_BALLENTRY(JTAG_EMU0, "y15", NULL),
847 _OMAP3_BALLENTRY(JTAG_EMU1, "y14", NULL),
848 _OMAP3_BALLENTRY(MCBSP1_CLKR, "u19", NULL),
849 _OMAP3_BALLENTRY(MCBSP1_CLKX, "t17", NULL),
850 _OMAP3_BALLENTRY(MCBSP1_DR, "t20", NULL),
851 _OMAP3_BALLENTRY(MCBSP1_DX, "u17", NULL),
852 _OMAP3_BALLENTRY(MCBSP1_FSR, "v17", NULL),
853 _OMAP3_BALLENTRY(MCBSP1_FSX, "p20", NULL),
854 _OMAP3_BALLENTRY(MCBSP2_CLKX, "r18", NULL),
855 _OMAP3_BALLENTRY(MCBSP2_DR, "t18", NULL),
856 _OMAP3_BALLENTRY(MCBSP2_DX, "r19", NULL),
857 _OMAP3_BALLENTRY(MCBSP2_FSX, "u18", NULL),
858 _OMAP3_BALLENTRY(MCBSP3_CLKX, "u3", NULL),
859 _OMAP3_BALLENTRY(MCBSP3_DR, "n3", NULL),
860 _OMAP3_BALLENTRY(MCBSP3_DX, "p3", NULL),
861 _OMAP3_BALLENTRY(MCBSP3_FSX, "w3", NULL),
862 _OMAP3_BALLENTRY(MCBSP4_CLKX, "v3", NULL),
863 _OMAP3_BALLENTRY(MCBSP4_DR, "u4", NULL),
864 _OMAP3_BALLENTRY(MCBSP4_DX, "r3", NULL),
865 _OMAP3_BALLENTRY(MCBSP4_FSX, "t3", NULL),
866 _OMAP3_BALLENTRY(MCBSP_CLKS, "t19", NULL),
867 _OMAP3_BALLENTRY(MCSPI1_CLK, "p9", NULL),
868 _OMAP3_BALLENTRY(MCSPI1_CS0, "r7", NULL),
869 _OMAP3_BALLENTRY(MCSPI1_CS1, "r8", NULL),
870 _OMAP3_BALLENTRY(MCSPI1_CS2, "r9", NULL),
871 _OMAP3_BALLENTRY(MCSPI1_CS3, "t8", NULL),
872 _OMAP3_BALLENTRY(MCSPI1_SIMO, "p8", NULL),
873 _OMAP3_BALLENTRY(MCSPI1_SOMI, "p7", NULL),
874 _OMAP3_BALLENTRY(MCSPI2_CLK, "w7", NULL),
875 _OMAP3_BALLENTRY(MCSPI2_CS0, "v8", NULL),
876 _OMAP3_BALLENTRY(MCSPI2_CS1, "v9", NULL),
877 _OMAP3_BALLENTRY(MCSPI2_SIMO, "w8", NULL),
878 _OMAP3_BALLENTRY(MCSPI2_SOMI, "u8", NULL),
879 _OMAP3_BALLENTRY(SDMMC1_CLK, "n19", NULL),
880 _OMAP3_BALLENTRY(SDMMC1_CMD, "l18", NULL),
881 _OMAP3_BALLENTRY(SDMMC1_DAT0, "m19", NULL),
882 _OMAP3_BALLENTRY(SDMMC1_DAT1, "m18", NULL),
883 _OMAP3_BALLENTRY(SDMMC1_DAT2, "k18", NULL),
884 _OMAP3_BALLENTRY(SDMMC1_DAT3, "n20", NULL),
885 _OMAP3_BALLENTRY(SDMMC1_DAT4, "m20", NULL),
886 _OMAP3_BALLENTRY(SDMMC1_DAT5, "p17", NULL),
887 _OMAP3_BALLENTRY(SDMMC1_DAT6, "p18", NULL),
888 _OMAP3_BALLENTRY(SDMMC1_DAT7, "p19", NULL),
889 _OMAP3_BALLENTRY(SDMMC2_CLK, "w10", NULL),
890 _OMAP3_BALLENTRY(SDMMC2_CMD, "r10", NULL),
891 _OMAP3_BALLENTRY(SDMMC2_DAT0, "t10", NULL),
892 _OMAP3_BALLENTRY(SDMMC2_DAT1, "t9", NULL),
893 _OMAP3_BALLENTRY(SDMMC2_DAT2, "u10", NULL),
894 _OMAP3_BALLENTRY(SDMMC2_DAT3, "u9", NULL),
895 _OMAP3_BALLENTRY(SDMMC2_DAT4, "v10", NULL),
896 _OMAP3_BALLENTRY(SDMMC2_DAT5, "m3", NULL),
897 _OMAP3_BALLENTRY(SDMMC2_DAT6, "l3", NULL),
898 _OMAP3_BALLENTRY(SDMMC2_DAT7, "k3", NULL),
899 _OMAP3_BALLENTRY(SYS_BOOT0, "f3", NULL),
900 _OMAP3_BALLENTRY(SYS_BOOT1, "d3", NULL),
901 _OMAP3_BALLENTRY(SYS_BOOT2, "c3", NULL),
902 _OMAP3_BALLENTRY(SYS_BOOT3, "e3", NULL),
903 _OMAP3_BALLENTRY(SYS_BOOT4, "e4", NULL),
904 _OMAP3_BALLENTRY(SYS_BOOT5, "g3", NULL),
905 _OMAP3_BALLENTRY(SYS_BOOT6, "d4", NULL),
906 _OMAP3_BALLENTRY(SYS_CLKOUT1, "ae14", NULL),
907 _OMAP3_BALLENTRY(SYS_CLKOUT2, "w11", NULL),
908 _OMAP3_BALLENTRY(SYS_CLKREQ, "w15", NULL),
909 _OMAP3_BALLENTRY(SYS_NIRQ, "v16", NULL),
910 _OMAP3_BALLENTRY(SYS_NRESWARM, "ad7", "aa5"),
911 _OMAP3_BALLENTRY(SYS_OFF_MODE, "v12", NULL),
912 _OMAP3_BALLENTRY(UART1_CTS, "w2", NULL),
913 _OMAP3_BALLENTRY(UART1_RTS, "r2", NULL),
914 _OMAP3_BALLENTRY(UART1_RX, "h3", NULL),
915 _OMAP3_BALLENTRY(UART1_TX, "l4", NULL),
916 _OMAP3_BALLENTRY(UART2_CTS, "y24", NULL),
917 _OMAP3_BALLENTRY(UART2_RTS, "aa24", NULL),
918 _OMAP3_BALLENTRY(UART2_RX, "ad21", NULL),
919 _OMAP3_BALLENTRY(UART2_TX, "ad22", NULL),
920 _OMAP3_BALLENTRY(UART3_CTS_RCTX, "f23", NULL),
921 _OMAP3_BALLENTRY(UART3_RTS_SD, "f24", NULL),
922 _OMAP3_BALLENTRY(UART3_RX_IRRX, "h24", NULL),
923 _OMAP3_BALLENTRY(UART3_TX_IRTX, "g24", NULL),
924 { .reg_offset = OMAP_MUX_TERMINATOR },
925};
926#else
927#define omap3_cbc_ball NULL
928#endif
929
930/*
931 * Signals different on CUS package compared to superset
932 */
933#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_OMAP_PACKAGE_CUS)
934static struct omap_mux __initdata omap3_cus_subset[] = {
935 _OMAP3_MUXENTRY(CAM_D10, 109,
936 "cam_d10", NULL, NULL, NULL,
937 "gpio_109", NULL, NULL, "safe_mode"),
938 _OMAP3_MUXENTRY(CAM_D11, 110,
939 "cam_d11", NULL, NULL, NULL,
940 "gpio_110", NULL, NULL, "safe_mode"),
941 _OMAP3_MUXENTRY(CAM_D2, 101,
942 "cam_d2", NULL, NULL, NULL,
943 "gpio_101", NULL, NULL, "safe_mode"),
944 _OMAP3_MUXENTRY(CAM_D3, 102,
945 "cam_d3", NULL, NULL, NULL,
946 "gpio_102", NULL, NULL, "safe_mode"),
947 _OMAP3_MUXENTRY(CAM_D4, 103,
948 "cam_d4", NULL, NULL, NULL,
949 "gpio_103", NULL, NULL, "safe_mode"),
950 _OMAP3_MUXENTRY(CAM_D5, 104,
951 "cam_d5", NULL, NULL, NULL,
952 "gpio_104", NULL, NULL, "safe_mode"),
953 _OMAP3_MUXENTRY(CAM_FLD, 98,
954 "cam_fld", NULL, "cam_global_reset", NULL,
955 "gpio_98", NULL, NULL, "safe_mode"),
956 _OMAP3_MUXENTRY(CAM_HS, 94,
957 "cam_hs", NULL, NULL, NULL,
958 "gpio_94", NULL, NULL, "safe_mode"),
959 _OMAP3_MUXENTRY(CAM_PCLK, 97,
960 "cam_pclk", NULL, NULL, NULL,
961 "gpio_97", NULL, NULL, "safe_mode"),
962 _OMAP3_MUXENTRY(CAM_STROBE, 126,
963 "cam_strobe", NULL, NULL, NULL,
964 "gpio_126", NULL, NULL, "safe_mode"),
965 _OMAP3_MUXENTRY(CAM_VS, 95,
966 "cam_vs", NULL, NULL, NULL,
967 "gpio_95", NULL, NULL, "safe_mode"),
968 _OMAP3_MUXENTRY(CAM_WEN, 167,
969 "cam_wen", NULL, "cam_shutter", NULL,
970 "gpio_167", NULL, NULL, "safe_mode"),
971 _OMAP3_MUXENTRY(DSS_DATA6, 76,
972 "dss_data6", NULL, "uart1_tx", NULL,
973 "gpio_76", NULL, NULL, "safe_mode"),
974 _OMAP3_MUXENTRY(DSS_DATA7, 77,
975 "dss_data7", NULL, "uart1_rx", NULL,
976 "gpio_77", NULL, NULL, "safe_mode"),
977 _OMAP3_MUXENTRY(DSS_DATA8, 78,
978 "dss_data8", NULL, NULL, NULL,
979 "gpio_78", NULL, NULL, "safe_mode"),
980 _OMAP3_MUXENTRY(DSS_DATA9, 79,
981 "dss_data9", NULL, NULL, NULL,
982 "gpio_79", NULL, NULL, "safe_mode"),
983 _OMAP3_MUXENTRY(DSS_HSYNC, 67,
984 "dss_hsync", NULL, NULL, NULL,
985 "gpio_67", NULL, NULL, "safe_mode"),
986 _OMAP3_MUXENTRY(DSS_PCLK, 66,
987 "dss_pclk", NULL, NULL, NULL,
988 "gpio_66", NULL, NULL, "safe_mode"),
989 _OMAP3_MUXENTRY(ETK_CLK, 12,
990 "etk_clk", "mcbsp5_clkx", "sdmmc3_clk", "hsusb1_stp",
991 "gpio_12", "mm1_rxdp", "hsusb1_tll_stp", NULL),
992 _OMAP3_MUXENTRY(ETK_CTL, 13,
993 "etk_ctl", NULL, "sdmmc3_cmd", "hsusb1_clk",
994 "gpio_13", NULL, "hsusb1_tll_clk", NULL),
995 _OMAP3_MUXENTRY(ETK_D0, 14,
996 "etk_d0", "mcspi3_simo", "sdmmc3_dat4", "hsusb1_data0",
997 "gpio_14", "mm1_rxrcv", "hsusb1_tll_data0", NULL),
998 _OMAP3_MUXENTRY(ETK_D1, 15,
999 "etk_d1", "mcspi3_somi", NULL, "hsusb1_data1",
1000 "gpio_15", "mm1_txse0", "hsusb1_tll_data1", NULL),
1001 _OMAP3_MUXENTRY(ETK_D10, 24,
1002 "etk_d10", NULL, "uart1_rx", "hsusb2_clk",
1003 "gpio_24", NULL, "hsusb2_tll_clk", NULL),
1004 _OMAP3_MUXENTRY(ETK_D11, 25,
1005 "etk_d11", NULL, NULL, "hsusb2_stp",
1006 "gpio_25", "mm2_rxdp", "hsusb2_tll_stp", NULL),
1007 _OMAP3_MUXENTRY(ETK_D12, 26,
1008 "etk_d12", NULL, NULL, "hsusb2_dir",
1009 "gpio_26", NULL, "hsusb2_tll_dir", NULL),
1010 _OMAP3_MUXENTRY(ETK_D13, 27,
1011 "etk_d13", NULL, NULL, "hsusb2_nxt",
1012 "gpio_27", "mm2_rxdm", "hsusb2_tll_nxt", NULL),
1013 _OMAP3_MUXENTRY(ETK_D14, 28,
1014 "etk_d14", NULL, NULL, "hsusb2_data0",
1015 "gpio_28", "mm2_rxrcv", "hsusb2_tll_data0", NULL),
1016 _OMAP3_MUXENTRY(ETK_D15, 29,
1017 "etk_d15", NULL, NULL, "hsusb2_data1",
1018 "gpio_29", "mm2_txse0", "hsusb2_tll_data1", NULL),
1019 _OMAP3_MUXENTRY(ETK_D2, 16,
1020 "etk_d2", "mcspi3_cs0", NULL, "hsusb1_data2",
1021 "gpio_16", "mm1_txdat", "hsusb1_tll_data2", NULL),
1022 _OMAP3_MUXENTRY(ETK_D3, 17,
1023 "etk_d3", "mcspi3_clk", "sdmmc3_dat3", "hsusb1_data7",
1024 "gpio_17", NULL, "hsusb1_tll_data7", NULL),
1025 _OMAP3_MUXENTRY(ETK_D4, 18,
1026 "etk_d4", "mcbsp5_dr", "sdmmc3_dat0", "hsusb1_data4",
1027 "gpio_18", NULL, "hsusb1_tll_data4", NULL),
1028 _OMAP3_MUXENTRY(ETK_D5, 19,
1029 "etk_d5", "mcbsp5_fsx", "sdmmc3_dat1", "hsusb1_data5",
1030 "gpio_19", NULL, "hsusb1_tll_data5", NULL),
1031 _OMAP3_MUXENTRY(ETK_D6, 20,
1032 "etk_d6", "mcbsp5_dx", "sdmmc3_dat2", "hsusb1_data6",
1033 "gpio_20", NULL, "hsusb1_tll_data6", NULL),
1034 _OMAP3_MUXENTRY(ETK_D7, 21,
1035 "etk_d7", "mcspi3_cs1", "sdmmc3_dat7", "hsusb1_data3",
1036 "gpio_21", "mm1_txen_n", "hsusb1_tll_data3", NULL),
1037 _OMAP3_MUXENTRY(ETK_D8, 22,
1038 "etk_d8", "sys_drm_msecure", "sdmmc3_dat6", "hsusb1_dir",
1039 "gpio_22", NULL, "hsusb1_tll_dir", NULL),
1040 _OMAP3_MUXENTRY(ETK_D9, 23,
1041 "etk_d9", "sys_secure_indicator", "sdmmc3_dat5", "hsusb1_nxt",
1042 "gpio_23", "mm1_rxdm", "hsusb1_tll_nxt", NULL),
1043 _OMAP3_MUXENTRY(MCBSP3_CLKX, 142,
1044 "mcbsp3_clkx", "uart2_tx", NULL, NULL,
1045 "gpio_142", NULL, NULL, "safe_mode"),
1046 _OMAP3_MUXENTRY(MCBSP3_DR, 141,
1047 "mcbsp3_dr", "uart2_rts", NULL, NULL,
1048 "gpio_141", NULL, NULL, "safe_mode"),
1049 _OMAP3_MUXENTRY(MCBSP3_DX, 140,
1050 "mcbsp3_dx", "uart2_cts", NULL, NULL,
1051 "gpio_140", NULL, NULL, "safe_mode"),
1052 _OMAP3_MUXENTRY(MCBSP3_FSX, 143,
1053 "mcbsp3_fsx", "uart2_rx", NULL, NULL,
1054 "gpio_143", NULL, NULL, "safe_mode"),
1055 _OMAP3_MUXENTRY(SDMMC2_DAT5, 137,
1056 "sdmmc2_dat5", "sdmmc2_dir_dat1",
1057 "cam_global_reset", "sdmmc3_dat1",
1058 "gpio_137", NULL, NULL, "safe_mode"),
1059 _OMAP3_MUXENTRY(SDMMC2_DAT6, 138,
1060 "sdmmc2_dat6", "sdmmc2_dir_cmd", "cam_shutter", "sdmmc3_dat2",
1061 "gpio_138", NULL, NULL, "safe_mode"),
1062 _OMAP3_MUXENTRY(SDMMC2_DAT7, 139,
1063 "sdmmc2_dat7", "sdmmc2_clkin", NULL, "sdmmc3_dat3",
1064 "gpio_139", NULL, NULL, "safe_mode"),
1065 _OMAP3_MUXENTRY(UART1_CTS, 150,
1066 "uart1_cts", NULL, NULL, NULL,
1067 "gpio_150", NULL, NULL, "safe_mode"),
1068 { .reg_offset = OMAP_MUX_TERMINATOR },
1069};
1070#else
1071#define omap3_cus_subset NULL
1072#endif
1073
1074/*
1075 * Balls for CUS package
1076 * 423-pin s-PBGA Package, 0.65mm Ball Pitch (Bottom)
1077 */
1078#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \
1079 && defined(CONFIG_OMAP_PACKAGE_CUS)
1080static struct omap_ball __initdata omap3_cus_ball[] = {
1081 _OMAP3_BALLENTRY(CAM_D0, "ab18", NULL),
1082 _OMAP3_BALLENTRY(CAM_D1, "ac18", NULL),
1083 _OMAP3_BALLENTRY(CAM_D10, "f21", NULL),
1084 _OMAP3_BALLENTRY(CAM_D11, "g21", NULL),
1085 _OMAP3_BALLENTRY(CAM_D2, "g19", NULL),
1086 _OMAP3_BALLENTRY(CAM_D3, "f19", NULL),
1087 _OMAP3_BALLENTRY(CAM_D4, "g20", NULL),
1088 _OMAP3_BALLENTRY(CAM_D5, "b21", NULL),
1089 _OMAP3_BALLENTRY(CAM_D6, "l24", NULL),
1090 _OMAP3_BALLENTRY(CAM_D7, "k24", NULL),
1091 _OMAP3_BALLENTRY(CAM_D8, "j23", NULL),
1092 _OMAP3_BALLENTRY(CAM_D9, "k23", NULL),
1093 _OMAP3_BALLENTRY(CAM_FLD, "h24", NULL),
1094 _OMAP3_BALLENTRY(CAM_HS, "a22", NULL),
1095 _OMAP3_BALLENTRY(CAM_PCLK, "j19", NULL),
1096 _OMAP3_BALLENTRY(CAM_STROBE, "j20", NULL),
1097 _OMAP3_BALLENTRY(CAM_VS, "e18", NULL),
1098 _OMAP3_BALLENTRY(CAM_WEN, "f18", NULL),
1099 _OMAP3_BALLENTRY(CAM_XCLKA, "b22", NULL),
1100 _OMAP3_BALLENTRY(CAM_XCLKB, "c22", NULL),
1101 _OMAP3_BALLENTRY(DSS_ACBIAS, "j21", NULL),
1102 _OMAP3_BALLENTRY(DSS_DATA0, "ac19", NULL),
1103 _OMAP3_BALLENTRY(DSS_DATA1, "ab19", NULL),
1104 _OMAP3_BALLENTRY(DSS_DATA10, "ac22", NULL),
1105 _OMAP3_BALLENTRY(DSS_DATA11, "ac23", NULL),
1106 _OMAP3_BALLENTRY(DSS_DATA12, "ab22", NULL),
1107 _OMAP3_BALLENTRY(DSS_DATA13, "y22", NULL),
1108 _OMAP3_BALLENTRY(DSS_DATA14, "w22", NULL),
1109 _OMAP3_BALLENTRY(DSS_DATA15, "v22", NULL),
1110 _OMAP3_BALLENTRY(DSS_DATA16, "j22", NULL),
1111 _OMAP3_BALLENTRY(DSS_DATA17, "g23", NULL),
1112 _OMAP3_BALLENTRY(DSS_DATA18, "g24", NULL),
1113 _OMAP3_BALLENTRY(DSS_DATA19, "h23", NULL),
1114 _OMAP3_BALLENTRY(DSS_DATA2, "ad20", NULL),
1115 _OMAP3_BALLENTRY(DSS_DATA20, "d23", NULL),
1116 _OMAP3_BALLENTRY(DSS_DATA21, "k22", NULL),
1117 _OMAP3_BALLENTRY(DSS_DATA22, "v21", NULL),
1118 _OMAP3_BALLENTRY(DSS_DATA23, "w21", NULL),
1119 _OMAP3_BALLENTRY(DSS_DATA3, "ac20", NULL),
1120 _OMAP3_BALLENTRY(DSS_DATA4, "ad21", NULL),
1121 _OMAP3_BALLENTRY(DSS_DATA5, "ac21", NULL),
1122 _OMAP3_BALLENTRY(DSS_DATA6, "d24", NULL),
1123 _OMAP3_BALLENTRY(DSS_DATA7, "e23", NULL),
1124 _OMAP3_BALLENTRY(DSS_DATA8, "e24", NULL),
1125 _OMAP3_BALLENTRY(DSS_DATA9, "f23", NULL),
1126 _OMAP3_BALLENTRY(DSS_HSYNC, "e22", NULL),
1127 _OMAP3_BALLENTRY(DSS_PCLK, "g22", NULL),
1128 _OMAP3_BALLENTRY(DSS_VSYNC, "f22", NULL),
1129 _OMAP3_BALLENTRY(ETK_CLK, "ac1", NULL),
1130 _OMAP3_BALLENTRY(ETK_CTL, "ad3", NULL),
1131 _OMAP3_BALLENTRY(ETK_D0, "ad6", NULL),
1132 _OMAP3_BALLENTRY(ETK_D1, "ac6", NULL),
1133 _OMAP3_BALLENTRY(ETK_D10, "ac3", NULL),
1134 _OMAP3_BALLENTRY(ETK_D11, "ac9", NULL),
1135 _OMAP3_BALLENTRY(ETK_D12, "ac10", NULL),
1136 _OMAP3_BALLENTRY(ETK_D13, "ad11", NULL),
1137 _OMAP3_BALLENTRY(ETK_D14, "ac11", NULL),
1138 _OMAP3_BALLENTRY(ETK_D15, "ad12", NULL),
1139 _OMAP3_BALLENTRY(ETK_D2, "ac7", NULL),
1140 _OMAP3_BALLENTRY(ETK_D3, "ad8", NULL),
1141 _OMAP3_BALLENTRY(ETK_D4, "ac5", NULL),
1142 _OMAP3_BALLENTRY(ETK_D5, "ad2", NULL),
1143 _OMAP3_BALLENTRY(ETK_D6, "ac8", NULL),
1144 _OMAP3_BALLENTRY(ETK_D7, "ad9", NULL),
1145 _OMAP3_BALLENTRY(ETK_D8, "ac4", NULL),
1146 _OMAP3_BALLENTRY(ETK_D9, "ad5", NULL),
1147 _OMAP3_BALLENTRY(GPMC_A1, "k4", NULL),
1148 _OMAP3_BALLENTRY(GPMC_A10, "g2", NULL),
1149 _OMAP3_BALLENTRY(GPMC_A2, "k3", NULL),
1150 _OMAP3_BALLENTRY(GPMC_A3, "k2", NULL),
1151 _OMAP3_BALLENTRY(GPMC_A4, "j4", NULL),
1152 _OMAP3_BALLENTRY(GPMC_A5, "j3", NULL),
1153 _OMAP3_BALLENTRY(GPMC_A6, "j2", NULL),
1154 _OMAP3_BALLENTRY(GPMC_A7, "j1", NULL),
1155 _OMAP3_BALLENTRY(GPMC_A8, "h1", NULL),
1156 _OMAP3_BALLENTRY(GPMC_A9, "h2", NULL),
1157 _OMAP3_BALLENTRY(GPMC_CLK, "w2", NULL),
1158 _OMAP3_BALLENTRY(GPMC_D10, "u1", NULL),
1159 _OMAP3_BALLENTRY(GPMC_D11, "r3", NULL),
1160 _OMAP3_BALLENTRY(GPMC_D12, "t3", NULL),
1161 _OMAP3_BALLENTRY(GPMC_D13, "u2", NULL),
1162 _OMAP3_BALLENTRY(GPMC_D14, "v1", NULL),
1163 _OMAP3_BALLENTRY(GPMC_D15, "v2", NULL),
1164 _OMAP3_BALLENTRY(GPMC_D8, "r2", NULL),
1165 _OMAP3_BALLENTRY(GPMC_D9, "t2", NULL),
1166 _OMAP3_BALLENTRY(GPMC_NBE0_CLE, "k5", NULL),
1167 _OMAP3_BALLENTRY(GPMC_NBE1, "l1", NULL),
1168 _OMAP3_BALLENTRY(GPMC_NCS3, "d2", NULL),
1169 _OMAP3_BALLENTRY(GPMC_NCS4, "f4", NULL),
1170 _OMAP3_BALLENTRY(GPMC_NCS5, "g5", NULL),
1171 _OMAP3_BALLENTRY(GPMC_NCS6, "f3", NULL),
1172 _OMAP3_BALLENTRY(GPMC_NCS7, "g4", NULL),
1173 _OMAP3_BALLENTRY(GPMC_NWP, "e1", NULL),
1174 _OMAP3_BALLENTRY(GPMC_WAIT3, "c2", NULL),
1175 _OMAP3_BALLENTRY(HDQ_SIO, "a24", NULL),
1176 _OMAP3_BALLENTRY(HSUSB0_CLK, "r21", NULL),
1177 _OMAP3_BALLENTRY(HSUSB0_DATA0, "t24", NULL),
1178 _OMAP3_BALLENTRY(HSUSB0_DATA1, "t23", NULL),
1179 _OMAP3_BALLENTRY(HSUSB0_DATA2, "u24", NULL),
1180 _OMAP3_BALLENTRY(HSUSB0_DATA3, "u23", NULL),
1181 _OMAP3_BALLENTRY(HSUSB0_DATA4, "w24", NULL),
1182 _OMAP3_BALLENTRY(HSUSB0_DATA5, "v23", NULL),
1183 _OMAP3_BALLENTRY(HSUSB0_DATA6, "w23", NULL),
1184 _OMAP3_BALLENTRY(HSUSB0_DATA7, "t22", NULL),
1185 _OMAP3_BALLENTRY(HSUSB0_DIR, "p23", NULL),
1186 _OMAP3_BALLENTRY(HSUSB0_NXT, "r22", NULL),
1187 _OMAP3_BALLENTRY(HSUSB0_STP, "r23", NULL),
1188 _OMAP3_BALLENTRY(I2C2_SCL, "ac15", NULL),
1189 _OMAP3_BALLENTRY(I2C2_SDA, "ac14", NULL),
1190 _OMAP3_BALLENTRY(I2C3_SCL, "ac13", NULL),
1191 _OMAP3_BALLENTRY(I2C3_SDA, "ac12", NULL),
1192 _OMAP3_BALLENTRY(I2C4_SCL, "y16", NULL),
1193 _OMAP3_BALLENTRY(I2C4_SDA, "y15", NULL),
1194 _OMAP3_BALLENTRY(JTAG_EMU0, "ac24", NULL),
1195 _OMAP3_BALLENTRY(JTAG_EMU1, "ad24", NULL),
1196 _OMAP3_BALLENTRY(MCBSP1_CLKR, "w19", NULL),
1197 _OMAP3_BALLENTRY(MCBSP1_CLKX, "v18", NULL),
1198 _OMAP3_BALLENTRY(MCBSP1_DR, "y18", NULL),
1199 _OMAP3_BALLENTRY(MCBSP1_DX, "w18", NULL),
1200 _OMAP3_BALLENTRY(MCBSP1_FSR, "ab20", NULL),
1201 _OMAP3_BALLENTRY(MCBSP1_FSX, "aa19", NULL),
1202 _OMAP3_BALLENTRY(MCBSP2_CLKX, "t21", NULL),
1203 _OMAP3_BALLENTRY(MCBSP2_DR, "v19", NULL),
1204 _OMAP3_BALLENTRY(MCBSP2_DX, "r20", NULL),
1205 _OMAP3_BALLENTRY(MCBSP2_FSX, "v20", NULL),
1206 _OMAP3_BALLENTRY(MCBSP3_CLKX, "w4", NULL),
1207 _OMAP3_BALLENTRY(MCBSP3_DR, "v5", NULL),
1208 _OMAP3_BALLENTRY(MCBSP3_DX, "v6", NULL),
1209 _OMAP3_BALLENTRY(MCBSP3_FSX, "v4", NULL),
1210 _OMAP3_BALLENTRY(MCBSP_CLKS, "aa18", NULL),
1211 _OMAP3_BALLENTRY(MCSPI1_CLK, "t5", NULL),
1212 _OMAP3_BALLENTRY(MCSPI1_CS0, "t6", NULL),
1213 _OMAP3_BALLENTRY(MCSPI1_CS3, "r5", NULL),
1214 _OMAP3_BALLENTRY(MCSPI1_SIMO, "r4", NULL),
1215 _OMAP3_BALLENTRY(MCSPI1_SOMI, "t4", NULL),
1216 _OMAP3_BALLENTRY(MCSPI2_CLK, "n5", NULL),
1217 _OMAP3_BALLENTRY(MCSPI2_CS0, "m5", NULL),
1218 _OMAP3_BALLENTRY(MCSPI2_CS1, "m4", NULL),
1219 _OMAP3_BALLENTRY(MCSPI2_SIMO, "n4", NULL),
1220 _OMAP3_BALLENTRY(MCSPI2_SOMI, "n3", NULL),
1221 _OMAP3_BALLENTRY(SDMMC1_CLK, "m23", NULL),
1222 _OMAP3_BALLENTRY(SDMMC1_CMD, "l23", NULL),
1223 _OMAP3_BALLENTRY(SDMMC1_DAT0, "m22", NULL),
1224 _OMAP3_BALLENTRY(SDMMC1_DAT1, "m21", NULL),
1225 _OMAP3_BALLENTRY(SDMMC1_DAT2, "m20", NULL),
1226 _OMAP3_BALLENTRY(SDMMC1_DAT3, "n23", NULL),
1227 _OMAP3_BALLENTRY(SDMMC1_DAT4, "n22", NULL),
1228 _OMAP3_BALLENTRY(SDMMC1_DAT5, "n21", NULL),
1229 _OMAP3_BALLENTRY(SDMMC1_DAT6, "n20", NULL),
1230 _OMAP3_BALLENTRY(SDMMC1_DAT7, "p24", NULL),
1231 _OMAP3_BALLENTRY(SDMMC2_CLK, "y1", NULL),
1232 _OMAP3_BALLENTRY(SDMMC2_CMD, "ab5", NULL),
1233 _OMAP3_BALLENTRY(SDMMC2_DAT0, "ab3", NULL),
1234 _OMAP3_BALLENTRY(SDMMC2_DAT1, "y3", NULL),
1235 _OMAP3_BALLENTRY(SDMMC2_DAT2, "w3", NULL),
1236 _OMAP3_BALLENTRY(SDMMC2_DAT3, "v3", NULL),
1237 _OMAP3_BALLENTRY(SDMMC2_DAT4, "ab2", NULL),
1238 _OMAP3_BALLENTRY(SDMMC2_DAT5, "aa2", NULL),
1239 _OMAP3_BALLENTRY(SDMMC2_DAT6, "y2", NULL),
1240 _OMAP3_BALLENTRY(SDMMC2_DAT7, "aa1", NULL),
1241 _OMAP3_BALLENTRY(SYS_BOOT0, "ab12", NULL),
1242 _OMAP3_BALLENTRY(SYS_BOOT1, "ac16", NULL),
1243 _OMAP3_BALLENTRY(SYS_BOOT2, "ad17", NULL),
1244 _OMAP3_BALLENTRY(SYS_BOOT3, "ad18", NULL),
1245 _OMAP3_BALLENTRY(SYS_BOOT4, "ac17", NULL),
1246 _OMAP3_BALLENTRY(SYS_BOOT5, "ab16", NULL),
1247 _OMAP3_BALLENTRY(SYS_BOOT6, "aa15", NULL),
1248 _OMAP3_BALLENTRY(SYS_CLKOUT1, "y7", NULL),
1249 _OMAP3_BALLENTRY(SYS_CLKOUT2, "aa6", NULL),
1250 _OMAP3_BALLENTRY(SYS_CLKREQ, "y13", NULL),
1251 _OMAP3_BALLENTRY(SYS_NIRQ, "w16", NULL),
1252 _OMAP3_BALLENTRY(SYS_NRESWARM, "y10", NULL),
1253 _OMAP3_BALLENTRY(SYS_OFF_MODE, "ad23", NULL),
1254 _OMAP3_BALLENTRY(UART1_CTS, "ac2", NULL),
1255 _OMAP3_BALLENTRY(UART1_RTS, "w6", NULL),
1256 _OMAP3_BALLENTRY(UART1_RX, "v7", NULL),
1257 _OMAP3_BALLENTRY(UART1_TX, "w7", NULL),
1258 _OMAP3_BALLENTRY(UART3_CTS_RCTX, "a23", NULL),
1259 _OMAP3_BALLENTRY(UART3_RTS_SD, "b23", NULL),
1260 _OMAP3_BALLENTRY(UART3_RX_IRRX, "b24", NULL),
1261 _OMAP3_BALLENTRY(UART3_TX_IRTX, "c23", NULL),
1262 { .reg_offset = OMAP_MUX_TERMINATOR },
1263};
1264#else
1265#define omap3_cus_ball NULL
1266#endif
1267
1268/*
1269 * Signals different on CBB package compared to superset
1270 */
1271#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_OMAP_PACKAGE_CBB)
1272static struct omap_mux __initdata omap3_cbb_subset[] = {
1273 _OMAP3_MUXENTRY(CAM_D10, 109,
1274 "cam_d10", NULL, NULL, NULL,
1275 "gpio_109", NULL, NULL, "safe_mode"),
1276 _OMAP3_MUXENTRY(CAM_D11, 110,
1277 "cam_d11", NULL, NULL, NULL,
1278 "gpio_110", NULL, NULL, "safe_mode"),
1279 _OMAP3_MUXENTRY(CAM_D2, 101,
1280 "cam_d2", NULL, NULL, NULL,
1281 "gpio_101", NULL, NULL, "safe_mode"),
1282 _OMAP3_MUXENTRY(CAM_D3, 102,
1283 "cam_d3", NULL, NULL, NULL,
1284 "gpio_102", NULL, NULL, "safe_mode"),
1285 _OMAP3_MUXENTRY(CAM_D4, 103,
1286 "cam_d4", NULL, NULL, NULL,
1287 "gpio_103", NULL, NULL, "safe_mode"),
1288 _OMAP3_MUXENTRY(CAM_D5, 104,
1289 "cam_d5", NULL, NULL, NULL,
1290 "gpio_104", NULL, NULL, "safe_mode"),
1291 _OMAP3_MUXENTRY(CAM_FLD, 98,
1292 "cam_fld", NULL, "cam_global_reset", NULL,
1293 "gpio_98", NULL, NULL, "safe_mode"),
1294 _OMAP3_MUXENTRY(CAM_HS, 94,
1295 "cam_hs", NULL, NULL, NULL,
1296 "gpio_94", NULL, NULL, "safe_mode"),
1297 _OMAP3_MUXENTRY(CAM_PCLK, 97,
1298 "cam_pclk", NULL, NULL, NULL,
1299 "gpio_97", NULL, NULL, "safe_mode"),
1300 _OMAP3_MUXENTRY(CAM_STROBE, 126,
1301 "cam_strobe", NULL, NULL, NULL,
1302 "gpio_126", NULL, NULL, "safe_mode"),
1303 _OMAP3_MUXENTRY(CAM_VS, 95,
1304 "cam_vs", NULL, NULL, NULL,
1305 "gpio_95", NULL, NULL, "safe_mode"),
1306 _OMAP3_MUXENTRY(CAM_WEN, 167,
1307 "cam_wen", NULL, "cam_shutter", NULL,
1308 "gpio_167", NULL, NULL, "safe_mode"),
1309 _OMAP3_MUXENTRY(DSS_DATA6, 76,
1310 "dss_data6", NULL, "uart1_tx", NULL,
1311 "gpio_76", NULL, NULL, "safe_mode"),
1312 _OMAP3_MUXENTRY(DSS_DATA7, 77,
1313 "dss_data7", NULL, "uart1_rx", NULL,
1314 "gpio_77", NULL, NULL, "safe_mode"),
1315 _OMAP3_MUXENTRY(DSS_DATA8, 78,
1316 "dss_data8", NULL, NULL, NULL,
1317 "gpio_78", NULL, NULL, "safe_mode"),
1318 _OMAP3_MUXENTRY(DSS_DATA9, 79,
1319 "dss_data9", NULL, NULL, NULL,
1320 "gpio_79", NULL, NULL, "safe_mode"),
1321 _OMAP3_MUXENTRY(DSS_HSYNC, 67,
1322 "dss_hsync", NULL, NULL, NULL,
1323 "gpio_67", NULL, NULL, "safe_mode"),
1324 _OMAP3_MUXENTRY(DSS_PCLK, 66,
1325 "dss_pclk", NULL, NULL, NULL,
1326 "gpio_66", NULL, NULL, "safe_mode"),
1327 _OMAP3_MUXENTRY(ETK_CLK, 12,
1328 "etk_clk", "mcbsp5_clkx", "sdmmc3_clk", "hsusb1_stp",
1329 "gpio_12", "mm1_rxdp", "hsusb1_tll_stp", NULL),
1330 _OMAP3_MUXENTRY(ETK_CTL, 13,
1331 "etk_ctl", NULL, "sdmmc3_cmd", "hsusb1_clk",
1332 "gpio_13", NULL, "hsusb1_tll_clk", NULL),
1333 _OMAP3_MUXENTRY(ETK_D0, 14,
1334 "etk_d0", "mcspi3_simo", "sdmmc3_dat4", "hsusb1_data0",
1335 "gpio_14", "mm1_rxrcv", "hsusb1_tll_data0", NULL),
1336 _OMAP3_MUXENTRY(ETK_D1, 15,
1337 "etk_d1", "mcspi3_somi", NULL, "hsusb1_data1",
1338 "gpio_15", "mm1_txse0", "hsusb1_tll_data1", NULL),
1339 _OMAP3_MUXENTRY(ETK_D10, 24,
1340 "etk_d10", NULL, "uart1_rx", "hsusb2_clk",
1341 "gpio_24", NULL, "hsusb2_tll_clk", NULL),
1342 _OMAP3_MUXENTRY(ETK_D11, 25,
1343 "etk_d11", NULL, NULL, "hsusb2_stp",
1344 "gpio_25", "mm2_rxdp", "hsusb2_tll_stp", NULL),
1345 _OMAP3_MUXENTRY(ETK_D12, 26,
1346 "etk_d12", NULL, NULL, "hsusb2_dir",
1347 "gpio_26", NULL, "hsusb2_tll_dir", NULL),
1348 _OMAP3_MUXENTRY(ETK_D13, 27,
1349 "etk_d13", NULL, NULL, "hsusb2_nxt",
1350 "gpio_27", "mm2_rxdm", "hsusb2_tll_nxt", NULL),
1351 _OMAP3_MUXENTRY(ETK_D14, 28,
1352 "etk_d14", NULL, NULL, "hsusb2_data0",
1353 "gpio_28", "mm2_rxrcv", "hsusb2_tll_data0", NULL),
1354 _OMAP3_MUXENTRY(ETK_D15, 29,
1355 "etk_d15", NULL, NULL, "hsusb2_data1",
1356 "gpio_29", "mm2_txse0", "hsusb2_tll_data1", NULL),
1357 _OMAP3_MUXENTRY(ETK_D2, 16,
1358 "etk_d2", "mcspi3_cs0", NULL, "hsusb1_data2",
1359 "gpio_16", "mm1_txdat", "hsusb1_tll_data2", NULL),
1360 _OMAP3_MUXENTRY(ETK_D3, 17,
1361 "etk_d3", "mcspi3_clk", "sdmmc3_dat3", "hsusb1_data7",
1362 "gpio_17", NULL, "hsusb1_tll_data7", NULL),
1363 _OMAP3_MUXENTRY(ETK_D4, 18,
1364 "etk_d4", "mcbsp5_dr", "sdmmc3_dat0", "hsusb1_data4",
1365 "gpio_18", NULL, "hsusb1_tll_data4", NULL),
1366 _OMAP3_MUXENTRY(ETK_D5, 19,
1367 "etk_d5", "mcbsp5_fsx", "sdmmc3_dat1", "hsusb1_data5",
1368 "gpio_19", NULL, "hsusb1_tll_data5", NULL),
1369 _OMAP3_MUXENTRY(ETK_D6, 20,
1370 "etk_d6", "mcbsp5_dx", "sdmmc3_dat2", "hsusb1_data6",
1371 "gpio_20", NULL, "hsusb1_tll_data6", NULL),
1372 _OMAP3_MUXENTRY(ETK_D7, 21,
1373 "etk_d7", "mcspi3_cs1", "sdmmc3_dat7", "hsusb1_data3",
1374 "gpio_21", "mm1_txen_n", "hsusb1_tll_data3", NULL),
1375 _OMAP3_MUXENTRY(ETK_D8, 22,
1376 "etk_d8", "sys_drm_msecure", "sdmmc3_dat6", "hsusb1_dir",
1377 "gpio_22", NULL, "hsusb1_tll_dir", NULL),
1378 _OMAP3_MUXENTRY(ETK_D9, 23,
1379 "etk_d9", "sys_secure_indicator", "sdmmc3_dat5", "hsusb1_nxt",
1380 "gpio_23", "mm1_rxdm", "hsusb1_tll_nxt", NULL),
1381 { .reg_offset = OMAP_MUX_TERMINATOR },
1382};
1383#else
1384#define omap3_cbb_subset NULL
1385#endif
1386
1387/*
1388 * Balls for CBB package
1389 * 515-pin s-PBGA Package, 0.50mm Ball Pitch (Top), 0.40mm Ball Pitch (Bottom)
1390 */
1391#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \
1392 && defined(CONFIG_OMAP_PACKAGE_CBB)
1393static struct omap_ball __initdata omap3_cbb_ball[] = {
1394 _OMAP3_BALLENTRY(CAM_D0, "ag17", NULL),
1395 _OMAP3_BALLENTRY(CAM_D1, "ah17", NULL),
1396 _OMAP3_BALLENTRY(CAM_D10, "b25", NULL),
1397 _OMAP3_BALLENTRY(CAM_D11, "c26", NULL),
1398 _OMAP3_BALLENTRY(CAM_D2, "b24", NULL),
1399 _OMAP3_BALLENTRY(CAM_D3, "c24", NULL),
1400 _OMAP3_BALLENTRY(CAM_D4, "d24", NULL),
1401 _OMAP3_BALLENTRY(CAM_D5, "a25", NULL),
1402 _OMAP3_BALLENTRY(CAM_D6, "k28", NULL),
1403 _OMAP3_BALLENTRY(CAM_D7, "l28", NULL),
1404 _OMAP3_BALLENTRY(CAM_D8, "k27", NULL),
1405 _OMAP3_BALLENTRY(CAM_D9, "l27", NULL),
1406 _OMAP3_BALLENTRY(CAM_FLD, "c23", NULL),
1407 _OMAP3_BALLENTRY(CAM_HS, "a24", NULL),
1408 _OMAP3_BALLENTRY(CAM_PCLK, "c27", NULL),
1409 _OMAP3_BALLENTRY(CAM_STROBE, "d25", NULL),
1410 _OMAP3_BALLENTRY(CAM_VS, "a23", NULL),
1411 _OMAP3_BALLENTRY(CAM_WEN, "b23", NULL),
1412 _OMAP3_BALLENTRY(CAM_XCLKA, "c25", NULL),
1413 _OMAP3_BALLENTRY(CAM_XCLKB, "b26", NULL),
1414 _OMAP3_BALLENTRY(CSI2_DX0, "ag19", NULL),
1415 _OMAP3_BALLENTRY(CSI2_DX1, "ag18", NULL),
1416 _OMAP3_BALLENTRY(CSI2_DY0, "ah19", NULL),
1417 _OMAP3_BALLENTRY(CSI2_DY1, "ah18", NULL),
1418 _OMAP3_BALLENTRY(DSS_ACBIAS, "e27", NULL),
1419 _OMAP3_BALLENTRY(DSS_DATA0, "ag22", NULL),
1420 _OMAP3_BALLENTRY(DSS_DATA1, "ah22", NULL),
1421 _OMAP3_BALLENTRY(DSS_DATA10, "ad28", NULL),
1422 _OMAP3_BALLENTRY(DSS_DATA11, "ad27", NULL),
1423 _OMAP3_BALLENTRY(DSS_DATA12, "ab28", NULL),
1424 _OMAP3_BALLENTRY(DSS_DATA13, "ab27", NULL),
1425 _OMAP3_BALLENTRY(DSS_DATA14, "aa28", NULL),
1426 _OMAP3_BALLENTRY(DSS_DATA15, "aa27", NULL),
1427 _OMAP3_BALLENTRY(DSS_DATA16, "g25", NULL),
1428 _OMAP3_BALLENTRY(DSS_DATA17, "h27", NULL),
1429 _OMAP3_BALLENTRY(DSS_DATA18, "h26", NULL),
1430 _OMAP3_BALLENTRY(DSS_DATA19, "h25", NULL),
1431 _OMAP3_BALLENTRY(DSS_DATA2, "ag23", NULL),
1432 _OMAP3_BALLENTRY(DSS_DATA20, "e28", NULL),
1433 _OMAP3_BALLENTRY(DSS_DATA21, "j26", NULL),
1434 _OMAP3_BALLENTRY(DSS_DATA22, "ac27", NULL),
1435 _OMAP3_BALLENTRY(DSS_DATA23, "ac28", NULL),
1436 _OMAP3_BALLENTRY(DSS_DATA3, "ah23", NULL),
1437 _OMAP3_BALLENTRY(DSS_DATA4, "ag24", NULL),
1438 _OMAP3_BALLENTRY(DSS_DATA5, "ah24", NULL),
1439 _OMAP3_BALLENTRY(DSS_DATA6, "e26", NULL),
1440 _OMAP3_BALLENTRY(DSS_DATA7, "f28", NULL),
1441 _OMAP3_BALLENTRY(DSS_DATA8, "f27", NULL),
1442 _OMAP3_BALLENTRY(DSS_DATA9, "g26", NULL),
1443 _OMAP3_BALLENTRY(DSS_HSYNC, "d26", NULL),
1444 _OMAP3_BALLENTRY(DSS_PCLK, "d28", NULL),
1445 _OMAP3_BALLENTRY(DSS_VSYNC, "d27", NULL),
1446 _OMAP3_BALLENTRY(ETK_CLK, "af10", NULL),
1447 _OMAP3_BALLENTRY(ETK_CTL, "ae10", NULL),
1448 _OMAP3_BALLENTRY(ETK_D0, "af11", NULL),
1449 _OMAP3_BALLENTRY(ETK_D1, "ag12", NULL),
1450 _OMAP3_BALLENTRY(ETK_D10, "ae7", NULL),
1451 _OMAP3_BALLENTRY(ETK_D11, "af7", NULL),
1452 _OMAP3_BALLENTRY(ETK_D12, "ag7", NULL),
1453 _OMAP3_BALLENTRY(ETK_D13, "ah7", NULL),
1454 _OMAP3_BALLENTRY(ETK_D14, "ag8", NULL),
1455 _OMAP3_BALLENTRY(ETK_D15, "ah8", NULL),
1456 _OMAP3_BALLENTRY(ETK_D2, "ah12", NULL),
1457 _OMAP3_BALLENTRY(ETK_D3, "ae13", NULL),
1458 _OMAP3_BALLENTRY(ETK_D4, "ae11", NULL),
1459 _OMAP3_BALLENTRY(ETK_D5, "ah9", NULL),
1460 _OMAP3_BALLENTRY(ETK_D6, "af13", NULL),
1461 _OMAP3_BALLENTRY(ETK_D7, "ah14", NULL),
1462 _OMAP3_BALLENTRY(ETK_D8, "af9", NULL),
1463 _OMAP3_BALLENTRY(ETK_D9, "ag9", NULL),
1464 _OMAP3_BALLENTRY(GPMC_A1, "n4", "ac15"),
1465 _OMAP3_BALLENTRY(GPMC_A10, "k3", "ab19"),
1466 _OMAP3_BALLENTRY(GPMC_A2, "m4", "ab15"),
1467 _OMAP3_BALLENTRY(GPMC_A3, "l4", "ac16"),
1468 _OMAP3_BALLENTRY(GPMC_A4, "k4", "ab16"),
1469 _OMAP3_BALLENTRY(GPMC_A5, "t3", "ac17"),
1470 _OMAP3_BALLENTRY(GPMC_A6, "r3", "ab17"),
1471 _OMAP3_BALLENTRY(GPMC_A7, "n3", "ac18"),
1472 _OMAP3_BALLENTRY(GPMC_A8, "m3", "ab18"),
1473 _OMAP3_BALLENTRY(GPMC_A9, "l3", "ac19"),
1474 _OMAP3_BALLENTRY(GPMC_CLK, "t4", "w2"),
1475 _OMAP3_BALLENTRY(GPMC_D10, "p1", "ab4"),
1476 _OMAP3_BALLENTRY(GPMC_D11, "r1", "ac4"),
1477 _OMAP3_BALLENTRY(GPMC_D12, "r2", "ab6"),
1478 _OMAP3_BALLENTRY(GPMC_D13, "t2", "ac6"),
1479 _OMAP3_BALLENTRY(GPMC_D14, "w1", "ab7"),
1480 _OMAP3_BALLENTRY(GPMC_D15, "y1", "ac7"),
1481 _OMAP3_BALLENTRY(GPMC_D8, "h2", "ab3"),
1482 _OMAP3_BALLENTRY(GPMC_D9, "k2", "ac3"),
1483 _OMAP3_BALLENTRY(GPMC_NBE0_CLE, "g3", "ac12"),
1484 _OMAP3_BALLENTRY(GPMC_NBE1, "u3", NULL),
1485 _OMAP3_BALLENTRY(GPMC_NCS1, "h3", "y1"),
1486 _OMAP3_BALLENTRY(GPMC_NCS2, "v8", NULL),
1487 _OMAP3_BALLENTRY(GPMC_NCS3, "u8", NULL),
1488 _OMAP3_BALLENTRY(GPMC_NCS4, "t8", NULL),
1489 _OMAP3_BALLENTRY(GPMC_NCS5, "r8", NULL),
1490 _OMAP3_BALLENTRY(GPMC_NCS6, "p8", NULL),
1491 _OMAP3_BALLENTRY(GPMC_NCS7, "n8", NULL),
1492 _OMAP3_BALLENTRY(GPMC_NWP, "h1", "ab10"),
1493 _OMAP3_BALLENTRY(GPMC_WAIT1, "l8", "ac10"),
1494 _OMAP3_BALLENTRY(GPMC_WAIT2, "k8", NULL),
1495 _OMAP3_BALLENTRY(GPMC_WAIT3, "j8", NULL),
1496 _OMAP3_BALLENTRY(HDQ_SIO, "j25", NULL),
1497 _OMAP3_BALLENTRY(HSUSB0_CLK, "t28", NULL),
1498 _OMAP3_BALLENTRY(HSUSB0_DATA0, "t27", NULL),
1499 _OMAP3_BALLENTRY(HSUSB0_DATA1, "u28", NULL),
1500 _OMAP3_BALLENTRY(HSUSB0_DATA2, "u27", NULL),
1501 _OMAP3_BALLENTRY(HSUSB0_DATA3, "u26", NULL),
1502 _OMAP3_BALLENTRY(HSUSB0_DATA4, "u25", NULL),
1503 _OMAP3_BALLENTRY(HSUSB0_DATA5, "v28", NULL),
1504 _OMAP3_BALLENTRY(HSUSB0_DATA6, "v27", NULL),
1505 _OMAP3_BALLENTRY(HSUSB0_DATA7, "v26", NULL),
1506 _OMAP3_BALLENTRY(HSUSB0_DIR, "r28", NULL),
1507 _OMAP3_BALLENTRY(HSUSB0_NXT, "t26", NULL),
1508 _OMAP3_BALLENTRY(HSUSB0_STP, "t25", NULL),
1509 _OMAP3_BALLENTRY(I2C2_SCL, "af15", NULL),
1510 _OMAP3_BALLENTRY(I2C2_SDA, "ae15", NULL),
1511 _OMAP3_BALLENTRY(I2C3_SCL, "af14", NULL),
1512 _OMAP3_BALLENTRY(I2C3_SDA, "ag14", NULL),
1513 _OMAP3_BALLENTRY(I2C4_SCL, "ad26", NULL),
1514 _OMAP3_BALLENTRY(I2C4_SDA, "ae26", NULL),
1515 _OMAP3_BALLENTRY(JTAG_EMU0, "aa11", NULL),
1516 _OMAP3_BALLENTRY(JTAG_EMU1, "aa10", NULL),
1517 _OMAP3_BALLENTRY(MCBSP1_CLKR, "y21", NULL),
1518 _OMAP3_BALLENTRY(MCBSP1_CLKX, "w21", NULL),
1519 _OMAP3_BALLENTRY(MCBSP1_DR, "u21", NULL),
1520 _OMAP3_BALLENTRY(MCBSP1_DX, "v21", NULL),
1521 _OMAP3_BALLENTRY(MCBSP1_FSR, "aa21", NULL),
1522 _OMAP3_BALLENTRY(MCBSP1_FSX, "k26", NULL),
1523 _OMAP3_BALLENTRY(MCBSP2_CLKX, "n21", NULL),
1524 _OMAP3_BALLENTRY(MCBSP2_DR, "r21", NULL),
1525 _OMAP3_BALLENTRY(MCBSP2_DX, "m21", NULL),
1526 _OMAP3_BALLENTRY(MCBSP2_FSX, "p21", NULL),
1527 _OMAP3_BALLENTRY(MCBSP3_CLKX, "af5", NULL),
1528 _OMAP3_BALLENTRY(MCBSP3_DR, "ae6", NULL),
1529 _OMAP3_BALLENTRY(MCBSP3_DX, "af6", NULL),
1530 _OMAP3_BALLENTRY(MCBSP3_FSX, "ae5", NULL),
1531 _OMAP3_BALLENTRY(MCBSP4_CLKX, "ae1", NULL),
1532 _OMAP3_BALLENTRY(MCBSP4_DR, "ad1", NULL),
1533 _OMAP3_BALLENTRY(MCBSP4_DX, "ad2", NULL),
1534 _OMAP3_BALLENTRY(MCBSP4_FSX, "ac1", NULL),
1535 _OMAP3_BALLENTRY(MCBSP_CLKS, "t21", NULL),
1536 _OMAP3_BALLENTRY(MCSPI1_CLK, "ab3", NULL),
1537 _OMAP3_BALLENTRY(MCSPI1_CS0, "ac2", NULL),
1538 _OMAP3_BALLENTRY(MCSPI1_CS1, "ac3", NULL),
1539 _OMAP3_BALLENTRY(MCSPI1_CS2, "ab1", NULL),
1540 _OMAP3_BALLENTRY(MCSPI1_CS3, "ab2", NULL),
1541 _OMAP3_BALLENTRY(MCSPI1_SIMO, "ab4", NULL),
1542 _OMAP3_BALLENTRY(MCSPI1_SOMI, "aa4", NULL),
1543 _OMAP3_BALLENTRY(MCSPI2_CLK, "aa3", NULL),
1544 _OMAP3_BALLENTRY(MCSPI2_CS0, "y4", NULL),
1545 _OMAP3_BALLENTRY(MCSPI2_CS1, "v3", NULL),
1546 _OMAP3_BALLENTRY(MCSPI2_SIMO, "y2", NULL),
1547 _OMAP3_BALLENTRY(MCSPI2_SOMI, "y3", NULL),
1548 _OMAP3_BALLENTRY(SDMMC1_CLK, "n28", NULL),
1549 _OMAP3_BALLENTRY(SDMMC1_CMD, "m27", NULL),
1550 _OMAP3_BALLENTRY(SDMMC1_DAT0, "n27", NULL),
1551 _OMAP3_BALLENTRY(SDMMC1_DAT1, "n26", NULL),
1552 _OMAP3_BALLENTRY(SDMMC1_DAT2, "n25", NULL),
1553 _OMAP3_BALLENTRY(SDMMC1_DAT3, "p28", NULL),
1554 _OMAP3_BALLENTRY(SDMMC1_DAT4, "p27", NULL),
1555 _OMAP3_BALLENTRY(SDMMC1_DAT5, "p26", NULL),
1556 _OMAP3_BALLENTRY(SDMMC1_DAT6, "r27", NULL),
1557 _OMAP3_BALLENTRY(SDMMC1_DAT7, "r25", NULL),
1558 _OMAP3_BALLENTRY(SDMMC2_CLK, "ae2", NULL),
1559 _OMAP3_BALLENTRY(SDMMC2_CMD, "ag5", NULL),
1560 _OMAP3_BALLENTRY(SDMMC2_DAT0, "ah5", NULL),
1561 _OMAP3_BALLENTRY(SDMMC2_DAT1, "ah4", NULL),
1562 _OMAP3_BALLENTRY(SDMMC2_DAT2, "ag4", NULL),
1563 _OMAP3_BALLENTRY(SDMMC2_DAT3, "af4", NULL),
1564 _OMAP3_BALLENTRY(SDMMC2_DAT4, "ae4", NULL),
1565 _OMAP3_BALLENTRY(SDMMC2_DAT5, "ah3", NULL),
1566 _OMAP3_BALLENTRY(SDMMC2_DAT6, "af3", NULL),
1567 _OMAP3_BALLENTRY(SDMMC2_DAT7, "ae3", NULL),
1568 _OMAP3_BALLENTRY(SYS_BOOT0, "ah26", NULL),
1569 _OMAP3_BALLENTRY(SYS_BOOT1, "ag26", NULL),
1570 _OMAP3_BALLENTRY(SYS_BOOT2, "ae14", NULL),
1571 _OMAP3_BALLENTRY(SYS_BOOT3, "af18", NULL),
1572 _OMAP3_BALLENTRY(SYS_BOOT4, "af19", NULL),
1573 _OMAP3_BALLENTRY(SYS_BOOT5, "ae21", NULL),
1574 _OMAP3_BALLENTRY(SYS_BOOT6, "af21", NULL),
1575 _OMAP3_BALLENTRY(SYS_CLKOUT1, "ag25", NULL),
1576 _OMAP3_BALLENTRY(SYS_CLKOUT2, "ae22", NULL),
1577 _OMAP3_BALLENTRY(SYS_CLKREQ, "af25", NULL),
1578 _OMAP3_BALLENTRY(SYS_NIRQ, "af26", NULL),
1579 _OMAP3_BALLENTRY(SYS_NRESWARM, "af24", NULL),
1580 _OMAP3_BALLENTRY(SYS_OFF_MODE, "af22", NULL),
1581 _OMAP3_BALLENTRY(UART1_CTS, "w8", NULL),
1582 _OMAP3_BALLENTRY(UART1_RTS, "aa9", NULL),
1583 _OMAP3_BALLENTRY(UART1_RX, "y8", NULL),
1584 _OMAP3_BALLENTRY(UART1_TX, "aa8", NULL),
1585 _OMAP3_BALLENTRY(UART2_CTS, "ab26", NULL),
1586 _OMAP3_BALLENTRY(UART2_RTS, "ab25", NULL),
1587 _OMAP3_BALLENTRY(UART2_RX, "ad25", NULL),
1588 _OMAP3_BALLENTRY(UART2_TX, "aa25", NULL),
1589 _OMAP3_BALLENTRY(UART3_CTS_RCTX, "h18", NULL),
1590 _OMAP3_BALLENTRY(UART3_RTS_SD, "h19", NULL),
1591 _OMAP3_BALLENTRY(UART3_RX_IRRX, "h20", NULL),
1592 _OMAP3_BALLENTRY(UART3_TX_IRTX, "h21", NULL),
1593 { .reg_offset = OMAP_MUX_TERMINATOR },
1594};
1595#else
1596#define omap3_cbb_ball NULL
1597#endif
1598
1599/*
1600 * Signals different on 36XX CBP package compared to 34XX CBC package
1601 */
1602#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_OMAP_PACKAGE_CBP)
1603static struct omap_mux __initdata omap36xx_cbp_subset[] = {
1604 _OMAP3_MUXENTRY(CAM_D0, 99,
1605 "cam_d0", NULL, "csi2_dx2", NULL,
1606 "gpio_99", NULL, NULL, "safe_mode"),
1607 _OMAP3_MUXENTRY(CAM_D1, 100,
1608 "cam_d1", NULL, "csi2_dy2", NULL,
1609 "gpio_100", NULL, NULL, "safe_mode"),
1610 _OMAP3_MUXENTRY(CAM_D10, 109,
1611 "cam_d10", "ssi2_wake", NULL, NULL,
1612 "gpio_109", "hw_dbg8", NULL, "safe_mode"),
1613 _OMAP3_MUXENTRY(CAM_D2, 101,
1614 "cam_d2", "ssi2_rdy_tx", NULL, NULL,
1615 "gpio_101", "hw_dbg4", NULL, "safe_mode"),
1616 _OMAP3_MUXENTRY(CAM_D3, 102,
1617 "cam_d3", "ssi2_dat_rx", NULL, NULL,
1618 "gpio_102", "hw_dbg5", NULL, "safe_mode"),
1619 _OMAP3_MUXENTRY(CAM_D4, 103,
1620 "cam_d4", "ssi2_flag_rx", NULL, NULL,
1621 "gpio_103", "hw_dbg6", NULL, "safe_mode"),
1622 _OMAP3_MUXENTRY(CAM_D5, 104,
1623 "cam_d5", "ssi2_rdy_rx", NULL, NULL,
1624 "gpio_104", "hw_dbg7", NULL, "safe_mode"),
1625 _OMAP3_MUXENTRY(CAM_HS, 94,
1626 "cam_hs", "ssi2_dat_tx", NULL, NULL,
1627 "gpio_94", "hw_dbg0", NULL, "safe_mode"),
1628 _OMAP3_MUXENTRY(CAM_VS, 95,
1629 "cam_vs", "ssi2_flag_tx", NULL, NULL,
1630 "gpio_95", "hw_dbg1", NULL, "safe_mode"),
1631 _OMAP3_MUXENTRY(DSS_DATA0, 70,
1632 "dss_data0", "dsi_dx0", "uart1_cts", NULL,
1633 "gpio_70", NULL, NULL, "safe_mode"),
1634 _OMAP3_MUXENTRY(DSS_DATA1, 71,
1635 "dss_data1", "dsi_dy0", "uart1_rts", NULL,
1636 "gpio_71", NULL, NULL, "safe_mode"),
1637 _OMAP3_MUXENTRY(DSS_DATA2, 72,
1638 "dss_data2", "dsi_dx1", NULL, NULL,
1639 "gpio_72", NULL, NULL, "safe_mode"),
1640 _OMAP3_MUXENTRY(DSS_DATA3, 73,
1641 "dss_data3", "dsi_dy1", NULL, NULL,
1642 "gpio_73", NULL, NULL, "safe_mode"),
1643 _OMAP3_MUXENTRY(DSS_DATA4, 74,
1644 "dss_data4", "dsi_dx2", "uart3_rx_irrx", NULL,
1645 "gpio_74", NULL, NULL, "safe_mode"),
1646 _OMAP3_MUXENTRY(DSS_DATA5, 75,
1647 "dss_data5", "dsi_dy2", "uart3_tx_irtx", NULL,
1648 "gpio_75", NULL, NULL, "safe_mode"),
1649 _OMAP3_MUXENTRY(DSS_DATA6, 76,
1650 "dss_data6", NULL, "uart1_tx", "dssvenc656_data6",
1651 "gpio_76", "hw_dbg14", NULL, "safe_mode"),
1652 _OMAP3_MUXENTRY(DSS_DATA7, 77,
1653 "dss_data7", NULL, "uart1_rx", "dssvenc656_data7",
1654 "gpio_77", "hw_dbg15", NULL, "safe_mode"),
1655 _OMAP3_MUXENTRY(DSS_DATA8, 78,
1656 "dss_data8", NULL, "uart3_rx_irrx", NULL,
1657 "gpio_78", "hw_dbg16", NULL, "safe_mode"),
1658 _OMAP3_MUXENTRY(DSS_DATA9, 79,
1659 "dss_data9", NULL, "uart3_tx_irtx", NULL,
1660 "gpio_79", "hw_dbg17", NULL, "safe_mode"),
1661 _OMAP3_MUXENTRY(ETK_D12, 26,
1662 "etk_d12", "sys_drm_msecure", NULL, "hsusb2_dir",
1663 "gpio_26", NULL, "hsusb2_tll_dir", "hw_dbg14"),
1664 _OMAP3_MUXENTRY(GPMC_A11, 0,
1665 "gpmc_a11", NULL, NULL, NULL,
1666 NULL, NULL, NULL, "safe_mode"),
1667 _OMAP3_MUXENTRY(GPMC_WAIT2, 64,
1668 "gpmc_wait2", NULL, "uart4_tx", NULL,
1669 "gpio_64", NULL, NULL, "safe_mode"),
1670 _OMAP3_MUXENTRY(GPMC_WAIT3, 65,
1671 "gpmc_wait3", "sys_ndmareq1", "uart4_rx", NULL,
1672 "gpio_65", NULL, NULL, "safe_mode"),
1673 _OMAP3_MUXENTRY(HSUSB0_DATA0, 125,
1674 "hsusb0_data0", NULL, "uart3_tx_irtx", NULL,
1675 "gpio_125", "uart2_tx", NULL, "safe_mode"),
1676 _OMAP3_MUXENTRY(HSUSB0_DATA1, 130,
1677 "hsusb0_data1", NULL, "uart3_rx_irrx", NULL,
1678 "gpio_130", "uart2_rx", NULL, "safe_mode"),
1679 _OMAP3_MUXENTRY(HSUSB0_DATA2, 131,
1680 "hsusb0_data2", NULL, "uart3_rts_sd", NULL,
1681 "gpio_131", "uart2_rts", NULL, "safe_mode"),
1682 _OMAP3_MUXENTRY(HSUSB0_DATA3, 169,
1683 "hsusb0_data3", NULL, "uart3_cts_rctx", NULL,
1684 "gpio_169", "uart2_cts", NULL, "safe_mode"),
1685 _OMAP3_MUXENTRY(MCBSP1_CLKR, 156,
1686 "mcbsp1_clkr", "mcspi4_clk", "sim_cd", NULL,
1687 "gpio_156", NULL, NULL, "safe_mode"),
1688 _OMAP3_MUXENTRY(MCBSP1_FSR, 157,
1689 "mcbsp1_fsr", "adpllv2d_dithering_en1",
1690 "cam_global_reset", NULL,
1691 "gpio_157", NULL, NULL, "safe_mode"),
1692 _OMAP3_MUXENTRY(MCBSP4_CLKX, 152,
1693 "mcbsp4_clkx", "ssi1_dat_rx", NULL, NULL,
1694 "gpio_152", "hsusb3_tll_data1", "mm3_txse0", "safe_mode"),
1695 _OMAP3_MUXENTRY(MCBSP4_DR, 153,
1696 "mcbsp4_dr", "ssi1_flag_rx", NULL, NULL,
1697 "gpio_153", "hsusb3_tll_data0", "mm3_rxrcv", "safe_mode"),
1698 _OMAP3_MUXENTRY(MCBSP4_DX, 154,
1699 "mcbsp4_dx", "ssi1_rdy_rx", NULL, NULL,
1700 "gpio_154", "hsusb3_tll_data2", "mm3_txdat", "safe_mode"),
1701 _OMAP3_MUXENTRY(MCBSP4_FSX, 155,
1702 "mcbsp4_fsx", "ssi1_wake", NULL, NULL,
1703 "gpio_155", "hsusb3_tll_data3", "mm3_txen_n", "safe_mode"),
1704 _OMAP3_MUXENTRY(MCSPI1_CS1, 175,
1705 "mcspi1_cs1", "adpllv2d_dithering_en2", NULL, "sdmmc3_cmd",
1706 "gpio_175", NULL, NULL, "safe_mode"),
1707 _OMAP3_MUXENTRY(SAD2D_MBUSFLAG, 0,
1708 "sad2d_mbusflag", "mad2d_sbusflag", NULL, NULL,
1709 NULL, NULL, NULL, NULL),
1710 _OMAP3_MUXENTRY(SAD2D_MCAD28, 0,
1711 "sad2d_mcad28", "mad2d_mcad28", NULL, NULL,
1712 NULL, NULL, NULL, NULL),
1713 _OMAP3_MUXENTRY(SAD2D_MCAD29, 0,
1714 "sad2d_mcad29", "mad2d_mcad29", NULL, NULL,
1715 NULL, NULL, NULL, NULL),
1716 _OMAP3_MUXENTRY(SAD2D_MCAD32, 0,
1717 "sad2d_mcad32", "mad2d_mcad32", NULL, NULL,
1718 NULL, NULL, NULL, NULL),
1719 _OMAP3_MUXENTRY(SAD2D_MCAD33, 0,
1720 "sad2d_mcad33", "mad2d_mcad33", NULL, NULL,
1721 NULL, NULL, NULL, NULL),
1722 _OMAP3_MUXENTRY(SAD2D_MCAD34, 0,
1723 "sad2d_mcad34", "mad2d_mcad34", NULL, NULL,
1724 NULL, NULL, NULL, NULL),
1725 _OMAP3_MUXENTRY(SAD2D_MCAD35, 0,
1726 "sad2d_mcad35", "mad2d_mcad35", NULL, NULL,
1727 NULL, NULL, NULL, NULL),
1728 _OMAP3_MUXENTRY(SAD2D_MCAD36, 0,
1729 "sad2d_mcad36", "mad2d_mcad36", NULL, NULL,
1730 NULL, NULL, NULL, NULL),
1731 _OMAP3_MUXENTRY(SAD2D_MREAD, 0,
1732 "sad2d_mread", "mad2d_sread", NULL, NULL,
1733 NULL, NULL, NULL, NULL),
1734 _OMAP3_MUXENTRY(SAD2D_MWRITE, 0,
1735 "sad2d_mwrite", "mad2d_swrite", NULL, NULL,
1736 NULL, NULL, NULL, NULL),
1737 _OMAP3_MUXENTRY(SAD2D_SBUSFLAG, 0,
1738 "sad2d_sbusflag", "mad2d_mbusflag", NULL, NULL,
1739 NULL, NULL, NULL, NULL),
1740 _OMAP3_MUXENTRY(SAD2D_SREAD, 0,
1741 "sad2d_sread", "mad2d_mread", NULL, NULL,
1742 NULL, NULL, NULL, NULL),
1743 _OMAP3_MUXENTRY(SAD2D_SWRITE, 0,
1744 "sad2d_swrite", "mad2d_mwrite", NULL, NULL,
1745 NULL, NULL, NULL, NULL),
1746 _OMAP3_MUXENTRY(SDMMC1_CLK, 120,
1747 "sdmmc1_clk", "ms_clk", NULL, NULL,
1748 "gpio_120", NULL, NULL, "safe_mode"),
1749 _OMAP3_MUXENTRY(SDMMC1_CMD, 121,
1750 "sdmmc1_cmd", "ms_bs", NULL, NULL,
1751 "gpio_121", NULL, NULL, "safe_mode"),
1752 _OMAP3_MUXENTRY(SDMMC1_DAT0, 122,
1753 "sdmmc1_dat0", "ms_dat0", NULL, NULL,
1754 "gpio_122", NULL, NULL, "safe_mode"),
1755 _OMAP3_MUXENTRY(SDMMC1_DAT1, 123,
1756 "sdmmc1_dat1", "ms_dat1", NULL, NULL,
1757 "gpio_123", NULL, NULL, "safe_mode"),
1758 _OMAP3_MUXENTRY(SDMMC1_DAT2, 124,
1759 "sdmmc1_dat2", "ms_dat2", NULL, NULL,
1760 "gpio_124", NULL, NULL, "safe_mode"),
1761 _OMAP3_MUXENTRY(SDMMC1_DAT3, 125,
1762 "sdmmc1_dat3", "ms_dat3", NULL, NULL,
1763 "gpio_125", NULL, NULL, "safe_mode"),
1764 _OMAP3_MUXENTRY(SDRC_CKE0, 0,
1765 "sdrc_cke0", NULL, NULL, NULL,
1766 NULL, NULL, NULL, "safe_mode_out1"),
1767 _OMAP3_MUXENTRY(SDRC_CKE1, 0,
1768 "sdrc_cke1", NULL, NULL, NULL,
1769 NULL, NULL, NULL, "safe_mode_out1"),
1770 _OMAP3_MUXENTRY(SIM_IO, 126,
1771 "sim_io", "sim_io_low_impedance", NULL, NULL,
1772 "gpio_126", NULL, NULL, "safe_mode"),
1773 _OMAP3_MUXENTRY(SIM_CLK, 127,
1774 "sim_clk", NULL, NULL, NULL,
1775 "gpio_127", NULL, NULL, "safe_mode"),
1776 _OMAP3_MUXENTRY(SIM_PWRCTRL, 128,
1777 "sim_pwrctrl", NULL, NULL, NULL,
1778 "gpio_128", NULL, NULL, "safe_mode"),
1779 _OMAP3_MUXENTRY(SIM_RST, 129,
1780 "sim_rst", NULL, NULL, NULL,
1781 "gpio_129", NULL, NULL, "safe_mode"),
1782 _OMAP3_MUXENTRY(SYS_BOOT0, 2,
1783 "sys_boot0", NULL, NULL, "dss_data18",
1784 "gpio_2", NULL, NULL, "safe_mode"),
1785 _OMAP3_MUXENTRY(SYS_BOOT1, 3,
1786 "sys_boot1", NULL, NULL, "dss_data19",
1787 "gpio_3", NULL, NULL, "safe_mode"),
1788 _OMAP3_MUXENTRY(SYS_BOOT3, 5,
1789 "sys_boot3", NULL, NULL, "dss_data20",
1790 "gpio_5", NULL, NULL, "safe_mode"),
1791 _OMAP3_MUXENTRY(SYS_BOOT4, 6,
1792 "sys_boot4", "sdmmc2_dir_dat2", NULL, "dss_data21",
1793 "gpio_6", NULL, NULL, "safe_mode"),
1794 _OMAP3_MUXENTRY(SYS_BOOT5, 7,
1795 "sys_boot5", "sdmmc2_dir_dat3", NULL, "dss_data22",
1796 "gpio_7", NULL, NULL, "safe_mode"),
1797 _OMAP3_MUXENTRY(SYS_BOOT6, 8,
1798 "sys_boot6", NULL, NULL, "dss_data23",
1799 "gpio_8", NULL, NULL, "safe_mode"),
1800 _OMAP3_MUXENTRY(UART1_CTS, 150,
1801 "uart1_cts", "ssi1_rdy_tx", NULL, NULL,
1802 "gpio_150", "hsusb3_tll_clk", NULL, "safe_mode"),
1803 _OMAP3_MUXENTRY(UART1_RTS, 149,
1804 "uart1_rts", "ssi1_flag_tx", NULL, NULL,
1805 "gpio_149", NULL, NULL, "safe_mode"),
1806 _OMAP3_MUXENTRY(UART1_TX, 148,
1807 "uart1_tx", "ssi1_dat_tx", NULL, NULL,
1808 "gpio_148", NULL, NULL, "safe_mode"),
1809 { .reg_offset = OMAP_MUX_TERMINATOR },
1810};
1811#else
1812#define omap36xx_cbp_subset NULL
1813#endif
1814
1815/*
1816 * Balls for 36XX CBP package
1817 * 515-pin s-PBGA Package, 0.50mm Ball Pitch (Top), 0.40mm Ball Pitch (Bottom)
1818 */
1819#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \
1820 && defined (CONFIG_OMAP_PACKAGE_CBP)
1821static struct omap_ball __initdata omap36xx_cbp_ball[] = {
1822 _OMAP3_BALLENTRY(CAM_D0, "ag17", NULL),
1823 _OMAP3_BALLENTRY(CAM_D1, "ah17", NULL),
1824 _OMAP3_BALLENTRY(CAM_D10, "b25", NULL),
1825 _OMAP3_BALLENTRY(CAM_D11, "c26", NULL),
1826 _OMAP3_BALLENTRY(CAM_D2, "b24", NULL),
1827 _OMAP3_BALLENTRY(CAM_D3, "c24", NULL),
1828 _OMAP3_BALLENTRY(CAM_D4, "d24", NULL),
1829 _OMAP3_BALLENTRY(CAM_D5, "a25", NULL),
1830 _OMAP3_BALLENTRY(CAM_D6, "k28", NULL),
1831 _OMAP3_BALLENTRY(CAM_D7, "l28", NULL),
1832 _OMAP3_BALLENTRY(CAM_D8, "k27", NULL),
1833 _OMAP3_BALLENTRY(CAM_D9, "l27", NULL),
1834 _OMAP3_BALLENTRY(CAM_FLD, "c23", NULL),
1835 _OMAP3_BALLENTRY(CAM_HS, "a24", NULL),
1836 _OMAP3_BALLENTRY(CAM_PCLK, "c27", NULL),
1837 _OMAP3_BALLENTRY(CAM_STROBE, "d25", NULL),
1838 _OMAP3_BALLENTRY(CAM_VS, "a23", NULL),
1839 _OMAP3_BALLENTRY(CAM_WEN, "b23", NULL),
1840 _OMAP3_BALLENTRY(CAM_XCLKA, "c25", NULL),
1841 _OMAP3_BALLENTRY(CAM_XCLKB, "b26", NULL),
1842 _OMAP3_BALLENTRY(CSI2_DX0, "ag19", NULL),
1843 _OMAP3_BALLENTRY(CSI2_DX1, "ag18", NULL),
1844 _OMAP3_BALLENTRY(CSI2_DY0, "ah19", NULL),
1845 _OMAP3_BALLENTRY(CSI2_DY1, "ah18", NULL),
1846 _OMAP3_BALLENTRY(DSS_ACBIAS, "e27", NULL),
1847 _OMAP3_BALLENTRY(DSS_DATA0, "ag22", NULL),
1848 _OMAP3_BALLENTRY(DSS_DATA1, "ah22", NULL),
1849 _OMAP3_BALLENTRY(DSS_DATA10, "ad28", NULL),
1850 _OMAP3_BALLENTRY(DSS_DATA11, "ad27", NULL),
1851 _OMAP3_BALLENTRY(DSS_DATA12, "ab28", NULL),
1852 _OMAP3_BALLENTRY(DSS_DATA13, "ab27", NULL),
1853 _OMAP3_BALLENTRY(DSS_DATA14, "aa28", NULL),
1854 _OMAP3_BALLENTRY(DSS_DATA15, "aa27", NULL),
1855 _OMAP3_BALLENTRY(DSS_DATA16, "g25", NULL),
1856 _OMAP3_BALLENTRY(DSS_DATA17, "h27", NULL),
1857 _OMAP3_BALLENTRY(DSS_DATA18, "h26", NULL),
1858 _OMAP3_BALLENTRY(DSS_DATA19, "h25", NULL),
1859 _OMAP3_BALLENTRY(DSS_DATA2, "ag23", NULL),
1860 _OMAP3_BALLENTRY(DSS_DATA20, "e28", NULL),
1861 _OMAP3_BALLENTRY(DSS_DATA21, "j26", NULL),
1862 _OMAP3_BALLENTRY(DSS_DATA22, "ac27", NULL),
1863 _OMAP3_BALLENTRY(DSS_DATA23, "ac28", NULL),
1864 _OMAP3_BALLENTRY(DSS_DATA3, "ah23", NULL),
1865 _OMAP3_BALLENTRY(DSS_DATA4, "ag24", NULL),
1866 _OMAP3_BALLENTRY(DSS_DATA5, "ah24", NULL),
1867 _OMAP3_BALLENTRY(DSS_DATA6, "e26", NULL),
1868 _OMAP3_BALLENTRY(DSS_DATA7, "f28", NULL),
1869 _OMAP3_BALLENTRY(DSS_DATA8, "f27", NULL),
1870 _OMAP3_BALLENTRY(DSS_DATA9, "g26", NULL),
1871 _OMAP3_BALLENTRY(DSS_HSYNC, "d26", NULL),
1872 _OMAP3_BALLENTRY(DSS_PCLK, "d28", NULL),
1873 _OMAP3_BALLENTRY(DSS_VSYNC, "d27", NULL),
1874 _OMAP3_BALLENTRY(ETK_CLK, "af10", NULL),
1875 _OMAP3_BALLENTRY(ETK_CTL, "ae10", NULL),
1876 _OMAP3_BALLENTRY(ETK_D0, "af11", NULL),
1877 _OMAP3_BALLENTRY(ETK_D1, "ag12", NULL),
1878 _OMAP3_BALLENTRY(ETK_D10, "ae7", NULL),
1879 _OMAP3_BALLENTRY(ETK_D11, "af7", NULL),
1880 _OMAP3_BALLENTRY(ETK_D12, "ag7", NULL),
1881 _OMAP3_BALLENTRY(ETK_D13, "ah7", NULL),
1882 _OMAP3_BALLENTRY(ETK_D14, "ag8", NULL),
1883 _OMAP3_BALLENTRY(ETK_D15, "ah8", NULL),
1884 _OMAP3_BALLENTRY(ETK_D2, "ah12", NULL),
1885 _OMAP3_BALLENTRY(ETK_D3, "ae13", NULL),
1886 _OMAP3_BALLENTRY(ETK_D4, "ae11", NULL),
1887 _OMAP3_BALLENTRY(ETK_D5, "ah9", NULL),
1888 _OMAP3_BALLENTRY(ETK_D6, "af13", NULL),
1889 _OMAP3_BALLENTRY(ETK_D7, "ah14", NULL),
1890 _OMAP3_BALLENTRY(ETK_D8, "af9", NULL),
1891 _OMAP3_BALLENTRY(ETK_D9, "ag9", NULL),
1892 _OMAP3_BALLENTRY(GPMC_A1, "n4", "ac15"),
1893 _OMAP3_BALLENTRY(GPMC_A10, "k3", "ab19"),
1894 _OMAP3_BALLENTRY(GPMC_A11, NULL, "ac20"),
1895 _OMAP3_BALLENTRY(GPMC_A2, "m4", "ab15"),
1896 _OMAP3_BALLENTRY(GPMC_A3, "l4", "ac16"),
1897 _OMAP3_BALLENTRY(GPMC_A4, "k4", "ab16"),
1898 _OMAP3_BALLENTRY(GPMC_A5, "t3", "ac17"),
1899 _OMAP3_BALLENTRY(GPMC_A6, "r3", "ab17"),
1900 _OMAP3_BALLENTRY(GPMC_A7, "n3", "ac18"),
1901 _OMAP3_BALLENTRY(GPMC_A8, "m3", "ab18"),
1902 _OMAP3_BALLENTRY(GPMC_A9, "l3", "ac19"),
1903 _OMAP3_BALLENTRY(GPMC_CLK, "t4", "w2"),
1904 _OMAP3_BALLENTRY(GPMC_D10, "p1", "ab4"),
1905 _OMAP3_BALLENTRY(GPMC_D11, "r1", "ac4"),
1906 _OMAP3_BALLENTRY(GPMC_D12, "r2", "ab6"),
1907 _OMAP3_BALLENTRY(GPMC_D13, "t2", "ac6"),
1908 _OMAP3_BALLENTRY(GPMC_D14, "w1", "ab7"),
1909 _OMAP3_BALLENTRY(GPMC_D15, "y1", "ac7"),
1910 _OMAP3_BALLENTRY(GPMC_D9, "k2", "ac3"),
1911 _OMAP3_BALLENTRY(GPMC_NBE0_CLE, "g3", "ac12"),
1912 _OMAP3_BALLENTRY(GPMC_NBE1, "u3", NULL),
1913 _OMAP3_BALLENTRY(GPMC_NCS1, "h3", "y1"),
1914 _OMAP3_BALLENTRY(GPMC_NCS2, "v8", NULL),
1915 _OMAP3_BALLENTRY(GPMC_NCS3, "u8", NULL),
1916 _OMAP3_BALLENTRY(GPMC_NCS4, "t8", NULL),
1917 _OMAP3_BALLENTRY(GPMC_NCS5, "r8", NULL),
1918 _OMAP3_BALLENTRY(GPMC_NCS6, "p8", NULL),
1919 _OMAP3_BALLENTRY(GPMC_NCS7, "n8", NULL),
1920 _OMAP3_BALLENTRY(GPMC_NWP, "h1", "ab10"),
1921 _OMAP3_BALLENTRY(GPMC_WAIT1, "l8", "ac10"),
1922 _OMAP3_BALLENTRY(GPMC_WAIT2, "k8", NULL),
1923 _OMAP3_BALLENTRY(GPMC_WAIT3, "j8", NULL),
1924 _OMAP3_BALLENTRY(HDQ_SIO, "j25", NULL),
1925 _OMAP3_BALLENTRY(HSUSB0_CLK, "t28", NULL),
1926 _OMAP3_BALLENTRY(HSUSB0_DATA0, "t27", NULL),
1927 _OMAP3_BALLENTRY(HSUSB0_DATA1, "u28", NULL),
1928 _OMAP3_BALLENTRY(HSUSB0_DATA2, "u27", NULL),
1929 _OMAP3_BALLENTRY(HSUSB0_DATA3, "u26", NULL),
1930 _OMAP3_BALLENTRY(HSUSB0_DATA4, "u25", NULL),
1931 _OMAP3_BALLENTRY(HSUSB0_DATA5, "v28", NULL),
1932 _OMAP3_BALLENTRY(HSUSB0_DATA6, "v27", NULL),
1933 _OMAP3_BALLENTRY(HSUSB0_DATA7, "v26", NULL),
1934 _OMAP3_BALLENTRY(HSUSB0_DIR, "r28", NULL),
1935 _OMAP3_BALLENTRY(HSUSB0_NXT, "t26", NULL),
1936 _OMAP3_BALLENTRY(HSUSB0_STP, "t25", NULL),
1937 _OMAP3_BALLENTRY(I2C2_SCL, "af15", NULL),
1938 _OMAP3_BALLENTRY(I2C2_SDA, "ae15", NULL),
1939 _OMAP3_BALLENTRY(I2C3_SCL, "af14", NULL),
1940 _OMAP3_BALLENTRY(I2C3_SDA, "ag14", NULL),
1941 _OMAP3_BALLENTRY(I2C4_SCL, "ad26", NULL),
1942 _OMAP3_BALLENTRY(I2C4_SDA, "ae26", NULL),
1943 _OMAP3_BALLENTRY(JTAG_EMU0, "aa11", NULL),
1944 _OMAP3_BALLENTRY(JTAG_EMU1, "aa10", NULL),
1945 _OMAP3_BALLENTRY(MCBSP1_CLKR, "y21", NULL),
1946 _OMAP3_BALLENTRY(MCBSP1_CLKX, "w21", NULL),
1947 _OMAP3_BALLENTRY(MCBSP1_DR, "u21", NULL),
1948 _OMAP3_BALLENTRY(MCBSP1_DX, "v21", NULL),
1949 _OMAP3_BALLENTRY(MCBSP1_FSR, "aa21", NULL),
1950 _OMAP3_BALLENTRY(MCBSP1_FSX, "k26", NULL),
1951 _OMAP3_BALLENTRY(MCBSP2_CLKX, "n21", NULL),
1952 _OMAP3_BALLENTRY(MCBSP2_DR, "r21", NULL),
1953 _OMAP3_BALLENTRY(MCBSP2_DX, "m21", NULL),
1954 _OMAP3_BALLENTRY(MCBSP2_FSX, "p21", NULL),
1955 _OMAP3_BALLENTRY(MCBSP3_CLKX, "af5", NULL),
1956 _OMAP3_BALLENTRY(MCBSP3_DR, "ae6", NULL),
1957 _OMAP3_BALLENTRY(MCBSP3_DX, "af6", NULL),
1958 _OMAP3_BALLENTRY(MCBSP3_FSX, "ae5", NULL),
1959 _OMAP3_BALLENTRY(MCBSP4_CLKX, "ae1", NULL),
1960 _OMAP3_BALLENTRY(MCBSP4_DR, "ad1", NULL),
1961 _OMAP3_BALLENTRY(MCBSP4_DX, "ad2", NULL),
1962 _OMAP3_BALLENTRY(MCBSP4_FSX, "ac1", NULL),
1963 _OMAP3_BALLENTRY(MCBSP_CLKS, "t21", NULL),
1964 _OMAP3_BALLENTRY(MCSPI1_CLK, "ab3", NULL),
1965 _OMAP3_BALLENTRY(MCSPI1_CS0, "ac2", NULL),
1966 _OMAP3_BALLENTRY(MCSPI1_CS1, "ac3", NULL),
1967 _OMAP3_BALLENTRY(MCSPI1_CS2, "ab1", NULL),
1968 _OMAP3_BALLENTRY(MCSPI1_CS3, "ab2", NULL),
1969 _OMAP3_BALLENTRY(MCSPI1_SIMO, "ab4", NULL),
1970 _OMAP3_BALLENTRY(MCSPI1_SOMI, "aa4", NULL),
1971 _OMAP3_BALLENTRY(MCSPI2_CLK, "aa3", NULL),
1972 _OMAP3_BALLENTRY(MCSPI2_CS0, "y4", NULL),
1973 _OMAP3_BALLENTRY(MCSPI2_CS1, "v3", NULL),
1974 _OMAP3_BALLENTRY(MCSPI2_SIMO, "y2", NULL),
1975 _OMAP3_BALLENTRY(MCSPI2_SOMI, "y3", NULL),
1976 _OMAP3_BALLENTRY(SDMMC1_CLK, "n28", NULL),
1977 _OMAP3_BALLENTRY(SDMMC1_CMD, "m27", NULL),
1978 _OMAP3_BALLENTRY(SDMMC1_DAT0, "n27", NULL),
1979 _OMAP3_BALLENTRY(SDMMC1_DAT1, "n26", NULL),
1980 _OMAP3_BALLENTRY(SDMMC1_DAT2, "n25", NULL),
1981 _OMAP3_BALLENTRY(SDMMC1_DAT3, "p28", NULL),
1982 _OMAP3_BALLENTRY(SDMMC2_CLK, "ae2", NULL),
1983 _OMAP3_BALLENTRY(SDMMC2_CMD, "ag5", NULL),
1984 _OMAP3_BALLENTRY(SDMMC2_DAT0, "ah5", NULL),
1985 _OMAP3_BALLENTRY(SDMMC2_DAT1, "ah4", NULL),
1986 _OMAP3_BALLENTRY(SDMMC2_DAT2, "ag4", NULL),
1987 _OMAP3_BALLENTRY(SDMMC2_DAT3, "af4", NULL),
1988 _OMAP3_BALLENTRY(SDMMC2_DAT4, "ae4", NULL),
1989 _OMAP3_BALLENTRY(SDMMC2_DAT5, "ah3", NULL),
1990 _OMAP3_BALLENTRY(SDMMC2_DAT6, "af3", NULL),
1991 _OMAP3_BALLENTRY(SDMMC2_DAT7, "ae3", NULL),
1992 _OMAP3_BALLENTRY(SDRC_CKE0, "h16", "j22"),
1993 _OMAP3_BALLENTRY(SDRC_CKE1, "h17", "j23"),
1994 _OMAP3_BALLENTRY(SIM_CLK, "p26", NULL),
1995 _OMAP3_BALLENTRY(SIM_IO, "p27", NULL),
1996 _OMAP3_BALLENTRY(SIM_PWRCTRL, "r27", NULL),
1997 _OMAP3_BALLENTRY(SIM_RST, "r25", NULL),
1998 _OMAP3_BALLENTRY(SYS_BOOT0, "ah26", NULL),
1999 _OMAP3_BALLENTRY(SYS_BOOT1, "ag26", NULL),
2000 _OMAP3_BALLENTRY(SYS_BOOT2, "ae14", NULL),
2001 _OMAP3_BALLENTRY(SYS_BOOT3, "af18", NULL),
2002 _OMAP3_BALLENTRY(SYS_BOOT4, "af19", NULL),
2003 _OMAP3_BALLENTRY(SYS_BOOT5, "ae21", NULL),
2004 _OMAP3_BALLENTRY(SYS_BOOT6, "af21", NULL),
2005 _OMAP3_BALLENTRY(SYS_CLKOUT1, "ag25", NULL),
2006 _OMAP3_BALLENTRY(SYS_CLKOUT2, "ae22", NULL),
2007 _OMAP3_BALLENTRY(SYS_CLKREQ, "af25", NULL),
2008 _OMAP3_BALLENTRY(SYS_NIRQ, "af26", NULL),
2009 _OMAP3_BALLENTRY(SYS_NRESWARM, "af24", NULL),
2010 _OMAP3_BALLENTRY(SYS_OFF_MODE, "af22", NULL),
2011 _OMAP3_BALLENTRY(UART1_CTS, "w8", NULL),
2012 _OMAP3_BALLENTRY(UART1_RTS, "aa9", NULL),
2013 _OMAP3_BALLENTRY(UART1_RX, "y8", NULL),
2014 _OMAP3_BALLENTRY(UART1_TX, "aa8", NULL),
2015 _OMAP3_BALLENTRY(UART2_CTS, "ab26", NULL),
2016 _OMAP3_BALLENTRY(UART2_RTS, "ab25", NULL),
2017 _OMAP3_BALLENTRY(UART2_RX, "ad25", NULL),
2018 _OMAP3_BALLENTRY(UART2_TX, "aa25", NULL),
2019 _OMAP3_BALLENTRY(UART3_CTS_RCTX, "h18", NULL),
2020 _OMAP3_BALLENTRY(UART3_RTS_SD, "h19", NULL),
2021 _OMAP3_BALLENTRY(UART3_RX_IRRX, "h20", NULL),
2022 _OMAP3_BALLENTRY(UART3_TX_IRTX, "h21", NULL),
2023 { .reg_offset = OMAP_MUX_TERMINATOR },
2024};
2025#else
2026#define omap36xx_cbp_ball NULL
2027#endif
2028
2029int __init omap3_mux_init(struct omap_board_mux *board_subset, int flags)
2030{
2031 struct omap_mux *package_subset;
2032 struct omap_ball *package_balls;
2033
2034 switch (flags & OMAP_PACKAGE_MASK) {
2035 case OMAP_PACKAGE_CBC:
2036 package_subset = omap3_cbc_subset;
2037 package_balls = omap3_cbc_ball;
2038 break;
2039 case OMAP_PACKAGE_CBB:
2040 package_subset = omap3_cbb_subset;
2041 package_balls = omap3_cbb_ball;
2042 break;
2043 case OMAP_PACKAGE_CUS:
2044 package_subset = omap3_cus_subset;
2045 package_balls = omap3_cus_ball;
2046 break;
2047 case OMAP_PACKAGE_CBP:
2048 package_subset = omap36xx_cbp_subset;
2049 package_balls = omap36xx_cbp_ball;
2050 break;
2051 default:
2052 pr_err("%s Unknown omap package, mux disabled\n", __func__);
2053 return -EINVAL;
2054 }
2055
2056 return omap_mux_init("core", OMAP_MUX_GPIO_IN_MODE4,
2057 OMAP3_CONTROL_PADCONF_MUX_PBASE,
2058 OMAP3_CONTROL_PADCONF_MUX_SIZE,
2059 omap3_muxmodes, package_subset, board_subset,
2060 package_balls);
2061}
diff --git a/arch/arm/mach-omap2/mux34xx.h b/arch/arm/mach-omap2/mux34xx.h
deleted file mode 100644
index 3f26d297c082..000000000000
--- a/arch/arm/mach-omap2/mux34xx.h
+++ /dev/null
@@ -1,402 +0,0 @@
1/*
2 * Copyright (C) 2009 Nokia
3 * Copyright (C) 2009 Texas Instruments
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#define OMAP3_CONTROL_PADCONF_MUX_PBASE 0x48002030LU
11
12#define OMAP3_MUX(mode0, mux_value) \
13{ \
14 .reg_offset = (OMAP3_CONTROL_PADCONF_##mode0##_OFFSET), \
15 .value = (mux_value), \
16}
17
18/*
19 * OMAP3 CONTROL_PADCONF* register offsets for pin-muxing
20 *
21 * Extracted from the TRM. Add 0x48002030 to these values to get the
22 * absolute addresses. The name in the macro is the mode-0 name of
23 * the pin. NOTE: These registers are 16-bits wide.
24 *
25 * Note that 34XX TRM uses MMC instead of SDMMC and SAD2D instead
26 * of CHASSIS for some registers. For the defines, we follow the
27 * 36XX naming, and use SDMMC and CHASSIS.
28 */
29#define OMAP3_CONTROL_PADCONF_SDRC_D0_OFFSET 0x000
30#define OMAP3_CONTROL_PADCONF_SDRC_D1_OFFSET 0x002
31#define OMAP3_CONTROL_PADCONF_SDRC_D2_OFFSET 0x004
32#define OMAP3_CONTROL_PADCONF_SDRC_D3_OFFSET 0x006
33#define OMAP3_CONTROL_PADCONF_SDRC_D4_OFFSET 0x008
34#define OMAP3_CONTROL_PADCONF_SDRC_D5_OFFSET 0x00a
35#define OMAP3_CONTROL_PADCONF_SDRC_D6_OFFSET 0x00c
36#define OMAP3_CONTROL_PADCONF_SDRC_D7_OFFSET 0x00e
37#define OMAP3_CONTROL_PADCONF_SDRC_D8_OFFSET 0x010
38#define OMAP3_CONTROL_PADCONF_SDRC_D9_OFFSET 0x012
39#define OMAP3_CONTROL_PADCONF_SDRC_D10_OFFSET 0x014
40#define OMAP3_CONTROL_PADCONF_SDRC_D11_OFFSET 0x016
41#define OMAP3_CONTROL_PADCONF_SDRC_D12_OFFSET 0x018
42#define OMAP3_CONTROL_PADCONF_SDRC_D13_OFFSET 0x01a
43#define OMAP3_CONTROL_PADCONF_SDRC_D14_OFFSET 0x01c
44#define OMAP3_CONTROL_PADCONF_SDRC_D15_OFFSET 0x01e
45#define OMAP3_CONTROL_PADCONF_SDRC_D16_OFFSET 0x020
46#define OMAP3_CONTROL_PADCONF_SDRC_D17_OFFSET 0x022
47#define OMAP3_CONTROL_PADCONF_SDRC_D18_OFFSET 0x024
48#define OMAP3_CONTROL_PADCONF_SDRC_D19_OFFSET 0x026
49#define OMAP3_CONTROL_PADCONF_SDRC_D20_OFFSET 0x028
50#define OMAP3_CONTROL_PADCONF_SDRC_D21_OFFSET 0x02a
51#define OMAP3_CONTROL_PADCONF_SDRC_D22_OFFSET 0x02c
52#define OMAP3_CONTROL_PADCONF_SDRC_D23_OFFSET 0x02e
53#define OMAP3_CONTROL_PADCONF_SDRC_D24_OFFSET 0x030
54#define OMAP3_CONTROL_PADCONF_SDRC_D25_OFFSET 0x032
55#define OMAP3_CONTROL_PADCONF_SDRC_D26_OFFSET 0x034
56#define OMAP3_CONTROL_PADCONF_SDRC_D27_OFFSET 0x036
57#define OMAP3_CONTROL_PADCONF_SDRC_D28_OFFSET 0x038
58#define OMAP3_CONTROL_PADCONF_SDRC_D29_OFFSET 0x03a
59#define OMAP3_CONTROL_PADCONF_SDRC_D30_OFFSET 0x03c
60#define OMAP3_CONTROL_PADCONF_SDRC_D31_OFFSET 0x03e
61#define OMAP3_CONTROL_PADCONF_SDRC_CLK_OFFSET 0x040
62#define OMAP3_CONTROL_PADCONF_SDRC_DQS0_OFFSET 0x042
63#define OMAP3_CONTROL_PADCONF_SDRC_DQS1_OFFSET 0x044
64#define OMAP3_CONTROL_PADCONF_SDRC_DQS2_OFFSET 0x046
65#define OMAP3_CONTROL_PADCONF_SDRC_DQS3_OFFSET 0x048
66#define OMAP3_CONTROL_PADCONF_GPMC_A1_OFFSET 0x04a
67#define OMAP3_CONTROL_PADCONF_GPMC_A2_OFFSET 0x04c
68#define OMAP3_CONTROL_PADCONF_GPMC_A3_OFFSET 0x04e
69#define OMAP3_CONTROL_PADCONF_GPMC_A4_OFFSET 0x050
70#define OMAP3_CONTROL_PADCONF_GPMC_A5_OFFSET 0x052
71#define OMAP3_CONTROL_PADCONF_GPMC_A6_OFFSET 0x054
72#define OMAP3_CONTROL_PADCONF_GPMC_A7_OFFSET 0x056
73#define OMAP3_CONTROL_PADCONF_GPMC_A8_OFFSET 0x058
74#define OMAP3_CONTROL_PADCONF_GPMC_A9_OFFSET 0x05a
75#define OMAP3_CONTROL_PADCONF_GPMC_A10_OFFSET 0x05c
76#define OMAP3_CONTROL_PADCONF_GPMC_D0_OFFSET 0x05e
77#define OMAP3_CONTROL_PADCONF_GPMC_D1_OFFSET 0x060
78#define OMAP3_CONTROL_PADCONF_GPMC_D2_OFFSET 0x062
79#define OMAP3_CONTROL_PADCONF_GPMC_D3_OFFSET 0x064
80#define OMAP3_CONTROL_PADCONF_GPMC_D4_OFFSET 0x066
81#define OMAP3_CONTROL_PADCONF_GPMC_D5_OFFSET 0x068
82#define OMAP3_CONTROL_PADCONF_GPMC_D6_OFFSET 0x06a
83#define OMAP3_CONTROL_PADCONF_GPMC_D7_OFFSET 0x06c
84#define OMAP3_CONTROL_PADCONF_GPMC_D8_OFFSET 0x06e
85#define OMAP3_CONTROL_PADCONF_GPMC_D9_OFFSET 0x070
86#define OMAP3_CONTROL_PADCONF_GPMC_D10_OFFSET 0x072
87#define OMAP3_CONTROL_PADCONF_GPMC_D11_OFFSET 0x074
88#define OMAP3_CONTROL_PADCONF_GPMC_D12_OFFSET 0x076
89#define OMAP3_CONTROL_PADCONF_GPMC_D13_OFFSET 0x078
90#define OMAP3_CONTROL_PADCONF_GPMC_D14_OFFSET 0x07a
91#define OMAP3_CONTROL_PADCONF_GPMC_D15_OFFSET 0x07c
92#define OMAP3_CONTROL_PADCONF_GPMC_NCS0_OFFSET 0x07e
93#define OMAP3_CONTROL_PADCONF_GPMC_NCS1_OFFSET 0x080
94#define OMAP3_CONTROL_PADCONF_GPMC_NCS2_OFFSET 0x082
95#define OMAP3_CONTROL_PADCONF_GPMC_NCS3_OFFSET 0x084
96#define OMAP3_CONTROL_PADCONF_GPMC_NCS4_OFFSET 0x086
97#define OMAP3_CONTROL_PADCONF_GPMC_NCS5_OFFSET 0x088
98#define OMAP3_CONTROL_PADCONF_GPMC_NCS6_OFFSET 0x08a
99#define OMAP3_CONTROL_PADCONF_GPMC_NCS7_OFFSET 0x08c
100#define OMAP3_CONTROL_PADCONF_GPMC_CLK_OFFSET 0x08e
101#define OMAP3_CONTROL_PADCONF_GPMC_NADV_ALE_OFFSET 0x090
102#define OMAP3_CONTROL_PADCONF_GPMC_NOE_OFFSET 0x092
103#define OMAP3_CONTROL_PADCONF_GPMC_NWE_OFFSET 0x094
104#define OMAP3_CONTROL_PADCONF_GPMC_NBE0_CLE_OFFSET 0x096
105#define OMAP3_CONTROL_PADCONF_GPMC_NBE1_OFFSET 0x098
106#define OMAP3_CONTROL_PADCONF_GPMC_NWP_OFFSET 0x09a
107#define OMAP3_CONTROL_PADCONF_GPMC_WAIT0_OFFSET 0x09c
108#define OMAP3_CONTROL_PADCONF_GPMC_WAIT1_OFFSET 0x09e
109#define OMAP3_CONTROL_PADCONF_GPMC_WAIT2_OFFSET 0x0a0
110#define OMAP3_CONTROL_PADCONF_GPMC_WAIT3_OFFSET 0x0a2
111#define OMAP3_CONTROL_PADCONF_DSS_PCLK_OFFSET 0x0a4
112#define OMAP3_CONTROL_PADCONF_DSS_HSYNC_OFFSET 0x0a6
113#define OMAP3_CONTROL_PADCONF_DSS_VSYNC_OFFSET 0x0a8
114#define OMAP3_CONTROL_PADCONF_DSS_ACBIAS_OFFSET 0x0aa
115#define OMAP3_CONTROL_PADCONF_DSS_DATA0_OFFSET 0x0ac
116#define OMAP3_CONTROL_PADCONF_DSS_DATA1_OFFSET 0x0ae
117#define OMAP3_CONTROL_PADCONF_DSS_DATA2_OFFSET 0x0b0
118#define OMAP3_CONTROL_PADCONF_DSS_DATA3_OFFSET 0x0b2
119#define OMAP3_CONTROL_PADCONF_DSS_DATA4_OFFSET 0x0b4
120#define OMAP3_CONTROL_PADCONF_DSS_DATA5_OFFSET 0x0b6
121#define OMAP3_CONTROL_PADCONF_DSS_DATA6_OFFSET 0x0b8
122#define OMAP3_CONTROL_PADCONF_DSS_DATA7_OFFSET 0x0ba
123#define OMAP3_CONTROL_PADCONF_DSS_DATA8_OFFSET 0x0bc
124#define OMAP3_CONTROL_PADCONF_DSS_DATA9_OFFSET 0x0be
125#define OMAP3_CONTROL_PADCONF_DSS_DATA10_OFFSET 0x0c0
126#define OMAP3_CONTROL_PADCONF_DSS_DATA11_OFFSET 0x0c2
127#define OMAP3_CONTROL_PADCONF_DSS_DATA12_OFFSET 0x0c4
128#define OMAP3_CONTROL_PADCONF_DSS_DATA13_OFFSET 0x0c6
129#define OMAP3_CONTROL_PADCONF_DSS_DATA14_OFFSET 0x0c8
130#define OMAP3_CONTROL_PADCONF_DSS_DATA15_OFFSET 0x0ca
131#define OMAP3_CONTROL_PADCONF_DSS_DATA16_OFFSET 0x0cc
132#define OMAP3_CONTROL_PADCONF_DSS_DATA17_OFFSET 0x0ce
133#define OMAP3_CONTROL_PADCONF_DSS_DATA18_OFFSET 0x0d0
134#define OMAP3_CONTROL_PADCONF_DSS_DATA19_OFFSET 0x0d2
135#define OMAP3_CONTROL_PADCONF_DSS_DATA20_OFFSET 0x0d4
136#define OMAP3_CONTROL_PADCONF_DSS_DATA21_OFFSET 0x0d6
137#define OMAP3_CONTROL_PADCONF_DSS_DATA22_OFFSET 0x0d8
138#define OMAP3_CONTROL_PADCONF_DSS_DATA23_OFFSET 0x0da
139#define OMAP3_CONTROL_PADCONF_CAM_HS_OFFSET 0x0dc
140#define OMAP3_CONTROL_PADCONF_CAM_VS_OFFSET 0x0de
141#define OMAP3_CONTROL_PADCONF_CAM_XCLKA_OFFSET 0x0e0
142#define OMAP3_CONTROL_PADCONF_CAM_PCLK_OFFSET 0x0e2
143#define OMAP3_CONTROL_PADCONF_CAM_FLD_OFFSET 0x0e4
144#define OMAP3_CONTROL_PADCONF_CAM_D0_OFFSET 0x0e6
145#define OMAP3_CONTROL_PADCONF_CAM_D1_OFFSET 0x0e8
146#define OMAP3_CONTROL_PADCONF_CAM_D2_OFFSET 0x0ea
147#define OMAP3_CONTROL_PADCONF_CAM_D3_OFFSET 0x0ec
148#define OMAP3_CONTROL_PADCONF_CAM_D4_OFFSET 0x0ee
149#define OMAP3_CONTROL_PADCONF_CAM_D5_OFFSET 0x0f0
150#define OMAP3_CONTROL_PADCONF_CAM_D6_OFFSET 0x0f2
151#define OMAP3_CONTROL_PADCONF_CAM_D7_OFFSET 0x0f4
152#define OMAP3_CONTROL_PADCONF_CAM_D8_OFFSET 0x0f6
153#define OMAP3_CONTROL_PADCONF_CAM_D9_OFFSET 0x0f8
154#define OMAP3_CONTROL_PADCONF_CAM_D10_OFFSET 0x0fa
155#define OMAP3_CONTROL_PADCONF_CAM_D11_OFFSET 0x0fc
156#define OMAP3_CONTROL_PADCONF_CAM_XCLKB_OFFSET 0x0fe
157#define OMAP3_CONTROL_PADCONF_CAM_WEN_OFFSET 0x100
158#define OMAP3_CONTROL_PADCONF_CAM_STROBE_OFFSET 0x102
159#define OMAP3_CONTROL_PADCONF_CSI2_DX0_OFFSET 0x104
160#define OMAP3_CONTROL_PADCONF_CSI2_DY0_OFFSET 0x106
161#define OMAP3_CONTROL_PADCONF_CSI2_DX1_OFFSET 0x108
162#define OMAP3_CONTROL_PADCONF_CSI2_DY1_OFFSET 0x10a
163#define OMAP3_CONTROL_PADCONF_MCBSP2_FSX_OFFSET 0x10c
164#define OMAP3_CONTROL_PADCONF_MCBSP2_CLKX_OFFSET 0x10e
165#define OMAP3_CONTROL_PADCONF_MCBSP2_DR_OFFSET 0x110
166#define OMAP3_CONTROL_PADCONF_MCBSP2_DX_OFFSET 0x112
167#define OMAP3_CONTROL_PADCONF_SDMMC1_CLK_OFFSET 0x114
168#define OMAP3_CONTROL_PADCONF_SDMMC1_CMD_OFFSET 0x116
169#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT0_OFFSET 0x118
170#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT1_OFFSET 0x11a
171#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT2_OFFSET 0x11c
172#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT3_OFFSET 0x11e
173
174/* SDMMC1_DAT4 - DAT7 are SIM_IO SIM_CLK SIM_PWRCTRL and SIM_RST on 36xx */
175#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT4_OFFSET 0x120
176#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT5_OFFSET 0x122
177#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT6_OFFSET 0x124
178#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT7_OFFSET 0x126
179
180#define OMAP3_CONTROL_PADCONF_SDMMC2_CLK_OFFSET 0x128
181#define OMAP3_CONTROL_PADCONF_SDMMC2_CMD_OFFSET 0x12a
182#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT0_OFFSET 0x12c
183#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT1_OFFSET 0x12e
184#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT2_OFFSET 0x130
185#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT3_OFFSET 0x132
186#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT4_OFFSET 0x134
187#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT5_OFFSET 0x136
188#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT6_OFFSET 0x138
189#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT7_OFFSET 0x13a
190#define OMAP3_CONTROL_PADCONF_MCBSP3_DX_OFFSET 0x13c
191#define OMAP3_CONTROL_PADCONF_MCBSP3_DR_OFFSET 0x13e
192#define OMAP3_CONTROL_PADCONF_MCBSP3_CLKX_OFFSET 0x140
193#define OMAP3_CONTROL_PADCONF_MCBSP3_FSX_OFFSET 0x142
194#define OMAP3_CONTROL_PADCONF_UART2_CTS_OFFSET 0x144
195#define OMAP3_CONTROL_PADCONF_UART2_RTS_OFFSET 0x146
196#define OMAP3_CONTROL_PADCONF_UART2_TX_OFFSET 0x148
197#define OMAP3_CONTROL_PADCONF_UART2_RX_OFFSET 0x14a
198#define OMAP3_CONTROL_PADCONF_UART1_TX_OFFSET 0x14c
199#define OMAP3_CONTROL_PADCONF_UART1_RTS_OFFSET 0x14e
200#define OMAP3_CONTROL_PADCONF_UART1_CTS_OFFSET 0x150
201#define OMAP3_CONTROL_PADCONF_UART1_RX_OFFSET 0x152
202#define OMAP3_CONTROL_PADCONF_MCBSP4_CLKX_OFFSET 0x154
203#define OMAP3_CONTROL_PADCONF_MCBSP4_DR_OFFSET 0x156
204#define OMAP3_CONTROL_PADCONF_MCBSP4_DX_OFFSET 0x158
205#define OMAP3_CONTROL_PADCONF_MCBSP4_FSX_OFFSET 0x15a
206#define OMAP3_CONTROL_PADCONF_MCBSP1_CLKR_OFFSET 0x15c
207#define OMAP3_CONTROL_PADCONF_MCBSP1_FSR_OFFSET 0x15e
208#define OMAP3_CONTROL_PADCONF_MCBSP1_DX_OFFSET 0x160
209#define OMAP3_CONTROL_PADCONF_MCBSP1_DR_OFFSET 0x162
210#define OMAP3_CONTROL_PADCONF_MCBSP_CLKS_OFFSET 0x164
211#define OMAP3_CONTROL_PADCONF_MCBSP1_FSX_OFFSET 0x166
212#define OMAP3_CONTROL_PADCONF_MCBSP1_CLKX_OFFSET 0x168
213#define OMAP3_CONTROL_PADCONF_UART3_CTS_RCTX_OFFSET 0x16a
214#define OMAP3_CONTROL_PADCONF_UART3_RTS_SD_OFFSET 0x16c
215#define OMAP3_CONTROL_PADCONF_UART3_RX_IRRX_OFFSET 0x16e
216#define OMAP3_CONTROL_PADCONF_UART3_TX_IRTX_OFFSET 0x170
217#define OMAP3_CONTROL_PADCONF_HSUSB0_CLK_OFFSET 0x172
218#define OMAP3_CONTROL_PADCONF_HSUSB0_STP_OFFSET 0x174
219#define OMAP3_CONTROL_PADCONF_HSUSB0_DIR_OFFSET 0x176
220#define OMAP3_CONTROL_PADCONF_HSUSB0_NXT_OFFSET 0x178
221#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA0_OFFSET 0x17a
222#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA1_OFFSET 0x17c
223#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA2_OFFSET 0x17e
224#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA3_OFFSET 0x180
225#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA4_OFFSET 0x182
226#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA5_OFFSET 0x184
227#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA6_OFFSET 0x186
228#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA7_OFFSET 0x188
229#define OMAP3_CONTROL_PADCONF_I2C1_SCL_OFFSET 0x18a
230#define OMAP3_CONTROL_PADCONF_I2C1_SDA_OFFSET 0x18c
231#define OMAP3_CONTROL_PADCONF_I2C2_SCL_OFFSET 0x18e
232#define OMAP3_CONTROL_PADCONF_I2C2_SDA_OFFSET 0x190
233#define OMAP3_CONTROL_PADCONF_I2C3_SCL_OFFSET 0x192
234#define OMAP3_CONTROL_PADCONF_I2C3_SDA_OFFSET 0x194
235#define OMAP3_CONTROL_PADCONF_HDQ_SIO_OFFSET 0x196
236#define OMAP3_CONTROL_PADCONF_MCSPI1_CLK_OFFSET 0x198
237#define OMAP3_CONTROL_PADCONF_MCSPI1_SIMO_OFFSET 0x19a
238#define OMAP3_CONTROL_PADCONF_MCSPI1_SOMI_OFFSET 0x19c
239#define OMAP3_CONTROL_PADCONF_MCSPI1_CS0_OFFSET 0x19e
240#define OMAP3_CONTROL_PADCONF_MCSPI1_CS1_OFFSET 0x1a0
241#define OMAP3_CONTROL_PADCONF_MCSPI1_CS2_OFFSET 0x1a2
242#define OMAP3_CONTROL_PADCONF_MCSPI1_CS3_OFFSET 0x1a4
243#define OMAP3_CONTROL_PADCONF_MCSPI2_CLK_OFFSET 0x1a6
244#define OMAP3_CONTROL_PADCONF_MCSPI2_SIMO_OFFSET 0x1a8
245#define OMAP3_CONTROL_PADCONF_MCSPI2_SOMI_OFFSET 0x1aa
246#define OMAP3_CONTROL_PADCONF_MCSPI2_CS0_OFFSET 0x1ac
247#define OMAP3_CONTROL_PADCONF_MCSPI2_CS1_OFFSET 0x1ae
248#define OMAP3_CONTROL_PADCONF_SYS_NIRQ_OFFSET 0x1b0
249#define OMAP3_CONTROL_PADCONF_SYS_CLKOUT2_OFFSET 0x1b2
250#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD0_OFFSET 0x1b4
251#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD1_OFFSET 0x1b6
252#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD2_OFFSET 0x1b8
253#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD3_OFFSET 0x1ba
254#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD4_OFFSET 0x1bc
255#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD5_OFFSET 0x1be
256#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD6_OFFSET 0x1c0
257#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD7_OFFSET 0x1c2
258#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD8_OFFSET 0x1c4
259#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD9_OFFSET 0x1c6
260#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD10_OFFSET 0x1c8
261#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD11_OFFSET 0x1ca
262#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD12_OFFSET 0x1cc
263#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD13_OFFSET 0x1ce
264#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD14_OFFSET 0x1d0
265#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD15_OFFSET 0x1d2
266#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD16_OFFSET 0x1d4
267#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD17_OFFSET 0x1d6
268#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD18_OFFSET 0x1d8
269#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD19_OFFSET 0x1da
270#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD20_OFFSET 0x1dc
271#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD21_OFFSET 0x1de
272#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD22_OFFSET 0x1e0
273#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD23_OFFSET 0x1e2
274#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD24_OFFSET 0x1e4
275#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD25_OFFSET 0x1e6
276#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD26_OFFSET 0x1e8
277#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD27_OFFSET 0x1ea
278#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD28_OFFSET 0x1ec
279#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD29_OFFSET 0x1ee
280#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD30_OFFSET 0x1f0
281#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD31_OFFSET 0x1f2
282#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD32_OFFSET 0x1f4
283#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD33_OFFSET 0x1f6
284#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD34_OFFSET 0x1f8
285#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD35_OFFSET 0x1fa
286#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD36_OFFSET 0x1fc
287
288/* Note that 34xx TRM has SAD2D instead of CHASSIS for these */
289#define OMAP3_CONTROL_PADCONF_CHASSIS_CLK26MI_OFFSET 0x1fe
290#define OMAP3_CONTROL_PADCONF_CHASSIS_NRESPWRON_OFFSET 0x200
291#define OMAP3_CONTROL_PADCONF_CHASSIS_NRESWARW_OFFSET 0x202
292#define OMAP3_CONTROL_PADCONF_CHASSIS_NIRQ_OFFSET 0x204
293#define OMAP3_CONTROL_PADCONF_CHASSIS_FIQ_OFFSET 0x206
294#define OMAP3_CONTROL_PADCONF_CHASSIS_ARMIRQ_OFFSET 0x208
295#define OMAP3_CONTROL_PADCONF_CHASSIS_IVAIRQ_OFFSET 0x20a
296#define OMAP3_CONTROL_PADCONF_CHASSIS_DMAREQ0_OFFSET 0x20c
297#define OMAP3_CONTROL_PADCONF_CHASSIS_DMAREQ1_OFFSET 0x20e
298#define OMAP3_CONTROL_PADCONF_CHASSIS_DMAREQ2_OFFSET 0x210
299#define OMAP3_CONTROL_PADCONF_CHASSIS_DMAREQ3_OFFSET 0x212
300#define OMAP3_CONTROL_PADCONF_CHASSIS_NTRST_OFFSET 0x214
301#define OMAP3_CONTROL_PADCONF_CHASSIS_TDI_OFFSET 0x216
302#define OMAP3_CONTROL_PADCONF_CHASSIS_TDO_OFFSET 0x218
303#define OMAP3_CONTROL_PADCONF_CHASSIS_TMS_OFFSET 0x21a
304#define OMAP3_CONTROL_PADCONF_CHASSIS_TCK_OFFSET 0x21c
305#define OMAP3_CONTROL_PADCONF_CHASSIS_RTCK_OFFSET 0x21e
306#define OMAP3_CONTROL_PADCONF_CHASSIS_MSTDBY_OFFSET 0x220
307#define OMAP3_CONTROL_PADCONF_CHASSIS_IDLEREQ_OFFSET 0x222
308#define OMAP3_CONTROL_PADCONF_CHASSIS_IDLEACK_OFFSET 0x224
309
310#define OMAP3_CONTROL_PADCONF_SAD2D_MWRITE_OFFSET 0x226
311#define OMAP3_CONTROL_PADCONF_SAD2D_SWRITE_OFFSET 0x228
312#define OMAP3_CONTROL_PADCONF_SAD2D_MREAD_OFFSET 0x22a
313#define OMAP3_CONTROL_PADCONF_SAD2D_SREAD_OFFSET 0x22c
314#define OMAP3_CONTROL_PADCONF_SAD2D_MBUSFLAG_OFFSET 0x22e
315#define OMAP3_CONTROL_PADCONF_SAD2D_SBUSFLAG_OFFSET 0x230
316#define OMAP3_CONTROL_PADCONF_SDRC_CKE0_OFFSET 0x232
317#define OMAP3_CONTROL_PADCONF_SDRC_CKE1_OFFSET 0x234
318
319/* 36xx only */
320#define OMAP3_CONTROL_PADCONF_GPMC_A11_OFFSET 0x236
321#define OMAP3_CONTROL_PADCONF_SDRC_BA0_OFFSET 0x570
322#define OMAP3_CONTROL_PADCONF_SDRC_BA1_OFFSET 0x572
323#define OMAP3_CONTROL_PADCONF_SDRC_A0_OFFSET 0x574
324#define OMAP3_CONTROL_PADCONF_SDRC_A1_OFFSET 0x576
325#define OMAP3_CONTROL_PADCONF_SDRC_A2_OFFSET 0x578
326#define OMAP3_CONTROL_PADCONF_SDRC_A3_OFFSET 0x57a
327#define OMAP3_CONTROL_PADCONF_SDRC_A4_OFFSET 0x57c
328#define OMAP3_CONTROL_PADCONF_SDRC_A5_OFFSET 0x57e
329#define OMAP3_CONTROL_PADCONF_SDRC_A6_OFFSET 0x580
330#define OMAP3_CONTROL_PADCONF_SDRC_A7_OFFSET 0x582
331#define OMAP3_CONTROL_PADCONF_SDRC_A8_OFFSET 0x584
332#define OMAP3_CONTROL_PADCONF_SDRC_A9_OFFSET 0x586
333#define OMAP3_CONTROL_PADCONF_SDRC_A10_OFFSET 0x588
334#define OMAP3_CONTROL_PADCONF_SDRC_A11_OFFSET 0x58a
335#define OMAP3_CONTROL_PADCONF_SDRC_A12_OFFSET 0x58c
336#define OMAP3_CONTROL_PADCONF_SDRC_A13_OFFSET 0x58e
337#define OMAP3_CONTROL_PADCONF_SDRC_A14_OFFSET 0x590
338#define OMAP3_CONTROL_PADCONF_SDRC_NCS0_OFFSET 0x592
339#define OMAP3_CONTROL_PADCONF_SDRC_NCS1_OFFSET 0x594
340#define OMAP3_CONTROL_PADCONF_SDRC_NCLK_OFFSET 0x596
341#define OMAP3_CONTROL_PADCONF_SDRC_NRAS_OFFSET 0x598
342#define OMAP3_CONTROL_PADCONF_SDRC_NCAS_OFFSET 0x59a
343#define OMAP3_CONTROL_PADCONF_SDRC_NWE_OFFSET 0x59c
344#define OMAP3_CONTROL_PADCONF_SDRC_DM0_OFFSET 0x59e
345#define OMAP3_CONTROL_PADCONF_SDRC_DM1_OFFSET 0x5a0
346#define OMAP3_CONTROL_PADCONF_SDRC_DM2_OFFSET 0x5a2
347#define OMAP3_CONTROL_PADCONF_SDRC_DM3_OFFSET 0x5a4
348
349/* 36xx only, these are SDMMC1_DAT4 - DAT7 on 34xx */
350#define OMAP3_CONTROL_PADCONF_SIM_IO_OFFSET 0x120
351#define OMAP3_CONTROL_PADCONF_SIM_CLK_OFFSET 0x122
352#define OMAP3_CONTROL_PADCONF_SIM_PWRCTRL_OFFSET 0x124
353#define OMAP3_CONTROL_PADCONF_SIM_RST_OFFSET 0x126
354
355#define OMAP3_CONTROL_PADCONF_ETK_CLK_OFFSET 0x5a8
356#define OMAP3_CONTROL_PADCONF_ETK_CTL_OFFSET 0x5aa
357#define OMAP3_CONTROL_PADCONF_ETK_D0_OFFSET 0x5ac
358#define OMAP3_CONTROL_PADCONF_ETK_D1_OFFSET 0x5ae
359#define OMAP3_CONTROL_PADCONF_ETK_D2_OFFSET 0x5b0
360#define OMAP3_CONTROL_PADCONF_ETK_D3_OFFSET 0x5b2
361#define OMAP3_CONTROL_PADCONF_ETK_D4_OFFSET 0x5b4
362#define OMAP3_CONTROL_PADCONF_ETK_D5_OFFSET 0x5b6
363#define OMAP3_CONTROL_PADCONF_ETK_D6_OFFSET 0x5b8
364#define OMAP3_CONTROL_PADCONF_ETK_D7_OFFSET 0x5ba
365#define OMAP3_CONTROL_PADCONF_ETK_D8_OFFSET 0x5bc
366#define OMAP3_CONTROL_PADCONF_ETK_D9_OFFSET 0x5be
367#define OMAP3_CONTROL_PADCONF_ETK_D10_OFFSET 0x5c0
368#define OMAP3_CONTROL_PADCONF_ETK_D11_OFFSET 0x5c2
369#define OMAP3_CONTROL_PADCONF_ETK_D12_OFFSET 0x5c4
370#define OMAP3_CONTROL_PADCONF_ETK_D13_OFFSET 0x5c6
371#define OMAP3_CONTROL_PADCONF_ETK_D14_OFFSET 0x5c8
372#define OMAP3_CONTROL_PADCONF_ETK_D15_OFFSET 0x5ca
373#define OMAP3_CONTROL_PADCONF_I2C4_SCL_OFFSET 0x9d0
374#define OMAP3_CONTROL_PADCONF_I2C4_SDA_OFFSET 0x9d2
375#define OMAP3_CONTROL_PADCONF_SYS_32K_OFFSET 0x9d4
376#define OMAP3_CONTROL_PADCONF_SYS_CLKREQ_OFFSET 0x9d6
377#define OMAP3_CONTROL_PADCONF_SYS_NRESWARM_OFFSET 0x9d8
378#define OMAP3_CONTROL_PADCONF_SYS_BOOT0_OFFSET 0x9da
379#define OMAP3_CONTROL_PADCONF_SYS_BOOT1_OFFSET 0x9dc
380#define OMAP3_CONTROL_PADCONF_SYS_BOOT2_OFFSET 0x9de
381#define OMAP3_CONTROL_PADCONF_SYS_BOOT3_OFFSET 0x9e0
382#define OMAP3_CONTROL_PADCONF_SYS_BOOT4_OFFSET 0x9e2
383#define OMAP3_CONTROL_PADCONF_SYS_BOOT5_OFFSET 0x9e4
384#define OMAP3_CONTROL_PADCONF_SYS_BOOT6_OFFSET 0x9e6
385#define OMAP3_CONTROL_PADCONF_SYS_OFF_MODE_OFFSET 0x9e8
386#define OMAP3_CONTROL_PADCONF_SYS_CLKOUT1_OFFSET 0x9ea
387#define OMAP3_CONTROL_PADCONF_JTAG_NTRST_OFFSET 0x9ec
388#define OMAP3_CONTROL_PADCONF_JTAG_TCK_OFFSET 0x9ee
389#define OMAP3_CONTROL_PADCONF_JTAG_TMS_TMSC_OFFSET 0x9f0
390#define OMAP3_CONTROL_PADCONF_JTAG_TDI_OFFSET 0x9f2
391#define OMAP3_CONTROL_PADCONF_JTAG_EMU0_OFFSET 0x9f4
392#define OMAP3_CONTROL_PADCONF_JTAG_EMU1_OFFSET 0x9f6
393#define OMAP3_CONTROL_PADCONF_SAD2D_SWAKEUP_OFFSET 0xa1c
394#define OMAP3_CONTROL_PADCONF_JTAG_RTCK_OFFSET 0xa1e
395#define OMAP3_CONTROL_PADCONF_JTAG_TDO_OFFSET 0xa20
396#define OMAP3_CONTROL_PADCONF_GPIO_127 0xa24
397#define OMAP3_CONTROL_PADCONF_GPIO_126 0xa26
398#define OMAP3_CONTROL_PADCONF_GPIO_128 0xa28
399#define OMAP3_CONTROL_PADCONF_GPIO_129 0xa2a
400
401#define OMAP3_CONTROL_PADCONF_MUX_SIZE \
402 (OMAP3_CONTROL_PADCONF_GPIO_129 + 0x2)
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 1052b29697b8..759e1d45ba25 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -160,7 +160,6 @@
160#include "prm44xx.h" 160#include "prm44xx.h"
161#include "prm33xx.h" 161#include "prm33xx.h"
162#include "prminst44xx.h" 162#include "prminst44xx.h"
163#include "mux.h"
164#include "pm.h" 163#include "pm.h"
165 164
166/* Name of the OMAP hwmod for the MPU */ 165/* Name of the OMAP hwmod for the MPU */
@@ -217,9 +216,6 @@ static LIST_HEAD(omap_hwmod_list);
217/* mpu_oh: used to add/remove MPU initiator from sleepdep list */ 216/* mpu_oh: used to add/remove MPU initiator from sleepdep list */
218static struct omap_hwmod *mpu_oh; 217static struct omap_hwmod *mpu_oh;
219 218
220/* io_chain_lock: used to serialize reconfigurations of the I/O chain */
221static DEFINE_SPINLOCK(io_chain_lock);
222
223/* 219/*
224 * linkspace: ptr to a buffer that struct omap_hwmod_link records are 220 * linkspace: ptr to a buffer that struct omap_hwmod_link records are
225 * allocated from - used to reduce the number of small memory 221 * allocated from - used to reduce the number of small memory
@@ -594,51 +590,6 @@ static int _set_module_autoidle(struct omap_hwmod *oh, u8 autoidle,
594} 590}
595 591
596/** 592/**
597 * _set_idle_ioring_wakeup - enable/disable IO pad wakeup on hwmod idle for mux
598 * @oh: struct omap_hwmod *
599 * @set_wake: bool value indicating to set (true) or clear (false) wakeup enable
600 *
601 * Set or clear the I/O pad wakeup flag in the mux entries for the
602 * hwmod @oh. This function changes the @oh->mux->pads_dynamic array
603 * in memory. If the hwmod is currently idled, and the new idle
604 * values don't match the previous ones, this function will also
605 * update the SCM PADCTRL registers. Otherwise, if the hwmod is not
606 * currently idled, this function won't touch the hardware: the new
607 * mux settings are written to the SCM PADCTRL registers when the
608 * hwmod is idled. No return value.
609 */
610static void _set_idle_ioring_wakeup(struct omap_hwmod *oh, bool set_wake)
611{
612 struct omap_device_pad *pad;
613 bool change = false;
614 u16 prev_idle;
615 int j;
616
617 if (!oh->mux || !oh->mux->enabled)
618 return;
619
620 for (j = 0; j < oh->mux->nr_pads_dynamic; j++) {
621 pad = oh->mux->pads_dynamic[j];
622
623 if (!(pad->flags & OMAP_DEVICE_PAD_WAKEUP))
624 continue;
625
626 prev_idle = pad->idle;
627
628 if (set_wake)
629 pad->idle |= OMAP_WAKEUP_EN;
630 else
631 pad->idle &= ~OMAP_WAKEUP_EN;
632
633 if (prev_idle != pad->idle)
634 change = true;
635 }
636
637 if (change && oh->_state == _HWMOD_STATE_IDLE)
638 omap_hwmod_mux(oh->mux, _HWMOD_STATE_IDLE);
639}
640
641/**
642 * _enable_wakeup: set OCP_SYSCONFIG.ENAWAKEUP bit in the hardware 593 * _enable_wakeup: set OCP_SYSCONFIG.ENAWAKEUP bit in the hardware
643 * @oh: struct omap_hwmod * 594 * @oh: struct omap_hwmod *
644 * 595 *
@@ -2018,29 +1969,6 @@ static int _reset(struct omap_hwmod *oh)
2018} 1969}
2019 1970
2020/** 1971/**
2021 * _reconfigure_io_chain - clear any I/O chain wakeups and reconfigure chain
2022 *
2023 * Call the appropriate PRM function to clear any logged I/O chain
2024 * wakeups and to reconfigure the chain. This apparently needs to be
2025 * done upon every mux change. Since hwmods can be concurrently
2026 * enabled and idled, hold a spinlock around the I/O chain
2027 * reconfiguration sequence. No return value.
2028 *
2029 * XXX When the PRM code is moved to drivers, this function can be removed,
2030 * as the PRM infrastructure should abstract this.
2031 */
2032static void _reconfigure_io_chain(void)
2033{
2034 unsigned long flags;
2035
2036 spin_lock_irqsave(&io_chain_lock, flags);
2037
2038 omap_prm_reconfigure_io_chain();
2039
2040 spin_unlock_irqrestore(&io_chain_lock, flags);
2041}
2042
2043/**
2044 * _omap4_update_context_lost - increment hwmod context loss counter if 1972 * _omap4_update_context_lost - increment hwmod context loss counter if
2045 * hwmod context was lost, and clear hardware context loss reg 1973 * hwmod context was lost, and clear hardware context loss reg
2046 * @oh: hwmod to check for context loss 1974 * @oh: hwmod to check for context loss
@@ -2109,18 +2037,9 @@ static int _enable(struct omap_hwmod *oh)
2109 2037
2110 /* 2038 /*
2111 * hwmods with HWMOD_INIT_NO_IDLE flag set are left in enabled 2039 * hwmods with HWMOD_INIT_NO_IDLE flag set are left in enabled
2112 * state at init. Now that someone is really trying to enable 2040 * state at init.
2113 * them, just ensure that the hwmod mux is set.
2114 */ 2041 */
2115 if (oh->_int_flags & _HWMOD_SKIP_ENABLE) { 2042 if (oh->_int_flags & _HWMOD_SKIP_ENABLE) {
2116 /*
2117 * If the caller has mux data populated, do the mux'ing
2118 * which wouldn't have been done as part of the _enable()
2119 * done during setup.
2120 */
2121 if (oh->mux)
2122 omap_hwmod_mux(oh->mux, _HWMOD_STATE_ENABLED);
2123
2124 oh->_int_flags &= ~_HWMOD_SKIP_ENABLE; 2043 oh->_int_flags &= ~_HWMOD_SKIP_ENABLE;
2125 return 0; 2044 return 0;
2126 } 2045 }
@@ -2145,16 +2064,6 @@ static int _enable(struct omap_hwmod *oh)
2145 if (_are_all_hardreset_lines_asserted(oh)) 2064 if (_are_all_hardreset_lines_asserted(oh))
2146 return 0; 2065 return 0;
2147 2066
2148 /* Mux pins for device runtime if populated */
2149 if (oh->mux && (!oh->mux->enabled ||
2150 ((oh->_state == _HWMOD_STATE_IDLE) &&
2151 oh->mux->pads_dynamic))) {
2152 omap_hwmod_mux(oh->mux, _HWMOD_STATE_ENABLED);
2153 _reconfigure_io_chain();
2154 } else if (oh->flags & HWMOD_RECONFIG_IO_CHAIN) {
2155 _reconfigure_io_chain();
2156 }
2157
2158 _add_initiator_dep(oh, mpu_oh); 2067 _add_initiator_dep(oh, mpu_oh);
2159 2068
2160 if (oh->clkdm) { 2069 if (oh->clkdm) {
@@ -2260,14 +2169,6 @@ static int _idle(struct omap_hwmod *oh)
2260 clkdm_hwmod_disable(oh->clkdm, oh); 2169 clkdm_hwmod_disable(oh->clkdm, oh);
2261 } 2170 }
2262 2171
2263 /* Mux pins for device idle if populated */
2264 if (oh->mux && oh->mux->pads_dynamic) {
2265 omap_hwmod_mux(oh->mux, _HWMOD_STATE_IDLE);
2266 _reconfigure_io_chain();
2267 } else if (oh->flags & HWMOD_RECONFIG_IO_CHAIN) {
2268 _reconfigure_io_chain();
2269 }
2270
2271 oh->_state = _HWMOD_STATE_IDLE; 2172 oh->_state = _HWMOD_STATE_IDLE;
2272 2173
2273 return 0; 2174 return 0;
@@ -2334,10 +2235,6 @@ static int _shutdown(struct omap_hwmod *oh)
2334 for (i = 0; i < oh->rst_lines_cnt; i++) 2235 for (i = 0; i < oh->rst_lines_cnt; i++)
2335 _assert_hardreset(oh, oh->rst_lines[i].name); 2236 _assert_hardreset(oh, oh->rst_lines[i].name);
2336 2237
2337 /* Mux pins to safe mode or use populated off mode values */
2338 if (oh->mux)
2339 omap_hwmod_mux(oh->mux, _HWMOD_STATE_DISABLED);
2340
2341 oh->_state = _HWMOD_STATE_DISABLED; 2238 oh->_state = _HWMOD_STATE_DISABLED;
2342 2239
2343 return 0; 2240 return 0;
@@ -3729,7 +3626,6 @@ int omap_hwmod_enable_wakeup(struct omap_hwmod *oh)
3729 _write_sysconfig(v, oh); 3626 _write_sysconfig(v, oh);
3730 } 3627 }
3731 3628
3732 _set_idle_ioring_wakeup(oh, true);
3733 spin_unlock_irqrestore(&oh->_lock, flags); 3629 spin_unlock_irqrestore(&oh->_lock, flags);
3734 3630
3735 return 0; 3631 return 0;
@@ -3762,7 +3658,6 @@ int omap_hwmod_disable_wakeup(struct omap_hwmod *oh)
3762 _write_sysconfig(v, oh); 3658 _write_sysconfig(v, oh);
3763 } 3659 }
3764 3660
3765 _set_idle_ioring_wakeup(oh, false);
3766 spin_unlock_irqrestore(&oh->_lock, flags); 3661 spin_unlock_irqrestore(&oh->_lock, flags);
3767 3662
3768 return 0; 3663 return 0;
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c
index c1e98d589100..6d2e32462df9 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c
@@ -17,156 +17,11 @@
17 17
18#include "omap_hwmod_common_data.h" 18#include "omap_hwmod_common_data.h"
19 19
20struct omap_hwmod_addr_space omap2430_mmc1_addr_space[] = {
21 {
22 .pa_start = 0x4809c000,
23 .pa_end = 0x4809c1ff,
24 .flags = ADDR_TYPE_RT,
25 },
26 { }
27};
28
29struct omap_hwmod_addr_space omap2430_mmc2_addr_space[] = {
30 {
31 .pa_start = 0x480b4000,
32 .pa_end = 0x480b41ff,
33 .flags = ADDR_TYPE_RT,
34 },
35 { }
36};
37
38struct omap_hwmod_addr_space omap2_i2c1_addr_space[] = {
39 {
40 .pa_start = 0x48070000,
41 .pa_end = 0x48070000 + SZ_128 - 1,
42 .flags = ADDR_TYPE_RT,
43 },
44 { }
45};
46
47struct omap_hwmod_addr_space omap2_i2c2_addr_space[] = {
48 {
49 .pa_start = 0x48072000,
50 .pa_end = 0x48072000 + SZ_128 - 1,
51 .flags = ADDR_TYPE_RT,
52 },
53 { }
54};
55
56struct omap_hwmod_addr_space omap2_dss_addrs[] = {
57 {
58 .pa_start = 0x48050000,
59 .pa_end = 0x48050000 + SZ_1K - 1,
60 .flags = ADDR_TYPE_RT
61 },
62 { }
63};
64
65struct omap_hwmod_addr_space omap2_dss_dispc_addrs[] = {
66 {
67 .pa_start = 0x48050400,
68 .pa_end = 0x48050400 + SZ_1K - 1,
69 .flags = ADDR_TYPE_RT
70 },
71 { }
72};
73
74struct omap_hwmod_addr_space omap2_dss_rfbi_addrs[] = {
75 {
76 .pa_start = 0x48050800,
77 .pa_end = 0x48050800 + SZ_1K - 1,
78 .flags = ADDR_TYPE_RT
79 },
80 { }
81};
82
83struct omap_hwmod_addr_space omap2_dss_venc_addrs[] = {
84 {
85 .pa_start = 0x48050C00,
86 .pa_end = 0x48050C00 + SZ_1K - 1,
87 .flags = ADDR_TYPE_RT
88 },
89 { }
90};
91
92struct omap_hwmod_addr_space omap2_timer10_addrs[] = {
93 {
94 .pa_start = 0x48086000,
95 .pa_end = 0x48086000 + SZ_1K - 1,
96 .flags = ADDR_TYPE_RT
97 },
98 { }
99};
100
101struct omap_hwmod_addr_space omap2_timer11_addrs[] = {
102 {
103 .pa_start = 0x48088000,
104 .pa_end = 0x48088000 + SZ_1K - 1,
105 .flags = ADDR_TYPE_RT
106 },
107 { }
108};
109
110struct omap_hwmod_addr_space omap2xxx_timer12_addrs[] = {
111 {
112 .pa_start = 0x4808a000,
113 .pa_end = 0x4808a000 + SZ_1K - 1,
114 .flags = ADDR_TYPE_RT
115 },
116 { }
117};
118
119struct omap_hwmod_addr_space omap2_mcspi1_addr_space[] = {
120 {
121 .pa_start = 0x48098000,
122 .pa_end = 0x48098000 + SZ_256 - 1,
123 .flags = ADDR_TYPE_RT,
124 },
125 { }
126};
127
128struct omap_hwmod_addr_space omap2_mcspi2_addr_space[] = {
129 {
130 .pa_start = 0x4809a000,
131 .pa_end = 0x4809a000 + SZ_256 - 1,
132 .flags = ADDR_TYPE_RT,
133 },
134 { }
135};
136
137struct omap_hwmod_addr_space omap2430_mcspi3_addr_space[] = {
138 {
139 .pa_start = 0x480b8000,
140 .pa_end = 0x480b8000 + SZ_256 - 1,
141 .flags = ADDR_TYPE_RT,
142 },
143 { }
144};
145
146struct omap_hwmod_addr_space omap2_dma_system_addrs[] = { 20struct omap_hwmod_addr_space omap2_dma_system_addrs[] = {
147 { 21 {
148 .pa_start = 0x48056000, 22 .pa_start = 0x48056000,
149 .pa_end = 0x48056000 + SZ_4K - 1, 23 .pa_end = 0x48056000 + SZ_4K - 1,
150 .flags = ADDR_TYPE_RT 24 .flags = ADDR_TYPE_RT,
151 },
152 { }
153};
154
155struct omap_hwmod_addr_space omap2_mcbsp1_addrs[] = {
156 {
157 .name = "mpu",
158 .pa_start = 0x48074000,
159 .pa_end = 0x480740ff,
160 .flags = ADDR_TYPE_RT
161 },
162 { }
163};
164
165struct omap_hwmod_addr_space omap2_hdq1w_addr_space[] = {
166 {
167 .pa_start = 0x480b2000,
168 .pa_end = 0x480b2fff,
169 .flags = ADDR_TYPE_RT,
170 }, 25 },
171 { } 26 { },
172}; 27};
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
index c6c6384de867..cfaeb0f78cc8 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
@@ -45,204 +45,31 @@ struct omap_hwmod_class omap2_venc_hwmod_class = {
45 .name = "venc", 45 .name = "venc",
46}; 46};
47 47
48
49/* Common DMA request line data */
50struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[] = {
51 { .name = "rx", .dma_req = 50, },
52 { .name = "tx", .dma_req = 49, },
53 { .dma_req = -1 }
54};
55
56struct omap_hwmod_dma_info omap2_uart2_sdma_reqs[] = {
57 { .name = "rx", .dma_req = 52, },
58 { .name = "tx", .dma_req = 51, },
59 { .dma_req = -1 }
60};
61
62struct omap_hwmod_dma_info omap2_uart3_sdma_reqs[] = {
63 { .name = "rx", .dma_req = 54, },
64 { .name = "tx", .dma_req = 53, },
65 { .dma_req = -1 }
66};
67
68struct omap_hwmod_dma_info omap2_i2c1_sdma_reqs[] = {
69 { .name = "tx", .dma_req = 27 },
70 { .name = "rx", .dma_req = 28 },
71 { .dma_req = -1 }
72};
73
74struct omap_hwmod_dma_info omap2_i2c2_sdma_reqs[] = {
75 { .name = "tx", .dma_req = 29 },
76 { .name = "rx", .dma_req = 30 },
77 { .dma_req = -1 }
78};
79
80struct omap_hwmod_dma_info omap2_mcspi1_sdma_reqs[] = {
81 { .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */
82 { .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */
83 { .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */
84 { .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */
85 { .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */
86 { .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */
87 { .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */
88 { .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */
89 { .dma_req = -1 }
90};
91
92struct omap_hwmod_dma_info omap2_mcspi2_sdma_reqs[] = {
93 { .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */
94 { .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */
95 { .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */
96 { .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */
97 { .dma_req = -1 }
98};
99
100struct omap_hwmod_dma_info omap2_mcbsp1_sdma_reqs[] = {
101 { .name = "rx", .dma_req = 32 },
102 { .name = "tx", .dma_req = 31 },
103 { .dma_req = -1 }
104};
105
106struct omap_hwmod_dma_info omap2_mcbsp2_sdma_reqs[] = {
107 { .name = "rx", .dma_req = 34 },
108 { .name = "tx", .dma_req = 33 },
109 { .dma_req = -1 }
110};
111
112struct omap_hwmod_dma_info omap2_mcbsp3_sdma_reqs[] = {
113 { .name = "rx", .dma_req = 18 },
114 { .name = "tx", .dma_req = 17 },
115 { .dma_req = -1 }
116};
117
118/* Other IP block data */
119
120
121/* 48/*
122 * omap_hwmod class data 49 * omap_hwmod class data
123 */ 50 */
124 51
125struct omap_hwmod_class l3_hwmod_class = { 52struct omap_hwmod_class l3_hwmod_class = {
126 .name = "l3" 53 .name = "l3",
127}; 54};
128 55
129struct omap_hwmod_class l4_hwmod_class = { 56struct omap_hwmod_class l4_hwmod_class = {
130 .name = "l4" 57 .name = "l4",
131}; 58};
132 59
133struct omap_hwmod_class mpu_hwmod_class = { 60struct omap_hwmod_class mpu_hwmod_class = {
134 .name = "mpu" 61 .name = "mpu",
135}; 62};
136 63
137struct omap_hwmod_class iva_hwmod_class = { 64struct omap_hwmod_class iva_hwmod_class = {
138 .name = "iva" 65 .name = "iva",
139}; 66};
140 67
141/* Common MPU IRQ line data */ 68/* Common MPU IRQ line data */
142 69
143struct omap_hwmod_irq_info omap2_timer1_mpu_irqs[] = {
144 { .irq = 37 + OMAP_INTC_START, },
145 { .irq = -1 },
146};
147
148struct omap_hwmod_irq_info omap2_timer2_mpu_irqs[] = {
149 { .irq = 38 + OMAP_INTC_START, },
150 { .irq = -1 },
151};
152
153struct omap_hwmod_irq_info omap2_timer3_mpu_irqs[] = {
154 { .irq = 39 + OMAP_INTC_START, },
155 { .irq = -1 },
156};
157
158struct omap_hwmod_irq_info omap2_timer4_mpu_irqs[] = {
159 { .irq = 40 + OMAP_INTC_START, },
160 { .irq = -1 },
161};
162
163struct omap_hwmod_irq_info omap2_timer5_mpu_irqs[] = {
164 { .irq = 41 + OMAP_INTC_START, },
165 { .irq = -1 },
166};
167
168struct omap_hwmod_irq_info omap2_timer6_mpu_irqs[] = {
169 { .irq = 42 + OMAP_INTC_START, },
170 { .irq = -1 },
171};
172
173struct omap_hwmod_irq_info omap2_timer7_mpu_irqs[] = {
174 { .irq = 43 + OMAP_INTC_START, },
175 { .irq = -1 },
176};
177
178struct omap_hwmod_irq_info omap2_timer8_mpu_irqs[] = {
179 { .irq = 44 + OMAP_INTC_START, },
180 { .irq = -1 },
181};
182
183struct omap_hwmod_irq_info omap2_timer9_mpu_irqs[] = {
184 { .irq = 45 + OMAP_INTC_START, },
185 { .irq = -1 },
186};
187
188struct omap_hwmod_irq_info omap2_timer10_mpu_irqs[] = {
189 { .irq = 46 + OMAP_INTC_START, },
190 { .irq = -1 },
191};
192
193struct omap_hwmod_irq_info omap2_timer11_mpu_irqs[] = {
194 { .irq = 47 + OMAP_INTC_START, },
195 { .irq = -1 },
196};
197
198struct omap_hwmod_irq_info omap2_uart1_mpu_irqs[] = {
199 { .irq = 72 + OMAP_INTC_START, },
200 { .irq = -1 },
201};
202
203struct omap_hwmod_irq_info omap2_uart2_mpu_irqs[] = {
204 { .irq = 73 + OMAP_INTC_START, },
205 { .irq = -1 },
206};
207
208struct omap_hwmod_irq_info omap2_uart3_mpu_irqs[] = {
209 { .irq = 74 + OMAP_INTC_START, },
210 { .irq = -1 },
211};
212
213struct omap_hwmod_irq_info omap2_dispc_irqs[] = { 70struct omap_hwmod_irq_info omap2_dispc_irqs[] = {
214 { .irq = 25 + OMAP_INTC_START, }, 71 { .irq = 25 + OMAP_INTC_START, },
215 { .irq = -1 }, 72 { .irq = -1, },
216};
217
218struct omap_hwmod_irq_info omap2_i2c1_mpu_irqs[] = {
219 { .irq = 56 + OMAP_INTC_START, },
220 { .irq = -1 },
221};
222
223struct omap_hwmod_irq_info omap2_i2c2_mpu_irqs[] = {
224 { .irq = 57 + OMAP_INTC_START, },
225 { .irq = -1 },
226};
227
228struct omap_hwmod_irq_info omap2_gpio1_irqs[] = {
229 { .irq = 29 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK1 */
230 { .irq = -1 },
231};
232
233struct omap_hwmod_irq_info omap2_gpio2_irqs[] = {
234 { .irq = 30 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK2 */
235 { .irq = -1 },
236};
237
238struct omap_hwmod_irq_info omap2_gpio3_irqs[] = {
239 { .irq = 31 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK3 */
240 { .irq = -1 },
241};
242
243struct omap_hwmod_irq_info omap2_gpio4_irqs[] = {
244 { .irq = 32 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK4 */
245 { .irq = -1 },
246}; 73};
247 74
248struct omap_hwmod_irq_info omap2_dma_system_irqs[] = { 75struct omap_hwmod_irq_info omap2_dma_system_irqs[] = {
@@ -250,17 +77,7 @@ struct omap_hwmod_irq_info omap2_dma_system_irqs[] = {
250 { .name = "1", .irq = 13 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ1 */ 77 { .name = "1", .irq = 13 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ1 */
251 { .name = "2", .irq = 14 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ2 */ 78 { .name = "2", .irq = 14 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ2 */
252 { .name = "3", .irq = 15 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ3 */ 79 { .name = "3", .irq = 15 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ3 */
253 { .irq = -1 }, 80 { .irq = -1, },
254};
255
256struct omap_hwmod_irq_info omap2_mcspi1_mpu_irqs[] = {
257 { .irq = 65 + OMAP_INTC_START, },
258 { .irq = -1 },
259};
260
261struct omap_hwmod_irq_info omap2_mcspi2_mpu_irqs[] = {
262 { .irq = 66 + OMAP_INTC_START, },
263 { .irq = -1 },
264}; 81};
265 82
266struct omap_hwmod_class_sysconfig omap2_hdq1w_sysc = { 83struct omap_hwmod_class_sysconfig omap2_hdq1w_sysc = {
@@ -277,9 +94,3 @@ struct omap_hwmod_class omap2_hdq1w_class = {
277 .sysc = &omap2_hdq1w_sysc, 94 .sysc = &omap2_hdq1w_sysc,
278 .reset = &omap_hdq1w_reset, 95 .reset = &omap_hdq1w_reset,
279}; 96};
280
281struct omap_hwmod_irq_info omap2_hdq1w_mpu_irqs[] = {
282 { .irq = 58 + OMAP_INTC_START, },
283 { .irq = -1 },
284};
285
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
index 656861c29d5c..9b30b6b471ae 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
@@ -191,7 +191,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__dss = {
191 .master = &omap2xxx_l4_core_hwmod, 191 .master = &omap2xxx_l4_core_hwmod,
192 .slave = &omap2xxx_dss_core_hwmod, 192 .slave = &omap2xxx_dss_core_hwmod,
193 .clk = "dss_ick", 193 .clk = "dss_ick",
194 .addr = omap2_dss_addrs,
195 .fw = { 194 .fw = {
196 .omap2 = { 195 .omap2 = {
197 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION, 196 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
@@ -206,7 +205,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_dispc = {
206 .master = &omap2xxx_l4_core_hwmod, 205 .master = &omap2xxx_l4_core_hwmod,
207 .slave = &omap2xxx_dss_dispc_hwmod, 206 .slave = &omap2xxx_dss_dispc_hwmod,
208 .clk = "dss_ick", 207 .clk = "dss_ick",
209 .addr = omap2_dss_dispc_addrs,
210 .fw = { 208 .fw = {
211 .omap2 = { 209 .omap2 = {
212 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION, 210 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION,
@@ -221,7 +219,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_rfbi = {
221 .master = &omap2xxx_l4_core_hwmod, 219 .master = &omap2xxx_l4_core_hwmod,
222 .slave = &omap2xxx_dss_rfbi_hwmod, 220 .slave = &omap2xxx_dss_rfbi_hwmod,
223 .clk = "dss_ick", 221 .clk = "dss_ick",
224 .addr = omap2_dss_rfbi_addrs,
225 .fw = { 222 .fw = {
226 .omap2 = { 223 .omap2 = {
227 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION, 224 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
@@ -236,7 +233,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_venc = {
236 .master = &omap2xxx_l4_core_hwmod, 233 .master = &omap2xxx_l4_core_hwmod,
237 .slave = &omap2xxx_dss_venc_hwmod, 234 .slave = &omap2xxx_dss_venc_hwmod,
238 .clk = "dss_ick", 235 .clk = "dss_ick",
239 .addr = omap2_dss_venc_addrs,
240 .fw = { 236 .fw = {
241 .omap2 = { 237 .omap2 = {
242 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_VENC_REGION, 238 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_VENC_REGION,
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
index 36bcd2e75422..e047033caa3e 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
@@ -569,7 +569,6 @@ struct omap_hwmod omap2xxx_dss_core_hwmod = {
569struct omap_hwmod omap2xxx_dss_dispc_hwmod = { 569struct omap_hwmod omap2xxx_dss_dispc_hwmod = {
570 .name = "dss_dispc", 570 .name = "dss_dispc",
571 .class = &omap2_dispc_hwmod_class, 571 .class = &omap2_dispc_hwmod_class,
572 .mpu_irqs = omap2_dispc_irqs,
573 .main_clk = "dss1_fck", 572 .main_clk = "dss1_fck",
574 .prcm = { 573 .prcm = {
575 .omap2 = { 574 .omap2 = {
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 1cc4a6f3954e..56f917ec8621 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -53,16 +53,10 @@
53 */ 53 */
54 54
55/* L3 */ 55/* L3 */
56static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
57 { .irq = 9 + OMAP_INTC_START, },
58 { .irq = 10 + OMAP_INTC_START, },
59 { .irq = -1 },
60};
61 56
62static struct omap_hwmod omap3xxx_l3_main_hwmod = { 57static struct omap_hwmod omap3xxx_l3_main_hwmod = {
63 .name = "l3_main", 58 .name = "l3_main",
64 .class = &l3_hwmod_class, 59 .class = &l3_hwmod_class,
65 .mpu_irqs = omap3xxx_l3_main_irqs,
66 .flags = HWMOD_NO_IDLEST, 60 .flags = HWMOD_NO_IDLEST,
67}; 61};
68 62
@@ -95,14 +89,9 @@ static struct omap_hwmod omap3xxx_l4_sec_hwmod = {
95}; 89};
96 90
97/* MPU */ 91/* MPU */
98static struct omap_hwmod_irq_info omap3xxx_mpu_irqs[] = {
99 { .name = "pmu", .irq = 3 + OMAP_INTC_START },
100 { .irq = -1 }
101};
102 92
103static struct omap_hwmod omap3xxx_mpu_hwmod = { 93static struct omap_hwmod omap3xxx_mpu_hwmod = {
104 .name = "mpu", 94 .name = "mpu",
105 .mpu_irqs = omap3xxx_mpu_irqs,
106 .class = &mpu_hwmod_class, 95 .class = &mpu_hwmod_class,
107 .main_clk = "arm_fck", 96 .main_clk = "arm_fck",
108}; 97};
@@ -128,7 +117,7 @@ static struct omap_hwmod omap3xxx_iva_hwmod = {
128 .module_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT, 117 .module_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
129 .idlest_reg_id = 1, 118 .idlest_reg_id = 1,
130 .idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT, 119 .idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT,
131 } 120 },
132 }, 121 },
133}; 122};
134 123
@@ -197,7 +186,6 @@ static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
197/* timer1 */ 186/* timer1 */
198static struct omap_hwmod omap3xxx_timer1_hwmod = { 187static struct omap_hwmod omap3xxx_timer1_hwmod = {
199 .name = "timer1", 188 .name = "timer1",
200 .mpu_irqs = omap2_timer1_mpu_irqs,
201 .main_clk = "gpt1_fck", 189 .main_clk = "gpt1_fck",
202 .prcm = { 190 .prcm = {
203 .omap2 = { 191 .omap2 = {
@@ -216,7 +204,6 @@ static struct omap_hwmod omap3xxx_timer1_hwmod = {
216/* timer2 */ 204/* timer2 */
217static struct omap_hwmod omap3xxx_timer2_hwmod = { 205static struct omap_hwmod omap3xxx_timer2_hwmod = {
218 .name = "timer2", 206 .name = "timer2",
219 .mpu_irqs = omap2_timer2_mpu_irqs,
220 .main_clk = "gpt2_fck", 207 .main_clk = "gpt2_fck",
221 .prcm = { 208 .prcm = {
222 .omap2 = { 209 .omap2 = {
@@ -234,7 +221,6 @@ static struct omap_hwmod omap3xxx_timer2_hwmod = {
234/* timer3 */ 221/* timer3 */
235static struct omap_hwmod omap3xxx_timer3_hwmod = { 222static struct omap_hwmod omap3xxx_timer3_hwmod = {
236 .name = "timer3", 223 .name = "timer3",
237 .mpu_irqs = omap2_timer3_mpu_irqs,
238 .main_clk = "gpt3_fck", 224 .main_clk = "gpt3_fck",
239 .prcm = { 225 .prcm = {
240 .omap2 = { 226 .omap2 = {
@@ -252,7 +238,6 @@ static struct omap_hwmod omap3xxx_timer3_hwmod = {
252/* timer4 */ 238/* timer4 */
253static struct omap_hwmod omap3xxx_timer4_hwmod = { 239static struct omap_hwmod omap3xxx_timer4_hwmod = {
254 .name = "timer4", 240 .name = "timer4",
255 .mpu_irqs = omap2_timer4_mpu_irqs,
256 .main_clk = "gpt4_fck", 241 .main_clk = "gpt4_fck",
257 .prcm = { 242 .prcm = {
258 .omap2 = { 243 .omap2 = {
@@ -270,7 +255,6 @@ static struct omap_hwmod omap3xxx_timer4_hwmod = {
270/* timer5 */ 255/* timer5 */
271static struct omap_hwmod omap3xxx_timer5_hwmod = { 256static struct omap_hwmod omap3xxx_timer5_hwmod = {
272 .name = "timer5", 257 .name = "timer5",
273 .mpu_irqs = omap2_timer5_mpu_irqs,
274 .main_clk = "gpt5_fck", 258 .main_clk = "gpt5_fck",
275 .prcm = { 259 .prcm = {
276 .omap2 = { 260 .omap2 = {
@@ -289,7 +273,6 @@ static struct omap_hwmod omap3xxx_timer5_hwmod = {
289/* timer6 */ 273/* timer6 */
290static struct omap_hwmod omap3xxx_timer6_hwmod = { 274static struct omap_hwmod omap3xxx_timer6_hwmod = {
291 .name = "timer6", 275 .name = "timer6",
292 .mpu_irqs = omap2_timer6_mpu_irqs,
293 .main_clk = "gpt6_fck", 276 .main_clk = "gpt6_fck",
294 .prcm = { 277 .prcm = {
295 .omap2 = { 278 .omap2 = {
@@ -308,7 +291,6 @@ static struct omap_hwmod omap3xxx_timer6_hwmod = {
308/* timer7 */ 291/* timer7 */
309static struct omap_hwmod omap3xxx_timer7_hwmod = { 292static struct omap_hwmod omap3xxx_timer7_hwmod = {
310 .name = "timer7", 293 .name = "timer7",
311 .mpu_irqs = omap2_timer7_mpu_irqs,
312 .main_clk = "gpt7_fck", 294 .main_clk = "gpt7_fck",
313 .prcm = { 295 .prcm = {
314 .omap2 = { 296 .omap2 = {
@@ -327,7 +309,6 @@ static struct omap_hwmod omap3xxx_timer7_hwmod = {
327/* timer8 */ 309/* timer8 */
328static struct omap_hwmod omap3xxx_timer8_hwmod = { 310static struct omap_hwmod omap3xxx_timer8_hwmod = {
329 .name = "timer8", 311 .name = "timer8",
330 .mpu_irqs = omap2_timer8_mpu_irqs,
331 .main_clk = "gpt8_fck", 312 .main_clk = "gpt8_fck",
332 .prcm = { 313 .prcm = {
333 .omap2 = { 314 .omap2 = {
@@ -346,7 +327,6 @@ static struct omap_hwmod omap3xxx_timer8_hwmod = {
346/* timer9 */ 327/* timer9 */
347static struct omap_hwmod omap3xxx_timer9_hwmod = { 328static struct omap_hwmod omap3xxx_timer9_hwmod = {
348 .name = "timer9", 329 .name = "timer9",
349 .mpu_irqs = omap2_timer9_mpu_irqs,
350 .main_clk = "gpt9_fck", 330 .main_clk = "gpt9_fck",
351 .prcm = { 331 .prcm = {
352 .omap2 = { 332 .omap2 = {
@@ -365,7 +345,6 @@ static struct omap_hwmod omap3xxx_timer9_hwmod = {
365/* timer10 */ 345/* timer10 */
366static struct omap_hwmod omap3xxx_timer10_hwmod = { 346static struct omap_hwmod omap3xxx_timer10_hwmod = {
367 .name = "timer10", 347 .name = "timer10",
368 .mpu_irqs = omap2_timer10_mpu_irqs,
369 .main_clk = "gpt10_fck", 348 .main_clk = "gpt10_fck",
370 .prcm = { 349 .prcm = {
371 .omap2 = { 350 .omap2 = {
@@ -384,7 +363,6 @@ static struct omap_hwmod omap3xxx_timer10_hwmod = {
384/* timer11 */ 363/* timer11 */
385static struct omap_hwmod omap3xxx_timer11_hwmod = { 364static struct omap_hwmod omap3xxx_timer11_hwmod = {
386 .name = "timer11", 365 .name = "timer11",
387 .mpu_irqs = omap2_timer11_mpu_irqs,
388 .main_clk = "gpt11_fck", 366 .main_clk = "gpt11_fck",
389 .prcm = { 367 .prcm = {
390 .omap2 = { 368 .omap2 = {
@@ -401,14 +379,9 @@ static struct omap_hwmod omap3xxx_timer11_hwmod = {
401}; 379};
402 380
403/* timer12 */ 381/* timer12 */
404static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
405 { .irq = 95 + OMAP_INTC_START, },
406 { .irq = -1 },
407};
408 382
409static struct omap_hwmod omap3xxx_timer12_hwmod = { 383static struct omap_hwmod omap3xxx_timer12_hwmod = {
410 .name = "timer12", 384 .name = "timer12",
411 .mpu_irqs = omap3xxx_timer12_mpu_irqs,
412 .main_clk = "gpt12_fck", 385 .main_clk = "gpt12_fck",
413 .prcm = { 386 .prcm = {
414 .omap2 = { 387 .omap2 = {
@@ -485,8 +458,6 @@ static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
485/* UART1 */ 458/* UART1 */
486static struct omap_hwmod omap3xxx_uart1_hwmod = { 459static struct omap_hwmod omap3xxx_uart1_hwmod = {
487 .name = "uart1", 460 .name = "uart1",
488 .mpu_irqs = omap2_uart1_mpu_irqs,
489 .sdma_reqs = omap2_uart1_sdma_reqs,
490 .main_clk = "uart1_fck", 461 .main_clk = "uart1_fck",
491 .flags = DEBUG_TI81XXUART1_FLAGS | HWMOD_SWSUP_SIDLE, 462 .flags = DEBUG_TI81XXUART1_FLAGS | HWMOD_SWSUP_SIDLE,
492 .prcm = { 463 .prcm = {
@@ -504,8 +475,6 @@ static struct omap_hwmod omap3xxx_uart1_hwmod = {
504/* UART2 */ 475/* UART2 */
505static struct omap_hwmod omap3xxx_uart2_hwmod = { 476static struct omap_hwmod omap3xxx_uart2_hwmod = {
506 .name = "uart2", 477 .name = "uart2",
507 .mpu_irqs = omap2_uart2_mpu_irqs,
508 .sdma_reqs = omap2_uart2_sdma_reqs,
509 .main_clk = "uart2_fck", 478 .main_clk = "uart2_fck",
510 .flags = DEBUG_TI81XXUART2_FLAGS | HWMOD_SWSUP_SIDLE, 479 .flags = DEBUG_TI81XXUART2_FLAGS | HWMOD_SWSUP_SIDLE,
511 .prcm = { 480 .prcm = {
@@ -523,8 +492,6 @@ static struct omap_hwmod omap3xxx_uart2_hwmod = {
523/* UART3 */ 492/* UART3 */
524static struct omap_hwmod omap3xxx_uart3_hwmod = { 493static struct omap_hwmod omap3xxx_uart3_hwmod = {
525 .name = "uart3", 494 .name = "uart3",
526 .mpu_irqs = omap2_uart3_mpu_irqs,
527 .sdma_reqs = omap2_uart3_sdma_reqs,
528 .main_clk = "uart3_fck", 495 .main_clk = "uart3_fck",
529 .flags = DEBUG_OMAP3UART3_FLAGS | DEBUG_TI81XXUART3_FLAGS | 496 .flags = DEBUG_OMAP3UART3_FLAGS | DEBUG_TI81XXUART3_FLAGS |
530 HWMOD_SWSUP_SIDLE, 497 HWMOD_SWSUP_SIDLE,
@@ -541,21 +508,10 @@ static struct omap_hwmod omap3xxx_uart3_hwmod = {
541}; 508};
542 509
543/* UART4 */ 510/* UART4 */
544static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
545 { .irq = 80 + OMAP_INTC_START, },
546 { .irq = -1 },
547};
548 511
549static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
550 { .name = "rx", .dma_req = 82, },
551 { .name = "tx", .dma_req = 81, },
552 { .dma_req = -1 }
553};
554 512
555static struct omap_hwmod omap36xx_uart4_hwmod = { 513static struct omap_hwmod omap36xx_uart4_hwmod = {
556 .name = "uart4", 514 .name = "uart4",
557 .mpu_irqs = uart4_mpu_irqs,
558 .sdma_reqs = uart4_sdma_reqs,
559 .main_clk = "uart4_fck", 515 .main_clk = "uart4_fck",
560 .flags = DEBUG_OMAP3UART4_FLAGS | HWMOD_SWSUP_SIDLE, 516 .flags = DEBUG_OMAP3UART4_FLAGS | HWMOD_SWSUP_SIDLE,
561 .prcm = { 517 .prcm = {
@@ -570,16 +526,7 @@ static struct omap_hwmod omap36xx_uart4_hwmod = {
570 .class = &omap2_uart_class, 526 .class = &omap2_uart_class,
571}; 527};
572 528
573static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = {
574 { .irq = 84 + OMAP_INTC_START, },
575 { .irq = -1 },
576};
577 529
578static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = {
579 { .name = "rx", .dma_req = 55, },
580 { .name = "tx", .dma_req = 54, },
581 { .dma_req = -1 }
582};
583 530
584/* 531/*
585 * XXX AM35xx UART4 cannot complete its softreset without uart1_fck or 532 * XXX AM35xx UART4 cannot complete its softreset without uart1_fck or
@@ -597,8 +544,6 @@ static struct omap_hwmod_opt_clk am35xx_uart4_opt_clks[] = {
597 544
598static struct omap_hwmod am35xx_uart4_hwmod = { 545static struct omap_hwmod am35xx_uart4_hwmod = {
599 .name = "uart4", 546 .name = "uart4",
600 .mpu_irqs = am35xx_uart4_mpu_irqs,
601 .sdma_reqs = am35xx_uart4_sdma_reqs,
602 .main_clk = "uart4_fck", 547 .main_clk = "uart4_fck",
603 .prcm = { 548 .prcm = {
604 .omap2 = { 549 .omap2 = {
@@ -625,7 +570,7 @@ static struct omap_hwmod_class i2c_class = {
625static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = { 570static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
626 { .name = "dispc", .dma_req = 5 }, 571 { .name = "dispc", .dma_req = 5 },
627 { .name = "dsi1", .dma_req = 74 }, 572 { .name = "dsi1", .dma_req = 74 },
628 { .dma_req = -1 } 573 { .dma_req = -1, },
629}; 574};
630 575
631/* dss */ 576/* dss */
@@ -714,7 +659,7 @@ static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
714 }, 659 },
715 }, 660 },
716 .flags = HWMOD_NO_IDLEST, 661 .flags = HWMOD_NO_IDLEST,
717 .dev_attr = &omap2_3_dss_dispc_dev_attr 662 .dev_attr = &omap2_3_dss_dispc_dev_attr,
718}; 663};
719 664
720/* 665/*
@@ -738,11 +683,6 @@ static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
738 .sysc = &omap3xxx_dsi_sysc, 683 .sysc = &omap3xxx_dsi_sysc,
739}; 684};
740 685
741static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
742 { .irq = 25 + OMAP_INTC_START, },
743 { .irq = -1 },
744};
745
746/* dss_dsi1 */ 686/* dss_dsi1 */
747static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = { 687static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
748 { .role = "sys_clk", .clk = "dss2_alwon_fck" }, 688 { .role = "sys_clk", .clk = "dss2_alwon_fck" },
@@ -751,7 +691,6 @@ static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
751static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = { 691static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
752 .name = "dss_dsi1", 692 .name = "dss_dsi1",
753 .class = &omap3xxx_dsi_hwmod_class, 693 .class = &omap3xxx_dsi_hwmod_class,
754 .mpu_irqs = omap3xxx_dsi1_irqs,
755 .main_clk = "dss1_alwon_fck", 694 .main_clk = "dss1_alwon_fck",
756 .prcm = { 695 .prcm = {
757 .omap2 = { 696 .omap2 = {
@@ -815,8 +754,6 @@ static struct omap_i2c_dev_attr i2c1_dev_attr = {
815static struct omap_hwmod omap3xxx_i2c1_hwmod = { 754static struct omap_hwmod omap3xxx_i2c1_hwmod = {
816 .name = "i2c1", 755 .name = "i2c1",
817 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, 756 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
818 .mpu_irqs = omap2_i2c1_mpu_irqs,
819 .sdma_reqs = omap2_i2c1_sdma_reqs,
820 .main_clk = "i2c1_fck", 757 .main_clk = "i2c1_fck",
821 .prcm = { 758 .prcm = {
822 .omap2 = { 759 .omap2 = {
@@ -840,8 +777,6 @@ static struct omap_i2c_dev_attr i2c2_dev_attr = {
840static struct omap_hwmod omap3xxx_i2c2_hwmod = { 777static struct omap_hwmod omap3xxx_i2c2_hwmod = {
841 .name = "i2c2", 778 .name = "i2c2",
842 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, 779 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
843 .mpu_irqs = omap2_i2c2_mpu_irqs,
844 .sdma_reqs = omap2_i2c2_sdma_reqs,
845 .main_clk = "i2c2_fck", 780 .main_clk = "i2c2_fck",
846 .prcm = { 781 .prcm = {
847 .omap2 = { 782 .omap2 = {
@@ -862,22 +797,11 @@ static struct omap_i2c_dev_attr i2c3_dev_attr = {
862 .flags = OMAP_I2C_FLAG_BUS_SHIFT_2, 797 .flags = OMAP_I2C_FLAG_BUS_SHIFT_2,
863}; 798};
864 799
865static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
866 { .irq = 61 + OMAP_INTC_START, },
867 { .irq = -1 },
868};
869 800
870static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
871 { .name = "tx", .dma_req = 25 },
872 { .name = "rx", .dma_req = 26 },
873 { .dma_req = -1 }
874};
875 801
876static struct omap_hwmod omap3xxx_i2c3_hwmod = { 802static struct omap_hwmod omap3xxx_i2c3_hwmod = {
877 .name = "i2c3", 803 .name = "i2c3",
878 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, 804 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
879 .mpu_irqs = i2c3_mpu_irqs,
880 .sdma_reqs = i2c3_sdma_reqs,
881 .main_clk = "i2c3_fck", 805 .main_clk = "i2c3_fck",
882 .prcm = { 806 .prcm = {
883 .omap2 = { 807 .omap2 = {
@@ -928,7 +852,6 @@ static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
928static struct omap_hwmod omap3xxx_gpio1_hwmod = { 852static struct omap_hwmod omap3xxx_gpio1_hwmod = {
929 .name = "gpio1", 853 .name = "gpio1",
930 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 854 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
931 .mpu_irqs = omap2_gpio1_irqs,
932 .main_clk = "gpio1_ick", 855 .main_clk = "gpio1_ick",
933 .opt_clks = gpio1_opt_clks, 856 .opt_clks = gpio1_opt_clks,
934 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), 857 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
@@ -953,7 +876,6 @@ static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
953static struct omap_hwmod omap3xxx_gpio2_hwmod = { 876static struct omap_hwmod omap3xxx_gpio2_hwmod = {
954 .name = "gpio2", 877 .name = "gpio2",
955 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 878 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
956 .mpu_irqs = omap2_gpio2_irqs,
957 .main_clk = "gpio2_ick", 879 .main_clk = "gpio2_ick",
958 .opt_clks = gpio2_opt_clks, 880 .opt_clks = gpio2_opt_clks,
959 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), 881 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
@@ -978,7 +900,6 @@ static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
978static struct omap_hwmod omap3xxx_gpio3_hwmod = { 900static struct omap_hwmod omap3xxx_gpio3_hwmod = {
979 .name = "gpio3", 901 .name = "gpio3",
980 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 902 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
981 .mpu_irqs = omap2_gpio3_irqs,
982 .main_clk = "gpio3_ick", 903 .main_clk = "gpio3_ick",
983 .opt_clks = gpio3_opt_clks, 904 .opt_clks = gpio3_opt_clks,
984 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), 905 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
@@ -1003,7 +924,6 @@ static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1003static struct omap_hwmod omap3xxx_gpio4_hwmod = { 924static struct omap_hwmod omap3xxx_gpio4_hwmod = {
1004 .name = "gpio4", 925 .name = "gpio4",
1005 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 926 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1006 .mpu_irqs = omap2_gpio4_irqs,
1007 .main_clk = "gpio4_ick", 927 .main_clk = "gpio4_ick",
1008 .opt_clks = gpio4_opt_clks, 928 .opt_clks = gpio4_opt_clks,
1009 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), 929 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
@@ -1021,10 +941,6 @@ static struct omap_hwmod omap3xxx_gpio4_hwmod = {
1021}; 941};
1022 942
1023/* gpio5 */ 943/* gpio5 */
1024static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
1025 { .irq = 33 + OMAP_INTC_START, }, /* INT_34XX_GPIO_BANK5 */
1026 { .irq = -1 },
1027};
1028 944
1029static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { 945static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1030 { .role = "dbclk", .clk = "gpio5_dbck", }, 946 { .role = "dbclk", .clk = "gpio5_dbck", },
@@ -1033,7 +949,6 @@ static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1033static struct omap_hwmod omap3xxx_gpio5_hwmod = { 949static struct omap_hwmod omap3xxx_gpio5_hwmod = {
1034 .name = "gpio5", 950 .name = "gpio5",
1035 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 951 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1036 .mpu_irqs = omap3xxx_gpio5_irqs,
1037 .main_clk = "gpio5_ick", 952 .main_clk = "gpio5_ick",
1038 .opt_clks = gpio5_opt_clks, 953 .opt_clks = gpio5_opt_clks,
1039 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks), 954 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
@@ -1051,10 +966,6 @@ static struct omap_hwmod omap3xxx_gpio5_hwmod = {
1051}; 966};
1052 967
1053/* gpio6 */ 968/* gpio6 */
1054static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
1055 { .irq = 34 + OMAP_INTC_START, }, /* INT_34XX_GPIO_BANK6 */
1056 { .irq = -1 },
1057};
1058 969
1059static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { 970static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1060 { .role = "dbclk", .clk = "gpio6_dbck", }, 971 { .role = "dbclk", .clk = "gpio6_dbck", },
@@ -1063,7 +974,6 @@ static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1063static struct omap_hwmod omap3xxx_gpio6_hwmod = { 974static struct omap_hwmod omap3xxx_gpio6_hwmod = {
1064 .name = "gpio6", 975 .name = "gpio6",
1065 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 976 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1066 .mpu_irqs = omap3xxx_gpio6_irqs,
1067 .main_clk = "gpio6_ick", 977 .main_clk = "gpio6_ick",
1068 .opt_clks = gpio6_opt_clks, 978 .opt_clks = gpio6_opt_clks,
1069 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks), 979 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
@@ -1156,18 +1066,10 @@ static struct omap_hwmod_opt_clk mcbsp234_opt_clks[] = {
1156}; 1066};
1157 1067
1158/* mcbsp1 */ 1068/* mcbsp1 */
1159static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
1160 { .name = "common", .irq = 16 + OMAP_INTC_START, },
1161 { .name = "tx", .irq = 59 + OMAP_INTC_START, },
1162 { .name = "rx", .irq = 60 + OMAP_INTC_START, },
1163 { .irq = -1 },
1164};
1165 1069
1166static struct omap_hwmod omap3xxx_mcbsp1_hwmod = { 1070static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
1167 .name = "mcbsp1", 1071 .name = "mcbsp1",
1168 .class = &omap3xxx_mcbsp_hwmod_class, 1072 .class = &omap3xxx_mcbsp_hwmod_class,
1169 .mpu_irqs = omap3xxx_mcbsp1_irqs,
1170 .sdma_reqs = omap2_mcbsp1_sdma_reqs,
1171 .main_clk = "mcbsp1_fck", 1073 .main_clk = "mcbsp1_fck",
1172 .prcm = { 1074 .prcm = {
1173 .omap2 = { 1075 .omap2 = {
@@ -1183,12 +1085,6 @@ static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
1183}; 1085};
1184 1086
1185/* mcbsp2 */ 1087/* mcbsp2 */
1186static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
1187 { .name = "common", .irq = 17 + OMAP_INTC_START, },
1188 { .name = "tx", .irq = 62 + OMAP_INTC_START, },
1189 { .name = "rx", .irq = 63 + OMAP_INTC_START, },
1190 { .irq = -1 },
1191};
1192 1088
1193static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = { 1089static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
1194 .sidetone = "mcbsp2_sidetone", 1090 .sidetone = "mcbsp2_sidetone",
@@ -1197,8 +1093,6 @@ static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
1197static struct omap_hwmod omap3xxx_mcbsp2_hwmod = { 1093static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
1198 .name = "mcbsp2", 1094 .name = "mcbsp2",
1199 .class = &omap3xxx_mcbsp_hwmod_class, 1095 .class = &omap3xxx_mcbsp_hwmod_class,
1200 .mpu_irqs = omap3xxx_mcbsp2_irqs,
1201 .sdma_reqs = omap2_mcbsp2_sdma_reqs,
1202 .main_clk = "mcbsp2_fck", 1096 .main_clk = "mcbsp2_fck",
1203 .prcm = { 1097 .prcm = {
1204 .omap2 = { 1098 .omap2 = {
@@ -1215,12 +1109,6 @@ static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
1215}; 1109};
1216 1110
1217/* mcbsp3 */ 1111/* mcbsp3 */
1218static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
1219 { .name = "common", .irq = 22 + OMAP_INTC_START, },
1220 { .name = "tx", .irq = 89 + OMAP_INTC_START, },
1221 { .name = "rx", .irq = 90 + OMAP_INTC_START, },
1222 { .irq = -1 },
1223};
1224 1112
1225static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = { 1113static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
1226 .sidetone = "mcbsp3_sidetone", 1114 .sidetone = "mcbsp3_sidetone",
@@ -1229,8 +1117,6 @@ static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
1229static struct omap_hwmod omap3xxx_mcbsp3_hwmod = { 1117static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
1230 .name = "mcbsp3", 1118 .name = "mcbsp3",
1231 .class = &omap3xxx_mcbsp_hwmod_class, 1119 .class = &omap3xxx_mcbsp_hwmod_class,
1232 .mpu_irqs = omap3xxx_mcbsp3_irqs,
1233 .sdma_reqs = omap2_mcbsp3_sdma_reqs,
1234 .main_clk = "mcbsp3_fck", 1120 .main_clk = "mcbsp3_fck",
1235 .prcm = { 1121 .prcm = {
1236 .omap2 = { 1122 .omap2 = {
@@ -1247,24 +1133,11 @@ static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
1247}; 1133};
1248 1134
1249/* mcbsp4 */ 1135/* mcbsp4 */
1250static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
1251 { .name = "common", .irq = 23 + OMAP_INTC_START, },
1252 { .name = "tx", .irq = 54 + OMAP_INTC_START, },
1253 { .name = "rx", .irq = 55 + OMAP_INTC_START, },
1254 { .irq = -1 },
1255};
1256 1136
1257static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
1258 { .name = "rx", .dma_req = 20 },
1259 { .name = "tx", .dma_req = 19 },
1260 { .dma_req = -1 }
1261};
1262 1137
1263static struct omap_hwmod omap3xxx_mcbsp4_hwmod = { 1138static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
1264 .name = "mcbsp4", 1139 .name = "mcbsp4",
1265 .class = &omap3xxx_mcbsp_hwmod_class, 1140 .class = &omap3xxx_mcbsp_hwmod_class,
1266 .mpu_irqs = omap3xxx_mcbsp4_irqs,
1267 .sdma_reqs = omap3xxx_mcbsp4_sdma_chs,
1268 .main_clk = "mcbsp4_fck", 1141 .main_clk = "mcbsp4_fck",
1269 .prcm = { 1142 .prcm = {
1270 .omap2 = { 1143 .omap2 = {
@@ -1280,24 +1153,11 @@ static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
1280}; 1153};
1281 1154
1282/* mcbsp5 */ 1155/* mcbsp5 */
1283static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
1284 { .name = "common", .irq = 27 + OMAP_INTC_START, },
1285 { .name = "tx", .irq = 81 + OMAP_INTC_START, },
1286 { .name = "rx", .irq = 82 + OMAP_INTC_START, },
1287 { .irq = -1 },
1288};
1289 1156
1290static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
1291 { .name = "rx", .dma_req = 22 },
1292 { .name = "tx", .dma_req = 21 },
1293 { .dma_req = -1 }
1294};
1295 1157
1296static struct omap_hwmod omap3xxx_mcbsp5_hwmod = { 1158static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
1297 .name = "mcbsp5", 1159 .name = "mcbsp5",
1298 .class = &omap3xxx_mcbsp_hwmod_class, 1160 .class = &omap3xxx_mcbsp_hwmod_class,
1299 .mpu_irqs = omap3xxx_mcbsp5_irqs,
1300 .sdma_reqs = omap3xxx_mcbsp5_sdma_chs,
1301 .main_clk = "mcbsp5_fck", 1161 .main_clk = "mcbsp5_fck",
1302 .prcm = { 1162 .prcm = {
1303 .omap2 = { 1163 .omap2 = {
@@ -1325,29 +1185,19 @@ static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
1325}; 1185};
1326 1186
1327/* mcbsp2_sidetone */ 1187/* mcbsp2_sidetone */
1328static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
1329 { .name = "irq", .irq = 4 + OMAP_INTC_START, },
1330 { .irq = -1 },
1331};
1332 1188
1333static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = { 1189static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
1334 .name = "mcbsp2_sidetone", 1190 .name = "mcbsp2_sidetone",
1335 .class = &omap3xxx_mcbsp_sidetone_hwmod_class, 1191 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
1336 .mpu_irqs = omap3xxx_mcbsp2_sidetone_irqs,
1337 .main_clk = "mcbsp2_ick", 1192 .main_clk = "mcbsp2_ick",
1338 .flags = HWMOD_NO_IDLEST, 1193 .flags = HWMOD_NO_IDLEST,
1339}; 1194};
1340 1195
1341/* mcbsp3_sidetone */ 1196/* mcbsp3_sidetone */
1342static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
1343 { .name = "irq", .irq = 5 + OMAP_INTC_START, },
1344 { .irq = -1 },
1345};
1346 1197
1347static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = { 1198static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
1348 .name = "mcbsp3_sidetone", 1199 .name = "mcbsp3_sidetone",
1349 .class = &omap3xxx_mcbsp_sidetone_hwmod_class, 1200 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
1350 .mpu_irqs = omap3xxx_mcbsp3_sidetone_irqs,
1351 .main_clk = "mcbsp3_ick", 1201 .main_clk = "mcbsp3_ick",
1352 .flags = HWMOD_NO_IDLEST, 1202 .flags = HWMOD_NO_IDLEST,
1353}; 1203};
@@ -1394,10 +1244,6 @@ static struct omap_smartreflex_dev_attr sr1_dev_attr = {
1394 .sensor_voltdm_name = "mpu_iva", 1244 .sensor_voltdm_name = "mpu_iva",
1395}; 1245};
1396 1246
1397static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = {
1398 { .irq = 18 + OMAP_INTC_START, },
1399 { .irq = -1 },
1400};
1401 1247
1402static struct omap_hwmod omap34xx_sr1_hwmod = { 1248static struct omap_hwmod omap34xx_sr1_hwmod = {
1403 .name = "smartreflex_mpu_iva", 1249 .name = "smartreflex_mpu_iva",
@@ -1413,7 +1259,6 @@ static struct omap_hwmod omap34xx_sr1_hwmod = {
1413 }, 1259 },
1414 }, 1260 },
1415 .dev_attr = &sr1_dev_attr, 1261 .dev_attr = &sr1_dev_attr,
1416 .mpu_irqs = omap3_smartreflex_mpu_irqs,
1417 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 1262 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
1418}; 1263};
1419 1264
@@ -1431,7 +1276,6 @@ static struct omap_hwmod omap36xx_sr1_hwmod = {
1431 }, 1276 },
1432 }, 1277 },
1433 .dev_attr = &sr1_dev_attr, 1278 .dev_attr = &sr1_dev_attr,
1434 .mpu_irqs = omap3_smartreflex_mpu_irqs,
1435}; 1279};
1436 1280
1437/* SR2 */ 1281/* SR2 */
@@ -1439,10 +1283,6 @@ static struct omap_smartreflex_dev_attr sr2_dev_attr = {
1439 .sensor_voltdm_name = "core", 1283 .sensor_voltdm_name = "core",
1440}; 1284};
1441 1285
1442static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = {
1443 { .irq = 19 + OMAP_INTC_START, },
1444 { .irq = -1 },
1445};
1446 1286
1447static struct omap_hwmod omap34xx_sr2_hwmod = { 1287static struct omap_hwmod omap34xx_sr2_hwmod = {
1448 .name = "smartreflex_core", 1288 .name = "smartreflex_core",
@@ -1458,7 +1298,6 @@ static struct omap_hwmod omap34xx_sr2_hwmod = {
1458 }, 1298 },
1459 }, 1299 },
1460 .dev_attr = &sr2_dev_attr, 1300 .dev_attr = &sr2_dev_attr,
1461 .mpu_irqs = omap3_smartreflex_core_irqs,
1462 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 1301 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
1463}; 1302};
1464 1303
@@ -1476,7 +1315,6 @@ static struct omap_hwmod omap36xx_sr2_hwmod = {
1476 }, 1315 },
1477 }, 1316 },
1478 .dev_attr = &sr2_dev_attr, 1317 .dev_attr = &sr2_dev_attr,
1479 .mpu_irqs = omap3_smartreflex_core_irqs,
1480}; 1318};
1481 1319
1482/* 1320/*
@@ -1545,8 +1383,6 @@ static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
1545 1383
1546static struct omap_hwmod omap34xx_mcspi1 = { 1384static struct omap_hwmod omap34xx_mcspi1 = {
1547 .name = "mcspi1", 1385 .name = "mcspi1",
1548 .mpu_irqs = omap2_mcspi1_mpu_irqs,
1549 .sdma_reqs = omap2_mcspi1_sdma_reqs,
1550 .main_clk = "mcspi1_fck", 1386 .main_clk = "mcspi1_fck",
1551 .prcm = { 1387 .prcm = {
1552 .omap2 = { 1388 .omap2 = {
@@ -1568,8 +1404,6 @@ static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
1568 1404
1569static struct omap_hwmod omap34xx_mcspi2 = { 1405static struct omap_hwmod omap34xx_mcspi2 = {
1570 .name = "mcspi2", 1406 .name = "mcspi2",
1571 .mpu_irqs = omap2_mcspi2_mpu_irqs,
1572 .sdma_reqs = omap2_mcspi2_sdma_reqs,
1573 .main_clk = "mcspi2_fck", 1407 .main_clk = "mcspi2_fck",
1574 .prcm = { 1408 .prcm = {
1575 .omap2 = { 1409 .omap2 = {
@@ -1585,18 +1419,7 @@ static struct omap_hwmod omap34xx_mcspi2 = {
1585}; 1419};
1586 1420
1587/* mcspi3 */ 1421/* mcspi3 */
1588static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
1589 { .name = "irq", .irq = 91 + OMAP_INTC_START, }, /* 91 */
1590 { .irq = -1 },
1591};
1592 1422
1593static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
1594 { .name = "tx0", .dma_req = 15 },
1595 { .name = "rx0", .dma_req = 16 },
1596 { .name = "tx1", .dma_req = 23 },
1597 { .name = "rx1", .dma_req = 24 },
1598 { .dma_req = -1 }
1599};
1600 1423
1601static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = { 1424static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
1602 .num_chipselect = 2, 1425 .num_chipselect = 2,
@@ -1604,8 +1427,6 @@ static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
1604 1427
1605static struct omap_hwmod omap34xx_mcspi3 = { 1428static struct omap_hwmod omap34xx_mcspi3 = {
1606 .name = "mcspi3", 1429 .name = "mcspi3",
1607 .mpu_irqs = omap34xx_mcspi3_mpu_irqs,
1608 .sdma_reqs = omap34xx_mcspi3_sdma_reqs,
1609 .main_clk = "mcspi3_fck", 1430 .main_clk = "mcspi3_fck",
1610 .prcm = { 1431 .prcm = {
1611 .omap2 = { 1432 .omap2 = {
@@ -1621,16 +1442,7 @@ static struct omap_hwmod omap34xx_mcspi3 = {
1621}; 1442};
1622 1443
1623/* mcspi4 */ 1444/* mcspi4 */
1624static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
1625 { .name = "irq", .irq = 48 + OMAP_INTC_START, },
1626 { .irq = -1 },
1627};
1628 1445
1629static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
1630 { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
1631 { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
1632 { .dma_req = -1 }
1633};
1634 1446
1635static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = { 1447static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
1636 .num_chipselect = 1, 1448 .num_chipselect = 1,
@@ -1638,8 +1450,6 @@ static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
1638 1450
1639static struct omap_hwmod omap34xx_mcspi4 = { 1451static struct omap_hwmod omap34xx_mcspi4 = {
1640 .name = "mcspi4", 1452 .name = "mcspi4",
1641 .mpu_irqs = omap34xx_mcspi4_mpu_irqs,
1642 .sdma_reqs = omap34xx_mcspi4_sdma_reqs,
1643 .main_clk = "mcspi4_fck", 1453 .main_clk = "mcspi4_fck",
1644 .prcm = { 1454 .prcm = {
1645 .omap2 = { 1455 .omap2 = {
@@ -1673,16 +1483,9 @@ static struct omap_hwmod_class usbotg_class = {
1673}; 1483};
1674 1484
1675/* usb_otg_hs */ 1485/* usb_otg_hs */
1676static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
1677
1678 { .name = "mc", .irq = 92 + OMAP_INTC_START, },
1679 { .name = "dma", .irq = 93 + OMAP_INTC_START, },
1680 { .irq = -1 },
1681};
1682 1486
1683static struct omap_hwmod omap3xxx_usbhsotg_hwmod = { 1487static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
1684 .name = "usb_otg_hs", 1488 .name = "usb_otg_hs",
1685 .mpu_irqs = omap3xxx_usbhsotg_mpu_irqs,
1686 .main_clk = "hsotgusb_ick", 1489 .main_clk = "hsotgusb_ick",
1687 .prcm = { 1490 .prcm = {
1688 .omap2 = { 1491 .omap2 = {
@@ -1691,7 +1494,7 @@ static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
1691 .module_offs = CORE_MOD, 1494 .module_offs = CORE_MOD,
1692 .idlest_reg_id = 1, 1495 .idlest_reg_id = 1,
1693 .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT, 1496 .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
1694 .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT 1497 .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT,
1695 }, 1498 },
1696 }, 1499 },
1697 .class = &usbotg_class, 1500 .class = &usbotg_class,
@@ -1711,10 +1514,6 @@ static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
1711}; 1514};
1712 1515
1713/* usb_otg_hs */ 1516/* usb_otg_hs */
1714static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
1715 { .name = "mc", .irq = 71 + OMAP_INTC_START, },
1716 { .irq = -1 },
1717};
1718 1517
1719static struct omap_hwmod_class am35xx_usbotg_class = { 1518static struct omap_hwmod_class am35xx_usbotg_class = {
1720 .name = "am35xx_usbotg", 1519 .name = "am35xx_usbotg",
@@ -1722,7 +1521,6 @@ static struct omap_hwmod_class am35xx_usbotg_class = {
1722 1521
1723static struct omap_hwmod am35xx_usbhsotg_hwmod = { 1522static struct omap_hwmod am35xx_usbhsotg_hwmod = {
1724 .name = "am35x_otg_hs", 1523 .name = "am35x_otg_hs",
1725 .mpu_irqs = am35xx_usbhsotg_mpu_irqs,
1726 .main_clk = "hsotgusb_fck", 1524 .main_clk = "hsotgusb_fck",
1727 .class = &am35xx_usbotg_class, 1525 .class = &am35xx_usbotg_class,
1728 .flags = HWMOD_NO_IDLEST, 1526 .flags = HWMOD_NO_IDLEST,
@@ -1747,16 +1545,7 @@ static struct omap_hwmod_class omap34xx_mmc_class = {
1747 1545
1748/* MMC/SD/SDIO1 */ 1546/* MMC/SD/SDIO1 */
1749 1547
1750static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
1751 { .irq = 83 + OMAP_INTC_START, },
1752 { .irq = -1 },
1753};
1754 1548
1755static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
1756 { .name = "tx", .dma_req = 61, },
1757 { .name = "rx", .dma_req = 62, },
1758 { .dma_req = -1 }
1759};
1760 1549
1761static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = { 1550static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
1762 { .role = "dbck", .clk = "omap_32k_fck", }, 1551 { .role = "dbck", .clk = "omap_32k_fck", },
@@ -1774,8 +1563,6 @@ static struct omap_hsmmc_dev_attr mmc1_pre_es3_dev_attr = {
1774 1563
1775static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = { 1564static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = {
1776 .name = "mmc1", 1565 .name = "mmc1",
1777 .mpu_irqs = omap34xx_mmc1_mpu_irqs,
1778 .sdma_reqs = omap34xx_mmc1_sdma_reqs,
1779 .opt_clks = omap34xx_mmc1_opt_clks, 1566 .opt_clks = omap34xx_mmc1_opt_clks,
1780 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks), 1567 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
1781 .main_clk = "mmchs1_fck", 1568 .main_clk = "mmchs1_fck",
@@ -1794,8 +1581,6 @@ static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = {
1794 1581
1795static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = { 1582static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = {
1796 .name = "mmc1", 1583 .name = "mmc1",
1797 .mpu_irqs = omap34xx_mmc1_mpu_irqs,
1798 .sdma_reqs = omap34xx_mmc1_sdma_reqs,
1799 .opt_clks = omap34xx_mmc1_opt_clks, 1584 .opt_clks = omap34xx_mmc1_opt_clks,
1800 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks), 1585 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
1801 .main_clk = "mmchs1_fck", 1586 .main_clk = "mmchs1_fck",
@@ -1814,16 +1599,7 @@ static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = {
1814 1599
1815/* MMC/SD/SDIO2 */ 1600/* MMC/SD/SDIO2 */
1816 1601
1817static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
1818 { .irq = 86 + OMAP_INTC_START, },
1819 { .irq = -1 },
1820};
1821 1602
1822static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
1823 { .name = "tx", .dma_req = 47, },
1824 { .name = "rx", .dma_req = 48, },
1825 { .dma_req = -1 }
1826};
1827 1603
1828static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = { 1604static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
1829 { .role = "dbck", .clk = "omap_32k_fck", }, 1605 { .role = "dbck", .clk = "omap_32k_fck", },
@@ -1836,8 +1612,6 @@ static struct omap_hsmmc_dev_attr mmc2_pre_es3_dev_attr = {
1836 1612
1837static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = { 1613static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = {
1838 .name = "mmc2", 1614 .name = "mmc2",
1839 .mpu_irqs = omap34xx_mmc2_mpu_irqs,
1840 .sdma_reqs = omap34xx_mmc2_sdma_reqs,
1841 .opt_clks = omap34xx_mmc2_opt_clks, 1615 .opt_clks = omap34xx_mmc2_opt_clks,
1842 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks), 1616 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
1843 .main_clk = "mmchs2_fck", 1617 .main_clk = "mmchs2_fck",
@@ -1856,8 +1630,6 @@ static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = {
1856 1630
1857static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = { 1631static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = {
1858 .name = "mmc2", 1632 .name = "mmc2",
1859 .mpu_irqs = omap34xx_mmc2_mpu_irqs,
1860 .sdma_reqs = omap34xx_mmc2_sdma_reqs,
1861 .opt_clks = omap34xx_mmc2_opt_clks, 1633 .opt_clks = omap34xx_mmc2_opt_clks,
1862 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks), 1634 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
1863 .main_clk = "mmchs2_fck", 1635 .main_clk = "mmchs2_fck",
@@ -1875,16 +1647,7 @@ static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = {
1875 1647
1876/* MMC/SD/SDIO3 */ 1648/* MMC/SD/SDIO3 */
1877 1649
1878static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
1879 { .irq = 94 + OMAP_INTC_START, },
1880 { .irq = -1 },
1881};
1882 1650
1883static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
1884 { .name = "tx", .dma_req = 77, },
1885 { .name = "rx", .dma_req = 78, },
1886 { .dma_req = -1 }
1887};
1888 1651
1889static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = { 1652static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
1890 { .role = "dbck", .clk = "omap_32k_fck", }, 1653 { .role = "dbck", .clk = "omap_32k_fck", },
@@ -1892,8 +1655,6 @@ static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
1892 1655
1893static struct omap_hwmod omap3xxx_mmc3_hwmod = { 1656static struct omap_hwmod omap3xxx_mmc3_hwmod = {
1894 .name = "mmc3", 1657 .name = "mmc3",
1895 .mpu_irqs = omap34xx_mmc3_mpu_irqs,
1896 .sdma_reqs = omap34xx_mmc3_sdma_reqs,
1897 .opt_clks = omap34xx_mmc3_opt_clks, 1658 .opt_clks = omap34xx_mmc3_opt_clks,
1898 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc3_opt_clks), 1659 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
1899 .main_clk = "mmchs3_fck", 1660 .main_clk = "mmchs3_fck",
@@ -1931,17 +1692,11 @@ static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = {
1931 .sysc = &omap3xxx_usb_host_hs_sysc, 1692 .sysc = &omap3xxx_usb_host_hs_sysc,
1932}; 1693};
1933 1694
1934static struct omap_hwmod_irq_info omap3xxx_usb_host_hs_irqs[] = {
1935 { .name = "ohci-irq", .irq = 76 + OMAP_INTC_START, },
1936 { .name = "ehci-irq", .irq = 77 + OMAP_INTC_START, },
1937 { .irq = -1 },
1938};
1939 1695
1940static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = { 1696static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = {
1941 .name = "usb_host_hs", 1697 .name = "usb_host_hs",
1942 .class = &omap3xxx_usb_host_hs_hwmod_class, 1698 .class = &omap3xxx_usb_host_hs_hwmod_class,
1943 .clkdm_name = "usbhost_clkdm", 1699 .clkdm_name = "usbhost_clkdm",
1944 .mpu_irqs = omap3xxx_usb_host_hs_irqs,
1945 .main_clk = "usbhost_48m_fck", 1700 .main_clk = "usbhost_48m_fck",
1946 .prcm = { 1701 .prcm = {
1947 .omap2 = { 1702 .omap2 = {
@@ -2015,16 +1770,11 @@ static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class = {
2015 .sysc = &omap3xxx_usb_tll_hs_sysc, 1770 .sysc = &omap3xxx_usb_tll_hs_sysc,
2016}; 1771};
2017 1772
2018static struct omap_hwmod_irq_info omap3xxx_usb_tll_hs_irqs[] = {
2019 { .name = "tll-irq", .irq = 78 + OMAP_INTC_START, },
2020 { .irq = -1 },
2021};
2022 1773
2023static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = { 1774static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = {
2024 .name = "usb_tll_hs", 1775 .name = "usb_tll_hs",
2025 .class = &omap3xxx_usb_tll_hs_hwmod_class, 1776 .class = &omap3xxx_usb_tll_hs_hwmod_class,
2026 .clkdm_name = "core_l4_clkdm", 1777 .clkdm_name = "core_l4_clkdm",
2027 .mpu_irqs = omap3xxx_usb_tll_hs_irqs,
2028 .main_clk = "usbtll_fck", 1778 .main_clk = "usbtll_fck",
2029 .prcm = { 1779 .prcm = {
2030 .omap2 = { 1780 .omap2 = {
@@ -2039,7 +1789,6 @@ static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = {
2039 1789
2040static struct omap_hwmod omap3xxx_hdq1w_hwmod = { 1790static struct omap_hwmod omap3xxx_hdq1w_hwmod = {
2041 .name = "hdq1w", 1791 .name = "hdq1w",
2042 .mpu_irqs = omap2_hdq1w_mpu_irqs,
2043 .main_clk = "hdq_fck", 1792 .main_clk = "hdq_fck",
2044 .prcm = { 1793 .prcm = {
2045 .omap2 = { 1794 .omap2 = {
@@ -2134,16 +1883,10 @@ static struct omap_hwmod_class omap3xxx_gpmc_hwmod_class = {
2134 .sysc = &omap3xxx_gpmc_sysc, 1883 .sysc = &omap3xxx_gpmc_sysc,
2135}; 1884};
2136 1885
2137static struct omap_hwmod_irq_info omap3xxx_gpmc_irqs[] = {
2138 { .irq = 20 + OMAP_INTC_START, },
2139 { .irq = -1 }
2140};
2141
2142static struct omap_hwmod omap3xxx_gpmc_hwmod = { 1886static struct omap_hwmod omap3xxx_gpmc_hwmod = {
2143 .name = "gpmc", 1887 .name = "gpmc",
2144 .class = &omap3xxx_gpmc_hwmod_class, 1888 .class = &omap3xxx_gpmc_hwmod_class,
2145 .clkdm_name = "core_l3_clkdm", 1889 .clkdm_name = "core_l3_clkdm",
2146 .mpu_irqs = omap3xxx_gpmc_irqs,
2147 .main_clk = "gpmc_fck", 1890 .main_clk = "gpmc_fck",
2148 /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */ 1891 /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
2149 .flags = HWMOD_NO_IDLEST | DEBUG_OMAP_GPMC_HWMOD_FLAGS, 1892 .flags = HWMOD_NO_IDLEST | DEBUG_OMAP_GPMC_HWMOD_FLAGS,
@@ -2167,37 +1910,19 @@ static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
2167 .user = OCP_USER_MPU | OCP_USER_SDMA, 1910 .user = OCP_USER_MPU | OCP_USER_SDMA,
2168}; 1911};
2169 1912
2170static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
2171 {
2172 .pa_start = 0x68000000,
2173 .pa_end = 0x6800ffff,
2174 .flags = ADDR_TYPE_RT,
2175 },
2176 { }
2177};
2178 1913
2179/* MPU -> L3 interface */ 1914/* MPU -> L3 interface */
2180static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = { 1915static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
2181 .master = &omap3xxx_mpu_hwmod, 1916 .master = &omap3xxx_mpu_hwmod,
2182 .slave = &omap3xxx_l3_main_hwmod, 1917 .slave = &omap3xxx_l3_main_hwmod,
2183 .addr = omap3xxx_l3_main_addrs,
2184 .user = OCP_USER_MPU, 1918 .user = OCP_USER_MPU,
2185}; 1919};
2186 1920
2187static struct omap_hwmod_addr_space omap3xxx_l4_emu_addrs[] = {
2188 {
2189 .pa_start = 0x54000000,
2190 .pa_end = 0x547fffff,
2191 .flags = ADDR_TYPE_RT,
2192 },
2193 { }
2194};
2195 1921
2196/* l3 -> debugss */ 1922/* l3 -> debugss */
2197static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_debugss = { 1923static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_debugss = {
2198 .master = &omap3xxx_l3_main_hwmod, 1924 .master = &omap3xxx_l3_main_hwmod,
2199 .slave = &omap3xxx_debugss_hwmod, 1925 .slave = &omap3xxx_debugss_hwmod,
2200 .addr = omap3xxx_l4_emu_addrs,
2201 .user = OCP_USER_MPU, 1926 .user = OCP_USER_MPU,
2202}; 1927};
2203 1928
@@ -2215,7 +1940,7 @@ static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
2215 .omap2 = { 1940 .omap2 = {
2216 .l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS, 1941 .l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS,
2217 .flags = OMAP_FIREWALL_L3, 1942 .flags = OMAP_FIREWALL_L3,
2218 } 1943 },
2219 }, 1944 },
2220 .user = OCP_USER_MPU | OCP_USER_SDMA, 1945 .user = OCP_USER_MPU | OCP_USER_SDMA,
2221}; 1946};
@@ -2256,18 +1981,16 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc1 = {
2256 .master = &omap3xxx_l4_core_hwmod, 1981 .master = &omap3xxx_l4_core_hwmod,
2257 .slave = &omap3xxx_pre_es3_mmc1_hwmod, 1982 .slave = &omap3xxx_pre_es3_mmc1_hwmod,
2258 .clk = "mmchs1_ick", 1983 .clk = "mmchs1_ick",
2259 .addr = omap2430_mmc1_addr_space,
2260 .user = OCP_USER_MPU | OCP_USER_SDMA, 1984 .user = OCP_USER_MPU | OCP_USER_SDMA,
2261 .flags = OMAP_FIREWALL_L4 1985 .flags = OMAP_FIREWALL_L4,
2262}; 1986};
2263 1987
2264static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc1 = { 1988static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc1 = {
2265 .master = &omap3xxx_l4_core_hwmod, 1989 .master = &omap3xxx_l4_core_hwmod,
2266 .slave = &omap3xxx_es3plus_mmc1_hwmod, 1990 .slave = &omap3xxx_es3plus_mmc1_hwmod,
2267 .clk = "mmchs1_ick", 1991 .clk = "mmchs1_ick",
2268 .addr = omap2430_mmc1_addr_space,
2269 .user = OCP_USER_MPU | OCP_USER_SDMA, 1992 .user = OCP_USER_MPU | OCP_USER_SDMA,
2270 .flags = OMAP_FIREWALL_L4 1993 .flags = OMAP_FIREWALL_L4,
2271}; 1994};
2272 1995
2273/* L4 CORE -> MMC2 interface */ 1996/* L4 CORE -> MMC2 interface */
@@ -2275,126 +1998,70 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc2 = {
2275 .master = &omap3xxx_l4_core_hwmod, 1998 .master = &omap3xxx_l4_core_hwmod,
2276 .slave = &omap3xxx_pre_es3_mmc2_hwmod, 1999 .slave = &omap3xxx_pre_es3_mmc2_hwmod,
2277 .clk = "mmchs2_ick", 2000 .clk = "mmchs2_ick",
2278 .addr = omap2430_mmc2_addr_space,
2279 .user = OCP_USER_MPU | OCP_USER_SDMA, 2001 .user = OCP_USER_MPU | OCP_USER_SDMA,
2280 .flags = OMAP_FIREWALL_L4 2002 .flags = OMAP_FIREWALL_L4,
2281}; 2003};
2282 2004
2283static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc2 = { 2005static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc2 = {
2284 .master = &omap3xxx_l4_core_hwmod, 2006 .master = &omap3xxx_l4_core_hwmod,
2285 .slave = &omap3xxx_es3plus_mmc2_hwmod, 2007 .slave = &omap3xxx_es3plus_mmc2_hwmod,
2286 .clk = "mmchs2_ick", 2008 .clk = "mmchs2_ick",
2287 .addr = omap2430_mmc2_addr_space,
2288 .user = OCP_USER_MPU | OCP_USER_SDMA, 2009 .user = OCP_USER_MPU | OCP_USER_SDMA,
2289 .flags = OMAP_FIREWALL_L4 2010 .flags = OMAP_FIREWALL_L4,
2290}; 2011};
2291 2012
2292/* L4 CORE -> MMC3 interface */ 2013/* L4 CORE -> MMC3 interface */
2293static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
2294 {
2295 .pa_start = 0x480ad000,
2296 .pa_end = 0x480ad1ff,
2297 .flags = ADDR_TYPE_RT,
2298 },
2299 { }
2300};
2301 2014
2302static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = { 2015static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
2303 .master = &omap3xxx_l4_core_hwmod, 2016 .master = &omap3xxx_l4_core_hwmod,
2304 .slave = &omap3xxx_mmc3_hwmod, 2017 .slave = &omap3xxx_mmc3_hwmod,
2305 .clk = "mmchs3_ick", 2018 .clk = "mmchs3_ick",
2306 .addr = omap3xxx_mmc3_addr_space,
2307 .user = OCP_USER_MPU | OCP_USER_SDMA, 2019 .user = OCP_USER_MPU | OCP_USER_SDMA,
2308 .flags = OMAP_FIREWALL_L4 2020 .flags = OMAP_FIREWALL_L4,
2309}; 2021};
2310 2022
2311/* L4 CORE -> UART1 interface */ 2023/* L4 CORE -> UART1 interface */
2312static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
2313 {
2314 .pa_start = OMAP3_UART1_BASE,
2315 .pa_end = OMAP3_UART1_BASE + SZ_8K - 1,
2316 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2317 },
2318 { }
2319};
2320 2024
2321static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = { 2025static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
2322 .master = &omap3xxx_l4_core_hwmod, 2026 .master = &omap3xxx_l4_core_hwmod,
2323 .slave = &omap3xxx_uart1_hwmod, 2027 .slave = &omap3xxx_uart1_hwmod,
2324 .clk = "uart1_ick", 2028 .clk = "uart1_ick",
2325 .addr = omap3xxx_uart1_addr_space,
2326 .user = OCP_USER_MPU | OCP_USER_SDMA, 2029 .user = OCP_USER_MPU | OCP_USER_SDMA,
2327}; 2030};
2328 2031
2329/* L4 CORE -> UART2 interface */ 2032/* L4 CORE -> UART2 interface */
2330static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
2331 {
2332 .pa_start = OMAP3_UART2_BASE,
2333 .pa_end = OMAP3_UART2_BASE + SZ_1K - 1,
2334 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2335 },
2336 { }
2337};
2338 2033
2339static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = { 2034static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
2340 .master = &omap3xxx_l4_core_hwmod, 2035 .master = &omap3xxx_l4_core_hwmod,
2341 .slave = &omap3xxx_uart2_hwmod, 2036 .slave = &omap3xxx_uart2_hwmod,
2342 .clk = "uart2_ick", 2037 .clk = "uart2_ick",
2343 .addr = omap3xxx_uart2_addr_space,
2344 .user = OCP_USER_MPU | OCP_USER_SDMA, 2038 .user = OCP_USER_MPU | OCP_USER_SDMA,
2345}; 2039};
2346 2040
2347/* L4 PER -> UART3 interface */ 2041/* L4 PER -> UART3 interface */
2348static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
2349 {
2350 .pa_start = OMAP3_UART3_BASE,
2351 .pa_end = OMAP3_UART3_BASE + SZ_1K - 1,
2352 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2353 },
2354 { }
2355};
2356 2042
2357static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = { 2043static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
2358 .master = &omap3xxx_l4_per_hwmod, 2044 .master = &omap3xxx_l4_per_hwmod,
2359 .slave = &omap3xxx_uart3_hwmod, 2045 .slave = &omap3xxx_uart3_hwmod,
2360 .clk = "uart3_ick", 2046 .clk = "uart3_ick",
2361 .addr = omap3xxx_uart3_addr_space,
2362 .user = OCP_USER_MPU | OCP_USER_SDMA, 2047 .user = OCP_USER_MPU | OCP_USER_SDMA,
2363}; 2048};
2364 2049
2365/* L4 PER -> UART4 interface */ 2050/* L4 PER -> UART4 interface */
2366static struct omap_hwmod_addr_space omap36xx_uart4_addr_space[] = {
2367 {
2368 .pa_start = OMAP3_UART4_BASE,
2369 .pa_end = OMAP3_UART4_BASE + SZ_1K - 1,
2370 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2371 },
2372 { }
2373};
2374 2051
2375static struct omap_hwmod_ocp_if omap36xx_l4_per__uart4 = { 2052static struct omap_hwmod_ocp_if omap36xx_l4_per__uart4 = {
2376 .master = &omap3xxx_l4_per_hwmod, 2053 .master = &omap3xxx_l4_per_hwmod,
2377 .slave = &omap36xx_uart4_hwmod, 2054 .slave = &omap36xx_uart4_hwmod,
2378 .clk = "uart4_ick", 2055 .clk = "uart4_ick",
2379 .addr = omap36xx_uart4_addr_space,
2380 .user = OCP_USER_MPU | OCP_USER_SDMA, 2056 .user = OCP_USER_MPU | OCP_USER_SDMA,
2381}; 2057};
2382 2058
2383/* AM35xx: L4 CORE -> UART4 interface */ 2059/* AM35xx: L4 CORE -> UART4 interface */
2384static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = {
2385 {
2386 .pa_start = OMAP3_UART4_AM35XX_BASE,
2387 .pa_end = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1,
2388 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2389 },
2390 { }
2391};
2392 2060
2393static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = { 2061static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = {
2394 .master = &omap3xxx_l4_core_hwmod, 2062 .master = &omap3xxx_l4_core_hwmod,
2395 .slave = &am35xx_uart4_hwmod, 2063 .slave = &am35xx_uart4_hwmod,
2396 .clk = "uart4_ick", 2064 .clk = "uart4_ick",
2397 .addr = am35xx_uart4_addr_space,
2398 .user = OCP_USER_MPU | OCP_USER_SDMA, 2065 .user = OCP_USER_MPU | OCP_USER_SDMA,
2399}; 2066};
2400 2067
@@ -2403,13 +2070,12 @@ static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
2403 .master = &omap3xxx_l4_core_hwmod, 2070 .master = &omap3xxx_l4_core_hwmod,
2404 .slave = &omap3xxx_i2c1_hwmod, 2071 .slave = &omap3xxx_i2c1_hwmod,
2405 .clk = "i2c1_ick", 2072 .clk = "i2c1_ick",
2406 .addr = omap2_i2c1_addr_space,
2407 .fw = { 2073 .fw = {
2408 .omap2 = { 2074 .omap2 = {
2409 .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION, 2075 .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION,
2410 .l4_prot_group = 7, 2076 .l4_prot_group = 7,
2411 .flags = OMAP_FIREWALL_L4, 2077 .flags = OMAP_FIREWALL_L4,
2412 } 2078 },
2413 }, 2079 },
2414 .user = OCP_USER_MPU | OCP_USER_SDMA, 2080 .user = OCP_USER_MPU | OCP_USER_SDMA,
2415}; 2081};
@@ -2419,57 +2085,38 @@ static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
2419 .master = &omap3xxx_l4_core_hwmod, 2085 .master = &omap3xxx_l4_core_hwmod,
2420 .slave = &omap3xxx_i2c2_hwmod, 2086 .slave = &omap3xxx_i2c2_hwmod,
2421 .clk = "i2c2_ick", 2087 .clk = "i2c2_ick",
2422 .addr = omap2_i2c2_addr_space,
2423 .fw = { 2088 .fw = {
2424 .omap2 = { 2089 .omap2 = {
2425 .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION, 2090 .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION,
2426 .l4_prot_group = 7, 2091 .l4_prot_group = 7,
2427 .flags = OMAP_FIREWALL_L4, 2092 .flags = OMAP_FIREWALL_L4,
2428 } 2093 },
2429 }, 2094 },
2430 .user = OCP_USER_MPU | OCP_USER_SDMA, 2095 .user = OCP_USER_MPU | OCP_USER_SDMA,
2431}; 2096};
2432 2097
2433/* L4 CORE -> I2C3 interface */ 2098/* L4 CORE -> I2C3 interface */
2434static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
2435 {
2436 .pa_start = 0x48060000,
2437 .pa_end = 0x48060000 + SZ_128 - 1,
2438 .flags = ADDR_TYPE_RT,
2439 },
2440 { }
2441};
2442 2099
2443static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = { 2100static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
2444 .master = &omap3xxx_l4_core_hwmod, 2101 .master = &omap3xxx_l4_core_hwmod,
2445 .slave = &omap3xxx_i2c3_hwmod, 2102 .slave = &omap3xxx_i2c3_hwmod,
2446 .clk = "i2c3_ick", 2103 .clk = "i2c3_ick",
2447 .addr = omap3xxx_i2c3_addr_space,
2448 .fw = { 2104 .fw = {
2449 .omap2 = { 2105 .omap2 = {
2450 .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION, 2106 .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION,
2451 .l4_prot_group = 7, 2107 .l4_prot_group = 7,
2452 .flags = OMAP_FIREWALL_L4, 2108 .flags = OMAP_FIREWALL_L4,
2453 } 2109 },
2454 }, 2110 },
2455 .user = OCP_USER_MPU | OCP_USER_SDMA, 2111 .user = OCP_USER_MPU | OCP_USER_SDMA,
2456}; 2112};
2457 2113
2458/* L4 CORE -> SR1 interface */ 2114/* L4 CORE -> SR1 interface */
2459static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
2460 {
2461 .pa_start = OMAP34XX_SR1_BASE,
2462 .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1,
2463 .flags = ADDR_TYPE_RT,
2464 },
2465 { }
2466};
2467 2115
2468static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1 = { 2116static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1 = {
2469 .master = &omap3xxx_l4_core_hwmod, 2117 .master = &omap3xxx_l4_core_hwmod,
2470 .slave = &omap34xx_sr1_hwmod, 2118 .slave = &omap34xx_sr1_hwmod,
2471 .clk = "sr_l4_ick", 2119 .clk = "sr_l4_ick",
2472 .addr = omap3_sr1_addr_space,
2473 .user = OCP_USER_MPU, 2120 .user = OCP_USER_MPU,
2474}; 2121};
2475 2122
@@ -2477,25 +2124,15 @@ static struct omap_hwmod_ocp_if omap36xx_l4_core__sr1 = {
2477 .master = &omap3xxx_l4_core_hwmod, 2124 .master = &omap3xxx_l4_core_hwmod,
2478 .slave = &omap36xx_sr1_hwmod, 2125 .slave = &omap36xx_sr1_hwmod,
2479 .clk = "sr_l4_ick", 2126 .clk = "sr_l4_ick",
2480 .addr = omap3_sr1_addr_space,
2481 .user = OCP_USER_MPU, 2127 .user = OCP_USER_MPU,
2482}; 2128};
2483 2129
2484/* L4 CORE -> SR1 interface */ 2130/* L4 CORE -> SR1 interface */
2485static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
2486 {
2487 .pa_start = OMAP34XX_SR2_BASE,
2488 .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1,
2489 .flags = ADDR_TYPE_RT,
2490 },
2491 { }
2492};
2493 2131
2494static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2 = { 2132static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2 = {
2495 .master = &omap3xxx_l4_core_hwmod, 2133 .master = &omap3xxx_l4_core_hwmod,
2496 .slave = &omap34xx_sr2_hwmod, 2134 .slave = &omap34xx_sr2_hwmod,
2497 .clk = "sr_l4_ick", 2135 .clk = "sr_l4_ick",
2498 .addr = omap3_sr2_addr_space,
2499 .user = OCP_USER_MPU, 2136 .user = OCP_USER_MPU,
2500}; 2137};
2501 2138
@@ -2503,43 +2140,24 @@ static struct omap_hwmod_ocp_if omap36xx_l4_core__sr2 = {
2503 .master = &omap3xxx_l4_core_hwmod, 2140 .master = &omap3xxx_l4_core_hwmod,
2504 .slave = &omap36xx_sr2_hwmod, 2141 .slave = &omap36xx_sr2_hwmod,
2505 .clk = "sr_l4_ick", 2142 .clk = "sr_l4_ick",
2506 .addr = omap3_sr2_addr_space,
2507 .user = OCP_USER_MPU, 2143 .user = OCP_USER_MPU,
2508}; 2144};
2509 2145
2510static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
2511 {
2512 .pa_start = OMAP34XX_HSUSB_OTG_BASE,
2513 .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
2514 .flags = ADDR_TYPE_RT
2515 },
2516 { }
2517};
2518 2146
2519/* l4_core -> usbhsotg */ 2147/* l4_core -> usbhsotg */
2520static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = { 2148static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
2521 .master = &omap3xxx_l4_core_hwmod, 2149 .master = &omap3xxx_l4_core_hwmod,
2522 .slave = &omap3xxx_usbhsotg_hwmod, 2150 .slave = &omap3xxx_usbhsotg_hwmod,
2523 .clk = "l4_ick", 2151 .clk = "l4_ick",
2524 .addr = omap3xxx_usbhsotg_addrs,
2525 .user = OCP_USER_MPU, 2152 .user = OCP_USER_MPU,
2526}; 2153};
2527 2154
2528static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
2529 {
2530 .pa_start = AM35XX_IPSS_USBOTGSS_BASE,
2531 .pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
2532 .flags = ADDR_TYPE_RT
2533 },
2534 { }
2535};
2536 2155
2537/* l4_core -> usbhsotg */ 2156/* l4_core -> usbhsotg */
2538static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = { 2157static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
2539 .master = &omap3xxx_l4_core_hwmod, 2158 .master = &omap3xxx_l4_core_hwmod,
2540 .slave = &am35xx_usbhsotg_hwmod, 2159 .slave = &am35xx_usbhsotg_hwmod,
2541 .clk = "hsotgusb_ick", 2160 .clk = "hsotgusb_ick",
2542 .addr = am35xx_usbhsotg_addrs,
2543 .user = OCP_USER_MPU, 2161 .user = OCP_USER_MPU,
2544}; 2162};
2545 2163
@@ -2558,165 +2176,84 @@ static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
2558 .user = OCP_USER_MPU | OCP_USER_SDMA, 2176 .user = OCP_USER_MPU | OCP_USER_SDMA,
2559}; 2177};
2560 2178
2561static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
2562 {
2563 .pa_start = 0x48318000,
2564 .pa_end = 0x48318000 + SZ_1K - 1,
2565 .flags = ADDR_TYPE_RT
2566 },
2567 { }
2568};
2569 2179
2570/* l4_wkup -> timer1 */ 2180/* l4_wkup -> timer1 */
2571static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = { 2181static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
2572 .master = &omap3xxx_l4_wkup_hwmod, 2182 .master = &omap3xxx_l4_wkup_hwmod,
2573 .slave = &omap3xxx_timer1_hwmod, 2183 .slave = &omap3xxx_timer1_hwmod,
2574 .clk = "gpt1_ick", 2184 .clk = "gpt1_ick",
2575 .addr = omap3xxx_timer1_addrs,
2576 .user = OCP_USER_MPU | OCP_USER_SDMA, 2185 .user = OCP_USER_MPU | OCP_USER_SDMA,
2577}; 2186};
2578 2187
2579static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
2580 {
2581 .pa_start = 0x49032000,
2582 .pa_end = 0x49032000 + SZ_1K - 1,
2583 .flags = ADDR_TYPE_RT
2584 },
2585 { }
2586};
2587 2188
2588/* l4_per -> timer2 */ 2189/* l4_per -> timer2 */
2589static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = { 2190static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
2590 .master = &omap3xxx_l4_per_hwmod, 2191 .master = &omap3xxx_l4_per_hwmod,
2591 .slave = &omap3xxx_timer2_hwmod, 2192 .slave = &omap3xxx_timer2_hwmod,
2592 .clk = "gpt2_ick", 2193 .clk = "gpt2_ick",
2593 .addr = omap3xxx_timer2_addrs,
2594 .user = OCP_USER_MPU | OCP_USER_SDMA, 2194 .user = OCP_USER_MPU | OCP_USER_SDMA,
2595}; 2195};
2596 2196
2597static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
2598 {
2599 .pa_start = 0x49034000,
2600 .pa_end = 0x49034000 + SZ_1K - 1,
2601 .flags = ADDR_TYPE_RT
2602 },
2603 { }
2604};
2605 2197
2606/* l4_per -> timer3 */ 2198/* l4_per -> timer3 */
2607static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = { 2199static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
2608 .master = &omap3xxx_l4_per_hwmod, 2200 .master = &omap3xxx_l4_per_hwmod,
2609 .slave = &omap3xxx_timer3_hwmod, 2201 .slave = &omap3xxx_timer3_hwmod,
2610 .clk = "gpt3_ick", 2202 .clk = "gpt3_ick",
2611 .addr = omap3xxx_timer3_addrs,
2612 .user = OCP_USER_MPU | OCP_USER_SDMA, 2203 .user = OCP_USER_MPU | OCP_USER_SDMA,
2613}; 2204};
2614 2205
2615static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
2616 {
2617 .pa_start = 0x49036000,
2618 .pa_end = 0x49036000 + SZ_1K - 1,
2619 .flags = ADDR_TYPE_RT
2620 },
2621 { }
2622};
2623 2206
2624/* l4_per -> timer4 */ 2207/* l4_per -> timer4 */
2625static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = { 2208static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
2626 .master = &omap3xxx_l4_per_hwmod, 2209 .master = &omap3xxx_l4_per_hwmod,
2627 .slave = &omap3xxx_timer4_hwmod, 2210 .slave = &omap3xxx_timer4_hwmod,
2628 .clk = "gpt4_ick", 2211 .clk = "gpt4_ick",
2629 .addr = omap3xxx_timer4_addrs,
2630 .user = OCP_USER_MPU | OCP_USER_SDMA, 2212 .user = OCP_USER_MPU | OCP_USER_SDMA,
2631}; 2213};
2632 2214
2633static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
2634 {
2635 .pa_start = 0x49038000,
2636 .pa_end = 0x49038000 + SZ_1K - 1,
2637 .flags = ADDR_TYPE_RT
2638 },
2639 { }
2640};
2641 2215
2642/* l4_per -> timer5 */ 2216/* l4_per -> timer5 */
2643static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = { 2217static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
2644 .master = &omap3xxx_l4_per_hwmod, 2218 .master = &omap3xxx_l4_per_hwmod,
2645 .slave = &omap3xxx_timer5_hwmod, 2219 .slave = &omap3xxx_timer5_hwmod,
2646 .clk = "gpt5_ick", 2220 .clk = "gpt5_ick",
2647 .addr = omap3xxx_timer5_addrs,
2648 .user = OCP_USER_MPU | OCP_USER_SDMA, 2221 .user = OCP_USER_MPU | OCP_USER_SDMA,
2649}; 2222};
2650 2223
2651static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
2652 {
2653 .pa_start = 0x4903A000,
2654 .pa_end = 0x4903A000 + SZ_1K - 1,
2655 .flags = ADDR_TYPE_RT
2656 },
2657 { }
2658};
2659 2224
2660/* l4_per -> timer6 */ 2225/* l4_per -> timer6 */
2661static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = { 2226static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
2662 .master = &omap3xxx_l4_per_hwmod, 2227 .master = &omap3xxx_l4_per_hwmod,
2663 .slave = &omap3xxx_timer6_hwmod, 2228 .slave = &omap3xxx_timer6_hwmod,
2664 .clk = "gpt6_ick", 2229 .clk = "gpt6_ick",
2665 .addr = omap3xxx_timer6_addrs,
2666 .user = OCP_USER_MPU | OCP_USER_SDMA, 2230 .user = OCP_USER_MPU | OCP_USER_SDMA,
2667}; 2231};
2668 2232
2669static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
2670 {
2671 .pa_start = 0x4903C000,
2672 .pa_end = 0x4903C000 + SZ_1K - 1,
2673 .flags = ADDR_TYPE_RT
2674 },
2675 { }
2676};
2677 2233
2678/* l4_per -> timer7 */ 2234/* l4_per -> timer7 */
2679static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = { 2235static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
2680 .master = &omap3xxx_l4_per_hwmod, 2236 .master = &omap3xxx_l4_per_hwmod,
2681 .slave = &omap3xxx_timer7_hwmod, 2237 .slave = &omap3xxx_timer7_hwmod,
2682 .clk = "gpt7_ick", 2238 .clk = "gpt7_ick",
2683 .addr = omap3xxx_timer7_addrs,
2684 .user = OCP_USER_MPU | OCP_USER_SDMA, 2239 .user = OCP_USER_MPU | OCP_USER_SDMA,
2685}; 2240};
2686 2241
2687static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
2688 {
2689 .pa_start = 0x4903E000,
2690 .pa_end = 0x4903E000 + SZ_1K - 1,
2691 .flags = ADDR_TYPE_RT
2692 },
2693 { }
2694};
2695 2242
2696/* l4_per -> timer8 */ 2243/* l4_per -> timer8 */
2697static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = { 2244static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
2698 .master = &omap3xxx_l4_per_hwmod, 2245 .master = &omap3xxx_l4_per_hwmod,
2699 .slave = &omap3xxx_timer8_hwmod, 2246 .slave = &omap3xxx_timer8_hwmod,
2700 .clk = "gpt8_ick", 2247 .clk = "gpt8_ick",
2701 .addr = omap3xxx_timer8_addrs,
2702 .user = OCP_USER_MPU | OCP_USER_SDMA, 2248 .user = OCP_USER_MPU | OCP_USER_SDMA,
2703}; 2249};
2704 2250
2705static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
2706 {
2707 .pa_start = 0x49040000,
2708 .pa_end = 0x49040000 + SZ_1K - 1,
2709 .flags = ADDR_TYPE_RT
2710 },
2711 { }
2712};
2713 2251
2714/* l4_per -> timer9 */ 2252/* l4_per -> timer9 */
2715static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = { 2253static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
2716 .master = &omap3xxx_l4_per_hwmod, 2254 .master = &omap3xxx_l4_per_hwmod,
2717 .slave = &omap3xxx_timer9_hwmod, 2255 .slave = &omap3xxx_timer9_hwmod,
2718 .clk = "gpt9_ick", 2256 .clk = "gpt9_ick",
2719 .addr = omap3xxx_timer9_addrs,
2720 .user = OCP_USER_MPU | OCP_USER_SDMA, 2257 .user = OCP_USER_MPU | OCP_USER_SDMA,
2721}; 2258};
2722 2259
@@ -2725,7 +2262,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
2725 .master = &omap3xxx_l4_core_hwmod, 2262 .master = &omap3xxx_l4_core_hwmod,
2726 .slave = &omap3xxx_timer10_hwmod, 2263 .slave = &omap3xxx_timer10_hwmod,
2727 .clk = "gpt10_ick", 2264 .clk = "gpt10_ick",
2728 .addr = omap2_timer10_addrs,
2729 .user = OCP_USER_MPU | OCP_USER_SDMA, 2265 .user = OCP_USER_MPU | OCP_USER_SDMA,
2730}; 2266};
2731 2267
@@ -2734,43 +2270,24 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
2734 .master = &omap3xxx_l4_core_hwmod, 2270 .master = &omap3xxx_l4_core_hwmod,
2735 .slave = &omap3xxx_timer11_hwmod, 2271 .slave = &omap3xxx_timer11_hwmod,
2736 .clk = "gpt11_ick", 2272 .clk = "gpt11_ick",
2737 .addr = omap2_timer11_addrs,
2738 .user = OCP_USER_MPU | OCP_USER_SDMA, 2273 .user = OCP_USER_MPU | OCP_USER_SDMA,
2739}; 2274};
2740 2275
2741static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
2742 {
2743 .pa_start = 0x48304000,
2744 .pa_end = 0x48304000 + SZ_1K - 1,
2745 .flags = ADDR_TYPE_RT
2746 },
2747 { }
2748};
2749 2276
2750/* l4_core -> timer12 */ 2277/* l4_core -> timer12 */
2751static struct omap_hwmod_ocp_if omap3xxx_l4_sec__timer12 = { 2278static struct omap_hwmod_ocp_if omap3xxx_l4_sec__timer12 = {
2752 .master = &omap3xxx_l4_sec_hwmod, 2279 .master = &omap3xxx_l4_sec_hwmod,
2753 .slave = &omap3xxx_timer12_hwmod, 2280 .slave = &omap3xxx_timer12_hwmod,
2754 .clk = "gpt12_ick", 2281 .clk = "gpt12_ick",
2755 .addr = omap3xxx_timer12_addrs,
2756 .user = OCP_USER_MPU | OCP_USER_SDMA, 2282 .user = OCP_USER_MPU | OCP_USER_SDMA,
2757}; 2283};
2758 2284
2759/* l4_wkup -> wd_timer2 */ 2285/* l4_wkup -> wd_timer2 */
2760static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
2761 {
2762 .pa_start = 0x48314000,
2763 .pa_end = 0x4831407f,
2764 .flags = ADDR_TYPE_RT
2765 },
2766 { }
2767};
2768 2286
2769static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = { 2287static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
2770 .master = &omap3xxx_l4_wkup_hwmod, 2288 .master = &omap3xxx_l4_wkup_hwmod,
2771 .slave = &omap3xxx_wd_timer2_hwmod, 2289 .slave = &omap3xxx_wd_timer2_hwmod,
2772 .clk = "wdt2_ick", 2290 .clk = "wdt2_ick",
2773 .addr = omap3xxx_wd_timer2_addrs,
2774 .user = OCP_USER_MPU | OCP_USER_SDMA, 2291 .user = OCP_USER_MPU | OCP_USER_SDMA,
2775}; 2292};
2776 2293
@@ -2779,13 +2296,12 @@ static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
2779 .master = &omap3xxx_l4_core_hwmod, 2296 .master = &omap3xxx_l4_core_hwmod,
2780 .slave = &omap3430es1_dss_core_hwmod, 2297 .slave = &omap3430es1_dss_core_hwmod,
2781 .clk = "dss_ick", 2298 .clk = "dss_ick",
2782 .addr = omap2_dss_addrs,
2783 .fw = { 2299 .fw = {
2784 .omap2 = { 2300 .omap2 = {
2785 .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION, 2301 .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
2786 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, 2302 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2787 .flags = OMAP_FIREWALL_L4, 2303 .flags = OMAP_FIREWALL_L4,
2788 } 2304 },
2789 }, 2305 },
2790 .user = OCP_USER_MPU | OCP_USER_SDMA, 2306 .user = OCP_USER_MPU | OCP_USER_SDMA,
2791}; 2307};
@@ -2794,13 +2310,12 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
2794 .master = &omap3xxx_l4_core_hwmod, 2310 .master = &omap3xxx_l4_core_hwmod,
2795 .slave = &omap3xxx_dss_core_hwmod, 2311 .slave = &omap3xxx_dss_core_hwmod,
2796 .clk = "dss_ick", 2312 .clk = "dss_ick",
2797 .addr = omap2_dss_addrs,
2798 .fw = { 2313 .fw = {
2799 .omap2 = { 2314 .omap2 = {
2800 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION, 2315 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
2801 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, 2316 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2802 .flags = OMAP_FIREWALL_L4, 2317 .flags = OMAP_FIREWALL_L4,
2803 } 2318 },
2804 }, 2319 },
2805 .user = OCP_USER_MPU | OCP_USER_SDMA, 2320 .user = OCP_USER_MPU | OCP_USER_SDMA,
2806}; 2321};
@@ -2810,38 +2325,27 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
2810 .master = &omap3xxx_l4_core_hwmod, 2325 .master = &omap3xxx_l4_core_hwmod,
2811 .slave = &omap3xxx_dss_dispc_hwmod, 2326 .slave = &omap3xxx_dss_dispc_hwmod,
2812 .clk = "dss_ick", 2327 .clk = "dss_ick",
2813 .addr = omap2_dss_dispc_addrs,
2814 .fw = { 2328 .fw = {
2815 .omap2 = { 2329 .omap2 = {
2816 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION, 2330 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
2817 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, 2331 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2818 .flags = OMAP_FIREWALL_L4, 2332 .flags = OMAP_FIREWALL_L4,
2819 } 2333 },
2820 }, 2334 },
2821 .user = OCP_USER_MPU | OCP_USER_SDMA, 2335 .user = OCP_USER_MPU | OCP_USER_SDMA,
2822}; 2336};
2823 2337
2824static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
2825 {
2826 .pa_start = 0x4804FC00,
2827 .pa_end = 0x4804FFFF,
2828 .flags = ADDR_TYPE_RT
2829 },
2830 { }
2831};
2832
2833/* l4_core -> dss_dsi1 */ 2338/* l4_core -> dss_dsi1 */
2834static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = { 2339static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
2835 .master = &omap3xxx_l4_core_hwmod, 2340 .master = &omap3xxx_l4_core_hwmod,
2836 .slave = &omap3xxx_dss_dsi1_hwmod, 2341 .slave = &omap3xxx_dss_dsi1_hwmod,
2837 .clk = "dss_ick", 2342 .clk = "dss_ick",
2838 .addr = omap3xxx_dss_dsi1_addrs,
2839 .fw = { 2343 .fw = {
2840 .omap2 = { 2344 .omap2 = {
2841 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION, 2345 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
2842 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, 2346 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2843 .flags = OMAP_FIREWALL_L4, 2347 .flags = OMAP_FIREWALL_L4,
2844 } 2348 },
2845 }, 2349 },
2846 .user = OCP_USER_MPU | OCP_USER_SDMA, 2350 .user = OCP_USER_MPU | OCP_USER_SDMA,
2847}; 2351};
@@ -2851,13 +2355,12 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
2851 .master = &omap3xxx_l4_core_hwmod, 2355 .master = &omap3xxx_l4_core_hwmod,
2852 .slave = &omap3xxx_dss_rfbi_hwmod, 2356 .slave = &omap3xxx_dss_rfbi_hwmod,
2853 .clk = "dss_ick", 2357 .clk = "dss_ick",
2854 .addr = omap2_dss_rfbi_addrs,
2855 .fw = { 2358 .fw = {
2856 .omap2 = { 2359 .omap2 = {
2857 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION, 2360 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
2858 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP , 2361 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
2859 .flags = OMAP_FIREWALL_L4, 2362 .flags = OMAP_FIREWALL_L4,
2860 } 2363 },
2861 }, 2364 },
2862 .user = OCP_USER_MPU | OCP_USER_SDMA, 2365 .user = OCP_USER_MPU | OCP_USER_SDMA,
2863}; 2366};
@@ -2867,66 +2370,38 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
2867 .master = &omap3xxx_l4_core_hwmod, 2370 .master = &omap3xxx_l4_core_hwmod,
2868 .slave = &omap3xxx_dss_venc_hwmod, 2371 .slave = &omap3xxx_dss_venc_hwmod,
2869 .clk = "dss_ick", 2372 .clk = "dss_ick",
2870 .addr = omap2_dss_venc_addrs,
2871 .fw = { 2373 .fw = {
2872 .omap2 = { 2374 .omap2 = {
2873 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION, 2375 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
2874 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, 2376 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2875 .flags = OMAP_FIREWALL_L4, 2377 .flags = OMAP_FIREWALL_L4,
2876 } 2378 },
2877 }, 2379 },
2878 .flags = OCPIF_SWSUP_IDLE, 2380 .flags = OCPIF_SWSUP_IDLE,
2879 .user = OCP_USER_MPU | OCP_USER_SDMA, 2381 .user = OCP_USER_MPU | OCP_USER_SDMA,
2880}; 2382};
2881 2383
2882/* l4_wkup -> gpio1 */ 2384/* l4_wkup -> gpio1 */
2883static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
2884 {
2885 .pa_start = 0x48310000,
2886 .pa_end = 0x483101ff,
2887 .flags = ADDR_TYPE_RT
2888 },
2889 { }
2890};
2891 2385
2892static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = { 2386static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
2893 .master = &omap3xxx_l4_wkup_hwmod, 2387 .master = &omap3xxx_l4_wkup_hwmod,
2894 .slave = &omap3xxx_gpio1_hwmod, 2388 .slave = &omap3xxx_gpio1_hwmod,
2895 .addr = omap3xxx_gpio1_addrs,
2896 .user = OCP_USER_MPU | OCP_USER_SDMA, 2389 .user = OCP_USER_MPU | OCP_USER_SDMA,
2897}; 2390};
2898 2391
2899/* l4_per -> gpio2 */ 2392/* l4_per -> gpio2 */
2900static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
2901 {
2902 .pa_start = 0x49050000,
2903 .pa_end = 0x490501ff,
2904 .flags = ADDR_TYPE_RT
2905 },
2906 { }
2907};
2908 2393
2909static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = { 2394static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
2910 .master = &omap3xxx_l4_per_hwmod, 2395 .master = &omap3xxx_l4_per_hwmod,
2911 .slave = &omap3xxx_gpio2_hwmod, 2396 .slave = &omap3xxx_gpio2_hwmod,
2912 .addr = omap3xxx_gpio2_addrs,
2913 .user = OCP_USER_MPU | OCP_USER_SDMA, 2397 .user = OCP_USER_MPU | OCP_USER_SDMA,
2914}; 2398};
2915 2399
2916/* l4_per -> gpio3 */ 2400/* l4_per -> gpio3 */
2917static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
2918 {
2919 .pa_start = 0x49052000,
2920 .pa_end = 0x490521ff,
2921 .flags = ADDR_TYPE_RT
2922 },
2923 { }
2924};
2925 2401
2926static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = { 2402static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
2927 .master = &omap3xxx_l4_per_hwmod, 2403 .master = &omap3xxx_l4_per_hwmod,
2928 .slave = &omap3xxx_gpio3_hwmod, 2404 .slave = &omap3xxx_gpio3_hwmod,
2929 .addr = omap3xxx_gpio3_addrs,
2930 .user = OCP_USER_MPU | OCP_USER_SDMA, 2405 .user = OCP_USER_MPU | OCP_USER_SDMA,
2931}; 2406};
2932 2407
@@ -3002,53 +2477,26 @@ static struct omap_hwmod omap3xxx_mmu_iva_hwmod = {
3002}; 2477};
3003 2478
3004/* l4_per -> gpio4 */ 2479/* l4_per -> gpio4 */
3005static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
3006 {
3007 .pa_start = 0x49054000,
3008 .pa_end = 0x490541ff,
3009 .flags = ADDR_TYPE_RT
3010 },
3011 { }
3012};
3013 2480
3014static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = { 2481static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
3015 .master = &omap3xxx_l4_per_hwmod, 2482 .master = &omap3xxx_l4_per_hwmod,
3016 .slave = &omap3xxx_gpio4_hwmod, 2483 .slave = &omap3xxx_gpio4_hwmod,
3017 .addr = omap3xxx_gpio4_addrs,
3018 .user = OCP_USER_MPU | OCP_USER_SDMA, 2484 .user = OCP_USER_MPU | OCP_USER_SDMA,
3019}; 2485};
3020 2486
3021/* l4_per -> gpio5 */ 2487/* l4_per -> gpio5 */
3022static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
3023 {
3024 .pa_start = 0x49056000,
3025 .pa_end = 0x490561ff,
3026 .flags = ADDR_TYPE_RT
3027 },
3028 { }
3029};
3030 2488
3031static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = { 2489static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
3032 .master = &omap3xxx_l4_per_hwmod, 2490 .master = &omap3xxx_l4_per_hwmod,
3033 .slave = &omap3xxx_gpio5_hwmod, 2491 .slave = &omap3xxx_gpio5_hwmod,
3034 .addr = omap3xxx_gpio5_addrs,
3035 .user = OCP_USER_MPU | OCP_USER_SDMA, 2492 .user = OCP_USER_MPU | OCP_USER_SDMA,
3036}; 2493};
3037 2494
3038/* l4_per -> gpio6 */ 2495/* l4_per -> gpio6 */
3039static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
3040 {
3041 .pa_start = 0x49058000,
3042 .pa_end = 0x490581ff,
3043 .flags = ADDR_TYPE_RT
3044 },
3045 { }
3046};
3047 2496
3048static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = { 2497static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
3049 .master = &omap3xxx_l4_per_hwmod, 2498 .master = &omap3xxx_l4_per_hwmod,
3050 .slave = &omap3xxx_gpio6_hwmod, 2499 .slave = &omap3xxx_gpio6_hwmod,
3051 .addr = omap3xxx_gpio6_addrs,
3052 .user = OCP_USER_MPU | OCP_USER_SDMA, 2500 .user = OCP_USER_MPU | OCP_USER_SDMA,
3053}; 2501};
3054 2502
@@ -3064,9 +2512,9 @@ static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
3064 { 2512 {
3065 .pa_start = 0x48056000, 2513 .pa_start = 0x48056000,
3066 .pa_end = 0x48056fff, 2514 .pa_end = 0x48056fff,
3067 .flags = ADDR_TYPE_RT 2515 .flags = ADDR_TYPE_RT,
3068 }, 2516 },
3069 { } 2517 { },
3070}; 2518};
3071 2519
3072/* l4_cfg -> dma_system */ 2520/* l4_cfg -> dma_system */
@@ -3078,136 +2526,66 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
3078 .user = OCP_USER_MPU | OCP_USER_SDMA, 2526 .user = OCP_USER_MPU | OCP_USER_SDMA,
3079}; 2527};
3080 2528
3081static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
3082 {
3083 .name = "mpu",
3084 .pa_start = 0x48074000,
3085 .pa_end = 0x480740ff,
3086 .flags = ADDR_TYPE_RT
3087 },
3088 { }
3089};
3090 2529
3091/* l4_core -> mcbsp1 */ 2530/* l4_core -> mcbsp1 */
3092static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = { 2531static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
3093 .master = &omap3xxx_l4_core_hwmod, 2532 .master = &omap3xxx_l4_core_hwmod,
3094 .slave = &omap3xxx_mcbsp1_hwmod, 2533 .slave = &omap3xxx_mcbsp1_hwmod,
3095 .clk = "mcbsp1_ick", 2534 .clk = "mcbsp1_ick",
3096 .addr = omap3xxx_mcbsp1_addrs,
3097 .user = OCP_USER_MPU | OCP_USER_SDMA, 2535 .user = OCP_USER_MPU | OCP_USER_SDMA,
3098}; 2536};
3099 2537
3100static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
3101 {
3102 .name = "mpu",
3103 .pa_start = 0x49022000,
3104 .pa_end = 0x490220ff,
3105 .flags = ADDR_TYPE_RT
3106 },
3107 { }
3108};
3109 2538
3110/* l4_per -> mcbsp2 */ 2539/* l4_per -> mcbsp2 */
3111static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = { 2540static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
3112 .master = &omap3xxx_l4_per_hwmod, 2541 .master = &omap3xxx_l4_per_hwmod,
3113 .slave = &omap3xxx_mcbsp2_hwmod, 2542 .slave = &omap3xxx_mcbsp2_hwmod,
3114 .clk = "mcbsp2_ick", 2543 .clk = "mcbsp2_ick",
3115 .addr = omap3xxx_mcbsp2_addrs,
3116 .user = OCP_USER_MPU | OCP_USER_SDMA, 2544 .user = OCP_USER_MPU | OCP_USER_SDMA,
3117}; 2545};
3118 2546
3119static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
3120 {
3121 .name = "mpu",
3122 .pa_start = 0x49024000,
3123 .pa_end = 0x490240ff,
3124 .flags = ADDR_TYPE_RT
3125 },
3126 { }
3127};
3128 2547
3129/* l4_per -> mcbsp3 */ 2548/* l4_per -> mcbsp3 */
3130static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = { 2549static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
3131 .master = &omap3xxx_l4_per_hwmod, 2550 .master = &omap3xxx_l4_per_hwmod,
3132 .slave = &omap3xxx_mcbsp3_hwmod, 2551 .slave = &omap3xxx_mcbsp3_hwmod,
3133 .clk = "mcbsp3_ick", 2552 .clk = "mcbsp3_ick",
3134 .addr = omap3xxx_mcbsp3_addrs,
3135 .user = OCP_USER_MPU | OCP_USER_SDMA, 2553 .user = OCP_USER_MPU | OCP_USER_SDMA,
3136}; 2554};
3137 2555
3138static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
3139 {
3140 .name = "mpu",
3141 .pa_start = 0x49026000,
3142 .pa_end = 0x490260ff,
3143 .flags = ADDR_TYPE_RT
3144 },
3145 { }
3146};
3147 2556
3148/* l4_per -> mcbsp4 */ 2557/* l4_per -> mcbsp4 */
3149static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = { 2558static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
3150 .master = &omap3xxx_l4_per_hwmod, 2559 .master = &omap3xxx_l4_per_hwmod,
3151 .slave = &omap3xxx_mcbsp4_hwmod, 2560 .slave = &omap3xxx_mcbsp4_hwmod,
3152 .clk = "mcbsp4_ick", 2561 .clk = "mcbsp4_ick",
3153 .addr = omap3xxx_mcbsp4_addrs,
3154 .user = OCP_USER_MPU | OCP_USER_SDMA, 2562 .user = OCP_USER_MPU | OCP_USER_SDMA,
3155}; 2563};
3156 2564
3157static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
3158 {
3159 .name = "mpu",
3160 .pa_start = 0x48096000,
3161 .pa_end = 0x480960ff,
3162 .flags = ADDR_TYPE_RT
3163 },
3164 { }
3165};
3166 2565
3167/* l4_core -> mcbsp5 */ 2566/* l4_core -> mcbsp5 */
3168static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = { 2567static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
3169 .master = &omap3xxx_l4_core_hwmod, 2568 .master = &omap3xxx_l4_core_hwmod,
3170 .slave = &omap3xxx_mcbsp5_hwmod, 2569 .slave = &omap3xxx_mcbsp5_hwmod,
3171 .clk = "mcbsp5_ick", 2570 .clk = "mcbsp5_ick",
3172 .addr = omap3xxx_mcbsp5_addrs,
3173 .user = OCP_USER_MPU | OCP_USER_SDMA, 2571 .user = OCP_USER_MPU | OCP_USER_SDMA,
3174}; 2572};
3175 2573
3176static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
3177 {
3178 .name = "sidetone",
3179 .pa_start = 0x49028000,
3180 .pa_end = 0x490280ff,
3181 .flags = ADDR_TYPE_RT
3182 },
3183 { }
3184};
3185 2574
3186/* l4_per -> mcbsp2_sidetone */ 2575/* l4_per -> mcbsp2_sidetone */
3187static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = { 2576static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
3188 .master = &omap3xxx_l4_per_hwmod, 2577 .master = &omap3xxx_l4_per_hwmod,
3189 .slave = &omap3xxx_mcbsp2_sidetone_hwmod, 2578 .slave = &omap3xxx_mcbsp2_sidetone_hwmod,
3190 .clk = "mcbsp2_ick", 2579 .clk = "mcbsp2_ick",
3191 .addr = omap3xxx_mcbsp2_sidetone_addrs,
3192 .user = OCP_USER_MPU, 2580 .user = OCP_USER_MPU,
3193}; 2581};
3194 2582
3195static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
3196 {
3197 .name = "sidetone",
3198 .pa_start = 0x4902A000,
3199 .pa_end = 0x4902A0ff,
3200 .flags = ADDR_TYPE_RT
3201 },
3202 { }
3203};
3204 2583
3205/* l4_per -> mcbsp3_sidetone */ 2584/* l4_per -> mcbsp3_sidetone */
3206static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = { 2585static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
3207 .master = &omap3xxx_l4_per_hwmod, 2586 .master = &omap3xxx_l4_per_hwmod,
3208 .slave = &omap3xxx_mcbsp3_sidetone_hwmod, 2587 .slave = &omap3xxx_mcbsp3_sidetone_hwmod,
3209 .clk = "mcbsp3_ick", 2588 .clk = "mcbsp3_ick",
3210 .addr = omap3xxx_mcbsp3_sidetone_addrs,
3211 .user = OCP_USER_MPU, 2589 .user = OCP_USER_MPU,
3212}; 2590};
3213 2591
@@ -3223,7 +2601,6 @@ static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
3223 .master = &omap3xxx_l4_core_hwmod, 2601 .master = &omap3xxx_l4_core_hwmod,
3224 .slave = &omap34xx_mcspi1, 2602 .slave = &omap34xx_mcspi1,
3225 .clk = "mcspi1_ick", 2603 .clk = "mcspi1_ick",
3226 .addr = omap2_mcspi1_addr_space,
3227 .user = OCP_USER_MPU | OCP_USER_SDMA, 2604 .user = OCP_USER_MPU | OCP_USER_SDMA,
3228}; 2605};
3229 2606
@@ -3232,7 +2609,6 @@ static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
3232 .master = &omap3xxx_l4_core_hwmod, 2609 .master = &omap3xxx_l4_core_hwmod,
3233 .slave = &omap34xx_mcspi2, 2610 .slave = &omap34xx_mcspi2,
3234 .clk = "mcspi2_ick", 2611 .clk = "mcspi2_ick",
3235 .addr = omap2_mcspi2_addr_space,
3236 .user = OCP_USER_MPU | OCP_USER_SDMA, 2612 .user = OCP_USER_MPU | OCP_USER_SDMA,
3237}; 2613};
3238 2614
@@ -3241,25 +2617,15 @@ static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
3241 .master = &omap3xxx_l4_core_hwmod, 2617 .master = &omap3xxx_l4_core_hwmod,
3242 .slave = &omap34xx_mcspi3, 2618 .slave = &omap34xx_mcspi3,
3243 .clk = "mcspi3_ick", 2619 .clk = "mcspi3_ick",
3244 .addr = omap2430_mcspi3_addr_space,
3245 .user = OCP_USER_MPU | OCP_USER_SDMA, 2620 .user = OCP_USER_MPU | OCP_USER_SDMA,
3246}; 2621};
3247 2622
3248/* l4 core -> mcspi4 interface */ 2623/* l4 core -> mcspi4 interface */
3249static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
3250 {
3251 .pa_start = 0x480ba000,
3252 .pa_end = 0x480ba0ff,
3253 .flags = ADDR_TYPE_RT,
3254 },
3255 { }
3256};
3257 2624
3258static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = { 2625static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
3259 .master = &omap3xxx_l4_core_hwmod, 2626 .master = &omap3xxx_l4_core_hwmod,
3260 .slave = &omap34xx_mcspi4, 2627 .slave = &omap34xx_mcspi4,
3261 .clk = "mcspi4_ick", 2628 .clk = "mcspi4_ick",
3262 .addr = omap34xx_mcspi4_addr_space,
3263 .user = OCP_USER_MPU | OCP_USER_SDMA, 2629 .user = OCP_USER_MPU | OCP_USER_SDMA,
3264}; 2630};
3265 2631
@@ -3270,49 +2636,19 @@ static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = {
3270 .user = OCP_USER_MPU, 2636 .user = OCP_USER_MPU,
3271}; 2637};
3272 2638
3273static struct omap_hwmod_addr_space omap3xxx_usb_host_hs_addrs[] = {
3274 {
3275 .name = "uhh",
3276 .pa_start = 0x48064000,
3277 .pa_end = 0x480643ff,
3278 .flags = ADDR_TYPE_RT
3279 },
3280 {
3281 .name = "ohci",
3282 .pa_start = 0x48064400,
3283 .pa_end = 0x480647ff,
3284 },
3285 {
3286 .name = "ehci",
3287 .pa_start = 0x48064800,
3288 .pa_end = 0x48064cff,
3289 },
3290 {}
3291};
3292 2639
3293static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = { 2640static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = {
3294 .master = &omap3xxx_l4_core_hwmod, 2641 .master = &omap3xxx_l4_core_hwmod,
3295 .slave = &omap3xxx_usb_host_hs_hwmod, 2642 .slave = &omap3xxx_usb_host_hs_hwmod,
3296 .clk = "usbhost_ick", 2643 .clk = "usbhost_ick",
3297 .addr = omap3xxx_usb_host_hs_addrs,
3298 .user = OCP_USER_MPU | OCP_USER_SDMA, 2644 .user = OCP_USER_MPU | OCP_USER_SDMA,
3299}; 2645};
3300 2646
3301static struct omap_hwmod_addr_space omap3xxx_usb_tll_hs_addrs[] = {
3302 {
3303 .name = "tll",
3304 .pa_start = 0x48062000,
3305 .pa_end = 0x48062fff,
3306 .flags = ADDR_TYPE_RT
3307 },
3308 {}
3309};
3310 2647
3311static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = { 2648static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = {
3312 .master = &omap3xxx_l4_core_hwmod, 2649 .master = &omap3xxx_l4_core_hwmod,
3313 .slave = &omap3xxx_usb_tll_hs_hwmod, 2650 .slave = &omap3xxx_usb_tll_hs_hwmod,
3314 .clk = "usbtll_ick", 2651 .clk = "usbtll_ick",
3315 .addr = omap3xxx_usb_tll_hs_addrs,
3316 .user = OCP_USER_MPU | OCP_USER_SDMA, 2652 .user = OCP_USER_MPU | OCP_USER_SDMA,
3317}; 2653};
3318 2654
@@ -3321,35 +2657,17 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__hdq1w = {
3321 .master = &omap3xxx_l4_core_hwmod, 2657 .master = &omap3xxx_l4_core_hwmod,
3322 .slave = &omap3xxx_hdq1w_hwmod, 2658 .slave = &omap3xxx_hdq1w_hwmod,
3323 .clk = "hdq_ick", 2659 .clk = "hdq_ick",
3324 .addr = omap2_hdq1w_addr_space,
3325 .user = OCP_USER_MPU | OCP_USER_SDMA, 2660 .user = OCP_USER_MPU | OCP_USER_SDMA,
3326 .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE, 2661 .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
3327}; 2662};
3328 2663
3329/* l4_wkup -> 32ksync_counter */ 2664/* l4_wkup -> 32ksync_counter */
3330static struct omap_hwmod_addr_space omap3xxx_counter_32k_addrs[] = {
3331 {
3332 .pa_start = 0x48320000,
3333 .pa_end = 0x4832001f,
3334 .flags = ADDR_TYPE_RT
3335 },
3336 { }
3337};
3338 2665
3339static struct omap_hwmod_addr_space omap3xxx_gpmc_addrs[] = {
3340 {
3341 .pa_start = 0x6e000000,
3342 .pa_end = 0x6e000fff,
3343 .flags = ADDR_TYPE_RT
3344 },
3345 { }
3346};
3347 2666
3348static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = { 2667static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = {
3349 .master = &omap3xxx_l4_wkup_hwmod, 2668 .master = &omap3xxx_l4_wkup_hwmod,
3350 .slave = &omap3xxx_counter_32k_hwmod, 2669 .slave = &omap3xxx_counter_32k_hwmod,
3351 .clk = "omap_32ksync_ick", 2670 .clk = "omap_32ksync_ick",
3352 .addr = omap3xxx_counter_32k_addrs,
3353 .user = OCP_USER_MPU | OCP_USER_SDMA, 2671 .user = OCP_USER_MPU | OCP_USER_SDMA,
3354}; 2672};
3355 2673
@@ -3434,7 +2752,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l3_main__gpmc = {
3434 .master = &omap3xxx_l3_main_hwmod, 2752 .master = &omap3xxx_l3_main_hwmod,
3435 .slave = &omap3xxx_gpmc_hwmod, 2753 .slave = &omap3xxx_gpmc_hwmod,
3436 .clk = "core_l3_ick", 2754 .clk = "core_l3_ick",
3437 .addr = omap3xxx_gpmc_addrs,
3438 .user = OCP_USER_MPU | OCP_USER_SDMA, 2755 .user = OCP_USER_MPU | OCP_USER_SDMA,
3439}; 2756};
3440 2757
@@ -3459,20 +2776,10 @@ static struct omap_hwmod_class omap3xxx_sham_class = {
3459 .sysc = &omap3_sham_sysc, 2776 .sysc = &omap3_sham_sysc,
3460}; 2777};
3461 2778
3462static struct omap_hwmod_irq_info omap3_sham_mpu_irqs[] = {
3463 { .irq = 49 + OMAP_INTC_START, },
3464 { .irq = -1 }
3465};
3466 2779
3467static struct omap_hwmod_dma_info omap3_sham_sdma_reqs[] = {
3468 { .name = "rx", .dma_req = 69, },
3469 { .dma_req = -1 }
3470};
3471 2780
3472static struct omap_hwmod omap3xxx_sham_hwmod = { 2781static struct omap_hwmod omap3xxx_sham_hwmod = {
3473 .name = "sham", 2782 .name = "sham",
3474 .mpu_irqs = omap3_sham_mpu_irqs,
3475 .sdma_reqs = omap3_sham_sdma_reqs,
3476 .main_clk = "sha12_ick", 2783 .main_clk = "sha12_ick",
3477 .prcm = { 2784 .prcm = {
3478 .omap2 = { 2785 .omap2 = {
@@ -3486,20 +2793,11 @@ static struct omap_hwmod omap3xxx_sham_hwmod = {
3486 .class = &omap3xxx_sham_class, 2793 .class = &omap3xxx_sham_class,
3487}; 2794};
3488 2795
3489static struct omap_hwmod_addr_space omap3xxx_sham_addrs[] = {
3490 {
3491 .pa_start = 0x480c3000,
3492 .pa_end = 0x480c3000 + 0x64 - 1,
3493 .flags = ADDR_TYPE_RT
3494 },
3495 { }
3496};
3497 2796
3498static struct omap_hwmod_ocp_if omap3xxx_l4_core__sham = { 2797static struct omap_hwmod_ocp_if omap3xxx_l4_core__sham = {
3499 .master = &omap3xxx_l4_core_hwmod, 2798 .master = &omap3xxx_l4_core_hwmod,
3500 .slave = &omap3xxx_sham_hwmod, 2799 .slave = &omap3xxx_sham_hwmod,
3501 .clk = "sha12_ick", 2800 .clk = "sha12_ick",
3502 .addr = omap3xxx_sham_addrs,
3503 .user = OCP_USER_MPU | OCP_USER_SDMA, 2801 .user = OCP_USER_MPU | OCP_USER_SDMA,
3504}; 2802};
3505 2803
@@ -3525,15 +2823,9 @@ static struct omap_hwmod_class omap3xxx_aes_class = {
3525 .sysc = &omap3_aes_sysc, 2823 .sysc = &omap3_aes_sysc,
3526}; 2824};
3527 2825
3528static struct omap_hwmod_dma_info omap3_aes_sdma_reqs[] = {
3529 { .name = "tx", .dma_req = 65, },
3530 { .name = "rx", .dma_req = 66, },
3531 { .dma_req = -1 }
3532};
3533 2826
3534static struct omap_hwmod omap3xxx_aes_hwmod = { 2827static struct omap_hwmod omap3xxx_aes_hwmod = {
3535 .name = "aes", 2828 .name = "aes",
3536 .sdma_reqs = omap3_aes_sdma_reqs,
3537 .main_clk = "aes2_ick", 2829 .main_clk = "aes2_ick",
3538 .prcm = { 2830 .prcm = {
3539 .omap2 = { 2831 .omap2 = {
@@ -3547,20 +2839,11 @@ static struct omap_hwmod omap3xxx_aes_hwmod = {
3547 .class = &omap3xxx_aes_class, 2839 .class = &omap3xxx_aes_class,
3548}; 2840};
3549 2841
3550static struct omap_hwmod_addr_space omap3xxx_aes_addrs[] = {
3551 {
3552 .pa_start = 0x480c5000,
3553 .pa_end = 0x480c5000 + 0x50 - 1,
3554 .flags = ADDR_TYPE_RT
3555 },
3556 { }
3557};
3558 2842
3559static struct omap_hwmod_ocp_if omap3xxx_l4_core__aes = { 2843static struct omap_hwmod_ocp_if omap3xxx_l4_core__aes = {
3560 .master = &omap3xxx_l4_core_hwmod, 2844 .master = &omap3xxx_l4_core_hwmod,
3561 .slave = &omap3xxx_aes_hwmod, 2845 .slave = &omap3xxx_aes_hwmod,
3562 .clk = "aes2_ick", 2846 .clk = "aes2_ick",
3563 .addr = omap3xxx_aes_addrs,
3564 .user = OCP_USER_MPU | OCP_USER_SDMA, 2847 .user = OCP_USER_MPU | OCP_USER_SDMA,
3565}; 2848};
3566 2849
@@ -3661,28 +2944,28 @@ static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
3661/* GP-only hwmod links */ 2944/* GP-only hwmod links */
3662static struct omap_hwmod_ocp_if *omap34xx_gp_hwmod_ocp_ifs[] __initdata = { 2945static struct omap_hwmod_ocp_if *omap34xx_gp_hwmod_ocp_ifs[] __initdata = {
3663 &omap3xxx_l4_sec__timer12, 2946 &omap3xxx_l4_sec__timer12,
3664 NULL 2947 NULL,
3665}; 2948};
3666 2949
3667static struct omap_hwmod_ocp_if *omap36xx_gp_hwmod_ocp_ifs[] __initdata = { 2950static struct omap_hwmod_ocp_if *omap36xx_gp_hwmod_ocp_ifs[] __initdata = {
3668 &omap3xxx_l4_sec__timer12, 2951 &omap3xxx_l4_sec__timer12,
3669 NULL 2952 NULL,
3670}; 2953};
3671 2954
3672static struct omap_hwmod_ocp_if *am35xx_gp_hwmod_ocp_ifs[] __initdata = { 2955static struct omap_hwmod_ocp_if *am35xx_gp_hwmod_ocp_ifs[] __initdata = {
3673 &omap3xxx_l4_sec__timer12, 2956 &omap3xxx_l4_sec__timer12,
3674 NULL 2957 NULL,
3675}; 2958};
3676 2959
3677/* crypto hwmod links */ 2960/* crypto hwmod links */
3678static struct omap_hwmod_ocp_if *omap34xx_sham_hwmod_ocp_ifs[] __initdata = { 2961static struct omap_hwmod_ocp_if *omap34xx_sham_hwmod_ocp_ifs[] __initdata = {
3679 &omap3xxx_l4_core__sham, 2962 &omap3xxx_l4_core__sham,
3680 NULL 2963 NULL,
3681}; 2964};
3682 2965
3683static struct omap_hwmod_ocp_if *omap34xx_aes_hwmod_ocp_ifs[] __initdata = { 2966static struct omap_hwmod_ocp_if *omap34xx_aes_hwmod_ocp_ifs[] __initdata = {
3684 &omap3xxx_l4_core__aes, 2967 &omap3xxx_l4_core__aes,
3685 NULL 2968 NULL,
3686}; 2969};
3687 2970
3688static struct omap_hwmod_ocp_if *omap36xx_sham_hwmod_ocp_ifs[] __initdata = { 2971static struct omap_hwmod_ocp_if *omap36xx_sham_hwmod_ocp_ifs[] __initdata = {
@@ -3710,14 +2993,14 @@ static struct omap_hwmod_ocp_if *am35xx_sham_hwmod_ocp_ifs[] __initdata = {
3710 2993
3711static struct omap_hwmod_ocp_if *am35xx_aes_hwmod_ocp_ifs[] __initdata = { 2994static struct omap_hwmod_ocp_if *am35xx_aes_hwmod_ocp_ifs[] __initdata = {
3712 /* &omap3xxx_l4_core__aes, */ 2995 /* &omap3xxx_l4_core__aes, */
3713 NULL 2996 NULL,
3714}; 2997};
3715 2998
3716/* 3430ES1-only hwmod links */ 2999/* 3430ES1-only hwmod links */
3717static struct omap_hwmod_ocp_if *omap3430es1_hwmod_ocp_ifs[] __initdata = { 3000static struct omap_hwmod_ocp_if *omap3430es1_hwmod_ocp_ifs[] __initdata = {
3718 &omap3430es1_dss__l3, 3001 &omap3430es1_dss__l3,
3719 &omap3430es1_l4_core__dss, 3002 &omap3430es1_l4_core__dss,
3720 NULL 3003 NULL,
3721}; 3004};
3722 3005
3723/* 3430ES2+-only hwmod links */ 3006/* 3430ES2+-only hwmod links */
@@ -3729,21 +3012,21 @@ static struct omap_hwmod_ocp_if *omap3430es2plus_hwmod_ocp_ifs[] __initdata = {
3729 &omap3xxx_usb_host_hs__l3_main_2, 3012 &omap3xxx_usb_host_hs__l3_main_2,
3730 &omap3xxx_l4_core__usb_host_hs, 3013 &omap3xxx_l4_core__usb_host_hs,
3731 &omap3xxx_l4_core__usb_tll_hs, 3014 &omap3xxx_l4_core__usb_tll_hs,
3732 NULL 3015 NULL,
3733}; 3016};
3734 3017
3735/* <= 3430ES3-only hwmod links */ 3018/* <= 3430ES3-only hwmod links */
3736static struct omap_hwmod_ocp_if *omap3430_pre_es3_hwmod_ocp_ifs[] __initdata = { 3019static struct omap_hwmod_ocp_if *omap3430_pre_es3_hwmod_ocp_ifs[] __initdata = {
3737 &omap3xxx_l4_core__pre_es3_mmc1, 3020 &omap3xxx_l4_core__pre_es3_mmc1,
3738 &omap3xxx_l4_core__pre_es3_mmc2, 3021 &omap3xxx_l4_core__pre_es3_mmc2,
3739 NULL 3022 NULL,
3740}; 3023};
3741 3024
3742/* 3430ES3+-only hwmod links */ 3025/* 3430ES3+-only hwmod links */
3743static struct omap_hwmod_ocp_if *omap3430_es3plus_hwmod_ocp_ifs[] __initdata = { 3026static struct omap_hwmod_ocp_if *omap3430_es3plus_hwmod_ocp_ifs[] __initdata = {
3744 &omap3xxx_l4_core__es3plus_mmc1, 3027 &omap3xxx_l4_core__es3plus_mmc1,
3745 &omap3xxx_l4_core__es3plus_mmc2, 3028 &omap3xxx_l4_core__es3plus_mmc2,
3746 NULL 3029 NULL,
3747}; 3030};
3748 3031
3749/* 34xx-only hwmod links (all ES revisions) */ 3032/* 34xx-only hwmod links (all ES revisions) */
@@ -3757,7 +3040,7 @@ static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = {
3757 &omap3xxx_l4_core__mmu_isp, 3040 &omap3xxx_l4_core__mmu_isp,
3758 &omap3xxx_l3_main__mmu_iva, 3041 &omap3xxx_l3_main__mmu_iva,
3759 &omap3xxx_l4_core__ssi, 3042 &omap3xxx_l4_core__ssi,
3760 NULL 3043 NULL,
3761}; 3044};
3762 3045
3763/* 36xx-only hwmod links (all ES revisions) */ 3046/* 36xx-only hwmod links (all ES revisions) */
@@ -3781,7 +3064,7 @@ static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = {
3781 &omap3xxx_l4_core__mmu_isp, 3064 &omap3xxx_l4_core__mmu_isp,
3782 &omap3xxx_l3_main__mmu_iva, 3065 &omap3xxx_l3_main__mmu_iva,
3783 &omap3xxx_l4_core__ssi, 3066 &omap3xxx_l4_core__ssi,
3784 NULL 3067 NULL,
3785}; 3068};
3786 3069
3787static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = { 3070static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = {
@@ -3800,7 +3083,7 @@ static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = {
3800 &am35xx_l4_core__mdio, 3083 &am35xx_l4_core__mdio,
3801 &am35xx_emac__l3, 3084 &am35xx_emac__l3,
3802 &am35xx_l4_core__emac, 3085 &am35xx_l4_core__emac,
3803 NULL 3086 NULL,
3804}; 3087};
3805 3088
3806static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = { 3089static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = {
@@ -3808,7 +3091,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = {
3808 &omap3xxx_l4_core__dss_dsi1, 3091 &omap3xxx_l4_core__dss_dsi1,
3809 &omap3xxx_l4_core__dss_rfbi, 3092 &omap3xxx_l4_core__dss_rfbi,
3810 &omap3xxx_l4_core__dss_venc, 3093 &omap3xxx_l4_core__dss_venc,
3811 NULL 3094 NULL,
3812}; 3095};
3813 3096
3814/** 3097/**
diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.h b/arch/arm/mach-omap2/omap_hwmod_common_data.h
index 11ed5a17dd77..cdfbb44ceb0c 100644
--- a/arch/arm/mach-omap2/omap_hwmod_common_data.h
+++ b/arch/arm/mach-omap2/omap_hwmod_common_data.h
@@ -19,22 +19,7 @@
19#include "display.h" 19#include "display.h"
20 20
21/* Common address space across OMAP2xxx/3xxx */ 21/* Common address space across OMAP2xxx/3xxx */
22extern struct omap_hwmod_addr_space omap2_i2c1_addr_space[];
23extern struct omap_hwmod_addr_space omap2_i2c2_addr_space[];
24extern struct omap_hwmod_addr_space omap2_dss_addrs[];
25extern struct omap_hwmod_addr_space omap2_dss_dispc_addrs[];
26extern struct omap_hwmod_addr_space omap2_dss_rfbi_addrs[];
27extern struct omap_hwmod_addr_space omap2_dss_venc_addrs[];
28extern struct omap_hwmod_addr_space omap2_timer10_addrs[];
29extern struct omap_hwmod_addr_space omap2_timer11_addrs[];
30extern struct omap_hwmod_addr_space omap2430_mmc1_addr_space[];
31extern struct omap_hwmod_addr_space omap2430_mmc2_addr_space[];
32extern struct omap_hwmod_addr_space omap2_mcspi1_addr_space[];
33extern struct omap_hwmod_addr_space omap2_mcspi2_addr_space[];
34extern struct omap_hwmod_addr_space omap2430_mcspi3_addr_space[];
35extern struct omap_hwmod_addr_space omap2_dma_system_addrs[]; 22extern struct omap_hwmod_addr_space omap2_dma_system_addrs[];
36extern struct omap_hwmod_addr_space omap2_mcbsp1_addrs[];
37extern struct omap_hwmod_addr_space omap2_hdq1w_addr_space[];
38 23
39/* Common IP block data across OMAP2xxx */ 24/* Common IP block data across OMAP2xxx */
40extern struct omap_gpio_dev_attr omap2xxx_gpio_dev_attr; 25extern struct omap_gpio_dev_attr omap2xxx_gpio_dev_attr;
diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c
index 05e20aaf68dd..477910a48448 100644
--- a/arch/arm/mach-omap2/pdata-quirks.c
+++ b/arch/arm/mach-omap2/pdata-quirks.c
@@ -31,7 +31,6 @@
31 31
32#include "common.h" 32#include "common.h"
33#include "common-board-devices.h" 33#include "common-board-devices.h"
34#include "dss-common.h"
35#include "control.h" 34#include "control.h"
36#include "omap_device.h" 35#include "omap_device.h"
37#include "omap-pm.h" 36#include "omap-pm.h"
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index 678d2a31dcb8..76b0454ddc49 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -30,7 +30,6 @@
30#include "powerdomain.h" 30#include "powerdomain.h"
31#include "clockdomain.h" 31#include "clockdomain.h"
32#include "pm.h" 32#include "pm.h"
33#include "twl-common.h"
34 33
35#ifdef CONFIG_SUSPEND 34#ifdef CONFIG_SUSPEND
36/* 35/*
@@ -72,42 +71,6 @@ void omap_pm_get_oscillator(u32 *tstart, u32 *tshut)
72} 71}
73#endif 72#endif
74 73
75static int __init _init_omap_device(char *name)
76{
77 struct omap_hwmod *oh;
78 struct platform_device *pdev;
79
80 oh = omap_hwmod_lookup(name);
81 if (WARN(!oh, "%s: could not find omap_hwmod for %s\n",
82 __func__, name))
83 return -ENODEV;
84
85 pdev = omap_device_build(oh->name, 0, oh, NULL, 0);
86 if (WARN(IS_ERR(pdev), "%s: could not build omap_device for %s\n",
87 __func__, name))
88 return -ENODEV;
89
90 return 0;
91}
92
93/*
94 * Build omap_devices for processors and bus.
95 */
96static void __init omap2_init_processor_devices(void)
97{
98 _init_omap_device("mpu");
99 if (omap3_has_iva())
100 _init_omap_device("iva");
101
102 if (cpu_is_omap44xx()) {
103 _init_omap_device("l3_main_1");
104 _init_omap_device("dsp");
105 _init_omap_device("iva");
106 } else {
107 _init_omap_device("l3_main");
108 }
109}
110
111int __init omap_pm_clkdms_setup(struct clockdomain *clkdm, void *unused) 74int __init omap_pm_clkdms_setup(struct clockdomain *clkdm, void *unused)
112{ 75{
113 clkdm_allow_idle(clkdm); 76 clkdm_allow_idle(clkdm);
@@ -215,7 +178,7 @@ static int omap_pm_enter(suspend_state_t suspend_state)
215static int omap_pm_begin(suspend_state_t state) 178static int omap_pm_begin(suspend_state_t state)
216{ 179{
217 cpu_idle_poll_ctrl(true); 180 cpu_idle_poll_ctrl(true);
218 if (cpu_is_omap34xx()) 181 if (soc_is_omap34xx())
219 omap_prcm_irq_prepare(); 182 omap_prcm_irq_prepare();
220 return 0; 183 return 0;
221} 184}
@@ -227,7 +190,7 @@ static void omap_pm_end(void)
227 190
228static void omap_pm_finish(void) 191static void omap_pm_finish(void)
229{ 192{
230 if (cpu_is_omap34xx()) 193 if (soc_is_omap34xx())
231 omap_prcm_irq_complete(); 194 omap_prcm_irq_complete();
232} 195}
233 196
@@ -252,7 +215,7 @@ void omap_common_suspend_init(void *pm_suspend)
252 215
253static void __init omap3_init_voltages(void) 216static void __init omap3_init_voltages(void)
254{ 217{
255 if (!cpu_is_omap34xx()) 218 if (!soc_is_omap34xx())
256 return; 219 return;
257 220
258 omap2_set_init_voltage("mpu_iva", "dpll1_ck", "mpu"); 221 omap2_set_init_voltage("mpu_iva", "dpll1_ck", "mpu");
@@ -261,7 +224,7 @@ static void __init omap3_init_voltages(void)
261 224
262static void __init omap4_init_voltages(void) 225static void __init omap4_init_voltages(void)
263{ 226{
264 if (!cpu_is_omap44xx()) 227 if (!soc_is_omap44xx())
265 return; 228 return;
266 229
267 omap2_set_init_voltage("mpu", "dpll_mpu_ck", "mpu"); 230 omap2_set_init_voltage("mpu", "dpll_mpu_ck", "mpu");
@@ -269,18 +232,8 @@ static void __init omap4_init_voltages(void)
269 omap2_set_init_voltage("iva", "dpll_iva_m5x2_ck", "iva"); 232 omap2_set_init_voltage("iva", "dpll_iva_m5x2_ck", "iva");
270} 233}
271 234
272static inline void omap_init_cpufreq(void)
273{
274 struct platform_device_info devinfo = { .name = "omap-cpufreq" };
275
276 if (!of_have_populated_dt())
277 platform_device_register_full(&devinfo);
278}
279
280static int __init omap2_common_pm_init(void) 235static int __init omap2_common_pm_init(void)
281{ 236{
282 if (!of_have_populated_dt())
283 omap2_init_processor_devices();
284 omap_pm_if_init(); 237 omap_pm_if_init();
285 238
286 return 0; 239 return 0;
@@ -289,13 +242,9 @@ omap_postcore_initcall(omap2_common_pm_init);
289 242
290int __init omap2_common_pm_late_init(void) 243int __init omap2_common_pm_late_init(void)
291{ 244{
292 if (of_have_populated_dt()) {
293 omap3_twl_init();
294 omap4_twl_init();
295 }
296
297 /* Init the voltage layer */ 245 /* Init the voltage layer */
298 omap_pmic_late_init(); 246 omap3_twl_init();
247 omap4_twl_init();
299 omap_voltage_late_init(); 248 omap_voltage_late_init();
300 249
301 /* Initialize the voltages */ 250 /* Initialize the voltages */
@@ -305,8 +254,5 @@ int __init omap2_common_pm_late_init(void)
305 /* Smartreflex device init */ 254 /* Smartreflex device init */
306 omap_devinit_smartreflex(); 255 omap_devinit_smartreflex();
307 256
308 /* cpufreq dummy device instantiation */
309 omap_init_cpufreq();
310
311 return 0; 257 return 0;
312} 258}
diff --git a/arch/arm/mach-omap2/sdram-hynix-h8mbx00u0mer-0em.h b/arch/arm/mach-omap2/sdram-hynix-h8mbx00u0mer-0em.h
deleted file mode 100644
index 1ee58c281a31..000000000000
--- a/arch/arm/mach-omap2/sdram-hynix-h8mbx00u0mer-0em.h
+++ /dev/null
@@ -1,51 +0,0 @@
1/*
2 * SDRC register values for the Hynix H8MBX00U0MER-0EM
3 *
4 * Copyright (C) 2009 Texas Instruments, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ARCH_ARM_MACH_OMAP2_SDRAM_HYNIX_H8MBX00U0MER0EM
12#define __ARCH_ARM_MACH_OMAP2_SDRAM_HYNIX_H8MBX00U0MER0EM
13
14#include "sdrc.h"
15
16/* Hynix H8MBX00U0MER-0EM */
17static struct omap_sdrc_params h8mbx00u0mer0em_sdrc_params[] = {
18 [0] = {
19 .rate = 200000000,
20 .actim_ctrla = 0xa2e1b4c6,
21 .actim_ctrlb = 0x0002131c,
22 .rfr_ctrl = 0x0005e601,
23 .mr = 0x00000032,
24 },
25 [1] = {
26 .rate = 166000000,
27 .actim_ctrla = 0x629db4c6,
28 .actim_ctrlb = 0x00012214,
29 .rfr_ctrl = 0x0004dc01,
30 .mr = 0x00000032,
31 },
32 [2] = {
33 .rate = 100000000,
34 .actim_ctrla = 0x51912284,
35 .actim_ctrlb = 0x0002120e,
36 .rfr_ctrl = 0x0002d101,
37 .mr = 0x00000022,
38 },
39 [3] = {
40 .rate = 83000000,
41 .actim_ctrla = 0x31512283,
42 .actim_ctrlb = 0x0001220a,
43 .rfr_ctrl = 0x00025501,
44 .mr = 0x00000022,
45 },
46 [4] = {
47 .rate = 0
48 },
49};
50
51#endif
diff --git a/arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h b/arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h
deleted file mode 100644
index 85cccc004c06..000000000000
--- a/arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h
+++ /dev/null
@@ -1,55 +0,0 @@
1/*
2 * SDRC register values for the Micron MT46H32M32LF-6
3 *
4 * Copyright (C) 2008 Texas Instruments, Inc.
5 * Copyright (C) 2008-2009 Nokia Corporation
6 *
7 * Paul Walmsley
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#ifndef ARCH_ARM_MACH_OMAP2_SDRAM_MICRON_MT46H32M32LF
15#define ARCH_ARM_MACH_OMAP2_SDRAM_MICRON_MT46H32M32LF
16
17#include "sdrc.h"
18
19/* Micron MT46H32M32LF-6 */
20/* XXX Using ARE = 0x1 (no autorefresh burst) -- can this be changed? */
21static struct omap_sdrc_params mt46h32m32lf6_sdrc_params[] = {
22 [0] = {
23 .rate = 166000000,
24 .actim_ctrla = 0x9a9db4c6,
25 .actim_ctrlb = 0x00011217,
26 .rfr_ctrl = 0x0004dc01,
27 .mr = 0x00000032,
28 },
29 [1] = {
30 .rate = 165941176,
31 .actim_ctrla = 0x9a9db4c6,
32 .actim_ctrlb = 0x00011217,
33 .rfr_ctrl = 0x0004dc01,
34 .mr = 0x00000032,
35 },
36 [2] = {
37 .rate = 83000000,
38 .actim_ctrla = 0x51512283,
39 .actim_ctrlb = 0x0001120c,
40 .rfr_ctrl = 0x00025501,
41 .mr = 0x00000032,
42 },
43 [3] = {
44 .rate = 82970588,
45 .actim_ctrla = 0x51512283,
46 .actim_ctrlb = 0x0001120c,
47 .rfr_ctrl = 0x00025501,
48 .mr = 0x00000032,
49 },
50 [4] = {
51 .rate = 0
52 },
53};
54
55#endif
diff --git a/arch/arm/mach-omap2/sdram-nokia.c b/arch/arm/mach-omap2/sdram-nokia.c
deleted file mode 100644
index 0fa7ffa9b5ed..000000000000
--- a/arch/arm/mach-omap2/sdram-nokia.c
+++ /dev/null
@@ -1,299 +0,0 @@
1/*
2 * SDRC register values for Nokia boards
3 *
4 * Copyright (C) 2008, 2010-2011 Nokia Corporation
5 *
6 * Lauri Leukkunen <lauri.leukkunen@nokia.com>
7 *
8 * Original code by Juha Yrjola <juha.yrjola@solidboot.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/kernel.h>
16#include <linux/clk.h>
17#include <linux/err.h>
18#include <linux/io.h>
19
20#include "common.h"
21#include "sdram-nokia.h"
22#include "sdrc.h"
23
24/* In picoseconds, except for tREF (ns), tXP, tCKE, tWTR (clks) */
25struct sdram_timings {
26 u32 casl;
27 u32 tDAL;
28 u32 tDPL;
29 u32 tRRD;
30 u32 tRCD;
31 u32 tRP;
32 u32 tRAS;
33 u32 tRC;
34 u32 tRFC;
35 u32 tXSR;
36
37 u32 tREF; /* in ns */
38
39 u32 tXP;
40 u32 tCKE;
41 u32 tWTR;
42};
43
44static const struct sdram_timings nokia_97dot6mhz_timings[] = {
45 {
46 .casl = 3,
47 .tDAL = 30725,
48 .tDPL = 15362,
49 .tRRD = 10241,
50 .tRCD = 20483,
51 .tRP = 15362,
52 .tRAS = 40967,
53 .tRC = 56330,
54 .tRFC = 138266,
55 .tXSR = 204839,
56
57 .tREF = 7798,
58
59 .tXP = 2,
60 .tCKE = 4,
61 .tWTR = 2,
62 },
63};
64
65static const struct sdram_timings nokia_166mhz_timings[] = {
66 {
67 .casl = 3,
68 .tDAL = 33000,
69 .tDPL = 15000,
70 .tRRD = 12000,
71 .tRCD = 22500,
72 .tRP = 18000,
73 .tRAS = 42000,
74 .tRC = 66000,
75 .tRFC = 138000,
76 .tXSR = 200000,
77
78 .tREF = 7800,
79
80 .tXP = 2,
81 .tCKE = 2,
82 .tWTR = 2
83 },
84};
85
86static const struct sdram_timings nokia_195dot2mhz_timings[] = {
87 {
88 .casl = 3,
89 .tDAL = 30725,
90 .tDPL = 15362,
91 .tRRD = 10241,
92 .tRCD = 20483,
93 .tRP = 15362,
94 .tRAS = 40967,
95 .tRC = 56330,
96 .tRFC = 138266,
97 .tXSR = 204839,
98
99 .tREF = 7752,
100
101 .tXP = 2,
102 .tCKE = 4,
103 .tWTR = 2,
104 },
105};
106
107static const struct sdram_timings nokia_200mhz_timings[] = {
108 {
109 .casl = 3,
110 .tDAL = 30000,
111 .tDPL = 15000,
112 .tRRD = 10000,
113 .tRCD = 20000,
114 .tRP = 15000,
115 .tRAS = 40000,
116 .tRC = 55000,
117 .tRFC = 140000,
118 .tXSR = 200000,
119
120 .tREF = 7800,
121
122 .tXP = 2,
123 .tCKE = 4,
124 .tWTR = 2
125 },
126};
127
128static const struct {
129 long rate;
130 struct sdram_timings const *data;
131} nokia_timings[] = {
132 { 83000000, nokia_166mhz_timings },
133 { 97600000, nokia_97dot6mhz_timings },
134 { 100000000, nokia_200mhz_timings },
135 { 166000000, nokia_166mhz_timings },
136 { 195200000, nokia_195dot2mhz_timings },
137 { 200000000, nokia_200mhz_timings },
138};
139static struct omap_sdrc_params nokia_sdrc_params[ARRAY_SIZE(nokia_timings) + 1];
140
141static unsigned long sdrc_get_fclk_period(long rate)
142{
143 /* In picoseconds */
144 return 1000000000 / rate;
145}
146
147static unsigned int sdrc_ps_to_ticks(unsigned int time_ps, long rate)
148{
149 unsigned long tick_ps;
150
151 /* Calculate in picosecs to yield more exact results */
152 tick_ps = sdrc_get_fclk_period(rate);
153
154 return (time_ps + tick_ps - 1) / tick_ps;
155}
156#undef DEBUG
157#ifdef DEBUG
158static int set_sdrc_timing_regval(u32 *regval, int st_bit, int end_bit,
159 int ticks, long rate, const char *name)
160#else
161static int set_sdrc_timing_regval(u32 *regval, int st_bit, int end_bit,
162 int ticks)
163#endif
164{
165 int mask, nr_bits;
166
167 nr_bits = end_bit - st_bit + 1;
168 if (ticks >= 1 << nr_bits)
169 return -1;
170 mask = (1 << nr_bits) - 1;
171 *regval &= ~(mask << st_bit);
172 *regval |= ticks << st_bit;
173#ifdef DEBUG
174 printk(KERN_INFO "SDRC %s: %i ticks %i ns\n", name, ticks,
175 (unsigned int)sdrc_get_fclk_period(rate) * ticks /
176 1000);
177#endif
178
179 return 0;
180}
181
182#ifdef DEBUG
183#define SDRC_SET_ONE(reg, st, end, field, rate) \
184 if (set_sdrc_timing_regval((reg), (st), (end), \
185 memory_timings->field, (rate), #field) < 0) \
186 err = -1;
187#else
188#define SDRC_SET_ONE(reg, st, end, field, rate) \
189 if (set_sdrc_timing_regval((reg), (st), (end), \
190 memory_timings->field) < 0) \
191 err = -1;
192#endif
193
194#ifdef DEBUG
195static int set_sdrc_timing_regval_ps(u32 *regval, int st_bit, int end_bit,
196 int time, long rate, const char *name)
197#else
198static int set_sdrc_timing_regval_ps(u32 *regval, int st_bit, int end_bit,
199 int time, long rate)
200#endif
201{
202 int ticks, ret;
203 ret = 0;
204
205 if (time == 0)
206 ticks = 0;
207 else
208 ticks = sdrc_ps_to_ticks(time, rate);
209
210#ifdef DEBUG
211 ret = set_sdrc_timing_regval(regval, st_bit, end_bit, ticks,
212 rate, name);
213#else
214 ret = set_sdrc_timing_regval(regval, st_bit, end_bit, ticks);
215#endif
216
217 return ret;
218}
219
220#ifdef DEBUG
221#define SDRC_SET_ONE_PS(reg, st, end, field, rate) \
222 if (set_sdrc_timing_regval_ps((reg), (st), (end), \
223 memory_timings->field, \
224 (rate), #field) < 0) \
225 err = -1;
226
227#else
228#define SDRC_SET_ONE_PS(reg, st, end, field, rate) \
229 if (set_sdrc_timing_regval_ps((reg), (st), (end), \
230 memory_timings->field, (rate)) < 0) \
231 err = -1;
232#endif
233
234static int sdrc_timings(int id, long rate,
235 const struct sdram_timings *memory_timings)
236{
237 u32 ticks_per_ms;
238 u32 rfr, l;
239 u32 actim_ctrla = 0, actim_ctrlb = 0;
240 u32 rfr_ctrl;
241 int err = 0;
242 long l3_rate = rate / 1000;
243
244 SDRC_SET_ONE_PS(&actim_ctrla, 0, 4, tDAL, l3_rate);
245 SDRC_SET_ONE_PS(&actim_ctrla, 6, 8, tDPL, l3_rate);
246 SDRC_SET_ONE_PS(&actim_ctrla, 9, 11, tRRD, l3_rate);
247 SDRC_SET_ONE_PS(&actim_ctrla, 12, 14, tRCD, l3_rate);
248 SDRC_SET_ONE_PS(&actim_ctrla, 15, 17, tRP, l3_rate);
249 SDRC_SET_ONE_PS(&actim_ctrla, 18, 21, tRAS, l3_rate);
250 SDRC_SET_ONE_PS(&actim_ctrla, 22, 26, tRC, l3_rate);
251 SDRC_SET_ONE_PS(&actim_ctrla, 27, 31, tRFC, l3_rate);
252
253 SDRC_SET_ONE_PS(&actim_ctrlb, 0, 7, tXSR, l3_rate);
254
255 SDRC_SET_ONE(&actim_ctrlb, 8, 10, tXP, l3_rate);
256 SDRC_SET_ONE(&actim_ctrlb, 12, 14, tCKE, l3_rate);
257 SDRC_SET_ONE(&actim_ctrlb, 16, 17, tWTR, l3_rate);
258
259 ticks_per_ms = l3_rate;
260 rfr = memory_timings[0].tREF * ticks_per_ms / 1000000;
261 if (rfr > 65535 + 50)
262 rfr = 65535;
263 else
264 rfr -= 50;
265
266#ifdef DEBUG
267 printk(KERN_INFO "SDRC tREF: %i ticks\n", rfr);
268#endif
269
270 l = rfr << 8;
271 rfr_ctrl = l | 0x1; /* autorefresh, reload counter with 1xARCV */
272
273 nokia_sdrc_params[id].rate = rate;
274 nokia_sdrc_params[id].actim_ctrla = actim_ctrla;
275 nokia_sdrc_params[id].actim_ctrlb = actim_ctrlb;
276 nokia_sdrc_params[id].rfr_ctrl = rfr_ctrl;
277 nokia_sdrc_params[id].mr = 0x32;
278
279 nokia_sdrc_params[id + 1].rate = 0;
280
281 return err;
282}
283
284struct omap_sdrc_params *nokia_get_sdram_timings(void)
285{
286 int err = 0;
287 int i;
288
289 for (i = 0; i < ARRAY_SIZE(nokia_timings); i++) {
290 err |= sdrc_timings(i, nokia_timings[i].rate,
291 nokia_timings[i].data);
292 if (err)
293 pr_err("%s: error with rate %ld: %d\n", __func__,
294 nokia_timings[i].rate, err);
295 }
296
297 return err ? NULL : nokia_sdrc_params;
298}
299
diff --git a/arch/arm/mach-omap2/sdram-nokia.h b/arch/arm/mach-omap2/sdram-nokia.h
deleted file mode 100644
index ee63da5f8df0..000000000000
--- a/arch/arm/mach-omap2/sdram-nokia.h
+++ /dev/null
@@ -1,12 +0,0 @@
1/*
2 * SDRC register values for Nokia boards
3 *
4 * Copyright (C) 2010 Nokia
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11struct omap_sdrc_params *nokia_get_sdram_timings(void);
12
diff --git a/arch/arm/mach-omap2/sdram-numonyx-m65kxxxxam.h b/arch/arm/mach-omap2/sdram-numonyx-m65kxxxxam.h
deleted file mode 100644
index 003f7bf4e2e3..000000000000
--- a/arch/arm/mach-omap2/sdram-numonyx-m65kxxxxam.h
+++ /dev/null
@@ -1,51 +0,0 @@
1/*
2 * SDRC register values for the Numonyx M65KXXXXAM
3 *
4 * Copyright (C) 2009 Integration Software and Electronic Engineering.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ARCH_ARM_MACH_OMAP2_SDRAM_NUMONYX_M65KXXXXAM
12#define __ARCH_ARM_MACH_OMAP2_SDRAM_NUMONYX_M65KXXXXAM
13
14#include "sdrc.h"
15
16/* Numonyx M65KXXXXAM */
17static struct omap_sdrc_params m65kxxxxam_sdrc_params[] = {
18 [0] = {
19 .rate = 200000000,
20 .actim_ctrla = 0xe321d4c6,
21 .actim_ctrlb = 0x00022328,
22 .rfr_ctrl = 0x0005e601,
23 .mr = 0x00000032,
24 },
25 [1] = {
26 .rate = 166000000,
27 .actim_ctrla = 0xba9dc485,
28 .actim_ctrlb = 0x00022321,
29 .rfr_ctrl = 0x0004dc01,
30 .mr = 0x00000032,
31 },
32 [2] = {
33 .rate = 133000000,
34 .actim_ctrla = 0x9a19b485,
35 .actim_ctrlb = 0x0002231b,
36 .rfr_ctrl = 0x0003de01,
37 .mr = 0x00000032,
38 },
39 [3] = {
40 .rate = 83000000,
41 .actim_ctrla = 0x594ca242,
42 .actim_ctrlb = 0x00022310,
43 .rfr_ctrl = 0x00025501,
44 .mr = 0x00000032,
45 },
46 [4] = {
47 .rate = 0
48 },
49};
50
51#endif
diff --git a/arch/arm/mach-omap2/sdram-qimonda-hyb18m512160af-6.h b/arch/arm/mach-omap2/sdram-qimonda-hyb18m512160af-6.h
deleted file mode 100644
index 8dc3de5ebb5b..000000000000
--- a/arch/arm/mach-omap2/sdram-qimonda-hyb18m512160af-6.h
+++ /dev/null
@@ -1,54 +0,0 @@
1/*
2 * SDRC register values for the Qimonda HYB18M512160AF-6
3 *
4 * Copyright (C) 2008-2009 Texas Instruments, Inc.
5 * Copyright (C) 2008-2009 Nokia Corporation
6 *
7 * Paul Walmsley
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#ifndef ARCH_ARM_MACH_OMAP2_SDRAM_QIMONDA_HYB18M512160AF6
15#define ARCH_ARM_MACH_OMAP2_SDRAM_QIMONDA_HYB18M512160AF6
16
17#include "sdrc.h"
18
19/* Qimonda HYB18M512160AF-6 */
20static struct omap_sdrc_params hyb18m512160af6_sdrc_params[] = {
21 [0] = {
22 .rate = 166000000,
23 .actim_ctrla = 0x629db4c6,
24 .actim_ctrlb = 0x00012214,
25 .rfr_ctrl = 0x0004dc01,
26 .mr = 0x00000032,
27 },
28 [1] = {
29 .rate = 165941176,
30 .actim_ctrla = 0x629db4c6,
31 .actim_ctrlb = 0x00012214,
32 .rfr_ctrl = 0x0004dc01,
33 .mr = 0x00000032,
34 },
35 [2] = {
36 .rate = 83000000,
37 .actim_ctrla = 0x31512283,
38 .actim_ctrlb = 0x0001220a,
39 .rfr_ctrl = 0x00025501,
40 .mr = 0x00000022,
41 },
42 [3] = {
43 .rate = 82970588,
44 .actim_ctrla = 0x31512283,
45 .actim_ctrlb = 0x0001220a,
46 .rfr_ctrl = 0x00025501,
47 .mr = 0x00000022,
48 },
49 [4] = {
50 .rate = 0
51 },
52};
53
54#endif
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
deleted file mode 100644
index 8e072de89fed..000000000000
--- a/arch/arm/mach-omap2/serial.c
+++ /dev/null
@@ -1,332 +0,0 @@
1/*
2 * arch/arm/mach-omap2/serial.c
3 *
4 * OMAP2 serial support.
5 *
6 * Copyright (C) 2005-2008 Nokia Corporation
7 * Author: Paul Mundt <paul.mundt@nokia.com>
8 *
9 * Major rework for PM support by Kevin Hilman
10 *
11 * Based off of arch/arm/mach-omap/omap1/serial.c
12 *
13 * Copyright (C) 2009 Texas Instruments
14 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com
15 *
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
18 * for more details.
19 */
20#include <linux/kernel.h>
21#include <linux/init.h>
22#include <linux/clk.h>
23#include <linux/io.h>
24#include <linux/delay.h>
25#include <linux/platform_device.h>
26#include <linux/slab.h>
27#include <linux/pm_runtime.h>
28#include <linux/console.h>
29#include <linux/omap-dma.h>
30#include <linux/platform_data/serial-omap.h>
31
32#include "common.h"
33#include "omap_hwmod.h"
34#include "omap_device.h"
35#include "omap-pm.h"
36#include "soc.h"
37#include "prm2xxx_3xxx.h"
38#include "pm.h"
39#include "cm2xxx_3xxx.h"
40#include "prm-regbits-34xx.h"
41#include "control.h"
42#include "mux.h"
43#include "serial.h"
44
45/*
46 * NOTE: By default the serial auto_suspend timeout is disabled as it causes
47 * lost characters over the serial ports. This means that the UART clocks will
48 * stay on until power/autosuspend_delay is set for the uart from sysfs.
49 * This also causes that any deeper omap sleep states are blocked.
50 */
51#define DEFAULT_AUTOSUSPEND_DELAY -1
52
53#define MAX_UART_HWMOD_NAME_LEN 16
54
55struct omap_uart_state {
56 int num;
57
58 struct list_head node;
59 struct omap_hwmod *oh;
60 struct omap_device_pad default_omap_uart_pads[2];
61};
62
63static LIST_HEAD(uart_list);
64static u8 num_uarts;
65static u8 console_uart_id = -1;
66static u8 uart_debug;
67
68#define DEFAULT_RXDMA_POLLRATE 1 /* RX DMA polling rate (us) */
69#define DEFAULT_RXDMA_BUFSIZE 4096 /* RX DMA buffer size */
70#define DEFAULT_RXDMA_TIMEOUT (3 * HZ)/* RX DMA timeout (jiffies) */
71
72static struct omap_uart_port_info omap_serial_default_info[] __initdata = {
73 {
74 .dma_enabled = false,
75 .dma_rx_buf_size = DEFAULT_RXDMA_BUFSIZE,
76 .dma_rx_poll_rate = DEFAULT_RXDMA_POLLRATE,
77 .dma_rx_timeout = DEFAULT_RXDMA_TIMEOUT,
78 .autosuspend_timeout = DEFAULT_AUTOSUSPEND_DELAY,
79 },
80};
81
82#ifdef CONFIG_PM
83static void omap_uart_enable_wakeup(struct device *dev, bool enable)
84{
85 struct platform_device *pdev = to_platform_device(dev);
86 struct omap_device *od = to_omap_device(pdev);
87
88 if (!od)
89 return;
90
91 if (enable)
92 omap_hwmod_enable_wakeup(od->hwmods[0]);
93 else
94 omap_hwmod_disable_wakeup(od->hwmods[0]);
95}
96
97#else
98static void omap_uart_enable_wakeup(struct device *dev, bool enable)
99{}
100#endif /* CONFIG_PM */
101
102#ifdef CONFIG_OMAP_MUX
103
104#define OMAP_UART_DEFAULT_PAD_NAME_LEN 28
105static char rx_pad_name[OMAP_UART_DEFAULT_PAD_NAME_LEN],
106 tx_pad_name[OMAP_UART_DEFAULT_PAD_NAME_LEN] __initdata;
107
108static void __init
109omap_serial_fill_uart_tx_rx_pads(struct omap_board_data *bdata,
110 struct omap_uart_state *uart)
111{
112 uart->default_omap_uart_pads[0].name = rx_pad_name;
113 uart->default_omap_uart_pads[0].flags = OMAP_DEVICE_PAD_REMUX |
114 OMAP_DEVICE_PAD_WAKEUP;
115 uart->default_omap_uart_pads[0].enable = OMAP_PIN_INPUT |
116 OMAP_MUX_MODE0;
117 uart->default_omap_uart_pads[0].idle = OMAP_PIN_INPUT | OMAP_MUX_MODE0;
118 uart->default_omap_uart_pads[1].name = tx_pad_name;
119 uart->default_omap_uart_pads[1].enable = OMAP_PIN_OUTPUT |
120 OMAP_MUX_MODE0;
121 bdata->pads = uart->default_omap_uart_pads;
122 bdata->pads_cnt = ARRAY_SIZE(uart->default_omap_uart_pads);
123}
124
125static void __init omap_serial_check_wakeup(struct omap_board_data *bdata,
126 struct omap_uart_state *uart)
127{
128 struct omap_mux_partition *tx_partition = NULL, *rx_partition = NULL;
129 struct omap_mux *rx_mux = NULL, *tx_mux = NULL;
130 char *rx_fmt, *tx_fmt;
131 int uart_nr = bdata->id + 1;
132
133 if (bdata->id != 2) {
134 rx_fmt = "uart%d_rx.uart%d_rx";
135 tx_fmt = "uart%d_tx.uart%d_tx";
136 } else {
137 rx_fmt = "uart%d_rx_irrx.uart%d_rx_irrx";
138 tx_fmt = "uart%d_tx_irtx.uart%d_tx_irtx";
139 }
140
141 snprintf(rx_pad_name, OMAP_UART_DEFAULT_PAD_NAME_LEN, rx_fmt,
142 uart_nr, uart_nr);
143 snprintf(tx_pad_name, OMAP_UART_DEFAULT_PAD_NAME_LEN, tx_fmt,
144 uart_nr, uart_nr);
145
146 if (omap_mux_get_by_name(rx_pad_name, &rx_partition, &rx_mux) >= 0 &&
147 omap_mux_get_by_name
148 (tx_pad_name, &tx_partition, &tx_mux) >= 0) {
149 u16 tx_mode, rx_mode;
150
151 tx_mode = omap_mux_read(tx_partition, tx_mux->reg_offset);
152 rx_mode = omap_mux_read(rx_partition, rx_mux->reg_offset);
153
154 /*
155 * Check if uart is used in default tx/rx mode i.e. in mux mode0
156 * if yes then configure rx pin for wake up capability
157 */
158 if (OMAP_MODE_UART(rx_mode) && OMAP_MODE_UART(tx_mode))
159 omap_serial_fill_uart_tx_rx_pads(bdata, uart);
160 }
161}
162#else
163static void __init omap_serial_check_wakeup(struct omap_board_data *bdata,
164 struct omap_uart_state *uart)
165{
166}
167#endif
168
169static char *cmdline_find_option(char *str)
170{
171 extern char *saved_command_line;
172
173 return strstr(saved_command_line, str);
174}
175
176static int __init omap_serial_early_init(void)
177{
178 if (of_have_populated_dt())
179 return -ENODEV;
180
181 do {
182 char oh_name[MAX_UART_HWMOD_NAME_LEN];
183 struct omap_hwmod *oh;
184 struct omap_uart_state *uart;
185 char uart_name[MAX_UART_HWMOD_NAME_LEN];
186
187 snprintf(oh_name, MAX_UART_HWMOD_NAME_LEN,
188 "uart%d", num_uarts + 1);
189 oh = omap_hwmod_lookup(oh_name);
190 if (!oh)
191 break;
192
193 uart = kzalloc(sizeof(struct omap_uart_state), GFP_KERNEL);
194 if (WARN_ON(!uart))
195 return -ENODEV;
196
197 uart->oh = oh;
198 uart->num = num_uarts++;
199 list_add_tail(&uart->node, &uart_list);
200 snprintf(uart_name, MAX_UART_HWMOD_NAME_LEN,
201 "%s%d", OMAP_SERIAL_NAME, uart->num);
202
203 if (cmdline_find_option(uart_name)) {
204 console_uart_id = uart->num;
205
206 if (console_loglevel >= CONSOLE_LOGLEVEL_DEBUG) {
207 uart_debug = true;
208 pr_info("%s used as console in debug mode: uart%d clocks will not be gated",
209 uart_name, uart->num);
210 }
211 }
212 } while (1);
213
214 return 0;
215}
216omap_postcore_initcall(omap_serial_early_init);
217
218/**
219 * omap_serial_init_port() - initialize single serial port
220 * @bdata: port specific board data pointer
221 * @info: platform specific data pointer
222 *
223 * This function initialies serial driver for given port only.
224 * Platforms can call this function instead of omap_serial_init()
225 * if they don't plan to use all available UARTs as serial ports.
226 *
227 * Don't mix calls to omap_serial_init_port() and omap_serial_init(),
228 * use only one of the two.
229 */
230void __init omap_serial_init_port(struct omap_board_data *bdata,
231 struct omap_uart_port_info *info)
232{
233 struct omap_uart_state *uart;
234 struct omap_hwmod *oh;
235 struct platform_device *pdev;
236 void *pdata = NULL;
237 u32 pdata_size = 0;
238 char *name;
239 struct omap_uart_port_info omap_up;
240
241 if (WARN_ON(!bdata))
242 return;
243 if (WARN_ON(bdata->id < 0))
244 return;
245 if (WARN_ON(bdata->id >= num_uarts))
246 return;
247
248 list_for_each_entry(uart, &uart_list, node)
249 if (bdata->id == uart->num)
250 break;
251 if (!info)
252 info = omap_serial_default_info;
253
254 oh = uart->oh;
255 name = OMAP_SERIAL_DRIVER_NAME;
256
257 omap_up.dma_enabled = info->dma_enabled;
258 omap_up.uartclk = OMAP24XX_BASE_BAUD * 16;
259 omap_up.flags = UPF_BOOT_AUTOCONF;
260 omap_up.get_context_loss_count = omap_pm_get_dev_context_loss_count;
261 omap_up.enable_wakeup = omap_uart_enable_wakeup;
262 omap_up.dma_rx_buf_size = info->dma_rx_buf_size;
263 omap_up.dma_rx_timeout = info->dma_rx_timeout;
264 omap_up.dma_rx_poll_rate = info->dma_rx_poll_rate;
265 omap_up.autosuspend_timeout = info->autosuspend_timeout;
266
267 pdata = &omap_up;
268 pdata_size = sizeof(struct omap_uart_port_info);
269
270 if (WARN_ON(!oh))
271 return;
272
273 pdev = omap_device_build(name, uart->num, oh, pdata, pdata_size);
274 if (IS_ERR(pdev)) {
275 WARN(1, "Could not build omap_device for %s: %s.\n", name,
276 oh->name);
277 return;
278 }
279
280 oh->mux = omap_hwmod_mux_init(bdata->pads, bdata->pads_cnt);
281
282 if (console_uart_id == bdata->id) {
283 omap_device_enable(pdev);
284 pm_runtime_set_active(&pdev->dev);
285 }
286
287 oh->dev_attr = uart;
288
289 if (((cpu_is_omap34xx() || cpu_is_omap44xx()) && bdata->pads)
290 && !uart_debug)
291 device_init_wakeup(&pdev->dev, true);
292}
293
294/**
295 * omap_serial_board_init() - initialize all supported serial ports
296 * @info: platform specific data pointer
297 *
298 * Initializes all available UARTs as serial ports. Platforms
299 * can call this function when they want to have default behaviour
300 * for serial ports (e.g initialize them all as serial ports).
301 */
302void __init omap_serial_board_init(struct omap_uart_port_info *info)
303{
304 struct omap_uart_state *uart;
305 struct omap_board_data bdata;
306
307 list_for_each_entry(uart, &uart_list, node) {
308 bdata.id = uart->num;
309 bdata.flags = 0;
310 bdata.pads = NULL;
311 bdata.pads_cnt = 0;
312
313 omap_serial_check_wakeup(&bdata, uart);
314
315 if (!info)
316 omap_serial_init_port(&bdata, NULL);
317 else
318 omap_serial_init_port(&bdata, &info[uart->num]);
319 }
320}
321
322/**
323 * omap_serial_init() - initialize all supported serial ports
324 *
325 * Initializes all available UARTs.
326 * Platforms can call this function when they want to have default behaviour
327 * for serial ports (e.g initialize them all as serial ports).
328 */
329void __init omap_serial_init(void)
330{
331 omap_serial_board_init(NULL);
332}
diff --git a/arch/arm/mach-omap2/twl-common.c b/arch/arm/mach-omap2/twl-common.c
deleted file mode 100644
index a72738eab009..000000000000
--- a/arch/arm/mach-omap2/twl-common.c
+++ /dev/null
@@ -1,564 +0,0 @@
1/*
2 * twl-common.c
3 *
4 * Copyright (C) 2011 Texas Instruments, Inc..
5 * Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * version 2 as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
19 * 02110-1301 USA
20 *
21 */
22
23#include <linux/i2c.h>
24#include <linux/i2c/twl.h>
25#include <linux/gpio.h>
26#include <linux/string.h>
27#include <linux/phy/phy.h>
28#include <linux/regulator/machine.h>
29#include <linux/regulator/fixed.h>
30
31#include "soc.h"
32#include "twl-common.h"
33#include "pm.h"
34#include "voltage.h"
35#include "mux.h"
36
37static struct i2c_board_info __initdata pmic_i2c_board_info = {
38 .addr = 0x48,
39 .flags = I2C_CLIENT_WAKE,
40};
41
42#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
43static int twl_set_voltage(void *data, int target_uV)
44{
45 struct voltagedomain *voltdm = (struct voltagedomain *)data;
46 return voltdm_scale(voltdm, target_uV);
47}
48
49static int twl_get_voltage(void *data)
50{
51 struct voltagedomain *voltdm = (struct voltagedomain *)data;
52 return voltdm_get_voltage(voltdm);
53}
54#endif
55
56void __init omap_pmic_init(int bus, u32 clkrate,
57 const char *pmic_type, int pmic_irq,
58 struct twl4030_platform_data *pmic_data)
59{
60 omap_mux_init_signal("sys_nirq", OMAP_PIN_INPUT_PULLUP | OMAP_PIN_OFF_WAKEUPENABLE);
61 strlcpy(pmic_i2c_board_info.type, pmic_type,
62 sizeof(pmic_i2c_board_info.type));
63 pmic_i2c_board_info.irq = pmic_irq;
64 pmic_i2c_board_info.platform_data = pmic_data;
65
66 omap_register_i2c_bus(bus, clkrate, &pmic_i2c_board_info, 1);
67}
68
69#ifdef CONFIG_ARCH_OMAP4
70void __init omap4_pmic_init(const char *pmic_type,
71 struct twl4030_platform_data *pmic_data,
72 struct i2c_board_info *devices, int nr_devices)
73{
74 /* PMIC part*/
75 unsigned int irq;
76
77 omap_mux_init_signal("sys_nirq1", OMAP_PIN_INPUT_PULLUP | OMAP_PIN_OFF_WAKEUPENABLE);
78 omap_mux_init_signal("fref_clk0_out.sys_drm_msecure", OMAP_PIN_OUTPUT);
79 irq = omap4_xlate_irq(7 + OMAP44XX_IRQ_GIC_START);
80 omap_pmic_init(1, 400, pmic_type, irq, pmic_data);
81
82 /* Register additional devices on i2c1 bus if needed */
83 if (devices)
84 i2c_register_board_info(1, devices, nr_devices);
85}
86#endif
87
88void __init omap_pmic_late_init(void)
89{
90 /* Init the OMAP TWL parameters (if PMIC has been registerd) */
91 if (!pmic_i2c_board_info.irq)
92 return;
93
94 omap3_twl_init();
95 omap4_twl_init();
96}
97
98#if defined(CONFIG_ARCH_OMAP3)
99static struct twl4030_usb_data omap3_usb_pdata = {
100 .usb_mode = T2_USB_MODE_ULPI,
101};
102
103static int omap3_batt_table[] = {
104/* 0 C */
10530800, 29500, 28300, 27100,
10626000, 24900, 23900, 22900, 22000, 21100, 20300, 19400, 18700, 17900,
10717200, 16500, 15900, 15300, 14700, 14100, 13600, 13100, 12600, 12100,
10811600, 11200, 10800, 10400, 10000, 9630, 9280, 8950, 8620, 8310,
1098020, 7730, 7460, 7200, 6950, 6710, 6470, 6250, 6040, 5830,
1105640, 5450, 5260, 5090, 4920, 4760, 4600, 4450, 4310, 4170,
1114040, 3910, 3790, 3670, 3550
112};
113
114static struct twl4030_bci_platform_data omap3_bci_pdata = {
115 .battery_tmp_tbl = omap3_batt_table,
116 .tblsize = ARRAY_SIZE(omap3_batt_table),
117};
118
119static struct twl4030_madc_platform_data omap3_madc_pdata = {
120 .irq_line = 1,
121};
122
123static struct twl4030_codec_data omap3_codec;
124
125static struct twl4030_audio_data omap3_audio_pdata = {
126 .audio_mclk = 26000000,
127 .codec = &omap3_codec,
128};
129
130static struct regulator_consumer_supply omap3_vdda_dac_supplies[] = {
131 REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"),
132};
133
134static struct regulator_init_data omap3_vdac_idata = {
135 .constraints = {
136 .min_uV = 1800000,
137 .max_uV = 1800000,
138 .valid_modes_mask = REGULATOR_MODE_NORMAL
139 | REGULATOR_MODE_STANDBY,
140 .valid_ops_mask = REGULATOR_CHANGE_MODE
141 | REGULATOR_CHANGE_STATUS,
142 },
143 .num_consumer_supplies = ARRAY_SIZE(omap3_vdda_dac_supplies),
144 .consumer_supplies = omap3_vdda_dac_supplies,
145};
146
147static struct regulator_consumer_supply omap3_vpll2_supplies[] = {
148 REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
149 REGULATOR_SUPPLY("vdds_dsi", "omapdss_dpi.0"),
150 REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi.0"),
151};
152
153static struct regulator_init_data omap3_vpll2_idata = {
154 .constraints = {
155 .min_uV = 1800000,
156 .max_uV = 1800000,
157 .valid_modes_mask = REGULATOR_MODE_NORMAL
158 | REGULATOR_MODE_STANDBY,
159 .valid_ops_mask = REGULATOR_CHANGE_MODE
160 | REGULATOR_CHANGE_STATUS,
161 },
162 .num_consumer_supplies = ARRAY_SIZE(omap3_vpll2_supplies),
163 .consumer_supplies = omap3_vpll2_supplies,
164};
165
166static struct regulator_consumer_supply omap3_vdd1_supply[] = {
167 REGULATOR_SUPPLY("vcc", "cpu0"),
168};
169
170static struct regulator_consumer_supply omap3_vdd2_supply[] = {
171 REGULATOR_SUPPLY("vcc", "l3_main.0"),
172};
173
174static struct regulator_init_data omap3_vdd1 = {
175 .constraints = {
176 .name = "vdd_mpu_iva",
177 .min_uV = 600000,
178 .max_uV = 1450000,
179 .valid_modes_mask = REGULATOR_MODE_NORMAL,
180 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
181 },
182 .num_consumer_supplies = ARRAY_SIZE(omap3_vdd1_supply),
183 .consumer_supplies = omap3_vdd1_supply,
184};
185
186static struct regulator_init_data omap3_vdd2 = {
187 .constraints = {
188 .name = "vdd_core",
189 .min_uV = 600000,
190 .max_uV = 1450000,
191 .valid_modes_mask = REGULATOR_MODE_NORMAL,
192 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
193 },
194 .num_consumer_supplies = ARRAY_SIZE(omap3_vdd2_supply),
195 .consumer_supplies = omap3_vdd2_supply,
196};
197
198static struct twl_regulator_driver_data omap3_vdd1_drvdata = {
199 .get_voltage = twl_get_voltage,
200 .set_voltage = twl_set_voltage,
201};
202
203static struct twl_regulator_driver_data omap3_vdd2_drvdata = {
204 .get_voltage = twl_get_voltage,
205 .set_voltage = twl_set_voltage,
206};
207
208void __init omap3_pmic_get_config(struct twl4030_platform_data *pmic_data,
209 u32 pdata_flags, u32 regulators_flags)
210{
211 if (!pmic_data->vdd1) {
212 omap3_vdd1.driver_data = &omap3_vdd1_drvdata;
213 omap3_vdd1_drvdata.data = voltdm_lookup("mpu_iva");
214 pmic_data->vdd1 = &omap3_vdd1;
215 }
216 if (!pmic_data->vdd2) {
217 omap3_vdd2.driver_data = &omap3_vdd2_drvdata;
218 omap3_vdd2_drvdata.data = voltdm_lookup("core");
219 pmic_data->vdd2 = &omap3_vdd2;
220 }
221
222 /* Common platform data configurations */
223 if (pdata_flags & TWL_COMMON_PDATA_USB && !pmic_data->usb)
224 pmic_data->usb = &omap3_usb_pdata;
225
226 if (pdata_flags & TWL_COMMON_PDATA_BCI && !pmic_data->bci)
227 pmic_data->bci = &omap3_bci_pdata;
228
229 if (pdata_flags & TWL_COMMON_PDATA_MADC && !pmic_data->madc)
230 pmic_data->madc = &omap3_madc_pdata;
231
232 if (pdata_flags & TWL_COMMON_PDATA_AUDIO && !pmic_data->audio)
233 pmic_data->audio = &omap3_audio_pdata;
234
235 /* Common regulator configurations */
236 if (regulators_flags & TWL_COMMON_REGULATOR_VDAC && !pmic_data->vdac)
237 pmic_data->vdac = &omap3_vdac_idata;
238
239 if (regulators_flags & TWL_COMMON_REGULATOR_VPLL2 && !pmic_data->vpll2)
240 pmic_data->vpll2 = &omap3_vpll2_idata;
241}
242#endif /* CONFIG_ARCH_OMAP3 */
243
244#if defined(CONFIG_ARCH_OMAP4)
245static struct twl4030_usb_data omap4_usb_pdata = {
246};
247
248static struct regulator_consumer_supply omap4_vdda_hdmi_dac_supplies[] = {
249 REGULATOR_SUPPLY("vdda_hdmi_dac", "omapdss_hdmi"),
250};
251
252static struct regulator_init_data omap4_vdac_idata = {
253 .constraints = {
254 .min_uV = 1800000,
255 .max_uV = 1800000,
256 .valid_modes_mask = REGULATOR_MODE_NORMAL
257 | REGULATOR_MODE_STANDBY,
258 .valid_ops_mask = REGULATOR_CHANGE_MODE
259 | REGULATOR_CHANGE_STATUS,
260 },
261 .num_consumer_supplies = ARRAY_SIZE(omap4_vdda_hdmi_dac_supplies),
262 .consumer_supplies = omap4_vdda_hdmi_dac_supplies,
263 .supply_regulator = "V2V1",
264};
265
266static struct regulator_init_data omap4_vaux2_idata = {
267 .constraints = {
268 .min_uV = 1200000,
269 .max_uV = 2800000,
270 .apply_uV = true,
271 .valid_modes_mask = REGULATOR_MODE_NORMAL
272 | REGULATOR_MODE_STANDBY,
273 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
274 | REGULATOR_CHANGE_MODE
275 | REGULATOR_CHANGE_STATUS,
276 },
277};
278
279static struct regulator_init_data omap4_vaux3_idata = {
280 .constraints = {
281 .min_uV = 1000000,
282 .max_uV = 3000000,
283 .apply_uV = true,
284 .valid_modes_mask = REGULATOR_MODE_NORMAL
285 | REGULATOR_MODE_STANDBY,
286 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
287 | REGULATOR_CHANGE_MODE
288 | REGULATOR_CHANGE_STATUS,
289 },
290};
291
292static struct regulator_consumer_supply omap4_vmmc_supply[] = {
293 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
294};
295
296/* VMMC1 for MMC1 card */
297static struct regulator_init_data omap4_vmmc_idata = {
298 .constraints = {
299 .min_uV = 1200000,
300 .max_uV = 3000000,
301 .apply_uV = true,
302 .valid_modes_mask = REGULATOR_MODE_NORMAL
303 | REGULATOR_MODE_STANDBY,
304 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
305 | REGULATOR_CHANGE_MODE
306 | REGULATOR_CHANGE_STATUS,
307 },
308 .num_consumer_supplies = ARRAY_SIZE(omap4_vmmc_supply),
309 .consumer_supplies = omap4_vmmc_supply,
310};
311
312static struct regulator_init_data omap4_vpp_idata = {
313 .constraints = {
314 .min_uV = 1800000,
315 .max_uV = 2500000,
316 .apply_uV = true,
317 .valid_modes_mask = REGULATOR_MODE_NORMAL
318 | REGULATOR_MODE_STANDBY,
319 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
320 | REGULATOR_CHANGE_MODE
321 | REGULATOR_CHANGE_STATUS,
322 },
323};
324
325static struct regulator_init_data omap4_vana_idata = {
326 .constraints = {
327 .min_uV = 2100000,
328 .max_uV = 2100000,
329 .valid_modes_mask = REGULATOR_MODE_NORMAL
330 | REGULATOR_MODE_STANDBY,
331 .valid_ops_mask = REGULATOR_CHANGE_MODE
332 | REGULATOR_CHANGE_STATUS,
333 },
334};
335
336static struct regulator_consumer_supply omap4_vcxio_supply[] = {
337 REGULATOR_SUPPLY("vdds_dsi", "omapdss_dss"),
338 REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi.0"),
339 REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi.1"),
340};
341
342static struct regulator_init_data omap4_vcxio_idata = {
343 .constraints = {
344 .min_uV = 1800000,
345 .max_uV = 1800000,
346 .valid_modes_mask = REGULATOR_MODE_NORMAL
347 | REGULATOR_MODE_STANDBY,
348 .valid_ops_mask = REGULATOR_CHANGE_MODE
349 | REGULATOR_CHANGE_STATUS,
350 .always_on = true,
351 },
352 .num_consumer_supplies = ARRAY_SIZE(omap4_vcxio_supply),
353 .consumer_supplies = omap4_vcxio_supply,
354 .supply_regulator = "V2V1",
355};
356
357static struct regulator_init_data omap4_vusb_idata = {
358 .constraints = {
359 .min_uV = 3300000,
360 .max_uV = 3300000,
361 .valid_modes_mask = REGULATOR_MODE_NORMAL
362 | REGULATOR_MODE_STANDBY,
363 .valid_ops_mask = REGULATOR_CHANGE_MODE
364 | REGULATOR_CHANGE_STATUS,
365 },
366};
367
368static struct regulator_init_data omap4_clk32kg_idata = {
369 .constraints = {
370 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
371 },
372};
373
374static struct regulator_consumer_supply omap4_vdd1_supply[] = {
375 REGULATOR_SUPPLY("vcc", "cpu0"),
376};
377
378static struct regulator_consumer_supply omap4_vdd2_supply[] = {
379 REGULATOR_SUPPLY("vcc", "iva.0"),
380};
381
382static struct regulator_consumer_supply omap4_vdd3_supply[] = {
383 REGULATOR_SUPPLY("vcc", "l3_main.0"),
384};
385
386static struct regulator_init_data omap4_vdd1 = {
387 .constraints = {
388 .name = "vdd_mpu",
389 .min_uV = 500000,
390 .max_uV = 1500000,
391 .valid_modes_mask = REGULATOR_MODE_NORMAL,
392 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
393 },
394 .num_consumer_supplies = ARRAY_SIZE(omap4_vdd1_supply),
395 .consumer_supplies = omap4_vdd1_supply,
396};
397
398static struct regulator_init_data omap4_vdd2 = {
399 .constraints = {
400 .name = "vdd_iva",
401 .min_uV = 500000,
402 .max_uV = 1500000,
403 .valid_modes_mask = REGULATOR_MODE_NORMAL,
404 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
405 },
406 .num_consumer_supplies = ARRAY_SIZE(omap4_vdd2_supply),
407 .consumer_supplies = omap4_vdd2_supply,
408};
409
410static struct regulator_init_data omap4_vdd3 = {
411 .constraints = {
412 .name = "vdd_core",
413 .min_uV = 500000,
414 .max_uV = 1500000,
415 .valid_modes_mask = REGULATOR_MODE_NORMAL,
416 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
417 },
418 .num_consumer_supplies = ARRAY_SIZE(omap4_vdd3_supply),
419 .consumer_supplies = omap4_vdd3_supply,
420};
421
422
423static struct twl_regulator_driver_data omap4_vdd1_drvdata = {
424 .get_voltage = twl_get_voltage,
425 .set_voltage = twl_set_voltage,
426};
427
428static struct twl_regulator_driver_data omap4_vdd2_drvdata = {
429 .get_voltage = twl_get_voltage,
430 .set_voltage = twl_set_voltage,
431};
432
433static struct twl_regulator_driver_data omap4_vdd3_drvdata = {
434 .get_voltage = twl_get_voltage,
435 .set_voltage = twl_set_voltage,
436};
437
438static struct regulator_consumer_supply omap4_v1v8_supply[] = {
439 REGULATOR_SUPPLY("vio", "1-004b"),
440};
441
442static struct regulator_init_data omap4_v1v8_idata = {
443 .constraints = {
444 .min_uV = 1800000,
445 .max_uV = 1800000,
446 .valid_modes_mask = REGULATOR_MODE_NORMAL
447 | REGULATOR_MODE_STANDBY,
448 .valid_ops_mask = REGULATOR_CHANGE_MODE
449 | REGULATOR_CHANGE_STATUS,
450 .always_on = true,
451 },
452 .num_consumer_supplies = ARRAY_SIZE(omap4_v1v8_supply),
453 .consumer_supplies = omap4_v1v8_supply,
454};
455
456static struct regulator_consumer_supply omap4_v2v1_supply[] = {
457 REGULATOR_SUPPLY("v2v1", "1-004b"),
458};
459
460static struct regulator_init_data omap4_v2v1_idata = {
461 .constraints = {
462 .min_uV = 2100000,
463 .max_uV = 2100000,
464 .valid_modes_mask = REGULATOR_MODE_NORMAL
465 | REGULATOR_MODE_STANDBY,
466 .valid_ops_mask = REGULATOR_CHANGE_MODE
467 | REGULATOR_CHANGE_STATUS,
468 },
469 .num_consumer_supplies = ARRAY_SIZE(omap4_v2v1_supply),
470 .consumer_supplies = omap4_v2v1_supply,
471};
472
473void __init omap4_pmic_get_config(struct twl4030_platform_data *pmic_data,
474 u32 pdata_flags, u32 regulators_flags)
475{
476 if (!pmic_data->vdd1) {
477 omap4_vdd1.driver_data = &omap4_vdd1_drvdata;
478 omap4_vdd1_drvdata.data = voltdm_lookup("mpu");
479 pmic_data->vdd1 = &omap4_vdd1;
480 }
481
482 if (!pmic_data->vdd2) {
483 omap4_vdd2.driver_data = &omap4_vdd2_drvdata;
484 omap4_vdd2_drvdata.data = voltdm_lookup("iva");
485 pmic_data->vdd2 = &omap4_vdd2;
486 }
487
488 if (!pmic_data->vdd3) {
489 omap4_vdd3.driver_data = &omap4_vdd3_drvdata;
490 omap4_vdd3_drvdata.data = voltdm_lookup("core");
491 pmic_data->vdd3 = &omap4_vdd3;
492 }
493
494 /* Common platform data configurations */
495 if (pdata_flags & TWL_COMMON_PDATA_USB && !pmic_data->usb)
496 pmic_data->usb = &omap4_usb_pdata;
497
498 /* Common regulator configurations */
499 if (regulators_flags & TWL_COMMON_REGULATOR_VDAC && !pmic_data->vdac)
500 pmic_data->vdac = &omap4_vdac_idata;
501
502 if (regulators_flags & TWL_COMMON_REGULATOR_VAUX2 && !pmic_data->vaux2)
503 pmic_data->vaux2 = &omap4_vaux2_idata;
504
505 if (regulators_flags & TWL_COMMON_REGULATOR_VAUX3 && !pmic_data->vaux3)
506 pmic_data->vaux3 = &omap4_vaux3_idata;
507
508 if (regulators_flags & TWL_COMMON_REGULATOR_VMMC && !pmic_data->vmmc)
509 pmic_data->vmmc = &omap4_vmmc_idata;
510
511 if (regulators_flags & TWL_COMMON_REGULATOR_VPP && !pmic_data->vpp)
512 pmic_data->vpp = &omap4_vpp_idata;
513
514 if (regulators_flags & TWL_COMMON_REGULATOR_VANA && !pmic_data->vana)
515 pmic_data->vana = &omap4_vana_idata;
516
517 if (regulators_flags & TWL_COMMON_REGULATOR_VCXIO && !pmic_data->vcxio)
518 pmic_data->vcxio = &omap4_vcxio_idata;
519
520 if (regulators_flags & TWL_COMMON_REGULATOR_VUSB && !pmic_data->vusb)
521 pmic_data->vusb = &omap4_vusb_idata;
522
523 if (regulators_flags & TWL_COMMON_REGULATOR_CLK32KG &&
524 !pmic_data->clk32kg)
525 pmic_data->clk32kg = &omap4_clk32kg_idata;
526
527 if (regulators_flags & TWL_COMMON_REGULATOR_V1V8 && !pmic_data->v1v8)
528 pmic_data->v1v8 = &omap4_v1v8_idata;
529
530 if (regulators_flags & TWL_COMMON_REGULATOR_V2V1 && !pmic_data->v2v1)
531 pmic_data->v2v1 = &omap4_v2v1_idata;
532}
533#endif /* CONFIG_ARCH_OMAP4 */
534
535#if IS_ENABLED(CONFIG_SND_OMAP_SOC_OMAP_TWL4030)
536#include <linux/platform_data/omap-twl4030.h>
537
538/* Commonly used configuration */
539static struct omap_tw4030_pdata omap_twl4030_audio_data;
540
541static struct platform_device audio_device = {
542 .name = "omap-twl4030",
543 .id = -1,
544};
545
546void omap_twl4030_audio_init(char *card_name,
547 struct omap_tw4030_pdata *pdata)
548{
549 if (!pdata)
550 pdata = &omap_twl4030_audio_data;
551
552 pdata->card_name = card_name;
553
554 audio_device.dev.platform_data = pdata;
555 platform_device_register(&audio_device);
556}
557
558#else /* SOC_OMAP_TWL4030 */
559void omap_twl4030_audio_init(char *card_name,
560 struct omap_tw4030_pdata *pdata)
561{
562 return;
563}
564#endif /* SOC_OMAP_TWL4030 */
diff --git a/arch/arm/mach-omap2/twl-common.h b/arch/arm/mach-omap2/twl-common.h
deleted file mode 100644
index 24b65d081b69..000000000000
--- a/arch/arm/mach-omap2/twl-common.h
+++ /dev/null
@@ -1,66 +0,0 @@
1#ifndef __OMAP_PMIC_COMMON__
2#define __OMAP_PMIC_COMMON__
3
4#include "common.h"
5
6#define TWL_COMMON_PDATA_USB (1 << 0)
7#define TWL_COMMON_PDATA_BCI (1 << 1)
8#define TWL_COMMON_PDATA_MADC (1 << 2)
9#define TWL_COMMON_PDATA_AUDIO (1 << 3)
10
11/* Common LDO regulators for TWL4030/TWL6030 */
12#define TWL_COMMON_REGULATOR_VDAC (1 << 0)
13#define TWL_COMMON_REGULATOR_VAUX1 (1 << 1)
14#define TWL_COMMON_REGULATOR_VAUX2 (1 << 2)
15#define TWL_COMMON_REGULATOR_VAUX3 (1 << 3)
16
17/* TWL6030 LDO regulators */
18#define TWL_COMMON_REGULATOR_VMMC (1 << 4)
19#define TWL_COMMON_REGULATOR_VPP (1 << 5)
20#define TWL_COMMON_REGULATOR_VUSIM (1 << 6)
21#define TWL_COMMON_REGULATOR_VANA (1 << 7)
22#define TWL_COMMON_REGULATOR_VCXIO (1 << 8)
23#define TWL_COMMON_REGULATOR_VUSB (1 << 9)
24#define TWL_COMMON_REGULATOR_CLK32KG (1 << 10)
25#define TWL_COMMON_REGULATOR_V1V8 (1 << 11)
26#define TWL_COMMON_REGULATOR_V2V1 (1 << 12)
27
28/* TWL4030 LDO regulators */
29#define TWL_COMMON_REGULATOR_VPLL1 (1 << 4)
30#define TWL_COMMON_REGULATOR_VPLL2 (1 << 5)
31
32
33struct twl4030_platform_data;
34struct twl6040_platform_data;
35struct omap_tw4030_pdata;
36struct i2c_board_info;
37
38void omap_pmic_init(int bus, u32 clkrate, const char *pmic_type, int pmic_irq,
39 struct twl4030_platform_data *pmic_data);
40void omap_pmic_late_init(void);
41
42static inline void omap2_pmic_init(const char *pmic_type,
43 struct twl4030_platform_data *pmic_data)
44{
45 omap_pmic_init(2, 2600, pmic_type, 7 + OMAP_INTC_START, pmic_data);
46}
47
48static inline void omap3_pmic_init(const char *pmic_type,
49 struct twl4030_platform_data *pmic_data)
50{
51 omap_pmic_init(1, 2600, pmic_type, 7 + OMAP_INTC_START, pmic_data);
52}
53
54void omap4_pmic_init(const char *pmic_type,
55 struct twl4030_platform_data *pmic_data,
56 struct i2c_board_info *devices, int nr_devices);
57
58void omap3_pmic_get_config(struct twl4030_platform_data *pmic_data,
59 u32 pdata_flags, u32 regulators_flags);
60
61void omap4_pmic_get_config(struct twl4030_platform_data *pmic_data,
62 u32 pdata_flags, u32 regulators_flags);
63
64void omap_twl4030_audio_init(char *card_name, struct omap_tw4030_pdata *pdata);
65
66#endif /* __OMAP_PMIC_COMMON__ */
diff --git a/arch/arm/mach-omap2/usb-host.c b/arch/arm/mach-omap2/usb-host.c
deleted file mode 100644
index 745367c0c2bb..000000000000
--- a/arch/arm/mach-omap2/usb-host.c
+++ /dev/null
@@ -1,496 +0,0 @@
1/*
2 * usb-host.c - OMAP USB Host
3 *
4 * This file will contain the board specific details for the
5 * Synopsys EHCI/OHCI host controller on OMAP3430 and onwards
6 *
7 * Copyright (C) 2007-2011 Texas Instruments
8 * Author: Vikram Pandita <vikram.pandita@ti.com>
9 * Author: Keshava Munegowda <keshava_mgowda@ti.com>
10 *
11 * Generalization by:
12 * Felipe Balbi <balbi@ti.com>
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 */
18
19#include <linux/types.h>
20#include <linux/errno.h>
21#include <linux/delay.h>
22#include <linux/platform_device.h>
23#include <linux/slab.h>
24#include <linux/dma-mapping.h>
25#include <linux/regulator/machine.h>
26#include <linux/regulator/fixed.h>
27#include <linux/string.h>
28#include <linux/io.h>
29#include <linux/gpio.h>
30#include <linux/usb/phy.h>
31#include <linux/usb/usb_phy_generic.h>
32
33#include "soc.h"
34#include "omap_device.h"
35#include "mux.h"
36#include "usb.h"
37
38#ifdef CONFIG_MFD_OMAP_USB_HOST
39
40#define OMAP_USBHS_DEVICE "usbhs_omap"
41#define OMAP_USBTLL_DEVICE "usbhs_tll"
42#define USBHS_UHH_HWMODNAME "usb_host_hs"
43#define USBHS_TLL_HWMODNAME "usb_tll_hs"
44
45/* MUX settings for EHCI pins */
46/*
47 * setup_ehci_io_mux - initialize IO pad mux for USBHOST
48 */
49static void __init setup_ehci_io_mux(const enum usbhs_omap_port_mode *port_mode)
50{
51 switch (port_mode[0]) {
52 case OMAP_EHCI_PORT_MODE_PHY:
53 omap_mux_init_signal("hsusb1_stp", OMAP_PIN_OUTPUT);
54 omap_mux_init_signal("hsusb1_clk", OMAP_PIN_OUTPUT);
55 omap_mux_init_signal("hsusb1_dir", OMAP_PIN_INPUT_PULLDOWN);
56 omap_mux_init_signal("hsusb1_nxt", OMAP_PIN_INPUT_PULLDOWN);
57 omap_mux_init_signal("hsusb1_data0", OMAP_PIN_INPUT_PULLDOWN);
58 omap_mux_init_signal("hsusb1_data1", OMAP_PIN_INPUT_PULLDOWN);
59 omap_mux_init_signal("hsusb1_data2", OMAP_PIN_INPUT_PULLDOWN);
60 omap_mux_init_signal("hsusb1_data3", OMAP_PIN_INPUT_PULLDOWN);
61 omap_mux_init_signal("hsusb1_data4", OMAP_PIN_INPUT_PULLDOWN);
62 omap_mux_init_signal("hsusb1_data5", OMAP_PIN_INPUT_PULLDOWN);
63 omap_mux_init_signal("hsusb1_data6", OMAP_PIN_INPUT_PULLDOWN);
64 omap_mux_init_signal("hsusb1_data7", OMAP_PIN_INPUT_PULLDOWN);
65 break;
66 case OMAP_EHCI_PORT_MODE_TLL:
67 omap_mux_init_signal("hsusb1_tll_stp",
68 OMAP_PIN_INPUT_PULLUP);
69 omap_mux_init_signal("hsusb1_tll_clk",
70 OMAP_PIN_INPUT_PULLDOWN);
71 omap_mux_init_signal("hsusb1_tll_dir",
72 OMAP_PIN_INPUT_PULLDOWN);
73 omap_mux_init_signal("hsusb1_tll_nxt",
74 OMAP_PIN_INPUT_PULLDOWN);
75 omap_mux_init_signal("hsusb1_tll_data0",
76 OMAP_PIN_INPUT_PULLDOWN);
77 omap_mux_init_signal("hsusb1_tll_data1",
78 OMAP_PIN_INPUT_PULLDOWN);
79 omap_mux_init_signal("hsusb1_tll_data2",
80 OMAP_PIN_INPUT_PULLDOWN);
81 omap_mux_init_signal("hsusb1_tll_data3",
82 OMAP_PIN_INPUT_PULLDOWN);
83 omap_mux_init_signal("hsusb1_tll_data4",
84 OMAP_PIN_INPUT_PULLDOWN);
85 omap_mux_init_signal("hsusb1_tll_data5",
86 OMAP_PIN_INPUT_PULLDOWN);
87 omap_mux_init_signal("hsusb1_tll_data6",
88 OMAP_PIN_INPUT_PULLDOWN);
89 omap_mux_init_signal("hsusb1_tll_data7",
90 OMAP_PIN_INPUT_PULLDOWN);
91 break;
92 case OMAP_USBHS_PORT_MODE_UNUSED:
93 /* FALLTHROUGH */
94 default:
95 break;
96 }
97
98 switch (port_mode[1]) {
99 case OMAP_EHCI_PORT_MODE_PHY:
100 omap_mux_init_signal("hsusb2_stp", OMAP_PIN_OUTPUT);
101 omap_mux_init_signal("hsusb2_clk", OMAP_PIN_OUTPUT);
102 omap_mux_init_signal("hsusb2_dir", OMAP_PIN_INPUT_PULLDOWN);
103 omap_mux_init_signal("hsusb2_nxt", OMAP_PIN_INPUT_PULLDOWN);
104 omap_mux_init_signal("hsusb2_data0",
105 OMAP_PIN_INPUT_PULLDOWN);
106 omap_mux_init_signal("hsusb2_data1",
107 OMAP_PIN_INPUT_PULLDOWN);
108 omap_mux_init_signal("hsusb2_data2",
109 OMAP_PIN_INPUT_PULLDOWN);
110 omap_mux_init_signal("hsusb2_data3",
111 OMAP_PIN_INPUT_PULLDOWN);
112 omap_mux_init_signal("hsusb2_data4",
113 OMAP_PIN_INPUT_PULLDOWN);
114 omap_mux_init_signal("hsusb2_data5",
115 OMAP_PIN_INPUT_PULLDOWN);
116 omap_mux_init_signal("hsusb2_data6",
117 OMAP_PIN_INPUT_PULLDOWN);
118 omap_mux_init_signal("hsusb2_data7",
119 OMAP_PIN_INPUT_PULLDOWN);
120 break;
121 case OMAP_EHCI_PORT_MODE_TLL:
122 omap_mux_init_signal("hsusb2_tll_stp",
123 OMAP_PIN_INPUT_PULLUP);
124 omap_mux_init_signal("hsusb2_tll_clk",
125 OMAP_PIN_INPUT_PULLDOWN);
126 omap_mux_init_signal("hsusb2_tll_dir",
127 OMAP_PIN_INPUT_PULLDOWN);
128 omap_mux_init_signal("hsusb2_tll_nxt",
129 OMAP_PIN_INPUT_PULLDOWN);
130 omap_mux_init_signal("hsusb2_tll_data0",
131 OMAP_PIN_INPUT_PULLDOWN);
132 omap_mux_init_signal("hsusb2_tll_data1",
133 OMAP_PIN_INPUT_PULLDOWN);
134 omap_mux_init_signal("hsusb2_tll_data2",
135 OMAP_PIN_INPUT_PULLDOWN);
136 omap_mux_init_signal("hsusb2_tll_data3",
137 OMAP_PIN_INPUT_PULLDOWN);
138 omap_mux_init_signal("hsusb2_tll_data4",
139 OMAP_PIN_INPUT_PULLDOWN);
140 omap_mux_init_signal("hsusb2_tll_data5",
141 OMAP_PIN_INPUT_PULLDOWN);
142 omap_mux_init_signal("hsusb2_tll_data6",
143 OMAP_PIN_INPUT_PULLDOWN);
144 omap_mux_init_signal("hsusb2_tll_data7",
145 OMAP_PIN_INPUT_PULLDOWN);
146 break;
147 case OMAP_USBHS_PORT_MODE_UNUSED:
148 /* FALLTHROUGH */
149 default:
150 break;
151 }
152
153 switch (port_mode[2]) {
154 case OMAP_EHCI_PORT_MODE_PHY:
155 printk(KERN_WARNING "Port3 can't be used in PHY mode\n");
156 break;
157 case OMAP_EHCI_PORT_MODE_TLL:
158 omap_mux_init_signal("hsusb3_tll_stp",
159 OMAP_PIN_INPUT_PULLUP);
160 omap_mux_init_signal("hsusb3_tll_clk",
161 OMAP_PIN_INPUT_PULLDOWN);
162 omap_mux_init_signal("hsusb3_tll_dir",
163 OMAP_PIN_INPUT_PULLDOWN);
164 omap_mux_init_signal("hsusb3_tll_nxt",
165 OMAP_PIN_INPUT_PULLDOWN);
166 omap_mux_init_signal("hsusb3_tll_data0",
167 OMAP_PIN_INPUT_PULLDOWN);
168 omap_mux_init_signal("hsusb3_tll_data1",
169 OMAP_PIN_INPUT_PULLDOWN);
170 omap_mux_init_signal("hsusb3_tll_data2",
171 OMAP_PIN_INPUT_PULLDOWN);
172 omap_mux_init_signal("hsusb3_tll_data3",
173 OMAP_PIN_INPUT_PULLDOWN);
174 omap_mux_init_signal("hsusb3_tll_data4",
175 OMAP_PIN_INPUT_PULLDOWN);
176 omap_mux_init_signal("hsusb3_tll_data5",
177 OMAP_PIN_INPUT_PULLDOWN);
178 omap_mux_init_signal("hsusb3_tll_data6",
179 OMAP_PIN_INPUT_PULLDOWN);
180 omap_mux_init_signal("hsusb3_tll_data7",
181 OMAP_PIN_INPUT_PULLDOWN);
182 break;
183 case OMAP_USBHS_PORT_MODE_UNUSED:
184 /* FALLTHROUGH */
185 default:
186 break;
187 }
188
189 return;
190}
191
192static void __init setup_ohci_io_mux(const enum usbhs_omap_port_mode *port_mode)
193{
194 switch (port_mode[0]) {
195 case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
196 case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM:
197 case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0:
198 case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM:
199 omap_mux_init_signal("mm1_rxdp",
200 OMAP_PIN_INPUT_PULLDOWN);
201 omap_mux_init_signal("mm1_rxdm",
202 OMAP_PIN_INPUT_PULLDOWN);
203 /* FALLTHROUGH */
204 case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM:
205 case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM:
206 omap_mux_init_signal("mm1_rxrcv",
207 OMAP_PIN_INPUT_PULLDOWN);
208 /* FALLTHROUGH */
209 case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0:
210 case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0:
211 omap_mux_init_signal("mm1_txen_n", OMAP_PIN_OUTPUT);
212 /* FALLTHROUGH */
213 case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0:
214 case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM:
215 omap_mux_init_signal("mm1_txse0",
216 OMAP_PIN_INPUT_PULLDOWN);
217 omap_mux_init_signal("mm1_txdat",
218 OMAP_PIN_INPUT_PULLDOWN);
219 break;
220 case OMAP_USBHS_PORT_MODE_UNUSED:
221 /* FALLTHROUGH */
222 default:
223 break;
224 }
225 switch (port_mode[1]) {
226 case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
227 case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM:
228 case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0:
229 case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM:
230 omap_mux_init_signal("mm2_rxdp",
231 OMAP_PIN_INPUT_PULLDOWN);
232 omap_mux_init_signal("mm2_rxdm",
233 OMAP_PIN_INPUT_PULLDOWN);
234 /* FALLTHROUGH */
235 case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM:
236 case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM:
237 omap_mux_init_signal("mm2_rxrcv",
238 OMAP_PIN_INPUT_PULLDOWN);
239 /* FALLTHROUGH */
240 case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0:
241 case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0:
242 omap_mux_init_signal("mm2_txen_n", OMAP_PIN_OUTPUT);
243 /* FALLTHROUGH */
244 case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0:
245 case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM:
246 omap_mux_init_signal("mm2_txse0",
247 OMAP_PIN_INPUT_PULLDOWN);
248 omap_mux_init_signal("mm2_txdat",
249 OMAP_PIN_INPUT_PULLDOWN);
250 break;
251 case OMAP_USBHS_PORT_MODE_UNUSED:
252 /* FALLTHROUGH */
253 default:
254 break;
255 }
256 switch (port_mode[2]) {
257 case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
258 case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM:
259 case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0:
260 case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM:
261 omap_mux_init_signal("mm3_rxdp",
262 OMAP_PIN_INPUT_PULLDOWN);
263 omap_mux_init_signal("mm3_rxdm",
264 OMAP_PIN_INPUT_PULLDOWN);
265 /* FALLTHROUGH */
266 case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM:
267 case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM:
268 omap_mux_init_signal("mm3_rxrcv",
269 OMAP_PIN_INPUT_PULLDOWN);
270 /* FALLTHROUGH */
271 case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0:
272 case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0:
273 omap_mux_init_signal("mm3_txen_n", OMAP_PIN_OUTPUT);
274 /* FALLTHROUGH */
275 case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0:
276 case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM:
277 omap_mux_init_signal("mm3_txse0",
278 OMAP_PIN_INPUT_PULLDOWN);
279 omap_mux_init_signal("mm3_txdat",
280 OMAP_PIN_INPUT_PULLDOWN);
281 break;
282 case OMAP_USBHS_PORT_MODE_UNUSED:
283 /* FALLTHROUGH */
284 default:
285 break;
286 }
287}
288
289void __init usbhs_init(struct usbhs_omap_platform_data *pdata)
290{
291 struct omap_hwmod *uhh_hwm, *tll_hwm;
292 struct platform_device *pdev;
293 int bus_id = -1;
294
295 if (cpu_is_omap34xx()) {
296 setup_ehci_io_mux(pdata->port_mode);
297 setup_ohci_io_mux(pdata->port_mode);
298
299 if (omap_rev() <= OMAP3430_REV_ES2_1)
300 pdata->single_ulpi_bypass = true;
301
302 }
303
304 uhh_hwm = omap_hwmod_lookup(USBHS_UHH_HWMODNAME);
305 if (!uhh_hwm) {
306 pr_err("Could not look up %s\n", USBHS_UHH_HWMODNAME);
307 return;
308 }
309
310 tll_hwm = omap_hwmod_lookup(USBHS_TLL_HWMODNAME);
311 if (!tll_hwm) {
312 pr_err("Could not look up %s\n", USBHS_TLL_HWMODNAME);
313 return;
314 }
315
316 pdev = omap_device_build(OMAP_USBTLL_DEVICE, bus_id, tll_hwm,
317 pdata, sizeof(*pdata));
318 if (IS_ERR(pdev)) {
319 pr_err("Could not build hwmod device %s\n",
320 USBHS_TLL_HWMODNAME);
321 return;
322 }
323
324 pdev = omap_device_build(OMAP_USBHS_DEVICE, bus_id, uhh_hwm,
325 pdata, sizeof(*pdata));
326 if (IS_ERR(pdev)) {
327 pr_err("Could not build hwmod devices %s\n",
328 USBHS_UHH_HWMODNAME);
329 return;
330 }
331}
332
333#else
334
335void __init usbhs_init(struct usbhs_omap_platform_data *pdata)
336{
337}
338
339#endif
340
341/* Template for PHY regulators */
342static struct fixed_voltage_config hsusb_reg_config = {
343 /* .supply_name filled later */
344 .microvolts = 3300000,
345 .gpio = -1, /* updated later */
346 .startup_delay = 70000, /* 70msec */
347 .enable_high = 1, /* updated later */
348 .enabled_at_boot = 0, /* keep in RESET */
349 /* .init_data filled later */
350};
351
352static const char *nop_name = "usb_phy_generic"; /* NOP PHY driver */
353static const char *reg_name = "reg-fixed-voltage"; /* Regulator driver */
354
355/**
356 * usbhs_add_regulator - Add a gpio based fixed voltage regulator device
357 * @name: name for the regulator
358 * @dev_id: device id of the device this regulator supplies power to
359 * @dev_supply: supply name that the device expects
360 * @gpio: GPIO number
361 * @polarity: 1 - Active high, 0 - Active low
362 */
363static int usbhs_add_regulator(char *name, char *dev_id, char *dev_supply,
364 int gpio, int polarity)
365{
366 struct regulator_consumer_supply *supplies;
367 struct regulator_init_data *reg_data;
368 struct fixed_voltage_config *config;
369 struct platform_device *pdev;
370 struct platform_device_info pdevinfo;
371 int ret = -ENOMEM;
372
373 supplies = kzalloc(sizeof(*supplies), GFP_KERNEL);
374 if (!supplies)
375 return -ENOMEM;
376
377 supplies->supply = dev_supply;
378 supplies->dev_name = dev_id;
379
380 reg_data = kzalloc(sizeof(*reg_data), GFP_KERNEL);
381 if (!reg_data)
382 goto err_data;
383
384 reg_data->constraints.valid_ops_mask = REGULATOR_CHANGE_STATUS;
385 reg_data->consumer_supplies = supplies;
386 reg_data->num_consumer_supplies = 1;
387
388 config = kmemdup(&hsusb_reg_config, sizeof(hsusb_reg_config),
389 GFP_KERNEL);
390 if (!config)
391 goto err_config;
392
393 config->supply_name = kstrdup(name, GFP_KERNEL);
394 if (!config->supply_name)
395 goto err_supplyname;
396
397 config->gpio = gpio;
398 config->enable_high = polarity;
399 config->init_data = reg_data;
400
401 /* create a regulator device */
402 memset(&pdevinfo, 0, sizeof(pdevinfo));
403 pdevinfo.name = reg_name;
404 pdevinfo.id = PLATFORM_DEVID_AUTO;
405 pdevinfo.data = config;
406 pdevinfo.size_data = sizeof(*config);
407
408 pdev = platform_device_register_full(&pdevinfo);
409 if (IS_ERR(pdev)) {
410 ret = PTR_ERR(pdev);
411 pr_err("%s: Failed registering regulator %s for %s : %d\n",
412 __func__, name, dev_id, ret);
413 goto err_register;
414 }
415
416 return 0;
417
418err_register:
419 kfree(config->supply_name);
420err_supplyname:
421 kfree(config);
422err_config:
423 kfree(reg_data);
424err_data:
425 kfree(supplies);
426 return ret;
427}
428
429#define MAX_STR 20
430
431int usbhs_init_phys(struct usbhs_phy_data *phy, int num_phys)
432{
433 char rail_name[MAX_STR];
434 int i;
435 struct platform_device *pdev;
436 char *phy_id;
437 struct platform_device_info pdevinfo;
438 struct usb_phy_generic_platform_data nop_pdata;
439
440 for (i = 0; i < num_phys; i++) {
441
442 if (!phy->port) {
443 pr_err("%s: Invalid port 0. Must start from 1\n",
444 __func__);
445 continue;
446 }
447
448 /* do we need a NOP PHY device ? */
449 if (!gpio_is_valid(phy->reset_gpio) &&
450 !gpio_is_valid(phy->vcc_gpio))
451 continue;
452
453 phy_id = kmalloc(MAX_STR, GFP_KERNEL);
454 if (!phy_id) {
455 pr_err("%s: kmalloc() failed\n", __func__);
456 return -ENOMEM;
457 }
458
459 /* set platform data */
460 memset(&nop_pdata, 0, sizeof(nop_pdata));
461 if (gpio_is_valid(phy->vcc_gpio))
462 nop_pdata.needs_vcc = true;
463 nop_pdata.gpio_reset = phy->reset_gpio;
464 nop_pdata.type = USB_PHY_TYPE_USB2;
465
466 /* create a NOP PHY device */
467 memset(&pdevinfo, 0, sizeof(pdevinfo));
468 pdevinfo.name = nop_name;
469 pdevinfo.id = phy->port;
470 pdevinfo.data = &nop_pdata;
471 pdevinfo.size_data =
472 sizeof(struct usb_phy_generic_platform_data);
473 scnprintf(phy_id, MAX_STR, "usb_phy_generic.%d",
474 phy->port);
475 pdev = platform_device_register_full(&pdevinfo);
476 if (IS_ERR(pdev)) {
477 pr_err("%s: Failed to register device %s : %ld\n",
478 __func__, phy_id, PTR_ERR(pdev));
479 kfree(phy_id);
480 continue;
481 }
482
483 usb_bind_phy("ehci-omap.0", phy->port - 1, phy_id);
484
485 /* Do we need VCC regulator ? */
486 if (gpio_is_valid(phy->vcc_gpio)) {
487 scnprintf(rail_name, MAX_STR, "hsusb%d_vcc", phy->port);
488 usbhs_add_regulator(rail_name, phy_id, "vcc",
489 phy->vcc_gpio, phy->vcc_polarity);
490 }
491
492 phy++;
493 }
494
495 return 0;
496}
diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c
deleted file mode 100644
index e4562b2b973b..000000000000
--- a/arch/arm/mach-omap2/usb-musb.c
+++ /dev/null
@@ -1,106 +0,0 @@
1/*
2 * linux/arch/arm/mach-omap2/usb-musb.c
3 *
4 * This file will contain the board specific details for the
5 * MENTOR USB OTG controller on OMAP3430
6 *
7 * Copyright (C) 2007-2008 Texas Instruments
8 * Copyright (C) 2008 Nokia Corporation
9 * Author: Vikram Pandita
10 *
11 * Generalization by:
12 * Felipe Balbi <felipe.balbi@nokia.com>
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 */
18
19#include <linux/types.h>
20#include <linux/errno.h>
21#include <linux/delay.h>
22#include <linux/platform_device.h>
23#include <linux/clk.h>
24#include <linux/dma-mapping.h>
25#include <linux/io.h>
26#include <linux/usb/musb.h>
27
28#include "omap_device.h"
29#include "soc.h"
30#include "mux.h"
31#include "usb.h"
32
33static struct musb_hdrc_config musb_config = {
34 .multipoint = 1,
35 .dyn_fifo = 1,
36 .num_eps = 16,
37 .ram_bits = 12,
38};
39
40static struct musb_hdrc_platform_data musb_plat = {
41 .mode = MUSB_OTG,
42
43 /* .clock is set dynamically */
44 .config = &musb_config,
45
46 /* REVISIT charge pump on TWL4030 can supply up to
47 * 100 mA ... but this value is board-specific, like
48 * "mode", and should be passed to usb_musb_init().
49 */
50 .power = 50, /* up to 100 mA */
51};
52
53static u64 musb_dmamask = DMA_BIT_MASK(32);
54
55static struct omap_musb_board_data musb_default_board_data = {
56 .interface_type = MUSB_INTERFACE_ULPI,
57 .mode = MUSB_OTG,
58 .power = 100,
59};
60
61void __init usb_musb_init(struct omap_musb_board_data *musb_board_data)
62{
63 struct omap_hwmod *oh;
64 struct platform_device *pdev;
65 struct device *dev;
66 int bus_id = -1;
67 const char *oh_name, *name;
68 struct omap_musb_board_data *board_data;
69
70 if (musb_board_data)
71 board_data = musb_board_data;
72 else
73 board_data = &musb_default_board_data;
74
75 /*
76 * REVISIT: This line can be removed once all the platforms using
77 * musb_core.c have been converted to use use clkdev.
78 */
79 musb_plat.clock = "ick";
80 musb_plat.board_data = board_data;
81 musb_plat.power = board_data->power >> 1;
82 musb_plat.mode = board_data->mode;
83 musb_plat.extvbus = board_data->extvbus;
84
85 oh_name = "usb_otg_hs";
86 name = "musb-omap2430";
87
88 oh = omap_hwmod_lookup(oh_name);
89 if (WARN(!oh, "%s: could not find omap_hwmod for %s\n",
90 __func__, oh_name))
91 return;
92
93 pdev = omap_device_build(name, bus_id, oh, &musb_plat,
94 sizeof(musb_plat));
95 if (IS_ERR(pdev)) {
96 pr_err("Could not build omap_device for %s %s\n",
97 name, oh_name);
98 return;
99 }
100
101 dev = &pdev->dev;
102 get_device(dev);
103 dev->dma_mask = &musb_dmamask;
104 dev->coherent_dma_mask = musb_dmamask;
105 put_device(dev);
106}
diff --git a/arch/arm/mach-omap2/usb-tusb6010.c b/arch/arm/mach-omap2/usb-tusb6010.c
index e554d9e66a1c..c2a6fbd7f8a9 100644
--- a/arch/arm/mach-omap2/usb-tusb6010.c
+++ b/arch/arm/mach-omap2/usb-tusb6010.c
@@ -22,8 +22,6 @@
22 22
23#include "gpmc.h" 23#include "gpmc.h"
24 24
25#include "mux.h"
26
27static u8 async_cs, sync_cs; 25static u8 async_cs, sync_cs;
28static unsigned refclk_psec; 26static unsigned refclk_psec;
29 27
@@ -226,25 +224,6 @@ tusb6010_setup_interface(struct musb_hdrc_platform_data *data,
226 } 224 }
227 tusb_device.dev.platform_data = data; 225 tusb_device.dev.platform_data = data;
228 226
229 /* REVISIT let the driver know what DMA channels work */
230 if (!dmachan)
231 tusb_device.dev.dma_mask = NULL;
232 else {
233 /* assume OMAP 2420 ES2.0 and later */
234 if (dmachan & (1 << 0))
235 omap_mux_init_signal("sys_ndmareq0", 0);
236 if (dmachan & (1 << 1))
237 omap_mux_init_signal("sys_ndmareq1", 0);
238 if (dmachan & (1 << 2))
239 omap_mux_init_signal("sys_ndmareq2", 0);
240 if (dmachan & (1 << 3))
241 omap_mux_init_signal("sys_ndmareq3", 0);
242 if (dmachan & (1 << 4))
243 omap_mux_init_signal("sys_ndmareq4", 0);
244 if (dmachan & (1 << 5))
245 omap_mux_init_signal("sys_ndmareq5", 0);
246 }
247
248 /* so far so good ... register the device */ 227 /* so far so good ... register the device */
249 status = platform_device_register(&tusb_device); 228 status = platform_device_register(&tusb_device);
250 if (status < 0) { 229 if (status < 0) {
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index d055db32ffcb..3e27bffb352d 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -63,32 +63,6 @@ config OMAP_RESET_CLOCKS
63 probably do not want this option enabled until your 63 probably do not want this option enabled until your
64 device drivers work properly. 64 device drivers work properly.
65 65
66config OMAP_MUX
67 bool "OMAP multiplexing support"
68 depends on ARCH_OMAP
69 default y
70 help
71 Pin multiplexing support for OMAP boards. If your bootloader
72 sets the multiplexing correctly, say N. Otherwise, or if unsure,
73 say Y.
74
75config OMAP_MUX_DEBUG
76 bool "Multiplexing debug output"
77 depends on OMAP_MUX
78 help
79 Makes the multiplexing functions print out a lot of debug info.
80 This is useful if you want to find out the correct values of the
81 multiplexing registers.
82
83config OMAP_MUX_WARNINGS
84 bool "Warn about pins the bootloader didn't set up"
85 depends on OMAP_MUX
86 default y
87 help
88 Choose Y here to warn whenever driver initialization logic needs
89 to change the pin multiplexing setup. When there are no warnings
90 printed, it's safe to deselect OMAP_MUX for your product.
91
92config OMAP_MPU_TIMER 66config OMAP_MPU_TIMER
93 bool "Use mpu timer" 67 bool "Use mpu timer"
94 depends on ARCH_OMAP1 68 depends on ARCH_OMAP1
diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile
index 97a50e8883f9..47e186729d44 100644
--- a/arch/arm/plat-omap/Makefile
+++ b/arch/arm/plat-omap/Makefile
@@ -11,6 +11,3 @@ obj-y := sram.o dma.o counter_32k.o
11 11
12obj-$(CONFIG_OMAP_DM_TIMER) += dmtimer.o 12obj-$(CONFIG_OMAP_DM_TIMER) += dmtimer.o
13obj-$(CONFIG_OMAP_DEBUG_LEDS) += debug-leds.o 13obj-$(CONFIG_OMAP_DEBUG_LEDS) += debug-leds.o
14i2c-omap-$(CONFIG_I2C_OMAP) := i2c.o
15obj-y += $(i2c-omap-m) $(i2c-omap-y)
16
diff --git a/arch/arm/plat-omap/i2c.c b/arch/arm/plat-omap/i2c.c
deleted file mode 100644
index 58213d9714cd..000000000000
--- a/arch/arm/plat-omap/i2c.c
+++ /dev/null
@@ -1,116 +0,0 @@
1/*
2 * linux/arch/arm/plat-omap/i2c.c
3 *
4 * Helper module for board specific I2C bus registration
5 *
6 * Copyright (C) 2007 Nokia Corporation.
7 *
8 * Contact: Jarkko Nikula <jhnikula@gmail.com>
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * version 2 as published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
22 * 02110-1301 USA
23 *
24 */
25
26#include <linux/kernel.h>
27#include <linux/platform_device.h>
28#include <linux/i2c.h>
29#include <linux/i2c-omap.h>
30#include <linux/slab.h>
31#include <linux/err.h>
32#include <linux/clk.h>
33
34#include <plat/i2c.h>
35
36#define OMAP_I2C_MAX_CONTROLLERS 4
37static struct omap_i2c_bus_platform_data i2c_pdata[OMAP_I2C_MAX_CONTROLLERS];
38
39#define OMAP_I2C_CMDLINE_SETUP (BIT(31))
40
41/**
42 * omap_i2c_bus_setup - Process command line options for the I2C bus speed
43 * @str: String of options
44 *
45 * This function allow to override the default I2C bus speed for given I2C
46 * bus with a command line option.
47 *
48 * Format: i2c_bus=bus_id,clkrate (in kHz)
49 *
50 * Returns 1 on success, 0 otherwise.
51 */
52static int __init omap_i2c_bus_setup(char *str)
53{
54 int ints[3];
55
56 get_options(str, 3, ints);
57 if (ints[0] < 2 || ints[1] < 1 ||
58 ints[1] > OMAP_I2C_MAX_CONTROLLERS)
59 return 0;
60 i2c_pdata[ints[1] - 1].clkrate = ints[2];
61 i2c_pdata[ints[1] - 1].clkrate |= OMAP_I2C_CMDLINE_SETUP;
62
63 return 1;
64}
65__setup("i2c_bus=", omap_i2c_bus_setup);
66
67/*
68 * Register busses defined in command line but that are not registered with
69 * omap_register_i2c_bus from board initialization code.
70 */
71int __init omap_register_i2c_bus_cmdline(void)
72{
73 int i, err = 0;
74
75 for (i = 0; i < ARRAY_SIZE(i2c_pdata); i++)
76 if (i2c_pdata[i].clkrate & OMAP_I2C_CMDLINE_SETUP) {
77 i2c_pdata[i].clkrate &= ~OMAP_I2C_CMDLINE_SETUP;
78 err = omap_i2c_add_bus(&i2c_pdata[i], i + 1);
79 if (err)
80 goto out;
81 }
82
83out:
84 return err;
85}
86
87/**
88 * omap_register_i2c_bus - register I2C bus with device descriptors
89 * @bus_id: bus id counting from number 1
90 * @clkrate: clock rate of the bus in kHz
91 * @info: pointer into I2C device descriptor table or NULL
92 * @len: number of descriptors in the table
93 *
94 * Returns 0 on success or an error code.
95 */
96int __init omap_register_i2c_bus(int bus_id, u32 clkrate,
97 struct i2c_board_info const *info,
98 unsigned len)
99{
100 int err;
101
102 BUG_ON(bus_id < 1 || bus_id > OMAP_I2C_MAX_CONTROLLERS);
103
104 if (info) {
105 err = i2c_register_board_info(bus_id, info, len);
106 if (err)
107 return err;
108 }
109
110 if (!i2c_pdata[bus_id - 1].clkrate)
111 i2c_pdata[bus_id - 1].clkrate = clkrate;
112
113 i2c_pdata[bus_id - 1].clkrate &= ~OMAP_I2C_CMDLINE_SETUP;
114
115 return omap_i2c_add_bus(&i2c_pdata[bus_id - 1], bus_id);
116}
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-23 10:46:36 -0400