Merge branch 'exynos/dt' into late/dt

* exynos/dt: (125 commits)
  ARM: dts: add PDMA0 changes for exynos5440
  ARM: dts: Add cpufreq controller node for Exynos5440 SoC
  ARM: dts: Fix gmac clock ids due to changes in Exynos5440
  ARM: dts: add device tree file for SD5v1 board
  ARM: dts: update bootargs to boot from sda2 for exynos5440-ssdk5440
  ARM: dts: add PMU support in exynos5440
  ARM: dts: Add node for GMAC for exynos5440
  ARM: dts: list the interrupts generated by pin-controller on Exynos5440
  ARM: dts: Add FIMD DT binding Documentation
  ARM: dts: Add FIMD node and display timing node to exynos4412-origen.dts
  ARM: dts: Add FIMD node to exynos4
  ARM: dts: Add SYSREG block node for S5P/Exynos4 SoC series
  ARM: dts: Add display timing node to exynos5250-smdk5250.dts
  ARM: dts: Add FIMD node to exynos5
  ARM: dts: Add virtual GIC DT bindings for exynos5440
  ARM: dts: Document usb clocks in samsung,exynos4210-ehci/ohci bindings
  ARM: dts: add usb 2.0 clock references to exynos5250 device tree
  ARM: dts: Add architected timer nodes for exynos5250
  ARM: dts: Declare the gic as a15 compatible for exynos5250
  ARM: dts: Add HDMI HPD and regulator node for Arndale board
  ...

149 files changed, 6962 insertions, 5558 deletions

diff --git a/Documentation/devicetree/bindings/arm/samsung/sysreg.txt b/Documentation/devicetree/bindings/arm/samsung/sysreg.txt
new file mode 100644
index 000000000000..5039c0a12f55
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/samsung/sysreg.txt
@@ -0,0 +1,7 @@
+SAMSUNG S5P/Exynos SoC series System Registers (SYSREG)
+
+Properties:
+ - name : should be 'sysreg';
+ - compatible : should contain "samsung,<chip name>-sysreg", "syscon";
+   For Exynos4 SoC series it should be "samsung,exynos4-sysreg", "syscon";
+ - reg : offset and length of the register set.
diff --git a/Documentation/devicetree/bindings/clock/exynos4-clock.txt b/Documentation/devicetree/bindings/clock/exynos4-clock.txt
new file mode 100644
index 000000000000..ea5e26f16aec
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/exynos4-clock.txt
@@ -0,0 +1,288 @@
+* Samsung Exynos4 Clock Controller
+
+The Exynos4 clock controller generates and supplies clock to various controllers
+within the Exynos4 SoC. The clock binding described here is applicable to all
+SoC's in the Exynos4 family.
+
+Required Properties:
+
+- comptible: should be one of the following.
+  - "samsung,exynos4210-clock" - controller compatible with Exynos4210 SoC.
+  - "samsung,exynos4412-clock" - controller compatible with Exynos4412 SoC.
+
+- reg: physical base address of the controller and length of memory mapped
+  region.
+
+- #clock-cells: should be 1.
+
+The following is the list of clocks generated by the controller. Each clock is
+assigned an identifier and client nodes use this identifier to specify the
+clock which they consume. Some of the clocks are available only on a particular
+Exynos4 SoC and this is specified where applicable.
+
+
+                 [Core Clocks]
+
+  Clock               ID      SoC (if specific)
+  -----------------------------------------------
+
+  xxti                1
+  xusbxti             2
+  fin_pll             3
+  fout_apll           4
+  fout_mpll           5
+  fout_epll           6
+  fout_vpll           7
+  sclk_apll           8
+  sclk_mpll           9
+  sclk_epll           10
+  sclk_vpll           11
+  arm_clk             12
+  aclk200             13
+  aclk100             14
+  aclk160             15
+  aclk133             16
+  mout_mpll_user_t    17      Exynos4x12
+  mout_mpll_user_c    18      Exynos4x12
+  mout_core           19
+  mout_apll           20
+
+
+            [Clock Gate for Special Clocks]
+
+  Clock               ID      SoC (if specific)
+  -----------------------------------------------
+
+  sclk_fimc0          128
+  sclk_fimc1          129
+  sclk_fimc2          130
+  sclk_fimc3          131
+  sclk_cam0           132
+  sclk_cam1           133
+  sclk_csis0          134
+  sclk_csis1          135
+  sclk_hdmi           136
+  sclk_mixer          137
+  sclk_dac            138
+  sclk_pixel          139
+  sclk_fimd0          140
+  sclk_mdnie0         141     Exynos4412
+  sclk_mdnie_pwm0 12  142     Exynos4412
+  sclk_mipi0          143
+  sclk_audio0         144
+  sclk_mmc0           145
+  sclk_mmc1           146
+  sclk_mmc2           147
+  sclk_mmc3           148
+  sclk_mmc4           149
+  sclk_sata           150     Exynos4210
+  sclk_uart0          151
+  sclk_uart1          152
+  sclk_uart2          153
+  sclk_uart3          154
+  sclk_uart4          155
+  sclk_audio1         156
+  sclk_audio2         157
+  sclk_spdif          158
+  sclk_spi0           159
+  sclk_spi1           160
+  sclk_spi2           161
+  sclk_slimbus        162
+  sclk_fimd1          163     Exynos4210
+  sclk_mipi1          164     Exynos4210
+  sclk_pcm1           165
+  sclk_pcm2           166
+  sclk_i2s1           167
+  sclk_i2s2           168
+  sclk_mipihsi        169     Exynos4412
+  sclk_mfc            170
+  sclk_pcm0           171
+  sclk_g3d            172
+  sclk_pwm_isp        173     Exynos4x12
+  sclk_spi0_isp       174     Exynos4x12
+  sclk_spi1_isp       175     Exynos4x12
+  sclk_uart_isp       176     Exynos4x12
+
+              [Peripheral Clock Gates]
+
+  Clock               ID      SoC (if specific)
+  -----------------------------------------------
+
+  fimc0               256
+  fimc1               257
+  fimc2               258
+  fimc3               259
+  csis0               260
+  csis1               261
+  jpeg                262
+  smmu_fimc0          263
+  smmu_fimc1          264
+  smmu_fimc2          265
+  smmu_fimc3          266
+  smmu_jpeg           267
+  vp                  268
+  mixer               269
+  tvenc               270     Exynos4210
+  hdmi                271
+  smmu_tv             272
+  mfc                 273
+  smmu_mfcl           274
+  smmu_mfcr           275
+  g3d                 276
+  g2d                 277     Exynos4210
+  rotator             278     Exynos4210
+  mdma                279     Exynos4210
+  smmu_g2d            280     Exynos4210
+  smmu_rotator        281     Exynos4210
+  smmu_mdma           282     Exynos4210
+  fimd0               283
+  mie0                284
+  mdnie0              285     Exynos4412
+  dsim0               286
+  smmu_fimd0          287
+  fimd1               288     Exynos4210
+  mie1                289     Exynos4210
+  dsim1               290     Exynos4210
+  smmu_fimd1          291     Exynos4210
+  pdma0               292
+  pdma1               293
+  pcie_phy            294
+  sata_phy            295     Exynos4210
+  tsi                 296
+  sdmmc0              297
+  sdmmc1              298
+  sdmmc2              299
+  sdmmc3              300
+  sdmmc4              301
+  sata                302     Exynos4210
+  sromc               303
+  usb_host            304
+  usb_device          305
+  pcie                306
+  onenand             307
+  nfcon               308
+  smmu_pcie           309
+  gps                 310
+  smmu_gps            311
+  uart0               312
+  uart1               313
+  uart2               314
+  uart3               315
+  uart4               316
+  i2c0                317
+  i2c1                318
+  i2c2                319
+  i2c3                320
+  i2c4                321
+  i2c5                322
+  i2c6                323
+  i2c7                324
+  i2c_hdmi            325
+  tsadc               326
+  spi0                327
+  spi1                328
+  spi2                329
+  i2s1                330
+  i2s2                331
+  pcm0                332
+  i2s0                333
+  pcm1                334
+  pcm2                335
+  pwm                 336
+  slimbus             337
+  spdif               338
+  ac97                339
+  modemif             340
+  chipid              341
+  sysreg              342
+  hdmi_cec            343
+  mct                 344
+  wdt                 345
+  rtc                 346
+  keyif               347
+  audss               348
+  mipi_hsi            349     Exynos4210
+  mdma2               350     Exynos4210
+  pixelasyncm0        351
+  pixelasyncm1        352
+  fimc_lite0          353     Exynos4x12
+  fimc_lite1          354     Exynos4x12
+  ppmuispx            355     Exynos4x12
+  ppmuispmx           356     Exynos4x12
+  fimc_isp            357     Exynos4x12
+  fimc_drc            358     Exynos4x12
+  fimc_fd             359     Exynos4x12
+  mcuisp              360     Exynos4x12
+  gicisp              361     Exynos4x12
+  smmu_isp            362     Exynos4x12
+  smmu_drc            363     Exynos4x12
+  smmu_fd             364     Exynos4x12
+  smmu_lite0          365     Exynos4x12
+  smmu_lite1          366     Exynos4x12
+  mcuctl_isp          367     Exynos4x12
+  mpwm_isp            368     Exynos4x12
+  i2c0_isp            369     Exynos4x12
+  i2c1_isp            370     Exynos4x12
+  mtcadc_isp          371     Exynos4x12
+  pwm_isp             372     Exynos4x12
+  wdt_isp             373     Exynos4x12
+  uart_isp            374     Exynos4x12
+  asyncaxim           375     Exynos4x12
+  smmu_ispcx          376     Exynos4x12
+  spi0_isp            377     Exynos4x12
+  spi1_isp            378     Exynos4x12
+  pwm_isp_sclk        379     Exynos4x12
+  spi0_isp_sclk       380     Exynos4x12
+  spi1_isp_sclk       381     Exynos4x12
+  uart_isp_sclk       382     Exynos4x12
+
+                [Mux Clocks]
+
+  Clock                 ID      SoC (if specific)
+  -----------------------------------------------
+
+  mout_fimc0            384
+  mout_fimc1            385
+  mout_fimc2            386
+  mout_fimc3            387
+  mout_cam0             388
+  mout_cam1             389
+  mout_csis0            390
+  mout_csis1            391
+  mout_g3d0             392
+  mout_g3d1             393
+  mout_g3d              394
+  aclk400_mcuisp        395     Exynos4x12
+
+                [Div Clocks]
+
+  Clock                 ID      SoC (if specific)
+  -----------------------------------------------
+
+  div_isp0              450     Exynos4x12
+  div_isp1              451     Exynos4x12
+  div_mcuisp0           452     Exynos4x12
+  div_mcuisp1           453     Exynos4x12
+  div_aclk200           454     Exynos4x12
+  div_aclk400_mcuisp    455     Exynos4x12
+
+
+Example 1: An example of a clock controller node is listed below.
+
+        clock: clock-controller@0x10030000 {
+                compatible = "samsung,exynos4210-clock";
+                reg = <0x10030000 0x20000>;
+                #clock-cells = <1>;
+        };
+
+Example 2: UART controller node that consumes the clock generated by the clock
+           controller. Refer to the standard clock bindings for information
+           about 'clocks' and 'clock-names' property.
+
+        serial@13820000 {
+                compatible = "samsung,exynos4210-uart";
+                reg = <0x13820000 0x100>;
+                interrupts = <0 54 0>;
+                clocks = <&clock 314>, <&clock 153>;
+                clock-names = "uart", "clk_uart_baud0";
+        };
diff --git a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
new file mode 100644
index 000000000000..781a6276adf7
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
@@ -0,0 +1,177 @@
+* Samsung Exynos5250 Clock Controller
+
+The Exynos5250 clock controller generates and supplies clock to various
+controllers within the Exynos5250 SoC.
+
+Required Properties:
+
+- comptible: should be one of the following.
+  - "samsung,exynos5250-clock" - controller compatible with Exynos5250 SoC.
+
+- reg: physical base address of the controller and length of memory mapped
+  region.
+
+- #clock-cells: should be 1.
+
+The following is the list of clocks generated by the controller. Each clock is
+assigned an identifier and client nodes use this identifier to specify the
+clock which they consume.
+
+
+       [Core Clocks]
+
+  Clock                 ID
+  ----------------------------
+
+  fin_pll               1
+
+  [Clock Gate for Special Clocks]
+
+  Clock                 ID
+  ----------------------------
+
+  sclk_cam_bayer        128
+  sclk_cam0             129
+  sclk_cam1             130
+  sclk_gscl_wa          131
+  sclk_gscl_wb          132
+  sclk_fimd1            133
+  sclk_mipi1            134
+  sclk_dp               135
+  sclk_hdmi             136
+  sclk_pixel            137
+  sclk_audio0           138
+  sclk_mmc0             139
+  sclk_mmc1             140
+  sclk_mmc2             141
+  sclk_mmc3             142
+  sclk_sata             143
+  sclk_usb3             144
+  sclk_jpeg             145
+  sclk_uart0            146
+  sclk_uart1            147
+  sclk_uart2            148
+  sclk_uart3            149
+  sclk_pwm              150
+  sclk_audio1           151
+  sclk_audio2           152
+  sclk_spdif            153
+  sclk_spi0             154
+  sclk_spi1             155
+  sclk_spi2             156
+
+
+   [Peripheral Clock Gates]
+
+  Clock                 ID
+  ----------------------------
+
+  gscl0                 256
+  gscl1                 257
+  gscl2                 258
+  gscl3                 259
+  gscl_wa               260
+  gscl_wb               261
+  smmu_gscl0            262
+  smmu_gscl1            263
+  smmu_gscl2            264
+  smmu_gscl3            265
+  mfc                   266
+  smmu_mfcl             267
+  smmu_mfcr             268
+  rotator               269
+  jpeg                  270
+  mdma1                 271
+  smmu_rotator          272
+  smmu_jpeg             273
+  smmu_mdma1            274
+  pdma0                 275
+  pdma1                 276
+  sata                  277
+  usbotg                278
+  mipi_hsi              279
+  sdmmc0                280
+  sdmmc1                281
+  sdmmc2                282
+  sdmmc3                283
+  sromc                 284
+  usb2                  285
+  usb3                  286
+  sata_phyctrl          287
+  sata_phyi2c           288
+  uart0                 289
+  uart1                 290
+  uart2                 291
+  uart3                 292
+  uart4                 293
+  i2c0                  294
+  i2c1                  295
+  i2c2                  296
+  i2c3                  297
+  i2c4                  298
+  i2c5                  299
+  i2c6                  300
+  i2c7                  301
+  i2c_hdmi              302
+  adc                   303
+  spi0                  304
+  spi1                  305
+  spi2                  306
+  i2s1                  307
+  i2s2                  308
+  pcm1                  309
+  pcm2                  310
+  pwm                   311
+  spdif                 312
+  ac97                  313
+  hsi2c0                314
+  hsi2c1                315
+  hs12c2                316
+  hs12c3                317
+  chipid                318
+  sysreg                319
+  pmu                   320
+  cmu_top               321
+  cmu_core              322
+  cmu_mem               323
+  tzpc0                 324
+  tzpc1                 325
+  tzpc2                 326
+  tzpc3                 327
+  tzpc4                 328
+  tzpc5                 329
+  tzpc6                 330
+  tzpc7                 331
+  tzpc8                 332
+  tzpc9                 333
+  hdmi_cec              334
+  mct                   335
+  wdt                   336
+  rtc                   337
+  tmu                   338
+  fimd1                 339
+  mie1                  340
+  dsim0                 341
+  dp                    342
+  mixer                 343
+  hdmi                  345
+
+Example 1: An example of a clock controller node is listed below.
+
+        clock: clock-controller@0x10010000 {
+                compatible = "samsung,exynos5250-clock";
+                reg = <0x10010000 0x30000>;
+                #clock-cells = <1>;
+        };
+
+Example 2: UART controller node that consumes the clock generated by the clock
+           controller. Refer to the standard clock bindings for information
+           about 'clocks' and 'clock-names' property.
+
+        serial@13820000 {
+                compatible = "samsung,exynos4210-uart";
+                reg = <0x13820000 0x100>;
+                interrupts = <0 54 0>;
+                clocks = <&clock 314>, <&clock 153>;
+                clock-names = "uart", "clk_uart_baud0";
+        };
diff --git a/Documentation/devicetree/bindings/clock/exynos5440-clock.txt b/Documentation/devicetree/bindings/clock/exynos5440-clock.txt
new file mode 100644
index 000000000000..4499e9966bc9
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/exynos5440-clock.txt
@@ -0,0 +1,61 @@
+* Samsung Exynos5440 Clock Controller
+
+The Exynos5440 clock controller generates and supplies clock to various
+controllers within the Exynos5440 SoC.
+
+Required Properties:
+
+- comptible: should be "samsung,exynos5440-clock".
+
+- reg: physical base address of the controller and length of memory mapped
+  region.
+
+- #clock-cells: should be 1.
+
+The following is the list of clocks generated by the controller. Each clock is
+assigned an identifier and client nodes use this identifier to specify the
+clock which they consume.
+
+
+       [Core Clocks]
+
+  Clock                 ID
+  ----------------------------
+
+  xtal                  1
+  arm_clk               2
+
+   [Peripheral Clock Gates]
+
+  Clock                 ID
+  ----------------------------
+
+  spi_baud              16
+  pb0_250               17
+  pr0_250               18
+  pr1_250               19
+  b_250                 20
+  b_125                 21
+  b_200                 22
+  sata                  23
+  usb                   24
+  gmac0                 25
+  cs250                 26
+  pb0_250_o             27
+  pr0_250_o             28
+  pr1_250_o             29
+  b_250_o               30
+  b_125_o               31
+  b_200_o               32
+  sata_o                33
+  usb_o                 34
+  gmac0_o               35
+  cs250_o               36
+
+Example: An example of a clock controller node is listed below.
+
+        clock: clock-controller@0x10010000 {
+                compatible = "samsung,exynos5440-clock";
+                reg = <0x160000 0x10000>;
+                #clock-cells = <1>;
+        };
diff --git a/Documentation/devicetree/bindings/gpu/samsung-g2d.txt b/Documentation/devicetree/bindings/gpu/samsung-g2d.txt
new file mode 100644
index 000000000000..2b14a940eb75
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpu/samsung-g2d.txt
@@ -0,0 +1,20 @@
+* Samsung 2D Graphics Accelerator
+
+Required properties:
+  - compatible : value should be one among the following:
+        (a) "samsung,s5pv210-g2d" for G2D IP present in S5PV210 & Exynos4210 SoC
+        (b) "samsung,exynos4212-g2d" for G2D IP present in Exynos4x12 SoCs
+        (c) "samsung,exynos5250-g2d" for G2D IP present in Exynos5250 SoC
+
+  - reg : Physical base address of the IP registers and length of memory
+          mapped region.
+
+  - interrupts : G2D interrupt number to the CPU.
+
+Example:
+        g2d@12800000 {
+                compatible = "samsung,s5pv210-g2d";
+                reg = <0x12800000 0x1000>;
+                interrupts = <0 89 0>;
+                status = "disabled";
+        };
diff --git a/Documentation/devicetree/bindings/media/s5p-mfc.txt b/Documentation/devicetree/bindings/media/s5p-mfc.txt
index 67ec3d4ccc7f..bf0182d8da25 100644
--- a/Documentation/devicetree/bindings/media/s5p-mfc.txt
+++ b/Documentation/devicetree/bindings/media/s5p-mfc.txt
@@ -21,3 +21,24 @@ Required properties:
 
   - samsung,mfc-l : Base address of the second memory bank used by MFC
                     for DMA contiguous memory allocation and its size.
+
+Optional properties:
+  - samsung,power-domain : power-domain property defined with a phandle
+                           to respective power domain.
+
+Example:
+SoC specific DT entry:
+
+mfc: codec@13400000 {
+        compatible = "samsung,mfc-v5";
+        reg = <0x13400000 0x10000>;
+        interrupts = <0 94 0>;
+        samsung,power-domain = <&pd_mfc>;
+};
+
+Board specific DT entry:
+
+codec@13400000 {
+        samsung,mfc-r = <0x43000000 0x800000>;
+        samsung,mfc-l = <0x51000000 0x800000>;
+};
diff --git a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt
new file mode 100644
index 000000000000..cb47bfbcaeea
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt
@@ -0,0 +1,68 @@
+Samsung's Multi Core Timer (MCT)
+
+The Samsung's Multi Core Timer (MCT) module includes two main blocks, the
+global timer and CPU local timers. The global timer is a 64-bit free running
+up-counter and can generate 4 interrupts when the counter reaches one of the
+four preset counter values. The CPU local timers are 32-bit free running
+down-counters and generate an interrupt when the counter expires. There is
+one CPU local timer instantiated in MCT for every CPU in the system.
+
+Required properties:
+
+- compatible: should be "samsung,exynos4210-mct".
+  (a) "samsung,exynos4210-mct", for mct compatible with Exynos4210 mct.
+  (b) "samsung,exynos4412-mct", for mct compatible with Exynos4412 mct.
+
+- reg: base address of the mct controller and length of the address space
+  it occupies.
+
+- interrupts: the list of interrupts generated by the controller. The following
+  should be the order of the interrupts specified. The local timer interrupts
+  should be specified after the four global timer interrupts have been
+  specified.
+
+        0: Global Timer Interrupt 0
+        1: Global Timer Interrupt 1
+        2: Global Timer Interrupt 2
+        3: Global Timer Interrupt 3
+        4: Local Timer Interrupt 0
+        5: Local Timer Interrupt 1
+        6: ..
+        7: ..
+        i: Local Timer Interrupt n
+
+Example 1: In this example, the system uses only the first global timer
+           interrupt generated by MCT and the remaining three global timer
+           interrupts are unused. Two local timer interrupts have been
+           specified.
+
+        mct@10050000 {
+                compatible = "samsung,exynos4210-mct";
+                reg = <0x10050000 0x800>;
+                interrupts = <0 57 0>, <0 0 0>, <0 0 0>, <0 0 0>,
+                             <0 42 0>, <0 48 0>;
+        };
+
+Example 2: In this example, the MCT global and local timer interrupts are
+           connected to two seperate interrupt controllers. Hence, an
+           interrupt-map is created to map the interrupts to the respective
+           interrupt controllers.
+
+        mct@101C0000 {
+                compatible = "samsung,exynos4210-mct";
+                reg = <0x101C0000 0x800>;
+                interrupt-controller;
+                #interrups-cells = <2>;
+                interrupt-parent = <&mct_map>;
+                interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
+                             <4 0>, <5 0>;
+
+                mct_map: mct-map {
+                        #interrupt-cells = <2>;
+                        #address-cells = <0>;
+                        #size-cells = <0>;
+                        interrupt-map = <0x0 0 &combiner 23 3>,
+                                        <0x4 0 &gic 0 120 0>,
+                                        <0x5 0 &gic 0 121 0>;
+                };
+        };
diff --git a/Documentation/devicetree/bindings/usb/exynos-usb.txt b/Documentation/devicetree/bindings/usb/exynos-usb.txt
new file mode 100644
index 000000000000..b3abde736017
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/exynos-usb.txt
@@ -0,0 +1,50 @@
+Samsung Exynos SoC USB controller
+
+The USB devices interface with USB controllers on Exynos SOCs.
+The device node has following properties.
+
+EHCI
+Required properties:
+ - compatible: should be "samsung,exynos4210-ehci" for USB 2.0
+   EHCI controller in host mode.
+ - reg: physical base address of the controller and length of memory mapped
+   region.
+ - interrupts: interrupt number to the cpu.
+ - clocks: from common clock binding: handle to usb clock.
+ - clock-names: from common clock binding: Shall be "usbhost".
+
+Optional properties:
+ - samsung,vbus-gpio:  if present, specifies the GPIO that
+   needs to be pulled up for the bus to be powered.
+
+Example:
+
+        usb@12110000 {
+                compatible = "samsung,exynos4210-ehci";
+                reg = <0x12110000 0x100>;
+                interrupts = <0 71 0>;
+                samsung,vbus-gpio = <&gpx2 6 1 3 3>;
+
+                clocks = <&clock 285>;
+                clock-names = "usbhost";
+        };
+
+OHCI
+Required properties:
+ - compatible: should be "samsung,exynos4210-ohci" for USB 2.0
+   OHCI companion controller in host mode.
+ - reg: physical base address of the controller and length of memory mapped
+   region.
+ - interrupts: interrupt number to the cpu.
+ - clocks: from common clock binding: handle to usb clock.
+ - clock-names: from common clock binding: Shall be "usbhost".
+
+Example:
+        usb@12120000 {
+                compatible = "samsung,exynos4210-ohci";
+                reg = <0x12120000 0x100>;
+                interrupts = <0 71 0>;
+
+                clocks = <&clock 285>;
+                clock-names = "usbhost";
+        };
diff --git a/Documentation/devicetree/bindings/video/samsung-fimd.txt b/Documentation/devicetree/bindings/video/samsung-fimd.txt
new file mode 100644
index 000000000000..778838a0336a
--- /dev/null
+++ b/Documentation/devicetree/bindings/video/samsung-fimd.txt
@@ -0,0 +1,65 @@
+Device-Tree bindings for Samsung SoC display controller (FIMD)
+
+FIMD (Fully Interactive Mobile Display) is the Display Controller for the
+Samsung series of SoCs which transfers the image data from a video memory
+buffer to an external LCD interface.
+
+Required properties:
+- compatible: value should be one of the following
+                "samsung,s3c2443-fimd"; /* for S3C24XX SoCs */
+                "samsung,s3c6400-fimd"; /* for S3C64XX SoCs */
+                "samsung,s5p6440-fimd"; /* for S5P64X0 SoCs */
+                "samsung,s5pc100-fimd"; /* for S5PC100 SoC  */
+                "samsung,s5pv210-fimd"; /* for S5PV210 SoC */
+                "samsung,exynos4210-fimd"; /* for Exynos4 SoCs */
+                "samsung,exynos5250-fimd"; /* for Exynos5 SoCs */
+
+- reg: physical base address and length of the FIMD registers set.
+
+- interrupt-parent: should be the phandle of the fimd controller's
+                parent interrupt controller.
+
+- interrupts: should contain a list of all FIMD IP block interrupts in the
+                 order: FIFO Level, VSYNC, LCD_SYSTEM. The interrupt specifier
+                 format depends on the interrupt controller used.
+
+- interrupt-names: should contain the interrupt names: "fifo", "vsync",
+        "lcd_sys", in the same order as they were listed in the interrupts
+        property.
+
+- pinctrl-0: pin control group to be used for this controller.
+
+- pinctrl-names: must contain a "default" entry.
+
+- clocks: must include clock specifiers corresponding to entries in the
+         clock-names property.
+
+- clock-names: list of clock names sorted in the same order as the clocks
+               property. Must contain "sclk_fimd" and "fimd".
+
+Optional Properties:
+- samsung,power-domain: a phandle to FIMD power domain node.
+
+Example:
+
+SoC specific DT entry:
+
+        fimd@11c00000 {
+                compatible = "samsung,exynos4210-fimd";
+                interrupt-parent = <&combiner>;
+                reg = <0x11c00000 0x20000>;
+                interrupt-names = "fifo", "vsync", "lcd_sys";
+                interrupts = <11 0>, <11 1>, <11 2>;
+                clocks = <&clock 140>, <&clock 283>;
+                clock-names = "sclk_fimd", "fimd";
+                samsung,power-domain = <&pd_lcd0>;
+                status = "disabled";
+        };
+
+Board specific DT entry:
+
+        fimd@11c00000 {
+                pinctrl-0 = <&lcd_clk &lcd_data24 &pwm1_out>;
+                pinctrl-names = "default";
+                status = "okay";
+        };
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 1cacda426a0e..be23497f5b29 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -769,8 +769,10 @@ config ARCH_SA1100
 config ARCH_S3C24XX
         bool "Samsung S3C24XX SoCs"
         select ARCH_HAS_CPUFREQ
-        select ARCH_USES_GETTIMEOFFSET
         select CLKDEV_LOOKUP
+        select CLKSRC_MMIO
+        select GENERIC_CLOCKEVENTS
+        select GENERIC_GPIO
         select HAVE_CLK
         select HAVE_S3C2410_I2C if I2C
         select HAVE_S3C2410_WATCHDOG if WATCHDOG
@@ -787,10 +789,11 @@ config ARCH_S3C64XX
         bool "Samsung S3C64XX"
         select ARCH_HAS_CPUFREQ
         select ARCH_REQUIRE_GPIOLIB
-        select ARCH_USES_GETTIMEOFFSET
         select ARM_VIC
         select CLKDEV_LOOKUP
+        select CLKSRC_MMIO
         select CPU_V6
+        select GENERIC_CLOCKEVENTS
         select HAVE_CLK
         select HAVE_S3C2410_I2C if I2C
         select HAVE_S3C2410_WATCHDOG if WATCHDOG
@@ -824,9 +827,11 @@ config ARCH_S5P64X0
 
 config ARCH_S5PC100
         bool "Samsung S5PC100"
-        select ARCH_USES_GETTIMEOFFSET
         select CLKDEV_LOOKUP
+        select CLKSRC_MMIO
         select CPU_V7
+        select GENERIC_CLOCKEVENTS
+        select GENERIC_GPIO
         select HAVE_CLK
         select HAVE_S3C2410_I2C if I2C
         select HAVE_S3C2410_WATCHDOG if WATCHDOG
@@ -859,6 +864,7 @@ config ARCH_EXYNOS
         select ARCH_HAS_HOLES_MEMORYMODEL
         select ARCH_SPARSEMEM_ENABLE
         select CLKDEV_LOOKUP
+        select COMMON_CLK
         select CPU_V7
         select GENERIC_CLOCKEVENTS
         select HAVE_CLK
@@ -1656,7 +1662,7 @@ config LOCAL_TIMERS
         bool "Use local timer interrupts"
         depends on SMP
         default y
-        select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
+        select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !CLKSRC_EXYNOS_MCT)
         help
           Enable support for local timers on SMP platforms, rather then the
           legacy IPI broadcast method.  Local timers allows the system
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 9c6255884cbb..11fef62e237b 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -42,7 +42,11 @@ dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \
 dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
         exynos4210-smdkv310.dtb \
         exynos4210-trats.dtb \
+        exynos4412-odroidx.dtb \
         exynos4412-smdk4412.dtb \
+        exynos4412-origen.dtb \
+        exynos5250-arndale.dtb \
+        exynos5440-sd5v1.dtb \
         exynos5250-smdk5250.dtb \
         exynos5250-snow.dtb \
         exynos5440-ssdk5440.dtb
diff --git a/arch/arm/boot/dts/cros5250-common.dtsi b/arch/arm/boot/dts/cros5250-common.dtsi
index 46c098017036..8a5b3a6cdc58 100644
--- a/arch/arm/boot/dts/cros5250-common.dtsi
+++ b/arch/arm/boot/dts/cros5250-common.dtsi
@@ -19,31 +19,168 @@
         chosen {
         };
 
+        pinctrl@11400000 {
+                /*
+                 * Disabled pullups since external part has its own pullups and
+                 * double-pulling gets us out of spec in some cases.
+                 */
+                i2c2_bus: i2c2-bus {
+                        samsung,pin-pud = <0>;
+                };
+        };
+
         i2c@12C60000 {
                 samsung,i2c-sda-delay = <100>;
                 samsung,i2c-max-bus-freq = <378000>;
-                gpios = <&gpb3 0 2 3 0>,
-                        <&gpb3 1 2 3 0>;
+
+                max77686@09 {
+                        compatible = "maxim,max77686";
+                        reg = <0x09>;
+
+                        voltage-regulators {
+                                ldo1_reg: LDO1 {
+                                        regulator-name = "P1.0V_LDO_OUT1";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo2_reg: LDO2 {
+                                        regulator-name = "P1.8V_LDO_OUT2";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo3_reg: LDO3 {
+                                        regulator-name = "P1.8V_LDO_OUT3";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo7_reg: LDO7 {
+                                        regulator-name = "P1.1V_LDO_OUT7";
+                                        regulator-min-microvolt = <1100000>;
+                                        regulator-max-microvolt = <1100000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo8_reg: LDO8 {
+                                        regulator-name = "P1.0V_LDO_OUT8";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo10_reg: LDO10 {
+                                        regulator-name = "P1.8V_LDO_OUT10";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo12_reg: LDO12 {
+                                        regulator-name = "P3.0V_LDO_OUT12";
+                                        regulator-min-microvolt = <3000000>;
+                                        regulator-max-microvolt = <3000000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo14_reg: LDO14 {
+                                        regulator-name = "P1.8V_LDO_OUT14";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo15_reg: LDO15 {
+                                        regulator-name = "P1.0V_LDO_OUT15";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo16_reg: LDO16 {
+                                        regulator-name = "P1.8V_LDO_OUT16";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+
+                                buck1_reg: BUCK1 {
+                                        regulator-name = "vdd_mif";
+                                        regulator-min-microvolt = <950000>;
+                                        regulator-max-microvolt = <1300000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                buck2_reg: BUCK2 {
+                                        regulator-name = "vdd_arm";
+                                        regulator-min-microvolt = <850000>;
+                                        regulator-max-microvolt = <1350000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                buck3_reg: BUCK3 {
+                                        regulator-name = "vdd_int";
+                                        regulator-min-microvolt = <900000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                buck4_reg: BUCK4 {
+                                        regulator-name = "vdd_g3d";
+                                        regulator-min-microvolt = <850000>;
+                                        regulator-max-microvolt = <1300000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                buck5_reg: BUCK5 {
+                                        regulator-name = "P1.8V_BUCK_OUT5";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                buck6_reg: BUCK6 {
+                                        regulator-name = "P1.35V_BUCK_OUT6";
+                                        regulator-min-microvolt = <1350000>;
+                                        regulator-max-microvolt = <1350000>;
+                                        regulator-always-on;
+                                };
+
+                                buck7_reg: BUCK7 {
+                                        regulator-name = "P2.0V_BUCK_OUT7";
+                                        regulator-min-microvolt = <2000000>;
+                                        regulator-max-microvolt = <2000000>;
+                                        regulator-always-on;
+                                };
+
+                                buck8_reg: BUCK8 {
+                                        regulator-name = "P2.85V_BUCK_OUT8";
+                                        regulator-min-microvolt = <2850000>;
+                                        regulator-max-microvolt = <2850000>;
+                                        regulator-always-on;
+                                };
+                        };
+                };
         };
 
         i2c@12C70000 {
                 samsung,i2c-sda-delay = <100>;
                 samsung,i2c-max-bus-freq = <378000>;
-                gpios = <&gpb3 2 2 3 0>,
-                        <&gpb3 3 2 3 0>;
         };
 
         i2c@12C80000 {
                 samsung,i2c-sda-delay = <100>;
                 samsung,i2c-max-bus-freq = <66000>;
 
-                /*
-                 * Disabled pullups since external part has its own pullups and
-                 * double-pulling gets us out of spec in some cases.
-                 */
-                gpios = <&gpa0 6 3 0 0>,
-                        <&gpa0 7 3 0 0>;
-
                 hdmiddc@50 {
                         compatible = "samsung,exynos5-hdmiddc";
                         reg = <0x50>;
@@ -53,8 +190,6 @@
         i2c@12C90000 {
                 samsung,i2c-sda-delay = <100>;
                 samsung,i2c-max-bus-freq = <66000>;
-                gpios = <&gpa1 2 3 3 0>,
-                        <&gpa1 3 3 3 0>;
         };
 
         i2c@12CA0000 {
@@ -64,8 +199,6 @@
         i2c@12CB0000 {
                 samsung,i2c-sda-delay = <100>;
                 samsung,i2c-max-bus-freq = <66000>;
-                gpios = <&gpa2 2 3 3 0>,
-                        <&gpa2 3 3 3 0>;
         };
 
         i2c@12CC0000 {
@@ -75,8 +208,6 @@
         i2c@12CD0000 {
                 samsung,i2c-sda-delay = <100>;
                 samsung,i2c-max-bus-freq = <66000>;
-                gpios = <&gpb2 2 3 3 0>,
-                        <&gpb2 3 3 3 0>;
         };
 
         i2c@12CE0000 {
@@ -98,15 +229,12 @@
                 samsung,dw-mshc-ciu-div = <3>;
                 samsung,dw-mshc-sdr-timing = <2 3>;
                 samsung,dw-mshc-ddr-timing = <1 2>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4 &sd0_bus8>;
 
                 slot@0 {
                         reg = <0>;
                         bus-width = <8>;
-                        gpios = <&gpc0 0 2 0 3>, <&gpc0 1 2 0 3>,
-                                <&gpc1 0 2 3 3>, <&gpc1 1 2 3 3>,
-                                <&gpc1 2 2 3 3>, <&gpc1 3 2 3 3>,
-                                <&gpc0 3 2 3 3>, <&gpc0 4 2 3 3>,
-                                <&gpc0 5 2 3 3>, <&gpc0 6 2 3 3>;
                 };
         };
 
@@ -122,15 +250,13 @@
                 samsung,dw-mshc-ciu-div = <3>;
                 samsung,dw-mshc-sdr-timing = <2 3>;
                 samsung,dw-mshc-ddr-timing = <1 2>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
 
                 slot@0 {
                         reg = <0>;
                         bus-width = <4>;
-                        samsung,cd-pinmux-gpio = <&gpc3 2 2 3 3>;
-                        wp-gpios = <&gpc2 1 0 0 3>;
-                        gpios = <&gpc3 0 2 0 3>, <&gpc3 1 2 0 3>,
-                                <&gpc3 3 2 3 3>, <&gpc3 4 2 3 3>,
-                                <&gpc3 5 2 3 3>, <&gpc3 6 2 3 3>;
+                        wp-gpios = <&gpc2 1 0>;
                 };
         };
 
@@ -143,11 +269,11 @@
                 samsung,dw-mshc-ciu-div = <3>;
                 samsung,dw-mshc-sdr-timing = <2 3>;
                 samsung,dw-mshc-ddr-timing = <1 2>;
+                /* See board-specific dts files for pin setup */
 
                 slot@0 {
                         reg = <0>;
                         bus-width = <4>;
-                        /* See board-specific dts files for GPIOs */
                 };
         };
 
@@ -156,9 +282,6 @@
         };
 
         spi_1: spi@12d30000 {
-                gpios = <&gpa2 4 2 3 0>,
-                        <&gpa2 6 2 3 0>,
-                        <&gpa2 7 2 3 0>;
                 samsung,spi-src-clk = <0>;
                 num-cs = <1>;
         };
@@ -168,7 +291,7 @@
         };
 
         hdmi {
-                hpd-gpio = <&gpx3 7 0xf 1 3>;
+                hpd-gpio = <&gpx3 7 0>;
         };
 
         gpio-keys {
@@ -176,7 +299,7 @@
 
                 power {
                         label = "Power";
-                        gpios = <&gpx1 3 0 0x10000 0>;
+                        gpios = <&gpx1 3 1>;
                         linux,code = <116>; /* KEY_POWER */
                         gpio-key,wakeup;
                 };
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index 1a62bcf18aa3..b8771c5cb2a3 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -82,10 +82,17 @@
                 reg = <0x10440000 0x1000>;
         };
 
+        sys_reg: sysreg {
+                compatible = "samsung,exynos4-sysreg", "syscon";
+                reg = <0x10010000 0x400>;
+        };
+
         watchdog@10060000 {
                 compatible = "samsung,s3c2410-wdt";
                 reg = <0x10060000 0x100>;
                 interrupts = <0 43 0>;
+                clocks = <&clock 345>;
+                clock-names = "watchdog";
                 status = "disabled";
         };
 
@@ -93,6 +100,8 @@
                 compatible = "samsung,s3c6410-rtc";
                 reg = <0x10070000 0x100>;
                 interrupts = <0 44 0>, <0 45 0>;
+                clocks = <&clock 346>;
+                clock-names = "rtc";
                 status = "disabled";
         };
 
@@ -100,6 +109,8 @@
                 compatible = "samsung,s5pv210-keypad";
                 reg = <0x100A0000 0x100>;
                 interrupts = <0 109 0>;
+                clocks = <&clock 347>;
+                clock-names = "keypad";
                 status = "disabled";
         };
 
@@ -107,6 +118,8 @@
                 compatible = "samsung,exynos4210-sdhci";
                 reg = <0x12510000 0x100>;
                 interrupts = <0 73 0>;
+                clocks = <&clock 297>, <&clock 145>;
+                clock-names = "hsmmc", "mmc_busclk.2";
                 status = "disabled";
         };
 
@@ -114,6 +127,8 @@
                 compatible = "samsung,exynos4210-sdhci";
                 reg = <0x12520000 0x100>;
                 interrupts = <0 74 0>;
+                clocks = <&clock 298>, <&clock 146>;
+                clock-names = "hsmmc", "mmc_busclk.2";
                 status = "disabled";
         };
 
@@ -121,6 +136,8 @@
                 compatible = "samsung,exynos4210-sdhci";
                 reg = <0x12530000 0x100>;
                 interrupts = <0 75 0>;
+                clocks = <&clock 299>, <&clock 147>;
+                clock-names = "hsmmc", "mmc_busclk.2";
                 status = "disabled";
         };
 
@@ -128,6 +145,16 @@
                 compatible = "samsung,exynos4210-sdhci";
                 reg = <0x12540000 0x100>;
                 interrupts = <0 76 0>;
+                clocks = <&clock 300>, <&clock 148>;
+                clock-names = "hsmmc", "mmc_busclk.2";
+                status = "disabled";
+        };
+
+        mfc: codec@13400000 {
+                compatible = "samsung,mfc-v5";
+                reg = <0x13400000 0x10000>;
+                interrupts = <0 94 0>;
+                samsung,power-domain = <&pd_mfc>;
                 status = "disabled";
         };
 
@@ -135,6 +162,8 @@
                 compatible = "samsung,exynos4210-uart";
                 reg = <0x13800000 0x100>;
                 interrupts = <0 52 0>;
+                clocks = <&clock 312>, <&clock 151>;
+                clock-names = "uart", "clk_uart_baud0";
                 status = "disabled";
         };
 
@@ -142,6 +171,8 @@
                 compatible = "samsung,exynos4210-uart";
                 reg = <0x13810000 0x100>;
                 interrupts = <0 53 0>;
+                clocks = <&clock 313>, <&clock 152>;
+                clock-names = "uart", "clk_uart_baud0";
                 status = "disabled";
         };
 
@@ -149,6 +180,8 @@
                 compatible = "samsung,exynos4210-uart";
                 reg = <0x13820000 0x100>;
                 interrupts = <0 54 0>;
+                clocks = <&clock 314>, <&clock 153>;
+                clock-names = "uart", "clk_uart_baud0";
                 status = "disabled";
         };
 
@@ -156,6 +189,8 @@
                 compatible = "samsung,exynos4210-uart";
                 reg = <0x13830000 0x100>;
                 interrupts = <0 55 0>;
+                clocks = <&clock 315>, <&clock 154>;
+                clock-names = "uart", "clk_uart_baud0";
                 status = "disabled";
         };
 
@@ -165,6 +200,10 @@
                 compatible = "samsung,s3c2440-i2c";
                 reg = <0x13860000 0x100>;
                 interrupts = <0 58 0>;
+                clocks = <&clock 317>;
+                clock-names = "i2c";
+                pinctrl-names = "default";
+                pinctrl-0 = <&i2c0_bus>;
                 status = "disabled";
         };
 
@@ -174,6 +213,10 @@
                 compatible = "samsung,s3c2440-i2c";
                 reg = <0x13870000 0x100>;
                 interrupts = <0 59 0>;
+                clocks = <&clock 318>;
+                clock-names = "i2c";
+                pinctrl-names = "default";
+                pinctrl-0 = <&i2c1_bus>;
                 status = "disabled";
         };
 
@@ -183,6 +226,8 @@
                 compatible = "samsung,s3c2440-i2c";
                 reg = <0x13880000 0x100>;
                 interrupts = <0 60 0>;
+                clocks = <&clock 319>;
+                clock-names = "i2c";
                 status = "disabled";
         };
 
@@ -192,6 +237,8 @@
                 compatible = "samsung,s3c2440-i2c";
                 reg = <0x13890000 0x100>;
                 interrupts = <0 61 0>;
+                clocks = <&clock 320>;
+                clock-names = "i2c";
                 status = "disabled";
         };
 
@@ -201,6 +248,8 @@
                 compatible = "samsung,s3c2440-i2c";
                 reg = <0x138A0000 0x100>;
                 interrupts = <0 62 0>;
+                clocks = <&clock 321>;
+                clock-names = "i2c";
                 status = "disabled";
         };
 
@@ -210,6 +259,8 @@
                 compatible = "samsung,s3c2440-i2c";
                 reg = <0x138B0000 0x100>;
                 interrupts = <0 63 0>;
+                clocks = <&clock 322>;
+                clock-names = "i2c";
                 status = "disabled";
         };
 
@@ -219,6 +270,8 @@
                 compatible = "samsung,s3c2440-i2c";
                 reg = <0x138C0000 0x100>;
                 interrupts = <0 64 0>;
+                clocks = <&clock 323>;
+                clock-names = "i2c";
                 status = "disabled";
         };
 
@@ -228,6 +281,8 @@
                 compatible = "samsung,s3c2440-i2c";
                 reg = <0x138D0000 0x100>;
                 interrupts = <0 65 0>;
+                clocks = <&clock 324>;
+                clock-names = "i2c";
                 status = "disabled";
         };
 
@@ -239,6 +294,10 @@
                 rx-dma-channel = <&pdma0 6>; /* preliminary */
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 327>, <&clock 159>;
+                clock-names = "spi", "spi_busclk0";
+                pinctrl-names = "default";
+                pinctrl-0 = <&spi0_bus>;
                 status = "disabled";
         };
 
@@ -250,6 +309,10 @@
                 rx-dma-channel = <&pdma1 6>; /* preliminary */
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 328>, <&clock 160>;
+                clock-names = "spi", "spi_busclk0";
+                pinctrl-names = "default";
+                pinctrl-0 = <&spi1_bus>;
                 status = "disabled";
         };
 
@@ -261,6 +324,10 @@
                 rx-dma-channel = <&pdma0 8>; /* preliminary */
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 329>, <&clock 161>;
+                clock-names = "spi", "spi_busclk0";
+                pinctrl-names = "default";
+                pinctrl-0 = <&spi2_bus>;
                 status = "disabled";
         };
 
@@ -275,6 +342,8 @@
                         compatible = "arm,pl330", "arm,primecell";
                         reg = <0x12680000 0x1000>;
                         interrupts = <0 35 0>;
+                        clocks = <&clock 292>;
+                        clock-names = "apb_pclk";
                         #dma-cells = <1>;
                         #dma-channels = <8>;
                         #dma-requests = <32>;
@@ -284,6 +353,8 @@
                         compatible = "arm,pl330", "arm,primecell";
                         reg = <0x12690000 0x1000>;
                         interrupts = <0 36 0>;
+                        clocks = <&clock 293>;
+                        clock-names = "apb_pclk";
                         #dma-cells = <1>;
                         #dma-channels = <8>;
                         #dma-requests = <32>;
@@ -293,9 +364,23 @@
                         compatible = "arm,pl330", "arm,primecell";
                         reg = <0x12850000 0x1000>;
                         interrupts = <0 34 0>;
+                        clocks = <&clock 279>;
+                        clock-names = "apb_pclk";
                         #dma-cells = <1>;
                         #dma-channels = <8>;
                         #dma-requests = <1>;
                 };
         };
+
+        fimd: fimd@11c00000 {
+                compatible = "samsung,exynos4210-fimd";
+                interrupt-parent = <&combiner>;
+                reg = <0x11c00000 0x20000>;
+                interrupt-names = "fifo", "vsync", "lcd_sys";
+                interrupts = <11 0>, <11 1>, <11 2>;
+                clocks = <&clock 140>, <&clock 283>;
+                clock-names = "sclk_fimd", "fimd";
+                samsung,power-domain = <&pd_lcd0>;
+                status = "disabled";
+        };
 };
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts
index f2710018e84e..524b90846df5 100644
--- a/arch/arm/boot/dts/exynos4210-origen.dts
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -57,6 +57,16 @@
                 status = "okay";
         };
 
+        g2d@12800000 {
+                status = "okay";
+        };
+
+        codec@13400000 {
+                samsung,mfc-r = <0x43000000 0x800000>;
+                samsung,mfc-l = <0x51000000 0x800000>;
+                status = "okay";
+        };
+
         serial@13800000 {
                 status = "okay";
         };
@@ -121,4 +131,16 @@
                         linux,default-trigger = "heartbeat";
                 };
         };
+
+        fixed-rate-clocks {
+                xxti {
+                        compatible = "samsung,clock-xxti";
+                        clock-frequency = <0>;
+                };
+
+                xusbxti {
+                        compatible = "samsung,clock-xusbxti";
+                        clock-frequency = <24000000>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts b/arch/arm/boot/dts/exynos4210-smdkv310.dts
index f63490707f3a..91332b72acf5 100644
--- a/arch/arm/boot/dts/exynos4210-smdkv310.dts
+++ b/arch/arm/boot/dts/exynos4210-smdkv310.dts
@@ -30,16 +30,19 @@
         };
 
         sdhci@12530000 {
-                samsung,sdhci-bus-width = <4>;
-                linux,mmc_cap_4_bit_data;
-                samsung,sdhci-cd-internal;
-                gpio-cd = <&gpk2 2 2 3 3>;
-                gpios = <&gpk2 0 2 0 3>,
-                        <&gpk2 1 2 0 3>,
-                        <&gpk2 3 2 3 3>,
-                        <&gpk2 4 2 3 3>,
-                        <&gpk2 5 2 3 3>,
-                        <&gpk2 6 2 3 3>;
+                bus-width = <4>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
+                status = "okay";
+        };
+
+        g2d@12800000 {
+                status = "okay";
+        };
+
+        codec@13400000 {
+                samsung,mfc-r = <0x43000000 0x800000>;
+                samsung,mfc-l = <0x51000000 0x800000>;
                 status = "okay";
         };
 
@@ -59,25 +62,32 @@
                 status = "okay";
         };
 
+        pinctrl@11000000 {
+                keypad_rows: keypad-rows {
+                        samsung,pins = "gpx2-0", "gpx2-1";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+
+                keypad_cols: keypad-cols {
+                        samsung,pins = "gpx1-0", "gpx1-1", "gpx1-2", "gpx1-3",
+                                       "gpx1-4", "gpx1-5", "gpx1-6", "gpx1-7";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+        };
+
         keypad@100A0000 {
                 samsung,keypad-num-rows = <2>;
                 samsung,keypad-num-columns = <8>;
                 linux,keypad-no-autorepeat;
                 linux,keypad-wakeup;
+                pinctrl-names = "default";
+                pinctrl-0 = <&keypad_rows &keypad_cols>;
                 status = "okay";
 
-                row-gpios = <&gpx2 0 3 3 0>,
-                            <&gpx2 1 3 3 0>;
-
-                col-gpios = <&gpx1 0 3 0 0>,
-                            <&gpx1 1 3 0 0>,
-                            <&gpx1 2 3 0 0>,
-                            <&gpx1 3 3 0 0>,
-                            <&gpx1 4 3 0 0>,
-                            <&gpx1 5 3 0 0>,
-                            <&gpx1 6 3 0 0>,
-                            <&gpx1 7 3 0 0>;
-
                 key_1 {
                         keypad,row = <0>;
                         keypad,column = <3>;
@@ -143,9 +153,7 @@
                 #address-cells = <1>;
                 #size-cells = <0>;
                 samsung,i2c-sda-delay = <100>;
-                samsung,i2c-max-bus-freq = <20000>;
-                gpios = <&gpd1 0 2 3 0>,
-                        <&gpd1 1 2 3 0>;
+                samsung,i2c-max-bus-freq = <100000>;
                 status = "okay";
 
                 eeprom@50 {
@@ -160,9 +168,6 @@
         };
 
         spi_2: spi@13940000 {
-                gpios = <&gpc1 1 5 3 0>,
-                        <&gpc1 3 5 3 0>,
-                        <&gpc1 4 5 3 0>;
                 status = "okay";
 
                 w25x80@0 {
@@ -173,7 +178,7 @@
                         spi-max-frequency = <1000000>;
 
                         controller-data {
-                                cs-gpio = <&gpc1 2 1 0 3>;
+                                cs-gpio = <&gpc1 2 0>;
                                 samsung,spi-feedback-delay = <0>;
                         };
 
@@ -189,4 +194,16 @@
                         };
                 };
         };
+
+        fixed-rate-clocks {
+                xxti {
+                        compatible = "samsung,clock-xxti";
+                        clock-frequency = <12000000>;
+                };
+
+                xusbxti {
+                        compatible = "samsung,clock-xusbxti";
+                        clock-frequency = <24000000>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts
index c346b64dff55..9a14484c7bb1 100644
--- a/arch/arm/boot/dts/exynos4210-trats.dts
+++ b/arch/arm/boot/dts/exynos4210-trats.dts
@@ -289,4 +289,16 @@
                         };
                 };
         };
+
+        fixed-rate-clocks {
+                xxti {
+                        compatible = "samsung,clock-xxti";
+                        clock-frequency = <0>;
+                };
+
+                xusbxti {
+                        compatible = "samsung,clock-xusbxti";
+                        clock-frequency = <24000000>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index 2feffc70814c..9e6f381fa835 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -47,6 +47,36 @@
                              <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
         };
 
+        mct@10050000 {
+                compatible = "samsung,exynos4210-mct";
+                reg = <0x10050000 0x800>;
+                interrupt-controller;
+                #interrups-cells = <2>;
+                interrupt-parent = <&mct_map>;
+                interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
+                             <4 0>, <5 0>;
+                clocks = <&clock 3>, <&clock 344>;
+                clock-names = "fin_pll", "mct";
+
+                mct_map: mct-map {
+                        #interrupt-cells = <2>;
+                        #address-cells = <0>;
+                        #size-cells = <0>;
+                        interrupt-map = <0x0 0 &gic 0 57 0>,
+                                        <0x1 0 &gic 0 69 0>,
+                                        <0x2 0 &combiner 12 6>,
+                                        <0x3 0 &combiner 12 7>,
+                                        <0x4 0 &gic 0 42 0>,
+                                        <0x5 0 &gic 0 48 0>;
+                };
+        };
+
+        clock: clock-controller@0x10030000 {
+                compatible = "samsung,exynos4210-clock";
+                reg = <0x10030000 0x20000>;
+                #clock-cells = <1>;
+        };
+
         pinctrl_0: pinctrl@11400000 {
                 compatible = "samsung,exynos4210-pinctrl";
                 reg = <0x11400000 0x1000>;
@@ -76,4 +106,11 @@
                 reg = <0x100C0000 0x100>;
                 interrupts = <2 4>;
         };
+
+        g2d@12800000 {
+                compatible = "samsung,s5pv210-g2d";
+                reg = <0x12800000 0x1000>;
+                interrupts = <0 89 0>;
+                status = "disabled";
+        };
 };
diff --git a/arch/arm/boot/dts/exynos4212.dtsi b/arch/arm/boot/dts/exynos4212.dtsi
index c6ae2005961f..36d4299789ef 100644
--- a/arch/arm/boot/dts/exynos4212.dtsi
+++ b/arch/arm/boot/dts/exynos4212.dtsi
@@ -25,4 +25,26 @@
         gic:interrupt-controller@10490000 {
                 cpu-offset = <0x8000>;
         };
+
+        mct@10050000 {
+                compatible = "samsung,exynos4412-mct";
+                reg = <0x10050000 0x800>;
+                interrupt-controller;
+                #interrups-cells = <2>;
+                interrupt-parent = <&mct_map>;
+                interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
+                             <4 0>, <5 0>;
+
+                mct_map: mct-map {
+                        #interrupt-cells = <2>;
+                        #address-cells = <0>;
+                        #size-cells = <0>;
+                        interrupt-map = <0x0 0 &gic 0 57 0>,
+                                        <0x1 0 &combiner 12 5>,
+                                        <0x2 0 &combiner 12 6>,
+                                        <0x3 0 &combiner 12 7>,
+                                        <0x4 0 &gic 1 12 0>,
+                                        <0x5 0 &gic 1 12 0>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts
new file mode 100644
index 000000000000..15dc0a38b96d
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4412-odroidx.dts
@@ -0,0 +1,109 @@
+/*
+ * Hardkernel's Exynos4412 based ODROID-X board device tree source
+ *
+ * Copyright (c) 2012 Dongjin Kim <tobetter@gmail.com>
+ *
+ * Device tree source file for Hardkernel's ODROID-X board which is based on
+ * Samsung's Exynos4412 SoC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+/include/ "exynos4412.dtsi"
+
+/ {
+        model = "Hardkernel ODROID-X board based on Exynos4412";
+        compatible = "hardkernel,odroid-x", "samsung,exynos4412";
+
+        memory {
+                reg = <0x40000000 0x40000000>;
+        };
+
+        leds {
+                compatible = "gpio-leds";
+                led1 {
+                        label = "led1:heart";
+                        gpios = <&gpc1 0 1>;
+                        default-state = "on";
+                        linux,default-trigger = "heartbeat";
+                };
+                led2 {
+                        label = "led2:mmc0";
+                        gpios = <&gpc1 2 1>;
+                        default-state = "on";
+                        linux,default-trigger = "mmc0";
+                };
+        };
+
+        mshc@12550000 {
+                pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>;
+                pinctrl-names = "default";
+                status = "okay";
+
+                num-slots = <1>;
+                supports-highspeed;
+                broken-cd;
+                fifo-depth = <0x80>;
+                card-detect-delay = <200>;
+                samsung,dw-mshc-ciu-div = <3>;
+                samsung,dw-mshc-sdr-timing = <2 3>;
+                samsung,dw-mshc-ddr-timing = <1 2>;
+
+                slot@0 {
+                        reg = <0>;
+                        bus-width = <8>;
+                };
+        };
+
+        regulator_p3v3 {
+                compatible = "regulator-fixed";
+                regulator-name = "p3v3_en";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                gpio = <&gpa1 1 1>;
+                enable-active-high;
+                regulator-boot-on;
+        };
+
+        rtc@10070000 {
+                status = "okay";
+        };
+
+        sdhci@12530000 {
+                bus-width = <4>;
+                pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
+                pinctrl-names = "default";
+                status = "okay";
+        };
+
+        serial@13800000 {
+                status = "okay";
+        };
+
+        serial@13810000 {
+                status = "okay";
+        };
+
+        serial@13820000 {
+                status = "okay";
+        };
+
+        serial@13830000 {
+                status = "okay";
+        };
+
+        fixed-rate-clocks {
+                xxti {
+                        compatible = "samsung,clock-xxti";
+                        clock-frequency = <0>;
+                };
+
+                xusbxti {
+                        compatible = "samsung,clock-xusbxti";
+                        clock-frequency = <24000000>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts
new file mode 100644
index 000000000000..b39bffccde86
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4412-origen.dts
@@ -0,0 +1,451 @@
+/*
+ * Insignal's Exynos4412 based Origen board device tree source
+ *
+ * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Device tree source file for Insignal's Origen board which is based on
+ * Samsung's Exynos4412 SoC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+/include/ "exynos4412.dtsi"
+
+/ {
+        model = "Insignal Origen evaluation board based on Exynos4412";
+        compatible = "insignal,origen4412", "samsung,exynos4412";
+
+        memory {
+                reg = <0x40000000 0x40000000>;
+        };
+
+        chosen {
+                bootargs ="console=ttySAC2,115200";
+        };
+
+        mmc_reg: voltage-regulator {
+                compatible = "regulator-fixed";
+                regulator-name = "VMEM_VDD_2.8V";
+                regulator-min-microvolt = <2800000>;
+                regulator-max-microvolt = <2800000>;
+                gpio = <&gpx1 1 0>;
+                enable-active-high;
+        };
+
+        sdhci@12530000 {
+                bus-width = <4>;
+                pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sd2_cd>;
+                pinctrl-names = "default";
+                vmmc-supply = <&mmc_reg>;
+                status = "okay";
+        };
+
+        mshc@12550000 {
+                pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>;
+                pinctrl-names = "default";
+                status = "okay";
+
+                num-slots = <1>;
+                supports-highspeed;
+                broken-cd;
+                fifo-depth = <0x80>;
+                card-detect-delay = <200>;
+                samsung,dw-mshc-ciu-div = <3>;
+                samsung,dw-mshc-sdr-timing = <2 3>;
+                samsung,dw-mshc-ddr-timing = <1 2>;
+
+                slot@0 {
+                        reg = <0>;
+                        bus-width = <8>;
+                };
+        };
+
+        codec@13400000 {
+                samsung,mfc-r = <0x43000000 0x800000>;
+                samsung,mfc-l = <0x51000000 0x800000>;
+                status = "okay";
+        };
+
+        fimd@11c00000 {
+                pinctrl-0 = <&lcd_clk &lcd_data24 &pwm1_out>;
+                pinctrl-names = "default";
+                status = "okay";
+        };
+
+        display-timings {
+                native-mode = <&timing0>;
+                timing0: timing {
+                        clock-frequency = <50000>;
+                        hactive = <1024>;
+                        vactive = <600>;
+                        hfront-porch = <64>;
+                        hback-porch = <16>;
+                        hsync-len = <48>;
+                        vback-porch = <64>;
+                        vfront-porch = <16>;
+                        vsync-len = <3>;
+                };
+        };
+
+        serial@13800000 {
+                status = "okay";
+        };
+
+        serial@13810000 {
+                status = "okay";
+        };
+
+        serial@13820000 {
+                status = "okay";
+        };
+
+        serial@13830000 {
+                status = "okay";
+        };
+
+        i2c@13860000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                samsung,i2c-sda-delay = <100>;
+                samsung,i2c-max-bus-freq = <20000>;
+                pinctrl-0 = <&i2c0_bus>;
+                pinctrl-names = "default";
+                status = "okay";
+
+                s5m8767_pmic@66 {
+                        compatible = "samsung,s5m8767-pmic";
+                        reg = <0x66>;
+
+                        s5m8767,pmic-buck-default-dvs-idx = <3>;
+
+                        s5m8767,pmic-buck-dvs-gpios = <&gpx2 3 0>,
+                                                         <&gpx2 4 0>,
+                                                         <&gpx2 5 0>;
+
+                        s5m8767,pmic-buck-ds-gpios = <&gpm3 5 0>,
+                                                        <&gpm3 6 0>,
+                                                        <&gpm3 7 0>;
+
+                        s5m8767,pmic-buck2-dvs-voltage = <1250000>, <1200000>,
+                                                         <1200000>, <1200000>,
+                                                         <1200000>, <1200000>,
+                                                         <1200000>, <1200000>;
+
+                        s5m8767,pmic-buck3-dvs-voltage = <1100000>, <1100000>,
+                                                         <1100000>, <1100000>,
+                                                         <1100000>, <1100000>,
+                                                         <1100000>, <1100000>;
+
+                        s5m8767,pmic-buck4-dvs-voltage = <1200000>, <1200000>,
+                                                         <1200000>, <1200000>,
+                                                         <1200000>, <1200000>,
+                                                         <1200000>, <1200000>;
+
+                        regulators {
+                                ldo1_reg: LDO1 {
+                                        regulator-name = "VDD_ALIVE";
+                                        regulator-min-microvolt = <1100000>;
+                                        regulator-max-microvolt = <1100000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo2_reg: LDO2 {
+                                        regulator-name = "VDDQ_M12";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo3_reg: LDO3 {
+                                        regulator-name = "VDDIOAP_18";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo4_reg: LDO4 {
+                                        regulator-name = "VDDQ_PRE";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo5_reg: LDO5 {
+                                        regulator-name = "VDD18_2M";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo6_reg: LDO6 {
+                                        regulator-name = "VDD10_MPLL";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo7_reg: LDO7 {
+                                        regulator-name = "VDD10_XPLL";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo8_reg: LDO8 {
+                                        regulator-name = "VDD10_MIPI";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo9_reg: LDO9 {
+                                        regulator-name = "VDD33_LCD";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo10_reg: LDO10 {
+                                        regulator-name = "VDD18_MIPI";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo11_reg: LDO11 {
+                                        regulator-name = "VDD18_ABB1";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo12_reg: LDO12 {
+                                        regulator-name = "VDD33_UOTG";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo13_reg: LDO13 {
+                                        regulator-name = "VDDIOPERI_18";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo14_reg: LDO14 {
+                                        regulator-name = "VDD18_ABB02";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo15_reg: LDO15 {
+                                        regulator-name = "VDD10_USH";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo16_reg: LDO16 {
+                                        regulator-name = "VDD18_HSIC";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo17_reg: LDO17 {
+                                        regulator-name = "VDDIOAP_MMC012_28";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo18_reg: LDO18 {
+                                        regulator-name = "VDDIOPERI_28";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo19_reg: LDO19 {
+                                        regulator-name = "DVDD25";
+                                        regulator-min-microvolt = <2500000>;
+                                        regulator-max-microvolt = <2500000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo20_reg: LDO20 {
+                                        regulator-name = "VDD28_CAM";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo21_reg: LDO21 {
+                                        regulator-name = "VDD28_AF";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo22_reg: LDO22 {
+                                        regulator-name = "VDDA28_2M";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo23_reg: LDO23 {
+                                        regulator-name = "VDD28_TF";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo24_reg: LDO24 {
+                                        regulator-name = "VDD33_A31";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo25_reg: LDO25 {
+                                        regulator-name = "VDD18_CAM";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo26_reg: LDO26 {
+                                        regulator-name = "VDD18_A31";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo27_reg: LDO27 {
+                                        regulator-name = "GPS_1V8";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo28_reg: LDO28 {
+                                        regulator-name = "DVDD12";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                buck1_reg: BUCK1 {
+                                        regulator-name = "vdd_mif";
+                                        regulator-min-microvolt = <950000>;
+                                        regulator-max-microvolt = <1100000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                buck2_reg: BUCK2 {
+                                        regulator-name = "vdd_arm";
+                                        regulator-min-microvolt = <925000>;
+                                        regulator-max-microvolt = <1300000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                buck3_reg: BUCK3 {
+                                        regulator-name = "vdd_int";
+                                        regulator-min-microvolt = <900000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                buck4_reg: BUCK4 {
+                                        regulator-name = "vdd_g3d";
+                                        regulator-min-microvolt = <750000>;
+                                        regulator-max-microvolt = <1500000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                buck5_reg: BUCK5 {
+                                        regulator-name = "vdd_m12";
+                                        regulator-min-microvolt = <750000>;
+                                        regulator-max-microvolt = <1500000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                buck6_reg: BUCK6 {
+                                        regulator-name = "vdd12_5m";
+                                        regulator-min-microvolt = <750000>;
+                                        regulator-max-microvolt = <1500000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                buck9_reg: BUCK9 {
+                                        regulator-name = "vddf28_emmc";
+                                        regulator-min-microvolt = <750000>;
+                                        regulator-max-microvolt = <3000000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+                        };
+                };
+        };
+
+        fixed-rate-clocks {
+                xxti {
+                        compatible = "samsung,clock-xxti";
+                        clock-frequency = <0>;
+                };
+
+                xusbxti {
+                        compatible = "samsung,clock-xusbxti";
+                        clock-frequency = <24000000>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/exynos4412-smdk4412.dts b/arch/arm/boot/dts/exynos4412-smdk4412.dts
index f05bf575cc45..dd564310d4a5 100644
--- a/arch/arm/boot/dts/exynos4412-smdk4412.dts
+++ b/arch/arm/boot/dts/exynos4412-smdk4412.dts
@@ -27,6 +27,27 @@
                 bootargs ="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc";
         };
 
+        g2d@10800000 {
+                status = "okay";
+        };
+
+        g2d@10800000 {
+                status = "okay";
+        };
+
+        sdhci@12530000 {
+                bus-width = <4>;
+                pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sd2_cd>;
+                pinctrl-names = "default";
+                status = "okay";
+        };
+
+        codec@13400000 {
+                samsung,mfc-r = <0x43000000 0x800000>;
+                samsung,mfc-l = <0x51000000 0x800000>;
+                status = "okay";
+        };
+
         serial@13800000 {
                 status = "okay";
         };
@@ -42,4 +63,16 @@
         serial@13830000 {
                 status = "okay";
         };
+
+        fixed-rate-clocks {
+                xxti {
+                        compatible = "samsung,clock-xxti";
+                        clock-frequency = <0>;
+                };
+
+                xusbxti {
+                        compatible = "samsung,clock-xusbxti";
+                        clock-frequency = <24000000>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi
index d7dfe312772a..d75c047e80a9 100644
--- a/arch/arm/boot/dts/exynos4412.dtsi
+++ b/arch/arm/boot/dts/exynos4412.dtsi
@@ -25,4 +25,30 @@
         gic:interrupt-controller@10490000 {
                 cpu-offset = <0x4000>;
         };
+
+        mct@10050000 {
+                compatible = "samsung,exynos4412-mct";
+                reg = <0x10050000 0x800>;
+                interrupt-controller;
+                #interrups-cells = <2>;
+                interrupt-parent = <&mct_map>;
+                interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
+                             <4 0>, <5 0>, <6 0>, <7 0>;
+                clocks = <&clock 3>, <&clock 344>;
+                clock-names = "fin_pll", "mct";
+
+                mct_map: mct-map {
+                        #interrupt-cells = <2>;
+                        #address-cells = <0>;
+                        #size-cells = <0>;
+                        interrupt-map = <0x0 0 &gic 0 57 0>,
+                                        <0x1 0 &combiner 12 5>,
+                                        <0x2 0 &combiner 12 6>,
+                                        <0x3 0 &combiner 12 7>,
+                                        <0x4 0 &gic 1 12 0>,
+                                        <0x5 0 &gic 1 12 0>,
+                                        <0x6 0 &gic 1 12 0>,
+                                        <0x7 0 &gic 1 12 0>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
index 9a8780694909..e3380a7a285c 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -36,6 +36,12 @@
                              <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>;
         };
 
+        clock: clock-controller@0x10030000 {
+                compatible = "samsung,exynos4412-clock";
+                reg = <0x10030000 0x20000>;
+                #clock-cells = <1>;
+        };
+
         pinctrl_0: pinctrl@11400000 {
                 compatible = "samsung,exynos4x12-pinctrl";
                 reg = <0x11400000 0x1000>;
@@ -66,4 +72,11 @@
                 reg = <0x106E0000 0x1000>;
                 interrupts = <0 72 0>;
         };
+
+        g2d@10800000 {
+                compatible = "samsung,exynos4212-g2d";
+                reg = <0x10800000 0x1000>;
+                interrupts = <0 89 0>;
+                status = "disabled";
+        };
 };
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts
new file mode 100644
index 000000000000..02cfc76d002f
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -0,0 +1,452 @@
+/*
+ * Samsung's Exynos5250 based Arndale board device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+/include/ "exynos5250.dtsi"
+
+/ {
+        model = "Insignal Arndale evaluation board based on EXYNOS5250";
+        compatible = "insignal,arndale", "samsung,exynos5250";
+
+        memory {
+                reg = <0x40000000 0x80000000>;
+        };
+
+        chosen {
+                bootargs = "console=ttySAC2,115200";
+        };
+
+        codec@11000000 {
+                samsung,mfc-r = <0x43000000 0x800000>;
+                samsung,mfc-l = <0x51000000 0x800000>;
+        };
+
+        i2c@12C60000 {
+                samsung,i2c-sda-delay = <100>;
+                samsung,i2c-max-bus-freq = <20000>;
+                samsung,i2c-slave-addr = <0x66>;
+
+                s5m8767_pmic@66 {
+                        compatible = "samsung,s5m8767-pmic";
+                        reg = <0x66>;
+
+                        s5m8767,pmic-buck2-dvs-voltage = <1300000>;
+                        s5m8767,pmic-buck3-dvs-voltage = <1100000>;
+                        s5m8767,pmic-buck4-dvs-voltage = <1200000>;
+                        s5m8767,pmic-buck-dvs-gpios = <&gpd1 0 0>,
+                                                        <&gpd1 1 0>,
+                                                        <&gpd1 2 0>;
+                        s5m8767,pmic-buck-ds-gpios = <&gpx2 3 0>,
+                                                        <&gpx2 4 0>,
+                                                        <&gpx2 5 0>;
+                        regulators {
+                                ldo1_reg: LDO1 {
+                                        regulator-name = "VDD_ALIVE_1.0V";
+                                        regulator-min-microvolt = <1100000>;
+                                        regulator-max-microvolt = <1100000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                        op_mode = <1>;
+                                };
+
+                                ldo2_reg: LDO2 {
+                                        regulator-name = "VDD_28IO_DP_1.35V";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                        op_mode = <1>;
+                                };
+
+                                ldo3_reg: LDO3 {
+                                        regulator-name = "VDD_COMMON1_1.8V";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                        op_mode = <1>;
+                                };
+
+                                ldo4_reg: LDO4 {
+                                        regulator-name = "VDD_IOPERI_1.8V";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        op_mode = <1>;
+                                };
+
+                                ldo5_reg: LDO5 {
+                                        regulator-name = "VDD_EXT_1.8V";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                        op_mode = <1>;
+                                };
+
+                                ldo6_reg: LDO6 {
+                                        regulator-name = "VDD_MPLL_1.1V";
+                                        regulator-min-microvolt = <1100000>;
+                                        regulator-max-microvolt = <1100000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                        op_mode = <1>;
+                                };
+
+                                ldo7_reg: LDO7 {
+                                        regulator-name = "VDD_XPLL_1.1V";
+                                        regulator-min-microvolt = <1100000>;
+                                        regulator-max-microvolt = <1100000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                        op_mode = <1>;
+                                };
+
+                                ldo8_reg: LDO8 {
+                                        regulator-name = "VDD_COMMON2_1.0V";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                        op_mode = <1>;
+                                };
+
+                                ldo9_reg: LDO9 {
+                                        regulator-name = "VDD_33ON_3.0V";
+                                        regulator-min-microvolt = <3000000>;
+                                        regulator-max-microvolt = <3000000>;
+                                        op_mode = <1>;
+                                };
+
+                                ldo10_reg: LDO10 {
+                                        regulator-name = "VDD_COMMON3_1.8V";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                        op_mode = <1>;
+                                };
+
+                                ldo11_reg: LDO11 {
+                                        regulator-name = "VDD_ABB2_1.8V";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                        op_mode = <1>;
+                                };
+
+                                ldo12_reg: LDO12 {
+                                        regulator-name = "VDD_USB_3.0V";
+                                        regulator-min-microvolt = <3000000>;
+                                        regulator-max-microvolt = <3000000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                        op_mode = <1>;
+                                };
+
+                                ldo13_reg: LDO13 {
+                                        regulator-name = "VDDQ_C2C_W_1.8V";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                        op_mode = <1>;
+                                };
+
+                                ldo14_reg: LDO14 {
+                                        regulator-name = "VDD18_ABB0_3_1.8V";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                        op_mode = <1>;
+                                };
+
+                                ldo15_reg: LDO15 {
+                                        regulator-name = "VDD10_COMMON4_1.0V";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                        op_mode = <1>;
+                                };
+
+                                ldo16_reg: LDO16 {
+                                        regulator-name = "VDD18_HSIC_1.8V";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                        op_mode = <1>;
+                                };
+
+                                ldo17_reg: LDO17 {
+                                        regulator-name = "VDDQ_MMC2_3_2.8V";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                        op_mode = <1>;
+                                };
+
+                                ldo18_reg: LDO18 {
+                                        regulator-name = "VDD_33ON_2.8V";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                        op_mode = <1>;
+                                };
+
+                                ldo22_reg: LDO22 {
+                                        regulator-name = "EXT_33_OFF";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        op_mode = <1>;
+                                };
+
+                                ldo23_reg: LDO23 {
+                                        regulator-name = "EXT_28_OFF";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                        op_mode = <1>;
+                                };
+
+                                ldo25_reg: LDO25 {
+                                        regulator-name = "PVDD_LDO25";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        op_mode = <1>;
+                                };
+
+                                ldo26_reg: LDO26 {
+                                        regulator-name = "EXT_18_OFF";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        op_mode = <1>;
+                                };
+
+                                buck1_reg: BUCK1 {
+                                        regulator-name = "vdd_mif";
+                                        regulator-min-microvolt = <950000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                        op_mode = <1>;
+                                };
+
+                                buck2_reg: BUCK2 {
+                                        regulator-name = "vdd_arm";
+                                        regulator-min-microvolt = <925000>;
+                                        regulator-max-microvolt = <1300000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                        op_mode = <1>;
+                                };
+
+                                buck3_reg: BUCK3 {
+                                        regulator-name = "vdd_int";
+                                        regulator-min-microvolt = <900000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                        op_mode = <1>;
+                                };
+
+                                buck4_reg: BUCK4 {
+                                        regulator-name = "vdd_g3d";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-boot-on;
+                                        op_mode = <1>;
+                                };
+
+                                buck5_reg: BUCK5 {
+                                        regulator-name = "VDD_MEM_1.35V";
+                                        regulator-min-microvolt = <750000>;
+                                        regulator-max-microvolt = <1355000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                        op_mode = <1>;
+                                };
+
+                                buck9_reg: BUCK9 {
+                                        regulator-name = "VDD_33_OFF_EXT1";
+                                        regulator-min-microvolt = <750000>;
+                                        regulator-max-microvolt = <3000000>;
+                                        op_mode = <1>;
+                                };
+                        };
+                };
+        };
+
+        i2c@12C70000 {
+                status = "disabled";
+        };
+
+        i2c@12C80000 {
+                status = "disabled";
+        };
+
+        i2c@12C90000 {
+                status = "disabled";
+        };
+
+        i2c@12CA0000 {
+                status = "disabled";
+        };
+
+        i2c@12CB0000 {
+                status = "disabled";
+        };
+
+        i2c@12CC0000 {
+                status = "disabled";
+        };
+
+        i2c@12CD0000 {
+                status = "disabled";
+        };
+
+        i2c@121D0000 {
+                status = "disabled";
+        };
+
+        dwmmc_0: dwmmc0@12200000 {
+                num-slots = <1>;
+                supports-highspeed;
+                broken-cd;
+                fifo-depth = <0x80>;
+                card-detect-delay = <200>;
+                samsung,dw-mshc-ciu-div = <3>;
+                samsung,dw-mshc-sdr-timing = <2 3>;
+                samsung,dw-mshc-ddr-timing = <1 2>;
+                vmmc-supply = <&mmc_reg>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
+
+                slot@0 {
+                        reg = <0>;
+                        bus-width = <8>;
+                };
+        };
+
+        dwmmc_1: dwmmc1@12210000 {
+                status = "disabled";
+        };
+
+        dwmmc_2: dwmmc2@12220000 {
+                num-slots = <1>;
+                supports-highspeed;
+                fifo-depth = <0x80>;
+                card-detect-delay = <200>;
+                samsung,dw-mshc-ciu-div = <3>;
+                samsung,dw-mshc-sdr-timing = <2 3>;
+                samsung,dw-mshc-ddr-timing = <1 2>;
+                vmmc-supply = <&mmc_reg>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
+
+                slot@0 {
+                        reg = <0>;
+                        bus-width = <4>;
+                        disable-wp;
+                };
+        };
+
+        dwmmc_3: dwmmc3@12230000 {
+                status = "disabled";
+        };
+
+        spi_0: spi@12d20000 {
+                status = "disabled";
+        };
+
+        spi_1: spi@12d30000 {
+                status = "disabled";
+        };
+
+        spi_2: spi@12d40000 {
+                status = "disabled";
+        };
+
+        gpio_keys {
+                compatible = "gpio-keys";
+
+                menu {
+                        label = "SW-TACT2";
+                        gpios = <&gpx1 4 1>;
+                        linux,code = <139>;
+                        gpio-key,wakeup;
+                };
+
+                home {
+                        label = "SW-TACT3";
+                        gpios = <&gpx1 5 1>;
+                        linux,code = <102>;
+                        gpio-key,wakeup;
+                };
+
+                up {
+                        label = "SW-TACT4";
+                        gpios = <&gpx1 6 1>;
+                        linux,code = <103>;
+                        gpio-key,wakeup;
+                };
+
+                down {
+                        label = "SW-TACT5";
+                        gpios = <&gpx1 7 1>;
+                        linux,code = <108>;
+                        gpio-key,wakeup;
+                };
+
+                back {
+                        label = "SW-TACT6";
+                        gpios = <&gpx2 0 1>;
+                        linux,code = <158>;
+                        gpio-key,wakeup;
+                };
+
+                wakeup {
+                        label = "SW-TACT7";
+                        gpios = <&gpx2 1 1>;
+                        linux,code = <143>;
+                        gpio-key,wakeup;
+                };
+        };
+
+        hdmi {
+                hpd-gpio = <&gpx3 7 2>;
+                vdd_osc-supply = <&ldo10_reg>;
+                vdd_pll-supply = <&ldo8_reg>;
+                vdd-supply = <&ldo8_reg>;
+        };
+
+        mmc_reg: voltage-regulator {
+                compatible = "regulator-fixed";
+                regulator-name = "VDD_33ON_2.8V";
+                regulator-min-microvolt = <2800000>;
+                regulator-max-microvolt = <2800000>;
+                gpio = <&gpx1 1 1>;
+                enable-active-high;
+        };
+
+        reg_hdmi_en: fixedregulator@0 {
+                compatible = "regulator-fixed";
+                regulator-name = "hdmi-en";
+        };
+
+        fixed-rate-clocks {
+                xxti {
+                        compatible = "samsung,clock-xxti";
+                        clock-frequency = <24000000>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi
new file mode 100644
index 000000000000..d1650fb34c0a
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi
@@ -0,0 +1,783 @@
+/*
+ * Samsung's Exynos5250 SoC pin-mux and pin-config device tree source
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Samsung's Exynos5250 SoC pin-mux and pin-config optiosn are listed as device
+ * tree nodes are listed in this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/ {
+        pinctrl@11400000 {
+                gpa0: gpa0 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gpa1: gpa1 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gpa2: gpa2 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gpb0: gpb0 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gpb1: gpb1 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gpb2: gpb2 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gpb3: gpb3 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gpc0: gpc0 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gpc1: gpc1 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gpc2: gpc2 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gpc3: gpc3 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gpd0: gpd0 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gpd1: gpd1 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gpy0: gpy0 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                };
+
+                gpy1: gpy1 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                };
+
+                gpy2: gpy2 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                };
+
+                gpy3: gpy3 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                };
+
+                gpy4: gpy4 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                };
+
+                gpy5: gpy5 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                };
+
+                gpy6: gpy6 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                };
+
+                gpc4: gpc4 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gpx0: gpx0 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        interrupt-parent = <&combiner>;
+                        #interrupt-cells = <2>;
+                        interrupts = <23 0>, <24 0>, <25 0>, <25 1>,
+                                     <26 0>, <26 1>, <27 0>, <27 1>;
+                };
+
+                gpx1: gpx1 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        interrupt-parent = <&combiner>;
+                        #interrupt-cells = <2>;
+                        interrupts = <28 0>, <28 1>, <29 0>, <29 1>,
+                                     <30 0>, <30 1>, <31 0>, <31 1>;
+                };
+
+                gpx2: gpx2 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gpx3: gpx3 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                uart0_data: uart0-data {
+                        samsung,pins = "gpa0-0", "gpa0-1";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+
+                uart0_fctl: uart0-fctl {
+                        samsung,pins = "gpa0-2", "gpa0-3";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samaung,pin-drv = <0>;
+                };
+
+                i2c2_bus: i2c2-bus {
+                        samsung,pins = "gpa0-6", "gpa0-7";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <3>;
+                        samaung,pin-drv = <0>;
+                };
+
+                i2c2_hs_bus: i2c2-hs-bus {
+                        samsung,pins = "gpa0-6", "gpa0-7";
+                        samsung,pin-function = <4>;
+                        samsung,pin-pud = <3>;
+                        samaung,pin-drv = <0>;
+                };
+
+                uart2_data: uart2-data {
+                        samsung,pins = "gpa1-0", "gpa1-1";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+
+                uart2_fctl: uart2-fctl {
+                        samsung,pins = "gpa1-2", "gpa1-3";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samaung,pin-drv = <0>;
+                };
+
+                i2c3_bus: i2c3-bus {
+                        samsung,pins = "gpa1-2", "gpa1-3";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <3>;
+                        samaung,pin-drv = <0>;
+                };
+
+                i2c3_hs_bus: i2c3-hs-bus {
+                        samsung,pins = "gpa1-2", "gpa1-3";
+                        samsung,pin-function = <4>;
+                        samsung,pin-pud = <3>;
+                        samaung,pin-drv = <0>;
+                };
+
+                uart3_data: uart3-data {
+                        samsung,pins = "gpa1-4", "gpa1-4";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+
+                spi0_bus: spi0-bus {
+                        samsung,pins = "gpa2-0", "gpa2-2", "gpa2-3";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+
+                i2c4_bus: i2c4-bus {
+                        samsung,pins = "gpa2-0", "gpa2-1";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <3>;
+                        samaung,pin-drv = <0>;
+                };
+
+                i2c5_bus: i2c5-bus {
+                        samsung,pins = "gpa2-2", "gpa2-3";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <3>;
+                        samaung,pin-drv = <0>;
+                };
+
+                spi1_bus: spi1-bus {
+                        samsung,pins = "gpa2-4", "gpa2-6", "gpa2-7";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+
+                i2s1_bus: i2s1-bus {
+                        samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3",
+                                        "gpb0-4";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+
+                pcm1_bus: pcm1-bus {
+                        samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3",
+                                        "gpb0-4";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+
+                ac97_bus: ac97-bus {
+                        samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3",
+                                        "gpb0-4";
+                        samsung,pin-function = <4>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+
+                i2s2_bus: i2s2-bus {
+                        samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3",
+                                        "gpb1-4";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+
+                pcm2_bus: pcm2-bus {
+                        samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3",
+                                        "gpb1-4";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+
+                spdif_bus: spdif-bus {
+                        samsung,pins = "gpb1-0", "gpb1-1";
+                        samsung,pin-function = <4>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+
+                spi2_bus: spi2-bus {
+                        samsung,pins = "gpb1-1", "gpb1-3", "gpb1-4";
+                        samsung,pin-function = <5>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+
+                i2c6_bus: i2c6-bus {
+                        samsung,pins = "gpb1-3", "gpb1-4";
+                        samsung,pin-function = <4>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+
+                i2c7_bus: i2c7-bus {
+                        samsung,pins = "gpb2-2", "gpb2-3";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+
+                i2c0_bus: i2c0-bus {
+                        samsung,pins = "gpb3-0", "gpb3-1";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+
+                i2c1_bus: i2c1-bus {
+                        samsung,pins = "gpb3-2", "gpb3-3";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+
+                i2c0_hs_bus: i2c0-hs-bus {
+                        samsung,pins = "gpb3-0", "gpb3-1";
+                        samsung,pin-function = <4>;
+                        samsung,pin-pud = <3>;
+                        samaung,pin-drv = <0>;
+                };
+
+                i2c1_hs_bus: i2c1-hs-bus {
+                        samsung,pins = "gpb3-2", "gpb3-3";
+                        samsung,pin-function = <4>;
+                        samsung,pin-pud = <3>;
+                        samaung,pin-drv = <0>;
+                };
+
+                sd0_clk: sd0-clk {
+                        samsung,pins = "gpc0-0";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <3>;
+                };
+
+                sd0_cmd: sd0-cmd {
+                        samsung,pins = "gpc0-1";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <3>;
+                };
+
+                sd0_cd: sd0-cd {
+                        samsung,pins = "gpc0-2";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <3>;
+                };
+
+                sd0_bus1: sd0-bus-width1 {
+                        samsung,pins = "gpc0-3";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <3>;
+                };
+
+                sd0_bus4: sd0-bus-width4 {
+                        samsung,pins = "gpc0-3", "gpc0-4", "gpc0-5", "gpc0-6";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <3>;
+                };
+
+                sd0_bus8: sd0-bus-width8 {
+                        samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <3>;
+                };
+
+                sd1_clk: sd1-clk {
+                        samsung,pins = "gpc2-0";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <3>;
+                };
+
+                sd1_cmd: sd1-cmd {
+                        samsung,pins = "gpc2-1";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <3>;
+                };
+
+                sd1_cd: sd1-cd {
+                        samsung,pins = "gpc2-2";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <3>;
+                };
+
+                sd1_bus1: sd1-bus-width1 {
+                        samsung,pins = "gpc2-3";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <3>;
+                };
+
+                sd1_bus4: sd1-bus-width4 {
+                        samsung,pins = "gpc2-3", "gpc2-4", "gpc2-5", "gpc2-6";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <3>;
+                };
+
+                sd2_clk: sd2-clk {
+                        samsung,pins = "gpc3-0";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <3>;
+                };
+
+                sd2_cmd: sd2-cmd {
+                        samsung,pins = "gpc3-1";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <3>;
+                };
+
+                sd2_cd: sd2-cd {
+                        samsung,pins = "gpc3-2";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <3>;
+                };
+
+                sd2_bus1: sd2-bus-width1 {
+                        samsung,pins = "gpc3-3";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <3>;
+                };
+
+                sd2_bus4: sd2-bus-width4 {
+                        samsung,pins = "gpc3-3", "gpc3-4", "gpc3-5", "gpc3-6";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <3>;
+                };
+
+                sd2_bus8: sd2-bus-width8 {
+                        samsung,pins = "gpc4-3", "gpc4-4", "gpc4-5", "gpc4-6";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <3>;
+                };
+
+                sd3_clk: sd3-clk {
+                        samsung,pins = "gpc4-0";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <3>;
+                };
+
+                sd3_cmd: sd3-cmd {
+                        samsung,pins = "gpc4-1";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <3>;
+                };
+
+                sd3_cd: sd3-cd {
+                        samsung,pins = "gpc4-2";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <3>;
+                };
+
+                sd3_bus1: sd3-bus-width1 {
+                        samsung,pins = "gpc4-3";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <3>;
+                };
+
+                sd3_bus4: sd3-bus-width4 {
+                        samsung,pins = "gpc4-3", "gpc4-4", "gpc4-5", "gpc4-6";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <3>;
+                };
+
+                uart1_data: uart1-data {
+                        samsung,pins = "gpd0-0", "gpd0-1";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+
+                uart1_fctl: uart1-fctl {
+                        samsung,pins = "gpd0-2", "gpd0-3";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samaung,pin-drv = <0>;
+                };
+        };
+
+        pinctrl@13400000 {
+                gpe0: gpe0 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gpe1: gpe1 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gpf0: gpf0 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gpf1: gpf1 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gpg0: gpg0 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gpg1: gpg1 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gpg2: gpg2 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gph0: gph0 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gph1: gph1 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                cam_gpio_a: cam-gpio-a {
+                        samsung,pins = "gpe0-0", "gpe0-1", "gpe0-2", "gpe0-3",
+                                       "gpe0-4", "gpe0-5", "gpe0-6", "gpe0-7",
+                                       "gpe1-0", "gpe1-1";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+
+                cam_gpio_b: cam-gpio-b {
+                        samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3",
+                                       "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <0>;
+                        samaung,pin-drv = <0>;
+                };
+
+                cam_i2c2_bus: cam-i2c2-bus {
+                        samsung,pins = "gpe0-6", "gpe1-0";
+                        samsung,pin-function = <4>;
+                        samsung,pin-pud = <3>;
+                        samaung,pin-drv = <0>;
+                };
+
+                cam_spi1_bus: cam-spi1-bus {
+                        samsung,pins = "gpe0-4", "gpe0-5", "gpf0-2", "gpf0-3";
+                        samsung,pin-function = <4>;
+                        samsung,pin-pud = <0>;
+                        samaung,pin-drv = <0>;
+                };
+
+                cam_i2c1_bus: cam-i2c1-bus {
+                        samsung,pins = "gpf0-2", "gpf0-3";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samaung,pin-drv = <0>;
+                };
+
+                cam_i2c0_bus: cam-i2c0-bus {
+                        samsung,pins = "gpf0-0", "gpf0-1";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samaung,pin-drv = <0>;
+                };
+
+                cam_spi0_bus: cam-spi0-bus {
+                        samsung,pins = "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samaung,pin-drv = <0>;
+                };
+
+                cam_bayrgb_bus: cam-bayrgb-bus {
+                        samsung,pins = "gpg0-0", "gpg0-1", "gpg0-2", "gpg0-3",
+                                       "gpg0-4", "gpg0-5", "gpg0-6", "gpg0-7",
+                                       "gpg1-0", "gpg1-1", "gpg1-2", "gpg1-3",
+                                       "gpg1-4", "gpg1-5", "gpg1-6", "gpg1-7",
+                                       "gpg2-0", "gpg2-1";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samaung,pin-drv = <0>;
+                };
+
+                cam_port_a: cam-port-a {
+                        samsung,pins = "gph0-0", "gph0-1", "gph0-2", "gph0-3",
+                                       "gph1-0", "gph1-1", "gph1-2", "gph1-3",
+                                       "gph1-4", "gph1-5", "gph1-6", "gph1-7";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samaung,pin-drv = <0>;
+                };
+        };
+
+        pinctrl@10d10000 {
+                gpv0: gpv0 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gpv1: gpv1 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gpv2: gpv2 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gpv3: gpv3 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gpv4: gpv4 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                c2c_rxd: c2c-rxd {
+                        samsung,pins = "gpv0-0", "gpv0-1", "gpv0-2", "gpv0-3",
+                                       "gpv0-4", "gpv0-5", "gpv0-6", "gpv0-7",
+                                       "gpv1-0", "gpv1-1", "gpv1-2", "gpv1-3",
+                                       "gpv1-4", "gpv1-5", "gpv1-6", "gpv1-7";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samaung,pin-drv = <0>;
+                };
+
+                c2c_txd: c2c-txd {
+                        samsung,pins = "gpv2-0", "gpv2-1", "gpv2-2", "gpv2-3",
+                                       "gpv2-4", "gpv2-5", "gpv2-6", "gpv2-7",
+                                       "gpv3-0", "gpv3-1", "gpv3-2", "gpv3-3",
+                                       "gpv3-4", "gpv3-5", "gpv3-6", "gpv3-7";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samaung,pin-drv = <0>;
+                };
+        };
+
+        pinctrl@03680000 {
+                gpz: gpz {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                i2s0_bus: i2s0-bus {
+                        samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3",
+                                        "gpz-4", "gpz-5", "gpz-6";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 1b8d4106d338..26d856ba50a1 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -30,8 +30,6 @@
         i2c@12C60000 {
                 samsung,i2c-sda-delay = <100>;
                 samsung,i2c-max-bus-freq = <20000>;
-                gpios = <&gpb3 0 2 3 0>,
-                        <&gpb3 1 2 3 0>;
 
                 eeprom@50 {
                         compatible = "samsung,s524ad0xd1";
@@ -42,8 +40,6 @@
         i2c@12C70000 {
                 samsung,i2c-sda-delay = <100>;
                 samsung,i2c-max-bus-freq = <20000>;
-                gpios = <&gpb3 2 2 3 0>,
-                        <&gpb3 3 2 3 0>;
 
                 eeprom@51 {
                         compatible = "samsung,s524ad0xd1";
@@ -74,8 +70,6 @@
         i2c@12C80000 {
                 samsung,i2c-sda-delay = <100>;
                 samsung,i2c-max-bus-freq = <66000>;
-                gpios = <&gpa0 6 3 3 0>,
-                        <&gpa0 7 3 3 0>;
 
                 hdmiddc@50 {
                         compatible = "samsung,exynos5-hdmiddc";
@@ -122,15 +116,12 @@
                 samsung,dw-mshc-ciu-div = <3>;
                 samsung,dw-mshc-sdr-timing = <2 3>;
                 samsung,dw-mshc-ddr-timing = <1 2>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
 
                 slot@0 {
                         reg = <0>;
                         bus-width = <8>;
-                        gpios = <&gpc0 0 2 0 3>, <&gpc0 1 2 0 3>,
-                                <&gpc1 0 2 3 3>, <&gpc1 1 2 3 3>,
-                                <&gpc1 2 2 3 3>, <&gpc1 3 2 3 3>,
-                                <&gpc0 3 2 3 3>, <&gpc0 4 2 3 3>,
-                                <&gpc0 5 2 3 3>, <&gpc0 6 2 3 3>;
                 };
         };
 
@@ -146,17 +137,13 @@
                 samsung,dw-mshc-ciu-div = <3>;
                 samsung,dw-mshc-sdr-timing = <2 3>;
                 samsung,dw-mshc-ddr-timing = <1 2>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
 
                 slot@0 {
                         reg = <0>;
                         bus-width = <4>;
-                        samsung,cd-pinmux-gpio = <&gpc3 2 2 3 3>;
                         disable-wp;
-                        gpios = <&gpc3 0 2 0 3>, <&gpc3 1 2 0 3>,
-                                <&gpc3 3 2 3 3>, <&gpc3 4 2 3 3>,
-                                <&gpc3 5 2 3 3>, <&gpc3 6 2 3 3>,
-                                <&gpc4 3 3 3 3>, <&gpc4 3 3 3 3>,
-                                <&gpc4 5 3 3 3>, <&gpc4 6 3 3 3>;
                 };
         };
 
@@ -169,10 +156,6 @@
         };
 
         spi_1: spi@12d30000 {
-                gpios = <&gpa2 4 2 3 0>,
-                        <&gpa2 6 2 3 0>,
-                        <&gpa2 7 2 3 0>;
-
                 w25q80bw@0 {
                         #address-cells = <1>;
                         #size-cells = <1>;
@@ -181,7 +164,7 @@
                         spi-max-frequency = <1000000>;
 
                         controller-data {
-                                cs-gpio = <&gpa2 5 1 0 3>;
+                                cs-gpio = <&gpa2 5 0>;
                                 samsung,spi-feedback-delay = <0>;
                         };
 
@@ -203,7 +186,7 @@
         };
 
         hdmi {
-                hpd-gpio = <&gpx3 7 0xf 1 3>;
+                hpd-gpio = <&gpx3 7 0>;
         };
 
         codec@11000000 {
@@ -212,9 +195,7 @@
         };
 
         i2s0: i2s@03830000 {
-                gpios = <&gpz 0 2 0 0>, <&gpz 1 2 0 0>, <&gpz 2 2 0 0>,
-                        <&gpz 3 2 0 0>, <&gpz 4 2 0 0>, <&gpz 5 2 0 0>,
-                        <&gpz 6 2 0 0>;
+                status = "okay";
         };
 
         i2s1: i2s@12D60000 {
@@ -231,4 +212,40 @@
                 samsung,i2s-controller = <&i2s0>;
                 samsung,audio-codec = <&wm8994>;
         };
+
+        usb@12110000 {
+                samsung,vbus-gpio = <&gpx2 6 1 3 3>;
+        };
+
+        dp-controller {
+                samsung,color-space = <0>;
+                samsung,dynamic-range = <0>;
+                samsung,ycbcr-coeff = <0>;
+                samsung,color-depth = <1>;
+                samsung,link-rate = <0x0a>;
+                samsung,lane-count = <4>;
+        };
+
+        display-timings {
+                native-mode = <&timing0>;
+                timing0: timing@0 {
+                        /* 1280x800 */
+                        clock-frequency = <50000>;
+                        hactive = <1280>;
+                        vactive = <800>;
+                        hfront-porch = <4>;
+                        hback-porch = <4>;
+                        hsync-len = <4>;
+                        vback-porch = <4>;
+                        vfront-porch = <4>;
+                        vsync-len = <4>;
+                };
+        };
+
+        fixed-rate-clocks {
+                xxti {
+                        compatible = "samsung,clock-xxti";
+                        clock-frequency = <24000000>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts
index 17dd951c1cd2..581ffae27e13 100644
--- a/arch/arm/boot/dts/exynos5250-snow.dts
+++ b/arch/arm/boot/dts/exynos5250-snow.dts
@@ -16,12 +16,27 @@
         model = "Google Snow";
         compatible = "google,snow", "samsung,exynos5250";
 
+        pinctrl@11400000 {
+                sd3_clk: sd3-clk {
+                        samsung,pin-drv = <0>;
+                };
+
+                sd3_cmd: sd3-cmd {
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+
+                sd3_bus4: sd3-bus-width4 {
+                        samsung,pin-drv = <0>;
+                };
+        };
+
         gpio-keys {
                 compatible = "gpio-keys";
 
                 lid-switch {
                         label = "Lid";
-                        gpios = <&gpx3 5 0 0x10000 0>;
+                        gpios = <&gpx3 5 1>;
                         linux,input-type = <5>; /* EV_SW */
                         linux,code = <0>; /* SW_LID */
                         debounce-interval = <1>;
@@ -35,9 +50,19 @@
          */
         dwmmc3@12230000 {
                 slot@0 {
-                        gpios = <&gpc4 0 2 0 0>, <&gpc4 1 2 3 0>,
-                                <&gpc4 3 2 3 0>, <&gpc4 4 2 3 0>,
-                                <&gpc4 5 2 3 0>, <&gpc4 6 2 3 0>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_bus4>;
+                };
+        };
+
+        usb@12110000 {
+                samsung,vbus-gpio = <&gpx1 1 1 3 3>;
+        };
+
+        fixed-rate-clocks {
+                xxti {
+                        compatible = "samsung,clock-xxti";
+                        clock-frequency = <24000000>;
                 };
         };
 };
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index b1ac73e21c80..af66e6b7bc77 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -18,6 +18,7 @@
 */
 
 /include/ "skeleton.dtsi"
+/include/ "exynos5250-pinctrl.dtsi"
 
 / {
         compatible = "samsung,exynos5250";
@@ -44,13 +45,45 @@
                 i2c6 = &i2c_6;
                 i2c7 = &i2c_7;
                 i2c8 = &i2c_8;
+                pinctrl0 = &pinctrl_0;
+                pinctrl1 = &pinctrl_1;
+                pinctrl2 = &pinctrl_2;
+                pinctrl3 = &pinctrl_3;
+        };
+
+        pd_gsc: gsc-power-domain@0x10044000 {
+                compatible = "samsung,exynos4210-pd";
+                reg = <0x10044000 0x20>;
+        };
+
+        pd_mfc: mfc-power-domain@0x10044040 {
+                compatible = "samsung,exynos4210-pd";
+                reg = <0x10044040 0x20>;
+        };
+
+        clock: clock-controller@0x10010000 {
+                compatible = "samsung,exynos5250-clock";
+                reg = <0x10010000 0x30000>;
+                #clock-cells = <1>;
         };
 
         gic:interrupt-controller@10481000 {
-                compatible = "arm,cortex-a9-gic";
+                compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
                 #interrupt-cells = <3>;
                 interrupt-controller;
-                reg = <0x10481000 0x1000>, <0x10482000 0x2000>;
+                reg = <0x10481000 0x1000>,
+                      <0x10482000 0x1000>,
+                      <0x10484000 0x2000>,
+                      <0x10486000 0x2000>;
+                interrupts = <1 9 0xf04>;
+        };
+
+        timer {
+                compatible = "arm,armv7-timer";
+                interrupts = <1 13 0xf08>,
+                             <1 14 0xf08>,
+                             <1 11 0xf08>,
+                             <1 10 0xf08>;
         };
 
         combiner:interrupt-controller@10440000 {
@@ -69,58 +102,129 @@
                              <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
         };
 
+        mct@101C0000 {
+                compatible = "samsung,exynos4210-mct";
+                reg = <0x101C0000 0x800>;
+                interrupt-controller;
+                #interrups-cells = <2>;
+                interrupt-parent = <&mct_map>;
+                interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
+                             <4 0>, <5 0>;
+                clocks = <&clock 1>, <&clock 335>;
+                clock-names = "fin_pll", "mct";
+
+                mct_map: mct-map {
+                        #interrupt-cells = <2>;
+                        #address-cells = <0>;
+                        #size-cells = <0>;
+                        interrupt-map = <0x0 0 &combiner 23 3>,
+                                        <0x1 0 &combiner 23 4>,
+                                        <0x2 0 &combiner 25 2>,
+                                        <0x3 0 &combiner 25 3>,
+                                        <0x4 0 &gic 0 120 0>,
+                                        <0x5 0 &gic 0 121 0>;
+                };
+        };
+
+        pinctrl_0: pinctrl@11400000 {
+                compatible = "samsung,exynos5250-pinctrl";
+                reg = <0x11400000 0x1000>;
+                interrupts = <0 46 0>;
+
+                wakup_eint: wakeup-interrupt-controller {
+                        compatible = "samsung,exynos4210-wakeup-eint";
+                        interrupt-parent = <&gic>;
+                        interrupts = <0 32 0>;
+                };
+        };
+
+        pinctrl_1: pinctrl@13400000 {
+                compatible = "samsung,exynos5250-pinctrl";
+                reg = <0x13400000 0x1000>;
+                interrupts = <0 45 0>;
+        };
+
+        pinctrl_2: pinctrl@10d10000 {
+                compatible = "samsung,exynos5250-pinctrl";
+                reg = <0x10d10000 0x1000>;
+                interrupts = <0 50 0>;
+        };
+
+        pinctrl_3: pinctrl@03680000 {
+                compatible = "samsung,exynos5250-pinctrl";
+                reg = <0x0368000 0x1000>;
+                interrupts = <0 47 0>;
+        };
+
         watchdog {
                 compatible = "samsung,s3c2410-wdt";
                 reg = <0x101D0000 0x100>;
                 interrupts = <0 42 0>;
+                clocks = <&clock 336>;
+                clock-names = "watchdog";
         };
 
         codec@11000000 {
                 compatible = "samsung,mfc-v6";
                 reg = <0x11000000 0x10000>;
                 interrupts = <0 96 0>;
+                samsung,power-domain = <&pd_mfc>;
         };
 
         rtc {
                 compatible = "samsung,s3c6410-rtc";
                 reg = <0x101E0000 0x100>;
                 interrupts = <0 43 0>, <0 44 0>;
+                clocks = <&clock 337>;
+                clock-names = "rtc";
         };
 
         tmu@10060000 {
                 compatible = "samsung,exynos5250-tmu";
                 reg = <0x10060000 0x100>;
                 interrupts = <0 65 0>;
+                clocks = <&clock 338>;
+                clock-names = "tmu_apbif";
         };
 
         serial@12C00000 {
                 compatible = "samsung,exynos4210-uart";
                 reg = <0x12C00000 0x100>;
                 interrupts = <0 51 0>;
+                clocks = <&clock 289>, <&clock 146>;
+                clock-names = "uart", "clk_uart_baud0";
         };
 
         serial@12C10000 {
                 compatible = "samsung,exynos4210-uart";
                 reg = <0x12C10000 0x100>;
                 interrupts = <0 52 0>;
+                clocks = <&clock 290>, <&clock 147>;
+                clock-names = "uart", "clk_uart_baud0";
         };
 
         serial@12C20000 {
                 compatible = "samsung,exynos4210-uart";
                 reg = <0x12C20000 0x100>;
                 interrupts = <0 53 0>;
+                clocks = <&clock 291>, <&clock 148>;
+                clock-names = "uart", "clk_uart_baud0";
         };
 
         serial@12C30000 {
                 compatible = "samsung,exynos4210-uart";
                 reg = <0x12C30000 0x100>;
                 interrupts = <0 54 0>;
+                clocks = <&clock 292>, <&clock 149>;
+                clock-names = "uart", "clk_uart_baud0";
         };
 
         sata@122F0000 {
                 compatible = "samsung,exynos5-sata-ahci";
                 reg = <0x122F0000 0x1ff>;
                 interrupts = <0 115 0>;
+                clocks = <&clock 277>, <&clock 143>;
+                clock-names = "sata", "sclk_sata";
         };
 
         sata-phy@12170000 {
@@ -134,6 +238,10 @@
                 interrupts = <0 56 0>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 294>;
+                clock-names = "i2c";
+                pinctrl-names = "default";
+                pinctrl-0 = <&i2c0_bus>;
         };
 
         i2c_1: i2c@12C70000 {
@@ -142,6 +250,10 @@
                 interrupts = <0 57 0>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 295>;
+                clock-names = "i2c";
+                pinctrl-names = "default";
+                pinctrl-0 = <&i2c1_bus>;
         };
 
         i2c_2: i2c@12C80000 {
@@ -150,6 +262,10 @@
                 interrupts = <0 58 0>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 296>;
+                clock-names = "i2c";
+                pinctrl-names = "default";
+                pinctrl-0 = <&i2c2_bus>;
         };
 
         i2c_3: i2c@12C90000 {
@@ -158,6 +274,10 @@
                 interrupts = <0 59 0>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 297>;
+                clock-names = "i2c";
+                pinctrl-names = "default";
+                pinctrl-0 = <&i2c3_bus>;
         };
 
         i2c_4: i2c@12CA0000 {
@@ -166,6 +286,10 @@
                 interrupts = <0 60 0>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 298>;
+                clock-names = "i2c";
+                pinctrl-names = "default";
+                pinctrl-0 = <&i2c4_bus>;
         };
 
         i2c_5: i2c@12CB0000 {
@@ -174,6 +298,10 @@
                 interrupts = <0 61 0>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 299>;
+                clock-names = "i2c";
+                pinctrl-names = "default";
+                pinctrl-0 = <&i2c5_bus>;
         };
 
         i2c_6: i2c@12CC0000 {
@@ -182,6 +310,10 @@
                 interrupts = <0 62 0>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 300>;
+                clock-names = "i2c";
+                pinctrl-names = "default";
+                pinctrl-0 = <&i2c6_bus>;
         };
 
         i2c_7: i2c@12CD0000 {
@@ -190,6 +322,10 @@
                 interrupts = <0 63 0>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 301>;
+                clock-names = "i2c";
+                pinctrl-names = "default";
+                pinctrl-0 = <&i2c7_bus>;
         };
 
         i2c_8: i2c@12CE0000 {
@@ -198,6 +334,8 @@
                 interrupts = <0 64 0>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 302>;
+                clock-names = "i2c";
         };
 
         i2c@121D0000 {
@@ -205,6 +343,8 @@
                 reg = <0x121D0000 0x100>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 288>;
+                clock-names = "i2c";
         };
 
         spi_0: spi@12d20000 {
@@ -216,6 +356,10 @@
                 dma-names = "tx", "rx";
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 304>, <&clock 154>;
+                clock-names = "spi", "spi_busclk0";
+                pinctrl-names = "default";
+                pinctrl-0 = <&spi0_bus>;
         };
 
         spi_1: spi@12d30000 {
@@ -227,6 +371,10 @@
                 dma-names = "tx", "rx";
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 305>, <&clock 155>;
+                clock-names = "spi", "spi_busclk0";
+                pinctrl-names = "default";
+                pinctrl-0 = <&spi1_bus>;
         };
 
         spi_2: spi@12d40000 {
@@ -238,6 +386,10 @@
                 dma-names = "tx", "rx";
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 306>, <&clock 156>;
+                clock-names = "spi", "spi_busclk0";
+                pinctrl-names = "default";
+                pinctrl-0 = <&spi2_bus>;
         };
 
         dwmmc_0: dwmmc0@12200000 {
@@ -246,6 +398,8 @@
                 interrupts = <0 75 0>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 280>, <&clock 139>;
+                clock-names = "biu", "ciu";
         };
 
         dwmmc_1: dwmmc1@12210000 {
@@ -254,6 +408,8 @@
                 interrupts = <0 76 0>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 281>, <&clock 140>;
+                clock-names = "biu", "ciu";
         };
 
         dwmmc_2: dwmmc2@12220000 {
@@ -262,6 +418,8 @@
                 interrupts = <0 77 0>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 282>, <&clock 141>;
+                clock-names = "biu", "ciu";
         };
 
         dwmmc_3: dwmmc3@12230000 {
@@ -270,6 +428,8 @@
                 interrupts = <0 78 0>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 283>, <&clock 142>;
+                clock-names = "biu", "ciu";
         };
 
         i2s0: i2s@03830000 {
@@ -283,6 +443,8 @@
                 samsung,supports-rstclr;
                 samsung,supports-secdai;
                 samsung,idma-addr = <0x03000000>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&i2s0_bus>;
         };
 
         i2s1: i2s@12D60000 {
@@ -291,6 +453,8 @@
                 dmas = <&pdma1 12
                         &pdma1 11>;
                 dma-names = "tx", "rx";
+                pinctrl-names = "default";
+                pinctrl-0 = <&i2s1_bus>;
         };
 
         i2s2: i2s@12D70000 {
@@ -299,6 +463,26 @@
                 dmas = <&pdma0 12
                         &pdma0 11>;
                 dma-names = "tx", "rx";
+                pinctrl-names = "default";
+                pinctrl-0 = <&i2s2_bus>;
+        };
+
+        usb@12110000 {
+                compatible = "samsung,exynos4210-ehci";
+                reg = <0x12110000 0x100>;
+                interrupts = <0 71 0>;
+
+                clocks = <&clock 285>;
+                clock-names = "usbhost";
+        };
+
+        usb@12120000 {
+                compatible = "samsung,exynos4210-ohci";
+                reg = <0x12120000 0x100>;
+                interrupts = <0 71 0>;
+
+                clocks = <&clock 285>;
+                clock-names = "usbhost";
         };
 
         amba {
@@ -312,6 +496,8 @@
                         compatible = "arm,pl330", "arm,primecell";
                         reg = <0x121A0000 0x1000>;
                         interrupts = <0 34 0>;
+                        clocks = <&clock 275>;
+                        clock-names = "apb_pclk";
                         #dma-cells = <1>;
                         #dma-channels = <8>;
                         #dma-requests = <32>;
@@ -321,6 +507,8 @@
                         compatible = "arm,pl330", "arm,primecell";
                         reg = <0x121B0000 0x1000>;
                         interrupts = <0 35 0>;
+                        clocks = <&clock 276>;
+                        clock-names = "apb_pclk";
                         #dma-cells = <1>;
                         #dma-channels = <8>;
                         #dma-requests = <32>;
@@ -330,6 +518,8 @@
                         compatible = "arm,pl330", "arm,primecell";
                         reg = <0x10800000 0x1000>;
                         interrupts = <0 33 0>;
+                        clocks = <&clock 271>;
+                        clock-names = "apb_pclk";
                         #dma-cells = <1>;
                         #dma-channels = <8>;
                         #dma-requests = <1>;
@@ -339,287 +529,58 @@
                         compatible = "arm,pl330", "arm,primecell";
                         reg = <0x11C10000 0x1000>;
                         interrupts = <0 124 0>;
+                        clocks = <&clock 271>;
+                        clock-names = "apb_pclk";
                         #dma-cells = <1>;
                         #dma-channels = <8>;
                         #dma-requests = <1>;
                 };
         };
 
-        gpio-controllers {
-                #address-cells = <1>;
-                #size-cells = <1>;
-                gpio-controller;
-                ranges;
-
-                gpa0: gpio-controller@11400000 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x11400000 0x20>;
-                        #gpio-cells = <4>;
-                };
-
-                gpa1: gpio-controller@11400020 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x11400020 0x20>;
-                        #gpio-cells = <4>;
-                };
-
-                gpa2: gpio-controller@11400040 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x11400040 0x20>;
-                        #gpio-cells = <4>;
-                };
-
-                gpb0: gpio-controller@11400060 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x11400060 0x20>;
-                        #gpio-cells = <4>;
-                };
-
-                gpb1: gpio-controller@11400080 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x11400080 0x20>;
-                        #gpio-cells = <4>;
-                };
-
-                gpb2: gpio-controller@114000A0 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x114000A0 0x20>;
-                        #gpio-cells = <4>;
-                };
-
-                gpb3: gpio-controller@114000C0 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x114000C0 0x20>;
-                        #gpio-cells = <4>;
-                };
-
-                gpc0: gpio-controller@114000E0 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x114000E0 0x20>;
-                        #gpio-cells = <4>;
-                };
-
-                gpc1: gpio-controller@11400100 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x11400100 0x20>;
-                        #gpio-cells = <4>;
-                };
-
-                gpc2: gpio-controller@11400120 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x11400120 0x20>;
-                        #gpio-cells = <4>;
-                };
-
-                gpc3: gpio-controller@11400140 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x11400140 0x20>;
-                        #gpio-cells = <4>;
-                };
-
-                gpc4: gpio-controller@114002E0 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x114002E0 0x20>;
-                        #gpio-cells = <4>;
-                };
-
-                gpd0: gpio-controller@11400160 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x11400160 0x20>;
-                        #gpio-cells = <4>;
-                };
-
-                gpd1: gpio-controller@11400180 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x11400180 0x20>;
-                        #gpio-cells = <4>;
-                };
-
-                gpy0: gpio-controller@114001A0 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x114001A0 0x20>;
-                        #gpio-cells = <4>;
-                };
-
-                gpy1: gpio-controller@114001C0 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x114001C0 0x20>;
-                        #gpio-cells = <4>;
-                };
-
-                gpy2: gpio-controller@114001E0 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x114001E0 0x20>;
-                        #gpio-cells = <4>;
-                };
-
-                gpy3: gpio-controller@11400200 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x11400200 0x20>;
-                        #gpio-cells = <4>;
-                };
-
-                gpy4: gpio-controller@11400220 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x11400220 0x20>;
-                        #gpio-cells = <4>;
-                };
-
-                gpy5: gpio-controller@11400240 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x11400240 0x20>;
-                        #gpio-cells = <4>;
-                };
-
-                gpy6: gpio-controller@11400260 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x11400260 0x20>;
-                        #gpio-cells = <4>;
-                };
-
-                gpx0: gpio-controller@11400C00 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x11400C00 0x20>;
-                        #gpio-cells = <4>;
-                };
-
-                gpx1: gpio-controller@11400C20 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x11400C20 0x20>;
-                        #gpio-cells = <4>;
-                };
-
-                gpx2: gpio-controller@11400C40 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x11400C40 0x20>;
-                        #gpio-cells = <4>;
-                };
-
-                gpx3: gpio-controller@11400C60 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x11400C60 0x20>;
-                        #gpio-cells = <4>;
-                };
-
-                gpe0: gpio-controller@13400000 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x13400000 0x20>;
-                        #gpio-cells = <4>;
-                };
-
-                gpe1: gpio-controller@13400020 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x13400020 0x20>;
-                        #gpio-cells = <4>;
-                };
-
-                gpf0: gpio-controller@13400040 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x13400040 0x20>;
-                        #gpio-cells = <4>;
-                };
-
-                gpf1: gpio-controller@13400060 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x13400060 0x20>;
-                        #gpio-cells = <4>;
-                };
-
-                gpg0: gpio-controller@13400080 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x13400080 0x20>;
-                        #gpio-cells = <4>;
-                };
-
-                gpg1: gpio-controller@134000A0 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x134000A0 0x20>;
-                        #gpio-cells = <4>;
-                };
-
-                gpg2: gpio-controller@134000C0 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x134000C0 0x20>;
-                        #gpio-cells = <4>;
-                };
-
-                gph0: gpio-controller@134000E0 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x134000E0 0x20>;
-                        #gpio-cells = <4>;
-                };
-
-                gph1: gpio-controller@13400100 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x13400100 0x20>;
-                        #gpio-cells = <4>;
-                };
-
-                gpv0: gpio-controller@10D10000 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x10D10000 0x20>;
-                        #gpio-cells = <4>;
-                };
-
-                gpv1: gpio-controller@10D10020 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x10D10020 0x20>;
-                        #gpio-cells = <4>;
-                };
-
-                gpv2: gpio-controller@10D10040 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x10D10060 0x20>;
-                        #gpio-cells = <4>;
-                };
-
-                gpv3: gpio-controller@10D10060 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x10D10080 0x20>;
-                        #gpio-cells = <4>;
-                };
-
-                gpv4: gpio-controller@10D10080 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x10D100C0 0x20>;
-                        #gpio-cells = <4>;
-                };
-
-                gpz: gpio-controller@03860000 {
-                        compatible = "samsung,exynos4-gpio";
-                        reg = <0x03860000 0x20>;
-                        #gpio-cells = <4>;
-                };
-        };
-
         gsc_0:  gsc@0x13e00000 {
                 compatible = "samsung,exynos5-gsc";
                 reg = <0x13e00000 0x1000>;
                 interrupts = <0 85 0>;
+                samsung,power-domain = <&pd_gsc>;
+                clocks = <&clock 256>;
+                clock-names = "gscl";
         };
 
         gsc_1:  gsc@0x13e10000 {
                 compatible = "samsung,exynos5-gsc";
                 reg = <0x13e10000 0x1000>;
                 interrupts = <0 86 0>;
+                samsung,power-domain = <&pd_gsc>;
+                clocks = <&clock 257>;
+                clock-names = "gscl";
         };
 
         gsc_2:  gsc@0x13e20000 {
                 compatible = "samsung,exynos5-gsc";
                 reg = <0x13e20000 0x1000>;
                 interrupts = <0 87 0>;
+                samsung,power-domain = <&pd_gsc>;
+                clocks = <&clock 258>;
+                clock-names = "gscl";
         };
 
         gsc_3:  gsc@0x13e30000 {
                 compatible = "samsung,exynos5-gsc";
                 reg = <0x13e30000 0x1000>;
                 interrupts = <0 88 0>;
+                samsung,power-domain = <&pd_gsc>;
+                clocks = <&clock 259>;
+                clock-names = "gscl";
         };
 
         hdmi {
                 compatible = "samsung,exynos5-hdmi";
                 reg = <0x14530000 0x70000>;
                 interrupts = <0 95 0>;
+                clocks = <&clock 333>, <&clock 136>, <&clock 137>,
+                                <&clock 333>, <&clock 333>;
+                clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
+                                "sclk_hdmiphy", "hdmiphy";
         };
 
         mixer {
@@ -627,4 +588,28 @@
                 reg = <0x14450000 0x10000>;
                 interrupts = <0 94 0>;
         };
+
+        dp-controller {
+                compatible = "samsung,exynos5-dp";
+                reg = <0x145b0000 0x1000>;
+                interrupts = <10 3>;
+                interrupt-parent = <&combiner>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                dptx-phy {
+                        reg = <0x10040720>;
+                        samsung,enable-mask = <1>;
+                };
+        };
+
+        fimd {
+                compatible = "samsung,exynos5250-fimd";
+                interrupt-parent = <&combiner>;
+                reg = <0x14400000 0x40000>;
+                interrupt-names = "fifo", "vsync", "lcd_sys";
+                interrupts = <18 4>, <18 5>, <18 6>;
+                clocks = <&clock 133>, <&clock 339>;
+                clock-names = "sclk_fimd", "fimd";
+        };
 };
diff --git a/arch/arm/boot/dts/exynos5440-sd5v1.dts b/arch/arm/boot/dts/exynos5440-sd5v1.dts
new file mode 100644
index 000000000000..ef747b52b674
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5440-sd5v1.dts
@@ -0,0 +1,39 @@
+/*
+ * SAMSUNG SD5v1 board device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+/include/ "exynos5440.dtsi"
+
+/ {
+        model = "SAMSUNG SD5v1 board based on EXYNOS5440";
+        compatible = "samsung,sd5v1", "samsung,exynos5440";
+
+        chosen {
+                bootargs = "root=/dev/sda2 rw rootwait ignore_loglevel early_printk no_console_suspend mem=2048M@0x80000000 console=ttySAC0,115200";
+        };
+
+        fixed-rate-clocks {
+                xtal {
+                        compatible = "samsung,clock-xtal";
+                        clock-frequency = <50000000>;
+                };
+        };
+
+        gmac: ethernet@00230000 {
+                fixed_phy;
+                phy_addr = <1>;
+        };
+
+        spi {
+                status = "disabled";
+        };
+
+};
diff --git a/arch/arm/boot/dts/exynos5440-ssdk5440.dts b/arch/arm/boot/dts/exynos5440-ssdk5440.dts
index 81e2c964a900..d55042beb5c5 100644
--- a/arch/arm/boot/dts/exynos5440-ssdk5440.dts
+++ b/arch/arm/boot/dts/exynos5440-ssdk5440.dts
@@ -16,31 +16,18 @@
         model = "SAMSUNG SSDK5440 board based on EXYNOS5440";
         compatible = "samsung,ssdk5440", "samsung,exynos5440";
 
-        memory {
-                reg = <0x80000000 0x80000000>;
-        };
-
         chosen {
-                bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x81000000,8M console=ttySAC0,115200 init=/linuxrc";
+                bootargs = "root=/dev/sda2 rw rootwait ignore_loglevel early_printk no_console_suspend mem=2048M@0x80000000 console=ttySAC0,115200";
         };
 
         spi {
                 status = "disabled";
         };
 
-        i2c@F0000 {
-                status = "disabled";
-        };
-
-        i2c@100000 {
-                status = "disabled";
-        };
-
-        watchdog {
-                status = "disabled";
-        };
-
-        rtc {
-                status = "disabled";
+        fixed-rate-clocks {
+                xtal {
+                        compatible = "samsung,clock-xtal";
+                        clock-frequency = <50000000>;
+                };
         };
 };
diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi
index 9a99755920c0..93e9028edaaf 100644
--- a/arch/arm/boot/dts/exynos5440.dtsi
+++ b/arch/arm/boot/dts/exynos5440.dtsi
@@ -16,63 +16,89 @@
 
         interrupt-parent = <&gic>;
 
+        clock: clock-controller@0x160000 {
+                compatible = "samsung,exynos5440-clock";
+                reg = <0x160000 0x1000>;
+                #clock-cells = <1>;
+        };
+
         gic:interrupt-controller@2E0000 {
                 compatible = "arm,cortex-a15-gic";
                 #interrupt-cells = <3>;
                 interrupt-controller;
-                reg = <0x2E1000 0x1000>, <0x2E2000 0x1000>;
+                reg =   <0x2E1000 0x1000>,
+                        <0x2E2000 0x1000>,
+                        <0x2E4000 0x2000>,
+                        <0x2E6000 0x2000>;
+                interrupts = <1 9 0xf04>;
         };
 
         cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
                 cpu@0 {
                         compatible = "arm,cortex-a15";
-                        timer {
-                                compatible = "arm,armv7-timer";
-                                interrupts = <1 13 0xf08>;
-                                clock-frequency = <1000000>;
-                        };
+                        reg = <0>;
                 };
                 cpu@1 {
                         compatible = "arm,cortex-a15";
-                        timer {
-                                compatible = "arm,armv7-timer";
-                                interrupts = <1 14 0xf08>;
-                                clock-frequency = <1000000>;
-                        };
+                        reg = <1>;
                 };
                 cpu@2 {
                         compatible = "arm,cortex-a15";
-                        timer {
-                                compatible = "arm,armv7-timer";
-                                interrupts = <1 14 0xf08>;
-                                clock-frequency = <1000000>;
-                        };
+                        reg = <2>;
                 };
                 cpu@3 {
                         compatible = "arm,cortex-a15";
-                        timer {
-                                compatible = "arm,armv7-timer";
-                                interrupts = <1 14 0xf08>;
-                                clock-frequency = <1000000>;
-                        };
+                        reg = <3>;
                 };
         };
 
-        common {
-                compatible = "samsung,exynos5440";
+        arm-pmu {
+                compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu";
+                interrupts = <0 52 4>,
+                             <0 53 4>,
+                             <0 54 4>,
+                             <0 55 4>;
+        };
+
+        timer {
+                compatible = "arm,cortex-a15-timer",
+                             "arm,armv7-timer";
+                interrupts = <1 13 0xf08>,
+                             <1 14 0xf08>,
+                             <1 11 0xf08>,
+                             <1 10 0xf08>;
+                clock-frequency = <50000000>;
+        };
 
+        cpufreq@160000 {
+                compatible = "samsung,exynos5440-cpufreq";
+                reg = <0x160000 0x1000>;
+                interrupts = <0 57 0>;
+                operating-points = <
+                                /* KHz    uV */
+                                1200000 1025000
+                                1000000 975000
+                                800000  925000
+                >;
         };
 
         serial@B0000 {
                 compatible = "samsung,exynos4210-uart";
                 reg = <0xB0000 0x1000>;
                 interrupts = <0 2 0>;
+                clocks = <&clock 21>, <&clock 21>;
+                clock-names = "uart", "clk_uart_baud0";
         };
 
         serial@C0000 {
                 compatible = "samsung,exynos4210-uart";
                 reg = <0xC0000 0x1000>;
                 interrupts = <0 3 0>;
+                clocks = <&clock 21>, <&clock 21>;
+                clock-names = "uart", "clk_uart_baud0";
         };
 
         spi {
@@ -83,11 +109,15 @@
                 rx-dma-channel = <&pdma0 4>; /* preliminary */
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 21>, <&clock 16>;
+                clock-names = "spi", "spi_busclk0";
         };
 
         pinctrl {
                 compatible = "samsung,exynos5440-pinctrl";
                 reg = <0xE0000 0x1000>;
+                interrupts = <0 37 0>, <0 38 0>, <0 39 0>, <0 40 0>,
+                             <0 41 0>, <0 42 0>, <0 43 0>, <0 44 0>;
                 interrupt-controller;
                 #interrupt-cells = <2>;
                 #gpio-cells = <2>;
@@ -110,25 +140,42 @@
         };
 
         i2c@F0000 {
-                compatible = "samsung,s3c2440-i2c";
+                compatible = "samsung,exynos5440-i2c";
                 reg = <0xF0000 0x1000>;
                 interrupts = <0 5 0>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 21>;
+                clock-names = "i2c";
         };
 
         i2c@100000 {
-                compatible = "samsung,s3c2440-i2c";
+                compatible = "samsung,exynos5440-i2c";
                 reg = <0x100000 0x1000>;
                 interrupts = <0 6 0>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 21>;
+                clock-names = "i2c";
         };
 
         watchdog {
                 compatible = "samsung,s3c2410-wdt";
                 reg = <0x110000 0x1000>;
                 interrupts = <0 1 0>;
+                clocks = <&clock 21>;
+                clock-names = "watchdog";
+        };
+
+        gmac: ethernet@00230000 {
+                compatible = "snps,dwmac-3.70a";
+                reg = <0x00230000 0x8000>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 31 4>;
+                interrupt-names = "macirq";
+                phy-mode = "sgmii";
+                clocks = <&clock 25>;
+                clock-names = "stmmaceth";
         };
 
         amba {
@@ -138,19 +185,23 @@
                 interrupt-parent = <&gic>;
                 ranges;
 
-                pdma0: pdma@121A0000 {
+                pdma0: pdma@00121000 {
                         compatible = "arm,pl330", "arm,primecell";
-                        reg = <0x120000 0x1000>;
-                        interrupts = <0 34 0>;
+                        reg = <0x121000 0x1000>;
+                        interrupts = <0 46 0>;
+                        clocks = <&clock 8>;
+                        clock-names = "apb_pclk";
                         #dma-cells = <1>;
                         #dma-channels = <8>;
                         #dma-requests = <32>;
                 };
 
-                pdma1: pdma@121B0000 {
+                pdma1: pdma@00120000 {
                         compatible = "arm,pl330", "arm,primecell";
-                        reg = <0x121000 0x1000>;
-                        interrupts = <0 35 0>;
+                        reg = <0x120000 0x1000>;
+                        interrupts = <0 47 0>;
+                        clocks = <&clock 8>;
+                        clock-names = "apb_pclk";
                         #dma-cells = <1>;
                         #dma-channels = <8>;
                         #dma-requests = <32>;
@@ -161,5 +212,7 @@
                 compatible = "samsung,s3c6410-rtc";
                 reg = <0x130000 0x1000>;
                 interrupts = <0 17 0>, <0 16 0>;
+                clocks = <&clock 21>;
+                clock-names = "rtc";
         };
 };
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 70f94c87479d..ef3b69a6277c 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -61,6 +61,7 @@ config SOC_EXYNOS5250
         bool "SAMSUNG EXYNOS5250"
         default y
         depends on ARCH_EXYNOS5
+        select PM_GENERIC_DOMAINS if PM
         select S5P_PM if PM
         select S5P_SLEEP if PM
         select S5P_DEV_MFC
@@ -79,12 +80,6 @@ config SOC_EXYNOS5440
         help
           Enable EXYNOS5440 SoC support
 
-config EXYNOS4_MCT
-        bool
-        default y
-        help
-          Use MCT (Multi Core Timer) as kernel timers
-
 config EXYNOS_DEV_DMA
         bool
         help
@@ -276,8 +271,8 @@ config MACH_UNIVERSAL_C210
         select S5P_DEV_ONENAND
         select S5P_DEV_TV
         select S5P_GPIO_INT
-        select S5P_HRT
         select S5P_SETUP_MIPIPHY
+        select SAMSUNG_HRT
         help
           Machine support for Samsung Mobile Universal S5PC210 Reference
           Board.
@@ -406,10 +401,12 @@ config MACH_EXYNOS4_DT
         bool "Samsung Exynos4 Machine using device tree"
         depends on ARCH_EXYNOS4
         select ARM_AMBA
+        select CLKSRC_OF
         select CPU_EXYNOS4210
         select HAVE_SAMSUNG_KEYPAD if INPUT_KEYBOARD
         select PINCTRL
         select PINCTRL_EXYNOS
+        select S5P_DEV_MFC
         select USE_OF
         help
           Machine support for Samsung Exynos4 machine with device tree enabled.
@@ -422,6 +419,7 @@ config MACH_EXYNOS5_DT
         default y
         depends on ARCH_EXYNOS5
         select ARM_AMBA
+        select CLKSRC_OF
         select USE_OF
         help
           Machine support for Samsung EXYNOS5 machine with device tree enabled.
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 435757e57bb4..d2f6b362b6dd 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -13,10 +13,6 @@ obj-				:=
 # Core
 
 obj-$(CONFIG_ARCH_EXYNOS)       += common.o
-obj-$(CONFIG_ARCH_EXYNOS4)      += clock-exynos4.o
-obj-$(CONFIG_CPU_EXYNOS4210)    += clock-exynos4210.o
-obj-$(CONFIG_SOC_EXYNOS4212)    += clock-exynos4212.o
-obj-$(CONFIG_SOC_EXYNOS5250)    += clock-exynos5.o
 
 obj-$(CONFIG_PM)                += pm.o
 obj-$(CONFIG_PM_GENERIC_DOMAINS) += pm_domains.o
@@ -26,8 +22,6 @@ obj-$(CONFIG_ARCH_EXYNOS)	+= pmu.o
 
 obj-$(CONFIG_SMP)               += platsmp.o headsmp.o
 
-obj-$(CONFIG_EXYNOS4_MCT)       += mct.o
-
 obj-$(CONFIG_HOTPLUG_CPU)       += hotplug.o
 
 # machine support
diff --git a/arch/arm/mach-exynos/clock-exynos4.c b/arch/arm/mach-exynos/clock-exynos4.c
deleted file mode 100644
index 8a8468d83c8c..000000000000
--- a/arch/arm/mach-exynos/clock-exynos4.c
+++ /dev/null
@@ -1,1601 +0,0 @@
-/*
- * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * EXYNOS4 - Clock support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/kernel.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/syscore_ops.h>
-
-#include <plat/cpu-freq.h>
-#include <plat/clock.h>
-#include <plat/cpu.h>
-#include <plat/pll.h>
-#include <plat/s5p-clock.h>
-#include <plat/clock-clksrc.h>
-#include <plat/pm.h>
-
-#include <mach/map.h>
-#include <mach/regs-clock.h>
-
-#include "common.h"
-#include "clock-exynos4.h"
-
-#ifdef CONFIG_PM_SLEEP
-static struct sleep_save exynos4_clock_save[] = {
-        SAVE_ITEM(EXYNOS4_CLKDIV_LEFTBUS),
-        SAVE_ITEM(EXYNOS4_CLKGATE_IP_LEFTBUS),
-        SAVE_ITEM(EXYNOS4_CLKDIV_RIGHTBUS),
-        SAVE_ITEM(EXYNOS4_CLKGATE_IP_RIGHTBUS),
-        SAVE_ITEM(EXYNOS4_CLKSRC_TOP0),
-        SAVE_ITEM(EXYNOS4_CLKSRC_TOP1),
-        SAVE_ITEM(EXYNOS4_CLKSRC_CAM),
-        SAVE_ITEM(EXYNOS4_CLKSRC_TV),
-        SAVE_ITEM(EXYNOS4_CLKSRC_MFC),
-        SAVE_ITEM(EXYNOS4_CLKSRC_G3D),
-        SAVE_ITEM(EXYNOS4_CLKSRC_LCD0),
-        SAVE_ITEM(EXYNOS4_CLKSRC_MAUDIO),
-        SAVE_ITEM(EXYNOS4_CLKSRC_FSYS),
-        SAVE_ITEM(EXYNOS4_CLKSRC_PERIL0),
-        SAVE_ITEM(EXYNOS4_CLKSRC_PERIL1),
-        SAVE_ITEM(EXYNOS4_CLKDIV_CAM),
-        SAVE_ITEM(EXYNOS4_CLKDIV_TV),
-        SAVE_ITEM(EXYNOS4_CLKDIV_MFC),
-        SAVE_ITEM(EXYNOS4_CLKDIV_G3D),
-        SAVE_ITEM(EXYNOS4_CLKDIV_LCD0),
-        SAVE_ITEM(EXYNOS4_CLKDIV_MAUDIO),
-        SAVE_ITEM(EXYNOS4_CLKDIV_FSYS0),
-        SAVE_ITEM(EXYNOS4_CLKDIV_FSYS1),
-        SAVE_ITEM(EXYNOS4_CLKDIV_FSYS2),
-        SAVE_ITEM(EXYNOS4_CLKDIV_FSYS3),
-        SAVE_ITEM(EXYNOS4_CLKDIV_PERIL0),
-        SAVE_ITEM(EXYNOS4_CLKDIV_PERIL1),
-        SAVE_ITEM(EXYNOS4_CLKDIV_PERIL2),
-        SAVE_ITEM(EXYNOS4_CLKDIV_PERIL3),
-        SAVE_ITEM(EXYNOS4_CLKDIV_PERIL4),
-        SAVE_ITEM(EXYNOS4_CLKDIV_PERIL5),
-        SAVE_ITEM(EXYNOS4_CLKDIV_TOP),
-        SAVE_ITEM(EXYNOS4_CLKSRC_MASK_TOP),
-        SAVE_ITEM(EXYNOS4_CLKSRC_MASK_CAM),
-        SAVE_ITEM(EXYNOS4_CLKSRC_MASK_TV),
-        SAVE_ITEM(EXYNOS4_CLKSRC_MASK_LCD0),
-        SAVE_ITEM(EXYNOS4_CLKSRC_MASK_MAUDIO),
-        SAVE_ITEM(EXYNOS4_CLKSRC_MASK_FSYS),
-        SAVE_ITEM(EXYNOS4_CLKSRC_MASK_PERIL0),
-        SAVE_ITEM(EXYNOS4_CLKSRC_MASK_PERIL1),
-        SAVE_ITEM(EXYNOS4_CLKDIV2_RATIO),
-        SAVE_ITEM(EXYNOS4_CLKGATE_SCLKCAM),
-        SAVE_ITEM(EXYNOS4_CLKGATE_IP_CAM),
-        SAVE_ITEM(EXYNOS4_CLKGATE_IP_TV),
-        SAVE_ITEM(EXYNOS4_CLKGATE_IP_MFC),
-        SAVE_ITEM(EXYNOS4_CLKGATE_IP_G3D),
-        SAVE_ITEM(EXYNOS4_CLKGATE_IP_LCD0),
-        SAVE_ITEM(EXYNOS4_CLKGATE_IP_FSYS),
-        SAVE_ITEM(EXYNOS4_CLKGATE_IP_GPS),
-        SAVE_ITEM(EXYNOS4_CLKGATE_IP_PERIL),
-        SAVE_ITEM(EXYNOS4_CLKGATE_BLOCK),
-        SAVE_ITEM(EXYNOS4_CLKSRC_MASK_DMC),
-        SAVE_ITEM(EXYNOS4_CLKSRC_DMC),
-        SAVE_ITEM(EXYNOS4_CLKDIV_DMC0),
-        SAVE_ITEM(EXYNOS4_CLKDIV_DMC1),
-        SAVE_ITEM(EXYNOS4_CLKGATE_IP_DMC),
-        SAVE_ITEM(EXYNOS4_CLKSRC_CPU),
-        SAVE_ITEM(EXYNOS4_CLKDIV_CPU),
-        SAVE_ITEM(EXYNOS4_CLKDIV_CPU + 0x4),
-        SAVE_ITEM(EXYNOS4_CLKGATE_SCLKCPU),
-        SAVE_ITEM(EXYNOS4_CLKGATE_IP_CPU),
-};
-#endif
-
-static struct clk exynos4_clk_sclk_hdmi27m = {
-        .name           = "sclk_hdmi27m",
-        .rate           = 27000000,
-};
-
-static struct clk exynos4_clk_sclk_hdmiphy = {
-        .name           = "sclk_hdmiphy",
-};
-
-static struct clk exynos4_clk_sclk_usbphy0 = {
-        .name           = "sclk_usbphy0",
-        .rate           = 27000000,
-};
-
-static struct clk exynos4_clk_sclk_usbphy1 = {
-        .name           = "sclk_usbphy1",
-};
-
-static struct clk dummy_apb_pclk = {
-        .name           = "apb_pclk",
-        .id             = -1,
-};
-
-static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_TOP, clk, enable);
-}
-
-static int exynos4_clksrc_mask_cam_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_CAM, clk, enable);
-}
-
-static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_LCD0, clk, enable);
-}
-
-int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_FSYS, clk, enable);
-}
-
-static int exynos4_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_PERIL0, clk, enable);
-}
-
-static int exynos4_clksrc_mask_peril1_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_PERIL1, clk, enable);
-}
-
-static int exynos4_clk_ip_mfc_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKGATE_IP_MFC, clk, enable);
-}
-
-static int exynos4_clksrc_mask_tv_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_TV, clk, enable);
-}
-
-static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKGATE_IP_CAM, clk, enable);
-}
-
-static int exynos4_clk_ip_tv_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKGATE_IP_TV, clk, enable);
-}
-
-int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKGATE_IP_IMAGE, clk, enable);
-}
-
-static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKGATE_IP_LCD0, clk, enable);
-}
-
-int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4210_CLKGATE_IP_LCD1, clk, enable);
-}
-
-int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKGATE_IP_FSYS, clk, enable);
-}
-
-static int exynos4_clk_ip_peril_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIL, clk, enable);
-}
-
-static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIR, clk, enable);
-}
-
-int exynos4_clk_ip_dmc_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKGATE_IP_DMC, clk, enable);
-}
-
-static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
-}
-
-static int exynos4_clk_dac_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_DAC_PHY_CONTROL, clk, enable);
-}
-
-/* Core list of CMU_CPU side */
-
-static struct clksrc_clk exynos4_clk_mout_apll = {
-        .clk    = {
-                .name           = "mout_apll",
-        },
-        .sources = &clk_src_apll,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 0, .size = 1 },
-};
-
-static struct clksrc_clk exynos4_clk_sclk_apll = {
-        .clk    = {
-                .name           = "sclk_apll",
-                .parent         = &exynos4_clk_mout_apll.clk,
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 24, .size = 3 },
-};
-
-static struct clksrc_clk exynos4_clk_mout_epll = {
-        .clk    = {
-                .name           = "mout_epll",
-        },
-        .sources = &clk_src_epll,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 4, .size = 1 },
-};
-
-struct clksrc_clk exynos4_clk_mout_mpll = {
-        .clk    = {
-                .name           = "mout_mpll",
-        },
-        .sources = &clk_src_mpll,
-
-        /* reg_src will be added in each SoCs' clock */
-};
-
-static struct clk *exynos4_clkset_moutcore_list[] = {
-        [0] = &exynos4_clk_mout_apll.clk,
-        [1] = &exynos4_clk_mout_mpll.clk,
-};
-
-static struct clksrc_sources exynos4_clkset_moutcore = {
-        .sources        = exynos4_clkset_moutcore_list,
-        .nr_sources     = ARRAY_SIZE(exynos4_clkset_moutcore_list),
-};
-
-static struct clksrc_clk exynos4_clk_moutcore = {
-        .clk    = {
-                .name           = "moutcore",
-        },
-        .sources = &exynos4_clkset_moutcore,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 16, .size = 1 },
-};
-
-static struct clksrc_clk exynos4_clk_coreclk = {
-        .clk    = {
-                .name           = "core_clk",
-                .parent         = &exynos4_clk_moutcore.clk,
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 0, .size = 3 },
-};
-
-static struct clksrc_clk exynos4_clk_armclk = {
-        .clk    = {
-                .name           = "armclk",
-                .parent         = &exynos4_clk_coreclk.clk,
-        },
-};
-
-static struct clksrc_clk exynos4_clk_aclk_corem0 = {
-        .clk    = {
-                .name           = "aclk_corem0",
-                .parent         = &exynos4_clk_coreclk.clk,
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 4, .size = 3 },
-};
-
-static struct clksrc_clk exynos4_clk_aclk_cores = {
-        .clk    = {
-                .name           = "aclk_cores",
-                .parent         = &exynos4_clk_coreclk.clk,
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 4, .size = 3 },
-};
-
-static struct clksrc_clk exynos4_clk_aclk_corem1 = {
-        .clk    = {
-                .name           = "aclk_corem1",
-                .parent         = &exynos4_clk_coreclk.clk,
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 8, .size = 3 },
-};
-
-static struct clksrc_clk exynos4_clk_periphclk = {
-        .clk    = {
-                .name           = "periphclk",
-                .parent         = &exynos4_clk_coreclk.clk,
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 12, .size = 3 },
-};
-
-/* Core list of CMU_CORE side */
-
-static struct clk *exynos4_clkset_corebus_list[] = {
-        [0] = &exynos4_clk_mout_mpll.clk,
-        [1] = &exynos4_clk_sclk_apll.clk,
-};
-
-struct clksrc_sources exynos4_clkset_mout_corebus = {
-        .sources        = exynos4_clkset_corebus_list,
-        .nr_sources     = ARRAY_SIZE(exynos4_clkset_corebus_list),
-};
-
-static struct clksrc_clk exynos4_clk_mout_corebus = {
-        .clk    = {
-                .name           = "mout_corebus",
-        },
-        .sources = &exynos4_clkset_mout_corebus,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 4, .size = 1 },
-};
-
-static struct clksrc_clk exynos4_clk_sclk_dmc = {
-        .clk    = {
-                .name           = "sclk_dmc",
-                .parent         = &exynos4_clk_mout_corebus.clk,
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 12, .size = 3 },
-};
-
-static struct clksrc_clk exynos4_clk_aclk_cored = {
-        .clk    = {
-                .name           = "aclk_cored",
-                .parent         = &exynos4_clk_sclk_dmc.clk,
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 16, .size = 3 },
-};
-
-static struct clksrc_clk exynos4_clk_aclk_corep = {
-        .clk    = {
-                .name           = "aclk_corep",
-                .parent         = &exynos4_clk_aclk_cored.clk,
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 20, .size = 3 },
-};
-
-static struct clksrc_clk exynos4_clk_aclk_acp = {
-        .clk    = {
-                .name           = "aclk_acp",
-                .parent         = &exynos4_clk_mout_corebus.clk,
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 0, .size = 3 },
-};
-
-static struct clksrc_clk exynos4_clk_pclk_acp = {
-        .clk    = {
-                .name           = "pclk_acp",
-                .parent         = &exynos4_clk_aclk_acp.clk,
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 4, .size = 3 },
-};
-
-/* Core list of CMU_TOP side */
-
-struct clk *exynos4_clkset_aclk_top_list[] = {
-        [0] = &exynos4_clk_mout_mpll.clk,
-        [1] = &exynos4_clk_sclk_apll.clk,
-};
-
-static struct clksrc_sources exynos4_clkset_aclk = {
-        .sources        = exynos4_clkset_aclk_top_list,
-        .nr_sources     = ARRAY_SIZE(exynos4_clkset_aclk_top_list),
-};
-
-static struct clksrc_clk exynos4_clk_aclk_200 = {
-        .clk    = {
-                .name           = "aclk_200",
-        },
-        .sources = &exynos4_clkset_aclk,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 12, .size = 1 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 0, .size = 3 },
-};
-
-static struct clksrc_clk exynos4_clk_aclk_100 = {
-        .clk    = {
-                .name           = "aclk_100",
-        },
-        .sources = &exynos4_clkset_aclk,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 16, .size = 1 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 4, .size = 4 },
-};
-
-static struct clksrc_clk exynos4_clk_aclk_160 = {
-        .clk    = {
-                .name           = "aclk_160",
-        },
-        .sources = &exynos4_clkset_aclk,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 20, .size = 1 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 8, .size = 3 },
-};
-
-struct clksrc_clk exynos4_clk_aclk_133 = {
-        .clk    = {
-                .name           = "aclk_133",
-        },
-        .sources = &exynos4_clkset_aclk,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 24, .size = 1 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 12, .size = 3 },
-};
-
-static struct clk *exynos4_clkset_vpllsrc_list[] = {
-        [0] = &clk_fin_vpll,
-        [1] = &exynos4_clk_sclk_hdmi27m,
-};
-
-static struct clksrc_sources exynos4_clkset_vpllsrc = {
-        .sources        = exynos4_clkset_vpllsrc_list,
-        .nr_sources     = ARRAY_SIZE(exynos4_clkset_vpllsrc_list),
-};
-
-static struct clksrc_clk exynos4_clk_vpllsrc = {
-        .clk    = {
-                .name           = "vpll_src",
-                .enable         = exynos4_clksrc_mask_top_ctrl,
-                .ctrlbit        = (1 << 0),
-        },
-        .sources = &exynos4_clkset_vpllsrc,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_TOP1, .shift = 0, .size = 1 },
-};
-
-static struct clk *exynos4_clkset_sclk_vpll_list[] = {
-        [0] = &exynos4_clk_vpllsrc.clk,
-        [1] = &clk_fout_vpll,
-};
-
-static struct clksrc_sources exynos4_clkset_sclk_vpll = {
-        .sources        = exynos4_clkset_sclk_vpll_list,
-        .nr_sources     = ARRAY_SIZE(exynos4_clkset_sclk_vpll_list),
-};
-
-static struct clksrc_clk exynos4_clk_sclk_vpll = {
-        .clk    = {
-                .name           = "sclk_vpll",
-        },
-        .sources = &exynos4_clkset_sclk_vpll,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 8, .size = 1 },
-};
-
-static struct clk exynos4_init_clocks_off[] = {
-        {
-                .name           = "timers",
-                .parent         = &exynos4_clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1<<24),
-        }, {
-                .name           = "csis",
-                .devname        = "s5p-mipi-csis.0",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 4),
-        }, {
-                .name           = "csis",
-                .devname        = "s5p-mipi-csis.1",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 5),
-        }, {
-                .name           = "jpeg",
-                .id             = 0,
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 6),
-        }, {
-                .name           = "fimc",
-                .devname        = "exynos4-fimc.0",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "fimc",
-                .devname        = "exynos4-fimc.1",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 1),
-        }, {
-                .name           = "fimc",
-                .devname        = "exynos4-fimc.2",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 2),
-        }, {
-                .name           = "fimc",
-                .devname        = "exynos4-fimc.3",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 3),
-        }, {
-                .name           = "tsi",
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 4),
-        }, {
-                .name           = "hsmmc",
-                .devname        = "exynos4-sdhci.0",
-                .parent         = &exynos4_clk_aclk_133.clk,
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 5),
-        }, {
-                .name           = "hsmmc",
-                .devname        = "exynos4-sdhci.1",
-                .parent         = &exynos4_clk_aclk_133.clk,
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 6),
-        }, {
-                .name           = "hsmmc",
-                .devname        = "exynos4-sdhci.2",
-                .parent         = &exynos4_clk_aclk_133.clk,
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 7),
-        }, {
-                .name           = "hsmmc",
-                .devname        = "exynos4-sdhci.3",
-                .parent         = &exynos4_clk_aclk_133.clk,
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 8),
-        }, {
-                .name           = "biu",
-                .parent         = &exynos4_clk_aclk_133.clk,
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 9),
-        }, {
-                .name           = "onenand",
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 15),
-        }, {
-                .name           = "nfcon",
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 16),
-        }, {
-                .name           = "dac",
-                .devname        = "s5p-sdo",
-                .enable         = exynos4_clk_ip_tv_ctrl,
-                .ctrlbit        = (1 << 2),
-        }, {
-                .name           = "mixer",
-                .devname        = "s5p-mixer",
-                .enable         = exynos4_clk_ip_tv_ctrl,
-                .ctrlbit        = (1 << 1),
-        }, {
-                .name           = "vp",
-                .devname        = "s5p-mixer",
-                .enable         = exynos4_clk_ip_tv_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "hdmi",
-                .devname        = "exynos4-hdmi",
-                .enable         = exynos4_clk_ip_tv_ctrl,
-                .ctrlbit        = (1 << 3),
-        }, {
-                .name           = "hdmiphy",
-                .devname        = "exynos4-hdmi",
-                .enable         = exynos4_clk_hdmiphy_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "dacphy",
-                .devname        = "s5p-sdo",
-                .enable         = exynos4_clk_dac_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "adc",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 15),
-        }, {
-                .name           = "tmu_apbif",
-                .enable         = exynos4_clk_ip_perir_ctrl,
-                .ctrlbit        = (1 << 17),
-        }, {
-                .name           = "keypad",
-                .enable         = exynos4_clk_ip_perir_ctrl,
-                .ctrlbit        = (1 << 16),
-        }, {
-                .name           = "rtc",
-                .enable         = exynos4_clk_ip_perir_ctrl,
-                .ctrlbit        = (1 << 15),
-        }, {
-                .name           = "watchdog",
-                .parent         = &exynos4_clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_perir_ctrl,
-                .ctrlbit        = (1 << 14),
-        }, {
-                .name           = "usbhost",
-                .enable         = exynos4_clk_ip_fsys_ctrl ,
-                .ctrlbit        = (1 << 12),
-        }, {
-                .name           = "otg",
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 13),
-        }, {
-                .name           = "spi",
-                .devname        = "exynos4210-spi.0",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 16),
-        }, {
-                .name           = "spi",
-                .devname        = "exynos4210-spi.1",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 17),
-        }, {
-                .name           = "spi",
-                .devname        = "exynos4210-spi.2",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 18),
-        }, {
-                .name           = "iis",
-                .devname        = "samsung-i2s.1",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 20),
-        }, {
-                .name           = "iis",
-                .devname        = "samsung-i2s.2",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 21),
-        }, {
-                .name           = "pcm",
-                .devname        = "samsung-pcm.1",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 22),
-        }, {
-                .name           = "pcm",
-                .devname        = "samsung-pcm.2",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 23),
-        }, {
-                .name           = "slimbus",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 25),
-        }, {
-                .name           = "spdif",
-                .devname        = "samsung-spdif",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 26),
-        }, {
-                .name           = "ac97",
-                .devname        = "samsung-ac97",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 27),
-        }, {
-                .name           = "mfc",
-                .devname        = "s5p-mfc",
-                .enable         = exynos4_clk_ip_mfc_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.0",
-                .parent         = &exynos4_clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 6),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.1",
-                .parent         = &exynos4_clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 7),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.2",
-                .parent         = &exynos4_clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 8),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.3",
-                .parent         = &exynos4_clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 9),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.4",
-                .parent         = &exynos4_clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 10),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.5",
-                .parent         = &exynos4_clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 11),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.6",
-                .parent         = &exynos4_clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 12),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.7",
-                .parent         = &exynos4_clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 13),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-hdmiphy-i2c",
-                .parent         = &exynos4_clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 14),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.0",
-                .enable         = exynos4_clk_ip_mfc_ctrl,
-                .ctrlbit        = (1 << 1),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.1",
-                .enable         = exynos4_clk_ip_mfc_ctrl,
-                .ctrlbit        = (1 << 2),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.2",
-                .enable         = exynos4_clk_ip_tv_ctrl,
-                .ctrlbit        = (1 << 4),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.3",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 11),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.4",
-                .enable         = exynos4_clk_ip_image_ctrl,
-                .ctrlbit        = (1 << 4),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.5",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 7),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.6",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 8),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.7",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 9),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.8",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 10),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.10",
-                .enable         = exynos4_clk_ip_lcd0_ctrl,
-                .ctrlbit        = (1 << 4),
-        }
-};
-
-static struct clk exynos4_init_clocks_on[] = {
-        {
-                .name           = "uart",
-                .devname        = "s5pv210-uart.0",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "uart",
-                .devname        = "s5pv210-uart.1",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 1),
-        }, {
-                .name           = "uart",
-                .devname        = "s5pv210-uart.2",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 2),
-        }, {
-                .name           = "uart",
-                .devname        = "s5pv210-uart.3",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 3),
-        }, {
-                .name           = "uart",
-                .devname        = "s5pv210-uart.4",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 4),
-        }, {
-                .name           = "uart",
-                .devname        = "s5pv210-uart.5",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 5),
-        }
-};
-
-static struct clk exynos4_clk_pdma0 = {
-        .name           = "dma",
-        .devname        = "dma-pl330.0",
-        .enable         = exynos4_clk_ip_fsys_ctrl,
-        .ctrlbit        = (1 << 0),
-};
-
-static struct clk exynos4_clk_pdma1 = {
-        .name           = "dma",
-        .devname        = "dma-pl330.1",
-        .enable         = exynos4_clk_ip_fsys_ctrl,
-        .ctrlbit        = (1 << 1),
-};
-
-static struct clk exynos4_clk_mdma1 = {
-        .name           = "dma",
-        .devname        = "dma-pl330.2",
-        .enable         = exynos4_clk_ip_image_ctrl,
-        .ctrlbit        = ((1 << 8) | (1 << 5) | (1 << 2)),
-};
-
-static struct clk exynos4_clk_fimd0 = {
-        .name           = "fimd",
-        .devname        = "exynos4-fb.0",
-        .enable         = exynos4_clk_ip_lcd0_ctrl,
-        .ctrlbit        = (1 << 0),
-};
-
-struct clk *exynos4_clkset_group_list[] = {
-        [0] = &clk_ext_xtal_mux,
-        [1] = &clk_xusbxti,
-        [2] = &exynos4_clk_sclk_hdmi27m,
-        [3] = &exynos4_clk_sclk_usbphy0,
-        [4] = &exynos4_clk_sclk_usbphy1,
-        [5] = &exynos4_clk_sclk_hdmiphy,
-        [6] = &exynos4_clk_mout_mpll.clk,
-        [7] = &exynos4_clk_mout_epll.clk,
-        [8] = &exynos4_clk_sclk_vpll.clk,
-};
-
-struct clksrc_sources exynos4_clkset_group = {
-        .sources        = exynos4_clkset_group_list,
-        .nr_sources     = ARRAY_SIZE(exynos4_clkset_group_list),
-};
-
-static struct clk *exynos4_clkset_mout_g2d0_list[] = {
-        [0] = &exynos4_clk_mout_mpll.clk,
-        [1] = &exynos4_clk_sclk_apll.clk,
-};
-
-struct clksrc_sources exynos4_clkset_mout_g2d0 = {
-        .sources        = exynos4_clkset_mout_g2d0_list,
-        .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_g2d0_list),
-};
-
-static struct clk *exynos4_clkset_mout_g2d1_list[] = {
-        [0] = &exynos4_clk_mout_epll.clk,
-        [1] = &exynos4_clk_sclk_vpll.clk,
-};
-
-struct clksrc_sources exynos4_clkset_mout_g2d1 = {
-        .sources        = exynos4_clkset_mout_g2d1_list,
-        .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_g2d1_list),
-};
-
-static struct clk *exynos4_clkset_mout_mfc0_list[] = {
-        [0] = &exynos4_clk_mout_mpll.clk,
-        [1] = &exynos4_clk_sclk_apll.clk,
-};
-
-static struct clksrc_sources exynos4_clkset_mout_mfc0 = {
-        .sources        = exynos4_clkset_mout_mfc0_list,
-        .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_mfc0_list),
-};
-
-static struct clksrc_clk exynos4_clk_mout_mfc0 = {
-        .clk    = {
-                .name           = "mout_mfc0",
-        },
-        .sources = &exynos4_clkset_mout_mfc0,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 0, .size = 1 },
-};
-
-static struct clk *exynos4_clkset_mout_mfc1_list[] = {
-        [0] = &exynos4_clk_mout_epll.clk,
-        [1] = &exynos4_clk_sclk_vpll.clk,
-};
-
-static struct clksrc_sources exynos4_clkset_mout_mfc1 = {
-        .sources        = exynos4_clkset_mout_mfc1_list,
-        .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_mfc1_list),
-};
-
-static struct clksrc_clk exynos4_clk_mout_mfc1 = {
-        .clk    = {
-                .name           = "mout_mfc1",
-        },
-        .sources = &exynos4_clkset_mout_mfc1,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 4, .size = 1 },
-};
-
-static struct clk *exynos4_clkset_mout_mfc_list[] = {
-        [0] = &exynos4_clk_mout_mfc0.clk,
-        [1] = &exynos4_clk_mout_mfc1.clk,
-};
-
-static struct clksrc_sources exynos4_clkset_mout_mfc = {
-        .sources        = exynos4_clkset_mout_mfc_list,
-        .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_mfc_list),
-};
-
-static struct clk *exynos4_clkset_sclk_dac_list[] = {
-        [0] = &exynos4_clk_sclk_vpll.clk,
-        [1] = &exynos4_clk_sclk_hdmiphy,
-};
-
-static struct clksrc_sources exynos4_clkset_sclk_dac = {
-        .sources        = exynos4_clkset_sclk_dac_list,
-        .nr_sources     = ARRAY_SIZE(exynos4_clkset_sclk_dac_list),
-};
-
-static struct clksrc_clk exynos4_clk_sclk_dac = {
-        .clk            = {
-                .name           = "sclk_dac",
-                .enable         = exynos4_clksrc_mask_tv_ctrl,
-                .ctrlbit        = (1 << 8),
-        },
-        .sources = &exynos4_clkset_sclk_dac,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 8, .size = 1 },
-};
-
-static struct clksrc_clk exynos4_clk_sclk_pixel = {
-        .clk            = {
-                .name           = "sclk_pixel",
-                .parent         = &exynos4_clk_sclk_vpll.clk,
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_TV, .shift = 0, .size = 4 },
-};
-
-static struct clk *exynos4_clkset_sclk_hdmi_list[] = {
-        [0] = &exynos4_clk_sclk_pixel.clk,
-        [1] = &exynos4_clk_sclk_hdmiphy,
-};
-
-static struct clksrc_sources exynos4_clkset_sclk_hdmi = {
-        .sources        = exynos4_clkset_sclk_hdmi_list,
-        .nr_sources     = ARRAY_SIZE(exynos4_clkset_sclk_hdmi_list),
-};
-
-static struct clksrc_clk exynos4_clk_sclk_hdmi = {
-        .clk            = {
-                .name           = "sclk_hdmi",
-                .enable         = exynos4_clksrc_mask_tv_ctrl,
-                .ctrlbit        = (1 << 0),
-        },
-        .sources = &exynos4_clkset_sclk_hdmi,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 0, .size = 1 },
-};
-
-static struct clk *exynos4_clkset_sclk_mixer_list[] = {
-        [0] = &exynos4_clk_sclk_dac.clk,
-        [1] = &exynos4_clk_sclk_hdmi.clk,
-};
-
-static struct clksrc_sources exynos4_clkset_sclk_mixer = {
-        .sources        = exynos4_clkset_sclk_mixer_list,
-        .nr_sources     = ARRAY_SIZE(exynos4_clkset_sclk_mixer_list),
-};
-
-static struct clksrc_clk exynos4_clk_sclk_mixer = {
-        .clk    = {
-                .name           = "sclk_mixer",
-                .enable         = exynos4_clksrc_mask_tv_ctrl,
-                .ctrlbit        = (1 << 4),
-        },
-        .sources = &exynos4_clkset_sclk_mixer,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 4, .size = 1 },
-};
-
-static struct clksrc_clk *exynos4_sclk_tv[] = {
-        &exynos4_clk_sclk_dac,
-        &exynos4_clk_sclk_pixel,
-        &exynos4_clk_sclk_hdmi,
-        &exynos4_clk_sclk_mixer,
-};
-
-static struct clksrc_clk exynos4_clk_dout_mmc0 = {
-        .clk    = {
-                .name           = "dout_mmc0",
-        },
-        .sources = &exynos4_clkset_group,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 0, .size = 4 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk exynos4_clk_dout_mmc1 = {
-        .clk    = {
-                .name           = "dout_mmc1",
-        },
-        .sources = &exynos4_clkset_group,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 4, .size = 4 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 16, .size = 4 },
-};
-
-static struct clksrc_clk exynos4_clk_dout_mmc2 = {
-        .clk    = {
-                .name           = "dout_mmc2",
-        },
-        .sources = &exynos4_clkset_group,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 8, .size = 4 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk exynos4_clk_dout_mmc3 = {
-        .clk    = {
-                .name           = "dout_mmc3",
-        },
-        .sources = &exynos4_clkset_group,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 12, .size = 4 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 16, .size = 4 },
-};
-
-static struct clksrc_clk exynos4_clk_dout_mmc4 = {
-        .clk            = {
-                .name           = "dout_mmc4",
-        },
-        .sources = &exynos4_clkset_group,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 16, .size = 4 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS3, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk exynos4_clksrcs[] = {
-        {
-                .clk    = {
-                        .name           = "sclk_pwm",
-                        .enable         = exynos4_clksrc_mask_peril0_ctrl,
-                        .ctrlbit        = (1 << 24),
-                },
-                .sources = &exynos4_clkset_group,
-                .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 24, .size = 4 },
-                .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL3, .shift = 0, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_csis",
-                        .devname        = "s5p-mipi-csis.0",
-                        .enable         = exynos4_clksrc_mask_cam_ctrl,
-                        .ctrlbit        = (1 << 24),
-                },
-                .sources = &exynos4_clkset_group,
-                .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 24, .size = 4 },
-                .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 24, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_csis",
-                        .devname        = "s5p-mipi-csis.1",
-                        .enable         = exynos4_clksrc_mask_cam_ctrl,
-                        .ctrlbit        = (1 << 28),
-                },
-                .sources = &exynos4_clkset_group,
-                .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 28, .size = 4 },
-                .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 28, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_cam0",
-                        .enable         = exynos4_clksrc_mask_cam_ctrl,
-                        .ctrlbit        = (1 << 16),
-                },
-                .sources = &exynos4_clkset_group,
-                .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 16, .size = 4 },
-                .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 16, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_cam1",
-                        .enable         = exynos4_clksrc_mask_cam_ctrl,
-                        .ctrlbit        = (1 << 20),
-                },
-                .sources = &exynos4_clkset_group,
-                .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 20, .size = 4 },
-                .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 20, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_fimc",
-                        .devname        = "exynos4-fimc.0",
-                        .enable         = exynos4_clksrc_mask_cam_ctrl,
-                        .ctrlbit        = (1 << 0),
-                },
-                .sources = &exynos4_clkset_group,
-                .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 0, .size = 4 },
-                .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 0, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_fimc",
-                        .devname        = "exynos4-fimc.1",
-                        .enable         = exynos4_clksrc_mask_cam_ctrl,
-                        .ctrlbit        = (1 << 4),
-                },
-                .sources = &exynos4_clkset_group,
-                .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 4, .size = 4 },
-                .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 4, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_fimc",
-                        .devname        = "exynos4-fimc.2",
-                        .enable         = exynos4_clksrc_mask_cam_ctrl,
-                        .ctrlbit        = (1 << 8),
-                },
-                .sources = &exynos4_clkset_group,
-                .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 8, .size = 4 },
-                .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 8, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_fimc",
-                        .devname        = "exynos4-fimc.3",
-                        .enable         = exynos4_clksrc_mask_cam_ctrl,
-                        .ctrlbit        = (1 << 12),
-                },
-                .sources = &exynos4_clkset_group,
-                .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 12, .size = 4 },
-                .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 12, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_fimd",
-                        .devname        = "exynos4-fb.0",
-                        .enable         = exynos4_clksrc_mask_lcd0_ctrl,
-                        .ctrlbit        = (1 << 0),
-                },
-                .sources = &exynos4_clkset_group,
-                .reg_src = { .reg = EXYNOS4_CLKSRC_LCD0, .shift = 0, .size = 4 },
-                .reg_div = { .reg = EXYNOS4_CLKDIV_LCD0, .shift = 0, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_mfc",
-                        .devname        = "s5p-mfc",
-                },
-                .sources = &exynos4_clkset_mout_mfc,
-                .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 8, .size = 1 },
-                .reg_div = { .reg = EXYNOS4_CLKDIV_MFC, .shift = 0, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "ciu",
-                        .parent         = &exynos4_clk_dout_mmc4.clk,
-                        .enable         = exynos4_clksrc_mask_fsys_ctrl,
-                        .ctrlbit        = (1 << 16),
-                },
-                .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS3, .shift = 8, .size = 8 },
-        }
-};
-
-static struct clksrc_clk exynos4_clk_sclk_uart0 = {
-        .clk    = {
-                .name           = "uclk1",
-                .devname        = "exynos4210-uart.0",
-                .enable         = exynos4_clksrc_mask_peril0_ctrl,
-                .ctrlbit        = (1 << 0),
-        },
-        .sources = &exynos4_clkset_group,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 0, .size = 4 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk exynos4_clk_sclk_uart1 = {
-        .clk    = {
-                .name           = "uclk1",
-                .devname        = "exynos4210-uart.1",
-                .enable         = exynos4_clksrc_mask_peril0_ctrl,
-                .ctrlbit        = (1 << 4),
-        },
-        .sources = &exynos4_clkset_group,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 4, .size = 4 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 4, .size = 4 },
-};
-
-static struct clksrc_clk exynos4_clk_sclk_uart2 = {
-        .clk    = {
-                .name           = "uclk1",
-                .devname        = "exynos4210-uart.2",
-                .enable         = exynos4_clksrc_mask_peril0_ctrl,
-                .ctrlbit        = (1 << 8),
-        },
-        .sources = &exynos4_clkset_group,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 8, .size = 4 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 8, .size = 4 },
-};
-
-static struct clksrc_clk exynos4_clk_sclk_uart3 = {
-        .clk    = {
-                .name           = "uclk1",
-                .devname        = "exynos4210-uart.3",
-                .enable         = exynos4_clksrc_mask_peril0_ctrl,
-                .ctrlbit        = (1 << 12),
-        },
-        .sources = &exynos4_clkset_group,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 12, .size = 4 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 12, .size = 4 },
-};
-
-static struct clksrc_clk exynos4_clk_sclk_mmc0 = {
-        .clk    = {
-                .name           = "sclk_mmc",
-                .devname        = "exynos4-sdhci.0",
-                .parent         = &exynos4_clk_dout_mmc0.clk,
-                .enable         = exynos4_clksrc_mask_fsys_ctrl,
-                .ctrlbit        = (1 << 0),
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 8, .size = 8 },
-};
-
-static struct clksrc_clk exynos4_clk_sclk_mmc1 = {
-        .clk    = {
-                .name           = "sclk_mmc",
-                .devname        = "exynos4-sdhci.1",
-                .parent         = &exynos4_clk_dout_mmc1.clk,
-                .enable         = exynos4_clksrc_mask_fsys_ctrl,
-                .ctrlbit        = (1 << 4),
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 24, .size = 8 },
-};
-
-static struct clksrc_clk exynos4_clk_sclk_mmc2 = {
-        .clk    = {
-                .name           = "sclk_mmc",
-                .devname        = "exynos4-sdhci.2",
-                .parent         = &exynos4_clk_dout_mmc2.clk,
-                .enable         = exynos4_clksrc_mask_fsys_ctrl,
-                .ctrlbit        = (1 << 8),
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 8, .size = 8 },
-};
-
-static struct clksrc_clk exynos4_clk_sclk_mmc3 = {
-        .clk    = {
-                .name           = "sclk_mmc",
-                .devname        = "exynos4-sdhci.3",
-                .parent         = &exynos4_clk_dout_mmc3.clk,
-                .enable         = exynos4_clksrc_mask_fsys_ctrl,
-                .ctrlbit        = (1 << 12),
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 24, .size = 8 },
-};
-
-static struct clksrc_clk exynos4_clk_mdout_spi0 = {
-        .clk    = {
-                .name           = "mdout_spi",
-                .devname        = "exynos4210-spi.0",
-        },
-        .sources = &exynos4_clkset_group,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 16, .size = 4 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk exynos4_clk_mdout_spi1 = {
-        .clk    = {
-                .name           = "mdout_spi",
-                .devname        = "exynos4210-spi.1",
-        },
-        .sources = &exynos4_clkset_group,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 20, .size = 4 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 16, .size = 4 },
-};
-
-static struct clksrc_clk exynos4_clk_mdout_spi2 = {
-        .clk    = {
-                .name           = "mdout_spi",
-                .devname        = "exynos4210-spi.2",
-        },
-        .sources = &exynos4_clkset_group,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 24, .size = 4 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk exynos4_clk_sclk_spi0 = {
-        .clk    = {
-                .name           = "sclk_spi",
-                .devname        = "exynos4210-spi.0",
-                .parent         = &exynos4_clk_mdout_spi0.clk,
-                .enable         = exynos4_clksrc_mask_peril1_ctrl,
-                .ctrlbit        = (1 << 16),
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 8, .size = 8 },
-};
-
-static struct clksrc_clk exynos4_clk_sclk_spi1 = {
-        .clk    = {
-                .name           = "sclk_spi",
-                .devname        = "exynos4210-spi.1",
-                .parent         = &exynos4_clk_mdout_spi1.clk,
-                .enable         = exynos4_clksrc_mask_peril1_ctrl,
-                .ctrlbit        = (1 << 20),
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 24, .size = 8 },
-};
-
-static struct clksrc_clk exynos4_clk_sclk_spi2 = {
-        .clk    = {
-                .name           = "sclk_spi",
-                .devname        = "exynos4210-spi.2",
-                .parent         = &exynos4_clk_mdout_spi2.clk,
-                .enable         = exynos4_clksrc_mask_peril1_ctrl,
-                .ctrlbit        = (1 << 24),
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 8, .size = 8 },
-};
-
-/* Clock initialization code */
-static struct clksrc_clk *exynos4_sysclks[] = {
-        &exynos4_clk_mout_apll,
-        &exynos4_clk_sclk_apll,
-        &exynos4_clk_mout_epll,
-        &exynos4_clk_mout_mpll,
-        &exynos4_clk_moutcore,
-        &exynos4_clk_coreclk,
-        &exynos4_clk_armclk,
-        &exynos4_clk_aclk_corem0,
-        &exynos4_clk_aclk_cores,
-        &exynos4_clk_aclk_corem1,
-        &exynos4_clk_periphclk,
-        &exynos4_clk_mout_corebus,
-        &exynos4_clk_sclk_dmc,
-        &exynos4_clk_aclk_cored,
-        &exynos4_clk_aclk_corep,
-        &exynos4_clk_aclk_acp,
-        &exynos4_clk_pclk_acp,
-        &exynos4_clk_vpllsrc,
-        &exynos4_clk_sclk_vpll,
-        &exynos4_clk_aclk_200,
-        &exynos4_clk_aclk_100,
-        &exynos4_clk_aclk_160,
-        &exynos4_clk_aclk_133,
-        &exynos4_clk_dout_mmc0,
-        &exynos4_clk_dout_mmc1,
-        &exynos4_clk_dout_mmc2,
-        &exynos4_clk_dout_mmc3,
-        &exynos4_clk_dout_mmc4,
-        &exynos4_clk_mout_mfc0,
-        &exynos4_clk_mout_mfc1,
-};
-
-static struct clk *exynos4_clk_cdev[] = {
-        &exynos4_clk_pdma0,
-        &exynos4_clk_pdma1,
-        &exynos4_clk_mdma1,
-        &exynos4_clk_fimd0,
-};
-
-static struct clksrc_clk *exynos4_clksrc_cdev[] = {
-        &exynos4_clk_sclk_uart0,
-        &exynos4_clk_sclk_uart1,
-        &exynos4_clk_sclk_uart2,
-        &exynos4_clk_sclk_uart3,
-        &exynos4_clk_sclk_mmc0,
-        &exynos4_clk_sclk_mmc1,
-        &exynos4_clk_sclk_mmc2,
-        &exynos4_clk_sclk_mmc3,
-        &exynos4_clk_sclk_spi0,
-        &exynos4_clk_sclk_spi1,
-        &exynos4_clk_sclk_spi2,
-        &exynos4_clk_mdout_spi0,
-        &exynos4_clk_mdout_spi1,
-        &exynos4_clk_mdout_spi2,
-};
-
-static struct clk_lookup exynos4_clk_lookup[] = {
-        CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &exynos4_clk_sclk_uart0.clk),
-        CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos4_clk_sclk_uart1.clk),
-        CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos4_clk_sclk_uart2.clk),
-        CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos4_clk_sclk_uart3.clk),
-        CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos4_clk_sclk_mmc0.clk),
-        CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1.clk),
-        CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2.clk),
-        CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk),
-        CLKDEV_INIT("exynos4-fb.0", "lcd", &exynos4_clk_fimd0),
-        CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0),
-        CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1),
-        CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos4_clk_mdma1),
-        CLKDEV_INIT("exynos4210-spi.0", "spi_busclk0", &exynos4_clk_sclk_spi0.clk),
-        CLKDEV_INIT("exynos4210-spi.1", "spi_busclk0", &exynos4_clk_sclk_spi1.clk),
-        CLKDEV_INIT("exynos4210-spi.2", "spi_busclk0", &exynos4_clk_sclk_spi2.clk),
-};
-
-static int xtal_rate;
-
-static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
-{
-        if (soc_is_exynos4210())
-                return s5p_get_pll45xx(xtal_rate, __raw_readl(EXYNOS4_APLL_CON0),
-                                        pll_4508);
-        else if (soc_is_exynos4212() || soc_is_exynos4412())
-                return s5p_get_pll35xx(xtal_rate, __raw_readl(EXYNOS4_APLL_CON0));
-        else
-                return 0;
-}
-
-static struct clk_ops exynos4_fout_apll_ops = {
-        .get_rate = exynos4_fout_apll_get_rate,
-};
-
-static u32 exynos4_vpll_div[][8] = {
-        {  54000000, 3, 53, 3, 1024, 0, 17, 0 },
-        { 108000000, 3, 53, 2, 1024, 0, 17, 0 },
-};
-
-static unsigned long exynos4_vpll_get_rate(struct clk *clk)
-{
-        return clk->rate;
-}
-
-static int exynos4_vpll_set_rate(struct clk *clk, unsigned long rate)
-{
-        unsigned int vpll_con0, vpll_con1 = 0;
-        unsigned int i;
-
-        /* Return if nothing changed */
-        if (clk->rate == rate)
-                return 0;
-
-        vpll_con0 = __raw_readl(EXYNOS4_VPLL_CON0);
-        vpll_con0 &= ~(0x1 << 27 |                                      \
-                        PLL90XX_MDIV_MASK << PLL46XX_MDIV_SHIFT |       \
-                        PLL90XX_PDIV_MASK << PLL46XX_PDIV_SHIFT |       \
-                        PLL90XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
-
-        vpll_con1 = __raw_readl(EXYNOS4_VPLL_CON1);
-        vpll_con1 &= ~(PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT |  \
-                        PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT | \
-                        PLL4650C_KDIV_MASK << PLL46XX_KDIV_SHIFT);
-
-        for (i = 0; i < ARRAY_SIZE(exynos4_vpll_div); i++) {
-                if (exynos4_vpll_div[i][0] == rate) {
-                        vpll_con0 |= exynos4_vpll_div[i][1] << PLL46XX_PDIV_SHIFT;
-                        vpll_con0 |= exynos4_vpll_div[i][2] << PLL46XX_MDIV_SHIFT;
-                        vpll_con0 |= exynos4_vpll_div[i][3] << PLL46XX_SDIV_SHIFT;
-                        vpll_con1 |= exynos4_vpll_div[i][4] << PLL46XX_KDIV_SHIFT;
-                        vpll_con1 |= exynos4_vpll_div[i][5] << PLL46XX_MFR_SHIFT;
-                        vpll_con1 |= exynos4_vpll_div[i][6] << PLL46XX_MRR_SHIFT;
-                        vpll_con0 |= exynos4_vpll_div[i][7] << 27;
-                        break;
-                }
-        }
-
-        if (i == ARRAY_SIZE(exynos4_vpll_div)) {
-                printk(KERN_ERR "%s: Invalid Clock VPLL Frequency\n",
-                                __func__);
-                return -EINVAL;
-        }
-
-        __raw_writel(vpll_con0, EXYNOS4_VPLL_CON0);
-        __raw_writel(vpll_con1, EXYNOS4_VPLL_CON1);
-
-        /* Wait for VPLL lock */
-        while (!(__raw_readl(EXYNOS4_VPLL_CON0) & (1 << PLL46XX_LOCKED_SHIFT)))
-                continue;
-
-        clk->rate = rate;
-        return 0;
-}
-
-static struct clk_ops exynos4_vpll_ops = {
-        .get_rate = exynos4_vpll_get_rate,
-        .set_rate = exynos4_vpll_set_rate,
-};
-
-void __init_or_cpufreq exynos4_setup_clocks(void)
-{
-        struct clk *xtal_clk;
-        unsigned long apll = 0;
-        unsigned long mpll = 0;
-        unsigned long epll = 0;
-        unsigned long vpll = 0;
-        unsigned long vpllsrc;
-        unsigned long xtal;
-        unsigned long armclk;
-        unsigned long sclk_dmc;
-        unsigned long aclk_200;
-        unsigned long aclk_100;
-        unsigned long aclk_160;
-        unsigned long aclk_133;
-        unsigned int ptr;
-
-        printk(KERN_DEBUG "%s: registering clocks\n", __func__);
-
-        xtal_clk = clk_get(NULL, "xtal");
-        BUG_ON(IS_ERR(xtal_clk));
-
-        xtal = clk_get_rate(xtal_clk);
-
-        xtal_rate = xtal;
-
-        clk_put(xtal_clk);
-
-        printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
-
-        if (soc_is_exynos4210()) {
-                apll = s5p_get_pll45xx(xtal, __raw_readl(EXYNOS4_APLL_CON0),
-                                        pll_4508);
-                mpll = s5p_get_pll45xx(xtal, __raw_readl(EXYNOS4_MPLL_CON0),
-                                        pll_4508);
-                epll = s5p_get_pll46xx(xtal, __raw_readl(EXYNOS4_EPLL_CON0),
-                                        __raw_readl(EXYNOS4_EPLL_CON1), pll_4600);
-
-                vpllsrc = clk_get_rate(&exynos4_clk_vpllsrc.clk);
-                vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(EXYNOS4_VPLL_CON0),
-                                        __raw_readl(EXYNOS4_VPLL_CON1), pll_4650c);
-        } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
-                apll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS4_APLL_CON0));
-                mpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS4_MPLL_CON0));
-                epll = s5p_get_pll36xx(xtal, __raw_readl(EXYNOS4_EPLL_CON0),
-                                        __raw_readl(EXYNOS4_EPLL_CON1));
-
-                vpllsrc = clk_get_rate(&exynos4_clk_vpllsrc.clk);
-                vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(EXYNOS4_VPLL_CON0),
-                                        __raw_readl(EXYNOS4_VPLL_CON1));
-        } else {
-                /* nothing */
-        }
-
-        clk_fout_apll.ops = &exynos4_fout_apll_ops;
-        clk_fout_mpll.rate = mpll;
-        clk_fout_epll.rate = epll;
-        clk_fout_vpll.ops = &exynos4_vpll_ops;
-        clk_fout_vpll.rate = vpll;
-
-        printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
-                        apll, mpll, epll, vpll);
-
-        armclk = clk_get_rate(&exynos4_clk_armclk.clk);
-        sclk_dmc = clk_get_rate(&exynos4_clk_sclk_dmc.clk);
-
-        aclk_200 = clk_get_rate(&exynos4_clk_aclk_200.clk);
-        aclk_100 = clk_get_rate(&exynos4_clk_aclk_100.clk);
-        aclk_160 = clk_get_rate(&exynos4_clk_aclk_160.clk);
-        aclk_133 = clk_get_rate(&exynos4_clk_aclk_133.clk);
-
-        printk(KERN_INFO "EXYNOS4: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n"
-                         "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n",
-                        armclk, sclk_dmc, aclk_200,
-                        aclk_100, aclk_160, aclk_133);
-
-        clk_f.rate = armclk;
-        clk_h.rate = sclk_dmc;
-        clk_p.rate = aclk_100;
-
-        for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clksrcs); ptr++)
-                s3c_set_clksrc(&exynos4_clksrcs[ptr], true);
-}
-
-static struct clk *exynos4_clks[] __initdata = {
-        &exynos4_clk_sclk_hdmi27m,
-        &exynos4_clk_sclk_hdmiphy,
-        &exynos4_clk_sclk_usbphy0,
-        &exynos4_clk_sclk_usbphy1,
-};
-
-#ifdef CONFIG_PM_SLEEP
-static int exynos4_clock_suspend(void)
-{
-        s3c_pm_do_save(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
-        return 0;
-}
-
-static void exynos4_clock_resume(void)
-{
-        s3c_pm_do_restore_core(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
-}
-
-#else
-#define exynos4_clock_suspend NULL
-#define exynos4_clock_resume NULL
-#endif
-
-static struct syscore_ops exynos4_clock_syscore_ops = {
-        .suspend        = exynos4_clock_suspend,
-        .resume         = exynos4_clock_resume,
-};
-
-void __init exynos4_register_clocks(void)
-{
-        int ptr;
-
-        s3c24xx_register_clocks(exynos4_clks, ARRAY_SIZE(exynos4_clks));
-
-        for (ptr = 0; ptr < ARRAY_SIZE(exynos4_sysclks); ptr++)
-                s3c_register_clksrc(exynos4_sysclks[ptr], 1);
-
-        for (ptr = 0; ptr < ARRAY_SIZE(exynos4_sclk_tv); ptr++)
-                s3c_register_clksrc(exynos4_sclk_tv[ptr], 1);
-
-        for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clksrc_cdev); ptr++)
-                s3c_register_clksrc(exynos4_clksrc_cdev[ptr], 1);
-
-        s3c_register_clksrc(exynos4_clksrcs, ARRAY_SIZE(exynos4_clksrcs));
-        s3c_register_clocks(exynos4_init_clocks_on, ARRAY_SIZE(exynos4_init_clocks_on));
-
-        s3c24xx_register_clocks(exynos4_clk_cdev, ARRAY_SIZE(exynos4_clk_cdev));
-        for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clk_cdev); ptr++)
-                s3c_disable_clocks(exynos4_clk_cdev[ptr], 1);
-
-        s3c_register_clocks(exynos4_init_clocks_off, ARRAY_SIZE(exynos4_init_clocks_off));
-        s3c_disable_clocks(exynos4_init_clocks_off, ARRAY_SIZE(exynos4_init_clocks_off));
-        clkdev_add_table(exynos4_clk_lookup, ARRAY_SIZE(exynos4_clk_lookup));
-
-        register_syscore_ops(&exynos4_clock_syscore_ops);
-        s3c24xx_register_clock(&dummy_apb_pclk);
-
-        s3c_pwmclk_init();
-}
diff --git a/arch/arm/mach-exynos/clock-exynos4.h b/arch/arm/mach-exynos/clock-exynos4.h
deleted file mode 100644
index bd12d5f8b63d..000000000000
--- a/arch/arm/mach-exynos/clock-exynos4.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * Header file for exynos4 clock support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_CLOCK_H
-#define __ASM_ARCH_CLOCK_H __FILE__
-
-#include <linux/clk.h>
-
-extern struct clksrc_clk exynos4_clk_aclk_133;
-extern struct clksrc_clk exynos4_clk_mout_mpll;
-
-extern struct clksrc_sources exynos4_clkset_mout_corebus;
-extern struct clksrc_sources exynos4_clkset_group;
-
-extern struct clk *exynos4_clkset_aclk_top_list[];
-extern struct clk *exynos4_clkset_group_list[];
-
-extern struct clksrc_sources exynos4_clkset_mout_g2d0;
-extern struct clksrc_sources exynos4_clkset_mout_g2d1;
-
-extern int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable);
-extern int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable);
-extern int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable);
-extern int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable);
-extern int exynos4_clk_ip_dmc_ctrl(struct clk *clk, int enable);
-
-#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/mach-exynos/clock-exynos4210.c b/arch/arm/mach-exynos/clock-exynos4210.c
deleted file mode 100644
index 19af9f783c56..000000000000
--- a/arch/arm/mach-exynos/clock-exynos4210.c
+++ /dev/null
@@ -1,187 +0,0 @@
-/*
- * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * EXYNOS4210 - Clock support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/kernel.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/syscore_ops.h>
-
-#include <plat/cpu-freq.h>
-#include <plat/clock.h>
-#include <plat/cpu.h>
-#include <plat/pll.h>
-#include <plat/s5p-clock.h>
-#include <plat/clock-clksrc.h>
-#include <plat/pm.h>
-
-#include <mach/hardware.h>
-#include <mach/map.h>
-#include <mach/regs-clock.h>
-
-#include "common.h"
-#include "clock-exynos4.h"
-
-#ifdef CONFIG_PM_SLEEP
-static struct sleep_save exynos4210_clock_save[] = {
-        SAVE_ITEM(EXYNOS4_CLKSRC_IMAGE),
-        SAVE_ITEM(EXYNOS4_CLKDIV_IMAGE),
-        SAVE_ITEM(EXYNOS4210_CLKSRC_LCD1),
-        SAVE_ITEM(EXYNOS4210_CLKDIV_LCD1),
-        SAVE_ITEM(EXYNOS4210_CLKSRC_MASK_LCD1),
-        SAVE_ITEM(EXYNOS4210_CLKGATE_IP_IMAGE),
-        SAVE_ITEM(EXYNOS4210_CLKGATE_IP_LCD1),
-        SAVE_ITEM(EXYNOS4210_CLKGATE_IP_PERIR),
-};
-#endif
-
-static struct clksrc_clk *sysclks[] = {
-        /* nothing here yet */
-};
-
-static struct clksrc_clk exynos4210_clk_mout_g2d0 = {
-        .clk    = {
-                .name           = "mout_g2d0",
-        },
-        .sources = &exynos4_clkset_mout_g2d0,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 0, .size = 1 },
-};
-
-static struct clksrc_clk exynos4210_clk_mout_g2d1 = {
-        .clk    = {
-                .name           = "mout_g2d1",
-        },
-        .sources = &exynos4_clkset_mout_g2d1,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 4, .size = 1 },
-};
-
-static struct clk *exynos4210_clkset_mout_g2d_list[] = {
-        [0] = &exynos4210_clk_mout_g2d0.clk,
-        [1] = &exynos4210_clk_mout_g2d1.clk,
-};
-
-static struct clksrc_sources exynos4210_clkset_mout_g2d = {
-        .sources        = exynos4210_clkset_mout_g2d_list,
-        .nr_sources     = ARRAY_SIZE(exynos4210_clkset_mout_g2d_list),
-};
-
-static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4210_CLKSRC_MASK_LCD1, clk, enable);
-}
-
-static struct clksrc_clk clksrcs[] = {
-        {
-                .clk            = {
-                        .name           = "sclk_sata",
-                        .id             = -1,
-                        .enable         = exynos4_clksrc_mask_fsys_ctrl,
-                        .ctrlbit        = (1 << 24),
-                },
-                .sources = &exynos4_clkset_mout_corebus,
-                .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 24, .size = 1 },
-                .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS0, .shift = 20, .size = 4 },
-        }, {
-                .clk            = {
-                        .name           = "sclk_fimd",
-                        .devname        = "exynos4-fb.1",
-                        .enable         = exynos4_clksrc_mask_lcd1_ctrl,
-                        .ctrlbit        = (1 << 0),
-                },
-                .sources = &exynos4_clkset_group,
-                .reg_src = { .reg = EXYNOS4210_CLKSRC_LCD1, .shift = 0, .size = 4 },
-                .reg_div = { .reg = EXYNOS4210_CLKDIV_LCD1, .shift = 0, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_fimg2d",
-                },
-                .sources = &exynos4210_clkset_mout_g2d,
-                .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 8, .size = 1 },
-                .reg_div = { .reg = EXYNOS4_CLKDIV_IMAGE, .shift = 0, .size = 4 },
-        },
-};
-
-static struct clk init_clocks_off[] = {
-        {
-                .name           = "sataphy",
-                .id             = -1,
-                .parent         = &exynos4_clk_aclk_133.clk,
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 3),
-        }, {
-                .name           = "sata",
-                .id             = -1,
-                .parent         = &exynos4_clk_aclk_133.clk,
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 10),
-        }, {
-                .name           = "fimd",
-                .devname        = "exynos4-fb.1",
-                .enable         = exynos4_clk_ip_lcd1_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.9",
-                .enable         = exynos4_clk_ip_image_ctrl,
-                .ctrlbit        = (1 << 3),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.11",
-                .enable         = exynos4_clk_ip_lcd1_ctrl,
-                .ctrlbit        = (1 << 4),
-        }, {
-                .name           = "fimg2d",
-                .enable         = exynos4_clk_ip_image_ctrl,
-                .ctrlbit        = (1 << 0),
-        },
-};
-
-#ifdef CONFIG_PM_SLEEP
-static int exynos4210_clock_suspend(void)
-{
-        s3c_pm_do_save(exynos4210_clock_save, ARRAY_SIZE(exynos4210_clock_save));
-
-        return 0;
-}
-
-static void exynos4210_clock_resume(void)
-{
-        s3c_pm_do_restore_core(exynos4210_clock_save, ARRAY_SIZE(exynos4210_clock_save));
-}
-
-#else
-#define exynos4210_clock_suspend NULL
-#define exynos4210_clock_resume NULL
-#endif
-
-static struct syscore_ops exynos4210_clock_syscore_ops = {
-        .suspend        = exynos4210_clock_suspend,
-        .resume         = exynos4210_clock_resume,
-};
-
-void __init exynos4210_register_clocks(void)
-{
-        int ptr;
-
-        exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_CPU;
-        exynos4_clk_mout_mpll.reg_src.shift = 8;
-        exynos4_clk_mout_mpll.reg_src.size = 1;
-
-        for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
-                s3c_register_clksrc(sysclks[ptr], 1);
-
-        s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
-
-        s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
-        s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
-
-        register_syscore_ops(&exynos4210_clock_syscore_ops);
-}
diff --git a/arch/arm/mach-exynos/clock-exynos4212.c b/arch/arm/mach-exynos/clock-exynos4212.c
deleted file mode 100644
index 529476f8ec71..000000000000
--- a/arch/arm/mach-exynos/clock-exynos4212.c
+++ /dev/null
@@ -1,201 +0,0 @@
-/*
- * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * EXYNOS4212 - Clock support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/kernel.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/syscore_ops.h>
-
-#include <plat/cpu-freq.h>
-#include <plat/clock.h>
-#include <plat/cpu.h>
-#include <plat/pll.h>
-#include <plat/s5p-clock.h>
-#include <plat/clock-clksrc.h>
-#include <plat/pm.h>
-
-#include <mach/hardware.h>
-#include <mach/map.h>
-#include <mach/regs-clock.h>
-
-#include "common.h"
-#include "clock-exynos4.h"
-
-#ifdef CONFIG_PM_SLEEP
-static struct sleep_save exynos4212_clock_save[] = {
-        SAVE_ITEM(EXYNOS4_CLKSRC_IMAGE),
-        SAVE_ITEM(EXYNOS4_CLKDIV_IMAGE),
-        SAVE_ITEM(EXYNOS4212_CLKGATE_IP_IMAGE),
-        SAVE_ITEM(EXYNOS4212_CLKGATE_IP_PERIR),
-};
-#endif
-
-static int exynos4212_clk_ip_isp0_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKGATE_IP_ISP0, clk, enable);
-}
-
-static int exynos4212_clk_ip_isp1_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKGATE_IP_ISP1, clk, enable);
-}
-
-static struct clk *clk_src_mpll_user_list[] = {
-        [0] = &clk_fin_mpll,
-        [1] = &exynos4_clk_mout_mpll.clk,
-};
-
-static struct clksrc_sources clk_src_mpll_user = {
-        .sources        = clk_src_mpll_user_list,
-        .nr_sources     = ARRAY_SIZE(clk_src_mpll_user_list),
-};
-
-static struct clksrc_clk clk_mout_mpll_user = {
-        .clk = {
-                .name           = "mout_mpll_user",
-        },
-        .sources        = &clk_src_mpll_user,
-        .reg_src        = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 24, .size = 1 },
-};
-
-static struct clksrc_clk exynos4x12_clk_mout_g2d0 = {
-        .clk    = {
-                .name           = "mout_g2d0",
-        },
-        .sources = &exynos4_clkset_mout_g2d0,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 20, .size = 1 },
-};
-
-static struct clksrc_clk exynos4x12_clk_mout_g2d1 = {
-        .clk    = {
-                .name           = "mout_g2d1",
-        },
-        .sources = &exynos4_clkset_mout_g2d1,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 24, .size = 1 },
-};
-
-static struct clk *exynos4x12_clkset_mout_g2d_list[] = {
-        [0] = &exynos4x12_clk_mout_g2d0.clk,
-        [1] = &exynos4x12_clk_mout_g2d1.clk,
-};
-
-static struct clksrc_sources exynos4x12_clkset_mout_g2d = {
-        .sources        = exynos4x12_clkset_mout_g2d_list,
-        .nr_sources     = ARRAY_SIZE(exynos4x12_clkset_mout_g2d_list),
-};
-
-static struct clksrc_clk *sysclks[] = {
-        &clk_mout_mpll_user,
-};
-
-static struct clksrc_clk clksrcs[] = {
-        {
-                .clk    = {
-                        .name           = "sclk_fimg2d",
-                },
-                .sources = &exynos4x12_clkset_mout_g2d,
-                .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 28, .size = 1 },
-                .reg_div = { .reg = EXYNOS4_CLKDIV_DMC1, .shift = 0, .size = 4 },
-        },
-};
-
-static struct clk init_clocks_off[] = {
-        {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.9",
-                .enable         = exynos4_clk_ip_dmc_ctrl,
-                .ctrlbit        = (1 << 24),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.12",
-                .enable         = exynos4212_clk_ip_isp0_ctrl,
-                .ctrlbit        = (7 << 8),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.13",
-                .enable         = exynos4212_clk_ip_isp1_ctrl,
-                .ctrlbit        = (1 << 4),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.14",
-                .enable         = exynos4212_clk_ip_isp0_ctrl,
-                .ctrlbit        = (1 << 11),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.15",
-                .enable         = exynos4212_clk_ip_isp0_ctrl,
-                .ctrlbit        = (1 << 12),
-        }, {
-                .name           = "flite",
-                .devname        = "exynos-fimc-lite.0",
-                .enable         = exynos4212_clk_ip_isp0_ctrl,
-                .ctrlbit        = (1 << 4),
-        }, {
-                .name           = "flite",
-                .devname        = "exynos-fimc-lite.1",
-                .enable         = exynos4212_clk_ip_isp0_ctrl,
-                .ctrlbit        = (1 << 3),
-        }, {
-                .name           = "fimg2d",
-                .enable         = exynos4_clk_ip_dmc_ctrl,
-                .ctrlbit        = (1 << 23),
-        },
-};
-
-#ifdef CONFIG_PM_SLEEP
-static int exynos4212_clock_suspend(void)
-{
-        s3c_pm_do_save(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save));
-
-        return 0;
-}
-
-static void exynos4212_clock_resume(void)
-{
-        s3c_pm_do_restore_core(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save));
-}
-
-#else
-#define exynos4212_clock_suspend NULL
-#define exynos4212_clock_resume NULL
-#endif
-
-static struct syscore_ops exynos4212_clock_syscore_ops = {
-        .suspend        = exynos4212_clock_suspend,
-        .resume         = exynos4212_clock_resume,
-};
-
-void __init exynos4212_register_clocks(void)
-{
-        int ptr;
-
-        /* usbphy1 is removed */
-        exynos4_clkset_group_list[4] = NULL;
-
-        /* mout_mpll_user is used */
-        exynos4_clkset_group_list[6] = &clk_mout_mpll_user.clk;
-        exynos4_clkset_aclk_top_list[0] = &clk_mout_mpll_user.clk;
-
-        exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_DMC;
-        exynos4_clk_mout_mpll.reg_src.shift = 12;
-        exynos4_clk_mout_mpll.reg_src.size = 1;
-
-        for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
-                s3c_register_clksrc(sysclks[ptr], 1);
-
-        s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
-
-        s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
-        s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
-
-        register_syscore_ops(&exynos4212_clock_syscore_ops);
-}
diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
deleted file mode 100644
index b0ea31fc9fb8..000000000000
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ /dev/null
@@ -1,1645 +0,0 @@
-/*
- * Copyright (c) 2012 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * Clock support for EXYNOS5 SoCs
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/kernel.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/syscore_ops.h>
-
-#include <plat/cpu-freq.h>
-#include <plat/clock.h>
-#include <plat/cpu.h>
-#include <plat/pll.h>
-#include <plat/s5p-clock.h>
-#include <plat/clock-clksrc.h>
-#include <plat/pm.h>
-
-#include <mach/map.h>
-#include <mach/regs-clock.h>
-
-#include "common.h"
-
-#ifdef CONFIG_PM_SLEEP
-static struct sleep_save exynos5_clock_save[] = {
-        SAVE_ITEM(EXYNOS5_CLKSRC_MASK_TOP),
-        SAVE_ITEM(EXYNOS5_CLKSRC_MASK_GSCL),
-        SAVE_ITEM(EXYNOS5_CLKSRC_MASK_DISP1_0),
-        SAVE_ITEM(EXYNOS5_CLKSRC_MASK_FSYS),
-        SAVE_ITEM(EXYNOS5_CLKSRC_MASK_MAUDIO),
-        SAVE_ITEM(EXYNOS5_CLKSRC_MASK_PERIC0),
-        SAVE_ITEM(EXYNOS5_CLKSRC_MASK_PERIC1),
-        SAVE_ITEM(EXYNOS5_CLKGATE_IP_GSCL),
-        SAVE_ITEM(EXYNOS5_CLKGATE_IP_DISP1),
-        SAVE_ITEM(EXYNOS5_CLKGATE_IP_MFC),
-        SAVE_ITEM(EXYNOS5_CLKGATE_IP_G3D),
-        SAVE_ITEM(EXYNOS5_CLKGATE_IP_GEN),
-        SAVE_ITEM(EXYNOS5_CLKGATE_IP_FSYS),
-        SAVE_ITEM(EXYNOS5_CLKGATE_IP_PERIC),
-        SAVE_ITEM(EXYNOS5_CLKGATE_IP_PERIS),
-        SAVE_ITEM(EXYNOS5_CLKGATE_BLOCK),
-        SAVE_ITEM(EXYNOS5_CLKDIV_TOP0),
-        SAVE_ITEM(EXYNOS5_CLKDIV_TOP1),
-        SAVE_ITEM(EXYNOS5_CLKDIV_GSCL),
-        SAVE_ITEM(EXYNOS5_CLKDIV_DISP1_0),
-        SAVE_ITEM(EXYNOS5_CLKDIV_GEN),
-        SAVE_ITEM(EXYNOS5_CLKDIV_MAUDIO),
-        SAVE_ITEM(EXYNOS5_CLKDIV_FSYS0),
-        SAVE_ITEM(EXYNOS5_CLKDIV_FSYS1),
-        SAVE_ITEM(EXYNOS5_CLKDIV_FSYS2),
-        SAVE_ITEM(EXYNOS5_CLKDIV_FSYS3),
-        SAVE_ITEM(EXYNOS5_CLKDIV_PERIC0),
-        SAVE_ITEM(EXYNOS5_CLKDIV_PERIC1),
-        SAVE_ITEM(EXYNOS5_CLKDIV_PERIC2),
-        SAVE_ITEM(EXYNOS5_CLKDIV_PERIC3),
-        SAVE_ITEM(EXYNOS5_CLKDIV_PERIC4),
-        SAVE_ITEM(EXYNOS5_CLKDIV_PERIC5),
-        SAVE_ITEM(EXYNOS5_SCLK_DIV_ISP),
-        SAVE_ITEM(EXYNOS5_CLKSRC_TOP0),
-        SAVE_ITEM(EXYNOS5_CLKSRC_TOP1),
-        SAVE_ITEM(EXYNOS5_CLKSRC_TOP2),
-        SAVE_ITEM(EXYNOS5_CLKSRC_TOP3),
-        SAVE_ITEM(EXYNOS5_CLKSRC_GSCL),
-        SAVE_ITEM(EXYNOS5_CLKSRC_DISP1_0),
-        SAVE_ITEM(EXYNOS5_CLKSRC_MAUDIO),
-        SAVE_ITEM(EXYNOS5_CLKSRC_FSYS),
-        SAVE_ITEM(EXYNOS5_CLKSRC_PERIC0),
-        SAVE_ITEM(EXYNOS5_CLKSRC_PERIC1),
-        SAVE_ITEM(EXYNOS5_SCLK_SRC_ISP),
-        SAVE_ITEM(EXYNOS5_EPLL_CON0),
-        SAVE_ITEM(EXYNOS5_EPLL_CON1),
-        SAVE_ITEM(EXYNOS5_EPLL_CON2),
-        SAVE_ITEM(EXYNOS5_VPLL_CON0),
-        SAVE_ITEM(EXYNOS5_VPLL_CON1),
-        SAVE_ITEM(EXYNOS5_VPLL_CON2),
-        SAVE_ITEM(EXYNOS5_PWR_CTRL1),
-        SAVE_ITEM(EXYNOS5_PWR_CTRL2),
-};
-#endif
-
-static struct clk exynos5_clk_sclk_dptxphy = {
-        .name           = "sclk_dptx",
-};
-
-static struct clk exynos5_clk_sclk_hdmi24m = {
-        .name           = "sclk_hdmi24m",
-        .rate           = 24000000,
-};
-
-static struct clk exynos5_clk_sclk_hdmi27m = {
-        .name           = "sclk_hdmi27m",
-        .rate           = 27000000,
-};
-
-static struct clk exynos5_clk_sclk_hdmiphy = {
-        .name           = "sclk_hdmiphy",
-};
-
-static struct clk exynos5_clk_sclk_usbphy = {
-        .name           = "sclk_usbphy",
-        .rate           = 48000000,
-};
-
-static int exynos5_clksrc_mask_top_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_TOP, clk, enable);
-}
-
-static int exynos5_clksrc_mask_disp1_0_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_DISP1_0, clk, enable);
-}
-
-static int exynos5_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_FSYS, clk, enable);
-}
-
-static int exynos5_clksrc_mask_gscl_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_GSCL, clk, enable);
-}
-
-static int exynos5_clksrc_mask_peric0_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC0, clk, enable);
-}
-
-static int exynos5_clksrc_mask_peric1_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC1, clk, enable);
-}
-
-static int exynos5_clk_ip_acp_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ACP, clk, enable);
-}
-
-static int exynos5_clk_ip_core_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKGATE_IP_CORE, clk, enable);
-}
-
-static int exynos5_clk_ip_disp1_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKGATE_IP_DISP1, clk, enable);
-}
-
-static int exynos5_clk_ip_fsys_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKGATE_IP_FSYS, clk, enable);
-}
-
-static int exynos5_clk_block_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKGATE_BLOCK, clk, enable);
-}
-
-static int exynos5_clk_ip_gen_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GEN, clk, enable);
-}
-
-static int exynos5_clk_ip_mfc_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKGATE_IP_MFC, clk, enable);
-}
-
-static int exynos5_clk_ip_peric_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKGATE_IP_PERIC, clk, enable);
-}
-
-static int exynos5_clk_ip_peris_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKGATE_IP_PERIS, clk, enable);
-}
-
-static int exynos5_clk_ip_gscl_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GSCL, clk, enable);
-}
-
-static int exynos5_clk_ip_isp0_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ISP0, clk, enable);
-}
-
-static int exynos5_clk_ip_isp1_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ISP1, clk, enable);
-}
-
-static int exynos5_clk_hdmiphy_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
-}
-
-/* Core list of CMU_CPU side */
-
-static struct clksrc_clk exynos5_clk_mout_apll = {
-        .clk    = {
-                .name           = "mout_apll",
-        },
-        .sources = &clk_src_apll,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_CPU, .shift = 0, .size = 1 },
-};
-
-static struct clksrc_clk exynos5_clk_sclk_apll = {
-        .clk    = {
-                .name           = "sclk_apll",
-                .parent         = &exynos5_clk_mout_apll.clk,
-        },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 24, .size = 3 },
-};
-
-static struct clksrc_clk exynos5_clk_mout_bpll_fout = {
-        .clk    = {
-                .name           = "mout_bpll_fout",
-        },
-        .sources = &clk_src_bpll_fout,
-        .reg_src = { .reg = EXYNOS5_PLL_DIV2_SEL, .shift = 0, .size = 1 },
-};
-
-static struct clk *exynos5_clk_src_bpll_list[] = {
-        [0] = &clk_fin_bpll,
-        [1] = &exynos5_clk_mout_bpll_fout.clk,
-};
-
-static struct clksrc_sources exynos5_clk_src_bpll = {
-        .sources        = exynos5_clk_src_bpll_list,
-        .nr_sources     = ARRAY_SIZE(exynos5_clk_src_bpll_list),
-};
-
-static struct clksrc_clk exynos5_clk_mout_bpll = {
-        .clk    = {
-                .name           = "mout_bpll",
-        },
-        .sources = &exynos5_clk_src_bpll,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 0, .size = 1 },
-};
-
-static struct clk *exynos5_clk_src_bpll_user_list[] = {
-        [0] = &clk_fin_mpll,
-        [1] = &exynos5_clk_mout_bpll.clk,
-};
-
-static struct clksrc_sources exynos5_clk_src_bpll_user = {
-        .sources        = exynos5_clk_src_bpll_user_list,
-        .nr_sources     = ARRAY_SIZE(exynos5_clk_src_bpll_user_list),
-};
-
-static struct clksrc_clk exynos5_clk_mout_bpll_user = {
-        .clk    = {
-                .name           = "mout_bpll_user",
-        },
-        .sources = &exynos5_clk_src_bpll_user,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 24, .size = 1 },
-};
-
-static struct clksrc_clk exynos5_clk_mout_cpll = {
-        .clk    = {
-                .name           = "mout_cpll",
-        },
-        .sources = &clk_src_cpll,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 8, .size = 1 },
-};
-
-static struct clksrc_clk exynos5_clk_mout_epll = {
-        .clk    = {
-                .name           = "mout_epll",
-        },
-        .sources = &clk_src_epll,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 12, .size = 1 },
-};
-
-static struct clksrc_clk exynos5_clk_mout_mpll_fout = {
-        .clk    = {
-                .name           = "mout_mpll_fout",
-        },
-        .sources = &clk_src_mpll_fout,
-        .reg_src = { .reg = EXYNOS5_PLL_DIV2_SEL, .shift = 4, .size = 1 },
-};
-
-static struct clk *exynos5_clk_src_mpll_list[] = {
-        [0] = &clk_fin_mpll,
-        [1] = &exynos5_clk_mout_mpll_fout.clk,
-};
-
-static struct clksrc_sources exynos5_clk_src_mpll = {
-        .sources        = exynos5_clk_src_mpll_list,
-        .nr_sources     = ARRAY_SIZE(exynos5_clk_src_mpll_list),
-};
-
-static struct clksrc_clk exynos5_clk_mout_mpll = {
-        .clk = {
-                .name           = "mout_mpll",
-        },
-        .sources = &exynos5_clk_src_mpll,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_CORE1, .shift = 8, .size = 1 },
-};
-
-static struct clk *exynos_clkset_vpllsrc_list[] = {
-        [0] = &clk_fin_vpll,
-        [1] = &exynos5_clk_sclk_hdmi27m,
-};
-
-static struct clksrc_sources exynos5_clkset_vpllsrc = {
-        .sources        = exynos_clkset_vpllsrc_list,
-        .nr_sources     = ARRAY_SIZE(exynos_clkset_vpllsrc_list),
-};
-
-static struct clksrc_clk exynos5_clk_vpllsrc = {
-        .clk    = {
-                .name           = "vpll_src",
-                .enable         = exynos5_clksrc_mask_top_ctrl,
-                .ctrlbit        = (1 << 0),
-        },
-        .sources = &exynos5_clkset_vpllsrc,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 0, .size = 1 },
-};
-
-static struct clk *exynos5_clkset_sclk_vpll_list[] = {
-        [0] = &exynos5_clk_vpllsrc.clk,
-        [1] = &clk_fout_vpll,
-};
-
-static struct clksrc_sources exynos5_clkset_sclk_vpll = {
-        .sources        = exynos5_clkset_sclk_vpll_list,
-        .nr_sources     = ARRAY_SIZE(exynos5_clkset_sclk_vpll_list),
-};
-
-static struct clksrc_clk exynos5_clk_sclk_vpll = {
-        .clk    = {
-                .name           = "sclk_vpll",
-        },
-        .sources = &exynos5_clkset_sclk_vpll,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 16, .size = 1 },
-};
-
-static struct clksrc_clk exynos5_clk_sclk_pixel = {
-        .clk    = {
-                .name           = "sclk_pixel",
-                .parent         = &exynos5_clk_sclk_vpll.clk,
-        },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 28, .size = 4 },
-};
-
-static struct clk *exynos5_clkset_sclk_hdmi_list[] = {
-        [0] = &exynos5_clk_sclk_pixel.clk,
-        [1] = &exynos5_clk_sclk_hdmiphy,
-};
-
-static struct clksrc_sources exynos5_clkset_sclk_hdmi = {
-        .sources        = exynos5_clkset_sclk_hdmi_list,
-        .nr_sources     = ARRAY_SIZE(exynos5_clkset_sclk_hdmi_list),
-};
-
-static struct clksrc_clk exynos5_clk_sclk_hdmi = {
-        .clk    = {
-                .name           = "sclk_hdmi",
-                .enable         = exynos5_clksrc_mask_disp1_0_ctrl,
-                .ctrlbit        = (1 << 20),
-        },
-        .sources = &exynos5_clkset_sclk_hdmi,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 20, .size = 1 },
-};
-
-static struct clksrc_clk *exynos5_sclk_tv[] = {
-        &exynos5_clk_sclk_pixel,
-        &exynos5_clk_sclk_hdmi,
-};
-
-static struct clk *exynos5_clk_src_mpll_user_list[] = {
-        [0] = &clk_fin_mpll,
-        [1] = &exynos5_clk_mout_mpll.clk,
-};
-
-static struct clksrc_sources exynos5_clk_src_mpll_user = {
-        .sources        = exynos5_clk_src_mpll_user_list,
-        .nr_sources     = ARRAY_SIZE(exynos5_clk_src_mpll_user_list),
-};
-
-static struct clksrc_clk exynos5_clk_mout_mpll_user = {
-        .clk    = {
-                .name           = "mout_mpll_user",
-        },
-        .sources = &exynos5_clk_src_mpll_user,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 20, .size = 1 },
-};
-
-static struct clk *exynos5_clkset_mout_cpu_list[] = {
-        [0] = &exynos5_clk_mout_apll.clk,
-        [1] = &exynos5_clk_mout_mpll.clk,
-};
-
-static struct clksrc_sources exynos5_clkset_mout_cpu = {
-        .sources        = exynos5_clkset_mout_cpu_list,
-        .nr_sources     = ARRAY_SIZE(exynos5_clkset_mout_cpu_list),
-};
-
-static struct clksrc_clk exynos5_clk_mout_cpu = {
-        .clk    = {
-                .name           = "mout_cpu",
-        },
-        .sources = &exynos5_clkset_mout_cpu,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_CPU, .shift = 16, .size = 1 },
-};
-
-static struct clksrc_clk exynos5_clk_dout_armclk = {
-        .clk    = {
-                .name           = "dout_armclk",
-                .parent         = &exynos5_clk_mout_cpu.clk,
-        },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 0, .size = 3 },
-};
-
-static struct clksrc_clk exynos5_clk_dout_arm2clk = {
-        .clk    = {
-                .name           = "dout_arm2clk",
-                .parent         = &exynos5_clk_dout_armclk.clk,
-        },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 28, .size = 3 },
-};
-
-static struct clk exynos5_clk_armclk = {
-        .name           = "armclk",
-        .parent         = &exynos5_clk_dout_arm2clk.clk,
-};
-
-/* Core list of CMU_CDREX side */
-
-static struct clk *exynos5_clkset_cdrex_list[] = {
-        [0] = &exynos5_clk_mout_mpll.clk,
-        [1] = &exynos5_clk_mout_bpll.clk,
-};
-
-static struct clksrc_sources exynos5_clkset_cdrex = {
-        .sources        = exynos5_clkset_cdrex_list,
-        .nr_sources     = ARRAY_SIZE(exynos5_clkset_cdrex_list),
-};
-
-static struct clksrc_clk exynos5_clk_cdrex = {
-        .clk    = {
-                .name           = "clk_cdrex",
-        },
-        .sources = &exynos5_clkset_cdrex,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 4, .size = 1 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_CDREX, .shift = 16, .size = 3 },
-};
-
-static struct clksrc_clk exynos5_clk_aclk_acp = {
-        .clk    = {
-                .name           = "aclk_acp",
-                .parent         = &exynos5_clk_mout_mpll.clk,
-        },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_ACP, .shift = 0, .size = 3 },
-};
-
-static struct clksrc_clk exynos5_clk_pclk_acp = {
-        .clk    = {
-                .name           = "pclk_acp",
-                .parent         = &exynos5_clk_aclk_acp.clk,
-        },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_ACP, .shift = 4, .size = 3 },
-};
-
-/* Core list of CMU_TOP side */
-
-static struct clk *exynos5_clkset_aclk_top_list[] = {
-        [0] = &exynos5_clk_mout_mpll_user.clk,
-        [1] = &exynos5_clk_mout_bpll_user.clk,
-};
-
-static struct clksrc_sources exynos5_clkset_aclk = {
-        .sources        = exynos5_clkset_aclk_top_list,
-        .nr_sources     = ARRAY_SIZE(exynos5_clkset_aclk_top_list),
-};
-
-static struct clksrc_clk exynos5_clk_aclk_400 = {
-        .clk    = {
-                .name           = "aclk_400",
-        },
-        .sources = &exynos5_clkset_aclk,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 20, .size = 1 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 24, .size = 3 },
-};
-
-static struct clk *exynos5_clkset_aclk_333_166_list[] = {
-        [0] = &exynos5_clk_mout_cpll.clk,
-        [1] = &exynos5_clk_mout_mpll_user.clk,
-};
-
-static struct clksrc_sources exynos5_clkset_aclk_333_166 = {
-        .sources        = exynos5_clkset_aclk_333_166_list,
-        .nr_sources     = ARRAY_SIZE(exynos5_clkset_aclk_333_166_list),
-};
-
-static struct clksrc_clk exynos5_clk_aclk_333 = {
-        .clk    = {
-                .name           = "aclk_333",
-        },
-        .sources = &exynos5_clkset_aclk_333_166,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 16, .size = 1 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 20, .size = 3 },
-};
-
-static struct clksrc_clk exynos5_clk_aclk_166 = {
-        .clk    = {
-                .name           = "aclk_166",
-        },
-        .sources = &exynos5_clkset_aclk_333_166,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 8, .size = 1 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 8, .size = 3 },
-};
-
-static struct clksrc_clk exynos5_clk_aclk_266 = {
-        .clk    = {
-                .name           = "aclk_266",
-                .parent         = &exynos5_clk_mout_mpll_user.clk,
-        },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 16, .size = 3 },
-};
-
-static struct clksrc_clk exynos5_clk_aclk_200 = {
-        .clk    = {
-                .name           = "aclk_200",
-        },
-        .sources = &exynos5_clkset_aclk,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 12, .size = 1 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 12, .size = 3 },
-};
-
-static struct clksrc_clk exynos5_clk_aclk_66_pre = {
-        .clk    = {
-                .name           = "aclk_66_pre",
-                .parent         = &exynos5_clk_mout_mpll_user.clk,
-        },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_TOP1, .shift = 24, .size = 3 },
-};
-
-static struct clksrc_clk exynos5_clk_aclk_66 = {
-        .clk    = {
-                .name           = "aclk_66",
-                .parent         = &exynos5_clk_aclk_66_pre.clk,
-        },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 0, .size = 3 },
-};
-
-static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl_mid = {
-        .clk    = {
-                .name           = "mout_aclk_300_gscl_mid",
-        },
-        .sources = &exynos5_clkset_aclk,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 24, .size = 1 },
-};
-
-static struct clk *exynos5_clkset_aclk_300_mid1_list[] = {
-        [0] = &exynos5_clk_sclk_vpll.clk,
-        [1] = &exynos5_clk_mout_cpll.clk,
-};
-
-static struct clksrc_sources exynos5_clkset_aclk_300_gscl_mid1 = {
-        .sources        = exynos5_clkset_aclk_300_mid1_list,
-        .nr_sources     = ARRAY_SIZE(exynos5_clkset_aclk_300_mid1_list),
-};
-
-static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl_mid1 = {
-        .clk    = {
-                .name           = "mout_aclk_300_gscl_mid1",
-        },
-        .sources = &exynos5_clkset_aclk_300_gscl_mid1,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP1, .shift = 12, .size = 1 },
-};
-
-static struct clk *exynos5_clkset_aclk_300_gscl_list[] = {
-        [0] = &exynos5_clk_mout_aclk_300_gscl_mid.clk,
-        [1] = &exynos5_clk_mout_aclk_300_gscl_mid1.clk,
-};
-
-static struct clksrc_sources exynos5_clkset_aclk_300_gscl = {
-        .sources        = exynos5_clkset_aclk_300_gscl_list,
-        .nr_sources     = ARRAY_SIZE(exynos5_clkset_aclk_300_gscl_list),
-};
-
-static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl = {
-        .clk    = {
-                .name           = "mout_aclk_300_gscl",
-        },
-        .sources = &exynos5_clkset_aclk_300_gscl,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 25, .size = 1 },
-};
-
-static struct clk *exynos5_clk_src_gscl_300_list[] = {
-        [0] = &clk_ext_xtal_mux,
-        [1] = &exynos5_clk_mout_aclk_300_gscl.clk,
-};
-
-static struct clksrc_sources exynos5_clk_src_gscl_300 = {
-        .sources        = exynos5_clk_src_gscl_300_list,
-        .nr_sources     = ARRAY_SIZE(exynos5_clk_src_gscl_300_list),
-};
-
-static struct clksrc_clk exynos5_clk_aclk_300_gscl = {
-        .clk    = {
-                .name           = "aclk_300_gscl",
-        },
-        .sources = &exynos5_clk_src_gscl_300,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 10, .size = 1 },
-};
-
-static struct clk exynos5_init_clocks_off[] = {
-        {
-                .name           = "timers",
-                .parent         = &exynos5_clk_aclk_66.clk,
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 24),
-        }, {
-                .name           = "tmu_apbif",
-                .parent         = &exynos5_clk_aclk_66.clk,
-                .enable         = exynos5_clk_ip_peris_ctrl,
-                .ctrlbit        = (1 << 21),
-        }, {
-                .name           = "rtc",
-                .parent         = &exynos5_clk_aclk_66.clk,
-                .enable         = exynos5_clk_ip_peris_ctrl,
-                .ctrlbit        = (1 << 20),
-        }, {
-                .name           = "watchdog",
-                .parent         = &exynos5_clk_aclk_66.clk,
-                .enable         = exynos5_clk_ip_peris_ctrl,
-                .ctrlbit        = (1 << 19),
-        }, {
-                .name           = "biu",        /* bus interface unit clock */
-                .devname        = "dw_mmc.0",
-                .parent         = &exynos5_clk_aclk_200.clk,
-                .enable         = exynos5_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 12),
-        }, {
-                .name           = "biu",
-                .devname        = "dw_mmc.1",
-                .parent         = &exynos5_clk_aclk_200.clk,
-                .enable         = exynos5_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 13),
-        }, {
-                .name           = "biu",
-                .devname        = "dw_mmc.2",
-                .parent         = &exynos5_clk_aclk_200.clk,
-                .enable         = exynos5_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 14),
-        }, {
-                .name           = "biu",
-                .devname        = "dw_mmc.3",
-                .parent         = &exynos5_clk_aclk_200.clk,
-                .enable         = exynos5_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 15),
-        }, {
-                .name           = "sata",
-                .devname        = "exynos5-sata",
-                .parent         = &exynos5_clk_aclk_200.clk,
-                .enable         = exynos5_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 6),
-        }, {
-                .name           = "sata-phy",
-                .devname        = "exynos5-sata-phy",
-                .parent         = &exynos5_clk_aclk_200.clk,
-                .enable         = exynos5_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 24),
-        }, {
-                .name           = "i2c",
-                .devname        = "exynos5-sata-phy-i2c",
-                .parent         = &exynos5_clk_aclk_200.clk,
-                .enable         = exynos5_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 25),
-        }, {
-                .name           = "mfc",
-                .devname        = "s5p-mfc-v6",
-                .enable         = exynos5_clk_ip_mfc_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "hdmi",
-                .devname        = "exynos5-hdmi",
-                .enable         = exynos5_clk_ip_disp1_ctrl,
-                .ctrlbit        = (1 << 6),
-        }, {
-                .name           = "hdmiphy",
-                .devname        = "exynos5-hdmi",
-                .enable         = exynos5_clk_hdmiphy_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "mixer",
-                .devname        = "exynos5-mixer",
-                .enable         = exynos5_clk_ip_disp1_ctrl,
-                .ctrlbit        = (1 << 5),
-        }, {
-                .name           = "dp",
-                .devname        = "exynos-dp",
-                .enable         = exynos5_clk_ip_disp1_ctrl,
-                .ctrlbit        = (1 << 4),
-        }, {
-                .name           = "jpeg",
-                .enable         = exynos5_clk_ip_gen_ctrl,
-                .ctrlbit        = (1 << 2),
-        }, {
-                .name           = "dsim0",
-                .enable         = exynos5_clk_ip_disp1_ctrl,
-                .ctrlbit        = (1 << 3),
-        }, {
-                .name           = "iis",
-                .devname        = "samsung-i2s.1",
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 20),
-        }, {
-                .name           = "iis",
-                .devname        = "samsung-i2s.2",
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 21),
-        }, {
-                .name           = "pcm",
-                .devname        = "samsung-pcm.1",
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 22),
-        }, {
-                .name           = "pcm",
-                .devname        = "samsung-pcm.2",
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 23),
-        }, {
-                .name           = "spdif",
-                .devname        = "samsung-spdif",
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 26),
-        }, {
-                .name           = "ac97",
-                .devname        = "samsung-ac97",
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 27),
-        }, {
-                .name           = "usbhost",
-                .enable         = exynos5_clk_ip_fsys_ctrl ,
-                .ctrlbit        = (1 << 18),
-        }, {
-                .name           = "usbotg",
-                .enable         = exynos5_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 7),
-        }, {
-                .name           = "nfcon",
-                .enable         = exynos5_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 22),
-        }, {
-                .name           = "iop",
-                .enable         = exynos5_clk_ip_fsys_ctrl,
-                .ctrlbit        = ((1 << 30) | (1 << 26) | (1 << 23)),
-        }, {
-                .name           = "core_iop",
-                .enable         = exynos5_clk_ip_core_ctrl,
-                .ctrlbit        = ((1 << 21) | (1 << 3)),
-        }, {
-                .name           = "mcu_iop",
-                .enable         = exynos5_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.0",
-                .parent         = &exynos5_clk_aclk_66.clk,
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 6),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.1",
-                .parent         = &exynos5_clk_aclk_66.clk,
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 7),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.2",
-                .parent         = &exynos5_clk_aclk_66.clk,
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 8),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.3",
-                .parent         = &exynos5_clk_aclk_66.clk,
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 9),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.4",
-                .parent         = &exynos5_clk_aclk_66.clk,
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 10),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.5",
-                .parent         = &exynos5_clk_aclk_66.clk,
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 11),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.6",
-                .parent         = &exynos5_clk_aclk_66.clk,
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 12),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.7",
-                .parent         = &exynos5_clk_aclk_66.clk,
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 13),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-hdmiphy-i2c",
-                .parent         = &exynos5_clk_aclk_66.clk,
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 14),
-        }, {
-                .name           = "spi",
-                .devname        = "exynos4210-spi.0",
-                .parent         = &exynos5_clk_aclk_66.clk,
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 16),
-        }, {
-                .name           = "spi",
-                .devname        = "exynos4210-spi.1",
-                .parent         = &exynos5_clk_aclk_66.clk,
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 17),
-        }, {
-                .name           = "spi",
-                .devname        = "exynos4210-spi.2",
-                .parent         = &exynos5_clk_aclk_66.clk,
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 18),
-        }, {
-                .name           = "gscl",
-                .devname        = "exynos-gsc.0",
-                .enable         = exynos5_clk_ip_gscl_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "gscl",
-                .devname        = "exynos-gsc.1",
-                .enable         = exynos5_clk_ip_gscl_ctrl,
-                .ctrlbit        = (1 << 1),
-        }, {
-                .name           = "gscl",
-                .devname        = "exynos-gsc.2",
-                .enable         = exynos5_clk_ip_gscl_ctrl,
-                .ctrlbit        = (1 << 2),
-        }, {
-                .name           = "gscl",
-                .devname        = "exynos-gsc.3",
-                .enable         = exynos5_clk_ip_gscl_ctrl,
-                .ctrlbit        = (1 << 3),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.1",
-                .enable         = &exynos5_clk_ip_mfc_ctrl,
-                .ctrlbit        = (1 << 1),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.0",
-                .enable         = &exynos5_clk_ip_mfc_ctrl,
-                .ctrlbit        = (1 << 2),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.2",
-                .enable         = &exynos5_clk_ip_disp1_ctrl,
-                .ctrlbit        = (1 << 9)
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.3",
-                .enable         = &exynos5_clk_ip_gen_ctrl,
-                .ctrlbit        = (1 << 7),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.4",
-                .enable         = &exynos5_clk_ip_gen_ctrl,
-                .ctrlbit        = (1 << 6)
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.5",
-                .enable         = &exynos5_clk_ip_gscl_ctrl,
-                .ctrlbit        = (1 << 7),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.6",
-                .enable         = &exynos5_clk_ip_gscl_ctrl,
-                .ctrlbit        = (1 << 8),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.7",
-                .enable         = &exynos5_clk_ip_gscl_ctrl,
-                .ctrlbit        = (1 << 9),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.8",
-                .enable         = &exynos5_clk_ip_gscl_ctrl,
-                .ctrlbit        = (1 << 10),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.9",
-                .enable         = &exynos5_clk_ip_isp0_ctrl,
-                .ctrlbit        = (0x3F << 8),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.10",
-                .enable         = &exynos5_clk_ip_isp1_ctrl,
-                .ctrlbit        = (0xF << 4),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.11",
-                .enable         = &exynos5_clk_ip_disp1_ctrl,
-                .ctrlbit        = (1 << 8)
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.12",
-                .enable         = &exynos5_clk_ip_gscl_ctrl,
-                .ctrlbit        = (1 << 11),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.13",
-                .enable         = &exynos5_clk_ip_gscl_ctrl,
-                .ctrlbit        = (1 << 12),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.14",
-                .enable         = &exynos5_clk_ip_acp_ctrl,
-                .ctrlbit        = (1 << 7)
-        }
-};
-
-static struct clk exynos5_init_clocks_on[] = {
-        {
-                .name           = "uart",
-                .devname        = "s5pv210-uart.0",
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "uart",
-                .devname        = "s5pv210-uart.1",
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 1),
-        }, {
-                .name           = "uart",
-                .devname        = "s5pv210-uart.2",
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 2),
-        }, {
-                .name           = "uart",
-                .devname        = "s5pv210-uart.3",
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 3),
-        }, {
-                .name           = "uart",
-                .devname        = "s5pv210-uart.4",
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 4),
-        }, {
-                .name           = "uart",
-                .devname        = "s5pv210-uart.5",
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 5),
-        }
-};
-
-static struct clk exynos5_clk_pdma0 = {
-        .name           = "dma",
-        .devname        = "dma-pl330.0",
-        .enable         = exynos5_clk_ip_fsys_ctrl,
-        .ctrlbit        = (1 << 1),
-};
-
-static struct clk exynos5_clk_pdma1 = {
-        .name           = "dma",
-        .devname        = "dma-pl330.1",
-        .enable         = exynos5_clk_ip_fsys_ctrl,
-        .ctrlbit        = (1 << 2),
-};
-
-static struct clk exynos5_clk_mdma1 = {
-        .name           = "dma",
-        .devname        = "dma-pl330.2",
-        .enable         = exynos5_clk_ip_gen_ctrl,
-        .ctrlbit        = (1 << 4),
-};
-
-static struct clk exynos5_clk_fimd1 = {
-        .name           = "fimd",
-        .devname        = "exynos5-fb.1",
-        .enable         = exynos5_clk_ip_disp1_ctrl,
-        .ctrlbit        = (1 << 0),
-};
-
-static struct clk *exynos5_clkset_group_list[] = {
-        [0] = &clk_ext_xtal_mux,
-        [1] = NULL,
-        [2] = &exynos5_clk_sclk_hdmi24m,
-        [3] = &exynos5_clk_sclk_dptxphy,
-        [4] = &exynos5_clk_sclk_usbphy,
-        [5] = &exynos5_clk_sclk_hdmiphy,
-        [6] = &exynos5_clk_mout_mpll_user.clk,
-        [7] = &exynos5_clk_mout_epll.clk,
-        [8] = &exynos5_clk_sclk_vpll.clk,
-        [9] = &exynos5_clk_mout_cpll.clk,
-};
-
-static struct clksrc_sources exynos5_clkset_group = {
-        .sources        = exynos5_clkset_group_list,
-        .nr_sources     = ARRAY_SIZE(exynos5_clkset_group_list),
-};
-
-/* Possible clock sources for aclk_266_gscl_sub Mux */
-static struct clk *clk_src_gscl_266_list[] = {
-        [0] = &clk_ext_xtal_mux,
-        [1] = &exynos5_clk_aclk_266.clk,
-};
-
-static struct clksrc_sources clk_src_gscl_266 = {
-        .sources        = clk_src_gscl_266_list,
-        .nr_sources     = ARRAY_SIZE(clk_src_gscl_266_list),
-};
-
-static struct clksrc_clk exynos5_clk_dout_mmc0 = {
-        .clk            = {
-                .name           = "dout_mmc0",
-        },
-        .sources = &exynos5_clkset_group,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 0, .size = 4 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk exynos5_clk_dout_mmc1 = {
-        .clk            = {
-                .name           = "dout_mmc1",
-        },
-        .sources = &exynos5_clkset_group,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 4, .size = 4 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 16, .size = 4 },
-};
-
-static struct clksrc_clk exynos5_clk_dout_mmc2 = {
-        .clk            = {
-                .name           = "dout_mmc2",
-        },
-        .sources = &exynos5_clkset_group,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 8, .size = 4 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk exynos5_clk_dout_mmc3 = {
-        .clk            = {
-                .name           = "dout_mmc3",
-        },
-        .sources = &exynos5_clkset_group,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 12, .size = 4 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 16, .size = 4 },
-};
-
-static struct clksrc_clk exynos5_clk_dout_mmc4 = {
-        .clk            = {
-                .name           = "dout_mmc4",
-        },
-        .sources = &exynos5_clkset_group,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 16, .size = 4 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS3, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk exynos5_clk_sclk_uart0 = {
-        .clk    = {
-                .name           = "uclk1",
-                .devname        = "exynos4210-uart.0",
-                .enable         = exynos5_clksrc_mask_peric0_ctrl,
-                .ctrlbit        = (1 << 0),
-        },
-        .sources = &exynos5_clkset_group,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 0, .size = 4 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk exynos5_clk_sclk_uart1 = {
-        .clk    = {
-                .name           = "uclk1",
-                .devname        = "exynos4210-uart.1",
-                .enable         = exynos5_clksrc_mask_peric0_ctrl,
-                .ctrlbit        = (1 << 4),
-        },
-        .sources = &exynos5_clkset_group,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 4, .size = 4 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 4, .size = 4 },
-};
-
-static struct clksrc_clk exynos5_clk_sclk_uart2 = {
-        .clk    = {
-                .name           = "uclk1",
-                .devname        = "exynos4210-uart.2",
-                .enable         = exynos5_clksrc_mask_peric0_ctrl,
-                .ctrlbit        = (1 << 8),
-        },
-        .sources = &exynos5_clkset_group,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 8, .size = 4 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 8, .size = 4 },
-};
-
-static struct clksrc_clk exynos5_clk_sclk_uart3 = {
-        .clk    = {
-                .name           = "uclk1",
-                .devname        = "exynos4210-uart.3",
-                .enable         = exynos5_clksrc_mask_peric0_ctrl,
-                .ctrlbit        = (1 << 12),
-        },
-        .sources = &exynos5_clkset_group,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 12, .size = 4 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 12, .size = 4 },
-};
-
-static struct clksrc_clk exynos5_clk_sclk_mmc0 = {
-        .clk    = {
-                .name           = "ciu",        /* card interface unit clock */
-                .devname        = "dw_mmc.0",
-                .parent         = &exynos5_clk_dout_mmc0.clk,
-                .enable         = exynos5_clksrc_mask_fsys_ctrl,
-                .ctrlbit        = (1 << 0),
-        },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 8, .size = 8 },
-};
-
-static struct clksrc_clk exynos5_clk_sclk_mmc1 = {
-        .clk    = {
-                .name           = "ciu",
-                .devname        = "dw_mmc.1",
-                .parent         = &exynos5_clk_dout_mmc1.clk,
-                .enable         = exynos5_clksrc_mask_fsys_ctrl,
-                .ctrlbit        = (1 << 4),
-        },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 24, .size = 8 },
-};
-
-static struct clksrc_clk exynos5_clk_sclk_mmc2 = {
-        .clk    = {
-                .name           = "ciu",
-                .devname        = "dw_mmc.2",
-                .parent         = &exynos5_clk_dout_mmc2.clk,
-                .enable         = exynos5_clksrc_mask_fsys_ctrl,
-                .ctrlbit        = (1 << 8),
-        },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 8, .size = 8 },
-};
-
-static struct clksrc_clk exynos5_clk_sclk_mmc3 = {
-        .clk    = {
-                .name           = "ciu",
-                .devname        = "dw_mmc.3",
-                .parent         = &exynos5_clk_dout_mmc3.clk,
-                .enable         = exynos5_clksrc_mask_fsys_ctrl,
-                .ctrlbit        = (1 << 12),
-        },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 24, .size = 8 },
-};
-
-static struct clksrc_clk exynos5_clk_mdout_spi0 = {
-        .clk    = {
-                .name           = "mdout_spi",
-                .devname        = "exynos4210-spi.0",
-        },
-        .sources = &exynos5_clkset_group,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 16, .size = 4 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk exynos5_clk_mdout_spi1 = {
-        .clk    = {
-                .name           = "mdout_spi",
-                .devname        = "exynos4210-spi.1",
-        },
-        .sources = &exynos5_clkset_group,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 20, .size = 4 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 16, .size = 4 },
-};
-
-static struct clksrc_clk exynos5_clk_mdout_spi2 = {
-        .clk    = {
-                .name           = "mdout_spi",
-                .devname        = "exynos4210-spi.2",
-        },
-        .sources = &exynos5_clkset_group,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 24, .size = 4 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk exynos5_clk_sclk_spi0 = {
-        .clk    = {
-                .name           = "sclk_spi",
-                .devname        = "exynos4210-spi.0",
-                .parent         = &exynos5_clk_mdout_spi0.clk,
-                .enable         = exynos5_clksrc_mask_peric1_ctrl,
-                .ctrlbit        = (1 << 16),
-        },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 8, .size = 8 },
-};
-
-static struct clksrc_clk exynos5_clk_sclk_spi1 = {
-        .clk    = {
-                .name           = "sclk_spi",
-                .devname        = "exynos4210-spi.1",
-                .parent         = &exynos5_clk_mdout_spi1.clk,
-                .enable         = exynos5_clksrc_mask_peric1_ctrl,
-                .ctrlbit        = (1 << 20),
-        },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 24, .size = 8 },
-};
-
-static struct clksrc_clk exynos5_clk_sclk_spi2 = {
-        .clk    = {
-                .name           = "sclk_spi",
-                .devname        = "exynos4210-spi.2",
-                .parent         = &exynos5_clk_mdout_spi2.clk,
-                .enable         = exynos5_clksrc_mask_peric1_ctrl,
-                .ctrlbit        = (1 << 24),
-        },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 8, .size = 8 },
-};
-
-static struct clksrc_clk exynos5_clk_sclk_fimd1 = {
-        .clk    = {
-                .name           = "sclk_fimd",
-                .devname        = "exynos5-fb.1",
-                .enable         = exynos5_clksrc_mask_disp1_0_ctrl,
-                .ctrlbit        = (1 << 0),
-        },
-        .sources = &exynos5_clkset_group,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 0, .size = 4 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk exynos5_clksrcs[] = {
-        {
-                .clk    = {
-                        .name           = "aclk_266_gscl",
-                },
-                .sources = &clk_src_gscl_266,
-                .reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 8, .size = 1 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_g3d",
-                        .devname        = "mali-t604.0",
-                        .enable         = exynos5_clk_block_ctrl,
-                        .ctrlbit        = (1 << 1),
-                },
-                .sources = &exynos5_clkset_aclk,
-                .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 20, .size = 1 },
-                .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 24, .size = 3 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_sata",
-                        .devname        = "exynos5-sata",
-                        .enable         = exynos5_clksrc_mask_fsys_ctrl,
-                        .ctrlbit        = (1 << 24),
-                },
-                .sources = &exynos5_clkset_aclk,
-                .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 24, .size = 1 },
-                .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS0, .shift = 20, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_gscl_wrap",
-                        .devname        = "s5p-mipi-csis.0",
-                        .enable         = exynos5_clksrc_mask_gscl_ctrl,
-                        .ctrlbit        = (1 << 24),
-                },
-                .sources = &exynos5_clkset_group,
-                .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 24, .size = 4 },
-                .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 24, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_gscl_wrap",
-                        .devname        = "s5p-mipi-csis.1",
-                        .enable         = exynos5_clksrc_mask_gscl_ctrl,
-                        .ctrlbit        = (1 << 28),
-                },
-                .sources = &exynos5_clkset_group,
-                .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 28, .size = 4 },
-                .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 28, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_cam0",
-                        .enable         = exynos5_clksrc_mask_gscl_ctrl,
-                        .ctrlbit        = (1 << 16),
-                },
-                .sources = &exynos5_clkset_group,
-                .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 16, .size = 4 },
-                .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 16, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_cam1",
-                        .enable         = exynos5_clksrc_mask_gscl_ctrl,
-                        .ctrlbit        = (1 << 20),
-                },
-                .sources = &exynos5_clkset_group,
-                .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 20, .size = 4 },
-                .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 20, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_jpeg",
-                        .parent         = &exynos5_clk_mout_cpll.clk,
-                },
-                .reg_div = { .reg = EXYNOS5_CLKDIV_GEN, .shift = 4, .size = 3 },
-        },
-};
-
-/* Clock initialization code */
-static struct clksrc_clk *exynos5_sysclks[] = {
-        &exynos5_clk_mout_apll,
-        &exynos5_clk_sclk_apll,
-        &exynos5_clk_mout_bpll,
-        &exynos5_clk_mout_bpll_fout,
-        &exynos5_clk_mout_bpll_user,
-        &exynos5_clk_mout_cpll,
-        &exynos5_clk_mout_epll,
-        &exynos5_clk_mout_mpll,
-        &exynos5_clk_mout_mpll_fout,
-        &exynos5_clk_mout_mpll_user,
-        &exynos5_clk_vpllsrc,
-        &exynos5_clk_sclk_vpll,
-        &exynos5_clk_mout_cpu,
-        &exynos5_clk_dout_armclk,
-        &exynos5_clk_dout_arm2clk,
-        &exynos5_clk_cdrex,
-        &exynos5_clk_aclk_400,
-        &exynos5_clk_aclk_333,
-        &exynos5_clk_aclk_266,
-        &exynos5_clk_aclk_200,
-        &exynos5_clk_aclk_166,
-        &exynos5_clk_aclk_300_gscl,
-        &exynos5_clk_mout_aclk_300_gscl,
-        &exynos5_clk_mout_aclk_300_gscl_mid,
-        &exynos5_clk_mout_aclk_300_gscl_mid1,
-        &exynos5_clk_aclk_66_pre,
-        &exynos5_clk_aclk_66,
-        &exynos5_clk_dout_mmc0,
-        &exynos5_clk_dout_mmc1,
-        &exynos5_clk_dout_mmc2,
-        &exynos5_clk_dout_mmc3,
-        &exynos5_clk_dout_mmc4,
-        &exynos5_clk_aclk_acp,
-        &exynos5_clk_pclk_acp,
-        &exynos5_clk_sclk_spi0,
-        &exynos5_clk_sclk_spi1,
-        &exynos5_clk_sclk_spi2,
-        &exynos5_clk_mdout_spi0,
-        &exynos5_clk_mdout_spi1,
-        &exynos5_clk_mdout_spi2,
-        &exynos5_clk_sclk_fimd1,
-};
-
-static struct clk *exynos5_clk_cdev[] = {
-        &exynos5_clk_pdma0,
-        &exynos5_clk_pdma1,
-        &exynos5_clk_mdma1,
-        &exynos5_clk_fimd1,
-};
-
-static struct clksrc_clk *exynos5_clksrc_cdev[] = {
-        &exynos5_clk_sclk_uart0,
-        &exynos5_clk_sclk_uart1,
-        &exynos5_clk_sclk_uart2,
-        &exynos5_clk_sclk_uart3,
-        &exynos5_clk_sclk_mmc0,
-        &exynos5_clk_sclk_mmc1,
-        &exynos5_clk_sclk_mmc2,
-        &exynos5_clk_sclk_mmc3,
-};
-
-static struct clk_lookup exynos5_clk_lookup[] = {
-        CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &exynos5_clk_sclk_uart0.clk),
-        CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos5_clk_sclk_uart1.clk),
-        CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos5_clk_sclk_uart2.clk),
-        CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos5_clk_sclk_uart3.clk),
-        CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos5_clk_sclk_mmc0.clk),
-        CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk),
-        CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk),
-        CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk),
-        CLKDEV_INIT("exynos4210-spi.0", "spi_busclk0", &exynos5_clk_sclk_spi0.clk),
-        CLKDEV_INIT("exynos4210-spi.1", "spi_busclk0", &exynos5_clk_sclk_spi1.clk),
-        CLKDEV_INIT("exynos4210-spi.2", "spi_busclk0", &exynos5_clk_sclk_spi2.clk),
-        CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0),
-        CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1),
-        CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1),
-        CLKDEV_INIT("exynos5-fb.1", "lcd", &exynos5_clk_fimd1),
-};
-
-static unsigned long exynos5_epll_get_rate(struct clk *clk)
-{
-        return clk->rate;
-}
-
-static struct clk *exynos5_clks[] __initdata = {
-        &exynos5_clk_sclk_hdmi27m,
-        &exynos5_clk_sclk_hdmiphy,
-        &clk_fout_bpll,
-        &clk_fout_bpll_div2,
-        &clk_fout_cpll,
-        &clk_fout_mpll_div2,
-        &exynos5_clk_armclk,
-};
-
-static u32 epll_div[][6] = {
-        { 192000000, 0, 48, 3, 1, 0 },
-        { 180000000, 0, 45, 3, 1, 0 },
-        {  73728000, 1, 73, 3, 3, 47710 },
-        {  67737600, 1, 90, 4, 3, 20762 },
-        {  49152000, 0, 49, 3, 3, 9961 },
-        {  45158400, 0, 45, 3, 3, 10381 },
-        { 180633600, 0, 45, 3, 1, 10381 },
-};
-
-static int exynos5_epll_set_rate(struct clk *clk, unsigned long rate)
-{
-        unsigned int epll_con, epll_con_k;
-        unsigned int i;
-        unsigned int tmp;
-        unsigned int epll_rate;
-        unsigned int locktime;
-        unsigned int lockcnt;
-
-        /* Return if nothing changed */
-        if (clk->rate == rate)
-                return 0;
-
-        if (clk->parent)
-                epll_rate = clk_get_rate(clk->parent);
-        else
-                epll_rate = clk_ext_xtal_mux.rate;
-
-        if (epll_rate != 24000000) {
-                pr_err("Invalid Clock : recommended clock is 24MHz.\n");
-                return -EINVAL;
-        }
-
-        epll_con = __raw_readl(EXYNOS5_EPLL_CON0);
-        epll_con &= ~(0x1 << 27 | \
-                        PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT |   \
-                        PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT | \
-                        PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
-
-        for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
-                if (epll_div[i][0] == rate) {
-                        epll_con_k = epll_div[i][5] << 0;
-                        epll_con |= epll_div[i][1] << 27;
-                        epll_con |= epll_div[i][2] << PLL46XX_MDIV_SHIFT;
-                        epll_con |= epll_div[i][3] << PLL46XX_PDIV_SHIFT;
-                        epll_con |= epll_div[i][4] << PLL46XX_SDIV_SHIFT;
-                        break;
-                }
-        }
-
-        if (i == ARRAY_SIZE(epll_div)) {
-                printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n",
-                                __func__);
-                return -EINVAL;
-        }
-
-        epll_rate /= 1000000;
-
-        /* 3000 max_cycls : specification data */
-        locktime = 3000 / epll_rate * epll_div[i][3];
-        lockcnt = locktime * 10000 / (10000 / epll_rate);
-
-        __raw_writel(lockcnt, EXYNOS5_EPLL_LOCK);
-
-        __raw_writel(epll_con, EXYNOS5_EPLL_CON0);
-        __raw_writel(epll_con_k, EXYNOS5_EPLL_CON1);
-
-        do {
-                tmp = __raw_readl(EXYNOS5_EPLL_CON0);
-        } while (!(tmp & 0x1 << EXYNOS5_EPLLCON0_LOCKED_SHIFT));
-
-        clk->rate = rate;
-
-        return 0;
-}
-
-static struct clk_ops exynos5_epll_ops = {
-        .get_rate = exynos5_epll_get_rate,
-        .set_rate = exynos5_epll_set_rate,
-};
-
-static int xtal_rate;
-
-static unsigned long exynos5_fout_apll_get_rate(struct clk *clk)
-{
-        return s5p_get_pll35xx(xtal_rate, __raw_readl(EXYNOS5_APLL_CON0));
-}
-
-static struct clk_ops exynos5_fout_apll_ops = {
-        .get_rate = exynos5_fout_apll_get_rate,
-};
-
-#ifdef CONFIG_PM
-static int exynos5_clock_suspend(void)
-{
-        s3c_pm_do_save(exynos5_clock_save, ARRAY_SIZE(exynos5_clock_save));
-
-        return 0;
-}
-
-static void exynos5_clock_resume(void)
-{
-        s3c_pm_do_restore_core(exynos5_clock_save, ARRAY_SIZE(exynos5_clock_save));
-}
-#else
-#define exynos5_clock_suspend NULL
-#define exynos5_clock_resume NULL
-#endif
-
-static struct syscore_ops exynos5_clock_syscore_ops = {
-        .suspend        = exynos5_clock_suspend,
-        .resume         = exynos5_clock_resume,
-};
-
-void __init_or_cpufreq exynos5_setup_clocks(void)
-{
-        struct clk *xtal_clk;
-        unsigned long apll;
-        unsigned long bpll;
-        unsigned long cpll;
-        unsigned long mpll;
-        unsigned long epll;
-        unsigned long vpll;
-        unsigned long vpllsrc;
-        unsigned long xtal;
-        unsigned long armclk;
-        unsigned long mout_cdrex;
-        unsigned long aclk_400;
-        unsigned long aclk_333;
-        unsigned long aclk_266;
-        unsigned long aclk_200;
-        unsigned long aclk_166;
-        unsigned long aclk_66;
-        unsigned int ptr;
-
-        printk(KERN_DEBUG "%s: registering clocks\n", __func__);
-
-        xtal_clk = clk_get(NULL, "xtal");
-        BUG_ON(IS_ERR(xtal_clk));
-
-        xtal = clk_get_rate(xtal_clk);
-
-        xtal_rate = xtal;
-
-        clk_put(xtal_clk);
-
-        printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
-
-        apll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_APLL_CON0));
-        bpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_BPLL_CON0));
-        cpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_CPLL_CON0));
-        mpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_MPLL_CON0));
-        epll = s5p_get_pll36xx(xtal, __raw_readl(EXYNOS5_EPLL_CON0),
-                        __raw_readl(EXYNOS5_EPLL_CON1));
-
-        vpllsrc = clk_get_rate(&exynos5_clk_vpllsrc.clk);
-        vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(EXYNOS5_VPLL_CON0),
-                        __raw_readl(EXYNOS5_VPLL_CON1));
-
-        clk_fout_apll.ops = &exynos5_fout_apll_ops;
-        clk_fout_bpll.rate = bpll;
-        clk_fout_bpll_div2.rate = bpll >> 1;
-        clk_fout_cpll.rate = cpll;
-        clk_fout_mpll.rate = mpll;
-        clk_fout_mpll_div2.rate = mpll >> 1;
-        clk_fout_epll.rate = epll;
-        clk_fout_vpll.rate = vpll;
-
-        printk(KERN_INFO "EXYNOS5: PLL settings, A=%ld, B=%ld, C=%ld\n"
-                        "M=%ld, E=%ld V=%ld",
-                        apll, bpll, cpll, mpll, epll, vpll);
-
-        armclk = clk_get_rate(&exynos5_clk_armclk);
-        mout_cdrex = clk_get_rate(&exynos5_clk_cdrex.clk);
-
-        aclk_400 = clk_get_rate(&exynos5_clk_aclk_400.clk);
-        aclk_333 = clk_get_rate(&exynos5_clk_aclk_333.clk);
-        aclk_266 = clk_get_rate(&exynos5_clk_aclk_266.clk);
-        aclk_200 = clk_get_rate(&exynos5_clk_aclk_200.clk);
-        aclk_166 = clk_get_rate(&exynos5_clk_aclk_166.clk);
-        aclk_66 = clk_get_rate(&exynos5_clk_aclk_66.clk);
-
-        printk(KERN_INFO "EXYNOS5: ARMCLK=%ld, CDREX=%ld, ACLK400=%ld\n"
-                        "ACLK333=%ld, ACLK266=%ld, ACLK200=%ld\n"
-                        "ACLK166=%ld, ACLK66=%ld\n",
-                        armclk, mout_cdrex, aclk_400,
-                        aclk_333, aclk_266, aclk_200,
-                        aclk_166, aclk_66);
-
-
-        clk_fout_epll.ops = &exynos5_epll_ops;
-
-        if (clk_set_parent(&exynos5_clk_mout_epll.clk, &clk_fout_epll))
-                printk(KERN_ERR "Unable to set parent %s of clock %s.\n",
-                                clk_fout_epll.name, exynos5_clk_mout_epll.clk.name);
-
-        clk_set_rate(&exynos5_clk_sclk_apll.clk, 100000000);
-        clk_set_rate(&exynos5_clk_aclk_266.clk, 300000000);
-
-        clk_set_rate(&exynos5_clk_aclk_acp.clk, 267000000);
-        clk_set_rate(&exynos5_clk_pclk_acp.clk, 134000000);
-
-        for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clksrcs); ptr++)
-                s3c_set_clksrc(&exynos5_clksrcs[ptr], true);
-}
-
-void __init exynos5_register_clocks(void)
-{
-        int ptr;
-
-        s3c24xx_register_clocks(exynos5_clks, ARRAY_SIZE(exynos5_clks));
-
-        for (ptr = 0; ptr < ARRAY_SIZE(exynos5_sysclks); ptr++)
-                s3c_register_clksrc(exynos5_sysclks[ptr], 1);
-
-        for (ptr = 0; ptr < ARRAY_SIZE(exynos5_sclk_tv); ptr++)
-                s3c_register_clksrc(exynos5_sclk_tv[ptr], 1);
-
-        for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clksrc_cdev); ptr++)
-                s3c_register_clksrc(exynos5_clksrc_cdev[ptr], 1);
-
-        s3c_register_clksrc(exynos5_clksrcs, ARRAY_SIZE(exynos5_clksrcs));
-        s3c_register_clocks(exynos5_init_clocks_on, ARRAY_SIZE(exynos5_init_clocks_on));
-
-        s3c24xx_register_clocks(exynos5_clk_cdev, ARRAY_SIZE(exynos5_clk_cdev));
-        for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clk_cdev); ptr++)
-                s3c_disable_clocks(exynos5_clk_cdev[ptr], 1);
-
-        s3c_register_clocks(exynos5_init_clocks_off, ARRAY_SIZE(exynos5_init_clocks_off));
-        s3c_disable_clocks(exynos5_init_clocks_off, ARRAY_SIZE(exynos5_init_clocks_off));
-        clkdev_add_table(exynos5_clk_lookup, ARRAY_SIZE(exynos5_clk_lookup));
-
-        register_syscore_ops(&exynos5_clock_syscore_ops);
-        s3c_pwmclk_init();
-}
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index bdd957978d9b..d3efd6768ff8 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -25,6 +25,8 @@
 #include <linux/irqdomain.h>
 #include <linux/irqchip.h>
 #include <linux/of_address.h>
+#include <linux/clocksource.h>
+#include <linux/clk-provider.h>
 #include <linux/irqchip/arm-gic.h>
 
 #include <asm/proc-fns.h>
@@ -39,7 +41,6 @@
 #include <mach/regs-gpio.h>
 
 #include <plat/cpu.h>
-#include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/pm.h>
 #include <plat/sdhci.h>
@@ -65,17 +66,16 @@ static const char name_exynos5440[] = "EXYNOS5440";
 static void exynos4_map_io(void);
 static void exynos5_map_io(void);
 static void exynos5440_map_io(void);
-static void exynos4_init_clocks(int xtal);
-static void exynos5_init_clocks(int xtal);
 static void exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no);
 static int exynos_init(void);
 
+unsigned long xxti_f = 0, xusbxti_f = 0;
+
 static struct cpu_table cpu_ids[] __initdata = {
         {
                 .idcode         = EXYNOS4210_CPU_ID,
                 .idmask         = EXYNOS4_CPU_MASK,
                 .map_io         = exynos4_map_io,
-                .init_clocks    = exynos4_init_clocks,
                 .init_uarts     = exynos4_init_uarts,
                 .init           = exynos_init,
                 .name           = name_exynos4210,
@@ -83,7 +83,6 @@ static struct cpu_table cpu_ids[] __initdata = {
                 .idcode         = EXYNOS4212_CPU_ID,
                 .idmask         = EXYNOS4_CPU_MASK,
                 .map_io         = exynos4_map_io,
-                .init_clocks    = exynos4_init_clocks,
                 .init_uarts     = exynos4_init_uarts,
                 .init           = exynos_init,
                 .name           = name_exynos4212,
@@ -91,7 +90,6 @@ static struct cpu_table cpu_ids[] __initdata = {
                 .idcode         = EXYNOS4412_CPU_ID,
                 .idmask         = EXYNOS4_CPU_MASK,
                 .map_io         = exynos4_map_io,
-                .init_clocks    = exynos4_init_clocks,
                 .init_uarts     = exynos4_init_uarts,
                 .init           = exynos_init,
                 .name           = name_exynos4412,
@@ -99,7 +97,6 @@ static struct cpu_table cpu_ids[] __initdata = {
                 .idcode         = EXYNOS5250_SOC_ID,
                 .idmask         = EXYNOS5_SOC_MASK,
                 .map_io         = exynos5_map_io,
-                .init_clocks    = exynos5_init_clocks,
                 .init           = exynos_init,
                 .name           = name_exynos5250,
         }, {
@@ -257,11 +254,6 @@ static struct map_desc exynos5_iodesc[] __initdata = {
                 .length         = SZ_4K,
                 .type           = MT_DEVICE,
         }, {
-                .virtual        = (unsigned long)S5P_VA_SYSTIMER,
-                .pfn            = __phys_to_pfn(EXYNOS5_PA_SYSTIMER),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        }, {
                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SYSRAM),
                 .length         = SZ_4K,
@@ -402,43 +394,26 @@ static void __init exynos5_map_io(void)
         iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
 }
 
-static void __init exynos4_init_clocks(int xtal)
-{
-        printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
-
-        s3c24xx_register_baseclocks(xtal);
-        s5p_register_clocks(xtal);
-
-        if (soc_is_exynos4210())
-                exynos4210_register_clocks();
-        else if (soc_is_exynos4212() || soc_is_exynos4412())
-                exynos4212_register_clocks();
-
-        exynos4_register_clocks();
-        exynos4_setup_clocks();
-}
-
 static void __init exynos5440_map_io(void)
 {
         iotable_init(exynos5440_iodesc0, ARRAY_SIZE(exynos5440_iodesc0));
 }
 
-static void __init exynos5_init_clocks(int xtal)
+void __init exynos_init_time(void)
 {
-        printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
-
-        /* EXYNOS5440 can support only common clock framework */
-
-        if (soc_is_exynos5440())
-                return;
-
-#ifdef CONFIG_SOC_EXYNOS5250
-        s3c24xx_register_baseclocks(xtal);
-        s5p_register_clocks(xtal);
-
-        exynos5_register_clocks();
-        exynos5_setup_clocks();
+        if (of_have_populated_dt()) {
+#ifdef CONFIG_OF
+                of_clk_init(NULL);
+                clocksource_of_init();
 #endif
+        } else {
+                /* todo: remove after migrating legacy E4 platforms to dt */
+#ifdef CONFIG_ARCH_EXYNOS4
+                exynos4_clk_init(NULL);
+                exynos4_clk_register_fixed_ext(xxti_f, xusbxti_f);
+#endif
+                mct_init();
+        }
 }
 
 void __init exynos4_init_irq(void)
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index 9339bb8954be..cb89ab886950 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -12,7 +12,11 @@
 #ifndef __ARCH_ARM_MACH_EXYNOS_COMMON_H
 #define __ARCH_ARM_MACH_EXYNOS_COMMON_H
 
-extern void exynos4_timer_init(void);
+#include <linux/of.h>
+
+extern void mct_init(void);
+void exynos_init_time(void);
+extern unsigned long xxti_f, xusbxti_f;
 
 struct map_desc;
 void exynos_init_io(struct map_desc *mach_desc, int size);
@@ -22,6 +26,10 @@ void exynos4_restart(char mode, const char *cmd);
 void exynos5_restart(char mode, const char *cmd);
 void exynos_init_late(void);
 
+/* ToDo: remove these after migrating legacy exynos4 platforms to dt */
+void exynos4_clk_init(struct device_node *np);
+void exynos4_clk_register_fixed_ext(unsigned long, unsigned long);
+
 #ifdef CONFIG_PM_GENERIC_DOMAINS
 int exynos_pm_late_initcall(void);
 #else
diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
index 1f4dc35cd4b9..c0e75d8dd737 100644
--- a/arch/arm/mach-exynos/include/mach/irqs.h
+++ b/arch/arm/mach-exynos/include/mach/irqs.h
@@ -30,8 +30,6 @@
 
 /* For EXYNOS4 and EXYNOS5 */
 
-#define EXYNOS_IRQ_MCT_LOCALTIMER       IRQ_PPI(12)
-
 #define EXYNOS_IRQ_EINT16_31            IRQ_SPI(32)
 
 /* For EXYNOS4 SoCs */
@@ -323,8 +321,6 @@
 #define EXYNOS5_IRQ_CEC                 IRQ_SPI(114)
 #define EXYNOS5_IRQ_SATA                IRQ_SPI(115)
 
-#define EXYNOS5_IRQ_MCT_L0              IRQ_SPI(120)
-#define EXYNOS5_IRQ_MCT_L1              IRQ_SPI(121)
 #define EXYNOS5_IRQ_MMC44               IRQ_SPI(123)
 #define EXYNOS5_IRQ_MDMA1               IRQ_SPI(124)
 #define EXYNOS5_IRQ_FIMC_LITE0          IRQ_SPI(125)
@@ -419,8 +415,6 @@
 #define EXYNOS5_IRQ_PMU_CPU1            COMBINER_IRQ(22, 4)
 
 #define EXYNOS5_IRQ_EINT0               COMBINER_IRQ(23, 0)
-#define EXYNOS5_IRQ_MCT_G0              COMBINER_IRQ(23, 3)
-#define EXYNOS5_IRQ_MCT_G1              COMBINER_IRQ(23, 4)
 
 #define EXYNOS5_IRQ_EINT1               COMBINER_IRQ(24, 0)
 #define EXYNOS5_IRQ_SYSMMU_LITE1_0      COMBINER_IRQ(24, 1)
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index 1df6abbf53b8..7f99b7b187d6 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -65,7 +65,6 @@
 #define EXYNOS5_PA_CMU                  0x10010000
 
 #define EXYNOS4_PA_SYSTIMER             0x10050000
-#define EXYNOS5_PA_SYSTIMER             0x101C0000
 
 #define EXYNOS4_PA_WATCHDOG             0x10060000
 #define EXYNOS5_PA_WATCHDOG             0x101D0000
diff --git a/arch/arm/mach-exynos/include/mach/regs-clock.h b/arch/arm/mach-exynos/include/mach/regs-clock.h
index d36ad76ad6a4..20fbbdddd105 100644
--- a/arch/arm/mach-exynos/include/mach/regs-clock.h
+++ b/arch/arm/mach-exynos/include/mach/regs-clock.h
@@ -256,113 +256,6 @@
 #define EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT          (0)
 #define EXYNOS4_CLKDIV_CAM1_JPEG_MASK           (0xf << EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT)
 
-/* For EXYNOS5250 */
-
-#define EXYNOS5_APLL_LOCK                       EXYNOS_CLKREG(0x00000)
-#define EXYNOS5_APLL_CON0                       EXYNOS_CLKREG(0x00100)
-#define EXYNOS5_CLKSRC_CPU                      EXYNOS_CLKREG(0x00200)
-#define EXYNOS5_CLKMUX_STATCPU                  EXYNOS_CLKREG(0x00400)
-#define EXYNOS5_CLKDIV_CPU0                     EXYNOS_CLKREG(0x00500)
-#define EXYNOS5_CLKDIV_CPU1                     EXYNOS_CLKREG(0x00504)
-#define EXYNOS5_CLKDIV_STATCPU0                 EXYNOS_CLKREG(0x00600)
-#define EXYNOS5_CLKDIV_STATCPU1                 EXYNOS_CLKREG(0x00604)
-
-#define EXYNOS5_PWR_CTRL1                       EXYNOS_CLKREG(0x01020)
-#define EXYNOS5_PWR_CTRL2                       EXYNOS_CLKREG(0x01024)
-
-#define EXYNOS5_MPLL_CON0                       EXYNOS_CLKREG(0x04100)
-#define EXYNOS5_CLKSRC_CORE1                    EXYNOS_CLKREG(0x04204)
-
-#define EXYNOS5_CLKGATE_IP_CORE                 EXYNOS_CLKREG(0x04900)
-
-#define EXYNOS5_CLKDIV_ACP                      EXYNOS_CLKREG(0x08500)
-
-#define EXYNOS5_EPLL_CON0                       EXYNOS_CLKREG(0x10130)
-#define EXYNOS5_EPLL_CON1                       EXYNOS_CLKREG(0x10134)
-#define EXYNOS5_EPLL_CON2                       EXYNOS_CLKREG(0x10138)
-#define EXYNOS5_VPLL_CON0                       EXYNOS_CLKREG(0x10140)
-#define EXYNOS5_VPLL_CON1                       EXYNOS_CLKREG(0x10144)
-#define EXYNOS5_VPLL_CON2                       EXYNOS_CLKREG(0x10148)
-#define EXYNOS5_CPLL_CON0                       EXYNOS_CLKREG(0x10120)
-
-#define EXYNOS5_CLKSRC_TOP0                     EXYNOS_CLKREG(0x10210)
-#define EXYNOS5_CLKSRC_TOP1                     EXYNOS_CLKREG(0x10214)
-#define EXYNOS5_CLKSRC_TOP2                     EXYNOS_CLKREG(0x10218)
-#define EXYNOS5_CLKSRC_TOP3                     EXYNOS_CLKREG(0x1021C)
-#define EXYNOS5_CLKSRC_GSCL                     EXYNOS_CLKREG(0x10220)
-#define EXYNOS5_CLKSRC_DISP1_0                  EXYNOS_CLKREG(0x1022C)
-#define EXYNOS5_CLKSRC_MAUDIO                   EXYNOS_CLKREG(0x10240)
-#define EXYNOS5_CLKSRC_FSYS                     EXYNOS_CLKREG(0x10244)
-#define EXYNOS5_CLKSRC_PERIC0                   EXYNOS_CLKREG(0x10250)
-#define EXYNOS5_CLKSRC_PERIC1                   EXYNOS_CLKREG(0x10254)
-#define EXYNOS5_SCLK_SRC_ISP                    EXYNOS_CLKREG(0x10270)
-
-#define EXYNOS5_CLKSRC_MASK_TOP                 EXYNOS_CLKREG(0x10310)
-#define EXYNOS5_CLKSRC_MASK_GSCL                EXYNOS_CLKREG(0x10320)
-#define EXYNOS5_CLKSRC_MASK_DISP1_0             EXYNOS_CLKREG(0x1032C)
-#define EXYNOS5_CLKSRC_MASK_MAUDIO              EXYNOS_CLKREG(0x10334)
-#define EXYNOS5_CLKSRC_MASK_FSYS                EXYNOS_CLKREG(0x10340)
-#define EXYNOS5_CLKSRC_MASK_PERIC0              EXYNOS_CLKREG(0x10350)
-#define EXYNOS5_CLKSRC_MASK_PERIC1              EXYNOS_CLKREG(0x10354)
-
-#define EXYNOS5_CLKDIV_TOP0                     EXYNOS_CLKREG(0x10510)
-#define EXYNOS5_CLKDIV_TOP1                     EXYNOS_CLKREG(0x10514)
-#define EXYNOS5_CLKDIV_GSCL                     EXYNOS_CLKREG(0x10520)
-#define EXYNOS5_CLKDIV_DISP1_0                  EXYNOS_CLKREG(0x1052C)
-#define EXYNOS5_CLKDIV_GEN                      EXYNOS_CLKREG(0x1053C)
-#define EXYNOS5_CLKDIV_MAUDIO                   EXYNOS_CLKREG(0x10544)
-#define EXYNOS5_CLKDIV_FSYS0                    EXYNOS_CLKREG(0x10548)
-#define EXYNOS5_CLKDIV_FSYS1                    EXYNOS_CLKREG(0x1054C)
-#define EXYNOS5_CLKDIV_FSYS2                    EXYNOS_CLKREG(0x10550)
-#define EXYNOS5_CLKDIV_FSYS3                    EXYNOS_CLKREG(0x10554)
-#define EXYNOS5_CLKDIV_PERIC0                   EXYNOS_CLKREG(0x10558)
-#define EXYNOS5_CLKDIV_PERIC1                   EXYNOS_CLKREG(0x1055C)
-#define EXYNOS5_CLKDIV_PERIC2                   EXYNOS_CLKREG(0x10560)
-#define EXYNOS5_CLKDIV_PERIC3                   EXYNOS_CLKREG(0x10564)
-#define EXYNOS5_CLKDIV_PERIC4                   EXYNOS_CLKREG(0x10568)
-#define EXYNOS5_CLKDIV_PERIC5                   EXYNOS_CLKREG(0x1056C)
-#define EXYNOS5_SCLK_DIV_ISP                    EXYNOS_CLKREG(0x10580)
-
-#define EXYNOS5_CLKGATE_IP_ACP                  EXYNOS_CLKREG(0x08800)
-#define EXYNOS5_CLKGATE_IP_ISP0                 EXYNOS_CLKREG(0x0C800)
-#define EXYNOS5_CLKGATE_IP_ISP1                 EXYNOS_CLKREG(0x0C804)
-#define EXYNOS5_CLKGATE_IP_GSCL                 EXYNOS_CLKREG(0x10920)
-#define EXYNOS5_CLKGATE_IP_DISP1                EXYNOS_CLKREG(0x10928)
-#define EXYNOS5_CLKGATE_IP_MFC                  EXYNOS_CLKREG(0x1092C)
-#define EXYNOS5_CLKGATE_IP_G3D                  EXYNOS_CLKREG(0x10930)
-#define EXYNOS5_CLKGATE_IP_GEN                  EXYNOS_CLKREG(0x10934)
-#define EXYNOS5_CLKGATE_IP_FSYS                 EXYNOS_CLKREG(0x10944)
-#define EXYNOS5_CLKGATE_IP_GPS                  EXYNOS_CLKREG(0x1094C)
-#define EXYNOS5_CLKGATE_IP_PERIC                EXYNOS_CLKREG(0x10950)
-#define EXYNOS5_CLKGATE_IP_PERIS                EXYNOS_CLKREG(0x10960)
-#define EXYNOS5_CLKGATE_BLOCK                   EXYNOS_CLKREG(0x10980)
-
-#define EXYNOS5_BPLL_CON0                       EXYNOS_CLKREG(0x20110)
-#define EXYNOS5_CLKSRC_CDREX                    EXYNOS_CLKREG(0x20200)
-#define EXYNOS5_CLKDIV_CDREX                    EXYNOS_CLKREG(0x20500)
-
-#define EXYNOS5_PLL_DIV2_SEL                    EXYNOS_CLKREG(0x20A24)
-
-#define EXYNOS5_EPLL_LOCK                       EXYNOS_CLKREG(0x10030)
-
-#define EXYNOS5_EPLLCON0_LOCKED_SHIFT           (29)
-
-#define PWR_CTRL1_CORE2_DOWN_RATIO              (7 << 28)
-#define PWR_CTRL1_CORE1_DOWN_RATIO              (7 << 16)
-#define PWR_CTRL1_DIV2_DOWN_EN                  (1 << 9)
-#define PWR_CTRL1_DIV1_DOWN_EN                  (1 << 8)
-#define PWR_CTRL1_USE_CORE1_WFE                 (1 << 5)
-#define PWR_CTRL1_USE_CORE0_WFE                 (1 << 4)
-#define PWR_CTRL1_USE_CORE1_WFI                 (1 << 1)
-#define PWR_CTRL1_USE_CORE0_WFI                 (1 << 0)
-
-#define PWR_CTRL2_DIV2_UP_EN                    (1 << 25)
-#define PWR_CTRL2_DIV1_UP_EN                    (1 << 24)
-#define PWR_CTRL2_DUR_STANDBY2_VAL              (1 << 16)
-#define PWR_CTRL2_DUR_STANDBY1_VAL              (1 << 8)
-#define PWR_CTRL2_CORE2_UP_RATIO                (1 << 4)
-#define PWR_CTRL2_CORE1_UP_RATIO                (1 << 0)
-
 /* Compatibility defines and inclusion */
 
 #include <mach/regs-pmu.h>
diff --git a/arch/arm/mach-exynos/include/mach/regs-mct.h b/arch/arm/mach-exynos/include/mach/regs-mct.h
deleted file mode 100644
index 80dd02ad6d61..000000000000
--- a/arch/arm/mach-exynos/include/mach/regs-mct.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/* arch/arm/mach-exynos4/include/mach/regs-mct.h
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * EXYNOS4 MCT configutation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_REGS_MCT_H
-#define __ASM_ARCH_REGS_MCT_H __FILE__
-
-#include <mach/map.h>
-
-#define EXYNOS4_MCTREG(x)               (S5P_VA_SYSTIMER + (x))
-
-#define EXYNOS4_MCT_G_CNT_L             EXYNOS4_MCTREG(0x100)
-#define EXYNOS4_MCT_G_CNT_U             EXYNOS4_MCTREG(0x104)
-#define EXYNOS4_MCT_G_CNT_WSTAT         EXYNOS4_MCTREG(0x110)
-
-#define EXYNOS4_MCT_G_COMP0_L           EXYNOS4_MCTREG(0x200)
-#define EXYNOS4_MCT_G_COMP0_U           EXYNOS4_MCTREG(0x204)
-#define EXYNOS4_MCT_G_COMP0_ADD_INCR    EXYNOS4_MCTREG(0x208)
-
-#define EXYNOS4_MCT_G_TCON              EXYNOS4_MCTREG(0x240)
-
-#define EXYNOS4_MCT_G_INT_CSTAT         EXYNOS4_MCTREG(0x244)
-#define EXYNOS4_MCT_G_INT_ENB           EXYNOS4_MCTREG(0x248)
-#define EXYNOS4_MCT_G_WSTAT             EXYNOS4_MCTREG(0x24C)
-
-#define _EXYNOS4_MCT_L_BASE             EXYNOS4_MCTREG(0x300)
-#define EXYNOS4_MCT_L_BASE(x)           (_EXYNOS4_MCT_L_BASE + (0x100 * x))
-#define EXYNOS4_MCT_L_MASK              (0xffffff00)
-
-#define MCT_L_TCNTB_OFFSET              (0x00)
-#define MCT_L_ICNTB_OFFSET              (0x08)
-#define MCT_L_TCON_OFFSET               (0x20)
-#define MCT_L_INT_CSTAT_OFFSET          (0x30)
-#define MCT_L_INT_ENB_OFFSET            (0x34)
-#define MCT_L_WSTAT_OFFSET              (0x40)
-
-#define MCT_G_TCON_START                (1 << 8)
-#define MCT_G_TCON_COMP0_AUTO_INC       (1 << 1)
-#define MCT_G_TCON_COMP0_ENABLE         (1 << 0)
-
-#define MCT_L_TCON_INTERVAL_MODE        (1 << 2)
-#define MCT_L_TCON_INT_START            (1 << 1)
-#define MCT_L_TCON_TIMER_START          (1 << 0)
-
-#endif /* __ASM_ARCH_REGS_MCT_H */
diff --git a/arch/arm/mach-exynos/mach-armlex4210.c b/arch/arm/mach-exynos/mach-armlex4210.c
index 685f29173afa..2c23b659ae3e 100644
--- a/arch/arm/mach-exynos/mach-armlex4210.c
+++ b/arch/arm/mach-exynos/mach-armlex4210.c
@@ -177,7 +177,6 @@ static void __init armlex4210_smsc911x_init(void)
 static void __init armlex4210_map_io(void)
 {
         exynos_init_io(NULL, 0);
-        s3c24xx_init_clocks(24000000);
         s3c24xx_init_uarts(armlex4210_uartcfgs,
                            ARRAY_SIZE(armlex4210_uartcfgs));
 }
@@ -202,6 +201,6 @@ MACHINE_START(ARMLEX4210, "ARMLEX4210")
         .map_io         = armlex4210_map_io,
         .init_machine   = armlex4210_machine_init,
         .init_late      = exynos_init_late,
-        .init_time      = exynos4_timer_init,
+        .init_time      = exynos_init_time,
         .restart        = exynos4_restart,
 MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-exynos4-dt.c b/arch/arm/mach-exynos/mach-exynos4-dt.c
index 3358088c822a..ac27f3cd121f 100644
--- a/arch/arm/mach-exynos/mach-exynos4-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos4-dt.c
@@ -11,121 +11,26 @@
  * published by the Free Software Foundation.
 */
 
+#include <linux/kernel.h>
 #include <linux/of_platform.h>
+#include <linux/of_fdt.h>
 #include <linux/serial_core.h>
+#include <linux/memblock.h>
+#include <linux/clocksource.h>
 
 #include <asm/mach/arch.h>
-#include <mach/map.h>
-
-#include <plat/cpu.h>
-#include <plat/regs-serial.h>
+#include <plat/mfc.h>
 
 #include "common.h"
 
-/*
- * The following lookup table is used to override device names when devices
- * are registered from device tree. This is temporarily added to enable
- * device tree support addition for the Exynos4 architecture.
- *
- * For drivers that require platform data to be provided from the machine
- * file, a platform data pointer can also be supplied along with the
- * devices names. Usually, the platform data elements that cannot be parsed
- * from the device tree by the drivers (example: function pointers) are
- * supplied. But it should be noted that this is a temporary mechanism and
- * at some point, the drivers should be capable of parsing all the platform
- * data from the device tree.
- */
-static const struct of_dev_auxdata exynos4_auxdata_lookup[] __initconst = {
-        OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART0,
-                                "exynos4210-uart.0", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART1,
-                                "exynos4210-uart.1", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART2,
-                                "exynos4210-uart.2", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART3,
-                                "exynos4210-uart.3", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(0),
-                                "exynos4-sdhci.0", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(1),
-                                "exynos4-sdhci.1", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(2),
-                                "exynos4-sdhci.2", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(3),
-                                "exynos4-sdhci.3", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(0),
-                                "s3c2440-i2c.0", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(1),
-                                "s3c2440-i2c.1", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(2),
-                                "s3c2440-i2c.2", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(3),
-                                "s3c2440-i2c.3", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(4),
-                                "s3c2440-i2c.4", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(5),
-                                "s3c2440-i2c.5", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(6),
-                                "s3c2440-i2c.6", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(7),
-                                "s3c2440-i2c.7", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS4_PA_SPI0,
-                                "exynos4210-spi.0", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS4_PA_SPI1,
-                                "exynos4210-spi.1", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS4_PA_SPI2,
-                                "exynos4210-spi.2", NULL),
-        OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA0, "dma-pl330.0", NULL),
-        OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA1, "dma-pl330.1", NULL),
-        OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_MDMA1, "dma-pl330.2", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-tmu", EXYNOS4_PA_TMU,
-                                "exynos-tmu", NULL),
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13620000,
-                        "exynos-sysmmu.0", NULL), /* MFC_L */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13630000,
-                        "exynos-sysmmu.1", NULL), /* MFC_R */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13E20000,
-                        "exynos-sysmmu.2", NULL), /* TV */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A60000,
-                        "exynos-sysmmu.3", NULL), /* JPEG */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x12A30000,
-                        "exynos-sysmmu.4", NULL), /* ROTATOR */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A20000,
-                        "exynos-sysmmu.5", NULL), /* FIMC0 */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A30000,
-                        "exynos-sysmmu.6", NULL), /* FIMC1 */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A40000,
-                        "exynos-sysmmu.7", NULL), /* FIMC2 */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A50000,
-                        "exynos-sysmmu.8", NULL), /* FIMC3 */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x12A20000,
-                        "exynos-sysmmu.9", NULL), /* G2D(4210) */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x10A40000,
-                        "exynos-sysmmu.9", NULL), /* G2D(4x12) */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11E20000,
-                        "exynos-sysmmu.10", NULL), /* FIMD0 */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x12220000,
-                        "exynos-sysmmu.11", NULL), /* FIMD1(4210) */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x12260000,
-                        "exynos-sysmmu.12", NULL), /* IS0(4x12) */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x122B0000,
-                        "exynos-sysmmu.13", NULL), /* IS1(4x12) */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x123B0000,
-                        "exynos-sysmmu.14", NULL), /* FIMC-LITE0(4x12) */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x123C0000,
-                        "exynos-sysmmu.15", NULL), /* FIMC-LITE1(4x12) */
-        {},
-};
-
 static void __init exynos4_dt_map_io(void)
 {
         exynos_init_io(NULL, 0);
-        s3c24xx_init_clocks(24000000);
 }
 
 static void __init exynos4_dt_machine_init(void)
 {
-        of_platform_populate(NULL, of_default_bus_match_table,
-                                exynos4_auxdata_lookup, NULL);
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
 static char const *exynos4_dt_compat[] __initdata = {
@@ -135,6 +40,18 @@ static char const *exynos4_dt_compat[] __initdata = {
         NULL
 };
 
+static void __init exynos4_reserve(void)
+{
+#ifdef CONFIG_S5P_DEV_MFC
+        struct s5p_mfc_dt_meminfo mfc_mem;
+
+        /* Reserve memory for MFC only if it's available */
+        mfc_mem.compatible = "samsung,mfc-v5";
+        if (of_scan_flat_dt(s5p_fdt_find_mfc_mem, &mfc_mem))
+                s5p_mfc_reserve_mem(mfc_mem.roff, mfc_mem.rsize, mfc_mem.loff,
+                                mfc_mem.lsize);
+#endif
+}
 DT_MACHINE_START(EXYNOS4210_DT, "Samsung Exynos4 (Flattened Device Tree)")
         /* Maintainer: Thomas Abraham <thomas.abraham@linaro.org> */
         .smp            = smp_ops(exynos_smp_ops),
@@ -142,7 +59,8 @@ DT_MACHINE_START(EXYNOS4210_DT, "Samsung Exynos4 (Flattened Device Tree)")
         .map_io         = exynos4_dt_map_io,
         .init_machine   = exynos4_dt_machine_init,
         .init_late      = exynos_init_late,
-        .init_time      = exynos4_timer_init,
+        .init_time      = exynos_init_time,
         .dt_compat      = exynos4_dt_compat,
         .restart        = exynos4_restart,
+        .reserve        = exynos4_reserve,
 MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
index acaeb14db54b..753b94f3fca7 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -11,151 +11,21 @@
 
 #include <linux/of_platform.h>
 #include <linux/of_fdt.h>
-#include <linux/serial_core.h>
 #include <linux/memblock.h>
 #include <linux/io.h>
+#include <linux/clocksource.h>
 
 #include <asm/mach/arch.h>
-#include <mach/map.h>
 #include <mach/regs-pmu.h>
 
 #include <plat/cpu.h>
-#include <plat/regs-serial.h>
 #include <plat/mfc.h>
 
 #include "common.h"
 
-/*
- * The following lookup table is used to override device names when devices
- * are registered from device tree. This is temporarily added to enable
- * device tree support addition for the EXYNOS5 architecture.
- *
- * For drivers that require platform data to be provided from the machine
- * file, a platform data pointer can also be supplied along with the
- * devices names. Usually, the platform data elements that cannot be parsed
- * from the device tree by the drivers (example: function pointers) are
- * supplied. But it should be noted that this is a temporary mechanism and
- * at some point, the drivers should be capable of parsing all the platform
- * data from the device tree.
- */
-static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
-        OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART0,
-                                "exynos4210-uart.0", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART1,
-                                "exynos4210-uart.1", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART2,
-                                "exynos4210-uart.2", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART3,
-                                "exynos4210-uart.3", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(0),
-                                "s3c2440-i2c.0", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(1),
-                                "s3c2440-i2c.1", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(2),
-                                "s3c2440-i2c.2", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(3),
-                                "s3c2440-i2c.3", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(4),
-                                "s3c2440-i2c.4", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(5),
-                                "s3c2440-i2c.5", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(6),
-                                "s3c2440-i2c.6", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(7),
-                                "s3c2440-i2c.7", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-hdmiphy-i2c", EXYNOS5_PA_IIC(8),
-                                "s3c2440-hdmiphy-i2c", NULL),
-        OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI0,
-                                "dw_mmc.0", NULL),
-        OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI1,
-                                "dw_mmc.1", NULL),
-        OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI2,
-                                "dw_mmc.2", NULL),
-        OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI3,
-                                "dw_mmc.3", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI0,
-                                "exynos4210-spi.0", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI1,
-                                "exynos4210-spi.1", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI2,
-                                "exynos4210-spi.2", NULL),
-        OF_DEV_AUXDATA("samsung,exynos5-sata-ahci", 0x122F0000,
-                                "exynos5-sata", NULL),
-        OF_DEV_AUXDATA("samsung,exynos5-sata-phy", 0x12170000,
-                                "exynos5-sata-phy", NULL),
-        OF_DEV_AUXDATA("samsung,exynos5-sata-phy-i2c", 0x121D0000,
-                                "exynos5-sata-phy-i2c", NULL),
-        OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL),
-        OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL),
-        OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL),
-        OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC0,
-                                "exynos-gsc.0", NULL),
-        OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC1,
-                                "exynos-gsc.1", NULL),
-        OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC2,
-                                "exynos-gsc.2", NULL),
-        OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC3,
-                                "exynos-gsc.3", NULL),
-        OF_DEV_AUXDATA("samsung,exynos5-hdmi", 0x14530000,
-                                "exynos5-hdmi", NULL),
-        OF_DEV_AUXDATA("samsung,exynos5-mixer", 0x14450000,
-                                "exynos5-mixer", NULL),
-        OF_DEV_AUXDATA("samsung,mfc-v6", 0x11000000, "s5p-mfc-v6", NULL),
-        OF_DEV_AUXDATA("samsung,exynos5250-tmu", 0x10060000,
-                                "exynos-tmu", NULL),
-        OF_DEV_AUXDATA("samsung,i2s-v5", 0x03830000,
-                                "samsung-i2s.0", NULL),
-        OF_DEV_AUXDATA("samsung,i2s-v5", 0x12D60000,
-                                "samsung-i2s.1", NULL),
-        OF_DEV_AUXDATA("samsung,i2s-v5", 0x12D70000,
-                                "samsung-i2s.2", NULL),
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11210000,
-                        "exynos-sysmmu.0", "mfc"), /* MFC_L */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11200000,
-                        "exynos-sysmmu.1", "mfc"), /* MFC_R */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x14650000,
-                        "exynos-sysmmu.2", NULL), /* TV */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11F20000,
-                        "exynos-sysmmu.3", "jpeg"), /* JPEG */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11D40000,
-                        "exynos-sysmmu.4", NULL), /* ROTATOR */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13E80000,
-                        "exynos-sysmmu.5", "gscl"), /* GSCL0 */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13E90000,
-                        "exynos-sysmmu.6", "gscl"), /* GSCL1 */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13EA0000,
-                        "exynos-sysmmu.7", "gscl"), /* GSCL2 */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13EB0000,
-                        "exynos-sysmmu.8", "gscl"), /* GSCL3 */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13260000,
-                        "exynos-sysmmu.9", NULL), /* FIMC-IS0 */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x132C0000,
-                        "exynos-sysmmu.10", NULL), /* FIMC-IS1 */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x14640000,
-                        "exynos-sysmmu.11", NULL), /* FIMD1 */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13C40000,
-                        "exynos-sysmmu.12", NULL), /* FIMC-LITE0 */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13C50000,
-                        "exynos-sysmmu.13", NULL), /* FIMC-LITE1 */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x10A60000,
-                        "exynos-sysmmu.14", NULL), /* G2D */
-        {},
-};
-
-static const struct of_dev_auxdata exynos5440_auxdata_lookup[] __initconst = {
-        OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5440_PA_UART0,
-                                "exynos4210-uart.0", NULL),
-        {},
-};
-
 static void __init exynos5_dt_map_io(void)
 {
-        unsigned long root = of_get_flat_dt_root();
-
         exynos_init_io(NULL, 0);
-
-        if (of_flat_dt_is_compatible(root, "samsung,exynos5250"))
-                s3c24xx_init_clocks(24000000);
 }
 
 static void __init exynos5_dt_machine_init(void)
@@ -182,12 +52,7 @@ static void __init exynos5_dt_machine_init(void)
                 }
         }
 
-        if (of_machine_is_compatible("samsung,exynos5250"))
-                of_platform_populate(NULL, of_default_bus_match_table,
-                                     exynos5250_auxdata_lookup, NULL);
-        else if (of_machine_is_compatible("samsung,exynos5440"))
-                of_platform_populate(NULL, of_default_bus_match_table,
-                                     exynos5440_auxdata_lookup, NULL);
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
 static char const *exynos5_dt_compat[] __initdata = {
@@ -216,7 +81,7 @@ DT_MACHINE_START(EXYNOS5_DT, "SAMSUNG EXYNOS5 (Flattened Device Tree)")
         .map_io         = exynos5_dt_map_io,
         .init_machine   = exynos5_dt_machine_init,
         .init_late      = exynos_init_late,
-        .init_time      = exynos4_timer_init,
+        .init_time      = exynos_init_time,
         .dt_compat      = exynos5_dt_compat,
         .restart        = exynos5_restart,
         .reserve        = exynos5_reserve,
diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c
index 1ea79730187f..0c10852423c3 100644
--- a/arch/arm/mach-exynos/mach-nuri.c
+++ b/arch/arm/mach-exynos/mach-nuri.c
@@ -1330,8 +1330,9 @@ static struct platform_device *nuri_devices[] __initdata = {
 static void __init nuri_map_io(void)
 {
         exynos_init_io(NULL, 0);
-        s3c24xx_init_clocks(clk_xusbxti.rate);
         s3c24xx_init_uarts(nuri_uartcfgs, ARRAY_SIZE(nuri_uartcfgs));
+        xxti_f = 0;
+        xusbxti_f = 24000000;
 }
 
 static void __init nuri_reserve(void)
@@ -1380,7 +1381,7 @@ MACHINE_START(NURI, "NURI")
         .map_io         = nuri_map_io,
         .init_machine   = nuri_machine_init,
         .init_late      = exynos_init_late,
-        .init_time      = exynos4_timer_init,
+        .init_time      = exynos_init_time,
         .reserve        = &nuri_reserve,
         .restart        = exynos4_restart,
 MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-origen.c b/arch/arm/mach-exynos/mach-origen.c
index 579d2d171daa..a9aa5c034b23 100644
--- a/arch/arm/mach-exynos/mach-origen.c
+++ b/arch/arm/mach-exynos/mach-origen.c
@@ -754,8 +754,9 @@ static void s5p_tv_setup(void)
 static void __init origen_map_io(void)
 {
         exynos_init_io(NULL, 0);
-        s3c24xx_init_clocks(clk_xusbxti.rate);
         s3c24xx_init_uarts(origen_uartcfgs, ARRAY_SIZE(origen_uartcfgs));
+        xxti_f = 0;
+        xusbxti_f = 24000000;
 }
 
 static void __init origen_power_init(void)
@@ -815,7 +816,7 @@ MACHINE_START(ORIGEN, "ORIGEN")
         .map_io         = origen_map_io,
         .init_machine   = origen_machine_init,
         .init_late      = exynos_init_late,
-        .init_time      = exynos4_timer_init,
+        .init_time      = exynos_init_time,
         .reserve        = &origen_reserve,
         .restart        = exynos4_restart,
 MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-smdk4x12.c b/arch/arm/mach-exynos/mach-smdk4x12.c
index fe6149624b84..184faa3bd93a 100644
--- a/arch/arm/mach-exynos/mach-smdk4x12.c
+++ b/arch/arm/mach-exynos/mach-smdk4x12.c
@@ -322,7 +322,6 @@ static struct platform_device *smdk4x12_devices[] __initdata = {
 static void __init smdk4x12_map_io(void)
 {
         exynos_init_io(NULL, 0);
-        s3c24xx_init_clocks(clk_xusbxti.rate);
         s3c24xx_init_uarts(smdk4x12_uartcfgs, ARRAY_SIZE(smdk4x12_uartcfgs));
 }
 
@@ -376,7 +375,7 @@ MACHINE_START(SMDK4212, "SMDK4212")
         .init_irq       = exynos4_init_irq,
         .map_io         = smdk4x12_map_io,
         .init_machine   = smdk4x12_machine_init,
-        .init_time      = exynos4_timer_init,
+        .init_time      = exynos_init_time,
         .restart        = exynos4_restart,
         .reserve        = &smdk4x12_reserve,
 MACHINE_END
@@ -390,7 +389,7 @@ MACHINE_START(SMDK4412, "SMDK4412")
         .map_io         = smdk4x12_map_io,
         .init_machine   = smdk4x12_machine_init,
         .init_late      = exynos_init_late,
-        .init_time      = exynos4_timer_init,
+        .init_time      = exynos_init_time,
         .restart        = exynos4_restart,
         .reserve        = &smdk4x12_reserve,
 MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-smdkv310.c b/arch/arm/mach-exynos/mach-smdkv310.c
index d71672922b19..75eca7d4e128 100644
--- a/arch/arm/mach-exynos/mach-smdkv310.c
+++ b/arch/arm/mach-exynos/mach-smdkv310.c
@@ -371,8 +371,9 @@ static void s5p_tv_setup(void)
 static void __init smdkv310_map_io(void)
 {
         exynos_init_io(NULL, 0);
-        s3c24xx_init_clocks(clk_xusbxti.rate);
         s3c24xx_init_uarts(smdkv310_uartcfgs, ARRAY_SIZE(smdkv310_uartcfgs));
+        xxti_f = 12000000;
+        xusbxti_f = 24000000;
 }
 
 static void __init smdkv310_reserve(void)
@@ -423,7 +424,7 @@ MACHINE_START(SMDKV310, "SMDKV310")
         .init_irq       = exynos4_init_irq,
         .map_io         = smdkv310_map_io,
         .init_machine   = smdkv310_machine_init,
-        .init_time      = exynos4_timer_init,
+        .init_time      = exynos_init_time,
         .reserve        = &smdkv310_reserve,
         .restart        = exynos4_restart,
 MACHINE_END
@@ -436,7 +437,7 @@ MACHINE_START(SMDKC210, "SMDKC210")
         .map_io         = smdkv310_map_io,
         .init_machine   = smdkv310_machine_init,
         .init_late      = exynos_init_late,
-        .init_time      = exynos4_timer_init,
+        .init_time      = exynos_init_time,
         .reserve        = &smdkv310_reserve,
         .restart        = exynos4_restart,
 MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c
index 497fcb793dc1..72f08fd7cfa9 100644
--- a/arch/arm/mach-exynos/mach-universal_c210.c
+++ b/arch/arm/mach-exynos/mach-universal_c210.c
@@ -41,7 +41,7 @@
 #include <plat/mfc.h>
 #include <plat/sdhci.h>
 #include <plat/fimc-core.h>
-#include <plat/s5p-time.h>
+#include <plat/samsung-time.h>
 #include <plat/camport.h>
 
 #include <mach/map.h>
@@ -1092,9 +1092,10 @@ static struct platform_device *universal_devices[] __initdata = {
 static void __init universal_map_io(void)
 {
         exynos_init_io(NULL, 0);
-        s3c24xx_init_clocks(clk_xusbxti.rate);
         s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs));
-        s5p_set_timer_source(S5P_PWM2, S5P_PWM4);
+        samsung_set_timer_source(SAMSUNG_PWM2, SAMSUNG_PWM4);
+        xxti_f = 0;
+        xusbxti_f = 24000000;
 }
 
 static void s5p_tv_setup(void)
@@ -1152,7 +1153,7 @@ MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")
         .map_io         = universal_map_io,
         .init_machine   = universal_machine_init,
         .init_late      = exynos_init_late,
-        .init_time      = s5p_timer_init,
+        .init_time      = samsung_timer_init,
         .reserve        = &universal_reserve,
         .restart        = exynos4_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
index 37f513d1588e..0c5e4fb61117 100644
--- a/arch/arm/mach-s3c24xx/Kconfig
+++ b/arch/arm/mach-s3c24xx/Kconfig
@@ -30,6 +30,7 @@ config CPU_S3C2410
         select S3C2410_CLOCK
         select S3C2410_CPUFREQ if CPU_FREQ_S3C24XX
         select S3C2410_PM if PM
+        select SAMSUNG_HRT
         help
           Support for S3C2410 and S3C2410A family from the S3C24XX line
           of Samsung Mobile CPUs.
@@ -41,6 +42,7 @@ config CPU_S3C2412
         select CPU_LLSERIAL_S3C2440
         select S3C2412_DMA if S3C24XX_DMA
         select S3C2412_PM if PM
+        select SAMSUNG_HRT
         help
           Support for the S3C2412 and S3C2413 SoCs from the S3C24XX line
 
@@ -53,6 +55,7 @@ config CPU_S3C2416
         select S3C2443_COMMON
         select S3C2443_DMA if S3C24XX_DMA
         select SAMSUNG_CLKSRC
+        select SAMSUNG_HRT
         help
           Support for the S3C2416 SoC from the S3C24XX line
 
@@ -63,6 +66,7 @@ config CPU_S3C2440
         select S3C2410_CLOCK
         select S3C2410_PM if PM
         select S3C2440_DMA if S3C24XX_DMA
+        select SAMSUNG_HRT
         help
           Support for S3C2440 Samsung Mobile CPU based systems.
 
@@ -72,6 +76,7 @@ config CPU_S3C2442
         select CPU_LLSERIAL_S3C2440
         select S3C2410_CLOCK
         select S3C2410_PM if PM
+        select SAMSUNG_HRT
         help
           Support for S3C2442 Samsung Mobile CPU based systems.
 
@@ -87,6 +92,7 @@ config CPU_S3C2443
         select S3C2443_COMMON
         select S3C2443_DMA if S3C24XX_DMA
         select SAMSUNG_CLKSRC
+        select SAMSUNG_HRT
         help
           Support for the S3C2443 SoC from the S3C24XX line
 
diff --git a/arch/arm/mach-s3c24xx/bast-irq.c b/arch/arm/mach-s3c24xx/bast-irq.c
index c0daa9590b4c..cb1b791954de 100644
--- a/arch/arm/mach-s3c24xx/bast-irq.c
+++ b/arch/arm/mach-s3c24xx/bast-irq.c
@@ -34,8 +34,6 @@
 #include <mach/hardware.h>
 #include <mach/regs-irq.h>
 
-#include <plat/irq.h>
-
 #include "bast.h"
 
 #define irqdbf(x...)
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2410.c b/arch/arm/mach-s3c24xx/clock-s3c2410.c
index 641266f3d152..34fffdf6fc1d 100644
--- a/arch/arm/mach-s3c24xx/clock-s3c2410.c
+++ b/arch/arm/mach-s3c24xx/clock-s3c2410.c
@@ -40,7 +40,6 @@
 #include <mach/regs-clock.h>
 #include <mach/regs-gpio.h>
 
-#include <plat/s3c2410.h>
 #include <plat/clock.h>
 #include <plat/cpu.h>
 
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2412.c b/arch/arm/mach-s3c24xx/clock-s3c2412.c
index d10b695a9066..2cc017da88fe 100644
--- a/arch/arm/mach-s3c24xx/clock-s3c2412.c
+++ b/arch/arm/mach-s3c24xx/clock-s3c2412.c
@@ -41,7 +41,6 @@
 #include <mach/regs-clock.h>
 #include <mach/regs-gpio.h>
 
-#include <plat/s3c2412.h>
 #include <plat/clock.h>
 #include <plat/cpu.h>
 
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2416.c b/arch/arm/mach-s3c24xx/clock-s3c2416.c
index 14a81c2317a4..036056cea57c 100644
--- a/arch/arm/mach-s3c24xx/clock-s3c2416.c
+++ b/arch/arm/mach-s3c24xx/clock-s3c2416.c
@@ -14,7 +14,6 @@
 #include <linux/init.h>
 #include <linux/clk.h>
 
-#include <plat/s3c2416.h>
 #include <plat/clock.h>
 #include <plat/clock-clksrc.h>
 #include <plat/cpu.h>
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2443.c b/arch/arm/mach-s3c24xx/clock-s3c2443.c
index bdaba59b42dc..0a53051b0787 100644
--- a/arch/arm/mach-s3c24xx/clock-s3c2443.c
+++ b/arch/arm/mach-s3c24xx/clock-s3c2443.c
@@ -41,7 +41,6 @@
 
 #include <plat/cpu-freq.h>
 
-#include <plat/s3c2443.h>
 #include <plat/clock.h>
 #include <plat/clock-clksrc.h>
 #include <plat/cpu.h>
diff --git a/arch/arm/mach-s3c24xx/common-smdk.c b/arch/arm/mach-s3c24xx/common-smdk.c
index 3b2cf6db3634..404444dd3840 100644
--- a/arch/arm/mach-s3c24xx/common-smdk.c
+++ b/arch/arm/mach-s3c24xx/common-smdk.c
@@ -41,11 +41,12 @@
 
 #include <linux/platform_data/mtd-nand-s3c2410.h>
 
-#include <plat/common-smdk.h>
 #include <plat/gpio-cfg.h>
 #include <plat/devs.h>
 #include <plat/pm.h>
 
+#include "common-smdk.h"
+
 /* LED devices */
 
 static struct s3c24xx_led_platdata smdk_pdata_led4 = {
diff --git a/arch/arm/plat-samsung/include/plat/common-smdk.h b/arch/arm/mach-s3c24xx/common-smdk.h
index ba028f1ed30b..98f733e1cb42 100644
--- a/arch/arm/plat-samsung/include/plat/common-smdk.h
+++ b/arch/arm/mach-s3c24xx/common-smdk.h
@@ -1,5 +1,4 @@
-/* linux/arch/arm/plat-samsung/include/plat/common-smdk.h
- *
+/*
  * Copyright (c) 2006 Simtec Electronics
  *      Ben Dooks <ben@simtec.co.uk>
  *
diff --git a/arch/arm/mach-s3c24xx/common.c b/arch/arm/mach-s3c24xx/common.c
index 6bcf87f65f9e..d97533d21ac4 100644
--- a/arch/arm/mach-s3c24xx/common.c
+++ b/arch/arm/mach-s3c24xx/common.c
@@ -47,14 +47,11 @@
 #include <plat/cpu.h>
 #include <plat/devs.h>
 #include <plat/clock.h>
-#include <plat/s3c2410.h>
-#include <plat/s3c2412.h>
-#include <plat/s3c2416.h>
-#include <plat/s3c244x.h>
-#include <plat/s3c2443.h>
 #include <plat/cpu-freq.h>
 #include <plat/pll.h>
 
+#include "common.h"
+
 /* table of supported CPUs */
 
 static const char name_s3c2410[]  = "S3C2410";
diff --git a/arch/arm/mach-s3c24xx/common.h b/arch/arm/mach-s3c24xx/common.h
index ed6276fcaa3b..8a2b4137ddb6 100644
--- a/arch/arm/mach-s3c24xx/common.h
+++ b/arch/arm/mach-s3c24xx/common.h
@@ -12,8 +12,94 @@
 #ifndef __ARCH_ARM_MACH_S3C24XX_COMMON_H
 #define __ARCH_ARM_MACH_S3C24XX_COMMON_H __FILE__
 
-void s3c2410_restart(char mode, const char *cmd);
-void s3c244x_restart(char mode, const char *cmd);
+struct s3c2410_uartcfg;
+
+#ifdef CONFIG_CPU_S3C2410
+extern  int s3c2410_init(void);
+extern  int s3c2410a_init(void);
+extern void s3c2410_map_io(void);
+extern void s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no);
+extern void s3c2410_init_clocks(int xtal);
+extern void s3c2410_restart(char mode, const char *cmd);
+#else
+#define s3c2410_init_clocks NULL
+#define s3c2410_init_uarts NULL
+#define s3c2410_map_io NULL
+#define s3c2410_init NULL
+#define s3c2410a_init NULL
+#endif
+
+#ifdef CONFIG_CPU_S3C2412
+extern  int s3c2412_init(void);
+extern void s3c2412_map_io(void);
+extern void s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no);
+extern void s3c2412_init_clocks(int xtal);
+extern  int s3c2412_baseclk_add(void);
+extern void s3c2412_restart(char mode, const char *cmd);
+#else
+#define s3c2412_init_clocks NULL
+#define s3c2412_init_uarts NULL
+#define s3c2412_map_io NULL
+#define s3c2412_init NULL
+#endif
+
+#ifdef CONFIG_CPU_S3C2416
+extern  int s3c2416_init(void);
+extern void s3c2416_map_io(void);
+extern void s3c2416_init_uarts(struct s3c2410_uartcfg *cfg, int no);
+extern void s3c2416_init_clocks(int xtal);
+extern  int s3c2416_baseclk_add(void);
+extern void s3c2416_restart(char mode, const char *cmd);
+extern void s3c2416_init_irq(void);
+
+extern struct syscore_ops s3c2416_irq_syscore_ops;
+#else
+#define s3c2416_init_clocks NULL
+#define s3c2416_init_uarts NULL
+#define s3c2416_map_io NULL
+#define s3c2416_init NULL
+#endif
+
+#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
+extern void s3c244x_map_io(void);
+extern void s3c244x_init_uarts(struct s3c2410_uartcfg *cfg, int no);
+extern void s3c244x_init_clocks(int xtal);
+extern void s3c244x_restart(char mode, const char *cmd);
+#else
+#define s3c244x_init_clocks NULL
+#define s3c244x_init_uarts NULL
+#endif
+
+#ifdef CONFIG_CPU_S3C2440
+extern  int s3c2440_init(void);
+extern void s3c2440_map_io(void);
+#else
+#define s3c2440_init NULL
+#define s3c2440_map_io NULL
+#endif
+
+#ifdef CONFIG_CPU_S3C2442
+extern  int s3c2442_init(void);
+extern void s3c2442_map_io(void);
+#else
+#define s3c2442_init NULL
+#define s3c2442_map_io NULL
+#endif
+
+#ifdef CONFIG_CPU_S3C2443
+extern  int s3c2443_init(void);
+extern void s3c2443_map_io(void);
+extern void s3c2443_init_uarts(struct s3c2410_uartcfg *cfg, int no);
+extern void s3c2443_init_clocks(int xtal);
+extern  int s3c2443_baseclk_add(void);
+extern void s3c2443_restart(char mode, const char *cmd);
+extern void s3c2443_init_irq(void);
+#else
+#define s3c2443_init_clocks NULL
+#define s3c2443_init_uarts NULL
+#define s3c2443_map_io NULL
+#define s3c2443_init NULL
+#endif
 
 extern struct syscore_ops s3c24xx_irq_syscore_ops;
 
diff --git a/arch/arm/mach-s3c24xx/dma-s3c2410.c b/arch/arm/mach-s3c24xx/dma-s3c2410.c
index 25d085adc93c..a6c94b820954 100644
--- a/arch/arm/mach-s3c24xx/dma-s3c2410.c
+++ b/arch/arm/mach-s3c24xx/dma-s3c2410.c
@@ -28,7 +28,6 @@
 #include <plat/regs-ac97.h>
 #include <plat/regs-dma.h>
 #include <mach/regs-lcd.h>
-#include <mach/regs-sdi.h>
 #include <plat/regs-iis.h>
 #include <plat/regs-spi.h>
 
diff --git a/arch/arm/mach-s3c24xx/dma-s3c2412.c b/arch/arm/mach-s3c24xx/dma-s3c2412.c
index d2408ba372cb..c0e8c3f5057e 100644
--- a/arch/arm/mach-s3c24xx/dma-s3c2412.c
+++ b/arch/arm/mach-s3c24xx/dma-s3c2412.c
@@ -28,7 +28,6 @@
 #include <plat/regs-ac97.h>
 #include <plat/regs-dma.h>
 #include <mach/regs-lcd.h>
-#include <mach/regs-sdi.h>
 #include <plat/regs-iis.h>
 #include <plat/regs-spi.h>
 
diff --git a/arch/arm/mach-s3c24xx/dma-s3c2440.c b/arch/arm/mach-s3c24xx/dma-s3c2440.c
index 0b86e74d104f..1c08eccd9425 100644
--- a/arch/arm/mach-s3c24xx/dma-s3c2440.c
+++ b/arch/arm/mach-s3c24xx/dma-s3c2440.c
@@ -28,7 +28,6 @@
 #include <plat/regs-ac97.h>
 #include <plat/regs-dma.h>
 #include <mach/regs-lcd.h>
-#include <mach/regs-sdi.h>
 #include <plat/regs-iis.h>
 #include <plat/regs-spi.h>
 
diff --git a/arch/arm/mach-s3c24xx/dma-s3c2443.c b/arch/arm/mach-s3c24xx/dma-s3c2443.c
index 05536254a3f8..000e4c69fce9 100644
--- a/arch/arm/mach-s3c24xx/dma-s3c2443.c
+++ b/arch/arm/mach-s3c24xx/dma-s3c2443.c
@@ -28,7 +28,6 @@
 #include <plat/regs-ac97.h>
 #include <plat/regs-dma.h>
 #include <mach/regs-lcd.h>
-#include <mach/regs-sdi.h>
 #include <plat/regs-iis.h>
 #include <plat/regs-spi.h>
 
diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-sdi.h b/arch/arm/mach-s3c24xx/include/mach/regs-sdi.h
deleted file mode 100644
index cbf2d8884e30..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/regs-sdi.h
+++ /dev/null
@@ -1,127 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/regs-sdi.h
- *
- * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
- *                    http://www.simtec.co.uk/products/SWLINUX/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C2410 MMC/SDIO register definitions
-*/
-
-#ifndef __ASM_ARM_REGS_SDI
-#define __ASM_ARM_REGS_SDI "regs-sdi.h"
-
-#define S3C2410_SDICON                (0x00)
-#define S3C2410_SDIPRE                (0x04)
-#define S3C2410_SDICMDARG             (0x08)
-#define S3C2410_SDICMDCON             (0x0C)
-#define S3C2410_SDICMDSTAT            (0x10)
-#define S3C2410_SDIRSP0               (0x14)
-#define S3C2410_SDIRSP1               (0x18)
-#define S3C2410_SDIRSP2               (0x1C)
-#define S3C2410_SDIRSP3               (0x20)
-#define S3C2410_SDITIMER              (0x24)
-#define S3C2410_SDIBSIZE              (0x28)
-#define S3C2410_SDIDCON               (0x2C)
-#define S3C2410_SDIDCNT               (0x30)
-#define S3C2410_SDIDSTA               (0x34)
-#define S3C2410_SDIFSTA               (0x38)
-
-#define S3C2410_SDIDATA               (0x3C)
-#define S3C2410_SDIIMSK               (0x40)
-
-#define S3C2440_SDIDATA               (0x40)
-#define S3C2440_SDIIMSK               (0x3C)
-
-#define S3C2440_SDICON_SDRESET        (1<<8)
-#define S3C2440_SDICON_MMCCLOCK       (1<<5)
-#define S3C2410_SDICON_BYTEORDER      (1<<4)
-#define S3C2410_SDICON_SDIOIRQ        (1<<3)
-#define S3C2410_SDICON_RWAITEN        (1<<2)
-#define S3C2410_SDICON_FIFORESET      (1<<1)
-#define S3C2410_SDICON_CLOCKTYPE      (1<<0)
-
-#define S3C2410_SDICMDCON_ABORT       (1<<12)
-#define S3C2410_SDICMDCON_WITHDATA    (1<<11)
-#define S3C2410_SDICMDCON_LONGRSP     (1<<10)
-#define S3C2410_SDICMDCON_WAITRSP     (1<<9)
-#define S3C2410_SDICMDCON_CMDSTART    (1<<8)
-#define S3C2410_SDICMDCON_SENDERHOST  (1<<6)
-#define S3C2410_SDICMDCON_INDEX       (0x3f)
-
-#define S3C2410_SDICMDSTAT_CRCFAIL    (1<<12)
-#define S3C2410_SDICMDSTAT_CMDSENT    (1<<11)
-#define S3C2410_SDICMDSTAT_CMDTIMEOUT (1<<10)
-#define S3C2410_SDICMDSTAT_RSPFIN     (1<<9)
-#define S3C2410_SDICMDSTAT_XFERING    (1<<8)
-#define S3C2410_SDICMDSTAT_INDEX      (0xff)
-
-#define S3C2440_SDIDCON_DS_BYTE       (0<<22)
-#define S3C2440_SDIDCON_DS_HALFWORD   (1<<22)
-#define S3C2440_SDIDCON_DS_WORD       (2<<22)
-#define S3C2410_SDIDCON_IRQPERIOD     (1<<21)
-#define S3C2410_SDIDCON_TXAFTERRESP   (1<<20)
-#define S3C2410_SDIDCON_RXAFTERCMD    (1<<19)
-#define S3C2410_SDIDCON_BUSYAFTERCMD  (1<<18)
-#define S3C2410_SDIDCON_BLOCKMODE     (1<<17)
-#define S3C2410_SDIDCON_WIDEBUS       (1<<16)
-#define S3C2410_SDIDCON_DMAEN         (1<<15)
-#define S3C2410_SDIDCON_STOP          (1<<14)
-#define S3C2440_SDIDCON_DATSTART      (1<<14)
-#define S3C2410_SDIDCON_DATMODE       (3<<12)
-#define S3C2410_SDIDCON_BLKNUM        (0x7ff)
-
-/* constants for S3C2410_SDIDCON_DATMODE */
-#define S3C2410_SDIDCON_XFER_READY    (0<<12)
-#define S3C2410_SDIDCON_XFER_CHKSTART (1<<12)
-#define S3C2410_SDIDCON_XFER_RXSTART  (2<<12)
-#define S3C2410_SDIDCON_XFER_TXSTART  (3<<12)
-
-#define S3C2410_SDIDCON_BLKNUM_MASK   (0xFFF)
-#define S3C2410_SDIDCNT_BLKNUM_SHIFT  (12)
-
-#define S3C2410_SDIDSTA_RDYWAITREQ    (1<<10)
-#define S3C2410_SDIDSTA_SDIOIRQDETECT (1<<9)
-#define S3C2410_SDIDSTA_FIFOFAIL      (1<<8)    /* reserved on 2440 */
-#define S3C2410_SDIDSTA_CRCFAIL       (1<<7)
-#define S3C2410_SDIDSTA_RXCRCFAIL     (1<<6)
-#define S3C2410_SDIDSTA_DATATIMEOUT   (1<<5)
-#define S3C2410_SDIDSTA_XFERFINISH    (1<<4)
-#define S3C2410_SDIDSTA_BUSYFINISH    (1<<3)
-#define S3C2410_SDIDSTA_SBITERR       (1<<2)    /* reserved on 2410a/2440 */
-#define S3C2410_SDIDSTA_TXDATAON      (1<<1)
-#define S3C2410_SDIDSTA_RXDATAON      (1<<0)
-
-#define S3C2440_SDIFSTA_FIFORESET      (1<<16)
-#define S3C2440_SDIFSTA_FIFOFAIL       (3<<14)  /* 3 is correct (2 bits) */
-#define S3C2410_SDIFSTA_TFDET          (1<<13)
-#define S3C2410_SDIFSTA_RFDET          (1<<12)
-#define S3C2410_SDIFSTA_TFHALF         (1<<11)
-#define S3C2410_SDIFSTA_TFEMPTY        (1<<10)
-#define S3C2410_SDIFSTA_RFLAST         (1<<9)
-#define S3C2410_SDIFSTA_RFFULL         (1<<8)
-#define S3C2410_SDIFSTA_RFHALF         (1<<7)
-#define S3C2410_SDIFSTA_COUNTMASK      (0x7f)
-
-#define S3C2410_SDIIMSK_RESPONSECRC    (1<<17)
-#define S3C2410_SDIIMSK_CMDSENT        (1<<16)
-#define S3C2410_SDIIMSK_CMDTIMEOUT     (1<<15)
-#define S3C2410_SDIIMSK_RESPONSEND     (1<<14)
-#define S3C2410_SDIIMSK_READWAIT       (1<<13)
-#define S3C2410_SDIIMSK_SDIOIRQ        (1<<12)
-#define S3C2410_SDIIMSK_FIFOFAIL       (1<<11)
-#define S3C2410_SDIIMSK_CRCSTATUS      (1<<10)
-#define S3C2410_SDIIMSK_DATACRC        (1<<9)
-#define S3C2410_SDIIMSK_DATATIMEOUT    (1<<8)
-#define S3C2410_SDIIMSK_DATAFINISH     (1<<7)
-#define S3C2410_SDIIMSK_BUSYFINISH     (1<<6)
-#define S3C2410_SDIIMSK_SBITERR        (1<<5)   /* reserved 2440/2410a */
-#define S3C2410_SDIIMSK_TXFIFOHALF     (1<<4)
-#define S3C2410_SDIIMSK_TXFIFOEMPTY    (1<<3)
-#define S3C2410_SDIIMSK_RXFIFOLAST     (1<<2)
-#define S3C2410_SDIIMSK_RXFIFOFULL     (1<<1)
-#define S3C2410_SDIIMSK_RXFIFOHALF     (1<<0)
-
-#endif /* __ASM_ARM_REGS_SDI */
diff --git a/arch/arm/mach-s3c24xx/irq-pm.c b/arch/arm/mach-s3c24xx/irq-pm.c
index e1199599873e..b91341ef2b2e 100644
--- a/arch/arm/mach-s3c24xx/irq-pm.c
+++ b/arch/arm/mach-s3c24xx/irq-pm.c
@@ -16,10 +16,15 @@
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/syscore_ops.h>
+#include <linux/io.h>
 
 #include <plat/cpu.h>
 #include <plat/pm.h>
-#include <plat/irq.h>
+#include <plat/map-base.h>
+#include <plat/map-s3c.h>
+
+#include <mach/regs-irq.h>
+#include <mach/regs-gpio.h>
 
 #include <asm/irq.h>
 
diff --git a/arch/arm/mach-s3c24xx/irq.c b/arch/arm/mach-s3c24xx/irq.c
index d8ba9bee4c7e..e0769fb03e94 100644
--- a/arch/arm/mach-s3c24xx/irq.c
+++ b/arch/arm/mach-s3c24xx/irq.c
@@ -34,7 +34,6 @@
 #include <plat/cpu.h>
 #include <plat/regs-irqtype.h>
 #include <plat/pm.h>
-#include <plat/irq.h>
 
 #define S3C_IRQTYPE_NONE        0
 #define S3C_IRQTYPE_EINT        1
@@ -175,8 +174,7 @@ static int s3c_irqext_type_set(void __iomem *gpcon_reg,
         return 0;
 }
 
-/* FIXME: make static when it's out of plat-samsung/irq.h */
-int s3c_irqext_type(struct irq_data *data, unsigned int type)
+static int s3c_irqext_type(struct irq_data *data, unsigned int type)
 {
         void __iomem *extint_reg;
         void __iomem *gpcon_reg;
@@ -224,7 +222,7 @@ static int s3c_irqext0_type(struct irq_data *data, unsigned int type)
                                    extint_offset, type);
 }
 
-struct irq_chip s3c_irq_chip = {
+static struct irq_chip s3c_irq_chip = {
         .name           = "s3c",
         .irq_ack        = s3c_irq_ack,
         .irq_mask       = s3c_irq_mask,
@@ -232,7 +230,7 @@ struct irq_chip s3c_irq_chip = {
         .irq_set_wake   = s3c_irq_wake
 };
 
-struct irq_chip s3c_irq_level_chip = {
+static struct irq_chip s3c_irq_level_chip = {
         .name           = "s3c-level",
         .irq_mask       = s3c_irq_mask,
         .irq_unmask     = s3c_irq_unmask,
diff --git a/arch/arm/mach-s3c24xx/mach-amlm5900.c b/arch/arm/mach-s3c24xx/mach-amlm5900.c
index 0e0279e79150..432144cb54ae 100644
--- a/arch/arm/mach-s3c24xx/mach-amlm5900.c
+++ b/arch/arm/mach-s3c24xx/mach-amlm5900.c
@@ -63,6 +63,8 @@
 #include <linux/mtd/map.h>
 #include <linux/mtd/physmap.h>
 
+#include <plat/samsung-time.h>
+
 #include "common.h"
 
 static struct resource amlm5900_nor_resource =
@@ -160,6 +162,7 @@ static void __init amlm5900_map_io(void)
         s3c24xx_init_io(amlm5900_iodesc, ARRAY_SIZE(amlm5900_iodesc));
         s3c24xx_init_clocks(0);
         s3c24xx_init_uarts(amlm5900_uartcfgs, ARRAY_SIZE(amlm5900_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 #ifdef CONFIG_FB_S3C2410
@@ -237,6 +240,6 @@ MACHINE_START(AML_M5900, "AML_M5900")
         .map_io         = amlm5900_map_io,
         .init_irq       = s3c24xx_init_irq,
         .init_machine   = amlm5900_init,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-anubis.c b/arch/arm/mach-s3c24xx/mach-anubis.c
index bb595f15ce36..24f1a04ccc88 100644
--- a/arch/arm/mach-s3c24xx/mach-anubis.c
+++ b/arch/arm/mach-s3c24xx/mach-anubis.c
@@ -49,6 +49,7 @@
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <linux/platform_data/asoc-s3c24xx_simtec.h>
+#include <plat/samsung-time.h>
 
 #include "anubis.h"
 #include "common.h"
@@ -410,6 +411,7 @@ static void __init anubis_map_io(void)
         s3c24xx_init_io(anubis_iodesc, ARRAY_SIZE(anubis_iodesc));
         s3c24xx_init_clocks(0);
         s3c24xx_init_uarts(anubis_uartcfgs, ARRAY_SIZE(anubis_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 
         /* check for the newer revision boards with large page nand */
 
@@ -444,6 +446,6 @@ MACHINE_START(ANUBIS, "Simtec-Anubis")
         .map_io         = anubis_map_io,
         .init_machine   = anubis_init,
         .init_irq       = s3c24xx_init_irq,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-at2440evb.c b/arch/arm/mach-s3c24xx/mach-at2440evb.c
index b4bc60c78ebb..2bf6c8c24317 100644
--- a/arch/arm/mach-s3c24xx/mach-at2440evb.c
+++ b/arch/arm/mach-s3c24xx/mach-at2440evb.c
@@ -48,6 +48,7 @@
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <linux/platform_data/mmc-s3cmci.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 
@@ -192,6 +193,7 @@ static void __init at2440evb_map_io(void)
         s3c24xx_init_io(at2440evb_iodesc, ARRAY_SIZE(at2440evb_iodesc));
         s3c24xx_init_clocks(16934400);
         s3c24xx_init_uarts(at2440evb_uartcfgs, ARRAY_SIZE(at2440evb_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init at2440evb_init(void)
@@ -210,6 +212,6 @@ MACHINE_START(AT2440EVB, "AT2440EVB")
         .map_io         = at2440evb_map_io,
         .init_machine   = at2440evb_init,
         .init_irq       = s3c24xx_init_irq,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-bast.c b/arch/arm/mach-s3c24xx/mach-bast.c
index ca6618081041..eabe2db42ef6 100644
--- a/arch/arm/mach-s3c24xx/mach-bast.c
+++ b/arch/arm/mach-s3c24xx/mach-bast.c
@@ -55,6 +55,7 @@
 #include <plat/devs.h>
 #include <plat/gpio-cfg.h>
 #include <plat/regs-serial.h>
+#include <plat/samsung-time.h>
 
 #include "bast.h"
 #include "common.h"
@@ -576,6 +577,7 @@ static void __init bast_map_io(void)
         s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
         s3c24xx_init_clocks(0);
         s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init bast_init(void)
@@ -605,6 +607,6 @@ MACHINE_START(BAST, "Simtec-BAST")
         .map_io         = bast_map_io,
         .init_irq       = s3c24xx_init_irq,
         .init_machine   = bast_init,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-gta02.c b/arch/arm/mach-s3c24xx/mach-gta02.c
index a25e8c5a7b4c..84a750d46d4b 100644
--- a/arch/arm/mach-s3c24xx/mach-gta02.c
+++ b/arch/arm/mach-s3c24xx/mach-gta02.c
@@ -81,6 +81,7 @@
 #include <plat/gpio-cfg.h>
 #include <plat/pm.h>
 #include <plat/regs-serial.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 #include "gta02.h"
@@ -501,6 +502,7 @@ static void __init gta02_map_io(void)
         s3c24xx_init_io(gta02_iodesc, ARRAY_SIZE(gta02_iodesc));
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(gta02_uartcfgs, ARRAY_SIZE(gta02_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 
@@ -589,6 +591,6 @@ MACHINE_START(NEO1973_GTA02, "GTA02")
         .map_io         = gta02_map_io,
         .init_irq       = s3c24xx_init_irq,
         .init_machine   = gta02_machine_init,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-h1940.c b/arch/arm/mach-s3c24xx/mach-h1940.c
index 79bc0830d740..8dd660102846 100644
--- a/arch/arm/mach-s3c24xx/mach-h1940.c
+++ b/arch/arm/mach-s3c24xx/mach-h1940.c
@@ -62,7 +62,7 @@
 #include <plat/pll.h>
 #include <plat/pm.h>
 #include <plat/regs-serial.h>
-
+#include <plat/samsung-time.h>
 
 #include "common.h"
 #include "h1940.h"
@@ -646,6 +646,7 @@ static void __init h1940_map_io(void)
         s3c24xx_init_io(h1940_iodesc, ARRAY_SIZE(h1940_iodesc));
         s3c24xx_init_clocks(0);
         s3c24xx_init_uarts(h1940_uartcfgs, ARRAY_SIZE(h1940_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 
         /* setup PM */
 
@@ -741,6 +742,6 @@ MACHINE_START(H1940, "IPAQ-H1940")
         .reserve        = h1940_reserve,
         .init_irq       = h1940_init_irq,
         .init_machine   = h1940_init,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-jive.c b/arch/arm/mach-s3c24xx/mach-jive.c
index 54e83c1f780c..aade943288c7 100644
--- a/arch/arm/mach-s3c24xx/mach-jive.c
+++ b/arch/arm/mach-s3c24xx/mach-jive.c
@@ -46,14 +46,15 @@
 #include <linux/mtd/nand_ecc.h>
 #include <linux/mtd/partitions.h>
 
-#include <plat/s3c2412.h>
 #include <plat/gpio-cfg.h>
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/pm.h>
 #include <linux/platform_data/usb-s3c2410_udc.h>
+#include <plat/samsung-time.h>
 
+#include "common.h"
 #include "s3c2412-power.h"
 
 static struct map_desc jive_iodesc[] __initdata = {
@@ -506,6 +507,7 @@ static void __init jive_map_io(void)
         s3c24xx_init_io(jive_iodesc, ARRAY_SIZE(jive_iodesc));
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(jive_uartcfgs, ARRAY_SIZE(jive_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void jive_power_off(void)
@@ -661,6 +663,6 @@ MACHINE_START(JIVE, "JIVE")
         .init_irq       = s3c24xx_init_irq,
         .map_io         = jive_map_io,
         .init_machine   = jive_machine_init,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c2412_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-mini2440.c b/arch/arm/mach-s3c24xx/mach-mini2440.c
index 2865e5919f2c..29f106cb370e 100644
--- a/arch/arm/mach-s3c24xx/mach-mini2440.c
+++ b/arch/arm/mach-s3c24xx/mach-mini2440.c
@@ -56,6 +56,7 @@
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
+#include <plat/samsung-time.h>
 
 #include <sound/s3c24xx_uda134x.h>
 
@@ -525,6 +526,7 @@ static void __init mini2440_map_io(void)
         s3c24xx_init_io(mini2440_iodesc, ARRAY_SIZE(mini2440_iodesc));
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(mini2440_uartcfgs, ARRAY_SIZE(mini2440_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 /*
@@ -687,6 +689,6 @@ MACHINE_START(MINI2440, "MINI2440")
         .map_io         = mini2440_map_io,
         .init_machine   = mini2440_init,
         .init_irq       = s3c24xx_init_irq,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-n30.c b/arch/arm/mach-s3c24xx/mach-n30.c
index d9d04b240295..73a690f431e6 100644
--- a/arch/arm/mach-s3c24xx/mach-n30.c
+++ b/arch/arm/mach-s3c24xx/mach-n30.c
@@ -48,8 +48,8 @@
 #include <plat/cpu.h>
 #include <plat/devs.h>
 #include <linux/platform_data/mmc-s3cmci.h>
-#include <plat/s3c2410.h>
 #include <linux/platform_data/usb-s3c2410_udc.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 
@@ -536,6 +536,7 @@ static void __init n30_map_io(void)
         n30_hwinit();
         s3c24xx_init_clocks(0);
         s3c24xx_init_uarts(n30_uartcfgs, ARRAY_SIZE(n30_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 /* GPB3 is the line that controls the pull-up for the USB D+ line */
@@ -589,7 +590,7 @@ MACHINE_START(N30, "Acer-N30")
                                 Ben Dooks <ben-linux@fluff.org>
         */
         .atag_offset    = 0x100,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .init_machine   = n30_init,
         .init_irq       = s3c24xx_init_irq,
         .map_io         = n30_map_io,
@@ -600,7 +601,7 @@ MACHINE_START(N35, "Acer-N35")
         /* Maintainer: Christer Weinigel <christer@weinigel.se>
         */
         .atag_offset    = 0x100,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .init_machine   = n30_init,
         .init_irq       = s3c24xx_init_irq,
         .map_io         = n30_map_io,
diff --git a/arch/arm/mach-s3c24xx/mach-nexcoder.c b/arch/arm/mach-s3c24xx/mach-nexcoder.c
index a454e2461860..5c826d10a66d 100644
--- a/arch/arm/mach-s3c24xx/mach-nexcoder.c
+++ b/arch/arm/mach-s3c24xx/mach-nexcoder.c
@@ -41,11 +41,10 @@
 #include <linux/platform_data/i2c-s3c2410.h>
 
 #include <plat/gpio-cfg.h>
-#include <plat/s3c2410.h>
-#include <plat/s3c244x.h>
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 
@@ -137,6 +136,7 @@ static void __init nexcoder_map_io(void)
         s3c24xx_init_io(nexcoder_iodesc, ARRAY_SIZE(nexcoder_iodesc));
         s3c24xx_init_clocks(0);
         s3c24xx_init_uarts(nexcoder_uartcfgs, ARRAY_SIZE(nexcoder_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 
         nexcoder_sensorboard_init();
 }
@@ -153,6 +153,6 @@ MACHINE_START(NEXCODER_2440, "NexVision - Nexcoder 2440")
         .map_io         = nexcoder_map_io,
         .init_machine   = nexcoder_init,
         .init_irq       = s3c24xx_init_irq,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-osiris.c b/arch/arm/mach-s3c24xx/mach-osiris.c
index ae2cbdf3e3ca..4c90ffda4e11 100644
--- a/arch/arm/mach-s3c24xx/mach-osiris.c
+++ b/arch/arm/mach-s3c24xx/mach-osiris.c
@@ -45,6 +45,7 @@
 #include <plat/devs.h>
 #include <plat/gpio-cfg.h>
 #include <plat/regs-serial.h>
+#include <plat/samsung-time.h>
 
 #include <mach/hardware.h>
 #include <mach/regs-gpio.h>
@@ -384,6 +385,7 @@ static void __init osiris_map_io(void)
         s3c24xx_init_io(osiris_iodesc, ARRAY_SIZE(osiris_iodesc));
         s3c24xx_init_clocks(0);
         s3c24xx_init_uarts(osiris_uartcfgs, ARRAY_SIZE(osiris_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 
         /* check for the newer revision boards with large page nand */
 
@@ -426,6 +428,6 @@ MACHINE_START(OSIRIS, "Simtec-OSIRIS")
         .map_io         = osiris_map_io,
         .init_irq       = s3c24xx_init_irq,
         .init_machine   = osiris_init,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-otom.c b/arch/arm/mach-s3c24xx/mach-otom.c
index 40a47d6c6a85..7b8670746b6a 100644
--- a/arch/arm/mach-s3c24xx/mach-otom.c
+++ b/arch/arm/mach-s3c24xx/mach-otom.c
@@ -33,7 +33,7 @@
 #include <plat/cpu.h>
 #include <plat/devs.h>
 #include <plat/regs-serial.h>
-#include <plat/s3c2410.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 #include "otom.h"
@@ -102,6 +102,7 @@ static void __init otom11_map_io(void)
         s3c24xx_init_io(otom11_iodesc, ARRAY_SIZE(otom11_iodesc));
         s3c24xx_init_clocks(0);
         s3c24xx_init_uarts(otom11_uartcfgs, ARRAY_SIZE(otom11_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init otom11_init(void)
@@ -116,6 +117,6 @@ MACHINE_START(OTOM, "Nex Vision - Otom 1.1")
         .map_io         = otom11_map_io,
         .init_machine   = otom11_init,
         .init_irq       = s3c24xx_init_irq,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-qt2410.c b/arch/arm/mach-s3c24xx/mach-qt2410.c
index 56175f0941b1..71cf29b12d1f 100644
--- a/arch/arm/mach-s3c24xx/mach-qt2410.c
+++ b/arch/arm/mach-s3c24xx/mach-qt2410.c
@@ -55,13 +55,14 @@
 #include <linux/platform_data/usb-s3c2410_udc.h>
 #include <linux/platform_data/i2c-s3c2410.h>
 
-#include <plat/common-smdk.h>
 #include <plat/gpio-cfg.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/pm.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
+#include "common-smdk.h"
 
 static struct map_desc qt2410_iodesc[] __initdata = {
         { 0xe0000000, __phys_to_pfn(S3C2410_CS3+0x01000000), SZ_1M, MT_DEVICE }
@@ -304,6 +305,7 @@ static void __init qt2410_map_io(void)
         s3c24xx_init_io(qt2410_iodesc, ARRAY_SIZE(qt2410_iodesc));
         s3c24xx_init_clocks(12*1000*1000);
         s3c24xx_init_uarts(smdk2410_uartcfgs, ARRAY_SIZE(smdk2410_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init qt2410_machine_init(void)
@@ -343,6 +345,6 @@ MACHINE_START(QT2410, "QT2410")
         .map_io         = qt2410_map_io,
         .init_irq       = s3c24xx_init_irq,
         .init_machine   = qt2410_machine_init,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-rx1950.c b/arch/arm/mach-s3c24xx/mach-rx1950.c
index 1f9ba2ae5288..799af43b4e6a 100644
--- a/arch/arm/mach-s3c24xx/mach-rx1950.c
+++ b/arch/arm/mach-s3c24xx/mach-rx1950.c
@@ -58,6 +58,7 @@
 #include <plat/pm.h>
 #include <plat/regs-iic.h>
 #include <plat/regs-serial.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 #include "h1940.h"
@@ -741,6 +742,7 @@ static void __init rx1950_map_io(void)
         s3c24xx_init_io(rx1950_iodesc, ARRAY_SIZE(rx1950_iodesc));
         s3c24xx_init_clocks(16934000);
         s3c24xx_init_uarts(rx1950_uartcfgs, ARRAY_SIZE(rx1950_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 
         /* setup PM */
 
@@ -813,6 +815,6 @@ MACHINE_START(RX1950, "HP iPAQ RX1950")
         .reserve        = rx1950_reserve,
         .init_irq = s3c24xx_init_irq,
         .init_machine = rx1950_init_machine,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-rx3715.c b/arch/arm/mach-s3c24xx/mach-rx3715.c
index f20418a2fb1b..0a3c96452f0f 100644
--- a/arch/arm/mach-s3c24xx/mach-rx3715.c
+++ b/arch/arm/mach-s3c24xx/mach-rx3715.c
@@ -49,6 +49,7 @@
 #include <plat/devs.h>
 #include <plat/pm.h>
 #include <plat/regs-serial.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 #include "h1940.h"
@@ -179,6 +180,7 @@ static void __init rx3715_map_io(void)
         s3c24xx_init_io(rx3715_iodesc, ARRAY_SIZE(rx3715_iodesc));
         s3c24xx_init_clocks(16934000);
         s3c24xx_init_uarts(rx3715_uartcfgs, ARRAY_SIZE(rx3715_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 /* H1940 and RX3715 need to reserve this for suspend */
@@ -212,6 +214,6 @@ MACHINE_START(RX3715, "IPAQ-RX3715")
         .reserve        = rx3715_reserve,
         .init_irq       = rx3715_init_irq,
         .init_machine   = rx3715_init_machine,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2410.c b/arch/arm/mach-s3c24xx/mach-smdk2410.c
index e184bfa9613a..fd96f7fc330c 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2410.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2410.c
@@ -51,10 +51,10 @@
 
 #include <plat/devs.h>
 #include <plat/cpu.h>
-
-#include <plat/common-smdk.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
+#include "common-smdk.h"
 
 static struct map_desc smdk2410_iodesc[] __initdata = {
   /* nothing here yet */
@@ -101,6 +101,7 @@ static void __init smdk2410_map_io(void)
         s3c24xx_init_io(smdk2410_iodesc, ARRAY_SIZE(smdk2410_iodesc));
         s3c24xx_init_clocks(0);
         s3c24xx_init_uarts(smdk2410_uartcfgs, ARRAY_SIZE(smdk2410_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init smdk2410_init(void)
@@ -117,6 +118,6 @@ MACHINE_START(SMDK2410, "SMDK2410") /* @TODO: request a new identifier and switc
         .map_io         = smdk2410_map_io,
         .init_irq       = s3c24xx_init_irq,
         .init_machine   = smdk2410_init,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2413.c b/arch/arm/mach-s3c24xx/mach-smdk2413.c
index 86d7847c9d45..8e3f1d9bbb7c 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2413.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2413.c
@@ -41,13 +41,13 @@
 #include <linux/platform_data/i2c-s3c2410.h>
 #include <mach/fb.h>
 
-#include <plat/s3c2410.h>
-#include <plat/s3c2412.h>
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
+#include <plat/samsung-time.h>
 
-#include <plat/common-smdk.h>
+#include "common.h"
+#include "common-smdk.h"
 
 static struct map_desc smdk2413_iodesc[] __initdata = {
 };
@@ -106,6 +106,7 @@ static void __init smdk2413_map_io(void)
         s3c24xx_init_io(smdk2413_iodesc, ARRAY_SIZE(smdk2413_iodesc));
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(smdk2413_uartcfgs, ARRAY_SIZE(smdk2413_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init smdk2413_machine_init(void)
@@ -132,7 +133,7 @@ MACHINE_START(S3C2413, "S3C2413")
         .init_irq       = s3c24xx_init_irq,
         .map_io         = smdk2413_map_io,
         .init_machine   = smdk2413_machine_init,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c2412_restart,
 MACHINE_END
 
@@ -144,7 +145,7 @@ MACHINE_START(SMDK2412, "SMDK2412")
         .init_irq       = s3c24xx_init_irq,
         .map_io         = smdk2413_map_io,
         .init_machine   = smdk2413_machine_init,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c2412_restart,
 MACHINE_END
 
@@ -156,6 +157,6 @@ MACHINE_START(SMDK2413, "SMDK2413")
         .init_irq       = s3c24xx_init_irq,
         .map_io         = smdk2413_map_io,
         .init_machine   = smdk2413_machine_init,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c2412_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2416.c b/arch/arm/mach-s3c24xx/mach-smdk2416.c
index ebb2e61f3d07..cb46847c66b4 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2416.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2416.c
@@ -42,7 +42,6 @@
 #include <linux/platform_data/leds-s3c24xx.h>
 #include <linux/platform_data/i2c-s3c2410.h>
 
-#include <plat/s3c2416.h>
 #include <plat/gpio-cfg.h>
 #include <plat/clock.h>
 #include <plat/devs.h>
@@ -51,10 +50,12 @@
 #include <plat/sdhci.h>
 #include <linux/platform_data/usb-s3c2410_udc.h>
 #include <linux/platform_data/s3c-hsudc.h>
+#include <plat/samsung-time.h>
 
 #include <plat/fb.h>
 
-#include <plat/common-smdk.h>
+#include "common.h"
+#include "common-smdk.h"
 
 static struct map_desc smdk2416_iodesc[] __initdata = {
         /* ISA IO Space map (memory space selected by A24) */
@@ -221,6 +222,7 @@ static void __init smdk2416_map_io(void)
         s3c24xx_init_io(smdk2416_iodesc, ARRAY_SIZE(smdk2416_iodesc));
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(smdk2416_uartcfgs, ARRAY_SIZE(smdk2416_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init smdk2416_machine_init(void)
@@ -253,6 +255,6 @@ MACHINE_START(SMDK2416, "SMDK2416")
         .init_irq       = s3c2416_init_irq,
         .map_io         = smdk2416_map_io,
         .init_machine   = smdk2416_machine_init,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c2416_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2440.c b/arch/arm/mach-s3c24xx/mach-smdk2440.c
index 08cc38c8a4ae..f56cb08e6d1c 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2440.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2440.c
@@ -38,15 +38,13 @@
 #include <mach/fb.h>
 #include <linux/platform_data/i2c-s3c2410.h>
 
-#include <plat/s3c2410.h>
-#include <plat/s3c244x.h>
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
-
-#include <plat/common-smdk.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
+#include "common-smdk.h"
 
 static struct map_desc smdk2440_iodesc[] __initdata = {
         /* ISA IO Space map (memory space selected by A24) */
@@ -163,6 +161,7 @@ static void __init smdk2440_map_io(void)
         s3c24xx_init_io(smdk2440_iodesc, ARRAY_SIZE(smdk2440_iodesc));
         s3c24xx_init_clocks(16934400);
         s3c24xx_init_uarts(smdk2440_uartcfgs, ARRAY_SIZE(smdk2440_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init smdk2440_machine_init(void)
@@ -181,6 +180,6 @@ MACHINE_START(S3C2440, "SMDK2440")
         .init_irq       = s3c24xx_init_irq,
         .map_io         = smdk2440_map_io,
         .init_machine   = smdk2440_machine_init,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2443.c b/arch/arm/mach-s3c24xx/mach-smdk2443.c
index fc65d74d3c73..9435c3bef18a 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2443.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2443.c
@@ -38,13 +38,13 @@
 #include <mach/fb.h>
 #include <linux/platform_data/i2c-s3c2410.h>
 
-#include <plat/s3c2410.h>
-#include <plat/s3c2443.h>
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
+#include <plat/samsung-time.h>
 
-#include <plat/common-smdk.h>
+#include "common.h"
+#include "common-smdk.h"
 
 static struct map_desc smdk2443_iodesc[] __initdata = {
         /* ISA IO Space map (memory space selected by A24) */
@@ -122,6 +122,7 @@ static void __init smdk2443_map_io(void)
         s3c24xx_init_io(smdk2443_iodesc, ARRAY_SIZE(smdk2443_iodesc));
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(smdk2443_uartcfgs, ARRAY_SIZE(smdk2443_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init smdk2443_machine_init(void)
@@ -143,6 +144,6 @@ MACHINE_START(SMDK2443, "SMDK2443")
         .init_irq       = s3c2443_init_irq,
         .map_io         = smdk2443_map_io,
         .init_machine   = smdk2443_machine_init,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c2443_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-tct_hammer.c b/arch/arm/mach-s3c24xx/mach-tct_hammer.c
index 24b3d79e7b2c..31dfe589e349 100644
--- a/arch/arm/mach-s3c24xx/mach-tct_hammer.c
+++ b/arch/arm/mach-s3c24xx/mach-tct_hammer.c
@@ -53,6 +53,7 @@
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/map.h>
 #include <linux/mtd/physmap.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 
@@ -136,6 +137,7 @@ static void __init tct_hammer_map_io(void)
         s3c24xx_init_io(tct_hammer_iodesc, ARRAY_SIZE(tct_hammer_iodesc));
         s3c24xx_init_clocks(0);
         s3c24xx_init_uarts(tct_hammer_uartcfgs, ARRAY_SIZE(tct_hammer_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init tct_hammer_init(void)
@@ -149,6 +151,6 @@ MACHINE_START(TCT_HAMMER, "TCT_HAMMER")
         .map_io         = tct_hammer_map_io,
         .init_irq       = s3c24xx_init_irq,
         .init_machine   = tct_hammer_init,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-vr1000.c b/arch/arm/mach-s3c24xx/mach-vr1000.c
index ec42d1e4e465..deeb8a0a4034 100644
--- a/arch/arm/mach-s3c24xx/mach-vr1000.c
+++ b/arch/arm/mach-s3c24xx/mach-vr1000.c
@@ -45,6 +45,7 @@
 #include <plat/cpu.h>
 #include <plat/devs.h>
 #include <plat/regs-serial.h>
+#include <plat/samsung-time.h>
 
 #include "bast.h"
 #include "common.h"
@@ -332,6 +333,7 @@ static void __init vr1000_map_io(void)
         s3c24xx_init_io(vr1000_iodesc, ARRAY_SIZE(vr1000_iodesc));
         s3c24xx_init_clocks(0);
         s3c24xx_init_uarts(vr1000_uartcfgs, ARRAY_SIZE(vr1000_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init vr1000_init(void)
@@ -354,6 +356,6 @@ MACHINE_START(VR1000, "Thorcom-VR1000")
         .map_io         = vr1000_map_io,
         .init_machine   = vr1000_init,
         .init_irq       = s3c24xx_init_irq,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-vstms.c b/arch/arm/mach-s3c24xx/mach-vstms.c
index 3e2bfddc9df1..622a1ed24509 100644
--- a/arch/arm/mach-s3c24xx/mach-vstms.c
+++ b/arch/arm/mach-s3c24xx/mach-vstms.c
@@ -41,12 +41,12 @@
 #include <linux/platform_data/i2c-s3c2410.h>
 #include <linux/platform_data/mtd-nand-s3c2410.h>
 
-#include <plat/s3c2410.h>
-#include <plat/s3c2412.h>
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
+#include <plat/samsung-time.h>
 
+#include "common.h"
 
 static struct map_desc vstms_iodesc[] __initdata = {
 };
@@ -143,6 +143,7 @@ static void __init vstms_map_io(void)
         s3c24xx_init_io(vstms_iodesc, ARRAY_SIZE(vstms_iodesc));
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(vstms_uartcfgs, ARRAY_SIZE(vstms_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init vstms_init(void)
@@ -160,6 +161,6 @@ MACHINE_START(VSTMS, "VSTMS")
         .init_irq       = s3c24xx_init_irq,
         .init_machine   = vstms_init,
         .map_io         = vstms_map_io,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c2412_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/pm-s3c2412.c b/arch/arm/mach-s3c24xx/pm-s3c2412.c
index 668a78a8b195..4c4bc1c83b77 100644
--- a/arch/arm/mach-s3c24xx/pm-s3c2412.c
+++ b/arch/arm/mach-s3c24xx/pm-s3c2412.c
@@ -29,7 +29,6 @@
 
 #include <plat/cpu.h>
 #include <plat/pm.h>
-#include <plat/s3c2412.h>
 
 #include "regs-dsc.h"
 #include "s3c2412-power.h"
diff --git a/arch/arm/mach-s3c24xx/s3c2410.c b/arch/arm/mach-s3c24xx/s3c2410.c
index 9ebef95da721..d850ea5adac2 100644
--- a/arch/arm/mach-s3c24xx/s3c2410.c
+++ b/arch/arm/mach-s3c24xx/s3c2410.c
@@ -37,7 +37,6 @@
 #include <mach/regs-clock.h>
 #include <plat/regs-serial.h>
 
-#include <plat/s3c2410.h>
 #include <plat/cpu.h>
 #include <plat/devs.h>
 #include <plat/clock.h>
diff --git a/arch/arm/mach-s3c24xx/s3c2412.c b/arch/arm/mach-s3c24xx/s3c2412.c
index 0d592159a5c3..0f864d4c97de 100644
--- a/arch/arm/mach-s3c24xx/s3c2412.c
+++ b/arch/arm/mach-s3c24xx/s3c2412.c
@@ -44,7 +44,6 @@
 #include <plat/pm.h>
 #include <plat/regs-serial.h>
 #include <plat/regs-spi.h>
-#include <plat/s3c2412.h>
 
 #include "common.h"
 #include "regs-dsc.h"
diff --git a/arch/arm/mach-s3c24xx/s3c2416.c b/arch/arm/mach-s3c24xx/s3c2416.c
index e30476db0295..b9c5d382dafb 100644
--- a/arch/arm/mach-s3c24xx/s3c2416.c
+++ b/arch/arm/mach-s3c24xx/s3c2416.c
@@ -50,7 +50,6 @@
 #include <plat/gpio-core.h>
 #include <plat/gpio-cfg.h>
 #include <plat/gpio-cfg-helpers.h>
-#include <plat/s3c2416.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/sdhci.h>
diff --git a/arch/arm/mach-s3c24xx/s3c2440.c b/arch/arm/mach-s3c24xx/s3c2440.c
index 559e394e8989..5f9d6569475d 100644
--- a/arch/arm/mach-s3c24xx/s3c2440.c
+++ b/arch/arm/mach-s3c24xx/s3c2440.c
@@ -33,7 +33,6 @@
 
 #include <plat/devs.h>
 #include <plat/cpu.h>
-#include <plat/s3c244x.h>
 #include <plat/pm.h>
 
 #include <plat/gpio-core.h>
diff --git a/arch/arm/mach-s3c24xx/s3c2442.c b/arch/arm/mach-s3c24xx/s3c2442.c
index f732826c2359..6819961f6b19 100644
--- a/arch/arm/mach-s3c24xx/s3c2442.c
+++ b/arch/arm/mach-s3c24xx/s3c2442.c
@@ -44,7 +44,6 @@
 
 #include <plat/clock.h>
 #include <plat/cpu.h>
-#include <plat/s3c244x.h>
 #include <plat/pm.h>
 
 #include <plat/gpio-core.h>
diff --git a/arch/arm/mach-s3c24xx/s3c2443.c b/arch/arm/mach-s3c24xx/s3c2443.c
index 165b6a6b3daa..8328cd65bf3d 100644
--- a/arch/arm/mach-s3c24xx/s3c2443.c
+++ b/arch/arm/mach-s3c24xx/s3c2443.c
@@ -36,7 +36,6 @@
 #include <plat/gpio-core.h>
 #include <plat/gpio-cfg.h>
 #include <plat/gpio-cfg-helpers.h>
-#include <plat/s3c2443.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/fb-core.h>
diff --git a/arch/arm/mach-s3c24xx/s3c244x.c b/arch/arm/mach-s3c24xx/s3c244x.c
index ad2671baa910..2a35edb67354 100644
--- a/arch/arm/mach-s3c24xx/s3c244x.c
+++ b/arch/arm/mach-s3c24xx/s3c244x.c
@@ -37,8 +37,6 @@
 #include <plat/regs-serial.h>
 #include <mach/regs-gpio.h>
 
-#include <plat/s3c2410.h>
-#include <plat/s3c244x.h>
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c64xx/Kconfig
index 131c86284711..283cb77d4721 100644
--- a/arch/arm/mach-s3c64xx/Kconfig
+++ b/arch/arm/mach-s3c64xx/Kconfig
@@ -17,11 +17,13 @@ config PLAT_S3C64XX
 # Configuration options for the S3C6410 CPU
 
 config CPU_S3C6400
+        select SAMSUNG_HRT
         bool
         help
           Enable S3C6400 CPU support
 
 config CPU_S3C6410
+        select SAMSUNG_HRT
         bool
         help
           Enable S3C6410 CPU support
diff --git a/arch/arm/mach-s3c64xx/mach-anw6410.c b/arch/arm/mach-s3c64xx/mach-anw6410.c
index 728eef3296b2..35e3f54574ef 100644
--- a/arch/arm/mach-s3c64xx/mach-anw6410.c
+++ b/arch/arm/mach-s3c64xx/mach-anw6410.c
@@ -49,6 +49,7 @@
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <mach/regs-gpio.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 #include "regs-modem.h"
@@ -208,6 +209,7 @@ static void __init anw6410_map_io(void)
         s3c64xx_init_io(anw6410_iodesc, ARRAY_SIZE(anw6410_iodesc));
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(anw6410_uartcfgs, ARRAY_SIZE(anw6410_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 
         anw6410_lcd_mode_set();
 }
@@ -232,6 +234,6 @@ MACHINE_START(ANW6410, "A&W6410")
         .map_io         = anw6410_map_io,
         .init_machine   = anw6410_machine_init,
         .init_late      = s3c64xx_init_late,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c64xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c64xx/mach-crag6410.c
index 1acf02bace57..8ad88ace795a 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410.c
@@ -64,6 +64,7 @@
 #include <plat/adc.h>
 #include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/pm.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 #include "crag6410.h"
@@ -744,6 +745,7 @@ static void __init crag6410_map_io(void)
         s3c64xx_init_io(NULL, 0);
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(crag6410_uartcfgs, ARRAY_SIZE(crag6410_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 
         /* LCD type and Bypass set by bootloader */
 }
@@ -868,6 +870,6 @@ MACHINE_START(WLF_CRAGG_6410, "Wolfson Cragganmore 6410")
         .map_io         = crag6410_map_io,
         .init_machine   = crag6410_machine_init,
         .init_late      = s3c64xx_init_late,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c64xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-hmt.c b/arch/arm/mach-s3c64xx/mach-hmt.c
index 7212eb9cfeb9..5b7f357d8c22 100644
--- a/arch/arm/mach-s3c64xx/mach-hmt.c
+++ b/arch/arm/mach-s3c64xx/mach-hmt.c
@@ -41,6 +41,7 @@
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 
@@ -248,6 +249,7 @@ static void __init hmt_map_io(void)
         s3c64xx_init_io(hmt_iodesc, ARRAY_SIZE(hmt_iodesc));
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(hmt_uartcfgs, ARRAY_SIZE(hmt_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init hmt_machine_init(void)
@@ -275,6 +277,6 @@ MACHINE_START(HMT, "Airgoo-HMT")
         .map_io         = hmt_map_io,
         .init_machine   = hmt_machine_init,
         .init_late      = s3c64xx_init_late,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c64xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-mini6410.c b/arch/arm/mach-s3c64xx/mach-mini6410.c
index 4b41fcdaa7b6..fc043e3ecdf8 100644
--- a/arch/arm/mach-s3c64xx/mach-mini6410.c
+++ b/arch/arm/mach-s3c64xx/mach-mini6410.c
@@ -41,6 +41,7 @@
 
 #include <video/platform_lcd.h>
 #include <video/samsung_fimd.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 #include "regs-modem.h"
@@ -232,6 +233,7 @@ static void __init mini6410_map_io(void)
         s3c64xx_init_io(NULL, 0);
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(mini6410_uartcfgs, ARRAY_SIZE(mini6410_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 
         /* set the LCD type */
         tmp = __raw_readl(S3C64XX_SPCON);
@@ -354,6 +356,6 @@ MACHINE_START(MINI6410, "MINI6410")
         .map_io         = mini6410_map_io,
         .init_machine   = mini6410_machine_init,
         .init_late      = s3c64xx_init_late,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c64xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-ncp.c b/arch/arm/mach-s3c64xx/mach-ncp.c
index 8d3cedd995ff..7e2c3908f1f8 100644
--- a/arch/arm/mach-s3c64xx/mach-ncp.c
+++ b/arch/arm/mach-s3c64xx/mach-ncp.c
@@ -43,6 +43,7 @@
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 
@@ -87,6 +88,7 @@ static void __init ncp_map_io(void)
         s3c64xx_init_io(ncp_iodesc, ARRAY_SIZE(ncp_iodesc));
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(ncp_uartcfgs, ARRAY_SIZE(ncp_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init ncp_machine_init(void)
@@ -103,6 +105,6 @@ MACHINE_START(NCP, "NCP")
         .map_io         = ncp_map_io,
         .init_machine   = ncp_machine_init,
         .init_late      = s3c64xx_init_late,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c64xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-real6410.c b/arch/arm/mach-s3c64xx/mach-real6410.c
index fa12bd21ad82..8bed37b3d5ac 100644
--- a/arch/arm/mach-s3c64xx/mach-real6410.c
+++ b/arch/arm/mach-s3c64xx/mach-real6410.c
@@ -42,6 +42,7 @@
 
 #include <video/platform_lcd.h>
 #include <video/samsung_fimd.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 #include "regs-modem.h"
@@ -211,6 +212,7 @@ static void __init real6410_map_io(void)
         s3c64xx_init_io(NULL, 0);
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(real6410_uartcfgs, ARRAY_SIZE(real6410_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 
         /* set the LCD type */
         tmp = __raw_readl(S3C64XX_SPCON);
@@ -333,6 +335,6 @@ MACHINE_START(REAL6410, "REAL6410")
         .map_io         = real6410_map_io,
         .init_machine   = real6410_machine_init,
         .init_late      = s3c64xx_init_late,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c64xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-smartq.c b/arch/arm/mach-s3c64xx/mach-smartq.c
index fc3e9b32e26f..58ac99041274 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq.c
@@ -38,6 +38,7 @@
 #include <linux/platform_data/touchscreen-s3c2410.h>
 
 #include <video/platform_lcd.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 #include "regs-modem.h"
@@ -378,6 +379,7 @@ void __init smartq_map_io(void)
         s3c64xx_init_io(smartq_iodesc, ARRAY_SIZE(smartq_iodesc));
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(smartq_uartcfgs, ARRAY_SIZE(smartq_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 
         smartq_lcd_mode_set();
 }
diff --git a/arch/arm/mach-s3c64xx/mach-smartq5.c b/arch/arm/mach-s3c64xx/mach-smartq5.c
index ca2afcfce573..8aca5daf3d05 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq5.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq5.c
@@ -28,6 +28,7 @@
 #include <plat/devs.h>
 #include <plat/fb.h>
 #include <plat/gpio-cfg.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 #include "mach-smartq.h"
@@ -155,6 +156,6 @@ MACHINE_START(SMARTQ5, "SmartQ 5")
         .map_io         = smartq_map_io,
         .init_machine   = smartq5_machine_init,
         .init_late      = s3c64xx_init_late,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c64xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-smartq7.c b/arch/arm/mach-s3c64xx/mach-smartq7.c
index 37bb0c632a5e..a052e107c0b4 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq7.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq7.c
@@ -28,6 +28,7 @@
 #include <plat/devs.h>
 #include <plat/fb.h>
 #include <plat/gpio-cfg.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 #include "mach-smartq.h"
@@ -171,6 +172,6 @@ MACHINE_START(SMARTQ7, "SmartQ 7")
         .map_io         = smartq_map_io,
         .init_machine   = smartq7_machine_init,
         .init_late      = s3c64xx_init_late,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c64xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6400.c b/arch/arm/mach-s3c64xx/mach-smdk6400.c
index a392869c8342..d70c0843aea2 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6400.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6400.c
@@ -35,6 +35,7 @@
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <linux/platform_data/i2c-s3c2410.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 
@@ -66,6 +67,7 @@ static void __init smdk6400_map_io(void)
         s3c64xx_init_io(smdk6400_iodesc, ARRAY_SIZE(smdk6400_iodesc));
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(smdk6400_uartcfgs, ARRAY_SIZE(smdk6400_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static struct platform_device *smdk6400_devices[] __initdata = {
@@ -92,6 +94,6 @@ MACHINE_START(SMDK6400, "SMDK6400")
         .map_io         = smdk6400_map_io,
         .init_machine   = smdk6400_machine_init,
         .init_late      = s3c64xx_init_late,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c64xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c
index ba7544e2d04d..bd3295a19ad7 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6410.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c
@@ -69,6 +69,7 @@
 #include <linux/platform_data/touchscreen-s3c2410.h>
 #include <plat/keypad.h>
 #include <plat/backlight.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 #include "regs-modem.h"
@@ -634,6 +635,7 @@ static void __init smdk6410_map_io(void)
         s3c64xx_init_io(smdk6410_iodesc, ARRAY_SIZE(smdk6410_iodesc));
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(smdk6410_uartcfgs, ARRAY_SIZE(smdk6410_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 
         /* set the LCD type */
 
@@ -702,6 +704,6 @@ MACHINE_START(SMDK6410, "SMDK6410")
         .map_io         = smdk6410_map_io,
         .init_machine   = smdk6410_machine_init,
         .init_late      = s3c64xx_init_late,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c64xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s5p64x0/Kconfig b/arch/arm/mach-s5p64x0/Kconfig
index e8742cb7ddd9..5a707bdb9ea0 100644
--- a/arch/arm/mach-s5p64x0/Kconfig
+++ b/arch/arm/mach-s5p64x0/Kconfig
@@ -9,16 +9,16 @@ if ARCH_S5P64X0
 
 config CPU_S5P6440
         bool
-        select S5P_HRT
         select S5P_SLEEP if PM
         select SAMSUNG_DMADEV
+        select SAMSUNG_HRT
         select SAMSUNG_WAKEMASK if PM
         help
           Enable S5P6440 CPU support
 
 config CPU_S5P6450
         bool
-        select S5P_HRT
+        select SAMSUNG_HRT
         select S5P_SLEEP if PM
         select SAMSUNG_DMADEV
         select SAMSUNG_WAKEMASK if PM
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6440.c b/arch/arm/mach-s5p64x0/mach-smdk6440.c
index e23723a5a214..73f71a698a34 100644
--- a/arch/arm/mach-s5p64x0/mach-smdk6440.c
+++ b/arch/arm/mach-s5p64x0/mach-smdk6440.c
@@ -48,7 +48,7 @@
 #include <plat/pll.h>
 #include <plat/adc.h>
 #include <linux/platform_data/touchscreen-s3c2410.h>
-#include <plat/s5p-time.h>
+#include <plat/samsung-time.h>
 #include <plat/backlight.h>
 #include <plat/fb.h>
 #include <plat/sdhci.h>
@@ -229,7 +229,7 @@ static void __init smdk6440_map_io(void)
         s5p64x0_init_io(NULL, 0);
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(smdk6440_uartcfgs, ARRAY_SIZE(smdk6440_uartcfgs));
-        s5p_set_timer_source(S5P_PWM3, S5P_PWM4);
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void s5p6440_set_lcd_interface(void)
@@ -273,6 +273,6 @@ MACHINE_START(SMDK6440, "SMDK6440")
         .init_irq       = s5p6440_init_irq,
         .map_io         = smdk6440_map_io,
         .init_machine   = smdk6440_machine_init,
-        .init_time      = s5p_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s5p64x0_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6450.c b/arch/arm/mach-s5p64x0/mach-smdk6450.c
index ca10963a959e..18303e12019f 100644
--- a/arch/arm/mach-s5p64x0/mach-smdk6450.c
+++ b/arch/arm/mach-s5p64x0/mach-smdk6450.c
@@ -48,7 +48,7 @@
 #include <plat/pll.h>
 #include <plat/adc.h>
 #include <linux/platform_data/touchscreen-s3c2410.h>
-#include <plat/s5p-time.h>
+#include <plat/samsung-time.h>
 #include <plat/backlight.h>
 #include <plat/fb.h>
 #include <plat/sdhci.h>
@@ -248,7 +248,7 @@ static void __init smdk6450_map_io(void)
         s5p64x0_init_io(NULL, 0);
         s3c24xx_init_clocks(19200000);
         s3c24xx_init_uarts(smdk6450_uartcfgs, ARRAY_SIZE(smdk6450_uartcfgs));
-        s5p_set_timer_source(S5P_PWM3, S5P_PWM4);
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void s5p6450_set_lcd_interface(void)
@@ -292,6 +292,6 @@ MACHINE_START(SMDK6450, "SMDK6450")
         .init_irq       = s5p6450_init_irq,
         .map_io         = smdk6450_map_io,
         .init_machine   = smdk6450_machine_init,
-        .init_time      = s5p_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s5p64x0_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s5pc100/Kconfig b/arch/arm/mach-s5pc100/Kconfig
index 15170be97a74..2f456a4533ba 100644
--- a/arch/arm/mach-s5pc100/Kconfig
+++ b/arch/arm/mach-s5pc100/Kconfig
@@ -11,6 +11,7 @@ config CPU_S5PC100
         bool
         select S5P_EXT_INT
         select SAMSUNG_DMADEV
+        select SAMSUNG_HRT
         help
           Enable S5PC100 CPU support
 
diff --git a/arch/arm/mach-s5pc100/mach-smdkc100.c b/arch/arm/mach-s5pc100/mach-smdkc100.c
index 185a19583898..8c880f76f274 100644
--- a/arch/arm/mach-s5pc100/mach-smdkc100.c
+++ b/arch/arm/mach-s5pc100/mach-smdkc100.c
@@ -51,6 +51,7 @@
 #include <linux/platform_data/touchscreen-s3c2410.h>
 #include <linux/platform_data/asoc-s3c.h>
 #include <plat/backlight.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 
@@ -221,6 +222,7 @@ static void __init smdkc100_map_io(void)
         s5pc100_init_io(NULL, 0);
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(smdkc100_uartcfgs, ARRAY_SIZE(smdkc100_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init smdkc100_machine_init(void)
@@ -255,6 +257,6 @@ MACHINE_START(SMDKC100, "SMDKC100")
         .init_irq       = s5pc100_init_irq,
         .map_io         = smdkc100_map_io,
         .init_machine   = smdkc100_machine_init,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s5pc100_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig
index 92ad72f0ef98..0963283a7c5d 100644
--- a/arch/arm/mach-s5pv210/Kconfig
+++ b/arch/arm/mach-s5pv210/Kconfig
@@ -12,10 +12,10 @@ if ARCH_S5PV210
 config CPU_S5PV210
         bool
         select S5P_EXT_INT
-        select S5P_HRT
         select S5P_PM if PM
         select S5P_SLEEP if PM
         select SAMSUNG_DMADEV
+        select SAMSUNG_HRT
         help
           Enable S5PV210 CPU support
 
diff --git a/arch/arm/mach-s5pv210/mach-aquila.c b/arch/arm/mach-s5pv210/mach-aquila.c
index 11900a8e88a3..ed2b85485b9d 100644
--- a/arch/arm/mach-s5pv210/mach-aquila.c
+++ b/arch/arm/mach-s5pv210/mach-aquila.c
@@ -38,7 +38,7 @@
 #include <plat/fb.h>
 #include <plat/fimc-core.h>
 #include <plat/sdhci.h>
-#include <plat/s5p-time.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 
@@ -651,7 +651,7 @@ static void __init aquila_map_io(void)
         s5pv210_init_io(NULL, 0);
         s3c24xx_init_clocks(24000000);
         s3c24xx_init_uarts(aquila_uartcfgs, ARRAY_SIZE(aquila_uartcfgs));
-        s5p_set_timer_source(S5P_PWM3, S5P_PWM4);
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init aquila_machine_init(void)
@@ -686,6 +686,6 @@ MACHINE_START(AQUILA, "Aquila")
         .init_irq       = s5pv210_init_irq,
         .map_io         = aquila_map_io,
         .init_machine   = aquila_machine_init,
-        .init_time      = s5p_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s5pv210_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c
index e373de44a8b6..30b24ad84f49 100644
--- a/arch/arm/mach-s5pv210/mach-goni.c
+++ b/arch/arm/mach-s5pv210/mach-goni.c
@@ -47,7 +47,7 @@
 #include <plat/keypad.h>
 #include <plat/sdhci.h>
 #include <plat/clock.h>
-#include <plat/s5p-time.h>
+#include <plat/samsung-time.h>
 #include <plat/mfc.h>
 #include <plat/camport.h>
 
@@ -908,7 +908,7 @@ static void __init goni_map_io(void)
         s5pv210_init_io(NULL, 0);
         s3c24xx_init_clocks(clk_xusbxti.rate);
         s3c24xx_init_uarts(goni_uartcfgs, ARRAY_SIZE(goni_uartcfgs));
-        s5p_set_timer_source(S5P_PWM3, S5P_PWM4);
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init goni_reserve(void)
@@ -973,7 +973,7 @@ MACHINE_START(GONI, "GONI")
         .init_irq       = s5pv210_init_irq,
         .map_io         = goni_map_io,
         .init_machine   = goni_machine_init,
-        .init_time      = s5p_timer_init,
+        .init_time      = samsung_timer_init,
         .reserve        = &goni_reserve,
         .restart        = s5pv210_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s5pv210/mach-smdkc110.c b/arch/arm/mach-s5pv210/mach-smdkc110.c
index 28bd0248a3e2..7c0ed07a78a3 100644
--- a/arch/arm/mach-s5pv210/mach-smdkc110.c
+++ b/arch/arm/mach-s5pv210/mach-smdkc110.c
@@ -29,7 +29,7 @@
 #include <linux/platform_data/ata-samsung_cf.h>
 #include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/pm.h>
-#include <plat/s5p-time.h>
+#include <plat/samsung-time.h>
 #include <plat/mfc.h>
 
 #include "common.h"
@@ -120,7 +120,7 @@ static void __init smdkc110_map_io(void)
         s5pv210_init_io(NULL, 0);
         s3c24xx_init_clocks(24000000);
         s3c24xx_init_uarts(smdkv210_uartcfgs, ARRAY_SIZE(smdkv210_uartcfgs));
-        s5p_set_timer_source(S5P_PWM3, S5P_PWM4);
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init smdkc110_reserve(void)
@@ -153,7 +153,7 @@ MACHINE_START(SMDKC110, "SMDKC110")
         .init_irq       = s5pv210_init_irq,
         .map_io         = smdkc110_map_io,
         .init_machine   = smdkc110_machine_init,
-        .init_time      = s5p_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s5pv210_restart,
         .reserve        = &smdkc110_reserve,
 MACHINE_END
diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c
index 3c73f36869bb..d50b6f124465 100644
--- a/arch/arm/mach-s5pv210/mach-smdkv210.c
+++ b/arch/arm/mach-s5pv210/mach-smdkv210.c
@@ -44,7 +44,7 @@
 #include <plat/keypad.h>
 #include <plat/pm.h>
 #include <plat/fb.h>
-#include <plat/s5p-time.h>
+#include <plat/samsung-time.h>
 #include <plat/backlight.h>
 #include <plat/mfc.h>
 #include <plat/clock.h>
@@ -285,7 +285,7 @@ static void __init smdkv210_map_io(void)
         s5pv210_init_io(NULL, 0);
         s3c24xx_init_clocks(clk_xusbxti.rate);
         s3c24xx_init_uarts(smdkv210_uartcfgs, ARRAY_SIZE(smdkv210_uartcfgs));
-        s5p_set_timer_source(S5P_PWM2, S5P_PWM4);
+        samsung_set_timer_source(SAMSUNG_PWM2, SAMSUNG_PWM4);
 }
 
 static void __init smdkv210_reserve(void)
@@ -329,7 +329,7 @@ MACHINE_START(SMDKV210, "SMDKV210")
         .init_irq       = s5pv210_init_irq,
         .map_io         = smdkv210_map_io,
         .init_machine   = smdkv210_machine_init,
-        .init_time      = s5p_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s5pv210_restart,
         .reserve        = &smdkv210_reserve,
 MACHINE_END
diff --git a/arch/arm/mach-s5pv210/mach-torbreck.c b/arch/arm/mach-s5pv210/mach-torbreck.c
index 2d4c5531819c..579afe89842a 100644
--- a/arch/arm/mach-s5pv210/mach-torbreck.c
+++ b/arch/arm/mach-s5pv210/mach-torbreck.c
@@ -26,7 +26,7 @@
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <linux/platform_data/i2c-s3c2410.h>
-#include <plat/s5p-time.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 
@@ -106,7 +106,7 @@ static void __init torbreck_map_io(void)
         s5pv210_init_io(NULL, 0);
         s3c24xx_init_clocks(24000000);
         s3c24xx_init_uarts(torbreck_uartcfgs, ARRAY_SIZE(torbreck_uartcfgs));
-        s5p_set_timer_source(S5P_PWM3, S5P_PWM4);
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init torbreck_machine_init(void)
@@ -130,6 +130,6 @@ MACHINE_START(TORBRECK, "TORBRECK")
         .init_irq       = s5pv210_init_irq,
         .map_io         = torbreck_map_io,
         .init_machine   = torbreck_machine_init,
-        .init_time      = s5p_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s5pv210_restart,
 MACHINE_END
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index a9d52167e16e..6cb19c6aa9d6 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -25,7 +25,7 @@ config PLAT_S5P
         select PLAT_SAMSUNG
         select S3C_GPIO_TRACK
         select S5P_GPIO_DRVSTR
-        select SAMSUNG_CLKSRC
+        select SAMSUNG_CLKSRC if !COMMON_CLK
         select SAMSUNG_GPIOLIB_4BIT
         select SAMSUNG_IRQ_VIC_TIMER
         help
@@ -70,7 +70,7 @@ config S3C_LOWLEVEL_UART_PORT
 
 # timer options
 
-config S5P_HRT
+config SAMSUNG_HRT
         bool
         select SAMSUNG_DEV_PWM
         help
@@ -89,7 +89,7 @@ config SAMSUNG_CLKSRC
           used by newer systems such as the S3C64XX.
 
 config S5P_CLOCK
-        def_bool (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_EXYNOS)
+        def_bool (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210)
         help
           Support common clock part for ARCH_S5P and ARCH_EXYNOS SoCs
 
diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile
index 3a7c64d1814a..a23c460299a1 100644
--- a/arch/arm/plat-samsung/Makefile
+++ b/arch/arm/plat-samsung/Makefile
@@ -12,8 +12,7 @@ obj-				:=
 # Objects we always build independent of SoC choice
 
 obj-y                           += init.o cpu.o
-obj-$(CONFIG_ARCH_USES_GETTIMEOFFSET)   += time.o
-obj-$(CONFIG_S5P_HRT)           += s5p-time.o
+obj-$(CONFIG_SAMSUNG_HRT)       += samsung-time.o
 
 obj-$(CONFIG_SAMSUNG_CLOCK)     += clock.o
 obj-$(CONFIG_SAMSUNG_CLOCK)     += pwm-clock.o
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h
index 37703ef6dfc7..e126644cadf4 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -192,10 +192,6 @@ extern void s3c24xx_init_uartdevs(char *name,
                                   struct s3c24xx_uart_resources *res,
                                   struct s3c2410_uartcfg *cfg, int no);
 
-/* timer for 2410/2440 */
-
-extern void s3c24xx_timer_init(void);
-
 extern struct syscore_ops s3c2410_pm_syscore_ops;
 extern struct syscore_ops s3c2412_pm_syscore_ops;
 extern struct syscore_ops s3c2416_pm_syscore_ops;
diff --git a/arch/arm/plat-samsung/include/plat/irq.h b/arch/arm/plat-samsung/include/plat/irq.h
deleted file mode 100644
index e21a89bc26c9..000000000000
--- a/arch/arm/plat-samsung/include/plat/irq.h
+++ /dev/null
@@ -1,116 +0,0 @@
-/* linux/arch/arm/plat-samsung/include/plat/irq.h
- *
- * Copyright (c) 2004-2005 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * Header file for S3C24XX CPU IRQ support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/io.h>
-
-#include <mach/hardware.h>
-#include <mach/regs-irq.h>
-#include <mach/regs-gpio.h>
-
-#define irqdbf(x...)
-#define irqdbf2(x...)
-
-#define EXTINT_OFF (IRQ_EINT4 - 4)
-
-/* these are exported for arch/arm/mach-* usage */
-extern struct irq_chip s3c_irq_level_chip;
-extern struct irq_chip s3c_irq_chip;
-
-static inline void s3c_irqsub_mask(unsigned int irqno,
-                                   unsigned int parentbit,
-                                   int subcheck)
-{
-        unsigned long mask;
-        unsigned long submask;
-
-        submask = __raw_readl(S3C2410_INTSUBMSK);
-        mask = __raw_readl(S3C2410_INTMSK);
-
-        submask |= (1UL << (irqno - IRQ_S3CUART_RX0));
-
-        /* check to see if we need to mask the parent IRQ */
-
-        if ((submask  & subcheck) == subcheck)
-                __raw_writel(mask | parentbit, S3C2410_INTMSK);
-
-        /* write back masks */
-        __raw_writel(submask, S3C2410_INTSUBMSK);
-
-}
-
-static inline void s3c_irqsub_unmask(unsigned int irqno,
-                                     unsigned int parentbit)
-{
-        unsigned long mask;
-        unsigned long submask;
-
-        submask = __raw_readl(S3C2410_INTSUBMSK);
-        mask = __raw_readl(S3C2410_INTMSK);
-
-        submask &= ~(1UL << (irqno - IRQ_S3CUART_RX0));
-        mask &= ~parentbit;
-
-        /* write back masks */
-        __raw_writel(submask, S3C2410_INTSUBMSK);
-        __raw_writel(mask, S3C2410_INTMSK);
-}
-
-
-static inline void s3c_irqsub_maskack(unsigned int irqno,
-                                      unsigned int parentmask,
-                                      unsigned int group)
-{
-        unsigned int bit = 1UL << (irqno - IRQ_S3CUART_RX0);
-
-        s3c_irqsub_mask(irqno, parentmask, group);
-
-        __raw_writel(bit, S3C2410_SUBSRCPND);
-
-        /* only ack parent if we've got all the irqs (seems we must
-         * ack, all and hope that the irq system retriggers ok when
-         * the interrupt goes off again)
-         */
-
-        if (1) {
-                __raw_writel(parentmask, S3C2410_SRCPND);
-                __raw_writel(parentmask, S3C2410_INTPND);
-        }
-}
-
-static inline void s3c_irqsub_ack(unsigned int irqno,
-                                  unsigned int parentmask,
-                                  unsigned int group)
-{
-        unsigned int bit = 1UL << (irqno - IRQ_S3CUART_RX0);
-
-        __raw_writel(bit, S3C2410_SUBSRCPND);
-
-        /* only ack parent if we've got all the irqs (seems we must
-         * ack, all and hope that the irq system retriggers ok when
-         * the interrupt goes off again)
-         */
-
-        if (1) {
-                __raw_writel(parentmask, S3C2410_SRCPND);
-                __raw_writel(parentmask, S3C2410_INTPND);
-        }
-}
-
-/* exported for use in arch/arm/mach-s3c2410 */
-
-#ifdef CONFIG_PM
-extern int s3c_irq_wake(struct irq_data *data, unsigned int state);
-#else
-#define s3c_irq_wake NULL
-#endif
-
-extern int s3c_irqext_type(struct irq_data *d, unsigned int type);
diff --git a/arch/arm/plat-samsung/include/plat/s3c2410.h b/arch/arm/plat-samsung/include/plat/s3c2410.h
deleted file mode 100644
index 55b0e5f51e97..000000000000
--- a/arch/arm/plat-samsung/include/plat/s3c2410.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/* linux/arch/arm/plat-samsung/include/plat/s3c2410.h
- *
- * Copyright (c) 2004 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * Header file for s3c2410 machine directory
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
-*/
-
-#ifdef CONFIG_CPU_S3C2410
-
-extern  int s3c2410_init(void);
-extern  int s3c2410a_init(void);
-
-extern void s3c2410_map_io(void);
-
-extern void s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no);
-
-extern void s3c2410_init_clocks(int xtal);
-
-#else
-#define s3c2410_init_clocks NULL
-#define s3c2410_init_uarts NULL
-#define s3c2410_map_io NULL
-#define s3c2410_init NULL
-#define s3c2410a_init NULL
-#endif
diff --git a/arch/arm/plat-samsung/include/plat/s3c2412.h b/arch/arm/plat-samsung/include/plat/s3c2412.h
deleted file mode 100644
index cbae50ddacc8..000000000000
--- a/arch/arm/plat-samsung/include/plat/s3c2412.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/* linux/arch/arm/plat-samsung/include/plat/s3c2412.h
- *
- * Copyright (c) 2006 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * Header file for s3c2412 cpu support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifdef CONFIG_CPU_S3C2412
-
-extern  int s3c2412_init(void);
-
-extern void s3c2412_map_io(void);
-
-extern void s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no);
-
-extern void s3c2412_init_clocks(int xtal);
-
-extern  int s3c2412_baseclk_add(void);
-
-extern void s3c2412_restart(char mode, const char *cmd);
-#else
-#define s3c2412_init_clocks NULL
-#define s3c2412_init_uarts NULL
-#define s3c2412_map_io NULL
-#define s3c2412_init NULL
-#define s3c2412_restart NULL
-#endif
diff --git a/arch/arm/plat-samsung/include/plat/s3c2416.h b/arch/arm/plat-samsung/include/plat/s3c2416.h
deleted file mode 100644
index f27399a3c68d..000000000000
--- a/arch/arm/plat-samsung/include/plat/s3c2416.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/* linux/arch/arm/plat-samsung/include/plat/s3c2416.h
- *
- * Copyright (c) 2009 Yauhen Kharuzhy <jekhor@gmail.com>
- *
- * Header file for s3c2416 cpu support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifdef CONFIG_CPU_S3C2416
-
-struct s3c2410_uartcfg;
-
-extern  int s3c2416_init(void);
-
-extern void s3c2416_map_io(void);
-
-extern void s3c2416_init_uarts(struct s3c2410_uartcfg *cfg, int no);
-
-extern void s3c2416_init_clocks(int xtal);
-
-extern  int s3c2416_baseclk_add(void);
-
-extern void s3c2416_restart(char mode, const char *cmd);
-
-extern void s3c2416_init_irq(void);
-extern struct syscore_ops s3c2416_irq_syscore_ops;
-
-#else
-#define s3c2416_init_clocks NULL
-#define s3c2416_init_uarts NULL
-#define s3c2416_map_io NULL
-#define s3c2416_init NULL
-#define s3c2416_restart NULL
-#endif
diff --git a/arch/arm/plat-samsung/include/plat/s3c2443.h b/arch/arm/plat-samsung/include/plat/s3c2443.h
deleted file mode 100644
index 71b88ec48956..000000000000
--- a/arch/arm/plat-samsung/include/plat/s3c2443.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/* linux/arch/arm/plat-samsung/include/plat/s3c2443.h
- *
- * Copyright (c) 2004-2005 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * Header file for s3c2443 cpu support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifdef CONFIG_CPU_S3C2443
-
-struct s3c2410_uartcfg;
-
-extern  int s3c2443_init(void);
-
-extern void s3c2443_map_io(void);
-
-extern void s3c2443_init_uarts(struct s3c2410_uartcfg *cfg, int no);
-
-extern void s3c2443_init_clocks(int xtal);
-
-extern  int s3c2443_baseclk_add(void);
-
-extern void s3c2443_restart(char mode, const char *cmd);
-
-extern void s3c2443_init_irq(void);
-#else
-#define s3c2443_init_clocks NULL
-#define s3c2443_init_uarts NULL
-#define s3c2443_map_io NULL
-#define s3c2443_init NULL
-#define s3c2443_restart NULL
-#endif
diff --git a/arch/arm/plat-samsung/include/plat/s3c244x.h b/arch/arm/plat-samsung/include/plat/s3c244x.h
deleted file mode 100644
index ea0c961b7603..000000000000
--- a/arch/arm/plat-samsung/include/plat/s3c244x.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/* linux/arch/arm/plat-samsung/include/plat/s3c244x.h
- *
- * Copyright (c) 2004-2005 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * Header file for S3C2440 and S3C2442 cpu support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
-
-extern void s3c244x_map_io(void);
-
-extern void s3c244x_init_uarts(struct s3c2410_uartcfg *cfg, int no);
-
-extern void s3c244x_init_clocks(int xtal);
-
-#else
-#define s3c244x_init_clocks NULL
-#define s3c244x_init_uarts NULL
-#endif
-
-#ifdef CONFIG_CPU_S3C2440
-extern  int s3c2440_init(void);
-
-extern void s3c2440_map_io(void);
-#else
-#define s3c2440_init NULL
-#define s3c2440_map_io NULL
-#endif
-
-#ifdef CONFIG_CPU_S3C2442
-extern  int s3c2442_init(void);
-
-extern void s3c2442_map_io(void);
-#else
-#define s3c2442_init NULL
-#define s3c2442_map_io NULL
-#endif
diff --git a/arch/arm/plat-samsung/include/plat/s5p-time.h b/arch/arm/plat-samsung/include/plat/s5p-time.h
deleted file mode 100644
index 9c96f3586ce0..000000000000
--- a/arch/arm/plat-samsung/include/plat/s5p-time.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/* linux/arch/arm/plat-samsung/include/plat/s5p-time.h
- *
- * Copyright 2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * Header file for s5p time support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_PLAT_S5P_TIME_H
-#define __ASM_PLAT_S5P_TIME_H __FILE__
-
-/* S5P HR-Timer Clock mode */
-enum s5p_timer_mode {
-        S5P_PWM0,
-        S5P_PWM1,
-        S5P_PWM2,
-        S5P_PWM3,
-        S5P_PWM4,
-};
-
-struct s5p_timer_source {
-        unsigned int event_id;
-        unsigned int source_id;
-};
-
-/* Be able to sleep for atleast 4 seconds (usually more) */
-#define S5PTIMER_MIN_RANGE      4
-
-#define TCNT_MAX                0xffffffff
-#define NON_PERIODIC            0
-#define PERIODIC                1
-
-extern void __init s5p_set_timer_source(enum s5p_timer_mode event,
-                                        enum s5p_timer_mode source);
-extern  void s5p_timer_init(void);
-#endif /* __ASM_PLAT_S5P_TIME_H */
diff --git a/arch/arm/plat-samsung/include/plat/samsung-time.h b/arch/arm/plat-samsung/include/plat/samsung-time.h
new file mode 100644
index 000000000000..4cc99bb1f176
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/samsung-time.h
@@ -0,0 +1,53 @@
+/* linux/arch/arm/plat-samsung/include/plat/samsung-time.h
+ *
+ * Copyright 2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com/
+ *
+ * Header file for samsung s3c and s5p time support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_PLAT_SAMSUNG_TIME_H
+#define __ASM_PLAT_SAMSUNG_TIME_H __FILE__
+
+/* SAMSUNG HR-Timer Clock mode */
+enum samsung_timer_mode {
+        SAMSUNG_PWM0,
+        SAMSUNG_PWM1,
+        SAMSUNG_PWM2,
+        SAMSUNG_PWM3,
+        SAMSUNG_PWM4,
+};
+
+struct samsung_timer_source {
+        unsigned int event_id;
+        unsigned int source_id;
+};
+
+/* Be able to sleep for atleast 4 seconds (usually more) */
+#define SAMSUNG_TIMER_MIN_RANGE 4
+
+#if defined(CONFIG_ARCH_S3C24XX) || defined(CONFIG_ARCH_S5PC100)
+#define TCNT_MAX                0xffff
+#define TSCALER_DIV             25
+#define TDIV                    50
+#define TSIZE                   16
+#else
+#define TCNT_MAX                0xffffffff
+#define TSCALER_DIV             2
+#define TDIV                    2
+#define TSIZE                   32
+#endif
+
+#define NON_PERIODIC            0
+#define PERIODIC                1
+
+extern void __init samsung_set_timer_source(enum samsung_timer_mode event,
+                                        enum samsung_timer_mode source);
+
+extern void __init samsung_timer_init(void);
+
+#endif /* __ASM_PLAT_SAMSUNG_TIME_H */
diff --git a/arch/arm/plat-samsung/s5p-time.c b/arch/arm/plat-samsung/samsung-time.c
index e92510cf82ee..f899cbc9b288 100644
--- a/arch/arm/plat-samsung/s5p-time.c
+++ b/arch/arm/plat-samsung/samsung-time.c
@@ -2,7 +2,7 @@
  * Copyright (c) 2011 Samsung Electronics Co., Ltd.
  *              http://www.samsung.com/
  *
- * S5P - Common hr-timer support
+ * samsung - Common hr-timer support (s3c and s5p)
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -25,41 +25,41 @@
 #include <mach/map.h>
 #include <plat/devs.h>
 #include <plat/regs-timer.h>
-#include <plat/s5p-time.h>
+#include <plat/samsung-time.h>
 
 static struct clk *tin_event;
 static struct clk *tin_source;
 static struct clk *tdiv_event;
 static struct clk *tdiv_source;
 static struct clk *timerclk;
-static struct s5p_timer_source timer_source;
+static struct samsung_timer_source timer_source;
 static unsigned long clock_count_per_tick;
-static void s5p_timer_resume(void);
+static void samsung_timer_resume(void);
 
-static void s5p_time_stop(enum s5p_timer_mode mode)
+static void samsung_time_stop(enum samsung_timer_mode mode)
 {
         unsigned long tcon;
 
         tcon = __raw_readl(S3C2410_TCON);
 
         switch (mode) {
-        case S5P_PWM0:
+        case SAMSUNG_PWM0:
                 tcon &= ~S3C2410_TCON_T0START;
                 break;
 
-        case S5P_PWM1:
+        case SAMSUNG_PWM1:
                 tcon &= ~S3C2410_TCON_T1START;
                 break;
 
-        case S5P_PWM2:
+        case SAMSUNG_PWM2:
                 tcon &= ~S3C2410_TCON_T2START;
                 break;
 
-        case S5P_PWM3:
+        case SAMSUNG_PWM3:
                 tcon &= ~S3C2410_TCON_T3START;
                 break;
 
-        case S5P_PWM4:
+        case SAMSUNG_PWM4:
                 tcon &= ~S3C2410_TCON_T4START;
                 break;
 
@@ -70,7 +70,7 @@ static void s5p_time_stop(enum s5p_timer_mode mode)
         __raw_writel(tcon, S3C2410_TCON);
 }
 
-static void s5p_time_setup(enum s5p_timer_mode mode, unsigned long tcnt)
+static void samsung_time_setup(enum samsung_timer_mode mode, unsigned long tcnt)
 {
         unsigned long tcon;
 
@@ -79,27 +79,27 @@ static void s5p_time_setup(enum s5p_timer_mode mode, unsigned long tcnt)
         tcnt--;
 
         switch (mode) {
-        case S5P_PWM0:
+        case SAMSUNG_PWM0:
                 tcon &= ~(0x0f << 0);
                 tcon |= S3C2410_TCON_T0MANUALUPD;
                 break;
 
-        case S5P_PWM1:
+        case SAMSUNG_PWM1:
                 tcon &= ~(0x0f << 8);
                 tcon |= S3C2410_TCON_T1MANUALUPD;
                 break;
 
-        case S5P_PWM2:
+        case SAMSUNG_PWM2:
                 tcon &= ~(0x0f << 12);
                 tcon |= S3C2410_TCON_T2MANUALUPD;
                 break;
 
-        case S5P_PWM3:
+        case SAMSUNG_PWM3:
                 tcon &= ~(0x0f << 16);
                 tcon |= S3C2410_TCON_T3MANUALUPD;
                 break;
 
-        case S5P_PWM4:
+        case SAMSUNG_PWM4:
                 tcon &= ~(0x07 << 20);
                 tcon |= S3C2410_TCON_T4MANUALUPD;
                 break;
@@ -114,14 +114,14 @@ static void s5p_time_setup(enum s5p_timer_mode mode, unsigned long tcnt)
         __raw_writel(tcon, S3C2410_TCON);
 }
 
-static void s5p_time_start(enum s5p_timer_mode mode, bool periodic)
+static void samsung_time_start(enum samsung_timer_mode mode, bool periodic)
 {
         unsigned long tcon;
 
         tcon  = __raw_readl(S3C2410_TCON);
 
         switch (mode) {
-        case S5P_PWM0:
+        case SAMSUNG_PWM0:
                 tcon |= S3C2410_TCON_T0START;
                 tcon &= ~S3C2410_TCON_T0MANUALUPD;
 
@@ -131,7 +131,7 @@ static void s5p_time_start(enum s5p_timer_mode mode, bool periodic)
                         tcon &= ~S3C2410_TCON_T0RELOAD;
                 break;
 
-        case S5P_PWM1:
+        case SAMSUNG_PWM1:
                 tcon |= S3C2410_TCON_T1START;
                 tcon &= ~S3C2410_TCON_T1MANUALUPD;
 
@@ -141,7 +141,7 @@ static void s5p_time_start(enum s5p_timer_mode mode, bool periodic)
                         tcon &= ~S3C2410_TCON_T1RELOAD;
                 break;
 
-        case S5P_PWM2:
+        case SAMSUNG_PWM2:
                 tcon |= S3C2410_TCON_T2START;
                 tcon &= ~S3C2410_TCON_T2MANUALUPD;
 
@@ -151,7 +151,7 @@ static void s5p_time_start(enum s5p_timer_mode mode, bool periodic)
                         tcon &= ~S3C2410_TCON_T2RELOAD;
                 break;
 
-        case S5P_PWM3:
+        case SAMSUNG_PWM3:
                 tcon |= S3C2410_TCON_T3START;
                 tcon &= ~S3C2410_TCON_T3MANUALUPD;
 
@@ -161,7 +161,7 @@ static void s5p_time_start(enum s5p_timer_mode mode, bool periodic)
                         tcon &= ~S3C2410_TCON_T3RELOAD;
                 break;
 
-        case S5P_PWM4:
+        case SAMSUNG_PWM4:
                 tcon |= S3C2410_TCON_T4START;
                 tcon &= ~S3C2410_TCON_T4MANUALUPD;
 
@@ -178,24 +178,24 @@ static void s5p_time_start(enum s5p_timer_mode mode, bool periodic)
         __raw_writel(tcon, S3C2410_TCON);
 }
 
-static int s5p_set_next_event(unsigned long cycles,
+static int samsung_set_next_event(unsigned long cycles,
                                 struct clock_event_device *evt)
 {
-        s5p_time_setup(timer_source.event_id, cycles);
-        s5p_time_start(timer_source.event_id, NON_PERIODIC);
+        samsung_time_setup(timer_source.event_id, cycles);
+        samsung_time_start(timer_source.event_id, NON_PERIODIC);
 
         return 0;
 }
 
-static void s5p_set_mode(enum clock_event_mode mode,
+static void samsung_set_mode(enum clock_event_mode mode,
                                 struct clock_event_device *evt)
 {
-        s5p_time_stop(timer_source.event_id);
+        samsung_time_stop(timer_source.event_id);
 
         switch (mode) {
         case CLOCK_EVT_MODE_PERIODIC:
-                s5p_time_setup(timer_source.event_id, clock_count_per_tick);
-                s5p_time_start(timer_source.event_id, PERIODIC);
+                samsung_time_setup(timer_source.event_id, clock_count_per_tick);
+                samsung_time_start(timer_source.event_id, PERIODIC);
                 break;
 
         case CLOCK_EVT_MODE_ONESHOT:
@@ -206,24 +206,24 @@ static void s5p_set_mode(enum clock_event_mode mode,
                 break;
 
         case CLOCK_EVT_MODE_RESUME:
-                s5p_timer_resume();
+                samsung_timer_resume();
                 break;
         }
 }
 
-static void s5p_timer_resume(void)
+static void samsung_timer_resume(void)
 {
         /* event timer restart */
-        s5p_time_setup(timer_source.event_id, clock_count_per_tick);
-        s5p_time_start(timer_source.event_id, PERIODIC);
+        samsung_time_setup(timer_source.event_id, clock_count_per_tick);
+        samsung_time_start(timer_source.event_id, PERIODIC);
 
         /* source timer restart */
-        s5p_time_setup(timer_source.source_id, TCNT_MAX);
-        s5p_time_start(timer_source.source_id, PERIODIC);
+        samsung_time_setup(timer_source.source_id, TCNT_MAX);
+        samsung_time_start(timer_source.source_id, PERIODIC);
 }
 
-void __init s5p_set_timer_source(enum s5p_timer_mode event,
-                                 enum s5p_timer_mode source)
+void __init samsung_set_timer_source(enum samsung_timer_mode event,
+                                 enum samsung_timer_mode source)
 {
         s3c_device_timer[event].dev.bus = &platform_bus_type;
         s3c_device_timer[source].dev.bus = &platform_bus_type;
@@ -233,14 +233,14 @@ void __init s5p_set_timer_source(enum s5p_timer_mode event,
 }
 
 static struct clock_event_device time_event_device = {
-        .name           = "s5p_event_timer",
+        .name           = "samsung_event_timer",
         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
         .rating         = 200,
-        .set_next_event = s5p_set_next_event,
-        .set_mode       = s5p_set_mode,
+        .set_next_event = samsung_set_next_event,
+        .set_mode       = samsung_set_mode,
 };
 
-static irqreturn_t s5p_clock_event_isr(int irq, void *dev_id)
+static irqreturn_t samsung_clock_event_isr(int irq, void *dev_id)
 {
         struct clock_event_device *evt = dev_id;
 
@@ -249,14 +249,14 @@ static irqreturn_t s5p_clock_event_isr(int irq, void *dev_id)
         return IRQ_HANDLED;
 }
 
-static struct irqaction s5p_clock_event_irq = {
-        .name           = "s5p_time_irq",
+static struct irqaction samsung_clock_event_irq = {
+        .name           = "samsung_time_irq",
         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
-        .handler        = s5p_clock_event_isr,
+        .handler        = samsung_clock_event_isr,
         .dev_id         = &time_event_device,
 };
 
-static void __init s5p_clockevent_init(void)
+static void __init samsung_clockevent_init(void)
 {
         unsigned long pclk;
         unsigned long clock_rate;
@@ -267,8 +267,8 @@ static void __init s5p_clockevent_init(void)
 
         tscaler = clk_get_parent(tdiv_event);
 
-        clk_set_rate(tscaler, pclk / 2);
-        clk_set_rate(tdiv_event, pclk / 2);
+        clk_set_rate(tscaler, pclk / TSCALER_DIV);
+        clk_set_rate(tdiv_event, pclk / TDIV);
         clk_set_parent(tin_event, tdiv_event);
 
         clock_rate = clk_get_rate(tin_event);
@@ -278,22 +278,22 @@ static void __init s5p_clockevent_init(void)
         clockevents_config_and_register(&time_event_device, clock_rate, 1, -1);
 
         irq_number = timer_source.event_id + IRQ_TIMER0;
-        setup_irq(irq_number, &s5p_clock_event_irq);
+        setup_irq(irq_number, &samsung_clock_event_irq);
 }
 
-static void __iomem *s5p_timer_reg(void)
+static void __iomem *samsung_timer_reg(void)
 {
         unsigned long offset = 0;
 
         switch (timer_source.source_id) {
-        case S5P_PWM0:
-        case S5P_PWM1:
-        case S5P_PWM2:
-        case S5P_PWM3:
+        case SAMSUNG_PWM0:
+        case SAMSUNG_PWM1:
+        case SAMSUNG_PWM2:
+        case SAMSUNG_PWM3:
                 offset = (timer_source.source_id * 0x0c) + 0x14;
                 break;
 
-        case S5P_PWM4:
+        case SAMSUNG_PWM4:
                 offset = 0x40;
                 break;
 
@@ -312,9 +312,9 @@ static void __iomem *s5p_timer_reg(void)
  * this wraps around for now, since it is just a relative time
  * stamp. (Inspired by U300 implementation.)
  */
-static u32 notrace s5p_read_sched_clock(void)
+static u32 notrace samsung_read_sched_clock(void)
 {
-        void __iomem *reg = s5p_timer_reg();
+        void __iomem *reg = samsung_timer_reg();
 
         if (!reg)
                 return 0;
@@ -322,29 +322,29 @@ static u32 notrace s5p_read_sched_clock(void)
         return ~__raw_readl(reg);
 }
 
-static void __init s5p_clocksource_init(void)
+static void __init samsung_clocksource_init(void)
 {
         unsigned long pclk;
         unsigned long clock_rate;
 
         pclk = clk_get_rate(timerclk);
 
-        clk_set_rate(tdiv_source, pclk / 2);
+        clk_set_rate(tdiv_source, pclk / TDIV);
         clk_set_parent(tin_source, tdiv_source);
 
         clock_rate = clk_get_rate(tin_source);
 
-        s5p_time_setup(timer_source.source_id, TCNT_MAX);
-        s5p_time_start(timer_source.source_id, PERIODIC);
+        samsung_time_setup(timer_source.source_id, TCNT_MAX);
+        samsung_time_start(timer_source.source_id, PERIODIC);
 
-        setup_sched_clock(s5p_read_sched_clock, 32, clock_rate);
+        setup_sched_clock(samsung_read_sched_clock, TSIZE, clock_rate);
 
-        if (clocksource_mmio_init(s5p_timer_reg(), "s5p_clocksource_timer",
-                        clock_rate, 250, 32, clocksource_mmio_readl_down))
-                panic("s5p_clocksource_timer: can't register clocksource\n");
+        if (clocksource_mmio_init(samsung_timer_reg(), "samsung_clocksource_timer",
+                        clock_rate, 250, TSIZE, clocksource_mmio_readl_down))
+                panic("samsung_clocksource_timer: can't register clocksource\n");
 }
 
-static void __init s5p_timer_resources(void)
+static void __init samsung_timer_resources(void)
 {
 
         unsigned long event_id = timer_source.event_id;
@@ -386,9 +386,9 @@ static void __init s5p_timer_resources(void)
         clk_enable(tin_source);
 }
 
-void __init s5p_timer_init(void)
+void __init samsung_timer_init(void)
 {
-        s5p_timer_resources();
-        s5p_clockevent_init();
-        s5p_clocksource_init();
+        samsung_timer_resources();
+        samsung_clockevent_init();
+        samsung_clocksource_init();
 }
diff --git a/arch/arm/plat-samsung/time.c b/arch/arm/plat-samsung/time.c
deleted file mode 100644
index 73defd00c3e4..000000000000
--- a/arch/arm/plat-samsung/time.c
+++ /dev/null
@@ -1,287 +0,0 @@
-/* linux/arch/arm/plat-samsung/time.c
- *
- * Copyright (C) 2003-2005 Simtec Electronics
- *      Ben Dooks, <ben@simtec.co.uk>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/platform_device.h>
-#include <linux/syscore_ops.h>
-
-#include <asm/mach-types.h>
-
-#include <asm/irq.h>
-#include <mach/map.h>
-#include <plat/regs-timer.h>
-#include <mach/regs-irq.h>
-#include <asm/mach/time.h>
-#include <mach/tick.h>
-
-#include <plat/clock.h>
-#include <plat/cpu.h>
-
-static unsigned long timer_startval;
-static unsigned long timer_usec_ticks;
-
-#ifndef TICK_MAX
-#define TICK_MAX (0xffff)
-#endif
-
-#define TIMER_USEC_SHIFT 16
-
-/* we use the shifted arithmetic to work out the ratio of timer ticks
- * to usecs, as often the peripheral clock is not a nice even multiple
- * of 1MHz.
- *
- * shift of 14 and 15 are too low for the 12MHz, 16 seems to be ok
- * for the current HZ value of 200 without producing overflows.
- *
- * Original patch by Dimitry Andric, updated by Ben Dooks
-*/
-
-
-/* timer_mask_usec_ticks
- *
- * given a clock and divisor, make the value to pass into timer_ticks_to_usec
- * to scale the ticks into usecs
-*/
-
-static inline unsigned long
-timer_mask_usec_ticks(unsigned long scaler, unsigned long pclk)
-{
-        unsigned long den = pclk / 1000;
-
-        return ((1000 << TIMER_USEC_SHIFT) * scaler + (den >> 1)) / den;
-}
-
-/* timer_ticks_to_usec
- *
- * convert timer ticks to usec.
-*/
-
-static inline unsigned long timer_ticks_to_usec(unsigned long ticks)
-{
-        unsigned long res;
-
-        res = ticks * timer_usec_ticks;
-        res += 1 << (TIMER_USEC_SHIFT - 4);     /* round up slightly */
-
-        return res >> TIMER_USEC_SHIFT;
-}
-
-/***
- * Returns microsecond  since last clock interrupt.  Note that interrupts
- * will have been disabled by do_gettimeoffset()
- * IRQs are disabled before entering here from do_gettimeofday()
- */
-
-static u32 s3c2410_gettimeoffset(void)
-{
-        unsigned long tdone;
-        unsigned long tval;
-
-        /* work out how many ticks have gone since last timer interrupt */
-
-        tval =  __raw_readl(S3C2410_TCNTO(4));
-        tdone = timer_startval - tval;
-
-        /* check to see if there is an interrupt pending */
-
-        if (s3c24xx_ostimer_pending()) {
-                /* re-read the timer, and try and fix up for the missed
-                 * interrupt. Note, the interrupt may go off before the
-                 * timer has re-loaded from wrapping.
-                 */
-
-                tval =  __raw_readl(S3C2410_TCNTO(4));
-                tdone = timer_startval - tval;
-
-                if (tval != 0)
-                        tdone += timer_startval;
-        }
-
-        return timer_ticks_to_usec(tdone) * 1000;
-}
-
-
-/*
- * IRQ handler for the timer
- */
-static irqreturn_t
-s3c2410_timer_interrupt(int irq, void *dev_id)
-{
-        timer_tick();
-        return IRQ_HANDLED;
-}
-
-static struct irqaction s3c2410_timer_irq = {
-        .name           = "S3C2410 Timer Tick",
-        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
-        .handler        = s3c2410_timer_interrupt,
-};
-
-#define use_tclk1_12() ( \
-        machine_is_bast()       || \
-        machine_is_vr1000()     || \
-        machine_is_anubis()     || \
-        machine_is_osiris())
-
-static struct clk *tin;
-static struct clk *tdiv;
-static struct clk *timerclk;
-
-/*
- * Set up timer interrupt, and return the current time in seconds.
- *
- * Currently we only use timer4, as it is the only timer which has no
- * other function that can be exploited externally
- */
-static void s3c2410_timer_setup (void)
-{
-        unsigned long tcon;
-        unsigned long tcnt;
-        unsigned long tcfg1;
-        unsigned long tcfg0;
-
-        tcnt = TICK_MAX;  /* default value for tcnt */
-
-        /* configure the system for whichever machine is in use */
-
-        if (use_tclk1_12()) {
-                /* timer is at 12MHz, scaler is 1 */
-                timer_usec_ticks = timer_mask_usec_ticks(1, 12000000);
-                tcnt = 12000000 / HZ;
-
-                tcfg1 = __raw_readl(S3C2410_TCFG1);
-                tcfg1 &= ~S3C2410_TCFG1_MUX4_MASK;
-                tcfg1 |= S3C2410_TCFG1_MUX4_TCLK1;
-                __raw_writel(tcfg1, S3C2410_TCFG1);
-        } else {
-                unsigned long pclk;
-                struct clk *tscaler;
-
-                /* for the h1940 (and others), we use the pclk from the core
-                 * to generate the timer values. since values around 50 to
-                 * 70MHz are not values we can directly generate the timer
-                 * value from, we need to pre-scale and divide before using it.
-                 *
-                 * for instance, using 50.7MHz and dividing by 6 gives 8.45MHz
-                 * (8.45 ticks per usec)
-                 */
-
-                pclk = clk_get_rate(timerclk);
-
-                /* configure clock tick */
-
-                timer_usec_ticks = timer_mask_usec_ticks(6, pclk);
-
-                tscaler = clk_get_parent(tdiv);
-
-                clk_set_rate(tscaler, pclk / 3);
-                clk_set_rate(tdiv, pclk / 6);
-                clk_set_parent(tin, tdiv);
-
-                tcnt = clk_get_rate(tin) / HZ;
-        }
-
-        tcon = __raw_readl(S3C2410_TCON);
-        tcfg0 = __raw_readl(S3C2410_TCFG0);
-        tcfg1 = __raw_readl(S3C2410_TCFG1);
-
-        /* timers reload after counting zero, so reduce the count by 1 */
-
-        tcnt--;
-
-        printk(KERN_DEBUG "timer tcon=%08lx, tcnt %04lx, tcfg %08lx,%08lx, usec %08lx\n",
-               tcon, tcnt, tcfg0, tcfg1, timer_usec_ticks);
-
-        /* check to see if timer is within 16bit range... */
-        if (tcnt > TICK_MAX) {
-                panic("setup_timer: HZ is too small, cannot configure timer!");
-                return;
-        }
-
-        __raw_writel(tcfg1, S3C2410_TCFG1);
-        __raw_writel(tcfg0, S3C2410_TCFG0);
-
-        timer_startval = tcnt;
-        __raw_writel(tcnt, S3C2410_TCNTB(4));
-
-        /* ensure timer is stopped... */
-
-        tcon &= ~(7<<20);
-        tcon |= S3C2410_TCON_T4RELOAD;
-        tcon |= S3C2410_TCON_T4MANUALUPD;
-
-        __raw_writel(tcon, S3C2410_TCON);
-        __raw_writel(tcnt, S3C2410_TCNTB(4));
-        __raw_writel(tcnt, S3C2410_TCMPB(4));
-
-        /* start the timer running */
-        tcon |= S3C2410_TCON_T4START;
-        tcon &= ~S3C2410_TCON_T4MANUALUPD;
-        __raw_writel(tcon, S3C2410_TCON);
-}
-
-static void __init s3c2410_timer_resources(void)
-{
-        struct platform_device tmpdev;
-
-        tmpdev.dev.bus = &platform_bus_type;
-        tmpdev.id = 4;
-
-        timerclk = clk_get(NULL, "timers");
-        if (IS_ERR(timerclk))
-                panic("failed to get clock for system timer");
-
-        clk_enable(timerclk);
-
-        if (!use_tclk1_12()) {
-                tmpdev.id = 4;
-                tmpdev.dev.init_name = "s3c24xx-pwm.4";
-                tin = clk_get(&tmpdev.dev, "pwm-tin");
-                if (IS_ERR(tin))
-                        panic("failed to get pwm-tin clock for system timer");
-
-                tdiv = clk_get(&tmpdev.dev, "pwm-tdiv");
-                if (IS_ERR(tdiv))
-                        panic("failed to get pwm-tdiv clock for system timer");
-        }
-
-        clk_enable(tin);
-}
-
-static struct syscore_ops s3c24xx_syscore_ops = {
-        .resume         = s3c2410_timer_setup,
-};
-
-void __init s3c24xx_timer_init(void)
-{
-        arch_gettimeoffset = s3c2410_gettimeoffset;
-
-        s3c2410_timer_resources();
-        s3c2410_timer_setup();
-        setup_irq(IRQ_TIMER4, &s3c2410_timer_irq);
-        register_syscore_ops(&s3c24xx_syscore_ops);
-}
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 300d4775d926..0147022b9813 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_ARCH_U8500)	+= ux500/
 obj-$(CONFIG_ARCH_VT8500)       += clk-vt8500.o
 obj-$(CONFIG_ARCH_ZYNQ)         += clk-zynq.o
 obj-$(CONFIG_ARCH_TEGRA)        += tegra/
+obj-$(CONFIG_PLAT_SAMSUNG)      += samsung/
 
 obj-$(CONFIG_X86)               += x86/
 
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
new file mode 100644
index 000000000000..b7c232e67425
--- /dev/null
+++ b/drivers/clk/samsung/Makefile
@@ -0,0 +1,8 @@
+#
+# Samsung Clock specific Makefile
+#
+
+obj-$(CONFIG_COMMON_CLK)        += clk.o clk-pll.o
+obj-$(CONFIG_ARCH_EXYNOS4)      += clk-exynos4.o
+obj-$(CONFIG_SOC_EXYNOS5250)    += clk-exynos5250.o
+obj-$(CONFIG_SOC_EXYNOS5440)    += clk-exynos5440.o
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
new file mode 100644
index 000000000000..71046694d9dd
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -0,0 +1,1091 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2013 Linaro Ltd.
+ * Author: Thomas Abraham <thomas.ab@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for all Exynos4 SoCs.
+*/
+
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+#include <plat/cpu.h>
+#include "clk.h"
+#include "clk-pll.h"
+
+/* Exynos4 clock controller register offsets */
+#define SRC_LEFTBUS             0x4200
+#define DIV_LEFTBUS             0x4500
+#define GATE_IP_LEFTBUS         0x4800
+#define E4X12_GATE_IP_IMAGE     0x4930
+#define SRC_RIGHTBUS            0x8200
+#define DIV_RIGHTBUS            0x8500
+#define GATE_IP_RIGHTBUS        0x8800
+#define E4X12_GATE_IP_PERIR     0x8960
+#define EPLL_LOCK               0xc010
+#define VPLL_LOCK               0xc020
+#define EPLL_CON0               0xc110
+#define EPLL_CON1               0xc114
+#define EPLL_CON2               0xc118
+#define VPLL_CON0               0xc120
+#define VPLL_CON1               0xc124
+#define VPLL_CON2               0xc128
+#define SRC_TOP0                0xc210
+#define SRC_TOP1                0xc214
+#define SRC_CAM                 0xc220
+#define SRC_TV                  0xc224
+#define SRC_MFC                 0xcc28
+#define SRC_G3D                 0xc22c
+#define E4210_SRC_IMAGE         0xc230
+#define SRC_LCD0                0xc234
+#define E4210_SRC_LCD1          0xc238
+#define E4X12_SRC_ISP           0xc238
+#define SRC_MAUDIO              0xc23c
+#define SRC_FSYS                0xc240
+#define SRC_PERIL0              0xc250
+#define SRC_PERIL1              0xc254
+#define E4X12_SRC_CAM1          0xc258
+#define SRC_MASK_TOP            0xc310
+#define SRC_MASK_CAM            0xc320
+#define SRC_MASK_TV             0xc324
+#define SRC_MASK_LCD0           0xc334
+#define E4210_SRC_MASK_LCD1     0xc338
+#define E4X12_SRC_MASK_ISP      0xc338
+#define SRC_MASK_MAUDIO         0xc33c
+#define SRC_MASK_FSYS           0xc340
+#define SRC_MASK_PERIL0         0xc350
+#define SRC_MASK_PERIL1         0xc354
+#define DIV_TOP                 0xc510
+#define DIV_CAM                 0xc520
+#define DIV_TV                  0xc524
+#define DIV_MFC                 0xc528
+#define DIV_G3D                 0xc52c
+#define DIV_IMAGE               0xc530
+#define DIV_LCD0                0xc534
+#define E4210_DIV_LCD1          0xc538
+#define E4X12_DIV_ISP           0xc538
+#define DIV_MAUDIO              0xc53c
+#define DIV_FSYS0               0xc540
+#define DIV_FSYS1               0xc544
+#define DIV_FSYS2               0xc548
+#define DIV_FSYS3               0xc54c
+#define DIV_PERIL0              0xc550
+#define DIV_PERIL1              0xc554
+#define DIV_PERIL2              0xc558
+#define DIV_PERIL3              0xc55c
+#define DIV_PERIL4              0xc560
+#define DIV_PERIL5              0xc564
+#define E4X12_DIV_CAM1          0xc568
+#define GATE_SCLK_CAM           0xc820
+#define GATE_IP_CAM             0xc920
+#define GATE_IP_TV              0xc924
+#define GATE_IP_MFC             0xc928
+#define GATE_IP_G3D             0xc92c
+#define E4210_GATE_IP_IMAGE     0xc930
+#define GATE_IP_LCD0            0xc934
+#define E4210_GATE_IP_LCD1      0xc938
+#define E4X12_GATE_IP_ISP       0xc938
+#define E4X12_GATE_IP_MAUDIO    0xc93c
+#define GATE_IP_FSYS            0xc940
+#define GATE_IP_GPS             0xc94c
+#define GATE_IP_PERIL           0xc950
+#define E4210_GATE_IP_PERIR     0xc960
+#define GATE_BLOCK              0xc970
+#define E4X12_MPLL_CON0         0x10108
+#define SRC_DMC                 0x10200
+#define SRC_MASK_DMC            0x10300
+#define DIV_DMC0                0x10500
+#define DIV_DMC1                0x10504
+#define GATE_IP_DMC             0x10900
+#define APLL_CON0               0x14100
+#define E4210_MPLL_CON0         0x14108
+#define SRC_CPU                 0x14200
+#define DIV_CPU0                0x14500
+#define DIV_CPU1                0x14504
+#define GATE_SCLK_CPU           0x14800
+#define GATE_IP_CPU             0x14900
+#define E4X12_DIV_ISP0          0x18300
+#define E4X12_DIV_ISP1          0x18304
+#define E4X12_GATE_ISP0         0x18800
+#define E4X12_GATE_ISP1         0x18804
+
+/* the exynos4 soc type */
+enum exynos4_soc {
+        EXYNOS4210,
+        EXYNOS4X12,
+};
+
+/*
+ * Let each supported clock get a unique id. This id is used to lookup the clock
+ * for device tree based platforms. The clocks are categorized into three
+ * sections: core, sclk gate and bus interface gate clocks.
+ *
+ * When adding a new clock to this list, it is advised to choose a clock
+ * category and add it to the end of that category. That is because the the
+ * device tree source file is referring to these ids and any change in the
+ * sequence number of existing clocks will require corresponding change in the
+ * device tree files. This limitation would go away when pre-processor support
+ * for dtc would be available.
+ */
+enum exynos4_clks {
+        none,
+
+        /* core clocks */
+        xxti, xusbxti, fin_pll, fout_apll, fout_mpll, fout_epll, fout_vpll,
+        sclk_apll, sclk_mpll, sclk_epll, sclk_vpll, arm_clk, aclk200, aclk100,
+        aclk160, aclk133, mout_mpll_user_t, mout_mpll_user_c, mout_core,
+        mout_apll, /* 20 */
+
+        /* gate for special clocks (sclk) */
+        sclk_fimc0 = 128, sclk_fimc1, sclk_fimc2, sclk_fimc3, sclk_cam0,
+        sclk_cam1, sclk_csis0, sclk_csis1, sclk_hdmi, sclk_mixer, sclk_dac,
+        sclk_pixel, sclk_fimd0, sclk_mdnie0, sclk_mdnie_pwm0, sclk_mipi0,
+        sclk_audio0, sclk_mmc0, sclk_mmc1, sclk_mmc2, sclk_mmc3, sclk_mmc4,
+        sclk_sata, sclk_uart0, sclk_uart1, sclk_uart2, sclk_uart3, sclk_uart4,
+        sclk_audio1, sclk_audio2, sclk_spdif, sclk_spi0, sclk_spi1, sclk_spi2,
+        sclk_slimbus, sclk_fimd1, sclk_mipi1, sclk_pcm1, sclk_pcm2, sclk_i2s1,
+        sclk_i2s2, sclk_mipihsi, sclk_mfc, sclk_pcm0, sclk_g3d, sclk_pwm_isp,
+        sclk_spi0_isp, sclk_spi1_isp, sclk_uart_isp,
+
+        /* gate clocks */
+        fimc0 = 256, fimc1, fimc2, fimc3, csis0, csis1, jpeg, smmu_fimc0,
+        smmu_fimc1, smmu_fimc2, smmu_fimc3, smmu_jpeg, vp, mixer, tvenc, hdmi,
+        smmu_tv, mfc, smmu_mfcl, smmu_mfcr, g3d, g2d, rotator, mdma, smmu_g2d,
+        smmu_rotator, smmu_mdma, fimd0, mie0, mdnie0, dsim0, smmu_fimd0, fimd1,
+        mie1, dsim1, smmu_fimd1, pdma0, pdma1, pcie_phy, sata_phy, tsi, sdmmc0,
+        sdmmc1, sdmmc2, sdmmc3, sdmmc4, sata, sromc, usb_host, usb_device, pcie,
+        onenand, nfcon, smmu_pcie, gps, smmu_gps, uart0, uart1, uart2, uart3,
+        uart4, i2c0, i2c1, i2c2, i2c3, i2c4, i2c5, i2c6, i2c7, i2c_hdmi, tsadc,
+        spi0, spi1, spi2, i2s1, i2s2, pcm0, i2s0, pcm1, pcm2, pwm, slimbus,
+        spdif, ac97, modemif, chipid, sysreg, hdmi_cec, mct, wdt, rtc, keyif,
+        audss, mipi_hsi, mdma2, pixelasyncm0, pixelasyncm1, fimc_lite0,
+        fimc_lite1, ppmuispx, ppmuispmx, fimc_isp, fimc_drc, fimc_fd, mcuisp,
+        gicisp, smmu_isp, smmu_drc, smmu_fd, smmu_lite0, smmu_lite1, mcuctl_isp,
+        mpwm_isp, i2c0_isp, i2c1_isp, mtcadc_isp, pwm_isp, wdt_isp, uart_isp,
+        asyncaxim, smmu_ispcx, spi0_isp, spi1_isp, pwm_isp_sclk, spi0_isp_sclk,
+        spi1_isp_sclk, uart_isp_sclk,
+
+        /* mux clocks */
+        mout_fimc0 = 384, mout_fimc1, mout_fimc2, mout_fimc3, mout_cam0,
+        mout_cam1, mout_csis0, mout_csis1, mout_g3d0, mout_g3d1, mout_g3d,
+        aclk400_mcuisp,
+
+        /* div clocks */
+        div_isp0 = 450, div_isp1, div_mcuisp0, div_mcuisp1, div_aclk200,
+        div_aclk400_mcuisp,
+
+        nr_clks,
+};
+
+/*
+ * list of controller registers to be saved and restored during a
+ * suspend/resume cycle.
+ */
+static __initdata unsigned long exynos4210_clk_save[] = {
+        E4210_SRC_IMAGE,
+        E4210_SRC_LCD1,
+        E4210_SRC_MASK_LCD1,
+        E4210_DIV_LCD1,
+        E4210_GATE_IP_IMAGE,
+        E4210_GATE_IP_LCD1,
+        E4210_GATE_IP_PERIR,
+        E4210_MPLL_CON0,
+};
+
+static __initdata unsigned long exynos4x12_clk_save[] = {
+        E4X12_GATE_IP_IMAGE,
+        E4X12_GATE_IP_PERIR,
+        E4X12_SRC_CAM1,
+        E4X12_DIV_ISP,
+        E4X12_DIV_CAM1,
+        E4X12_MPLL_CON0,
+};
+
+static __initdata unsigned long exynos4_clk_regs[] = {
+        SRC_LEFTBUS,
+        DIV_LEFTBUS,
+        GATE_IP_LEFTBUS,
+        SRC_RIGHTBUS,
+        DIV_RIGHTBUS,
+        GATE_IP_RIGHTBUS,
+        EPLL_CON0,
+        EPLL_CON1,
+        EPLL_CON2,
+        VPLL_CON0,
+        VPLL_CON1,
+        VPLL_CON2,
+        SRC_TOP0,
+        SRC_TOP1,
+        SRC_CAM,
+        SRC_TV,
+        SRC_MFC,
+        SRC_G3D,
+        SRC_LCD0,
+        SRC_MAUDIO,
+        SRC_FSYS,
+        SRC_PERIL0,
+        SRC_PERIL1,
+        SRC_MASK_TOP,
+        SRC_MASK_CAM,
+        SRC_MASK_TV,
+        SRC_MASK_LCD0,
+        SRC_MASK_MAUDIO,
+        SRC_MASK_FSYS,
+        SRC_MASK_PERIL0,
+        SRC_MASK_PERIL1,
+        DIV_TOP,
+        DIV_CAM,
+        DIV_TV,
+        DIV_MFC,
+        DIV_G3D,
+        DIV_IMAGE,
+        DIV_LCD0,
+        DIV_MAUDIO,
+        DIV_FSYS0,
+        DIV_FSYS1,
+        DIV_FSYS2,
+        DIV_FSYS3,
+        DIV_PERIL0,
+        DIV_PERIL1,
+        DIV_PERIL2,
+        DIV_PERIL3,
+        DIV_PERIL4,
+        DIV_PERIL5,
+        GATE_SCLK_CAM,
+        GATE_IP_CAM,
+        GATE_IP_TV,
+        GATE_IP_MFC,
+        GATE_IP_G3D,
+        GATE_IP_LCD0,
+        GATE_IP_FSYS,
+        GATE_IP_GPS,
+        GATE_IP_PERIL,
+        GATE_BLOCK,
+        SRC_MASK_DMC,
+        SRC_DMC,
+        DIV_DMC0,
+        DIV_DMC1,
+        GATE_IP_DMC,
+        APLL_CON0,
+        SRC_CPU,
+        DIV_CPU0,
+        DIV_CPU1,
+        GATE_SCLK_CPU,
+        GATE_IP_CPU,
+};
+
+/* list of all parent clock list */
+PNAME(mout_apll_p)      = { "fin_pll", "fout_apll", };
+PNAME(mout_mpll_p)      = { "fin_pll", "fout_mpll", };
+PNAME(mout_epll_p)      = { "fin_pll", "fout_epll", };
+PNAME(mout_vpllsrc_p)   = { "fin_pll", "sclk_hdmi24m", };
+PNAME(mout_vpll_p)      = { "fin_pll", "fout_vpll", };
+PNAME(sclk_evpll_p)     = { "sclk_epll", "sclk_vpll", };
+PNAME(mout_mfc_p)       = { "mout_mfc0", "mout_mfc1", };
+PNAME(mout_g3d_p)       = { "mout_g3d0", "mout_g3d1", };
+PNAME(mout_g2d_p)       = { "mout_g2d0", "mout_g2d1", };
+PNAME(mout_hdmi_p)      = { "sclk_pixel", "sclk_hdmiphy", };
+PNAME(mout_jpeg_p)      = { "mout_jpeg0", "mout_jpeg1", };
+PNAME(mout_spdif_p)     = { "sclk_audio0", "sclk_audio1", "sclk_audio2",
+                                "spdif_extclk", };
+PNAME(mout_onenand_p)  = {"aclk133", "aclk160", };
+PNAME(mout_onenand1_p) = {"mout_onenand", "sclk_vpll", };
+
+/* Exynos 4210-specific parent groups */
+PNAME(sclk_vpll_p4210)  = { "mout_vpllsrc", "fout_vpll", };
+PNAME(mout_core_p4210)  = { "mout_apll", "sclk_mpll", };
+PNAME(sclk_ampll_p4210) = { "sclk_mpll", "sclk_apll", };
+PNAME(group1_p4210)     = { "xxti", "xusbxti", "sclk_hdmi24m",
+                                "sclk_usbphy0", "none", "sclk_hdmiphy",
+                                "sclk_mpll", "sclk_epll", "sclk_vpll", };
+PNAME(mout_audio0_p4210) = { "cdclk0", "none", "sclk_hdmi24m",
+                                "sclk_usbphy0", "xxti", "xusbxti", "sclk_mpll",
+                                "sclk_epll", "sclk_vpll" };
+PNAME(mout_audio1_p4210) = { "cdclk1", "none", "sclk_hdmi24m",
+                                "sclk_usbphy0", "xxti", "xusbxti", "sclk_mpll",
+                                "sclk_epll", "sclk_vpll", };
+PNAME(mout_audio2_p4210) = { "cdclk2", "none", "sclk_hdmi24m",
+                                "sclk_usbphy0", "xxti", "xusbxti", "sclk_mpll",
+                                "sclk_epll", "sclk_vpll", };
+PNAME(mout_mixer_p4210) = { "sclk_dac", "sclk_hdmi", };
+PNAME(mout_dac_p4210)   = { "sclk_vpll", "sclk_hdmiphy", };
+
+/* Exynos 4x12-specific parent groups */
+PNAME(mout_mpll_user_p4x12) = { "fin_pll", "sclk_mpll", };
+PNAME(mout_core_p4x12)  = { "mout_apll", "mout_mpll_user_c", };
+PNAME(sclk_ampll_p4x12) = { "mout_mpll_user_t", "sclk_apll", };
+PNAME(group1_p4x12)     = { "xxti", "xusbxti", "sclk_hdmi24m", "sclk_usbphy0",
+                                "none", "sclk_hdmiphy", "mout_mpll_user_t",
+                                "sclk_epll", "sclk_vpll", };
+PNAME(mout_audio0_p4x12) = { "cdclk0", "none", "sclk_hdmi24m",
+                                "sclk_usbphy0", "xxti", "xusbxti",
+                                "mout_mpll_user_t", "sclk_epll", "sclk_vpll" };
+PNAME(mout_audio1_p4x12) = { "cdclk1", "none", "sclk_hdmi24m",
+                                "sclk_usbphy0", "xxti", "xusbxti",
+                                "mout_mpll_user_t", "sclk_epll", "sclk_vpll", };
+PNAME(mout_audio2_p4x12) = { "cdclk2", "none", "sclk_hdmi24m",
+                                "sclk_usbphy0", "xxti", "xusbxti",
+                                "mout_mpll_user_t", "sclk_epll", "sclk_vpll", };
+PNAME(aclk_p4412)       = { "mout_mpll_user_t", "sclk_apll", };
+PNAME(mout_user_aclk400_mcuisp_p4x12) = {"fin_pll", "div_aclk400_mcuisp", };
+PNAME(mout_user_aclk200_p4x12) = {"fin_pll", "div_aclk200", };
+PNAME(mout_user_aclk266_gps_p4x12) = {"fin_pll", "div_aclk266_gps", };
+
+/* fixed rate clocks generated outside the soc */
+struct samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata = {
+        FRATE(xxti, "xxti", NULL, CLK_IS_ROOT, 0),
+        FRATE(xusbxti, "xusbxti", NULL, CLK_IS_ROOT, 0),
+};
+
+/* fixed rate clocks generated inside the soc */
+struct samsung_fixed_rate_clock exynos4_fixed_rate_clks[] __initdata = {
+        FRATE(none, "sclk_hdmi24m", NULL, CLK_IS_ROOT, 24000000),
+        FRATE(none, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 27000000),
+        FRATE(none, "sclk_usbphy0", NULL, CLK_IS_ROOT, 48000000),
+};
+
+struct samsung_fixed_rate_clock exynos4210_fixed_rate_clks[] __initdata = {
+        FRATE(none, "sclk_usbphy1", NULL, CLK_IS_ROOT, 48000000),
+};
+
+/* list of mux clocks supported in all exynos4 soc's */
+struct samsung_mux_clock exynos4_mux_clks[] __initdata = {
+        MUX_F(mout_apll, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
+                        CLK_SET_RATE_PARENT, 0),
+        MUX(none, "mout_hdmi", mout_hdmi_p, SRC_TV, 0, 1),
+        MUX(none, "mout_mfc1", sclk_evpll_p, SRC_MFC, 4, 1),
+        MUX(none, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1),
+        MUX_F(mout_g3d1, "mout_g3d1", sclk_evpll_p, SRC_G3D, 4, 1,
+                        CLK_SET_RATE_PARENT, 0),
+        MUX_F(mout_g3d, "mout_g3d", mout_g3d_p, SRC_G3D, 8, 1,
+                        CLK_SET_RATE_PARENT, 0),
+        MUX(none, "mout_spdif", mout_spdif_p, SRC_PERIL1, 8, 2),
+        MUX(none, "mout_onenand1", mout_onenand1_p, SRC_TOP0, 0, 1),
+        MUX_A(sclk_epll, "sclk_epll", mout_epll_p, SRC_TOP0, 4, 1, "sclk_epll"),
+        MUX(none, "mout_onenand", mout_onenand_p, SRC_TOP0, 28, 1),
+};
+
+/* list of mux clocks supported in exynos4210 soc */
+struct samsung_mux_clock exynos4210_mux_clks[] __initdata = {
+        MUX(none, "mout_aclk200", sclk_ampll_p4210, SRC_TOP0, 12, 1),
+        MUX(none, "mout_aclk100", sclk_ampll_p4210, SRC_TOP0, 16, 1),
+        MUX(none, "mout_aclk160", sclk_ampll_p4210, SRC_TOP0, 20, 1),
+        MUX(none, "mout_aclk133", sclk_ampll_p4210, SRC_TOP0, 24, 1),
+        MUX(none, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP1, 0, 1),
+        MUX(none, "mout_mixer", mout_mixer_p4210, SRC_TV, 4, 1),
+        MUX(none, "mout_dac", mout_dac_p4210, SRC_TV, 8, 1),
+        MUX(none, "mout_g2d0", sclk_ampll_p4210, E4210_SRC_IMAGE, 0, 1),
+        MUX(none, "mout_g2d1", sclk_evpll_p, E4210_SRC_IMAGE, 4, 1),
+        MUX(none, "mout_g2d", mout_g2d_p, E4210_SRC_IMAGE, 8, 1),
+        MUX(none, "mout_fimd1", group1_p4210, E4210_SRC_LCD1, 0, 4),
+        MUX(none, "mout_mipi1", group1_p4210, E4210_SRC_LCD1, 12, 4),
+        MUX_A(sclk_mpll, "sclk_mpll", mout_mpll_p, SRC_CPU, 8, 1, "sclk_mpll"),
+        MUX_A(mout_core, "mout_core", mout_core_p4210,
+                        SRC_CPU, 16, 1, "mout_core"),
+        MUX_A(sclk_vpll, "sclk_vpll", sclk_vpll_p4210,
+                        SRC_TOP0, 8, 1, "sclk_vpll"),
+        MUX(mout_fimc0, "mout_fimc0", group1_p4210, SRC_CAM, 0, 4),
+        MUX(mout_fimc1, "mout_fimc1", group1_p4210, SRC_CAM, 4, 4),
+        MUX(mout_fimc2, "mout_fimc2", group1_p4210, SRC_CAM, 8, 4),
+        MUX(mout_fimc3, "mout_fimc3", group1_p4210, SRC_CAM, 12, 4),
+        MUX(mout_cam0, "mout_cam0", group1_p4210, SRC_CAM, 16, 4),
+        MUX(mout_cam1, "mout_cam1", group1_p4210, SRC_CAM, 20, 4),
+        MUX(mout_csis0, "mout_csis0", group1_p4210, SRC_CAM, 24, 4),
+        MUX(mout_csis1, "mout_csis1", group1_p4210, SRC_CAM, 28, 4),
+        MUX(none, "mout_mfc0", sclk_ampll_p4210, SRC_MFC, 0, 1),
+        MUX_F(mout_g3d0, "mout_g3d0", sclk_ampll_p4210, SRC_G3D, 0, 1,
+                        CLK_SET_RATE_PARENT, 0),
+        MUX(none, "mout_fimd0", group1_p4210, SRC_LCD0, 0, 4),
+        MUX(none, "mout_mipi0", group1_p4210, SRC_LCD0, 12, 4),
+        MUX(none, "mout_audio0", mout_audio0_p4210, SRC_MAUDIO, 0, 4),
+        MUX(none, "mout_mmc0", group1_p4210, SRC_FSYS, 0, 4),
+        MUX(none, "mout_mmc1", group1_p4210, SRC_FSYS, 4, 4),
+        MUX(none, "mout_mmc2", group1_p4210, SRC_FSYS, 8, 4),
+        MUX(none, "mout_mmc3", group1_p4210, SRC_FSYS, 12, 4),
+        MUX(none, "mout_mmc4", group1_p4210, SRC_FSYS, 16, 4),
+        MUX(none, "mout_sata", sclk_ampll_p4210, SRC_FSYS, 24, 1),
+        MUX(none, "mout_uart0", group1_p4210, SRC_PERIL0, 0, 4),
+        MUX(none, "mout_uart1", group1_p4210, SRC_PERIL0, 4, 4),
+        MUX(none, "mout_uart2", group1_p4210, SRC_PERIL0, 8, 4),
+        MUX(none, "mout_uart3", group1_p4210, SRC_PERIL0, 12, 4),
+        MUX(none, "mout_uart4", group1_p4210, SRC_PERIL0, 16, 4),
+        MUX(none, "mout_audio1", mout_audio1_p4210, SRC_PERIL1, 0, 4),
+        MUX(none, "mout_audio2", mout_audio2_p4210, SRC_PERIL1, 4, 4),
+        MUX(none, "mout_spi0", group1_p4210, SRC_PERIL1, 16, 4),
+        MUX(none, "mout_spi1", group1_p4210, SRC_PERIL1, 20, 4),
+        MUX(none, "mout_spi2", group1_p4210, SRC_PERIL1, 24, 4),
+};
+
+/* list of mux clocks supported in exynos4x12 soc */
+struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = {
+        MUX(mout_mpll_user_c, "mout_mpll_user_c", mout_mpll_user_p4x12,
+                        SRC_CPU, 24, 1),
+        MUX(none, "mout_aclk266_gps", aclk_p4412, SRC_TOP1, 4, 1),
+        MUX(none, "mout_aclk400_mcuisp", aclk_p4412, SRC_TOP1, 8, 1),
+        MUX(mout_mpll_user_t, "mout_mpll_user_t", mout_mpll_user_p4x12,
+                        SRC_TOP1, 12, 1),
+        MUX(none, "mout_user_aclk266_gps", mout_user_aclk266_gps_p4x12,
+                        SRC_TOP1, 16, 1),
+        MUX(aclk200, "aclk200", mout_user_aclk200_p4x12, SRC_TOP1, 20, 1),
+        MUX(aclk400_mcuisp, "aclk400_mcuisp", mout_user_aclk400_mcuisp_p4x12,
+                        SRC_TOP1, 24, 1),
+        MUX(none, "mout_aclk200", aclk_p4412, SRC_TOP0, 12, 1),
+        MUX(none, "mout_aclk100", aclk_p4412, SRC_TOP0, 16, 1),
+        MUX(none, "mout_aclk160", aclk_p4412, SRC_TOP0, 20, 1),
+        MUX(none, "mout_aclk133", aclk_p4412, SRC_TOP0, 24, 1),
+        MUX(none, "mout_mdnie0", group1_p4x12, SRC_LCD0, 4, 4),
+        MUX(none, "mout_mdnie_pwm0", group1_p4x12, SRC_LCD0, 8, 4),
+        MUX(none, "mout_sata", sclk_ampll_p4x12, SRC_FSYS, 24, 1),
+        MUX(none, "mout_jpeg0", sclk_ampll_p4x12, E4X12_SRC_CAM1, 0, 1),
+        MUX(none, "mout_jpeg1", sclk_evpll_p, E4X12_SRC_CAM1, 4, 1),
+        MUX(none, "mout_jpeg", mout_jpeg_p, E4X12_SRC_CAM1, 8, 1),
+        MUX_A(sclk_mpll, "sclk_mpll", mout_mpll_p,
+                        SRC_DMC, 12, 1, "sclk_mpll"),
+        MUX_A(sclk_vpll, "sclk_vpll", mout_vpll_p,
+                        SRC_TOP0, 8, 1, "sclk_vpll"),
+        MUX(mout_core, "mout_core", mout_core_p4x12, SRC_CPU, 16, 1),
+        MUX(mout_fimc0, "mout_fimc0", group1_p4x12, SRC_CAM, 0, 4),
+        MUX(mout_fimc1, "mout_fimc1", group1_p4x12, SRC_CAM, 4, 4),
+        MUX(mout_fimc2, "mout_fimc2", group1_p4x12, SRC_CAM, 8, 4),
+        MUX(mout_fimc3, "mout_fimc3", group1_p4x12, SRC_CAM, 12, 4),
+        MUX(mout_cam0, "mout_cam0", group1_p4x12, SRC_CAM, 16, 4),
+        MUX(mout_cam1, "mout_cam1", group1_p4x12, SRC_CAM, 20, 4),
+        MUX(mout_csis0, "mout_csis0", group1_p4x12, SRC_CAM, 24, 4),
+        MUX(mout_csis1, "mout_csis1", group1_p4x12, SRC_CAM, 28, 4),
+        MUX(none, "mout_mfc0", sclk_ampll_p4x12, SRC_MFC, 0, 1),
+        MUX_F(mout_g3d0, "mout_g3d0", sclk_ampll_p4x12, SRC_G3D, 0, 1,
+                        CLK_SET_RATE_PARENT, 0),
+        MUX(none, "mout_fimd0", group1_p4x12, SRC_LCD0, 0, 4),
+        MUX(none, "mout_mipi0", group1_p4x12, SRC_LCD0, 12, 4),
+        MUX(none, "mout_audio0", mout_audio0_p4x12, SRC_MAUDIO, 0, 4),
+        MUX(none, "mout_mmc0", group1_p4x12, SRC_FSYS, 0, 4),
+        MUX(none, "mout_mmc1", group1_p4x12, SRC_FSYS, 4, 4),
+        MUX(none, "mout_mmc2", group1_p4x12, SRC_FSYS, 8, 4),
+        MUX(none, "mout_mmc3", group1_p4x12, SRC_FSYS, 12, 4),
+        MUX(none, "mout_mmc4", group1_p4x12, SRC_FSYS, 16, 4),
+        MUX(none, "mout_mipihsi", aclk_p4412, SRC_FSYS, 24, 1),
+        MUX(none, "mout_uart0", group1_p4x12, SRC_PERIL0, 0, 4),
+        MUX(none, "mout_uart1", group1_p4x12, SRC_PERIL0, 4, 4),
+        MUX(none, "mout_uart2", group1_p4x12, SRC_PERIL0, 8, 4),
+        MUX(none, "mout_uart3", group1_p4x12, SRC_PERIL0, 12, 4),
+        MUX(none, "mout_uart4", group1_p4x12, SRC_PERIL0, 16, 4),
+        MUX(none, "mout_audio1", mout_audio1_p4x12, SRC_PERIL1, 0, 4),
+        MUX(none, "mout_audio2", mout_audio2_p4x12, SRC_PERIL1, 4, 4),
+        MUX(none, "mout_spi0", group1_p4x12, SRC_PERIL1, 16, 4),
+        MUX(none, "mout_spi1", group1_p4x12, SRC_PERIL1, 20, 4),
+        MUX(none, "mout_spi2", group1_p4x12, SRC_PERIL1, 24, 4),
+        MUX(none, "mout_pwm_isp", group1_p4x12, E4X12_SRC_ISP, 0, 4),
+        MUX(none, "mout_spi0_isp", group1_p4x12, E4X12_SRC_ISP, 4, 4),
+        MUX(none, "mout_spi1_isp", group1_p4x12, E4X12_SRC_ISP, 8, 4),
+        MUX(none, "mout_uart_isp", group1_p4x12, E4X12_SRC_ISP, 12, 4),
+};
+
+/* list of divider clocks supported in all exynos4 soc's */
+struct samsung_div_clock exynos4_div_clks[] __initdata = {
+        DIV(none, "div_core", "mout_core", DIV_CPU0, 0, 3),
+        DIV(none, "div_core2", "div_core", DIV_CPU0, 28, 3),
+        DIV(none, "div_fimc0", "mout_fimc0", DIV_CAM, 0, 4),
+        DIV(none, "div_fimc1", "mout_fimc1", DIV_CAM, 4, 4),
+        DIV(none, "div_fimc2", "mout_fimc2", DIV_CAM, 8, 4),
+        DIV(none, "div_fimc3", "mout_fimc3", DIV_CAM, 12, 4),
+        DIV(none, "div_cam0", "mout_cam0", DIV_CAM, 16, 4),
+        DIV(none, "div_cam1", "mout_cam1", DIV_CAM, 20, 4),
+        DIV(none, "div_csis0", "mout_csis0", DIV_CAM, 24, 4),
+        DIV(none, "div_csis1", "mout_csis1", DIV_CAM, 28, 4),
+        DIV(sclk_mfc, "sclk_mfc", "mout_mfc", DIV_MFC, 0, 4),
+        DIV_F(none, "div_g3d", "mout_g3d", DIV_G3D, 0, 4,
+                        CLK_SET_RATE_PARENT, 0),
+        DIV(none, "div_fimd0", "mout_fimd0", DIV_LCD0, 0, 4),
+        DIV(none, "div_mipi0", "mout_mipi0", DIV_LCD0, 16, 4),
+        DIV(none, "div_audio0", "mout_audio0", DIV_MAUDIO, 0, 4),
+        DIV(sclk_pcm0, "sclk_pcm0", "sclk_audio0", DIV_MAUDIO, 4, 8),
+        DIV(none, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
+        DIV(none, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
+        DIV(none, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),
+        DIV(none, "div_mmc3", "mout_mmc3", DIV_FSYS2, 16, 4),
+        DIV(sclk_pixel, "sclk_pixel", "sclk_vpll", DIV_TV, 0, 4),
+        DIV(aclk100, "aclk100", "mout_aclk100", DIV_TOP, 4, 4),
+        DIV(aclk160, "aclk160", "mout_aclk160", DIV_TOP, 8, 3),
+        DIV(aclk133, "aclk133", "mout_aclk133", DIV_TOP, 12, 3),
+        DIV(none, "div_onenand", "mout_onenand1", DIV_TOP, 16, 3),
+        DIV(sclk_slimbus, "sclk_slimbus", "sclk_epll", DIV_PERIL3, 4, 4),
+        DIV(sclk_pcm1, "sclk_pcm1", "sclk_audio1", DIV_PERIL4, 4, 8),
+        DIV(sclk_pcm2, "sclk_pcm2", "sclk_audio2", DIV_PERIL4, 20, 8),
+        DIV(sclk_i2s1, "sclk_i2s1", "sclk_audio1", DIV_PERIL5, 0, 6),
+        DIV(sclk_i2s2, "sclk_i2s2", "sclk_audio2", DIV_PERIL5, 8, 6),
+        DIV(none, "div_mmc4", "mout_mmc4", DIV_FSYS3, 0, 4),
+        DIV(none, "div_mmc_pre4", "div_mmc4", DIV_FSYS3, 8, 8),
+        DIV(none, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4),
+        DIV(none, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
+        DIV(none, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4),
+        DIV(none, "div_uart3", "mout_uart3", DIV_PERIL0, 12, 4),
+        DIV(none, "div_uart4", "mout_uart4", DIV_PERIL0, 16, 4),
+        DIV(none, "div_spi0", "mout_spi0", DIV_PERIL1, 0, 4),
+        DIV(none, "div_spi_pre0", "div_spi0", DIV_PERIL1, 8, 8),
+        DIV(none, "div_spi1", "mout_spi1", DIV_PERIL1, 16, 4),
+        DIV(none, "div_spi_pre1", "div_spi1", DIV_PERIL1, 24, 8),
+        DIV(none, "div_spi2", "mout_spi2", DIV_PERIL2, 0, 4),
+        DIV(none, "div_spi_pre2", "div_spi2", DIV_PERIL2, 8, 8),
+        DIV(none, "div_audio1", "mout_audio1", DIV_PERIL4, 0, 4),
+        DIV(none, "div_audio2", "mout_audio2", DIV_PERIL4, 16, 4),
+        DIV_A(arm_clk, "arm_clk", "div_core2", DIV_CPU0, 28, 3, "arm_clk"),
+        DIV_A(sclk_apll, "sclk_apll", "mout_apll",
+                        DIV_CPU0, 24, 3, "sclk_apll"),
+        DIV_F(none, "div_mipi_pre0", "div_mipi0", DIV_LCD0, 20, 4,
+                        CLK_SET_RATE_PARENT, 0),
+        DIV_F(none, "div_mmc_pre0", "div_mmc0", DIV_FSYS1, 8, 8,
+                        CLK_SET_RATE_PARENT, 0),
+        DIV_F(none, "div_mmc_pre1", "div_mmc1", DIV_FSYS1, 24, 8,
+                        CLK_SET_RATE_PARENT, 0),
+        DIV_F(none, "div_mmc_pre2", "div_mmc2", DIV_FSYS2, 8, 8,
+                        CLK_SET_RATE_PARENT, 0),
+        DIV_F(none, "div_mmc_pre3", "div_mmc3", DIV_FSYS2, 24, 8,
+                        CLK_SET_RATE_PARENT, 0),
+};
+
+/* list of divider clocks supported in exynos4210 soc */
+struct samsung_div_clock exynos4210_div_clks[] __initdata = {
+        DIV(aclk200, "aclk200", "mout_aclk200", DIV_TOP, 0, 3),
+        DIV(none, "div_g2d", "mout_g2d", DIV_IMAGE, 0, 4),
+        DIV(none, "div_fimd1", "mout_fimd1", E4210_DIV_LCD1, 0, 4),
+        DIV(none, "div_mipi1", "mout_mipi1", E4210_DIV_LCD1, 16, 4),
+        DIV(none, "div_sata", "mout_sata", DIV_FSYS0, 20, 4),
+        DIV_F(none, "div_mipi_pre1", "div_mipi1", E4210_DIV_LCD1, 20, 4,
+                        CLK_SET_RATE_PARENT, 0),
+};
+
+/* list of divider clocks supported in exynos4x12 soc */
+struct samsung_div_clock exynos4x12_div_clks[] __initdata = {
+        DIV(none, "div_mdnie0", "mout_mdnie0", DIV_LCD0, 4, 4),
+        DIV(none, "div_mdnie_pwm0", "mout_mdnie_pwm0", DIV_LCD0, 8, 4),
+        DIV(none, "div_mdnie_pwm_pre0", "div_mdnie_pwm0", DIV_LCD0, 12, 4),
+        DIV(none, "div_mipihsi", "mout_mipihsi", DIV_FSYS0, 20, 4),
+        DIV(none, "div_jpeg", "mout_jpeg", E4X12_DIV_CAM1, 0, 4),
+        DIV(div_aclk200, "div_aclk200", "mout_aclk200", DIV_TOP, 0, 3),
+        DIV(none, "div_aclk266_gps", "mout_aclk266_gps", DIV_TOP, 20, 3),
+        DIV(div_aclk400_mcuisp, "div_aclk400_mcuisp", "mout_aclk400_mcuisp",
+                                                DIV_TOP, 24, 3),
+        DIV(none, "div_pwm_isp", "mout_pwm_isp", E4X12_DIV_ISP, 0, 4),
+        DIV(none, "div_spi0_isp", "mout_spi0_isp", E4X12_DIV_ISP, 4, 4),
+        DIV(none, "div_spi0_isp_pre", "div_spi0_isp", E4X12_DIV_ISP, 8, 8),
+        DIV(none, "div_spi1_isp", "mout_spi1_isp", E4X12_DIV_ISP, 16, 4),
+        DIV(none, "div_spi1_isp_pre", "div_spi1_isp", E4X12_DIV_ISP, 20, 8),
+        DIV(none, "div_uart_isp", "mout_uart_isp", E4X12_DIV_ISP, 28, 4),
+        DIV(div_isp0, "div_isp0", "aclk200", E4X12_DIV_ISP0, 0, 3),
+        DIV(div_isp1, "div_isp1", "aclk200", E4X12_DIV_ISP0, 4, 3),
+        DIV(none, "div_mpwm", "div_isp1", E4X12_DIV_ISP1, 0, 3),
+        DIV(div_mcuisp0, "div_mcuisp0", "aclk400_mcuisp", E4X12_DIV_ISP1, 4, 3),
+        DIV(div_mcuisp1, "div_mcuisp1", "div_mcuisp0", E4X12_DIV_ISP1, 8, 3),
+};
+
+/* list of gate clocks supported in all exynos4 soc's */
+struct samsung_gate_clock exynos4_gate_clks[] __initdata = {
+        /*
+         * After all Exynos4 based platforms are migrated to use device tree,
+         * the device name and clock alias names specified below for some
+         * of the clocks can be removed.
+         */
+        GATE(sclk_hdmi, "sclk_hdmi", "mout_hdmi", SRC_MASK_TV, 0, 0, 0),
+        GATE(sclk_spdif, "sclk_spdif", "mout_spdif", SRC_MASK_PERIL1, 8, 0, 0),
+        GATE(jpeg, "jpeg", "aclk160", GATE_IP_CAM, 6, 0, 0),
+        GATE(mie0, "mie0", "aclk160", GATE_IP_LCD0, 1, 0, 0),
+        GATE(dsim0, "dsim0", "aclk160", GATE_IP_LCD0, 3, 0, 0),
+        GATE(fimd1, "fimd1", "aclk160", E4210_GATE_IP_LCD1, 0, 0, 0),
+        GATE(mie1, "mie1", "aclk160", E4210_GATE_IP_LCD1, 1, 0, 0),
+        GATE(dsim1, "dsim1", "aclk160", E4210_GATE_IP_LCD1, 3, 0, 0),
+        GATE(smmu_fimd1, "smmu_fimd1", "aclk160", E4210_GATE_IP_LCD1, 4, 0, 0),
+        GATE(tsi, "tsi", "aclk133", GATE_IP_FSYS, 4, 0, 0),
+        GATE(sromc, "sromc", "aclk133", GATE_IP_FSYS, 11, 0, 0),
+        GATE(sclk_g3d, "sclk_g3d", "div_g3d", GATE_IP_G3D, 0,
+                        CLK_SET_RATE_PARENT, 0),
+        GATE(usb_device, "usb_device", "aclk133", GATE_IP_FSYS, 13, 0, 0),
+        GATE(onenand, "onenand", "aclk133", GATE_IP_FSYS, 15, 0, 0),
+        GATE(nfcon, "nfcon", "aclk133", GATE_IP_FSYS, 16, 0, 0),
+        GATE(gps, "gps", "aclk133", GATE_IP_GPS, 0, 0, 0),
+        GATE(smmu_gps, "smmu_gps", "aclk133", GATE_IP_GPS, 1, 0, 0),
+        GATE(slimbus, "slimbus", "aclk100", GATE_IP_PERIL, 25, 0, 0),
+        GATE(sclk_cam0, "sclk_cam0", "div_cam0", GATE_SCLK_CAM, 4,
+                        CLK_SET_RATE_PARENT, 0),
+        GATE(sclk_cam1, "sclk_cam1", "div_cam1", GATE_SCLK_CAM, 5,
+                        CLK_SET_RATE_PARENT, 0),
+        GATE(sclk_mipi0, "sclk_mipi0", "div_mipi_pre0",
+                        SRC_MASK_LCD0, 12, CLK_SET_RATE_PARENT, 0),
+        GATE(sclk_audio0, "sclk_audio0", "div_audio0", SRC_MASK_MAUDIO, 0,
+                        CLK_SET_RATE_PARENT, 0),
+        GATE(sclk_audio1, "sclk_audio1", "div_audio1", SRC_MASK_PERIL1, 0,
+                        CLK_SET_RATE_PARENT, 0),
+        GATE_D(vp, "s5p-mixer", "vp", "aclk160", GATE_IP_TV, 0, 0, 0),
+        GATE_D(mixer, "s5p-mixer", "mixer", "aclk160", GATE_IP_TV, 1, 0, 0),
+        GATE_D(hdmi, "exynos4-hdmi", "hdmi", "aclk160", GATE_IP_TV, 3, 0, 0),
+        GATE_A(pwm, "pwm", "aclk100", GATE_IP_PERIL, 24, 0, 0, "timers"),
+        GATE_A(sdmmc4, "sdmmc4", "aclk133", GATE_IP_FSYS, 9, 0, 0, "biu"),
+        GATE_A(usb_host, "usb_host", "aclk133",
+                        GATE_IP_FSYS, 12, 0, 0, "usbhost"),
+        GATE_DA(sclk_fimc0, "exynos4-fimc.0", "sclk_fimc0", "div_fimc0",
+                        SRC_MASK_CAM, 0, CLK_SET_RATE_PARENT, 0, "sclk_fimc"),
+        GATE_DA(sclk_fimc1, "exynos4-fimc.1", "sclk_fimc1", "div_fimc1",
+                        SRC_MASK_CAM, 4, CLK_SET_RATE_PARENT, 0, "sclk_fimc"),
+        GATE_DA(sclk_fimc2, "exynos4-fimc.2", "sclk_fimc2", "div_fimc2",
+                        SRC_MASK_CAM, 8, CLK_SET_RATE_PARENT, 0, "sclk_fimc"),
+        GATE_DA(sclk_fimc3, "exynos4-fimc.3", "sclk_fimc3", "div_fimc3",
+                        SRC_MASK_CAM, 12, CLK_SET_RATE_PARENT, 0, "sclk_fimc"),
+        GATE_DA(sclk_csis0, "s5p-mipi-csis.0", "sclk_csis0", "div_csis0",
+                        SRC_MASK_CAM, 24, CLK_SET_RATE_PARENT, 0, "sclk_csis"),
+        GATE_DA(sclk_csis1, "s5p-mipi-csis.1", "sclk_csis1", "div_csis1",
+                        SRC_MASK_CAM, 28, CLK_SET_RATE_PARENT, 0, "sclk_csis"),
+        GATE_DA(sclk_fimd0, "exynos4-fb.0", "sclk_fimd0", "div_fimd0",
+                        SRC_MASK_LCD0, 0, CLK_SET_RATE_PARENT, 0, "sclk_fimd"),
+        GATE_DA(sclk_mmc0, "exynos4-sdhci.0", "sclk_mmc0", "div_mmc_pre0",
+                        SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0,
+                        "mmc_busclk.2"),
+        GATE_DA(sclk_mmc1, "exynos4-sdhci.1", "sclk_mmc1", "div_mmc_pre1",
+                        SRC_MASK_FSYS, 4, CLK_SET_RATE_PARENT, 0,
+                        "mmc_busclk.2"),
+        GATE_DA(sclk_mmc2, "exynos4-sdhci.2", "sclk_mmc2", "div_mmc_pre2",
+                        SRC_MASK_FSYS, 8, CLK_SET_RATE_PARENT, 0,
+                        "mmc_busclk.2"),
+        GATE_DA(sclk_mmc3, "exynos4-sdhci.3", "sclk_mmc3", "div_mmc_pre3",
+                        SRC_MASK_FSYS, 12, CLK_SET_RATE_PARENT, 0,
+                        "mmc_busclk.2"),
+        GATE_DA(sclk_mmc4, NULL, "sclk_mmc4", "div_mmc_pre4",
+                        SRC_MASK_FSYS, 16, CLK_SET_RATE_PARENT, 0, "ciu"),
+        GATE_DA(sclk_uart0, "exynos4210-uart.0", "uclk0", "div_uart0",
+                        SRC_MASK_PERIL0, 0, CLK_SET_RATE_PARENT,
+                        0, "clk_uart_baud0"),
+        GATE_DA(sclk_uart1, "exynos4210-uart.1", "uclk1", "div_uart1",
+                        SRC_MASK_PERIL0, 4, CLK_SET_RATE_PARENT,
+                        0, "clk_uart_baud0"),
+        GATE_DA(sclk_uart2, "exynos4210-uart.2", "uclk2", "div_uart2",
+                        SRC_MASK_PERIL0, 8, CLK_SET_RATE_PARENT,
+                        0, "clk_uart_baud0"),
+        GATE_DA(sclk_uart3, "exynos4210-uart.3", "uclk3", "div_uart3",
+                        SRC_MASK_PERIL0, 12, CLK_SET_RATE_PARENT,
+                        0, "clk_uart_baud0"),
+        GATE_DA(sclk_uart4, "exynos4210-uart.4", "uclk4", "div_uart4",
+                        SRC_MASK_PERIL0, 16, CLK_SET_RATE_PARENT,
+                        0, "clk_uart_baud0"),
+        GATE(sclk_audio2, "sclk_audio2", "div_audio2", SRC_MASK_PERIL1, 4,
+                        CLK_SET_RATE_PARENT, 0),
+        GATE_DA(sclk_spi0, "exynos4210-spi.0", "sclk_spi0", "div_spi_pre0",
+                        SRC_MASK_PERIL1, 16, CLK_SET_RATE_PARENT,
+                        0, "spi_busclk0"),
+        GATE_DA(sclk_spi1, "exynos4210-spi.1", "sclk_spi1", "div_spi_pre1",
+                        SRC_MASK_PERIL1, 20, CLK_SET_RATE_PARENT,
+                        0, "spi_busclk0"),
+        GATE_DA(sclk_spi2, "exynos4210-spi.2", "sclk_spi2", "div_spi_pre2",
+                        SRC_MASK_PERIL1, 24, CLK_SET_RATE_PARENT,
+                        0, "spi_busclk0"),
+        GATE_DA(fimc0, "exynos4-fimc.0", "fimc0", "aclk160",
+                        GATE_IP_CAM, 0, 0, 0, "fimc"),
+        GATE_DA(fimc1, "exynos4-fimc.1", "fimc1", "aclk160",
+                        GATE_IP_CAM, 1, 0, 0, "fimc"),
+        GATE_DA(fimc2, "exynos4-fimc.2", "fimc2", "aclk160",
+                        GATE_IP_CAM, 2, 0, 0, "fimc"),
+        GATE_DA(fimc3, "exynos4-fimc.3", "fimc3", "aclk160",
+                        GATE_IP_CAM, 3, 0, 0, "fimc"),
+        GATE_DA(csis0, "s5p-mipi-csis.0", "csis0", "aclk160",
+                        GATE_IP_CAM, 4, 0, 0, "fimc"),
+        GATE_DA(csis1, "s5p-mipi-csis.1", "csis1", "aclk160",
+                        GATE_IP_CAM, 5, 0, 0, "fimc"),
+        GATE_DA(smmu_fimc0, "exynos-sysmmu.5", "smmu_fimc0", "aclk160",
+                        GATE_IP_CAM, 7, 0, 0, "sysmmu"),
+        GATE_DA(smmu_fimc1, "exynos-sysmmu.6", "smmu_fimc1", "aclk160",
+                        GATE_IP_CAM, 8, 0, 0, "sysmmu"),
+        GATE_DA(smmu_fimc2, "exynos-sysmmu.7", "smmu_fimc2", "aclk160",
+                        GATE_IP_CAM, 9, 0, 0, "sysmmu"),
+        GATE_DA(smmu_fimc3, "exynos-sysmmu.8", "smmu_fimc3", "aclk160",
+                        GATE_IP_CAM, 10, 0, 0, "sysmmu"),
+        GATE_DA(smmu_jpeg, "exynos-sysmmu.3", "smmu_jpeg", "aclk160",
+                        GATE_IP_CAM, 11, 0, 0, "sysmmu"),
+        GATE(pixelasyncm0, "pxl_async0", "aclk160", GATE_IP_CAM, 17, 0, 0),
+        GATE(pixelasyncm1, "pxl_async1", "aclk160", GATE_IP_CAM, 18, 0, 0),
+        GATE_DA(smmu_tv, "exynos-sysmmu.2", "smmu_tv", "aclk160",
+                        GATE_IP_TV, 4, 0, 0, "sysmmu"),
+        GATE_DA(mfc, "s5p-mfc", "mfc", "aclk100", GATE_IP_MFC, 0, 0, 0, "mfc"),
+        GATE_DA(smmu_mfcl, "exynos-sysmmu.0", "smmu_mfcl", "aclk100",
+                        GATE_IP_MFC, 1, 0, 0, "sysmmu"),
+        GATE_DA(smmu_mfcr, "exynos-sysmmu.1", "smmu_mfcr", "aclk100",
+                        GATE_IP_MFC, 2, 0, 0, "sysmmu"),
+        GATE_DA(fimd0, "exynos4-fb.0", "fimd0", "aclk160",
+                        GATE_IP_LCD0, 0, 0, 0, "fimd"),
+        GATE_DA(smmu_fimd0, "exynos-sysmmu.10", "smmu_fimd0", "aclk160",
+                        GATE_IP_LCD0, 4, 0, 0, "sysmmu"),
+        GATE_DA(pdma0, "dma-pl330.0", "pdma0", "aclk133",
+                        GATE_IP_FSYS, 0, 0, 0, "dma"),
+        GATE_DA(pdma1, "dma-pl330.1", "pdma1", "aclk133",
+                        GATE_IP_FSYS, 1, 0, 0, "dma"),
+        GATE_DA(sdmmc0, "exynos4-sdhci.0", "sdmmc0", "aclk133",
+                        GATE_IP_FSYS, 5, 0, 0, "hsmmc"),
+        GATE_DA(sdmmc1, "exynos4-sdhci.1", "sdmmc1", "aclk133",
+                        GATE_IP_FSYS, 6, 0, 0, "hsmmc"),
+        GATE_DA(sdmmc2, "exynos4-sdhci.2", "sdmmc2", "aclk133",
+                        GATE_IP_FSYS, 7, 0, 0, "hsmmc"),
+        GATE_DA(sdmmc3, "exynos4-sdhci.3", "sdmmc3", "aclk133",
+                        GATE_IP_FSYS, 8, 0, 0, "hsmmc"),
+        GATE_DA(uart0, "exynos4210-uart.0", "uart0", "aclk100",
+                        GATE_IP_PERIL, 0, 0, 0, "uart"),
+        GATE_DA(uart1, "exynos4210-uart.1", "uart1", "aclk100",
+                        GATE_IP_PERIL, 1, 0, 0, "uart"),
+        GATE_DA(uart2, "exynos4210-uart.2", "uart2", "aclk100",
+                        GATE_IP_PERIL, 2, 0, 0, "uart"),
+        GATE_DA(uart3, "exynos4210-uart.3", "uart3", "aclk100",
+                        GATE_IP_PERIL, 3, 0, 0, "uart"),
+        GATE_DA(uart4, "exynos4210-uart.4", "uart4", "aclk100",
+                        GATE_IP_PERIL, 4, 0, 0, "uart"),
+        GATE_DA(i2c0, "s3c2440-i2c.0", "i2c0", "aclk100",
+                        GATE_IP_PERIL, 6, 0, 0, "i2c"),
+        GATE_DA(i2c1, "s3c2440-i2c.1", "i2c1", "aclk100",
+                        GATE_IP_PERIL, 7, 0, 0, "i2c"),
+        GATE_DA(i2c2, "s3c2440-i2c.2", "i2c2", "aclk100",
+                        GATE_IP_PERIL, 8, 0, 0, "i2c"),
+        GATE_DA(i2c3, "s3c2440-i2c.3", "i2c3", "aclk100",
+                        GATE_IP_PERIL, 9, 0, 0, "i2c"),
+        GATE_DA(i2c4, "s3c2440-i2c.4", "i2c4", "aclk100",
+                        GATE_IP_PERIL, 10, 0, 0, "i2c"),
+        GATE_DA(i2c5, "s3c2440-i2c.5", "i2c5", "aclk100",
+                        GATE_IP_PERIL, 11, 0, 0, "i2c"),
+        GATE_DA(i2c6, "s3c2440-i2c.6", "i2c6", "aclk100",
+                        GATE_IP_PERIL, 12, 0, 0, "i2c"),
+        GATE_DA(i2c7, "s3c2440-i2c.7", "i2c7", "aclk100",
+                        GATE_IP_PERIL, 13, 0, 0, "i2c"),
+        GATE_DA(i2c_hdmi, "s3c2440-hdmiphy-i2c", "i2c-hdmi", "aclk100",
+                        GATE_IP_PERIL, 14, 0, 0, "i2c"),
+        GATE_DA(spi0, "exynos4210-spi.0", "spi0", "aclk100",
+                        GATE_IP_PERIL, 16, 0, 0, "spi"),
+        GATE_DA(spi1, "exynos4210-spi.1", "spi1", "aclk100",
+                        GATE_IP_PERIL, 17, 0, 0, "spi"),
+        GATE_DA(spi2, "exynos4210-spi.2", "spi2", "aclk100",
+                        GATE_IP_PERIL, 18, 0, 0, "spi"),
+        GATE_DA(i2s1, "samsung-i2s.1", "i2s1", "aclk100",
+                        GATE_IP_PERIL, 20, 0, 0, "iis"),
+        GATE_DA(i2s2, "samsung-i2s.2", "i2s2", "aclk100",
+                        GATE_IP_PERIL, 21, 0, 0, "iis"),
+        GATE_DA(pcm1, "samsung-pcm.1", "pcm1", "aclk100",
+                        GATE_IP_PERIL, 22, 0, 0, "pcm"),
+        GATE_DA(pcm2, "samsung-pcm.2", "pcm2", "aclk100",
+                        GATE_IP_PERIL, 23, 0, 0, "pcm"),
+        GATE_DA(spdif, "samsung-spdif", "spdif", "aclk100",
+                        GATE_IP_PERIL, 26, 0, 0, "spdif"),
+        GATE_DA(ac97, "samsung-ac97", "ac97", "aclk100",
+                        GATE_IP_PERIL, 27, 0, 0, "ac97"),
+};
+
+/* list of gate clocks supported in exynos4210 soc */
+struct samsung_gate_clock exynos4210_gate_clks[] __initdata = {
+        GATE(tvenc, "tvenc", "aclk160", GATE_IP_TV, 2, 0, 0),
+        GATE(g2d, "g2d", "aclk200", E4210_GATE_IP_IMAGE, 0, 0, 0),
+        GATE(rotator, "rotator", "aclk200", E4210_GATE_IP_IMAGE, 1, 0, 0),
+        GATE(mdma, "mdma", "aclk200", E4210_GATE_IP_IMAGE, 2, 0, 0),
+        GATE(smmu_g2d, "smmu_g2d", "aclk200", E4210_GATE_IP_IMAGE, 3, 0, 0),
+        GATE(smmu_mdma, "smmu_mdma", "aclk200", E4210_GATE_IP_IMAGE, 5, 0, 0),
+        GATE(pcie_phy, "pcie_phy", "aclk133", GATE_IP_FSYS, 2, 0, 0),
+        GATE(sata_phy, "sata_phy", "aclk133", GATE_IP_FSYS, 3, 0, 0),
+        GATE(sata, "sata", "aclk133", GATE_IP_FSYS, 10, 0, 0),
+        GATE(pcie, "pcie", "aclk133", GATE_IP_FSYS, 14, 0, 0),
+        GATE(smmu_pcie, "smmu_pcie", "aclk133", GATE_IP_FSYS, 18, 0, 0),
+        GATE(modemif, "modemif", "aclk100", GATE_IP_PERIL, 28, 0, 0),
+        GATE(chipid, "chipid", "aclk100", E4210_GATE_IP_PERIR, 0, 0, 0),
+        GATE(sysreg, "sysreg", "aclk100", E4210_GATE_IP_PERIR, 0, 0, 0),
+        GATE(hdmi_cec, "hdmi_cec", "aclk100", E4210_GATE_IP_PERIR, 11, 0, 0),
+        GATE(smmu_rotator, "smmu_rotator", "aclk200",
+                        E4210_GATE_IP_IMAGE, 4, 0, 0),
+        GATE(sclk_mipi1, "sclk_mipi1", "div_mipi_pre1",
+                        E4210_SRC_MASK_LCD1, 12, CLK_SET_RATE_PARENT, 0),
+        GATE(sclk_sata, "sclk_sata", "div_sata",
+                        SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
+        GATE(sclk_mixer, "sclk_mixer", "mout_mixer", SRC_MASK_TV, 4, 0, 0),
+        GATE(sclk_dac, "sclk_dac", "mout_dac", SRC_MASK_TV, 8, 0, 0),
+        GATE_A(tsadc, "tsadc", "aclk100", GATE_IP_PERIL, 15, 0, 0, "adc"),
+        GATE_A(mct, "mct", "aclk100", E4210_GATE_IP_PERIR, 13, 0, 0, "mct"),
+        GATE_A(wdt, "watchdog", "aclk100", E4210_GATE_IP_PERIR, 14, 0, 0, "watchdog"),
+        GATE_A(rtc, "rtc", "aclk100", E4210_GATE_IP_PERIR, 15, 0, 0, "rtc"),
+        GATE_A(keyif, "keyif", "aclk100", E4210_GATE_IP_PERIR, 16, 0, 0, "keypad"),
+        GATE_DA(sclk_fimd1, "exynos4-fb.1", "sclk_fimd1", "div_fimd1",
+                        E4210_SRC_MASK_LCD1, 0, CLK_SET_RATE_PARENT, 0, "sclk_fimd"),
+};
+
+/* list of gate clocks supported in exynos4x12 soc */
+struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = {
+        GATE(audss, "audss", "sclk_epll", E4X12_GATE_IP_MAUDIO, 0, 0, 0),
+        GATE(mdnie0, "mdnie0", "aclk160", GATE_IP_LCD0, 2, 0, 0),
+        GATE(rotator, "rotator", "aclk200", E4X12_GATE_IP_IMAGE, 1, 0, 0),
+        GATE(mdma2, "mdma2", "aclk200", E4X12_GATE_IP_IMAGE, 2, 0, 0),
+        GATE(smmu_mdma, "smmu_mdma", "aclk200", E4X12_GATE_IP_IMAGE, 5, 0, 0),
+        GATE(mipi_hsi, "mipi_hsi", "aclk133", GATE_IP_FSYS, 10, 0, 0),
+        GATE(chipid, "chipid", "aclk100", E4X12_GATE_IP_PERIR, 0, 0, 0),
+        GATE(sysreg, "sysreg", "aclk100", E4X12_GATE_IP_PERIR, 1, 0, 0),
+        GATE(hdmi_cec, "hdmi_cec", "aclk100", E4X12_GATE_IP_PERIR, 11, 0, 0),
+        GATE(sclk_mdnie0, "sclk_mdnie0", "div_mdnie0",
+                        SRC_MASK_LCD0, 4, CLK_SET_RATE_PARENT, 0),
+        GATE(sclk_mdnie_pwm0, "sclk_mdnie_pwm0", "div_mdnie_pwm_pre0",
+                        SRC_MASK_LCD0, 8, CLK_SET_RATE_PARENT, 0),
+        GATE(sclk_mipihsi, "sclk_mipihsi", "div_mipihsi",
+                        SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
+        GATE(smmu_rotator, "smmu_rotator", "aclk200",
+                        E4X12_GATE_IP_IMAGE, 4, 0, 0),
+        GATE_A(mct, "mct", "aclk100", E4X12_GATE_IP_PERIR, 13, 0, 0, "mct"),
+        GATE_A(rtc, "rtc", "aclk100", E4X12_GATE_IP_PERIR, 15, 0, 0, "rtc"),
+        GATE_A(keyif, "keyif", "aclk100",
+                        E4X12_GATE_IP_PERIR, 16, 0, 0, "keypad"),
+        GATE(sclk_pwm_isp, "sclk_pwm_isp", "div_pwm_isp",
+                        E4X12_SRC_MASK_ISP, 0, CLK_SET_RATE_PARENT, 0),
+        GATE(sclk_spi0_isp, "sclk_spi0_isp", "div_spi0_isp_pre",
+                        E4X12_SRC_MASK_ISP, 4, CLK_SET_RATE_PARENT, 0),
+        GATE(sclk_spi1_isp, "sclk_spi1_isp", "div_spi1_isp_pre",
+                        E4X12_SRC_MASK_ISP, 8, CLK_SET_RATE_PARENT, 0),
+        GATE(sclk_uart_isp, "sclk_uart_isp", "div_uart_isp",
+                        E4X12_SRC_MASK_ISP, 12, CLK_SET_RATE_PARENT, 0),
+        GATE(pwm_isp_sclk, "pwm_isp_sclk", "sclk_pwm_isp",
+                        E4X12_GATE_IP_ISP, 0, 0, 0),
+        GATE(spi0_isp_sclk, "spi0_isp_sclk", "sclk_spi0_isp",
+                        E4X12_GATE_IP_ISP, 1, 0, 0),
+        GATE(spi1_isp_sclk, "spi1_isp_sclk", "sclk_spi1_isp",
+                        E4X12_GATE_IP_ISP, 2, 0, 0),
+        GATE(uart_isp_sclk, "uart_isp_sclk", "sclk_uart_isp",
+                        E4X12_GATE_IP_ISP, 3, 0, 0),
+        GATE_A(wdt, "watchdog", "aclk100",
+                        E4X12_GATE_IP_PERIR, 14, 0, 0, "watchdog"),
+        GATE_DA(pcm0, "samsung-pcm.0", "pcm0", "aclk100",
+                        E4X12_GATE_IP_MAUDIO, 2, 0, 0, "pcm"),
+        GATE_DA(i2s0, "samsung-i2s.0", "i2s0", "aclk100",
+                        E4X12_GATE_IP_MAUDIO, 3, 0, 0, "iis"),
+        GATE(fimc_isp, "isp", "aclk200", E4X12_GATE_ISP0, 0,
+                        CLK_IGNORE_UNUSED, 0),
+        GATE(fimc_drc, "drc", "aclk200", E4X12_GATE_ISP0, 1,
+                        CLK_IGNORE_UNUSED, 0),
+        GATE(fimc_fd, "fd", "aclk200", E4X12_GATE_ISP0, 2,
+                        CLK_IGNORE_UNUSED, 0),
+        GATE(fimc_lite0, "lite0", "aclk200", E4X12_GATE_ISP0, 3,
+                        CLK_IGNORE_UNUSED, 0),
+        GATE(fimc_lite1, "lite1", "aclk200", E4X12_GATE_ISP0, 4,
+                        CLK_IGNORE_UNUSED, 0),
+        GATE(mcuisp, "mcuisp", "aclk200", E4X12_GATE_ISP0, 5,
+                        CLK_IGNORE_UNUSED, 0),
+        GATE(gicisp, "gicisp", "aclk200", E4X12_GATE_ISP0, 7,
+                        CLK_IGNORE_UNUSED, 0),
+        GATE(smmu_isp, "smmu_isp", "aclk200", E4X12_GATE_ISP0, 8,
+                        CLK_IGNORE_UNUSED, 0),
+        GATE(smmu_drc, "smmu_drc", "aclk200", E4X12_GATE_ISP0, 9,
+                        CLK_IGNORE_UNUSED, 0),
+        GATE(smmu_fd, "smmu_fd", "aclk200", E4X12_GATE_ISP0, 10,
+                        CLK_IGNORE_UNUSED, 0),
+        GATE(smmu_lite0, "smmu_lite0", "aclk200", E4X12_GATE_ISP0, 11,
+                        CLK_IGNORE_UNUSED, 0),
+        GATE(smmu_lite1, "smmu_lite1", "aclk200", E4X12_GATE_ISP0, 12,
+                        CLK_IGNORE_UNUSED, 0),
+        GATE(ppmuispmx, "ppmuispmx", "aclk200", E4X12_GATE_ISP0, 20,
+                        CLK_IGNORE_UNUSED, 0),
+        GATE(ppmuispx, "ppmuispx", "aclk200", E4X12_GATE_ISP0, 21,
+                        CLK_IGNORE_UNUSED, 0),
+        GATE(mcuctl_isp, "mcuctl_isp", "aclk200", E4X12_GATE_ISP0, 23,
+                        CLK_IGNORE_UNUSED, 0),
+        GATE(mpwm_isp, "mpwm_isp", "aclk200", E4X12_GATE_ISP0, 24,
+                        CLK_IGNORE_UNUSED, 0),
+        GATE(i2c0_isp, "i2c0_isp", "aclk200", E4X12_GATE_ISP0, 25,
+                        CLK_IGNORE_UNUSED, 0),
+        GATE(i2c1_isp, "i2c1_isp", "aclk200", E4X12_GATE_ISP0, 26,
+                        CLK_IGNORE_UNUSED, 0),
+        GATE(mtcadc_isp, "mtcadc_isp", "aclk200", E4X12_GATE_ISP0, 27,
+                        CLK_IGNORE_UNUSED, 0),
+        GATE(pwm_isp, "pwm_isp", "aclk200", E4X12_GATE_ISP0, 28,
+                        CLK_IGNORE_UNUSED, 0),
+        GATE(wdt_isp, "wdt_isp", "aclk200", E4X12_GATE_ISP0, 30,
+                        CLK_IGNORE_UNUSED, 0),
+        GATE(uart_isp, "uart_isp", "aclk200", E4X12_GATE_ISP0, 31,
+                        CLK_IGNORE_UNUSED, 0),
+        GATE(asyncaxim, "asyncaxim", "aclk200", E4X12_GATE_ISP1, 0,
+                        CLK_IGNORE_UNUSED, 0),
+        GATE(smmu_ispcx, "smmu_ispcx", "aclk200", E4X12_GATE_ISP1, 4,
+                        CLK_IGNORE_UNUSED, 0),
+        GATE(spi0_isp, "spi0_isp", "aclk200", E4X12_GATE_ISP1, 12,
+                        CLK_IGNORE_UNUSED, 0),
+        GATE(spi1_isp, "spi1_isp", "aclk200", E4X12_GATE_ISP1, 13,
+                        CLK_IGNORE_UNUSED, 0),
+};
+
+#ifdef CONFIG_OF
+static struct of_device_id exynos4_clk_ids[] __initdata = {
+        { .compatible = "samsung,exynos4210-clock",
+                        .data = (void *)EXYNOS4210, },
+        { .compatible = "samsung,exynos4412-clock",
+                        .data = (void *)EXYNOS4X12, },
+        { },
+};
+#endif
+
+/*
+ * The parent of the fin_pll clock is selected by the XOM[0] bit. This bit
+ * resides in chipid register space, outside of the clock controller memory
+ * mapped space. So to determine the parent of fin_pll clock, the chipid
+ * controller is first remapped and the value of XOM[0] bit is read to
+ * determine the parent clock.
+ */
+static void __init exynos4_clk_register_finpll(void)
+{
+        struct samsung_fixed_rate_clock fclk;
+        struct device_node *np;
+        struct clk *clk;
+        void __iomem *chipid_base = S5P_VA_CHIPID;
+        unsigned long xom, finpll_f = 24000000;
+        char *parent_name;
+
+        np = of_find_compatible_node(NULL, NULL, "samsung,exynos4210-chipid");
+        if (np)
+                chipid_base = of_iomap(np, 0);
+
+        if (chipid_base) {
+                xom = readl(chipid_base + 8);
+                parent_name = xom & 1 ? "xusbxti" : "xxti";
+                clk = clk_get(NULL, parent_name);
+                if (IS_ERR(clk)) {
+                        pr_err("%s: failed to lookup parent clock %s, assuming "
+                                "fin_pll clock frequency is 24MHz\n", __func__,
+                                parent_name);
+                } else {
+                        finpll_f = clk_get_rate(clk);
+                }
+        } else {
+                pr_err("%s: failed to map chipid registers, assuming "
+                        "fin_pll clock frequency is 24MHz\n", __func__);
+        }
+
+        fclk.id = fin_pll;
+        fclk.name = "fin_pll";
+        fclk.parent_name = NULL;
+        fclk.flags = CLK_IS_ROOT;
+        fclk.fixed_rate = finpll_f;
+        samsung_clk_register_fixed_rate(&fclk, 1);
+
+        if (np)
+                iounmap(chipid_base);
+}
+
+/*
+ * This function allows non-dt platforms to specify the clock speed of the
+ * xxti and xusbxti clocks. These clocks are then registered with the specified
+ * clock speed.
+ */
+void __init exynos4_clk_register_fixed_ext(unsigned long xxti_f,
+                                                unsigned long xusbxti_f)
+{
+        exynos4_fixed_rate_ext_clks[0].fixed_rate = xxti_f;
+        exynos4_fixed_rate_ext_clks[1].fixed_rate = xusbxti_f;
+        samsung_clk_register_fixed_rate(exynos4_fixed_rate_ext_clks,
+                        ARRAY_SIZE(exynos4_fixed_rate_ext_clks));
+}
+
+static __initdata struct of_device_id ext_clk_match[] = {
+        { .compatible = "samsung,clock-xxti", .data = (void *)0, },
+        { .compatible = "samsung,clock-xusbxti", .data = (void *)1, },
+        {},
+};
+
+/* register exynos4 clocks */
+void __init exynos4_clk_init(struct device_node *np)
+{
+        void __iomem *reg_base;
+        struct clk *apll, *mpll, *epll, *vpll;
+        u32 exynos4_soc;
+
+        if (np) {
+                const struct of_device_id *match;
+                match = of_match_node(exynos4_clk_ids, np);
+                exynos4_soc = (u32)match->data;
+
+                reg_base = of_iomap(np, 0);
+                if (!reg_base)
+                        panic("%s: failed to map registers\n", __func__);
+        } else {
+                reg_base = S5P_VA_CMU;
+                if (soc_is_exynos4210())
+                        exynos4_soc = EXYNOS4210;
+                else if (soc_is_exynos4212() || soc_is_exynos4412())
+                        exynos4_soc = EXYNOS4X12;
+                else
+                        panic("%s: unable to determine soc\n", __func__);
+        }
+
+        if (exynos4_soc == EXYNOS4210)
+                samsung_clk_init(np, reg_base, nr_clks,
+                        exynos4_clk_regs, ARRAY_SIZE(exynos4_clk_regs),
+                        exynos4210_clk_save, ARRAY_SIZE(exynos4210_clk_save));
+        else
+                samsung_clk_init(np, reg_base, nr_clks,
+                        exynos4_clk_regs, ARRAY_SIZE(exynos4_clk_regs),
+                        exynos4x12_clk_save, ARRAY_SIZE(exynos4x12_clk_save));
+
+        if (np)
+                samsung_clk_of_register_fixed_ext(exynos4_fixed_rate_ext_clks,
+                        ARRAY_SIZE(exynos4_fixed_rate_ext_clks),
+                        ext_clk_match);
+
+        exynos4_clk_register_finpll();
+
+        if (exynos4_soc == EXYNOS4210) {
+                apll = samsung_clk_register_pll45xx("fout_apll", "fin_pll",
+                                        reg_base + APLL_CON0, pll_4508);
+                mpll = samsung_clk_register_pll45xx("fout_mpll", "fin_pll",
+                                        reg_base + E4210_MPLL_CON0, pll_4508);
+                epll = samsung_clk_register_pll46xx("fout_epll", "fin_pll",
+                                        reg_base + EPLL_CON0, pll_4600);
+                vpll = samsung_clk_register_pll46xx("fout_vpll", "mout_vpllsrc",
+                                        reg_base + VPLL_CON0, pll_4650c);
+        } else {
+                apll = samsung_clk_register_pll35xx("fout_apll", "fin_pll",
+                                        reg_base + APLL_CON0);
+                mpll = samsung_clk_register_pll35xx("fout_mpll", "fin_pll",
+                                        reg_base + E4X12_MPLL_CON0);
+                epll = samsung_clk_register_pll36xx("fout_epll", "fin_pll",
+                                        reg_base + EPLL_CON0);
+                vpll = samsung_clk_register_pll36xx("fout_vpll", "fin_pll",
+                                        reg_base + VPLL_CON0);
+        }
+
+        samsung_clk_add_lookup(apll, fout_apll);
+        samsung_clk_add_lookup(mpll, fout_mpll);
+        samsung_clk_add_lookup(epll, fout_epll);
+        samsung_clk_add_lookup(vpll, fout_vpll);
+
+        samsung_clk_register_fixed_rate(exynos4_fixed_rate_clks,
+                        ARRAY_SIZE(exynos4_fixed_rate_clks));
+        samsung_clk_register_mux(exynos4_mux_clks,
+                        ARRAY_SIZE(exynos4_mux_clks));
+        samsung_clk_register_div(exynos4_div_clks,
+                        ARRAY_SIZE(exynos4_div_clks));
+        samsung_clk_register_gate(exynos4_gate_clks,
+                        ARRAY_SIZE(exynos4_gate_clks));
+
+        if (exynos4_soc == EXYNOS4210) {
+                samsung_clk_register_fixed_rate(exynos4210_fixed_rate_clks,
+                        ARRAY_SIZE(exynos4210_fixed_rate_clks));
+                samsung_clk_register_mux(exynos4210_mux_clks,
+                        ARRAY_SIZE(exynos4210_mux_clks));
+                samsung_clk_register_div(exynos4210_div_clks,
+                        ARRAY_SIZE(exynos4210_div_clks));
+                samsung_clk_register_gate(exynos4210_gate_clks,
+                        ARRAY_SIZE(exynos4210_gate_clks));
+        } else {
+                samsung_clk_register_mux(exynos4x12_mux_clks,
+                        ARRAY_SIZE(exynos4x12_mux_clks));
+                samsung_clk_register_div(exynos4x12_div_clks,
+                        ARRAY_SIZE(exynos4x12_div_clks));
+                samsung_clk_register_gate(exynos4x12_gate_clks,
+                        ARRAY_SIZE(exynos4x12_gate_clks));
+        }
+
+        pr_info("%s clocks: sclk_apll = %ld, sclk_mpll = %ld\n"
+                "\tsclk_epll = %ld, sclk_vpll = %ld, arm_clk = %ld\n",
+                exynos4_soc == EXYNOS4210 ? "Exynos4210" : "Exynos4x12",
+                _get_rate("sclk_apll"), _get_rate("sclk_mpll"),
+                _get_rate("sclk_epll"), _get_rate("sclk_vpll"),
+                _get_rate("arm_clk"));
+}
+CLK_OF_DECLARE(exynos4210_clk, "samsung,exynos4210-clock", exynos4_clk_init);
+CLK_OF_DECLARE(exynos4412_clk, "samsung,exynos4412-clock", exynos4_clk_init);
diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
new file mode 100644
index 000000000000..7290faa518d2
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -0,0 +1,523 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2013 Linaro Ltd.
+ * Author: Thomas Abraham <thomas.ab@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for Exynos5250 SoC.
+*/
+
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+#include <plat/cpu.h>
+#include "clk.h"
+#include "clk-pll.h"
+
+#define SRC_CPU                 0x200
+#define DIV_CPU0                0x500
+#define SRC_CORE1               0x4204
+#define SRC_TOP0                0x10210
+#define SRC_TOP2                0x10218
+#define SRC_GSCL                0x10220
+#define SRC_DISP1_0             0x1022c
+#define SRC_MAU                 0x10240
+#define SRC_FSYS                0x10244
+#define SRC_GEN                 0x10248
+#define SRC_PERIC0              0x10250
+#define SRC_PERIC1              0x10254
+#define SRC_MASK_GSCL           0x10320
+#define SRC_MASK_DISP1_0        0x1032c
+#define SRC_MASK_MAU            0x10334
+#define SRC_MASK_FSYS           0x10340
+#define SRC_MASK_GEN            0x10344
+#define SRC_MASK_PERIC0         0x10350
+#define SRC_MASK_PERIC1         0x10354
+#define DIV_TOP0                0x10510
+#define DIV_TOP1                0x10514
+#define DIV_GSCL                0x10520
+#define DIV_DISP1_0             0x1052c
+#define DIV_GEN                 0x1053c
+#define DIV_MAU                 0x10544
+#define DIV_FSYS0               0x10548
+#define DIV_FSYS1               0x1054c
+#define DIV_FSYS2               0x10550
+#define DIV_PERIC0              0x10558
+#define DIV_PERIC1              0x1055c
+#define DIV_PERIC2              0x10560
+#define DIV_PERIC3              0x10564
+#define DIV_PERIC4              0x10568
+#define DIV_PERIC5              0x1056c
+#define GATE_IP_GSCL            0x10920
+#define GATE_IP_MFC             0x1092c
+#define GATE_IP_GEN             0x10934
+#define GATE_IP_FSYS            0x10944
+#define GATE_IP_PERIC           0x10950
+#define GATE_IP_PERIS           0x10960
+#define SRC_CDREX               0x20200
+#define PLL_DIV2_SEL            0x20a24
+#define GATE_IP_DISP1           0x10928
+
+/*
+ * Let each supported clock get a unique id. This id is used to lookup the clock
+ * for device tree based platforms. The clocks are categorized into three
+ * sections: core, sclk gate and bus interface gate clocks.
+ *
+ * When adding a new clock to this list, it is advised to choose a clock
+ * category and add it to the end of that category. That is because the the
+ * device tree source file is referring to these ids and any change in the
+ * sequence number of existing clocks will require corresponding change in the
+ * device tree files. This limitation would go away when pre-processor support
+ * for dtc would be available.
+ */
+enum exynos5250_clks {
+        none,
+
+        /* core clocks */
+        fin_pll,
+
+        /* gate for special clocks (sclk) */
+        sclk_cam_bayer = 128, sclk_cam0, sclk_cam1, sclk_gscl_wa, sclk_gscl_wb,
+        sclk_fimd1, sclk_mipi1, sclk_dp, sclk_hdmi, sclk_pixel, sclk_audio0,
+        sclk_mmc0, sclk_mmc1, sclk_mmc2, sclk_mmc3, sclk_sata, sclk_usb3,
+        sclk_jpeg, sclk_uart0, sclk_uart1, sclk_uart2, sclk_uart3, sclk_pwm,
+        sclk_audio1, sclk_audio2, sclk_spdif, sclk_spi0, sclk_spi1, sclk_spi2,
+
+        /* gate clocks */
+        gscl0 = 256, gscl1, gscl2, gscl3, gscl_wa, gscl_wb, smmu_gscl0,
+        smmu_gscl1, smmu_gscl2, smmu_gscl3, mfc, smmu_mfcl, smmu_mfcr, rotator,
+        jpeg, mdma1, smmu_rotator, smmu_jpeg, smmu_mdma1, pdma0, pdma1, sata,
+        usbotg, mipi_hsi, sdmmc0, sdmmc1, sdmmc2, sdmmc3, sromc, usb2, usb3,
+        sata_phyctrl, sata_phyi2c, uart0, uart1, uart2, uart3, uart4, i2c0,
+        i2c1, i2c2, i2c3, i2c4, i2c5, i2c6, i2c7, i2c_hdmi, adc, spi0, spi1,
+        spi2, i2s1, i2s2, pcm1, pcm2, pwm, spdif, ac97, hsi2c0, hsi2c1, hsi2c2,
+        hsi2c3, chipid, sysreg, pmu, cmu_top, cmu_core, cmu_mem, tzpc0, tzpc1,
+        tzpc2, tzpc3, tzpc4, tzpc5, tzpc6, tzpc7, tzpc8, tzpc9, hdmi_cec, mct,
+        wdt, rtc, tmu, fimd1, mie1, dsim0, dp, mixer, hdmi,
+
+        nr_clks,
+};
+
+/*
+ * list of controller registers to be saved and restored during a
+ * suspend/resume cycle.
+ */
+static __initdata unsigned long exynos5250_clk_regs[] = {
+        SRC_CPU,
+        DIV_CPU0,
+        SRC_CORE1,
+        SRC_TOP0,
+        SRC_TOP2,
+        SRC_GSCL,
+        SRC_DISP1_0,
+        SRC_MAU,
+        SRC_FSYS,
+        SRC_GEN,
+        SRC_PERIC0,
+        SRC_PERIC1,
+        SRC_MASK_GSCL,
+        SRC_MASK_DISP1_0,
+        SRC_MASK_MAU,
+        SRC_MASK_FSYS,
+        SRC_MASK_GEN,
+        SRC_MASK_PERIC0,
+        SRC_MASK_PERIC1,
+        DIV_TOP0,
+        DIV_TOP1,
+        DIV_GSCL,
+        DIV_DISP1_0,
+        DIV_GEN,
+        DIV_MAU,
+        DIV_FSYS0,
+        DIV_FSYS1,
+        DIV_FSYS2,
+        DIV_PERIC0,
+        DIV_PERIC1,
+        DIV_PERIC2,
+        DIV_PERIC3,
+        DIV_PERIC4,
+        DIV_PERIC5,
+        GATE_IP_GSCL,
+        GATE_IP_MFC,
+        GATE_IP_GEN,
+        GATE_IP_FSYS,
+        GATE_IP_PERIC,
+        GATE_IP_PERIS,
+        SRC_CDREX,
+        PLL_DIV2_SEL,
+        GATE_IP_DISP1,
+};
+
+/* list of all parent clock list */
+PNAME(mout_apll_p)      = { "fin_pll", "fout_apll", };
+PNAME(mout_cpu_p)       = { "mout_apll", "mout_mpll", };
+PNAME(mout_mpll_fout_p) = { "fout_mplldiv2", "fout_mpll" };
+PNAME(mout_mpll_p)      = { "fin_pll", "mout_mpll_fout" };
+PNAME(mout_bpll_fout_p) = { "fout_bplldiv2", "fout_bpll" };
+PNAME(mout_bpll_p)      = { "fin_pll", "mout_bpll_fout" };
+PNAME(mout_vpllsrc_p)   = { "fin_pll", "sclk_hdmi27m" };
+PNAME(mout_vpll_p)      = { "mout_vpllsrc", "fout_vpll" };
+PNAME(mout_cpll_p)      = { "fin_pll", "fout_cpll" };
+PNAME(mout_epll_p)      = { "fin_pll", "fout_epll" };
+PNAME(mout_mpll_user_p) = { "fin_pll", "sclk_mpll" };
+PNAME(mout_bpll_user_p) = { "fin_pll", "sclk_bpll" };
+PNAME(mout_aclk166_p)   = { "sclk_cpll", "sclk_mpll_user" };
+PNAME(mout_aclk200_p)   = { "sclk_mpll_user", "sclk_bpll_user" };
+PNAME(mout_hdmi_p)      = { "div_hdmi_pixel", "sclk_hdmiphy" };
+PNAME(mout_usb3_p)      = { "sclk_mpll_user", "sclk_cpll" };
+PNAME(mout_group1_p)    = { "fin_pll", "fin_pll", "sclk_hdmi27m",
+                                "sclk_dptxphy", "sclk_uhostphy", "sclk_hdmiphy",
+                                "sclk_mpll_user", "sclk_epll", "sclk_vpll",
+                                "sclk_cpll" };
+PNAME(mout_audio0_p)    = { "cdclk0", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy",
+                                "sclk_uhostphy", "sclk_hdmiphy",
+                                "sclk_mpll_user", "sclk_epll", "sclk_vpll",
+                                "sclk_cpll" };
+PNAME(mout_audio1_p)    = { "cdclk1", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy",
+                                "sclk_uhostphy", "sclk_hdmiphy",
+                                "sclk_mpll_user", "sclk_epll", "sclk_vpll",
+                                "sclk_cpll" };
+PNAME(mout_audio2_p)    = { "cdclk2", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy",
+                                "sclk_uhostphy", "sclk_hdmiphy",
+                                "sclk_mpll_user", "sclk_epll", "sclk_vpll",
+                                "sclk_cpll" };
+PNAME(mout_spdif_p)     = { "sclk_audio0", "sclk_audio1", "sclk_audio2",
+                                "spdif_extclk" };
+
+/* fixed rate clocks generated outside the soc */
+struct samsung_fixed_rate_clock exynos5250_fixed_rate_ext_clks[] __initdata = {
+        FRATE(fin_pll, "fin_pll", NULL, CLK_IS_ROOT, 0),
+};
+
+/* fixed rate clocks generated inside the soc */
+struct samsung_fixed_rate_clock exynos5250_fixed_rate_clks[] __initdata = {
+        FRATE(none, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000),
+        FRATE(none, "sclk_hdmi27m", NULL, CLK_IS_ROOT, 27000000),
+        FRATE(none, "sclk_dptxphy", NULL, CLK_IS_ROOT, 24000000),
+        FRATE(none, "sclk_uhostphy", NULL, CLK_IS_ROOT, 48000000),
+};
+
+struct samsung_fixed_factor_clock exynos5250_fixed_factor_clks[] __initdata = {
+        FFACTOR(none, "fout_mplldiv2", "fout_mpll", 1, 2, 0),
+        FFACTOR(none, "fout_bplldiv2", "fout_bpll", 1, 2, 0),
+};
+
+struct samsung_mux_clock exynos5250_mux_clks[] __initdata = {
+        MUX(none, "mout_apll", mout_apll_p, SRC_CPU, 0, 1),
+        MUX(none, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
+        MUX(none, "mout_mpll_fout", mout_mpll_fout_p, PLL_DIV2_SEL, 4, 1),
+        MUX(none, "sclk_mpll", mout_mpll_p, SRC_CORE1, 8, 1),
+        MUX(none, "mout_bpll_fout", mout_bpll_fout_p, PLL_DIV2_SEL, 0, 1),
+        MUX(none, "sclk_bpll", mout_bpll_p, SRC_CDREX, 0, 1),
+        MUX(none, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP2, 0, 1),
+        MUX(none, "sclk_vpll", mout_vpll_p, SRC_TOP2, 16, 1),
+        MUX(none, "sclk_epll", mout_epll_p, SRC_TOP2, 12, 1),
+        MUX(none, "sclk_cpll", mout_cpll_p, SRC_TOP2, 8, 1),
+        MUX(none, "sclk_mpll_user", mout_mpll_user_p, SRC_TOP2, 20, 1),
+        MUX(none, "sclk_bpll_user", mout_bpll_user_p, SRC_TOP2, 24, 1),
+        MUX(none, "mout_aclk166", mout_aclk166_p, SRC_TOP0, 8, 1),
+        MUX(none, "mout_aclk333", mout_aclk166_p, SRC_TOP0, 16, 1),
+        MUX(none, "mout_aclk200", mout_aclk200_p, SRC_TOP0, 12, 1),
+        MUX(none, "mout_cam_bayer", mout_group1_p, SRC_GSCL, 12, 4),
+        MUX(none, "mout_cam0", mout_group1_p, SRC_GSCL, 16, 4),
+        MUX(none, "mout_cam1", mout_group1_p, SRC_GSCL, 20, 4),
+        MUX(none, "mout_gscl_wa", mout_group1_p, SRC_GSCL, 24, 4),
+        MUX(none, "mout_gscl_wb", mout_group1_p, SRC_GSCL, 28, 4),
+        MUX(none, "mout_fimd1", mout_group1_p, SRC_DISP1_0, 0, 4),
+        MUX(none, "mout_mipi1", mout_group1_p, SRC_DISP1_0, 12, 4),
+        MUX(none, "mout_dp", mout_group1_p, SRC_DISP1_0, 16, 4),
+        MUX(none, "mout_hdmi", mout_hdmi_p, SRC_DISP1_0, 20, 1),
+        MUX(none, "mout_audio0", mout_audio0_p, SRC_MAU, 0, 4),
+        MUX(none, "mout_mmc0", mout_group1_p, SRC_FSYS, 0, 4),
+        MUX(none, "mout_mmc1", mout_group1_p, SRC_FSYS, 4, 4),
+        MUX(none, "mout_mmc2", mout_group1_p, SRC_FSYS, 8, 4),
+        MUX(none, "mout_mmc3", mout_group1_p, SRC_FSYS, 12, 4),
+        MUX(none, "mout_sata", mout_aclk200_p, SRC_FSYS, 24, 1),
+        MUX(none, "mout_usb3", mout_usb3_p, SRC_FSYS, 28, 1),
+        MUX(none, "mout_jpeg", mout_group1_p, SRC_GEN, 0, 4),
+        MUX(none, "mout_uart0", mout_group1_p, SRC_PERIC0, 0, 4),
+        MUX(none, "mout_uart1", mout_group1_p, SRC_PERIC0, 4, 4),
+        MUX(none, "mout_uart2", mout_group1_p, SRC_PERIC0, 8, 4),
+        MUX(none, "mout_uart3", mout_group1_p, SRC_PERIC0, 12, 4),
+        MUX(none, "mout_pwm", mout_group1_p, SRC_PERIC0, 24, 4),
+        MUX(none, "mout_audio1", mout_audio1_p, SRC_PERIC1, 0, 4),
+        MUX(none, "mout_audio2", mout_audio2_p, SRC_PERIC1, 4, 4),
+        MUX(none, "mout_spdif", mout_spdif_p, SRC_PERIC1, 8, 2),
+        MUX(none, "mout_spi0", mout_group1_p, SRC_PERIC1, 16, 4),
+        MUX(none, "mout_spi1", mout_group1_p, SRC_PERIC1, 20, 4),
+        MUX(none, "mout_spi2", mout_group1_p, SRC_PERIC1, 24, 4),
+};
+
+struct samsung_div_clock exynos5250_div_clks[] __initdata = {
+        DIV(none, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
+        DIV(none, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3),
+        DIV(none, "aclk66_pre", "sclk_mpll_user", DIV_TOP1, 24, 3),
+        DIV(none, "aclk66", "aclk66_pre", DIV_TOP0, 0, 3),
+        DIV(none, "aclk266", "sclk_mpll_user", DIV_TOP0, 16, 3),
+        DIV(none, "aclk166", "mout_aclk166", DIV_TOP0, 8, 3),
+        DIV(none, "aclk333", "mout_aclk333", DIV_TOP0, 20, 3),
+        DIV(none, "aclk200", "mout_aclk200", DIV_TOP0, 12, 3),
+        DIV(none, "div_cam_bayer", "mout_cam_bayer", DIV_GSCL, 12, 4),
+        DIV(none, "div_cam0", "mout_cam0", DIV_GSCL, 16, 4),
+        DIV(none, "div_cam1", "mout_cam1", DIV_GSCL, 20, 4),
+        DIV(none, "div_gscl_wa", "mout_gscl_wa", DIV_GSCL, 24, 4),
+        DIV(none, "div_gscl_wb", "mout_gscl_wb", DIV_GSCL, 28, 4),
+        DIV(none, "div_fimd1", "mout_fimd1", DIV_DISP1_0, 0, 4),
+        DIV(none, "div_mipi1", "mout_mipi1", DIV_DISP1_0, 16, 4),
+        DIV(none, "div_dp", "mout_dp", DIV_DISP1_0, 24, 4),
+        DIV(none, "div_jpeg", "mout_jpeg", DIV_GEN, 4, 4),
+        DIV(none, "div_audio0", "mout_audio0", DIV_MAU, 0, 4),
+        DIV(none, "div_pcm0", "sclk_audio0", DIV_MAU, 4, 8),
+        DIV(none, "div_sata", "mout_sata", DIV_FSYS0, 20, 4),
+        DIV(none, "div_usb3", "mout_usb3", DIV_FSYS0, 24, 4),
+        DIV(none, "div_mmc0", "mout_mmc0", DIV_FSYS1, 8, 8),
+        DIV(none, "div_mmc1", "mout_mmc1", DIV_FSYS1, 24, 8),
+        DIV(none, "div_mmc2", "mout_mmc2", DIV_FSYS2, 8, 8),
+        DIV(none, "div_mmc3", "mout_mmc3", DIV_FSYS2, 24, 8),
+        DIV(none, "div_uart0", "mout_uart0", DIV_PERIC0, 0, 4),
+        DIV(none, "div_uart1", "mout_uart1", DIV_PERIC0, 4, 4),
+        DIV(none, "div_uart2", "mout_uart2", DIV_PERIC0, 8, 4),
+        DIV(none, "div_uart3", "mout_uart3", DIV_PERIC0, 12, 4),
+        DIV(none, "div_spi0", "mout_spi0", DIV_PERIC1, 0, 4),
+        DIV(none, "div_spi1", "mout_spi1", DIV_PERIC1, 16, 4),
+        DIV(none, "div_spi2", "mout_spi2", DIV_PERIC2, 0, 4),
+        DIV(none, "div_pwm", "mout_pwm", DIV_PERIC3, 0, 4),
+        DIV(none, "div_audio1", "mout_audio1", DIV_PERIC4, 0, 4),
+        DIV(none, "div_pcm1", "sclk_audio1", DIV_PERIC4, 4, 8),
+        DIV(none, "div_audio2", "mout_audio2", DIV_PERIC4, 16, 4),
+        DIV(none, "div_pcm2", "sclk_audio2", DIV_PERIC4, 20, 8),
+        DIV(none, "div_i2s1", "sclk_audio1", DIV_PERIC5, 0, 6),
+        DIV(none, "div_i2s2", "sclk_audio2", DIV_PERIC5, 8, 6),
+        DIV(sclk_pixel, "div_hdmi_pixel", "sclk_vpll", DIV_DISP1_0, 28, 4),
+        DIV_A(none, "armclk", "div_arm", DIV_CPU0, 28, 3, "armclk"),
+        DIV_F(none, "div_mipi1_pre", "div_mipi1",
+                        DIV_DISP1_0, 20, 4, CLK_SET_RATE_PARENT, 0),
+        DIV_F(none, "div_mmc_pre0", "div_mmc0",
+                        DIV_FSYS1, 8, 8, CLK_SET_RATE_PARENT, 0),
+        DIV_F(none, "div_mmc_pre1", "div_mmc1",
+                        DIV_FSYS1, 24, 8, CLK_SET_RATE_PARENT, 0),
+        DIV_F(none, "div_mmc_pre2", "div_mmc2",
+                        DIV_FSYS2, 8, 8, CLK_SET_RATE_PARENT, 0),
+        DIV_F(none, "div_mmc_pre3", "div_mmc3",
+                        DIV_FSYS2, 24, 8, CLK_SET_RATE_PARENT, 0),
+        DIV_F(none, "div_spi_pre0", "div_spi0",
+                        DIV_PERIC1, 8, 8, CLK_SET_RATE_PARENT, 0),
+        DIV_F(none, "div_spi_pre1", "div_spi1",
+                        DIV_PERIC1, 24, 8, CLK_SET_RATE_PARENT, 0),
+        DIV_F(none, "div_spi_pre2", "div_spi2",
+                        DIV_PERIC2, 8, 8, CLK_SET_RATE_PARENT, 0),
+};
+
+struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {
+        GATE(gscl0, "gscl0", "none", GATE_IP_GSCL, 0, 0, 0),
+        GATE(gscl1, "gscl1", "none", GATE_IP_GSCL, 1, 0, 0),
+        GATE(gscl2, "gscl2", "aclk266", GATE_IP_GSCL, 2, 0, 0),
+        GATE(gscl3, "gscl3", "aclk266", GATE_IP_GSCL, 3, 0, 0),
+        GATE(gscl_wa, "gscl_wa", "div_gscl_wa", GATE_IP_GSCL, 5, 0, 0),
+        GATE(gscl_wb, "gscl_wb", "div_gscl_wb", GATE_IP_GSCL, 6, 0, 0),
+        GATE(smmu_gscl0, "smmu_gscl0", "aclk266", GATE_IP_GSCL, 7, 0, 0),
+        GATE(smmu_gscl1, "smmu_gscl1", "aclk266", GATE_IP_GSCL, 8, 0, 0),
+        GATE(smmu_gscl2, "smmu_gscl2", "aclk266", GATE_IP_GSCL, 9, 0, 0),
+        GATE(smmu_gscl3, "smmu_gscl3", "aclk266", GATE_IP_GSCL, 10, 0, 0),
+        GATE(mfc, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0),
+        GATE(smmu_mfcl, "smmu_mfcl", "aclk333", GATE_IP_MFC, 1, 0, 0),
+        GATE(smmu_mfcr, "smmu_mfcr", "aclk333", GATE_IP_MFC, 2, 0, 0),
+        GATE(rotator, "rotator", "aclk266", GATE_IP_GEN, 1, 0, 0),
+        GATE(jpeg, "jpeg", "aclk166", GATE_IP_GEN, 2, 0, 0),
+        GATE(mdma1, "mdma1", "aclk266", GATE_IP_GEN, 4, 0, 0),
+        GATE(smmu_rotator, "smmu_rotator", "aclk266", GATE_IP_GEN, 6, 0, 0),
+        GATE(smmu_jpeg, "smmu_jpeg", "aclk166", GATE_IP_GEN, 7, 0, 0),
+        GATE(smmu_mdma1, "smmu_mdma1", "aclk266", GATE_IP_GEN, 9, 0, 0),
+        GATE(pdma0, "pdma0", "aclk200", GATE_IP_FSYS, 1, 0, 0),
+        GATE(pdma1, "pdma1", "aclk200", GATE_IP_FSYS, 2, 0, 0),
+        GATE(sata, "sata", "aclk200", GATE_IP_FSYS, 6, 0, 0),
+        GATE(usbotg, "usbotg", "aclk200", GATE_IP_FSYS, 7, 0, 0),
+        GATE(mipi_hsi, "mipi_hsi", "aclk200", GATE_IP_FSYS, 8, 0, 0),
+        GATE(sdmmc0, "sdmmc0", "aclk200", GATE_IP_FSYS, 12, 0, 0),
+        GATE(sdmmc1, "sdmmc1", "aclk200", GATE_IP_FSYS, 13, 0, 0),
+        GATE(sdmmc2, "sdmmc2", "aclk200", GATE_IP_FSYS, 14, 0, 0),
+        GATE(sdmmc3, "sdmmc3", "aclk200", GATE_IP_FSYS, 15, 0, 0),
+        GATE(sromc, "sromc", "aclk200", GATE_IP_FSYS, 17, 0, 0),
+        GATE(usb2, "usb2", "aclk200", GATE_IP_FSYS, 18, 0, 0),
+        GATE(usb3, "usb3", "aclk200", GATE_IP_FSYS, 19, 0, 0),
+        GATE(sata_phyctrl, "sata_phyctrl", "aclk200", GATE_IP_FSYS, 24, 0, 0),
+        GATE(sata_phyi2c, "sata_phyi2c", "aclk200", GATE_IP_FSYS, 25, 0, 0),
+        GATE(uart0, "uart0", "aclk66", GATE_IP_PERIC, 0, 0, 0),
+        GATE(uart1, "uart1", "aclk66", GATE_IP_PERIC, 1, 0, 0),
+        GATE(uart2, "uart2", "aclk66", GATE_IP_PERIC, 2, 0, 0),
+        GATE(uart3, "uart3", "aclk66", GATE_IP_PERIC, 3, 0, 0),
+        GATE(uart4, "uart4", "aclk66", GATE_IP_PERIC, 4, 0, 0),
+        GATE(i2c0, "i2c0", "aclk66", GATE_IP_PERIC, 6, 0, 0),
+        GATE(i2c1, "i2c1", "aclk66", GATE_IP_PERIC, 7, 0, 0),
+        GATE(i2c2, "i2c2", "aclk66", GATE_IP_PERIC, 8, 0, 0),
+        GATE(i2c3, "i2c3", "aclk66", GATE_IP_PERIC, 9, 0, 0),
+        GATE(i2c4, "i2c4", "aclk66", GATE_IP_PERIC, 10, 0, 0),
+        GATE(i2c5, "i2c5", "aclk66", GATE_IP_PERIC, 11, 0, 0),
+        GATE(i2c6, "i2c6", "aclk66", GATE_IP_PERIC, 12, 0, 0),
+        GATE(i2c7, "i2c7", "aclk66", GATE_IP_PERIC, 13, 0, 0),
+        GATE(i2c_hdmi, "i2c_hdmi", "aclk66", GATE_IP_PERIC, 14, 0, 0),
+        GATE(adc, "adc", "aclk66", GATE_IP_PERIC, 15, 0, 0),
+        GATE(spi0, "spi0", "aclk66", GATE_IP_PERIC, 16, 0, 0),
+        GATE(spi1, "spi1", "aclk66", GATE_IP_PERIC, 17, 0, 0),
+        GATE(spi2, "spi2", "aclk66", GATE_IP_PERIC, 18, 0, 0),
+        GATE(i2s1, "i2s1", "aclk66", GATE_IP_PERIC, 20, 0, 0),
+        GATE(i2s2, "i2s2", "aclk66", GATE_IP_PERIC, 21, 0, 0),
+        GATE(pcm1, "pcm1", "aclk66", GATE_IP_PERIC, 22, 0, 0),
+        GATE(pcm2, "pcm2", "aclk66", GATE_IP_PERIC, 23, 0, 0),
+        GATE(pwm, "pwm", "aclk66", GATE_IP_PERIC, 24, 0, 0),
+        GATE(spdif, "spdif", "aclk66", GATE_IP_PERIC, 26, 0, 0),
+        GATE(ac97, "ac97", "aclk66", GATE_IP_PERIC, 27, 0, 0),
+        GATE(hsi2c0, "hsi2c0", "aclk66", GATE_IP_PERIC, 28, 0, 0),
+        GATE(hsi2c1, "hsi2c1", "aclk66", GATE_IP_PERIC, 29, 0, 0),
+        GATE(hsi2c2, "hsi2c2", "aclk66", GATE_IP_PERIC, 30, 0, 0),
+        GATE(hsi2c3, "hsi2c3", "aclk66", GATE_IP_PERIC, 31, 0, 0),
+        GATE(chipid, "chipid", "aclk66", GATE_IP_PERIS, 0, 0, 0),
+        GATE(sysreg, "sysreg", "aclk66", GATE_IP_PERIS, 1, 0, 0),
+        GATE(pmu, "pmu", "aclk66", GATE_IP_PERIS, 2, 0, 0),
+        GATE(tzpc0, "tzpc0", "aclk66", GATE_IP_PERIS, 6, 0, 0),
+        GATE(tzpc1, "tzpc1", "aclk66", GATE_IP_PERIS, 7, 0, 0),
+        GATE(tzpc2, "tzpc2", "aclk66", GATE_IP_PERIS, 8, 0, 0),
+        GATE(tzpc3, "tzpc3", "aclk66", GATE_IP_PERIS, 9, 0, 0),
+        GATE(tzpc4, "tzpc4", "aclk66", GATE_IP_PERIS, 10, 0, 0),
+        GATE(tzpc5, "tzpc5", "aclk66", GATE_IP_PERIS, 11, 0, 0),
+        GATE(tzpc6, "tzpc6", "aclk66", GATE_IP_PERIS, 12, 0, 0),
+        GATE(tzpc7, "tzpc7", "aclk66", GATE_IP_PERIS, 13, 0, 0),
+        GATE(tzpc8, "tzpc8", "aclk66", GATE_IP_PERIS, 14, 0, 0),
+        GATE(tzpc9, "tzpc9", "aclk66", GATE_IP_PERIS, 15, 0, 0),
+        GATE(hdmi_cec, "hdmi_cec", "aclk66", GATE_IP_PERIS, 16, 0, 0),
+        GATE(mct, "mct", "aclk66", GATE_IP_PERIS, 18, 0, 0),
+        GATE(wdt, "wdt", "aclk66", GATE_IP_PERIS, 19, 0, 0),
+        GATE(rtc, "rtc", "aclk66", GATE_IP_PERIS, 20, 0, 0),
+        GATE(tmu, "tmu", "aclk66", GATE_IP_PERIS, 21, 0, 0),
+        GATE(cmu_top, "cmu_top", "aclk66",
+                        GATE_IP_PERIS, 3, CLK_IGNORE_UNUSED, 0),
+        GATE(cmu_core, "cmu_core", "aclk66",
+                        GATE_IP_PERIS, 4, CLK_IGNORE_UNUSED, 0),
+        GATE(cmu_mem, "cmu_mem", "aclk66",
+                        GATE_IP_PERIS, 5, CLK_IGNORE_UNUSED, 0),
+        GATE(sclk_cam_bayer, "sclk_cam_bayer", "div_cam_bayer",
+                        SRC_MASK_GSCL, 12, CLK_SET_RATE_PARENT, 0),
+        GATE(sclk_cam0, "sclk_cam0", "div_cam0",
+                        SRC_MASK_GSCL, 16, CLK_SET_RATE_PARENT, 0),
+        GATE(sclk_cam1, "sclk_cam1", "div_cam1",
+                        SRC_MASK_GSCL, 20, CLK_SET_RATE_PARENT, 0),
+        GATE(sclk_gscl_wa, "sclk_gscl_wa", "div_gscl_wa",
+                        SRC_MASK_GSCL, 24, CLK_SET_RATE_PARENT, 0),
+        GATE(sclk_gscl_wb, "sclk_gscl_wb", "div_gscl_wb",
+                        SRC_MASK_GSCL, 28, CLK_SET_RATE_PARENT, 0),
+        GATE(sclk_fimd1, "sclk_fimd1", "div_fimd1",
+                        SRC_MASK_DISP1_0, 0, CLK_SET_RATE_PARENT, 0),
+        GATE(sclk_mipi1, "sclk_mipi1", "div_mipi1",
+                        SRC_MASK_DISP1_0, 12, CLK_SET_RATE_PARENT, 0),
+        GATE(sclk_dp, "sclk_dp", "div_dp",
+                        SRC_MASK_DISP1_0, 16, CLK_SET_RATE_PARENT, 0),
+        GATE(sclk_hdmi, "sclk_hdmi", "mout_hdmi",
+                        SRC_MASK_DISP1_0, 20, 0, 0),
+        GATE(sclk_audio0, "sclk_audio0", "div_audio0",
+                        SRC_MASK_MAU, 0, CLK_SET_RATE_PARENT, 0),
+        GATE(sclk_mmc0, "sclk_mmc0", "div_mmc0",
+                        SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
+        GATE(sclk_mmc1, "sclk_mmc1", "div_mmc1",
+                        SRC_MASK_FSYS, 4, CLK_SET_RATE_PARENT, 0),
+        GATE(sclk_mmc2, "sclk_mmc2", "div_mmc2",
+                        SRC_MASK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
+        GATE(sclk_mmc3, "sclk_mmc3", "div_mmc3",
+                        SRC_MASK_FSYS, 12, CLK_SET_RATE_PARENT, 0),
+        GATE(sclk_sata, "sclk_sata", "div_sata",
+                        SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
+        GATE(sclk_usb3, "sclk_usb3", "div_usb3",
+                        SRC_MASK_FSYS, 28, CLK_SET_RATE_PARENT, 0),
+        GATE(sclk_jpeg, "sclk_jpeg", "div_jpeg",
+                        SRC_MASK_GEN, 0, CLK_SET_RATE_PARENT, 0),
+        GATE(sclk_uart0, "sclk_uart0", "div_uart0",
+                        SRC_MASK_PERIC0, 0, CLK_SET_RATE_PARENT, 0),
+        GATE(sclk_uart1, "sclk_uart1", "div_uart1",
+                        SRC_MASK_PERIC0, 4, CLK_SET_RATE_PARENT, 0),
+        GATE(sclk_uart2, "sclk_uart2", "div_uart2",
+                        SRC_MASK_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
+        GATE(sclk_uart3, "sclk_uart3", "div_uart3",
+                        SRC_MASK_PERIC0, 12, CLK_SET_RATE_PARENT, 0),
+        GATE(sclk_pwm, "sclk_pwm", "div_pwm",
+                        SRC_MASK_PERIC0, 24, CLK_SET_RATE_PARENT, 0),
+        GATE(sclk_audio1, "sclk_audio1", "div_audio1",
+                        SRC_MASK_PERIC1, 0, CLK_SET_RATE_PARENT, 0),
+        GATE(sclk_audio2, "sclk_audio2", "div_audio2",
+                        SRC_MASK_PERIC1, 4, CLK_SET_RATE_PARENT, 0),
+        GATE(sclk_spdif, "sclk_spdif", "mout_spdif",
+                        SRC_MASK_PERIC1, 4, 0, 0),
+        GATE(sclk_spi0, "sclk_spi0", "div_spi_pre0",
+                        SRC_MASK_PERIC1, 16, CLK_SET_RATE_PARENT, 0),
+        GATE(sclk_spi1, "sclk_spi1", "div_spi_pre1",
+                        SRC_MASK_PERIC1, 20, CLK_SET_RATE_PARENT, 0),
+        GATE(sclk_spi2, "sclk_spi2", "div_spi_pre2",
+                        SRC_MASK_PERIC1, 24, CLK_SET_RATE_PARENT, 0),
+        GATE(fimd1, "fimd1", "aclk200", GATE_IP_DISP1, 0, 0, 0),
+        GATE(mie1, "mie1", "aclk200", GATE_IP_DISP1, 1, 0, 0),
+        GATE(dsim0, "dsim0", "aclk200", GATE_IP_DISP1, 3, 0, 0),
+        GATE(dp, "dp", "aclk200", GATE_IP_DISP1, 4, 0, 0),
+        GATE(mixer, "mixer", "aclk200", GATE_IP_DISP1, 5, 0, 0),
+        GATE(hdmi, "hdmi", "aclk200", GATE_IP_DISP1, 6, 0, 0),
+};
+
+static __initdata struct of_device_id ext_clk_match[] = {
+        { .compatible = "samsung,clock-xxti", .data = (void *)0, },
+        { },
+};
+
+/* register exynox5250 clocks */
+void __init exynos5250_clk_init(struct device_node *np)
+{
+        void __iomem *reg_base;
+        struct clk *apll, *mpll, *epll, *vpll, *bpll, *gpll, *cpll;
+
+        if (np) {
+                reg_base = of_iomap(np, 0);
+                if (!reg_base)
+                        panic("%s: failed to map registers\n", __func__);
+        } else {
+                panic("%s: unable to determine soc\n", __func__);
+        }
+
+        samsung_clk_init(np, reg_base, nr_clks,
+                        exynos5250_clk_regs, ARRAY_SIZE(exynos5250_clk_regs),
+                        NULL, 0);
+        samsung_clk_of_register_fixed_ext(exynos5250_fixed_rate_ext_clks,
+                        ARRAY_SIZE(exynos5250_fixed_rate_ext_clks),
+                        ext_clk_match);
+
+        apll = samsung_clk_register_pll35xx("fout_apll", "fin_pll",
+                        reg_base + 0x100);
+        mpll = samsung_clk_register_pll35xx("fout_mpll", "fin_pll",
+                        reg_base + 0x4100);
+        bpll = samsung_clk_register_pll35xx("fout_bpll", "fin_pll",
+                        reg_base + 0x20110);
+        gpll = samsung_clk_register_pll35xx("fout_gpll", "fin_pll",
+                        reg_base + 0x10150);
+        cpll = samsung_clk_register_pll35xx("fout_cpll", "fin_pll",
+                        reg_base + 0x10120);
+        epll = samsung_clk_register_pll36xx("fout_epll", "fin_pll",
+                        reg_base + 0x10130);
+        vpll = samsung_clk_register_pll36xx("fout_vpll", "mout_vpllsrc",
+                        reg_base + 0x10140);
+
+        samsung_clk_register_fixed_rate(exynos5250_fixed_rate_clks,
+                        ARRAY_SIZE(exynos5250_fixed_rate_clks));
+        samsung_clk_register_fixed_factor(exynos5250_fixed_factor_clks,
+                        ARRAY_SIZE(exynos5250_fixed_factor_clks));
+        samsung_clk_register_mux(exynos5250_mux_clks,
+                        ARRAY_SIZE(exynos5250_mux_clks));
+        samsung_clk_register_div(exynos5250_div_clks,
+                        ARRAY_SIZE(exynos5250_div_clks));
+        samsung_clk_register_gate(exynos5250_gate_clks,
+                        ARRAY_SIZE(exynos5250_gate_clks));
+
+        pr_info("Exynos5250: clock setup completed, armclk=%ld\n",
+                        _get_rate("armclk"));
+}
+CLK_OF_DECLARE(exynos5250_clk, "samsung,exynos5250-clock", exynos5250_clk_init);
diff --git a/drivers/clk/samsung/clk-exynos5440.c b/drivers/clk/samsung/clk-exynos5440.c
new file mode 100644
index 000000000000..a0a094c06f19
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos5440.c
@@ -0,0 +1,139 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Author: Thomas Abraham <thomas.ab@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for Exynos5440 SoC.
+*/
+
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+#include <plat/cpu.h>
+#include "clk.h"
+#include "clk-pll.h"
+
+#define CLKEN_OV_VAL            0xf8
+#define CPU_CLK_STATUS          0xfc
+#define MISC_DOUT1              0x558
+
+/*
+ * Let each supported clock get a unique id. This id is used to lookup the clock
+ * for device tree based platforms.
+ */
+enum exynos5440_clks {
+        none, xtal, arm_clk,
+
+        spi_baud = 16, pb0_250, pr0_250, pr1_250, b_250, b_125, b_200, sata,
+        usb, gmac0, cs250, pb0_250_o, pr0_250_o, pr1_250_o, b_250_o, b_125_o,
+        b_200_o, sata_o, usb_o, gmac0_o, cs250_o,
+
+        nr_clks,
+};
+
+/* parent clock name list */
+PNAME(mout_armclk_p)    = { "cplla", "cpllb" };
+PNAME(mout_spi_p)       = { "div125", "div200" };
+
+/* fixed rate clocks generated outside the soc */
+struct samsung_fixed_rate_clock exynos5440_fixed_rate_ext_clks[] __initdata = {
+        FRATE(none, "xtal", NULL, CLK_IS_ROOT, 0),
+};
+
+/* fixed rate clocks */
+struct samsung_fixed_rate_clock exynos5440_fixed_rate_clks[] __initdata = {
+        FRATE(none, "ppll", NULL, CLK_IS_ROOT, 1000000000),
+        FRATE(none, "usb_phy0", NULL, CLK_IS_ROOT, 60000000),
+        FRATE(none, "usb_phy1", NULL, CLK_IS_ROOT, 60000000),
+        FRATE(none, "usb_ohci12", NULL, CLK_IS_ROOT, 12000000),
+        FRATE(none, "usb_ohci48", NULL, CLK_IS_ROOT, 48000000),
+};
+
+/* fixed factor clocks */
+struct samsung_fixed_factor_clock exynos5440_fixed_factor_clks[] __initdata = {
+        FFACTOR(none, "div250", "ppll", 1, 4, 0),
+        FFACTOR(none, "div200", "ppll", 1, 5, 0),
+        FFACTOR(none, "div125", "div250", 1, 2, 0),
+};
+
+/* mux clocks */
+struct samsung_mux_clock exynos5440_mux_clks[] __initdata = {
+        MUX(none, "mout_spi", mout_spi_p, MISC_DOUT1, 5, 1),
+        MUX_A(arm_clk, "arm_clk", mout_armclk_p,
+                        CPU_CLK_STATUS, 0, 1, "armclk"),
+};
+
+/* divider clocks */
+struct samsung_div_clock exynos5440_div_clks[] __initdata = {
+        DIV(spi_baud, "div_spi", "mout_spi", MISC_DOUT1, 3, 2),
+};
+
+/* gate clocks */
+struct samsung_gate_clock exynos5440_gate_clks[] __initdata = {
+        GATE(pb0_250, "pb0_250", "div250", CLKEN_OV_VAL, 3, 0, 0),
+        GATE(pr0_250, "pr0_250", "div250", CLKEN_OV_VAL, 4, 0, 0),
+        GATE(pr1_250, "pr1_250", "div250", CLKEN_OV_VAL, 5, 0, 0),
+        GATE(b_250, "b_250", "div250", CLKEN_OV_VAL, 9, 0, 0),
+        GATE(b_125, "b_125", "div125", CLKEN_OV_VAL, 10, 0, 0),
+        GATE(b_200, "b_200", "div200", CLKEN_OV_VAL, 11, 0, 0),
+        GATE(sata, "sata", "div200", CLKEN_OV_VAL, 12, 0, 0),
+        GATE(usb, "usb", "div200", CLKEN_OV_VAL, 13, 0, 0),
+        GATE(gmac0, "gmac0", "div200", CLKEN_OV_VAL, 14, 0, 0),
+        GATE(cs250, "cs250", "div250", CLKEN_OV_VAL, 19, 0, 0),
+        GATE(pb0_250_o, "pb0_250_o", "pb0_250", CLKEN_OV_VAL, 3, 0, 0),
+        GATE(pr0_250_o, "pr0_250_o", "pr0_250", CLKEN_OV_VAL, 4, 0, 0),
+        GATE(pr1_250_o, "pr1_250_o", "pr1_250", CLKEN_OV_VAL, 5, 0, 0),
+        GATE(b_250_o, "b_250_o", "b_250", CLKEN_OV_VAL, 9, 0, 0),
+        GATE(b_125_o, "b_125_o", "b_125", CLKEN_OV_VAL, 10, 0, 0),
+        GATE(b_200_o, "b_200_o", "b_200", CLKEN_OV_VAL, 11, 0, 0),
+        GATE(sata_o, "sata_o", "sata", CLKEN_OV_VAL, 12, 0, 0),
+        GATE(usb_o, "usb_o", "usb", CLKEN_OV_VAL, 13, 0, 0),
+        GATE(gmac0_o, "gmac0_o", "gmac", CLKEN_OV_VAL, 14, 0, 0),
+        GATE(cs250_o, "cs250_o", "cs250", CLKEN_OV_VAL, 19, 0, 0),
+};
+
+static __initdata struct of_device_id ext_clk_match[] = {
+        { .compatible = "samsung,clock-xtal", .data = (void *)0, },
+        {},
+};
+
+/* register exynos5440 clocks */
+void __init exynos5440_clk_init(struct device_node *np)
+{
+        void __iomem *reg_base;
+
+        reg_base = of_iomap(np, 0);
+        if (!reg_base) {
+                pr_err("%s: failed to map clock controller registers,"
+                        " aborting clock initialization\n", __func__);
+                return;
+        }
+
+        samsung_clk_init(np, reg_base, nr_clks, NULL, 0, NULL, 0);
+        samsung_clk_of_register_fixed_ext(exynos5440_fixed_rate_ext_clks,
+                ARRAY_SIZE(exynos5440_fixed_rate_ext_clks), ext_clk_match);
+
+        samsung_clk_register_pll2550x("cplla", "xtal", reg_base + 0x1c, 0x10);
+        samsung_clk_register_pll2550x("cpllb", "xtal", reg_base + 0x20, 0x10);
+
+        samsung_clk_register_fixed_rate(exynos5440_fixed_rate_clks,
+                        ARRAY_SIZE(exynos5440_fixed_rate_clks));
+        samsung_clk_register_fixed_factor(exynos5440_fixed_factor_clks,
+                        ARRAY_SIZE(exynos5440_fixed_factor_clks));
+        samsung_clk_register_mux(exynos5440_mux_clks,
+                        ARRAY_SIZE(exynos5440_mux_clks));
+        samsung_clk_register_div(exynos5440_div_clks,
+                        ARRAY_SIZE(exynos5440_div_clks));
+        samsung_clk_register_gate(exynos5440_gate_clks,
+                        ARRAY_SIZE(exynos5440_gate_clks));
+
+        pr_info("Exynos5440: arm_clk = %ldHz\n", _get_rate("armclk"));
+        pr_info("exynos5440 clock initialization complete\n");
+}
+CLK_OF_DECLARE(exynos5440_clk, "samsung,exynos5440-clock", exynos5440_clk_init);
diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
new file mode 100644
index 000000000000..89135f6be116
--- /dev/null
+++ b/drivers/clk/samsung/clk-pll.c
@@ -0,0 +1,419 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2013 Linaro Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This file contains the utility functions to register the pll clocks.
+*/
+
+#include <linux/errno.h>
+#include "clk.h"
+#include "clk-pll.h"
+
+/*
+ * PLL35xx Clock Type
+ */
+
+#define PLL35XX_MDIV_MASK       (0x3FF)
+#define PLL35XX_PDIV_MASK       (0x3F)
+#define PLL35XX_SDIV_MASK       (0x7)
+#define PLL35XX_MDIV_SHIFT      (16)
+#define PLL35XX_PDIV_SHIFT      (8)
+#define PLL35XX_SDIV_SHIFT      (0)
+
+struct samsung_clk_pll35xx {
+        struct clk_hw           hw;
+        const void __iomem      *con_reg;
+};
+
+#define to_clk_pll35xx(_hw) container_of(_hw, struct samsung_clk_pll35xx, hw)
+
+static unsigned long samsung_pll35xx_recalc_rate(struct clk_hw *hw,
+                                unsigned long parent_rate)
+{
+        struct samsung_clk_pll35xx *pll = to_clk_pll35xx(hw);
+        u32 mdiv, pdiv, sdiv, pll_con;
+        u64 fvco = parent_rate;
+
+        pll_con = __raw_readl(pll->con_reg);
+        mdiv = (pll_con >> PLL35XX_MDIV_SHIFT) & PLL35XX_MDIV_MASK;
+        pdiv = (pll_con >> PLL35XX_PDIV_SHIFT) & PLL35XX_PDIV_MASK;
+        sdiv = (pll_con >> PLL35XX_SDIV_SHIFT) & PLL35XX_SDIV_MASK;
+
+        fvco *= mdiv;
+        do_div(fvco, (pdiv << sdiv));
+
+        return (unsigned long)fvco;
+}
+
+static const struct clk_ops samsung_pll35xx_clk_ops = {
+        .recalc_rate = samsung_pll35xx_recalc_rate,
+};
+
+struct clk * __init samsung_clk_register_pll35xx(const char *name,
+                        const char *pname, const void __iomem *con_reg)
+{
+        struct samsung_clk_pll35xx *pll;
+        struct clk *clk;
+        struct clk_init_data init;
+
+        pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+        if (!pll) {
+                pr_err("%s: could not allocate pll clk %s\n", __func__, name);
+                return NULL;
+        }
+
+        init.name = name;
+        init.ops = &samsung_pll35xx_clk_ops;
+        init.flags = CLK_GET_RATE_NOCACHE;
+        init.parent_names = &pname;
+        init.num_parents = 1;
+
+        pll->hw.init = &init;
+        pll->con_reg = con_reg;
+
+        clk = clk_register(NULL, &pll->hw);
+        if (IS_ERR(clk)) {
+                pr_err("%s: failed to register pll clock %s\n", __func__,
+                                name);
+                kfree(pll);
+        }
+
+        if (clk_register_clkdev(clk, name, NULL))
+                pr_err("%s: failed to register lookup for %s", __func__, name);
+
+        return clk;
+}
+
+/*
+ * PLL36xx Clock Type
+ */
+
+#define PLL36XX_KDIV_MASK       (0xFFFF)
+#define PLL36XX_MDIV_MASK       (0x1FF)
+#define PLL36XX_PDIV_MASK       (0x3F)
+#define PLL36XX_SDIV_MASK       (0x7)
+#define PLL36XX_MDIV_SHIFT      (16)
+#define PLL36XX_PDIV_SHIFT      (8)
+#define PLL36XX_SDIV_SHIFT      (0)
+
+struct samsung_clk_pll36xx {
+        struct clk_hw           hw;
+        const void __iomem      *con_reg;
+};
+
+#define to_clk_pll36xx(_hw) container_of(_hw, struct samsung_clk_pll36xx, hw)
+
+static unsigned long samsung_pll36xx_recalc_rate(struct clk_hw *hw,
+                                unsigned long parent_rate)
+{
+        struct samsung_clk_pll36xx *pll = to_clk_pll36xx(hw);
+        u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1;
+        u64 fvco = parent_rate;
+
+        pll_con0 = __raw_readl(pll->con_reg);
+        pll_con1 = __raw_readl(pll->con_reg + 4);
+        mdiv = (pll_con0 >> PLL36XX_MDIV_SHIFT) & PLL36XX_MDIV_MASK;
+        pdiv = (pll_con0 >> PLL36XX_PDIV_SHIFT) & PLL36XX_PDIV_MASK;
+        sdiv = (pll_con0 >> PLL36XX_SDIV_SHIFT) & PLL36XX_SDIV_MASK;
+        kdiv = pll_con1 & PLL36XX_KDIV_MASK;
+
+        fvco *= (mdiv << 16) + kdiv;
+        do_div(fvco, (pdiv << sdiv));
+        fvco >>= 16;
+
+        return (unsigned long)fvco;
+}
+
+static const struct clk_ops samsung_pll36xx_clk_ops = {
+        .recalc_rate = samsung_pll36xx_recalc_rate,
+};
+
+struct clk * __init samsung_clk_register_pll36xx(const char *name,
+                        const char *pname, const void __iomem *con_reg)
+{
+        struct samsung_clk_pll36xx *pll;
+        struct clk *clk;
+        struct clk_init_data init;
+
+        pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+        if (!pll) {
+                pr_err("%s: could not allocate pll clk %s\n", __func__, name);
+                return NULL;
+        }
+
+        init.name = name;
+        init.ops = &samsung_pll36xx_clk_ops;
+        init.flags = CLK_GET_RATE_NOCACHE;
+        init.parent_names = &pname;
+        init.num_parents = 1;
+
+        pll->hw.init = &init;
+        pll->con_reg = con_reg;
+
+        clk = clk_register(NULL, &pll->hw);
+        if (IS_ERR(clk)) {
+                pr_err("%s: failed to register pll clock %s\n", __func__,
+                                name);
+                kfree(pll);
+        }
+
+        if (clk_register_clkdev(clk, name, NULL))
+                pr_err("%s: failed to register lookup for %s", __func__, name);
+
+        return clk;
+}
+
+/*
+ * PLL45xx Clock Type
+ */
+
+#define PLL45XX_MDIV_MASK       (0x3FF)
+#define PLL45XX_PDIV_MASK       (0x3F)
+#define PLL45XX_SDIV_MASK       (0x7)
+#define PLL45XX_MDIV_SHIFT      (16)
+#define PLL45XX_PDIV_SHIFT      (8)
+#define PLL45XX_SDIV_SHIFT      (0)
+
+struct samsung_clk_pll45xx {
+        struct clk_hw           hw;
+        enum pll45xx_type       type;
+        const void __iomem      *con_reg;
+};
+
+#define to_clk_pll45xx(_hw) container_of(_hw, struct samsung_clk_pll45xx, hw)
+
+static unsigned long samsung_pll45xx_recalc_rate(struct clk_hw *hw,
+                                unsigned long parent_rate)
+{
+        struct samsung_clk_pll45xx *pll = to_clk_pll45xx(hw);
+        u32 mdiv, pdiv, sdiv, pll_con;
+        u64 fvco = parent_rate;
+
+        pll_con = __raw_readl(pll->con_reg);
+        mdiv = (pll_con >> PLL45XX_MDIV_SHIFT) & PLL45XX_MDIV_MASK;
+        pdiv = (pll_con >> PLL45XX_PDIV_SHIFT) & PLL45XX_PDIV_MASK;
+        sdiv = (pll_con >> PLL45XX_SDIV_SHIFT) & PLL45XX_SDIV_MASK;
+
+        if (pll->type == pll_4508)
+                sdiv = sdiv - 1;
+
+        fvco *= mdiv;
+        do_div(fvco, (pdiv << sdiv));
+
+        return (unsigned long)fvco;
+}
+
+static const struct clk_ops samsung_pll45xx_clk_ops = {
+        .recalc_rate = samsung_pll45xx_recalc_rate,
+};
+
+struct clk * __init samsung_clk_register_pll45xx(const char *name,
+                        const char *pname, const void __iomem *con_reg,
+                        enum pll45xx_type type)
+{
+        struct samsung_clk_pll45xx *pll;
+        struct clk *clk;
+        struct clk_init_data init;
+
+        pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+        if (!pll) {
+                pr_err("%s: could not allocate pll clk %s\n", __func__, name);
+                return NULL;
+        }
+
+        init.name = name;
+        init.ops = &samsung_pll45xx_clk_ops;
+        init.flags = CLK_GET_RATE_NOCACHE;
+        init.parent_names = &pname;
+        init.num_parents = 1;
+
+        pll->hw.init = &init;
+        pll->con_reg = con_reg;
+        pll->type = type;
+
+        clk = clk_register(NULL, &pll->hw);
+        if (IS_ERR(clk)) {
+                pr_err("%s: failed to register pll clock %s\n", __func__,
+                                name);
+                kfree(pll);
+        }
+
+        if (clk_register_clkdev(clk, name, NULL))
+                pr_err("%s: failed to register lookup for %s", __func__, name);
+
+        return clk;
+}
+
+/*
+ * PLL46xx Clock Type
+ */
+
+#define PLL46XX_MDIV_MASK       (0x1FF)
+#define PLL46XX_PDIV_MASK       (0x3F)
+#define PLL46XX_SDIV_MASK       (0x7)
+#define PLL46XX_MDIV_SHIFT      (16)
+#define PLL46XX_PDIV_SHIFT      (8)
+#define PLL46XX_SDIV_SHIFT      (0)
+
+#define PLL46XX_KDIV_MASK       (0xFFFF)
+#define PLL4650C_KDIV_MASK      (0xFFF)
+#define PLL46XX_KDIV_SHIFT      (0)
+
+struct samsung_clk_pll46xx {
+        struct clk_hw           hw;
+        enum pll46xx_type       type;
+        const void __iomem      *con_reg;
+};
+
+#define to_clk_pll46xx(_hw) container_of(_hw, struct samsung_clk_pll46xx, hw)
+
+static unsigned long samsung_pll46xx_recalc_rate(struct clk_hw *hw,
+                                unsigned long parent_rate)
+{
+        struct samsung_clk_pll46xx *pll = to_clk_pll46xx(hw);
+        u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1, shift;
+        u64 fvco = parent_rate;
+
+        pll_con0 = __raw_readl(pll->con_reg);
+        pll_con1 = __raw_readl(pll->con_reg + 4);
+        mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & PLL46XX_MDIV_MASK;
+        pdiv = (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK;
+        sdiv = (pll_con0 >> PLL46XX_SDIV_SHIFT) & PLL46XX_SDIV_MASK;
+        kdiv = pll->type == pll_4650c ? pll_con1 & PLL4650C_KDIV_MASK :
+                                        pll_con1 & PLL46XX_KDIV_MASK;
+
+        shift = pll->type == pll_4600 ? 16 : 10;
+        fvco *= (mdiv << shift) + kdiv;
+        do_div(fvco, (pdiv << sdiv));
+        fvco >>= shift;
+
+        return (unsigned long)fvco;
+}
+
+static const struct clk_ops samsung_pll46xx_clk_ops = {
+        .recalc_rate = samsung_pll46xx_recalc_rate,
+};
+
+struct clk * __init samsung_clk_register_pll46xx(const char *name,
+                        const char *pname, const void __iomem *con_reg,
+                        enum pll46xx_type type)
+{
+        struct samsung_clk_pll46xx *pll;
+        struct clk *clk;
+        struct clk_init_data init;
+
+        pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+        if (!pll) {
+                pr_err("%s: could not allocate pll clk %s\n", __func__, name);
+                return NULL;
+        }
+
+        init.name = name;
+        init.ops = &samsung_pll46xx_clk_ops;
+        init.flags = CLK_GET_RATE_NOCACHE;
+        init.parent_names = &pname;
+        init.num_parents = 1;
+
+        pll->hw.init = &init;
+        pll->con_reg = con_reg;
+        pll->type = type;
+
+        clk = clk_register(NULL, &pll->hw);
+        if (IS_ERR(clk)) {
+                pr_err("%s: failed to register pll clock %s\n", __func__,
+                                name);
+                kfree(pll);
+        }
+
+        if (clk_register_clkdev(clk, name, NULL))
+                pr_err("%s: failed to register lookup for %s", __func__, name);
+
+        return clk;
+}
+
+/*
+ * PLL2550x Clock Type
+ */
+
+#define PLL2550X_R_MASK       (0x1)
+#define PLL2550X_P_MASK       (0x3F)
+#define PLL2550X_M_MASK       (0x3FF)
+#define PLL2550X_S_MASK       (0x7)
+#define PLL2550X_R_SHIFT      (20)
+#define PLL2550X_P_SHIFT      (14)
+#define PLL2550X_M_SHIFT      (4)
+#define PLL2550X_S_SHIFT      (0)
+
+struct samsung_clk_pll2550x {
+        struct clk_hw           hw;
+        const void __iomem      *reg_base;
+        unsigned long           offset;
+};
+
+#define to_clk_pll2550x(_hw) container_of(_hw, struct samsung_clk_pll2550x, hw)
+
+static unsigned long samsung_pll2550x_recalc_rate(struct clk_hw *hw,
+                                unsigned long parent_rate)
+{
+        struct samsung_clk_pll2550x *pll = to_clk_pll2550x(hw);
+        u32 r, p, m, s, pll_stat;
+        u64 fvco = parent_rate;
+
+        pll_stat = __raw_readl(pll->reg_base + pll->offset * 3);
+        r = (pll_stat >> PLL2550X_R_SHIFT) & PLL2550X_R_MASK;
+        if (!r)
+                return 0;
+        p = (pll_stat >> PLL2550X_P_SHIFT) & PLL2550X_P_MASK;
+        m = (pll_stat >> PLL2550X_M_SHIFT) & PLL2550X_M_MASK;
+        s = (pll_stat >> PLL2550X_S_SHIFT) & PLL2550X_S_MASK;
+
+        fvco *= m;
+        do_div(fvco, (p << s));
+
+        return (unsigned long)fvco;
+}
+
+static const struct clk_ops samsung_pll2550x_clk_ops = {
+        .recalc_rate = samsung_pll2550x_recalc_rate,
+};
+
+struct clk * __init samsung_clk_register_pll2550x(const char *name,
+                        const char *pname, const void __iomem *reg_base,
+                        const unsigned long offset)
+{
+        struct samsung_clk_pll2550x *pll;
+        struct clk *clk;
+        struct clk_init_data init;
+
+        pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+        if (!pll) {
+                pr_err("%s: could not allocate pll clk %s\n", __func__, name);
+                return NULL;
+        }
+
+        init.name = name;
+        init.ops = &samsung_pll2550x_clk_ops;
+        init.flags = CLK_GET_RATE_NOCACHE;
+        init.parent_names = &pname;
+        init.num_parents = 1;
+
+        pll->hw.init = &init;
+        pll->reg_base = reg_base;
+        pll->offset = offset;
+
+        clk = clk_register(NULL, &pll->hw);
+        if (IS_ERR(clk)) {
+                pr_err("%s: failed to register pll clock %s\n", __func__,
+                                name);
+                kfree(pll);
+        }
+
+        if (clk_register_clkdev(clk, name, NULL))
+                pr_err("%s: failed to register lookup for %s", __func__, name);
+
+        return clk;
+}
diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h
new file mode 100644
index 000000000000..f33786e9a78b
--- /dev/null
+++ b/drivers/clk/samsung/clk-pll.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2013 Linaro Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for all PLL's in Samsung platforms
+*/
+
+#ifndef __SAMSUNG_CLK_PLL_H
+#define __SAMSUNG_CLK_PLL_H
+
+enum pll45xx_type {
+        pll_4500,
+        pll_4502,
+        pll_4508
+};
+
+enum pll46xx_type {
+        pll_4600,
+        pll_4650,
+        pll_4650c,
+};
+
+extern struct clk * __init samsung_clk_register_pll35xx(const char *name,
+                        const char *pname, const void __iomem *con_reg);
+extern struct clk * __init samsung_clk_register_pll36xx(const char *name,
+                        const char *pname, const void __iomem *con_reg);
+extern struct clk * __init samsung_clk_register_pll45xx(const char *name,
+                        const char *pname, const void __iomem *con_reg,
+                        enum pll45xx_type type);
+extern struct clk * __init samsung_clk_register_pll46xx(const char *name,
+                        const char *pname, const void __iomem *con_reg,
+                        enum pll46xx_type type);
+extern struct clk * __init samsung_clk_register_pll2550x(const char *name,
+                        const char *pname, const void __iomem *reg_base,
+                        const unsigned long offset);
+
+#endif /* __SAMSUNG_CLK_PLL_H */
diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c
new file mode 100644
index 000000000000..cd3c40ab50f3
--- /dev/null
+++ b/drivers/clk/samsung/clk.c
@@ -0,0 +1,320 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2013 Linaro Ltd.
+ * Author: Thomas Abraham <thomas.ab@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This file includes utility functions to register clocks to common
+ * clock framework for Samsung platforms.
+*/
+
+#include <linux/syscore_ops.h>
+#include "clk.h"
+
+static DEFINE_SPINLOCK(lock);
+static struct clk **clk_table;
+static void __iomem *reg_base;
+#ifdef CONFIG_OF
+static struct clk_onecell_data clk_data;
+#endif
+
+#ifdef CONFIG_PM_SLEEP
+static struct samsung_clk_reg_dump *reg_dump;
+static unsigned long nr_reg_dump;
+
+static int samsung_clk_suspend(void)
+{
+        struct samsung_clk_reg_dump *rd = reg_dump;
+        unsigned long i;
+
+        for (i = 0; i < nr_reg_dump; i++, rd++)
+                rd->value = __raw_readl(reg_base + rd->offset);
+
+        return 0;
+}
+
+static void samsung_clk_resume(void)
+{
+        struct samsung_clk_reg_dump *rd = reg_dump;
+        unsigned long i;
+
+        for (i = 0; i < nr_reg_dump; i++, rd++)
+                __raw_writel(rd->value, reg_base + rd->offset);
+}
+
+static struct syscore_ops samsung_clk_syscore_ops = {
+        .suspend        = samsung_clk_suspend,
+        .resume         = samsung_clk_resume,
+};
+#endif /* CONFIG_PM_SLEEP */
+
+/* setup the essentials required to support clock lookup using ccf */
+void __init samsung_clk_init(struct device_node *np, void __iomem *base,
+                unsigned long nr_clks, unsigned long *rdump,
+                unsigned long nr_rdump, unsigned long *soc_rdump,
+                unsigned long nr_soc_rdump)
+{
+        reg_base = base;
+
+#ifdef CONFIG_PM_SLEEP
+        if (rdump && nr_rdump) {
+                unsigned int idx;
+                reg_dump = kzalloc(sizeof(struct samsung_clk_reg_dump)
+                                * (nr_rdump + nr_soc_rdump), GFP_KERNEL);
+                if (!reg_dump) {
+                        pr_err("%s: memory alloc for register dump failed\n",
+                                        __func__);
+                        return;
+                }
+
+                for (idx = 0; idx < nr_rdump; idx++)
+                        reg_dump[idx].offset = rdump[idx];
+                for (idx = 0; idx < nr_soc_rdump; idx++)
+                        reg_dump[nr_rdump + idx].offset = soc_rdump[idx];
+                nr_reg_dump = nr_rdump + nr_soc_rdump;
+                register_syscore_ops(&samsung_clk_syscore_ops);
+        }
+#endif
+
+        clk_table = kzalloc(sizeof(struct clk *) * nr_clks, GFP_KERNEL);
+        if (!clk_table)
+                panic("could not allocate clock lookup table\n");
+
+        if (!np)
+                return;
+
+#ifdef CONFIG_OF
+        clk_data.clks = clk_table;
+        clk_data.clk_num = nr_clks;
+        of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+#endif
+}
+
+/* add a clock instance to the clock lookup table used for dt based lookup */
+void samsung_clk_add_lookup(struct clk *clk, unsigned int id)
+{
+        if (clk_table && id)
+                clk_table[id] = clk;
+}
+
+/* register a list of aliases */
+void __init samsung_clk_register_alias(struct samsung_clock_alias *list,
+                                        unsigned int nr_clk)
+{
+        struct clk *clk;
+        unsigned int idx, ret;
+
+        if (!clk_table) {
+                pr_err("%s: clock table missing\n", __func__);
+                return;
+        }
+
+        for (idx = 0; idx < nr_clk; idx++, list++) {
+                if (!list->id) {
+                        pr_err("%s: clock id missing for index %d\n", __func__,
+                                idx);
+                        continue;
+                }
+
+                clk = clk_table[list->id];
+                if (!clk) {
+                        pr_err("%s: failed to find clock %d\n", __func__,
+                                list->id);
+                        continue;
+                }
+
+                ret = clk_register_clkdev(clk, list->alias, list->dev_name);
+                if (ret)
+                        pr_err("%s: failed to register lookup %s\n",
+                                        __func__, list->alias);
+        }
+}
+
+/* register a list of fixed clocks */
+void __init samsung_clk_register_fixed_rate(
+                struct samsung_fixed_rate_clock *list, unsigned int nr_clk)
+{
+        struct clk *clk;
+        unsigned int idx, ret;
+
+        for (idx = 0; idx < nr_clk; idx++, list++) {
+                clk = clk_register_fixed_rate(NULL, list->name,
+                        list->parent_name, list->flags, list->fixed_rate);
+                if (IS_ERR(clk)) {
+                        pr_err("%s: failed to register clock %s\n", __func__,
+                                list->name);
+                        continue;
+                }
+
+                samsung_clk_add_lookup(clk, list->id);
+
+                /*
+                 * Unconditionally add a clock lookup for the fixed rate clocks.
+                 * There are not many of these on any of Samsung platforms.
+                 */
+                ret = clk_register_clkdev(clk, list->name, NULL);
+                if (ret)
+                        pr_err("%s: failed to register clock lookup for %s",
+                                __func__, list->name);
+        }
+}
+
+/* register a list of fixed factor clocks */
+void __init samsung_clk_register_fixed_factor(
+                struct samsung_fixed_factor_clock *list, unsigned int nr_clk)
+{
+        struct clk *clk;
+        unsigned int idx;
+
+        for (idx = 0; idx < nr_clk; idx++, list++) {
+                clk = clk_register_fixed_factor(NULL, list->name,
+                        list->parent_name, list->flags, list->mult, list->div);
+                if (IS_ERR(clk)) {
+                        pr_err("%s: failed to register clock %s\n", __func__,
+                                list->name);
+                        continue;
+                }
+
+                samsung_clk_add_lookup(clk, list->id);
+        }
+}
+
+/* register a list of mux clocks */
+void __init samsung_clk_register_mux(struct samsung_mux_clock *list,
+                                        unsigned int nr_clk)
+{
+        struct clk *clk;
+        unsigned int idx, ret;
+
+        for (idx = 0; idx < nr_clk; idx++, list++) {
+                clk = clk_register_mux(NULL, list->name, list->parent_names,
+                        list->num_parents, list->flags, reg_base + list->offset,
+                        list->shift, list->width, list->mux_flags, &lock);
+                if (IS_ERR(clk)) {
+                        pr_err("%s: failed to register clock %s\n", __func__,
+                                list->name);
+                        continue;
+                }
+
+                samsung_clk_add_lookup(clk, list->id);
+
+                /* register a clock lookup only if a clock alias is specified */
+                if (list->alias) {
+                        ret = clk_register_clkdev(clk, list->alias,
+                                                list->dev_name);
+                        if (ret)
+                                pr_err("%s: failed to register lookup %s\n",
+                                                __func__, list->alias);
+                }
+        }
+}
+
+/* register a list of div clocks */
+void __init samsung_clk_register_div(struct samsung_div_clock *list,
+                                        unsigned int nr_clk)
+{
+        struct clk *clk;
+        unsigned int idx, ret;
+
+        for (idx = 0; idx < nr_clk; idx++, list++) {
+                if (list->table)
+                        clk = clk_register_divider_table(NULL, list->name,
+                                        list->parent_name, list->flags,
+                                        reg_base + list->offset, list->shift,
+                                        list->width, list->div_flags,
+                                        list->table, &lock);
+                else
+                        clk = clk_register_divider(NULL, list->name,
+                                        list->parent_name, list->flags,
+                                        reg_base + list->offset, list->shift,
+                                        list->width, list->div_flags, &lock);
+                if (IS_ERR(clk)) {
+                        pr_err("%s: failed to register clock %s\n", __func__,
+                                list->name);
+                        continue;
+                }
+
+                samsung_clk_add_lookup(clk, list->id);
+
+                /* register a clock lookup only if a clock alias is specified */
+                if (list->alias) {
+                        ret = clk_register_clkdev(clk, list->alias,
+                                                list->dev_name);
+                        if (ret)
+                                pr_err("%s: failed to register lookup %s\n",
+                                                __func__, list->alias);
+                }
+        }
+}
+
+/* register a list of gate clocks */
+void __init samsung_clk_register_gate(struct samsung_gate_clock *list,
+                                                unsigned int nr_clk)
+{
+        struct clk *clk;
+        unsigned int idx, ret;
+
+        for (idx = 0; idx < nr_clk; idx++, list++) {
+                clk = clk_register_gate(NULL, list->name, list->parent_name,
+                                list->flags, reg_base + list->offset,
+                                list->bit_idx, list->gate_flags, &lock);
+                if (IS_ERR(clk)) {
+                        pr_err("%s: failed to register clock %s\n", __func__,
+                                list->name);
+                        continue;
+                }
+
+                /* register a clock lookup only if a clock alias is specified */
+                if (list->alias) {
+                        ret = clk_register_clkdev(clk, list->alias,
+                                                        list->dev_name);
+                        if (ret)
+                                pr_err("%s: failed to register lookup %s\n",
+                                        __func__, list->alias);
+                }
+
+                samsung_clk_add_lookup(clk, list->id);
+        }
+}
+
+/*
+ * obtain the clock speed of all external fixed clock sources from device
+ * tree and register it
+ */
+#ifdef CONFIG_OF
+void __init samsung_clk_of_register_fixed_ext(
+                        struct samsung_fixed_rate_clock *fixed_rate_clk,
+                        unsigned int nr_fixed_rate_clk,
+                        struct of_device_id *clk_matches)
+{
+        const struct of_device_id *match;
+        struct device_node *np;
+        u32 freq;
+
+        for_each_matching_node_and_match(np, clk_matches, &match) {
+                if (of_property_read_u32(np, "clock-frequency", &freq))
+                        continue;
+                fixed_rate_clk[(u32)match->data].fixed_rate = freq;
+        }
+        samsung_clk_register_fixed_rate(fixed_rate_clk, nr_fixed_rate_clk);
+}
+#endif
+
+/* utility function to get the rate of a specified clock */
+unsigned long _get_rate(const char *clk_name)
+{
+        struct clk *clk;
+        unsigned long rate;
+
+        clk = clk_get(NULL, clk_name);
+        if (IS_ERR(clk)) {
+                pr_err("%s: could not find clock %s\n", __func__, clk_name);
+                return 0;
+        }
+        rate = clk_get_rate(clk);
+        clk_put(clk);
+        return rate;
+}
diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h
new file mode 100644
index 000000000000..10b2111f0c0f
--- /dev/null
+++ b/drivers/clk/samsung/clk.h
@@ -0,0 +1,289 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2013 Linaro Ltd.
+ * Author: Thomas Abraham <thomas.ab@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for all Samsung platforms
+*/
+
+#ifndef __SAMSUNG_CLK_H
+#define __SAMSUNG_CLK_H
+
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/io.h>
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+#include <mach/map.h>
+
+/**
+ * struct samsung_clock_alias: information about mux clock
+ * @id: platform specific id of the clock.
+ * @dev_name: name of the device to which this clock belongs.
+ * @alias: optional clock alias name to be assigned to this clock.
+ */
+struct samsung_clock_alias {
+        unsigned int            id;
+        const char              *dev_name;
+        const char              *alias;
+};
+
+#define ALIAS(_id, dname, a)    \
+        {                                                       \
+                .id             = _id,                          \
+                .dev_name       = dname,                        \
+                .alias          = a,                            \
+        }
+
+/**
+ * struct samsung_fixed_rate_clock: information about fixed-rate clock
+ * @id: platform specific id of the clock.
+ * @name: name of this fixed-rate clock.
+ * @parent_name: optional parent clock name.
+ * @flags: optional fixed-rate clock flags.
+ * @fixed-rate: fixed clock rate of this clock.
+ */
+struct samsung_fixed_rate_clock {
+        unsigned int            id;
+        char                    *name;
+        const char              *parent_name;
+        unsigned long           flags;
+        unsigned long           fixed_rate;
+};
+
+#define FRATE(_id, cname, pname, f, frate)              \
+        {                                               \
+                .id             = _id,                  \
+                .name           = cname,                \
+                .parent_name    = pname,                \
+                .flags          = f,                    \
+                .fixed_rate     = frate,                \
+        }
+
+/*
+ * struct samsung_fixed_factor_clock: information about fixed-factor clock
+ * @id: platform specific id of the clock.
+ * @name: name of this fixed-factor clock.
+ * @parent_name: parent clock name.
+ * @mult: fixed multiplication factor.
+ * @div: fixed division factor.
+ * @flags: optional fixed-factor clock flags.
+ */
+struct samsung_fixed_factor_clock {
+        unsigned int            id;
+        char                    *name;
+        const char              *parent_name;
+        unsigned long           mult;
+        unsigned long           div;
+        unsigned long           flags;
+};
+
+#define FFACTOR(_id, cname, pname, m, d, f)             \
+        {                                               \
+                .id             = _id,                  \
+                .name           = cname,                \
+                .parent_name    = pname,                \
+                .mult           = m,                    \
+                .div            = d,                    \
+                .flags          = f,                    \
+        }
+
+/**
+ * struct samsung_mux_clock: information about mux clock
+ * @id: platform specific id of the clock.
+ * @dev_name: name of the device to which this clock belongs.
+ * @name: name of this mux clock.
+ * @parent_names: array of pointer to parent clock names.
+ * @num_parents: number of parents listed in @parent_names.
+ * @flags: optional flags for basic clock.
+ * @offset: offset of the register for configuring the mux.
+ * @shift: starting bit location of the mux control bit-field in @reg.
+ * @width: width of the mux control bit-field in @reg.
+ * @mux_flags: flags for mux-type clock.
+ * @alias: optional clock alias name to be assigned to this clock.
+ */
+struct samsung_mux_clock {
+        unsigned int            id;
+        const char              *dev_name;
+        const char              *name;
+        const char              **parent_names;
+        u8                      num_parents;
+        unsigned long           flags;
+        unsigned long           offset;
+        u8                      shift;
+        u8                      width;
+        u8                      mux_flags;
+        const char              *alias;
+};
+
+#define __MUX(_id, dname, cname, pnames, o, s, w, f, mf, a)     \
+        {                                                       \
+                .id             = _id,                          \
+                .dev_name       = dname,                        \
+                .name           = cname,                        \
+                .parent_names   = pnames,                       \
+                .num_parents    = ARRAY_SIZE(pnames),           \
+                .flags          = f,                            \
+                .offset         = o,                            \
+                .shift          = s,                            \
+                .width          = w,                            \
+                .mux_flags      = mf,                           \
+                .alias          = a,                            \
+        }
+
+#define MUX(_id, cname, pnames, o, s, w)                        \
+        __MUX(_id, NULL, cname, pnames, o, s, w, 0, 0, NULL)
+
+#define MUX_A(_id, cname, pnames, o, s, w, a)                   \
+        __MUX(_id, NULL, cname, pnames, o, s, w, 0, 0, a)
+
+#define MUX_F(_id, cname, pnames, o, s, w, f, mf)               \
+        __MUX(_id, NULL, cname, pnames, o, s, w, f, mf, NULL)
+
+/**
+ * @id: platform specific id of the clock.
+ * struct samsung_div_clock: information about div clock
+ * @dev_name: name of the device to which this clock belongs.
+ * @name: name of this div clock.
+ * @parent_name: name of the parent clock.
+ * @flags: optional flags for basic clock.
+ * @offset: offset of the register for configuring the div.
+ * @shift: starting bit location of the div control bit-field in @reg.
+ * @div_flags: flags for div-type clock.
+ * @alias: optional clock alias name to be assigned to this clock.
+ */
+struct samsung_div_clock {
+        unsigned int            id;
+        const char              *dev_name;
+        const char              *name;
+        const char              *parent_name;
+        unsigned long           flags;
+        unsigned long           offset;
+        u8                      shift;
+        u8                      width;
+        u8                      div_flags;
+        const char              *alias;
+        struct clk_div_table    *table;
+};
+
+#define __DIV(_id, dname, cname, pname, o, s, w, f, df, a, t)   \
+        {                                                       \
+                .id             = _id,                          \
+                .dev_name       = dname,                        \
+                .name           = cname,                        \
+                .parent_name    = pname,                        \
+                .flags          = f,                            \
+                .offset         = o,                            \
+                .shift          = s,                            \
+                .width          = w,                            \
+                .div_flags      = df,                           \
+                .alias          = a,                            \
+                .table          = t,                            \
+        }
+
+#define DIV(_id, cname, pname, o, s, w)                         \
+        __DIV(_id, NULL, cname, pname, o, s, w, 0, 0, NULL, NULL)
+
+#define DIV_A(_id, cname, pname, o, s, w, a)                    \
+        __DIV(_id, NULL, cname, pname, o, s, w, 0, 0, a, NULL)
+
+#define DIV_F(_id, cname, pname, o, s, w, f, df)                \
+        __DIV(_id, NULL, cname, pname, o, s, w, f, df, NULL, NULL)
+
+#define DIV_T(_id, cname, pname, o, s, w, t)                    \
+        __DIV(_id, NULL, cname, pname, o, s, w, 0, 0, NULL, t)
+
+/**
+ * struct samsung_gate_clock: information about gate clock
+ * @id: platform specific id of the clock.
+ * @dev_name: name of the device to which this clock belongs.
+ * @name: name of this gate clock.
+ * @parent_name: name of the parent clock.
+ * @flags: optional flags for basic clock.
+ * @offset: offset of the register for configuring the gate.
+ * @bit_idx: bit index of the gate control bit-field in @reg.
+ * @gate_flags: flags for gate-type clock.
+ * @alias: optional clock alias name to be assigned to this clock.
+ */
+struct samsung_gate_clock {
+        unsigned int            id;
+        const char              *dev_name;
+        const char              *name;
+        const char              *parent_name;
+        unsigned long           flags;
+        unsigned long           offset;
+        u8                      bit_idx;
+        u8                      gate_flags;
+        const char              *alias;
+};
+
+#define __GATE(_id, dname, cname, pname, o, b, f, gf, a)        \
+        {                                                       \
+                .id             = _id,                          \
+                .dev_name       = dname,                        \
+                .name           = cname,                        \
+                .parent_name    = pname,                        \
+                .flags          = f,                            \
+                .offset         = o,                            \
+                .bit_idx        = b,                            \
+                .gate_flags     = gf,                           \
+                .alias          = a,                            \
+        }
+
+#define GATE(_id, cname, pname, o, b, f, gf)                    \
+        __GATE(_id, NULL, cname, pname, o, b, f, gf, NULL)
+
+#define GATE_A(_id, cname, pname, o, b, f, gf, a)               \
+        __GATE(_id, NULL, cname, pname, o, b, f, gf, a)
+
+#define GATE_D(_id, dname, cname, pname, o, b, f, gf)           \
+        __GATE(_id, dname, cname, pname, o, b, f, gf, NULL)
+
+#define GATE_DA(_id, dname, cname, pname, o, b, f, gf, a)       \
+        __GATE(_id, dname, cname, pname, o, b, f, gf, a)
+
+#define PNAME(x) static const char *x[] __initdata
+
+/**
+ * struct samsung_clk_reg_dump: register dump of clock controller registers.
+ * @offset: clock register offset from the controller base address.
+ * @value: the value to be register at offset.
+ */
+struct samsung_clk_reg_dump {
+        u32     offset;
+        u32     value;
+};
+
+extern void __init samsung_clk_init(struct device_node *np, void __iomem *base,
+                unsigned long nr_clks, unsigned long *rdump,
+                unsigned long nr_rdump, unsigned long *soc_rdump,
+                unsigned long nr_soc_rdump);
+extern void __init samsung_clk_of_register_fixed_ext(
+                struct samsung_fixed_rate_clock *fixed_rate_clk,
+                unsigned int nr_fixed_rate_clk,
+                struct of_device_id *clk_matches);
+
+extern void samsung_clk_add_lookup(struct clk *clk, unsigned int id);
+
+extern void samsung_clk_register_alias(struct samsung_clock_alias *list,
+                unsigned int nr_clk);
+extern void __init samsung_clk_register_fixed_rate(
+                struct samsung_fixed_rate_clock *clk_list, unsigned int nr_clk);
+extern void __init samsung_clk_register_fixed_factor(
+                struct samsung_fixed_factor_clock *list, unsigned int nr_clk);
+extern void __init samsung_clk_register_mux(struct samsung_mux_clock *clk_list,
+                unsigned int nr_clk);
+extern void __init samsung_clk_register_div(struct samsung_div_clock *clk_list,
+                unsigned int nr_clk);
+extern void __init samsung_clk_register_gate(
+                struct samsung_gate_clock *clk_list, unsigned int nr_clk);
+
+extern unsigned long _get_rate(const char *clk_name);
+
+#endif /* __SAMSUNG_CLK_H */
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index e507ab7df60b..e8c453285151 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -67,3 +67,8 @@ config CLKSRC_METAG_GENERIC
         def_bool y if METAG
         help
           This option enables support for the Meta per-thread timers.
+
+config CLKSRC_EXYNOS_MCT
+        def_bool y if ARCH_EXYNOS
+        help
+          Support for Multi Core Timer controller on Exynos SoCs.
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 4d8283aec5b5..1c1b15db7c4d 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_ARCH_BCM2835)	+= bcm2835_timer.o
 obj-$(CONFIG_SUNXI_TIMER)       += sunxi_timer.o
 obj-$(CONFIG_ARCH_TEGRA)        += tegra20_timer.o
 obj-$(CONFIG_VT8500_TIMER)      += vt8500_timer.o
+obj-$(CONFIG_CLKSRC_EXYNOS_MCT) += exynos_mct.o
 
 obj-$(CONFIG_ARM_ARCH_TIMER)            += arm_arch_timer.o
 obj-$(CONFIG_CLKSRC_METAG_GENERIC)      += metag_generic.o
diff --git a/arch/arm/mach-exynos/mct.c b/drivers/clocksource/exynos_mct.c
index c9d6650f9b5d..203ac05e2b3d 100644
--- a/arch/arm/mach-exynos/mct.c
+++ b/drivers/clocksource/exynos_mct.c
@@ -20,6 +20,9 @@
 #include <linux/delay.h>
 #include <linux/percpu.h>
 #include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
+#include <linux/clocksource.h>
 
 #include <asm/arch_timer.h>
 #include <asm/localtimer.h>
@@ -28,9 +31,36 @@
 
 #include <mach/map.h>
 #include <mach/irqs.h>
-#include <mach/regs-mct.h>
 #include <asm/mach/time.h>
 
+#define EXYNOS4_MCTREG(x)               (x)
+#define EXYNOS4_MCT_G_CNT_L             EXYNOS4_MCTREG(0x100)
+#define EXYNOS4_MCT_G_CNT_U             EXYNOS4_MCTREG(0x104)
+#define EXYNOS4_MCT_G_CNT_WSTAT         EXYNOS4_MCTREG(0x110)
+#define EXYNOS4_MCT_G_COMP0_L           EXYNOS4_MCTREG(0x200)
+#define EXYNOS4_MCT_G_COMP0_U           EXYNOS4_MCTREG(0x204)
+#define EXYNOS4_MCT_G_COMP0_ADD_INCR    EXYNOS4_MCTREG(0x208)
+#define EXYNOS4_MCT_G_TCON              EXYNOS4_MCTREG(0x240)
+#define EXYNOS4_MCT_G_INT_CSTAT         EXYNOS4_MCTREG(0x244)
+#define EXYNOS4_MCT_G_INT_ENB           EXYNOS4_MCTREG(0x248)
+#define EXYNOS4_MCT_G_WSTAT             EXYNOS4_MCTREG(0x24C)
+#define _EXYNOS4_MCT_L_BASE             EXYNOS4_MCTREG(0x300)
+#define EXYNOS4_MCT_L_BASE(x)           (_EXYNOS4_MCT_L_BASE + (0x100 * x))
+#define EXYNOS4_MCT_L_MASK              (0xffffff00)
+
+#define MCT_L_TCNTB_OFFSET              (0x00)
+#define MCT_L_ICNTB_OFFSET              (0x08)
+#define MCT_L_TCON_OFFSET               (0x20)
+#define MCT_L_INT_CSTAT_OFFSET          (0x30)
+#define MCT_L_INT_ENB_OFFSET            (0x34)
+#define MCT_L_WSTAT_OFFSET              (0x40)
+#define MCT_G_TCON_START                (1 << 8)
+#define MCT_G_TCON_COMP0_AUTO_INC       (1 << 1)
+#define MCT_G_TCON_COMP0_ENABLE         (1 << 0)
+#define MCT_L_TCON_INTERVAL_MODE        (1 << 2)
+#define MCT_L_TCON_INT_START            (1 << 1)
+#define MCT_L_TCON_TIMER_START          (1 << 0)
+
 #define TICK_BASE_CNT   1
 
 enum {
@@ -38,64 +68,75 @@ enum {
         MCT_INT_PPI
 };
 
+enum {
+        MCT_G0_IRQ,
+        MCT_G1_IRQ,
+        MCT_G2_IRQ,
+        MCT_G3_IRQ,
+        MCT_L0_IRQ,
+        MCT_L1_IRQ,
+        MCT_L2_IRQ,
+        MCT_L3_IRQ,
+        MCT_NR_IRQS,
+};
+
+static void __iomem *reg_base;
 static unsigned long clk_rate;
 static unsigned int mct_int_type;
+static int mct_irqs[MCT_NR_IRQS];
 
 struct mct_clock_event_device {
         struct clock_event_device *evt;
-        void __iomem *base;
+        unsigned long base;
         char name[10];
 };
 
-static void exynos4_mct_write(unsigned int value, void *addr)
+static void exynos4_mct_write(unsigned int value, unsigned long offset)
 {
-        void __iomem *stat_addr;
+        unsigned long stat_addr;
         u32 mask;
         u32 i;
 
-        __raw_writel(value, addr);
+        __raw_writel(value, reg_base + offset);
 
-        if (likely(addr >= EXYNOS4_MCT_L_BASE(0))) {
-                u32 base = (u32) addr & EXYNOS4_MCT_L_MASK;
-                switch ((u32) addr & ~EXYNOS4_MCT_L_MASK) {
-                case (u32) MCT_L_TCON_OFFSET:
-                        stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET;
+        if (likely(offset >= EXYNOS4_MCT_L_BASE(0))) {
+                stat_addr = (offset & ~EXYNOS4_MCT_L_MASK) + MCT_L_WSTAT_OFFSET;
+                switch (offset & EXYNOS4_MCT_L_MASK) {
+                case MCT_L_TCON_OFFSET:
                         mask = 1 << 3;          /* L_TCON write status */
                         break;
-                case (u32) MCT_L_ICNTB_OFFSET:
-                        stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET;
+                case MCT_L_ICNTB_OFFSET:
                         mask = 1 << 1;          /* L_ICNTB write status */
                         break;
-                case (u32) MCT_L_TCNTB_OFFSET:
-                        stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET;
+                case MCT_L_TCNTB_OFFSET:
                         mask = 1 << 0;          /* L_TCNTB write status */
                         break;
                 default:
                         return;
                 }
         } else {
-                switch ((u32) addr) {
-                case (u32) EXYNOS4_MCT_G_TCON:
+                switch (offset) {
+                case EXYNOS4_MCT_G_TCON:
                         stat_addr = EXYNOS4_MCT_G_WSTAT;
                         mask = 1 << 16;         /* G_TCON write status */
                         break;
-                case (u32) EXYNOS4_MCT_G_COMP0_L:
+                case EXYNOS4_MCT_G_COMP0_L:
                         stat_addr = EXYNOS4_MCT_G_WSTAT;
                         mask = 1 << 0;          /* G_COMP0_L write status */
                         break;
-                case (u32) EXYNOS4_MCT_G_COMP0_U:
+                case EXYNOS4_MCT_G_COMP0_U:
                         stat_addr = EXYNOS4_MCT_G_WSTAT;
                         mask = 1 << 1;          /* G_COMP0_U write status */
                         break;
-                case (u32) EXYNOS4_MCT_G_COMP0_ADD_INCR:
+                case EXYNOS4_MCT_G_COMP0_ADD_INCR:
                         stat_addr = EXYNOS4_MCT_G_WSTAT;
                         mask = 1 << 2;          /* G_COMP0_ADD_INCR w status */
                         break;
-                case (u32) EXYNOS4_MCT_G_CNT_L:
+                case EXYNOS4_MCT_G_CNT_L:
                         stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
                         mask = 1 << 0;          /* G_CNT_L write status */
                         break;
-                case (u32) EXYNOS4_MCT_G_CNT_U:
+                case EXYNOS4_MCT_G_CNT_U:
                         stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
                         mask = 1 << 1;          /* G_CNT_U write status */
                         break;
@@ -106,12 +147,12 @@ static void exynos4_mct_write(unsigned int value, void *addr)
 
         /* Wait maximum 1 ms until written values are applied */
         for (i = 0; i < loops_per_jiffy / 1000 * HZ; i++)
-                if (__raw_readl(stat_addr) & mask) {
-                        __raw_writel(mask, stat_addr);
+                if (__raw_readl(reg_base + stat_addr) & mask) {
+                        __raw_writel(mask, reg_base + stat_addr);
                         return;
                 }
 
-        panic("MCT hangs after writing %d (addr:0x%08x)\n", value, (u32)addr);
+        panic("MCT hangs after writing %d (offset:0x%lx)\n", value, offset);
 }
 
 /* Clocksource handling */
@@ -122,7 +163,7 @@ static void exynos4_mct_frc_start(u32 hi, u32 lo)
         exynos4_mct_write(lo, EXYNOS4_MCT_G_CNT_L);
         exynos4_mct_write(hi, EXYNOS4_MCT_G_CNT_U);
 
-        reg = __raw_readl(EXYNOS4_MCT_G_TCON);
+        reg = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
         reg |= MCT_G_TCON_START;
         exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON);
 }
@@ -130,12 +171,12 @@ static void exynos4_mct_frc_start(u32 hi, u32 lo)
 static cycle_t exynos4_frc_read(struct clocksource *cs)
 {
         unsigned int lo, hi;
-        u32 hi2 = __raw_readl(EXYNOS4_MCT_G_CNT_U);
+        u32 hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U);
 
         do {
                 hi = hi2;
-                lo = __raw_readl(EXYNOS4_MCT_G_CNT_L);
-                hi2 = __raw_readl(EXYNOS4_MCT_G_CNT_U);
+                lo = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_L);
+                hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U);
         } while (hi != hi2);
 
         return ((cycle_t)hi << 32) | lo;
@@ -167,7 +208,7 @@ static void exynos4_mct_comp0_stop(void)
 {
         unsigned int tcon;
 
-        tcon = __raw_readl(EXYNOS4_MCT_G_TCON);
+        tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
         tcon &= ~(MCT_G_TCON_COMP0_ENABLE | MCT_G_TCON_COMP0_AUTO_INC);
 
         exynos4_mct_write(tcon, EXYNOS4_MCT_G_TCON);
@@ -180,7 +221,7 @@ static void exynos4_mct_comp0_start(enum clock_event_mode mode,
         unsigned int tcon;
         cycle_t comp_cycle;
 
-        tcon = __raw_readl(EXYNOS4_MCT_G_TCON);
+        tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
 
         if (mode == CLOCK_EVT_MODE_PERIODIC) {
                 tcon |= MCT_G_TCON_COMP0_AUTO_INC;
@@ -257,11 +298,7 @@ static void exynos4_clockevent_init(void)
         mct_comp_device.cpumask = cpumask_of(0);
         clockevents_config_and_register(&mct_comp_device, clk_rate,
                                         0xf, 0xffffffff);
-
-        if (soc_is_exynos5250())
-                setup_irq(EXYNOS5_IRQ_MCT_G0, &mct_comp_event_irq);
-        else
-                setup_irq(EXYNOS4_IRQ_MCT_G0, &mct_comp_event_irq);
+        setup_irq(mct_irqs[MCT_G0_IRQ], &mct_comp_event_irq);
 }
 
 #ifdef CONFIG_LOCAL_TIMERS
@@ -273,12 +310,12 @@ static void exynos4_mct_tick_stop(struct mct_clock_event_device *mevt)
 {
         unsigned long tmp;
         unsigned long mask = MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START;
-        void __iomem *addr = mevt->base + MCT_L_TCON_OFFSET;
+        unsigned long offset = mevt->base + MCT_L_TCON_OFFSET;
 
-        tmp = __raw_readl(addr);
+        tmp = __raw_readl(reg_base + offset);
         if (tmp & mask) {
                 tmp &= ~mask;
-                exynos4_mct_write(tmp, addr);
+                exynos4_mct_write(tmp, offset);
         }
 }
 
@@ -297,7 +334,7 @@ static void exynos4_mct_tick_start(unsigned long cycles,
         /* enable MCT tick interrupt */
         exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET);
 
-        tmp = __raw_readl(mevt->base + MCT_L_TCON_OFFSET);
+        tmp = __raw_readl(reg_base + mevt->base + MCT_L_TCON_OFFSET);
         tmp |= MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START |
                MCT_L_TCON_INTERVAL_MODE;
         exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET);
@@ -349,7 +386,7 @@ static int exynos4_mct_tick_clear(struct mct_clock_event_device *mevt)
                 exynos4_mct_tick_stop(mevt);
 
         /* Clear the MCT tick interrupt */
-        if (__raw_readl(mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) {
+        if (__raw_readl(reg_base + mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) {
                 exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
                 return 1;
         } else {
@@ -385,7 +422,6 @@ static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt)
 {
         struct mct_clock_event_device *mevt;
         unsigned int cpu = smp_processor_id();
-        int mct_lx_irq;
 
         mevt = this_cpu_ptr(&percpu_mct_tick);
         mevt->evt = evt;
@@ -406,21 +442,17 @@ static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt)
 
         if (mct_int_type == MCT_INT_SPI) {
                 if (cpu == 0) {
-                        mct_lx_irq = soc_is_exynos4210() ? EXYNOS4_IRQ_MCT_L0 :
-                                                EXYNOS5_IRQ_MCT_L0;
                         mct_tick0_event_irq.dev_id = mevt;
-                        evt->irq = mct_lx_irq;
-                        setup_irq(mct_lx_irq, &mct_tick0_event_irq);
+                        evt->irq = mct_irqs[MCT_L0_IRQ];
+                        setup_irq(evt->irq, &mct_tick0_event_irq);
                 } else {
-                        mct_lx_irq = soc_is_exynos4210() ? EXYNOS4_IRQ_MCT_L1 :
-                                                EXYNOS5_IRQ_MCT_L1;
                         mct_tick1_event_irq.dev_id = mevt;
-                        evt->irq = mct_lx_irq;
-                        setup_irq(mct_lx_irq, &mct_tick1_event_irq);
-                        irq_set_affinity(mct_lx_irq, cpumask_of(1));
+                        evt->irq = mct_irqs[MCT_L1_IRQ];
+                        setup_irq(evt->irq, &mct_tick1_event_irq);
+                        irq_set_affinity(evt->irq, cpumask_of(1));
                 }
         } else {
-                enable_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER, 0);
+                enable_percpu_irq(mct_irqs[MCT_L0_IRQ], 0);
         }
 
         return 0;
@@ -436,7 +468,7 @@ static void exynos4_local_timer_stop(struct clock_event_device *evt)
                 else
                         remove_irq(evt->irq, &mct_tick1_event_irq);
         else
-                disable_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER);
+                disable_percpu_irq(mct_irqs[MCT_L0_IRQ]);
 }
 
 static struct local_timer_ops exynos4_mct_tick_ops __cpuinitdata = {
@@ -445,41 +477,82 @@ static struct local_timer_ops exynos4_mct_tick_ops __cpuinitdata = {
 };
 #endif /* CONFIG_LOCAL_TIMERS */
 
-static void __init exynos4_timer_resources(void)
+static void __init exynos4_timer_resources(struct device_node *np)
 {
-        struct clk *mct_clk;
-        mct_clk = clk_get(NULL, "xtal");
+        struct clk *mct_clk, *tick_clk;
+
+        tick_clk = np ? of_clk_get_by_name(np, "fin_pll") :
+                                clk_get(NULL, "fin_pll");
+        if (IS_ERR(tick_clk))
+                panic("%s: unable to determine tick clock rate\n", __func__);
+        clk_rate = clk_get_rate(tick_clk);
+
+        mct_clk = np ? of_clk_get_by_name(np, "mct") : clk_get(NULL, "mct");
+        if (IS_ERR(mct_clk))
+                panic("%s: unable to retrieve mct clock instance\n", __func__);
+        clk_prepare_enable(mct_clk);
 
-        clk_rate = clk_get_rate(mct_clk);
+        reg_base = np ? of_iomap(np, 0) : S5P_VA_SYSTIMER;
+        if (!reg_base)
+                panic("%s: unable to ioremap mct address space\n", __func__);
 
 #ifdef CONFIG_LOCAL_TIMERS
         if (mct_int_type == MCT_INT_PPI) {
                 int err;
 
-                err = request_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER,
+                err = request_percpu_irq(mct_irqs[MCT_L0_IRQ],
                                          exynos4_mct_tick_isr, "MCT",
                                          &percpu_mct_tick);
                 WARN(err, "MCT: can't request IRQ %d (%d)\n",
-                     EXYNOS_IRQ_MCT_LOCALTIMER, err);
+                     mct_irqs[MCT_L0_IRQ], err);
         }
 
         local_timer_register(&exynos4_mct_tick_ops);
 #endif /* CONFIG_LOCAL_TIMERS */
 }
 
-void __init exynos4_timer_init(void)
-{
-        if (soc_is_exynos5440()) {
-                arch_timer_of_register();
-                return;
-        }
+static const struct of_device_id exynos_mct_ids[] = {
+        { .compatible = "samsung,exynos4210-mct", .data = (void *)MCT_INT_SPI },
+        { .compatible = "samsung,exynos4412-mct", .data = (void *)MCT_INT_PPI },
+};
 
-        if ((soc_is_exynos4210()) || (soc_is_exynos5250()))
+void __init mct_init(void)
+{
+        struct device_node *np = NULL;
+        const struct of_device_id *match;
+        u32 nr_irqs, i;
+
+#ifdef CONFIG_OF
+        np = of_find_matching_node_and_match(NULL, exynos_mct_ids, &match);
+#endif
+        if (np) {
+                mct_int_type = (u32)(match->data);
+
+                /* This driver uses only one global timer interrupt */
+                mct_irqs[MCT_G0_IRQ] = irq_of_parse_and_map(np, MCT_G0_IRQ);
+
+                /*
+                 * Find out the number of local irqs specified. The local
+                 * timer irqs are specified after the four global timer
+                 * irqs are specified.
+                 */
+#ifdef CONFIG_OF
+                nr_irqs = of_irq_count(np);
+#endif
+                for (i = MCT_L0_IRQ; i < nr_irqs; i++)
+                        mct_irqs[i] = irq_of_parse_and_map(np, i);
+        } else if (soc_is_exynos4210()) {
+                mct_irqs[MCT_G0_IRQ] = EXYNOS4_IRQ_MCT_G0;
+                mct_irqs[MCT_L0_IRQ] = EXYNOS4_IRQ_MCT_L0;
+                mct_irqs[MCT_L1_IRQ] = EXYNOS4_IRQ_MCT_L1;
                 mct_int_type = MCT_INT_SPI;
-        else
-                mct_int_type = MCT_INT_PPI;
+        } else {
+                panic("unable to determine mct controller type\n");
+        }
 
-        exynos4_timer_resources();
+        exynos4_timer_resources(np);
         exynos4_clocksource_init();
         exynos4_clockevent_init();
 }
+CLOCKSOURCE_OF_DECLARE(exynos4210, "samsung,exynos4210-mct", mct_init)
+CLOCKSOURCE_OF_DECLARE(exynos4412, "samsung,exynos4412-mct", mct_init)
diff --git a/drivers/mmc/host/s3cmci.c b/drivers/mmc/host/s3cmci.c
index 63fb265e0da6..8d6794cdf899 100644
--- a/drivers/mmc/host/s3cmci.c
+++ b/drivers/mmc/host/s3cmci.c
@@ -25,14 +25,93 @@
 
 #include <mach/dma.h>
 
-#include <mach/regs-sdi.h>
-
 #include <linux/platform_data/mmc-s3cmci.h>
 
 #include "s3cmci.h"
 
 #define DRIVER_NAME "s3c-mci"
 
+#define S3C2410_SDICON                  (0x00)
+#define S3C2410_SDIPRE                  (0x04)
+#define S3C2410_SDICMDARG               (0x08)
+#define S3C2410_SDICMDCON               (0x0C)
+#define S3C2410_SDICMDSTAT              (0x10)
+#define S3C2410_SDIRSP0                 (0x14)
+#define S3C2410_SDIRSP1                 (0x18)
+#define S3C2410_SDIRSP2                 (0x1C)
+#define S3C2410_SDIRSP3                 (0x20)
+#define S3C2410_SDITIMER                (0x24)
+#define S3C2410_SDIBSIZE                (0x28)
+#define S3C2410_SDIDCON                 (0x2C)
+#define S3C2410_SDIDCNT                 (0x30)
+#define S3C2410_SDIDSTA                 (0x34)
+#define S3C2410_SDIFSTA                 (0x38)
+
+#define S3C2410_SDIDATA                 (0x3C)
+#define S3C2410_SDIIMSK                 (0x40)
+
+#define S3C2440_SDIDATA                 (0x40)
+#define S3C2440_SDIIMSK                 (0x3C)
+
+#define S3C2440_SDICON_SDRESET          (1 << 8)
+#define S3C2410_SDICON_SDIOIRQ          (1 << 3)
+#define S3C2410_SDICON_FIFORESET        (1 << 1)
+#define S3C2410_SDICON_CLOCKTYPE        (1 << 0)
+
+#define S3C2410_SDICMDCON_LONGRSP       (1 << 10)
+#define S3C2410_SDICMDCON_WAITRSP       (1 << 9)
+#define S3C2410_SDICMDCON_CMDSTART      (1 << 8)
+#define S3C2410_SDICMDCON_SENDERHOST    (1 << 6)
+#define S3C2410_SDICMDCON_INDEX         (0x3f)
+
+#define S3C2410_SDICMDSTAT_CRCFAIL      (1 << 12)
+#define S3C2410_SDICMDSTAT_CMDSENT      (1 << 11)
+#define S3C2410_SDICMDSTAT_CMDTIMEOUT   (1 << 10)
+#define S3C2410_SDICMDSTAT_RSPFIN       (1 << 9)
+
+#define S3C2440_SDIDCON_DS_WORD         (2 << 22)
+#define S3C2410_SDIDCON_TXAFTERRESP     (1 << 20)
+#define S3C2410_SDIDCON_RXAFTERCMD      (1 << 19)
+#define S3C2410_SDIDCON_BLOCKMODE       (1 << 17)
+#define S3C2410_SDIDCON_WIDEBUS         (1 << 16)
+#define S3C2410_SDIDCON_DMAEN           (1 << 15)
+#define S3C2410_SDIDCON_STOP            (1 << 14)
+#define S3C2440_SDIDCON_DATSTART        (1 << 14)
+
+#define S3C2410_SDIDCON_XFER_RXSTART    (2 << 12)
+#define S3C2410_SDIDCON_XFER_TXSTART    (3 << 12)
+
+#define S3C2410_SDIDCON_BLKNUM_MASK     (0xFFF)
+
+#define S3C2410_SDIDSTA_SDIOIRQDETECT   (1 << 9)
+#define S3C2410_SDIDSTA_FIFOFAIL        (1 << 8)
+#define S3C2410_SDIDSTA_CRCFAIL         (1 << 7)
+#define S3C2410_SDIDSTA_RXCRCFAIL       (1 << 6)
+#define S3C2410_SDIDSTA_DATATIMEOUT     (1 << 5)
+#define S3C2410_SDIDSTA_XFERFINISH      (1 << 4)
+#define S3C2410_SDIDSTA_TXDATAON        (1 << 1)
+#define S3C2410_SDIDSTA_RXDATAON        (1 << 0)
+
+#define S3C2440_SDIFSTA_FIFORESET       (1 << 16)
+#define S3C2440_SDIFSTA_FIFOFAIL        (3 << 14)
+#define S3C2410_SDIFSTA_TFDET           (1 << 13)
+#define S3C2410_SDIFSTA_RFDET           (1 << 12)
+#define S3C2410_SDIFSTA_COUNTMASK       (0x7f)
+
+#define S3C2410_SDIIMSK_RESPONSECRC     (1 << 17)
+#define S3C2410_SDIIMSK_CMDSENT         (1 << 16)
+#define S3C2410_SDIIMSK_CMDTIMEOUT      (1 << 15)
+#define S3C2410_SDIIMSK_RESPONSEND      (1 << 14)
+#define S3C2410_SDIIMSK_SDIOIRQ         (1 << 12)
+#define S3C2410_SDIIMSK_FIFOFAIL        (1 << 11)
+#define S3C2410_SDIIMSK_CRCSTATUS       (1 << 10)
+#define S3C2410_SDIIMSK_DATACRC         (1 << 9)
+#define S3C2410_SDIIMSK_DATATIMEOUT     (1 << 8)
+#define S3C2410_SDIIMSK_DATAFINISH      (1 << 7)
+#define S3C2410_SDIIMSK_TXFIFOHALF      (1 << 4)
+#define S3C2410_SDIIMSK_RXFIFOLAST      (1 << 2)
+#define S3C2410_SDIIMSK_RXFIFOHALF      (1 << 0)
+
 enum dbg_channels {
         dbg_err   = (1 << 0),
         dbg_debug = (1 << 1),