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-rw-r--r--arch/arm/mach-exynos/clock-exynos5.c1645
1 files changed, 0 insertions, 1645 deletions
diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
deleted file mode 100644
index b0ea31fc9fb8..000000000000
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ /dev/null
@@ -1,1645 +0,0 @@
1/*
2 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * Clock support for EXYNOS5 SoCs
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#include <linux/kernel.h>
13#include <linux/err.h>
14#include <linux/io.h>
15#include <linux/syscore_ops.h>
16
17#include <plat/cpu-freq.h>
18#include <plat/clock.h>
19#include <plat/cpu.h>
20#include <plat/pll.h>
21#include <plat/s5p-clock.h>
22#include <plat/clock-clksrc.h>
23#include <plat/pm.h>
24
25#include <mach/map.h>
26#include <mach/regs-clock.h>
27
28#include "common.h"
29
30#ifdef CONFIG_PM_SLEEP
31static struct sleep_save exynos5_clock_save[] = {
32 SAVE_ITEM(EXYNOS5_CLKSRC_MASK_TOP),
33 SAVE_ITEM(EXYNOS5_CLKSRC_MASK_GSCL),
34 SAVE_ITEM(EXYNOS5_CLKSRC_MASK_DISP1_0),
35 SAVE_ITEM(EXYNOS5_CLKSRC_MASK_FSYS),
36 SAVE_ITEM(EXYNOS5_CLKSRC_MASK_MAUDIO),
37 SAVE_ITEM(EXYNOS5_CLKSRC_MASK_PERIC0),
38 SAVE_ITEM(EXYNOS5_CLKSRC_MASK_PERIC1),
39 SAVE_ITEM(EXYNOS5_CLKGATE_IP_GSCL),
40 SAVE_ITEM(EXYNOS5_CLKGATE_IP_DISP1),
41 SAVE_ITEM(EXYNOS5_CLKGATE_IP_MFC),
42 SAVE_ITEM(EXYNOS5_CLKGATE_IP_G3D),
43 SAVE_ITEM(EXYNOS5_CLKGATE_IP_GEN),
44 SAVE_ITEM(EXYNOS5_CLKGATE_IP_FSYS),
45 SAVE_ITEM(EXYNOS5_CLKGATE_IP_PERIC),
46 SAVE_ITEM(EXYNOS5_CLKGATE_IP_PERIS),
47 SAVE_ITEM(EXYNOS5_CLKGATE_BLOCK),
48 SAVE_ITEM(EXYNOS5_CLKDIV_TOP0),
49 SAVE_ITEM(EXYNOS5_CLKDIV_TOP1),
50 SAVE_ITEM(EXYNOS5_CLKDIV_GSCL),
51 SAVE_ITEM(EXYNOS5_CLKDIV_DISP1_0),
52 SAVE_ITEM(EXYNOS5_CLKDIV_GEN),
53 SAVE_ITEM(EXYNOS5_CLKDIV_MAUDIO),
54 SAVE_ITEM(EXYNOS5_CLKDIV_FSYS0),
55 SAVE_ITEM(EXYNOS5_CLKDIV_FSYS1),
56 SAVE_ITEM(EXYNOS5_CLKDIV_FSYS2),
57 SAVE_ITEM(EXYNOS5_CLKDIV_FSYS3),
58 SAVE_ITEM(EXYNOS5_CLKDIV_PERIC0),
59 SAVE_ITEM(EXYNOS5_CLKDIV_PERIC1),
60 SAVE_ITEM(EXYNOS5_CLKDIV_PERIC2),
61 SAVE_ITEM(EXYNOS5_CLKDIV_PERIC3),
62 SAVE_ITEM(EXYNOS5_CLKDIV_PERIC4),
63 SAVE_ITEM(EXYNOS5_CLKDIV_PERIC5),
64 SAVE_ITEM(EXYNOS5_SCLK_DIV_ISP),
65 SAVE_ITEM(EXYNOS5_CLKSRC_TOP0),
66 SAVE_ITEM(EXYNOS5_CLKSRC_TOP1),
67 SAVE_ITEM(EXYNOS5_CLKSRC_TOP2),
68 SAVE_ITEM(EXYNOS5_CLKSRC_TOP3),
69 SAVE_ITEM(EXYNOS5_CLKSRC_GSCL),
70 SAVE_ITEM(EXYNOS5_CLKSRC_DISP1_0),
71 SAVE_ITEM(EXYNOS5_CLKSRC_MAUDIO),
72 SAVE_ITEM(EXYNOS5_CLKSRC_FSYS),
73 SAVE_ITEM(EXYNOS5_CLKSRC_PERIC0),
74 SAVE_ITEM(EXYNOS5_CLKSRC_PERIC1),
75 SAVE_ITEM(EXYNOS5_SCLK_SRC_ISP),
76 SAVE_ITEM(EXYNOS5_EPLL_CON0),
77 SAVE_ITEM(EXYNOS5_EPLL_CON1),
78 SAVE_ITEM(EXYNOS5_EPLL_CON2),
79 SAVE_ITEM(EXYNOS5_VPLL_CON0),
80 SAVE_ITEM(EXYNOS5_VPLL_CON1),
81 SAVE_ITEM(EXYNOS5_VPLL_CON2),
82 SAVE_ITEM(EXYNOS5_PWR_CTRL1),
83 SAVE_ITEM(EXYNOS5_PWR_CTRL2),
84};
85#endif
86
87static struct clk exynos5_clk_sclk_dptxphy = {
88 .name = "sclk_dptx",
89};
90
91static struct clk exynos5_clk_sclk_hdmi24m = {
92 .name = "sclk_hdmi24m",
93 .rate = 24000000,
94};
95
96static struct clk exynos5_clk_sclk_hdmi27m = {
97 .name = "sclk_hdmi27m",
98 .rate = 27000000,
99};
100
101static struct clk exynos5_clk_sclk_hdmiphy = {
102 .name = "sclk_hdmiphy",
103};
104
105static struct clk exynos5_clk_sclk_usbphy = {
106 .name = "sclk_usbphy",
107 .rate = 48000000,
108};
109
110static int exynos5_clksrc_mask_top_ctrl(struct clk *clk, int enable)
111{
112 return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_TOP, clk, enable);
113}
114
115static int exynos5_clksrc_mask_disp1_0_ctrl(struct clk *clk, int enable)
116{
117 return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_DISP1_0, clk, enable);
118}
119
120static int exynos5_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
121{
122 return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_FSYS, clk, enable);
123}
124
125static int exynos5_clksrc_mask_gscl_ctrl(struct clk *clk, int enable)
126{
127 return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_GSCL, clk, enable);
128}
129
130static int exynos5_clksrc_mask_peric0_ctrl(struct clk *clk, int enable)
131{
132 return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC0, clk, enable);
133}
134
135static int exynos5_clksrc_mask_peric1_ctrl(struct clk *clk, int enable)
136{
137 return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC1, clk, enable);
138}
139
140static int exynos5_clk_ip_acp_ctrl(struct clk *clk, int enable)
141{
142 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ACP, clk, enable);
143}
144
145static int exynos5_clk_ip_core_ctrl(struct clk *clk, int enable)
146{
147 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_CORE, clk, enable);
148}
149
150static int exynos5_clk_ip_disp1_ctrl(struct clk *clk, int enable)
151{
152 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_DISP1, clk, enable);
153}
154
155static int exynos5_clk_ip_fsys_ctrl(struct clk *clk, int enable)
156{
157 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_FSYS, clk, enable);
158}
159
160static int exynos5_clk_block_ctrl(struct clk *clk, int enable)
161{
162 return s5p_gatectrl(EXYNOS5_CLKGATE_BLOCK, clk, enable);
163}
164
165static int exynos5_clk_ip_gen_ctrl(struct clk *clk, int enable)
166{
167 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GEN, clk, enable);
168}
169
170static int exynos5_clk_ip_mfc_ctrl(struct clk *clk, int enable)
171{
172 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_MFC, clk, enable);
173}
174
175static int exynos5_clk_ip_peric_ctrl(struct clk *clk, int enable)
176{
177 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_PERIC, clk, enable);
178}
179
180static int exynos5_clk_ip_peris_ctrl(struct clk *clk, int enable)
181{
182 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_PERIS, clk, enable);
183}
184
185static int exynos5_clk_ip_gscl_ctrl(struct clk *clk, int enable)
186{
187 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GSCL, clk, enable);
188}
189
190static int exynos5_clk_ip_isp0_ctrl(struct clk *clk, int enable)
191{
192 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ISP0, clk, enable);
193}
194
195static int exynos5_clk_ip_isp1_ctrl(struct clk *clk, int enable)
196{
197 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ISP1, clk, enable);
198}
199
200static int exynos5_clk_hdmiphy_ctrl(struct clk *clk, int enable)
201{
202 return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
203}
204
205/* Core list of CMU_CPU side */
206
207static struct clksrc_clk exynos5_clk_mout_apll = {
208 .clk = {
209 .name = "mout_apll",
210 },
211 .sources = &clk_src_apll,
212 .reg_src = { .reg = EXYNOS5_CLKSRC_CPU, .shift = 0, .size = 1 },
213};
214
215static struct clksrc_clk exynos5_clk_sclk_apll = {
216 .clk = {
217 .name = "sclk_apll",
218 .parent = &exynos5_clk_mout_apll.clk,
219 },
220 .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 24, .size = 3 },
221};
222
223static struct clksrc_clk exynos5_clk_mout_bpll_fout = {
224 .clk = {
225 .name = "mout_bpll_fout",
226 },
227 .sources = &clk_src_bpll_fout,
228 .reg_src = { .reg = EXYNOS5_PLL_DIV2_SEL, .shift = 0, .size = 1 },
229};
230
231static struct clk *exynos5_clk_src_bpll_list[] = {
232 [0] = &clk_fin_bpll,
233 [1] = &exynos5_clk_mout_bpll_fout.clk,
234};
235
236static struct clksrc_sources exynos5_clk_src_bpll = {
237 .sources = exynos5_clk_src_bpll_list,
238 .nr_sources = ARRAY_SIZE(exynos5_clk_src_bpll_list),
239};
240
241static struct clksrc_clk exynos5_clk_mout_bpll = {
242 .clk = {
243 .name = "mout_bpll",
244 },
245 .sources = &exynos5_clk_src_bpll,
246 .reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 0, .size = 1 },
247};
248
249static struct clk *exynos5_clk_src_bpll_user_list[] = {
250 [0] = &clk_fin_mpll,
251 [1] = &exynos5_clk_mout_bpll.clk,
252};
253
254static struct clksrc_sources exynos5_clk_src_bpll_user = {
255 .sources = exynos5_clk_src_bpll_user_list,
256 .nr_sources = ARRAY_SIZE(exynos5_clk_src_bpll_user_list),
257};
258
259static struct clksrc_clk exynos5_clk_mout_bpll_user = {
260 .clk = {
261 .name = "mout_bpll_user",
262 },
263 .sources = &exynos5_clk_src_bpll_user,
264 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 24, .size = 1 },
265};
266
267static struct clksrc_clk exynos5_clk_mout_cpll = {
268 .clk = {
269 .name = "mout_cpll",
270 },
271 .sources = &clk_src_cpll,
272 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 8, .size = 1 },
273};
274
275static struct clksrc_clk exynos5_clk_mout_epll = {
276 .clk = {
277 .name = "mout_epll",
278 },
279 .sources = &clk_src_epll,
280 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 12, .size = 1 },
281};
282
283static struct clksrc_clk exynos5_clk_mout_mpll_fout = {
284 .clk = {
285 .name = "mout_mpll_fout",
286 },
287 .sources = &clk_src_mpll_fout,
288 .reg_src = { .reg = EXYNOS5_PLL_DIV2_SEL, .shift = 4, .size = 1 },
289};
290
291static struct clk *exynos5_clk_src_mpll_list[] = {
292 [0] = &clk_fin_mpll,
293 [1] = &exynos5_clk_mout_mpll_fout.clk,
294};
295
296static struct clksrc_sources exynos5_clk_src_mpll = {
297 .sources = exynos5_clk_src_mpll_list,
298 .nr_sources = ARRAY_SIZE(exynos5_clk_src_mpll_list),
299};
300
301static struct clksrc_clk exynos5_clk_mout_mpll = {
302 .clk = {
303 .name = "mout_mpll",
304 },
305 .sources = &exynos5_clk_src_mpll,
306 .reg_src = { .reg = EXYNOS5_CLKSRC_CORE1, .shift = 8, .size = 1 },
307};
308
309static struct clk *exynos_clkset_vpllsrc_list[] = {
310 [0] = &clk_fin_vpll,
311 [1] = &exynos5_clk_sclk_hdmi27m,
312};
313
314static struct clksrc_sources exynos5_clkset_vpllsrc = {
315 .sources = exynos_clkset_vpllsrc_list,
316 .nr_sources = ARRAY_SIZE(exynos_clkset_vpllsrc_list),
317};
318
319static struct clksrc_clk exynos5_clk_vpllsrc = {
320 .clk = {
321 .name = "vpll_src",
322 .enable = exynos5_clksrc_mask_top_ctrl,
323 .ctrlbit = (1 << 0),
324 },
325 .sources = &exynos5_clkset_vpllsrc,
326 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 0, .size = 1 },
327};
328
329static struct clk *exynos5_clkset_sclk_vpll_list[] = {
330 [0] = &exynos5_clk_vpllsrc.clk,
331 [1] = &clk_fout_vpll,
332};
333
334static struct clksrc_sources exynos5_clkset_sclk_vpll = {
335 .sources = exynos5_clkset_sclk_vpll_list,
336 .nr_sources = ARRAY_SIZE(exynos5_clkset_sclk_vpll_list),
337};
338
339static struct clksrc_clk exynos5_clk_sclk_vpll = {
340 .clk = {
341 .name = "sclk_vpll",
342 },
343 .sources = &exynos5_clkset_sclk_vpll,
344 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 16, .size = 1 },
345};
346
347static struct clksrc_clk exynos5_clk_sclk_pixel = {
348 .clk = {
349 .name = "sclk_pixel",
350 .parent = &exynos5_clk_sclk_vpll.clk,
351 },
352 .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 28, .size = 4 },
353};
354
355static struct clk *exynos5_clkset_sclk_hdmi_list[] = {
356 [0] = &exynos5_clk_sclk_pixel.clk,
357 [1] = &exynos5_clk_sclk_hdmiphy,
358};
359
360static struct clksrc_sources exynos5_clkset_sclk_hdmi = {
361 .sources = exynos5_clkset_sclk_hdmi_list,
362 .nr_sources = ARRAY_SIZE(exynos5_clkset_sclk_hdmi_list),
363};
364
365static struct clksrc_clk exynos5_clk_sclk_hdmi = {
366 .clk = {
367 .name = "sclk_hdmi",
368 .enable = exynos5_clksrc_mask_disp1_0_ctrl,
369 .ctrlbit = (1 << 20),
370 },
371 .sources = &exynos5_clkset_sclk_hdmi,
372 .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 20, .size = 1 },
373};
374
375static struct clksrc_clk *exynos5_sclk_tv[] = {
376 &exynos5_clk_sclk_pixel,
377 &exynos5_clk_sclk_hdmi,
378};
379
380static struct clk *exynos5_clk_src_mpll_user_list[] = {
381 [0] = &clk_fin_mpll,
382 [1] = &exynos5_clk_mout_mpll.clk,
383};
384
385static struct clksrc_sources exynos5_clk_src_mpll_user = {
386 .sources = exynos5_clk_src_mpll_user_list,
387 .nr_sources = ARRAY_SIZE(exynos5_clk_src_mpll_user_list),
388};
389
390static struct clksrc_clk exynos5_clk_mout_mpll_user = {
391 .clk = {
392 .name = "mout_mpll_user",
393 },
394 .sources = &exynos5_clk_src_mpll_user,
395 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 20, .size = 1 },
396};
397
398static struct clk *exynos5_clkset_mout_cpu_list[] = {
399 [0] = &exynos5_clk_mout_apll.clk,
400 [1] = &exynos5_clk_mout_mpll.clk,
401};
402
403static struct clksrc_sources exynos5_clkset_mout_cpu = {
404 .sources = exynos5_clkset_mout_cpu_list,
405 .nr_sources = ARRAY_SIZE(exynos5_clkset_mout_cpu_list),
406};
407
408static struct clksrc_clk exynos5_clk_mout_cpu = {
409 .clk = {
410 .name = "mout_cpu",
411 },
412 .sources = &exynos5_clkset_mout_cpu,
413 .reg_src = { .reg = EXYNOS5_CLKSRC_CPU, .shift = 16, .size = 1 },
414};
415
416static struct clksrc_clk exynos5_clk_dout_armclk = {
417 .clk = {
418 .name = "dout_armclk",
419 .parent = &exynos5_clk_mout_cpu.clk,
420 },
421 .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 0, .size = 3 },
422};
423
424static struct clksrc_clk exynos5_clk_dout_arm2clk = {
425 .clk = {
426 .name = "dout_arm2clk",
427 .parent = &exynos5_clk_dout_armclk.clk,
428 },
429 .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 28, .size = 3 },
430};
431
432static struct clk exynos5_clk_armclk = {
433 .name = "armclk",
434 .parent = &exynos5_clk_dout_arm2clk.clk,
435};
436
437/* Core list of CMU_CDREX side */
438
439static struct clk *exynos5_clkset_cdrex_list[] = {
440 [0] = &exynos5_clk_mout_mpll.clk,
441 [1] = &exynos5_clk_mout_bpll.clk,
442};
443
444static struct clksrc_sources exynos5_clkset_cdrex = {
445 .sources = exynos5_clkset_cdrex_list,
446 .nr_sources = ARRAY_SIZE(exynos5_clkset_cdrex_list),
447};
448
449static struct clksrc_clk exynos5_clk_cdrex = {
450 .clk = {
451 .name = "clk_cdrex",
452 },
453 .sources = &exynos5_clkset_cdrex,
454 .reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 4, .size = 1 },
455 .reg_div = { .reg = EXYNOS5_CLKDIV_CDREX, .shift = 16, .size = 3 },
456};
457
458static struct clksrc_clk exynos5_clk_aclk_acp = {
459 .clk = {
460 .name = "aclk_acp",
461 .parent = &exynos5_clk_mout_mpll.clk,
462 },
463 .reg_div = { .reg = EXYNOS5_CLKDIV_ACP, .shift = 0, .size = 3 },
464};
465
466static struct clksrc_clk exynos5_clk_pclk_acp = {
467 .clk = {
468 .name = "pclk_acp",
469 .parent = &exynos5_clk_aclk_acp.clk,
470 },
471 .reg_div = { .reg = EXYNOS5_CLKDIV_ACP, .shift = 4, .size = 3 },
472};
473
474/* Core list of CMU_TOP side */
475
476static struct clk *exynos5_clkset_aclk_top_list[] = {
477 [0] = &exynos5_clk_mout_mpll_user.clk,
478 [1] = &exynos5_clk_mout_bpll_user.clk,
479};
480
481static struct clksrc_sources exynos5_clkset_aclk = {
482 .sources = exynos5_clkset_aclk_top_list,
483 .nr_sources = ARRAY_SIZE(exynos5_clkset_aclk_top_list),
484};
485
486static struct clksrc_clk exynos5_clk_aclk_400 = {
487 .clk = {
488 .name = "aclk_400",
489 },
490 .sources = &exynos5_clkset_aclk,
491 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 20, .size = 1 },
492 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 24, .size = 3 },
493};
494
495static struct clk *exynos5_clkset_aclk_333_166_list[] = {
496 [0] = &exynos5_clk_mout_cpll.clk,
497 [1] = &exynos5_clk_mout_mpll_user.clk,
498};
499
500static struct clksrc_sources exynos5_clkset_aclk_333_166 = {
501 .sources = exynos5_clkset_aclk_333_166_list,
502 .nr_sources = ARRAY_SIZE(exynos5_clkset_aclk_333_166_list),
503};
504
505static struct clksrc_clk exynos5_clk_aclk_333 = {
506 .clk = {
507 .name = "aclk_333",
508 },
509 .sources = &exynos5_clkset_aclk_333_166,
510 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 16, .size = 1 },
511 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 20, .size = 3 },
512};
513
514static struct clksrc_clk exynos5_clk_aclk_166 = {
515 .clk = {
516 .name = "aclk_166",
517 },
518 .sources = &exynos5_clkset_aclk_333_166,
519 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 8, .size = 1 },
520 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 8, .size = 3 },
521};
522
523static struct clksrc_clk exynos5_clk_aclk_266 = {
524 .clk = {
525 .name = "aclk_266",
526 .parent = &exynos5_clk_mout_mpll_user.clk,
527 },
528 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 16, .size = 3 },
529};
530
531static struct clksrc_clk exynos5_clk_aclk_200 = {
532 .clk = {
533 .name = "aclk_200",
534 },
535 .sources = &exynos5_clkset_aclk,
536 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 12, .size = 1 },
537 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 12, .size = 3 },
538};
539
540static struct clksrc_clk exynos5_clk_aclk_66_pre = {
541 .clk = {
542 .name = "aclk_66_pre",
543 .parent = &exynos5_clk_mout_mpll_user.clk,
544 },
545 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP1, .shift = 24, .size = 3 },
546};
547
548static struct clksrc_clk exynos5_clk_aclk_66 = {
549 .clk = {
550 .name = "aclk_66",
551 .parent = &exynos5_clk_aclk_66_pre.clk,
552 },
553 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 0, .size = 3 },
554};
555
556static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl_mid = {
557 .clk = {
558 .name = "mout_aclk_300_gscl_mid",
559 },
560 .sources = &exynos5_clkset_aclk,
561 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 24, .size = 1 },
562};
563
564static struct clk *exynos5_clkset_aclk_300_mid1_list[] = {
565 [0] = &exynos5_clk_sclk_vpll.clk,
566 [1] = &exynos5_clk_mout_cpll.clk,
567};
568
569static struct clksrc_sources exynos5_clkset_aclk_300_gscl_mid1 = {
570 .sources = exynos5_clkset_aclk_300_mid1_list,
571 .nr_sources = ARRAY_SIZE(exynos5_clkset_aclk_300_mid1_list),
572};
573
574static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl_mid1 = {
575 .clk = {
576 .name = "mout_aclk_300_gscl_mid1",
577 },
578 .sources = &exynos5_clkset_aclk_300_gscl_mid1,
579 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP1, .shift = 12, .size = 1 },
580};
581
582static struct clk *exynos5_clkset_aclk_300_gscl_list[] = {
583 [0] = &exynos5_clk_mout_aclk_300_gscl_mid.clk,
584 [1] = &exynos5_clk_mout_aclk_300_gscl_mid1.clk,
585};
586
587static struct clksrc_sources exynos5_clkset_aclk_300_gscl = {
588 .sources = exynos5_clkset_aclk_300_gscl_list,
589 .nr_sources = ARRAY_SIZE(exynos5_clkset_aclk_300_gscl_list),
590};
591
592static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl = {
593 .clk = {
594 .name = "mout_aclk_300_gscl",
595 },
596 .sources = &exynos5_clkset_aclk_300_gscl,
597 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 25, .size = 1 },
598};
599
600static struct clk *exynos5_clk_src_gscl_300_list[] = {
601 [0] = &clk_ext_xtal_mux,
602 [1] = &exynos5_clk_mout_aclk_300_gscl.clk,
603};
604
605static struct clksrc_sources exynos5_clk_src_gscl_300 = {
606 .sources = exynos5_clk_src_gscl_300_list,
607 .nr_sources = ARRAY_SIZE(exynos5_clk_src_gscl_300_list),
608};
609
610static struct clksrc_clk exynos5_clk_aclk_300_gscl = {
611 .clk = {
612 .name = "aclk_300_gscl",
613 },
614 .sources = &exynos5_clk_src_gscl_300,
615 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 10, .size = 1 },
616};
617
618static struct clk exynos5_init_clocks_off[] = {
619 {
620 .name = "timers",
621 .parent = &exynos5_clk_aclk_66.clk,
622 .enable = exynos5_clk_ip_peric_ctrl,
623 .ctrlbit = (1 << 24),
624 }, {
625 .name = "tmu_apbif",
626 .parent = &exynos5_clk_aclk_66.clk,
627 .enable = exynos5_clk_ip_peris_ctrl,
628 .ctrlbit = (1 << 21),
629 }, {
630 .name = "rtc",
631 .parent = &exynos5_clk_aclk_66.clk,
632 .enable = exynos5_clk_ip_peris_ctrl,
633 .ctrlbit = (1 << 20),
634 }, {
635 .name = "watchdog",
636 .parent = &exynos5_clk_aclk_66.clk,
637 .enable = exynos5_clk_ip_peris_ctrl,
638 .ctrlbit = (1 << 19),
639 }, {
640 .name = "biu", /* bus interface unit clock */
641 .devname = "dw_mmc.0",
642 .parent = &exynos5_clk_aclk_200.clk,
643 .enable = exynos5_clk_ip_fsys_ctrl,
644 .ctrlbit = (1 << 12),
645 }, {
646 .name = "biu",
647 .devname = "dw_mmc.1",
648 .parent = &exynos5_clk_aclk_200.clk,
649 .enable = exynos5_clk_ip_fsys_ctrl,
650 .ctrlbit = (1 << 13),
651 }, {
652 .name = "biu",
653 .devname = "dw_mmc.2",
654 .parent = &exynos5_clk_aclk_200.clk,
655 .enable = exynos5_clk_ip_fsys_ctrl,
656 .ctrlbit = (1 << 14),
657 }, {
658 .name = "biu",
659 .devname = "dw_mmc.3",
660 .parent = &exynos5_clk_aclk_200.clk,
661 .enable = exynos5_clk_ip_fsys_ctrl,
662 .ctrlbit = (1 << 15),
663 }, {
664 .name = "sata",
665 .devname = "exynos5-sata",
666 .parent = &exynos5_clk_aclk_200.clk,
667 .enable = exynos5_clk_ip_fsys_ctrl,
668 .ctrlbit = (1 << 6),
669 }, {
670 .name = "sata-phy",
671 .devname = "exynos5-sata-phy",
672 .parent = &exynos5_clk_aclk_200.clk,
673 .enable = exynos5_clk_ip_fsys_ctrl,
674 .ctrlbit = (1 << 24),
675 }, {
676 .name = "i2c",
677 .devname = "exynos5-sata-phy-i2c",
678 .parent = &exynos5_clk_aclk_200.clk,
679 .enable = exynos5_clk_ip_fsys_ctrl,
680 .ctrlbit = (1 << 25),
681 }, {
682 .name = "mfc",
683 .devname = "s5p-mfc-v6",
684 .enable = exynos5_clk_ip_mfc_ctrl,
685 .ctrlbit = (1 << 0),
686 }, {
687 .name = "hdmi",
688 .devname = "exynos5-hdmi",
689 .enable = exynos5_clk_ip_disp1_ctrl,
690 .ctrlbit = (1 << 6),
691 }, {
692 .name = "hdmiphy",
693 .devname = "exynos5-hdmi",
694 .enable = exynos5_clk_hdmiphy_ctrl,
695 .ctrlbit = (1 << 0),
696 }, {
697 .name = "mixer",
698 .devname = "exynos5-mixer",
699 .enable = exynos5_clk_ip_disp1_ctrl,
700 .ctrlbit = (1 << 5),
701 }, {
702 .name = "dp",
703 .devname = "exynos-dp",
704 .enable = exynos5_clk_ip_disp1_ctrl,
705 .ctrlbit = (1 << 4),
706 }, {
707 .name = "jpeg",
708 .enable = exynos5_clk_ip_gen_ctrl,
709 .ctrlbit = (1 << 2),
710 }, {
711 .name = "dsim0",
712 .enable = exynos5_clk_ip_disp1_ctrl,
713 .ctrlbit = (1 << 3),
714 }, {
715 .name = "iis",
716 .devname = "samsung-i2s.1",
717 .enable = exynos5_clk_ip_peric_ctrl,
718 .ctrlbit = (1 << 20),
719 }, {
720 .name = "iis",
721 .devname = "samsung-i2s.2",
722 .enable = exynos5_clk_ip_peric_ctrl,
723 .ctrlbit = (1 << 21),
724 }, {
725 .name = "pcm",
726 .devname = "samsung-pcm.1",
727 .enable = exynos5_clk_ip_peric_ctrl,
728 .ctrlbit = (1 << 22),
729 }, {
730 .name = "pcm",
731 .devname = "samsung-pcm.2",
732 .enable = exynos5_clk_ip_peric_ctrl,
733 .ctrlbit = (1 << 23),
734 }, {
735 .name = "spdif",
736 .devname = "samsung-spdif",
737 .enable = exynos5_clk_ip_peric_ctrl,
738 .ctrlbit = (1 << 26),
739 }, {
740 .name = "ac97",
741 .devname = "samsung-ac97",
742 .enable = exynos5_clk_ip_peric_ctrl,
743 .ctrlbit = (1 << 27),
744 }, {
745 .name = "usbhost",
746 .enable = exynos5_clk_ip_fsys_ctrl ,
747 .ctrlbit = (1 << 18),
748 }, {
749 .name = "usbotg",
750 .enable = exynos5_clk_ip_fsys_ctrl,
751 .ctrlbit = (1 << 7),
752 }, {
753 .name = "nfcon",
754 .enable = exynos5_clk_ip_fsys_ctrl,
755 .ctrlbit = (1 << 22),
756 }, {
757 .name = "iop",
758 .enable = exynos5_clk_ip_fsys_ctrl,
759 .ctrlbit = ((1 << 30) | (1 << 26) | (1 << 23)),
760 }, {
761 .name = "core_iop",
762 .enable = exynos5_clk_ip_core_ctrl,
763 .ctrlbit = ((1 << 21) | (1 << 3)),
764 }, {
765 .name = "mcu_iop",
766 .enable = exynos5_clk_ip_fsys_ctrl,
767 .ctrlbit = (1 << 0),
768 }, {
769 .name = "i2c",
770 .devname = "s3c2440-i2c.0",
771 .parent = &exynos5_clk_aclk_66.clk,
772 .enable = exynos5_clk_ip_peric_ctrl,
773 .ctrlbit = (1 << 6),
774 }, {
775 .name = "i2c",
776 .devname = "s3c2440-i2c.1",
777 .parent = &exynos5_clk_aclk_66.clk,
778 .enable = exynos5_clk_ip_peric_ctrl,
779 .ctrlbit = (1 << 7),
780 }, {
781 .name = "i2c",
782 .devname = "s3c2440-i2c.2",
783 .parent = &exynos5_clk_aclk_66.clk,
784 .enable = exynos5_clk_ip_peric_ctrl,
785 .ctrlbit = (1 << 8),
786 }, {
787 .name = "i2c",
788 .devname = "s3c2440-i2c.3",
789 .parent = &exynos5_clk_aclk_66.clk,
790 .enable = exynos5_clk_ip_peric_ctrl,
791 .ctrlbit = (1 << 9),
792 }, {
793 .name = "i2c",
794 .devname = "s3c2440-i2c.4",
795 .parent = &exynos5_clk_aclk_66.clk,
796 .enable = exynos5_clk_ip_peric_ctrl,
797 .ctrlbit = (1 << 10),
798 }, {
799 .name = "i2c",
800 .devname = "s3c2440-i2c.5",
801 .parent = &exynos5_clk_aclk_66.clk,
802 .enable = exynos5_clk_ip_peric_ctrl,
803 .ctrlbit = (1 << 11),
804 }, {
805 .name = "i2c",
806 .devname = "s3c2440-i2c.6",
807 .parent = &exynos5_clk_aclk_66.clk,
808 .enable = exynos5_clk_ip_peric_ctrl,
809 .ctrlbit = (1 << 12),
810 }, {
811 .name = "i2c",
812 .devname = "s3c2440-i2c.7",
813 .parent = &exynos5_clk_aclk_66.clk,
814 .enable = exynos5_clk_ip_peric_ctrl,
815 .ctrlbit = (1 << 13),
816 }, {
817 .name = "i2c",
818 .devname = "s3c2440-hdmiphy-i2c",
819 .parent = &exynos5_clk_aclk_66.clk,
820 .enable = exynos5_clk_ip_peric_ctrl,
821 .ctrlbit = (1 << 14),
822 }, {
823 .name = "spi",
824 .devname = "exynos4210-spi.0",
825 .parent = &exynos5_clk_aclk_66.clk,
826 .enable = exynos5_clk_ip_peric_ctrl,
827 .ctrlbit = (1 << 16),
828 }, {
829 .name = "spi",
830 .devname = "exynos4210-spi.1",
831 .parent = &exynos5_clk_aclk_66.clk,
832 .enable = exynos5_clk_ip_peric_ctrl,
833 .ctrlbit = (1 << 17),
834 }, {
835 .name = "spi",
836 .devname = "exynos4210-spi.2",
837 .parent = &exynos5_clk_aclk_66.clk,
838 .enable = exynos5_clk_ip_peric_ctrl,
839 .ctrlbit = (1 << 18),
840 }, {
841 .name = "gscl",
842 .devname = "exynos-gsc.0",
843 .enable = exynos5_clk_ip_gscl_ctrl,
844 .ctrlbit = (1 << 0),
845 }, {
846 .name = "gscl",
847 .devname = "exynos-gsc.1",
848 .enable = exynos5_clk_ip_gscl_ctrl,
849 .ctrlbit = (1 << 1),
850 }, {
851 .name = "gscl",
852 .devname = "exynos-gsc.2",
853 .enable = exynos5_clk_ip_gscl_ctrl,
854 .ctrlbit = (1 << 2),
855 }, {
856 .name = "gscl",
857 .devname = "exynos-gsc.3",
858 .enable = exynos5_clk_ip_gscl_ctrl,
859 .ctrlbit = (1 << 3),
860 }, {
861 .name = "sysmmu",
862 .devname = "exynos-sysmmu.1",
863 .enable = &exynos5_clk_ip_mfc_ctrl,
864 .ctrlbit = (1 << 1),
865 }, {
866 .name = "sysmmu",
867 .devname = "exynos-sysmmu.0",
868 .enable = &exynos5_clk_ip_mfc_ctrl,
869 .ctrlbit = (1 << 2),
870 }, {
871 .name = "sysmmu",
872 .devname = "exynos-sysmmu.2",
873 .enable = &exynos5_clk_ip_disp1_ctrl,
874 .ctrlbit = (1 << 9)
875 }, {
876 .name = "sysmmu",
877 .devname = "exynos-sysmmu.3",
878 .enable = &exynos5_clk_ip_gen_ctrl,
879 .ctrlbit = (1 << 7),
880 }, {
881 .name = "sysmmu",
882 .devname = "exynos-sysmmu.4",
883 .enable = &exynos5_clk_ip_gen_ctrl,
884 .ctrlbit = (1 << 6)
885 }, {
886 .name = "sysmmu",
887 .devname = "exynos-sysmmu.5",
888 .enable = &exynos5_clk_ip_gscl_ctrl,
889 .ctrlbit = (1 << 7),
890 }, {
891 .name = "sysmmu",
892 .devname = "exynos-sysmmu.6",
893 .enable = &exynos5_clk_ip_gscl_ctrl,
894 .ctrlbit = (1 << 8),
895 }, {
896 .name = "sysmmu",
897 .devname = "exynos-sysmmu.7",
898 .enable = &exynos5_clk_ip_gscl_ctrl,
899 .ctrlbit = (1 << 9),
900 }, {
901 .name = "sysmmu",
902 .devname = "exynos-sysmmu.8",
903 .enable = &exynos5_clk_ip_gscl_ctrl,
904 .ctrlbit = (1 << 10),
905 }, {
906 .name = "sysmmu",
907 .devname = "exynos-sysmmu.9",
908 .enable = &exynos5_clk_ip_isp0_ctrl,
909 .ctrlbit = (0x3F << 8),
910 }, {
911 .name = "sysmmu",
912 .devname = "exynos-sysmmu.10",
913 .enable = &exynos5_clk_ip_isp1_ctrl,
914 .ctrlbit = (0xF << 4),
915 }, {
916 .name = "sysmmu",
917 .devname = "exynos-sysmmu.11",
918 .enable = &exynos5_clk_ip_disp1_ctrl,
919 .ctrlbit = (1 << 8)
920 }, {
921 .name = "sysmmu",
922 .devname = "exynos-sysmmu.12",
923 .enable = &exynos5_clk_ip_gscl_ctrl,
924 .ctrlbit = (1 << 11),
925 }, {
926 .name = "sysmmu",
927 .devname = "exynos-sysmmu.13",
928 .enable = &exynos5_clk_ip_gscl_ctrl,
929 .ctrlbit = (1 << 12),
930 }, {
931 .name = "sysmmu",
932 .devname = "exynos-sysmmu.14",
933 .enable = &exynos5_clk_ip_acp_ctrl,
934 .ctrlbit = (1 << 7)
935 }
936};
937
938static struct clk exynos5_init_clocks_on[] = {
939 {
940 .name = "uart",
941 .devname = "s5pv210-uart.0",
942 .enable = exynos5_clk_ip_peric_ctrl,
943 .ctrlbit = (1 << 0),
944 }, {
945 .name = "uart",
946 .devname = "s5pv210-uart.1",
947 .enable = exynos5_clk_ip_peric_ctrl,
948 .ctrlbit = (1 << 1),
949 }, {
950 .name = "uart",
951 .devname = "s5pv210-uart.2",
952 .enable = exynos5_clk_ip_peric_ctrl,
953 .ctrlbit = (1 << 2),
954 }, {
955 .name = "uart",
956 .devname = "s5pv210-uart.3",
957 .enable = exynos5_clk_ip_peric_ctrl,
958 .ctrlbit = (1 << 3),
959 }, {
960 .name = "uart",
961 .devname = "s5pv210-uart.4",
962 .enable = exynos5_clk_ip_peric_ctrl,
963 .ctrlbit = (1 << 4),
964 }, {
965 .name = "uart",
966 .devname = "s5pv210-uart.5",
967 .enable = exynos5_clk_ip_peric_ctrl,
968 .ctrlbit = (1 << 5),
969 }
970};
971
972static struct clk exynos5_clk_pdma0 = {
973 .name = "dma",
974 .devname = "dma-pl330.0",
975 .enable = exynos5_clk_ip_fsys_ctrl,
976 .ctrlbit = (1 << 1),
977};
978
979static struct clk exynos5_clk_pdma1 = {
980 .name = "dma",
981 .devname = "dma-pl330.1",
982 .enable = exynos5_clk_ip_fsys_ctrl,
983 .ctrlbit = (1 << 2),
984};
985
986static struct clk exynos5_clk_mdma1 = {
987 .name = "dma",
988 .devname = "dma-pl330.2",
989 .enable = exynos5_clk_ip_gen_ctrl,
990 .ctrlbit = (1 << 4),
991};
992
993static struct clk exynos5_clk_fimd1 = {
994 .name = "fimd",
995 .devname = "exynos5-fb.1",
996 .enable = exynos5_clk_ip_disp1_ctrl,
997 .ctrlbit = (1 << 0),
998};
999
1000static struct clk *exynos5_clkset_group_list[] = {
1001 [0] = &clk_ext_xtal_mux,
1002 [1] = NULL,
1003 [2] = &exynos5_clk_sclk_hdmi24m,
1004 [3] = &exynos5_clk_sclk_dptxphy,
1005 [4] = &exynos5_clk_sclk_usbphy,
1006 [5] = &exynos5_clk_sclk_hdmiphy,
1007 [6] = &exynos5_clk_mout_mpll_user.clk,
1008 [7] = &exynos5_clk_mout_epll.clk,
1009 [8] = &exynos5_clk_sclk_vpll.clk,
1010 [9] = &exynos5_clk_mout_cpll.clk,
1011};
1012
1013static struct clksrc_sources exynos5_clkset_group = {
1014 .sources = exynos5_clkset_group_list,
1015 .nr_sources = ARRAY_SIZE(exynos5_clkset_group_list),
1016};
1017
1018/* Possible clock sources for aclk_266_gscl_sub Mux */
1019static struct clk *clk_src_gscl_266_list[] = {
1020 [0] = &clk_ext_xtal_mux,
1021 [1] = &exynos5_clk_aclk_266.clk,
1022};
1023
1024static struct clksrc_sources clk_src_gscl_266 = {
1025 .sources = clk_src_gscl_266_list,
1026 .nr_sources = ARRAY_SIZE(clk_src_gscl_266_list),
1027};
1028
1029static struct clksrc_clk exynos5_clk_dout_mmc0 = {
1030 .clk = {
1031 .name = "dout_mmc0",
1032 },
1033 .sources = &exynos5_clkset_group,
1034 .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 0, .size = 4 },
1035 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 0, .size = 4 },
1036};
1037
1038static struct clksrc_clk exynos5_clk_dout_mmc1 = {
1039 .clk = {
1040 .name = "dout_mmc1",
1041 },
1042 .sources = &exynos5_clkset_group,
1043 .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 4, .size = 4 },
1044 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 16, .size = 4 },
1045};
1046
1047static struct clksrc_clk exynos5_clk_dout_mmc2 = {
1048 .clk = {
1049 .name = "dout_mmc2",
1050 },
1051 .sources = &exynos5_clkset_group,
1052 .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 8, .size = 4 },
1053 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 0, .size = 4 },
1054};
1055
1056static struct clksrc_clk exynos5_clk_dout_mmc3 = {
1057 .clk = {
1058 .name = "dout_mmc3",
1059 },
1060 .sources = &exynos5_clkset_group,
1061 .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 12, .size = 4 },
1062 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 16, .size = 4 },
1063};
1064
1065static struct clksrc_clk exynos5_clk_dout_mmc4 = {
1066 .clk = {
1067 .name = "dout_mmc4",
1068 },
1069 .sources = &exynos5_clkset_group,
1070 .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 16, .size = 4 },
1071 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS3, .shift = 0, .size = 4 },
1072};
1073
1074static struct clksrc_clk exynos5_clk_sclk_uart0 = {
1075 .clk = {
1076 .name = "uclk1",
1077 .devname = "exynos4210-uart.0",
1078 .enable = exynos5_clksrc_mask_peric0_ctrl,
1079 .ctrlbit = (1 << 0),
1080 },
1081 .sources = &exynos5_clkset_group,
1082 .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 0, .size = 4 },
1083 .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 0, .size = 4 },
1084};
1085
1086static struct clksrc_clk exynos5_clk_sclk_uart1 = {
1087 .clk = {
1088 .name = "uclk1",
1089 .devname = "exynos4210-uart.1",
1090 .enable = exynos5_clksrc_mask_peric0_ctrl,
1091 .ctrlbit = (1 << 4),
1092 },
1093 .sources = &exynos5_clkset_group,
1094 .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 4, .size = 4 },
1095 .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 4, .size = 4 },
1096};
1097
1098static struct clksrc_clk exynos5_clk_sclk_uart2 = {
1099 .clk = {
1100 .name = "uclk1",
1101 .devname = "exynos4210-uart.2",
1102 .enable = exynos5_clksrc_mask_peric0_ctrl,
1103 .ctrlbit = (1 << 8),
1104 },
1105 .sources = &exynos5_clkset_group,
1106 .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 8, .size = 4 },
1107 .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 8, .size = 4 },
1108};
1109
1110static struct clksrc_clk exynos5_clk_sclk_uart3 = {
1111 .clk = {
1112 .name = "uclk1",
1113 .devname = "exynos4210-uart.3",
1114 .enable = exynos5_clksrc_mask_peric0_ctrl,
1115 .ctrlbit = (1 << 12),
1116 },
1117 .sources = &exynos5_clkset_group,
1118 .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 12, .size = 4 },
1119 .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 12, .size = 4 },
1120};
1121
1122static struct clksrc_clk exynos5_clk_sclk_mmc0 = {
1123 .clk = {
1124 .name = "ciu", /* card interface unit clock */
1125 .devname = "dw_mmc.0",
1126 .parent = &exynos5_clk_dout_mmc0.clk,
1127 .enable = exynos5_clksrc_mask_fsys_ctrl,
1128 .ctrlbit = (1 << 0),
1129 },
1130 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 8, .size = 8 },
1131};
1132
1133static struct clksrc_clk exynos5_clk_sclk_mmc1 = {
1134 .clk = {
1135 .name = "ciu",
1136 .devname = "dw_mmc.1",
1137 .parent = &exynos5_clk_dout_mmc1.clk,
1138 .enable = exynos5_clksrc_mask_fsys_ctrl,
1139 .ctrlbit = (1 << 4),
1140 },
1141 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 24, .size = 8 },
1142};
1143
1144static struct clksrc_clk exynos5_clk_sclk_mmc2 = {
1145 .clk = {
1146 .name = "ciu",
1147 .devname = "dw_mmc.2",
1148 .parent = &exynos5_clk_dout_mmc2.clk,
1149 .enable = exynos5_clksrc_mask_fsys_ctrl,
1150 .ctrlbit = (1 << 8),
1151 },
1152 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 8, .size = 8 },
1153};
1154
1155static struct clksrc_clk exynos5_clk_sclk_mmc3 = {
1156 .clk = {
1157 .name = "ciu",
1158 .devname = "dw_mmc.3",
1159 .parent = &exynos5_clk_dout_mmc3.clk,
1160 .enable = exynos5_clksrc_mask_fsys_ctrl,
1161 .ctrlbit = (1 << 12),
1162 },
1163 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 24, .size = 8 },
1164};
1165
1166static struct clksrc_clk exynos5_clk_mdout_spi0 = {
1167 .clk = {
1168 .name = "mdout_spi",
1169 .devname = "exynos4210-spi.0",
1170 },
1171 .sources = &exynos5_clkset_group,
1172 .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 16, .size = 4 },
1173 .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 0, .size = 4 },
1174};
1175
1176static struct clksrc_clk exynos5_clk_mdout_spi1 = {
1177 .clk = {
1178 .name = "mdout_spi",
1179 .devname = "exynos4210-spi.1",
1180 },
1181 .sources = &exynos5_clkset_group,
1182 .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 20, .size = 4 },
1183 .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 16, .size = 4 },
1184};
1185
1186static struct clksrc_clk exynos5_clk_mdout_spi2 = {
1187 .clk = {
1188 .name = "mdout_spi",
1189 .devname = "exynos4210-spi.2",
1190 },
1191 .sources = &exynos5_clkset_group,
1192 .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 24, .size = 4 },
1193 .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 0, .size = 4 },
1194};
1195
1196static struct clksrc_clk exynos5_clk_sclk_spi0 = {
1197 .clk = {
1198 .name = "sclk_spi",
1199 .devname = "exynos4210-spi.0",
1200 .parent = &exynos5_clk_mdout_spi0.clk,
1201 .enable = exynos5_clksrc_mask_peric1_ctrl,
1202 .ctrlbit = (1 << 16),
1203 },
1204 .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 8, .size = 8 },
1205};
1206
1207static struct clksrc_clk exynos5_clk_sclk_spi1 = {
1208 .clk = {
1209 .name = "sclk_spi",
1210 .devname = "exynos4210-spi.1",
1211 .parent = &exynos5_clk_mdout_spi1.clk,
1212 .enable = exynos5_clksrc_mask_peric1_ctrl,
1213 .ctrlbit = (1 << 20),
1214 },
1215 .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 24, .size = 8 },
1216};
1217
1218static struct clksrc_clk exynos5_clk_sclk_spi2 = {
1219 .clk = {
1220 .name = "sclk_spi",
1221 .devname = "exynos4210-spi.2",
1222 .parent = &exynos5_clk_mdout_spi2.clk,
1223 .enable = exynos5_clksrc_mask_peric1_ctrl,
1224 .ctrlbit = (1 << 24),
1225 },
1226 .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 8, .size = 8 },
1227};
1228
1229static struct clksrc_clk exynos5_clk_sclk_fimd1 = {
1230 .clk = {
1231 .name = "sclk_fimd",
1232 .devname = "exynos5-fb.1",
1233 .enable = exynos5_clksrc_mask_disp1_0_ctrl,
1234 .ctrlbit = (1 << 0),
1235 },
1236 .sources = &exynos5_clkset_group,
1237 .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 0, .size = 4 },
1238 .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 0, .size = 4 },
1239};
1240
1241static struct clksrc_clk exynos5_clksrcs[] = {
1242 {
1243 .clk = {
1244 .name = "aclk_266_gscl",
1245 },
1246 .sources = &clk_src_gscl_266,
1247 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 8, .size = 1 },
1248 }, {
1249 .clk = {
1250 .name = "sclk_g3d",
1251 .devname = "mali-t604.0",
1252 .enable = exynos5_clk_block_ctrl,
1253 .ctrlbit = (1 << 1),
1254 },
1255 .sources = &exynos5_clkset_aclk,
1256 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 20, .size = 1 },
1257 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 24, .size = 3 },
1258 }, {
1259 .clk = {
1260 .name = "sclk_sata",
1261 .devname = "exynos5-sata",
1262 .enable = exynos5_clksrc_mask_fsys_ctrl,
1263 .ctrlbit = (1 << 24),
1264 },
1265 .sources = &exynos5_clkset_aclk,
1266 .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 24, .size = 1 },
1267 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS0, .shift = 20, .size = 4 },
1268 }, {
1269 .clk = {
1270 .name = "sclk_gscl_wrap",
1271 .devname = "s5p-mipi-csis.0",
1272 .enable = exynos5_clksrc_mask_gscl_ctrl,
1273 .ctrlbit = (1 << 24),
1274 },
1275 .sources = &exynos5_clkset_group,
1276 .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 24, .size = 4 },
1277 .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 24, .size = 4 },
1278 }, {
1279 .clk = {
1280 .name = "sclk_gscl_wrap",
1281 .devname = "s5p-mipi-csis.1",
1282 .enable = exynos5_clksrc_mask_gscl_ctrl,
1283 .ctrlbit = (1 << 28),
1284 },
1285 .sources = &exynos5_clkset_group,
1286 .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 28, .size = 4 },
1287 .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 28, .size = 4 },
1288 }, {
1289 .clk = {
1290 .name = "sclk_cam0",
1291 .enable = exynos5_clksrc_mask_gscl_ctrl,
1292 .ctrlbit = (1 << 16),
1293 },
1294 .sources = &exynos5_clkset_group,
1295 .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 16, .size = 4 },
1296 .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 16, .size = 4 },
1297 }, {
1298 .clk = {
1299 .name = "sclk_cam1",
1300 .enable = exynos5_clksrc_mask_gscl_ctrl,
1301 .ctrlbit = (1 << 20),
1302 },
1303 .sources = &exynos5_clkset_group,
1304 .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 20, .size = 4 },
1305 .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 20, .size = 4 },
1306 }, {
1307 .clk = {
1308 .name = "sclk_jpeg",
1309 .parent = &exynos5_clk_mout_cpll.clk,
1310 },
1311 .reg_div = { .reg = EXYNOS5_CLKDIV_GEN, .shift = 4, .size = 3 },
1312 },
1313};
1314
1315/* Clock initialization code */
1316static struct clksrc_clk *exynos5_sysclks[] = {
1317 &exynos5_clk_mout_apll,
1318 &exynos5_clk_sclk_apll,
1319 &exynos5_clk_mout_bpll,
1320 &exynos5_clk_mout_bpll_fout,
1321 &exynos5_clk_mout_bpll_user,
1322 &exynos5_clk_mout_cpll,
1323 &exynos5_clk_mout_epll,
1324 &exynos5_clk_mout_mpll,
1325 &exynos5_clk_mout_mpll_fout,
1326 &exynos5_clk_mout_mpll_user,
1327 &exynos5_clk_vpllsrc,
1328 &exynos5_clk_sclk_vpll,
1329 &exynos5_clk_mout_cpu,
1330 &exynos5_clk_dout_armclk,
1331 &exynos5_clk_dout_arm2clk,
1332 &exynos5_clk_cdrex,
1333 &exynos5_clk_aclk_400,
1334 &exynos5_clk_aclk_333,
1335 &exynos5_clk_aclk_266,
1336 &exynos5_clk_aclk_200,
1337 &exynos5_clk_aclk_166,
1338 &exynos5_clk_aclk_300_gscl,
1339 &exynos5_clk_mout_aclk_300_gscl,
1340 &exynos5_clk_mout_aclk_300_gscl_mid,
1341 &exynos5_clk_mout_aclk_300_gscl_mid1,
1342 &exynos5_clk_aclk_66_pre,
1343 &exynos5_clk_aclk_66,
1344 &exynos5_clk_dout_mmc0,
1345 &exynos5_clk_dout_mmc1,
1346 &exynos5_clk_dout_mmc2,
1347 &exynos5_clk_dout_mmc3,
1348 &exynos5_clk_dout_mmc4,
1349 &exynos5_clk_aclk_acp,
1350 &exynos5_clk_pclk_acp,
1351 &exynos5_clk_sclk_spi0,
1352 &exynos5_clk_sclk_spi1,
1353 &exynos5_clk_sclk_spi2,
1354 &exynos5_clk_mdout_spi0,
1355 &exynos5_clk_mdout_spi1,
1356 &exynos5_clk_mdout_spi2,
1357 &exynos5_clk_sclk_fimd1,
1358};
1359
1360static struct clk *exynos5_clk_cdev[] = {
1361 &exynos5_clk_pdma0,
1362 &exynos5_clk_pdma1,
1363 &exynos5_clk_mdma1,
1364 &exynos5_clk_fimd1,
1365};
1366
1367static struct clksrc_clk *exynos5_clksrc_cdev[] = {
1368 &exynos5_clk_sclk_uart0,
1369 &exynos5_clk_sclk_uart1,
1370 &exynos5_clk_sclk_uart2,
1371 &exynos5_clk_sclk_uart3,
1372 &exynos5_clk_sclk_mmc0,
1373 &exynos5_clk_sclk_mmc1,
1374 &exynos5_clk_sclk_mmc2,
1375 &exynos5_clk_sclk_mmc3,
1376};
1377
1378static struct clk_lookup exynos5_clk_lookup[] = {
1379 CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &exynos5_clk_sclk_uart0.clk),
1380 CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos5_clk_sclk_uart1.clk),
1381 CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos5_clk_sclk_uart2.clk),
1382 CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos5_clk_sclk_uart3.clk),
1383 CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos5_clk_sclk_mmc0.clk),
1384 CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk),
1385 CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk),
1386 CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk),
1387 CLKDEV_INIT("exynos4210-spi.0", "spi_busclk0", &exynos5_clk_sclk_spi0.clk),
1388 CLKDEV_INIT("exynos4210-spi.1", "spi_busclk0", &exynos5_clk_sclk_spi1.clk),
1389 CLKDEV_INIT("exynos4210-spi.2", "spi_busclk0", &exynos5_clk_sclk_spi2.clk),
1390 CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0),
1391 CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1),
1392 CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1),
1393 CLKDEV_INIT("exynos5-fb.1", "lcd", &exynos5_clk_fimd1),
1394};
1395
1396static unsigned long exynos5_epll_get_rate(struct clk *clk)
1397{
1398 return clk->rate;
1399}
1400
1401static struct clk *exynos5_clks[] __initdata = {
1402 &exynos5_clk_sclk_hdmi27m,
1403 &exynos5_clk_sclk_hdmiphy,
1404 &clk_fout_bpll,
1405 &clk_fout_bpll_div2,
1406 &clk_fout_cpll,
1407 &clk_fout_mpll_div2,
1408 &exynos5_clk_armclk,
1409};
1410
1411static u32 epll_div[][6] = {
1412 { 192000000, 0, 48, 3, 1, 0 },
1413 { 180000000, 0, 45, 3, 1, 0 },
1414 { 73728000, 1, 73, 3, 3, 47710 },
1415 { 67737600, 1, 90, 4, 3, 20762 },
1416 { 49152000, 0, 49, 3, 3, 9961 },
1417 { 45158400, 0, 45, 3, 3, 10381 },
1418 { 180633600, 0, 45, 3, 1, 10381 },
1419};
1420
1421static int exynos5_epll_set_rate(struct clk *clk, unsigned long rate)
1422{
1423 unsigned int epll_con, epll_con_k;
1424 unsigned int i;
1425 unsigned int tmp;
1426 unsigned int epll_rate;
1427 unsigned int locktime;
1428 unsigned int lockcnt;
1429
1430 /* Return if nothing changed */
1431 if (clk->rate == rate)
1432 return 0;
1433
1434 if (clk->parent)
1435 epll_rate = clk_get_rate(clk->parent);
1436 else
1437 epll_rate = clk_ext_xtal_mux.rate;
1438
1439 if (epll_rate != 24000000) {
1440 pr_err("Invalid Clock : recommended clock is 24MHz.\n");
1441 return -EINVAL;
1442 }
1443
1444 epll_con = __raw_readl(EXYNOS5_EPLL_CON0);
1445 epll_con &= ~(0x1 << 27 | \
1446 PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT | \
1447 PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT | \
1448 PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
1449
1450 for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
1451 if (epll_div[i][0] == rate) {
1452 epll_con_k = epll_div[i][5] << 0;
1453 epll_con |= epll_div[i][1] << 27;
1454 epll_con |= epll_div[i][2] << PLL46XX_MDIV_SHIFT;
1455 epll_con |= epll_div[i][3] << PLL46XX_PDIV_SHIFT;
1456 epll_con |= epll_div[i][4] << PLL46XX_SDIV_SHIFT;
1457 break;
1458 }
1459 }
1460
1461 if (i == ARRAY_SIZE(epll_div)) {
1462 printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n",
1463 __func__);
1464 return -EINVAL;
1465 }
1466
1467 epll_rate /= 1000000;
1468
1469 /* 3000 max_cycls : specification data */
1470 locktime = 3000 / epll_rate * epll_div[i][3];
1471 lockcnt = locktime * 10000 / (10000 / epll_rate);
1472
1473 __raw_writel(lockcnt, EXYNOS5_EPLL_LOCK);
1474
1475 __raw_writel(epll_con, EXYNOS5_EPLL_CON0);
1476 __raw_writel(epll_con_k, EXYNOS5_EPLL_CON1);
1477
1478 do {
1479 tmp = __raw_readl(EXYNOS5_EPLL_CON0);
1480 } while (!(tmp & 0x1 << EXYNOS5_EPLLCON0_LOCKED_SHIFT));
1481
1482 clk->rate = rate;
1483
1484 return 0;
1485}
1486
1487static struct clk_ops exynos5_epll_ops = {
1488 .get_rate = exynos5_epll_get_rate,
1489 .set_rate = exynos5_epll_set_rate,
1490};
1491
1492static int xtal_rate;
1493
1494static unsigned long exynos5_fout_apll_get_rate(struct clk *clk)
1495{
1496 return s5p_get_pll35xx(xtal_rate, __raw_readl(EXYNOS5_APLL_CON0));
1497}
1498
1499static struct clk_ops exynos5_fout_apll_ops = {
1500 .get_rate = exynos5_fout_apll_get_rate,
1501};
1502
1503#ifdef CONFIG_PM
1504static int exynos5_clock_suspend(void)
1505{
1506 s3c_pm_do_save(exynos5_clock_save, ARRAY_SIZE(exynos5_clock_save));
1507
1508 return 0;
1509}
1510
1511static void exynos5_clock_resume(void)
1512{
1513 s3c_pm_do_restore_core(exynos5_clock_save, ARRAY_SIZE(exynos5_clock_save));
1514}
1515#else
1516#define exynos5_clock_suspend NULL
1517#define exynos5_clock_resume NULL
1518#endif
1519
1520static struct syscore_ops exynos5_clock_syscore_ops = {
1521 .suspend = exynos5_clock_suspend,
1522 .resume = exynos5_clock_resume,
1523};
1524
1525void __init_or_cpufreq exynos5_setup_clocks(void)
1526{
1527 struct clk *xtal_clk;
1528 unsigned long apll;
1529 unsigned long bpll;
1530 unsigned long cpll;
1531 unsigned long mpll;
1532 unsigned long epll;
1533 unsigned long vpll;
1534 unsigned long vpllsrc;
1535 unsigned long xtal;
1536 unsigned long armclk;
1537 unsigned long mout_cdrex;
1538 unsigned long aclk_400;
1539 unsigned long aclk_333;
1540 unsigned long aclk_266;
1541 unsigned long aclk_200;
1542 unsigned long aclk_166;
1543 unsigned long aclk_66;
1544 unsigned int ptr;
1545
1546 printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1547
1548 xtal_clk = clk_get(NULL, "xtal");
1549 BUG_ON(IS_ERR(xtal_clk));
1550
1551 xtal = clk_get_rate(xtal_clk);
1552
1553 xtal_rate = xtal;
1554
1555 clk_put(xtal_clk);
1556
1557 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1558
1559 apll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_APLL_CON0));
1560 bpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_BPLL_CON0));
1561 cpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_CPLL_CON0));
1562 mpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_MPLL_CON0));
1563 epll = s5p_get_pll36xx(xtal, __raw_readl(EXYNOS5_EPLL_CON0),
1564 __raw_readl(EXYNOS5_EPLL_CON1));
1565
1566 vpllsrc = clk_get_rate(&exynos5_clk_vpllsrc.clk);
1567 vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(EXYNOS5_VPLL_CON0),
1568 __raw_readl(EXYNOS5_VPLL_CON1));
1569
1570 clk_fout_apll.ops = &exynos5_fout_apll_ops;
1571 clk_fout_bpll.rate = bpll;
1572 clk_fout_bpll_div2.rate = bpll >> 1;
1573 clk_fout_cpll.rate = cpll;
1574 clk_fout_mpll.rate = mpll;
1575 clk_fout_mpll_div2.rate = mpll >> 1;
1576 clk_fout_epll.rate = epll;
1577 clk_fout_vpll.rate = vpll;
1578
1579 printk(KERN_INFO "EXYNOS5: PLL settings, A=%ld, B=%ld, C=%ld\n"
1580 "M=%ld, E=%ld V=%ld",
1581 apll, bpll, cpll, mpll, epll, vpll);
1582
1583 armclk = clk_get_rate(&exynos5_clk_armclk);
1584 mout_cdrex = clk_get_rate(&exynos5_clk_cdrex.clk);
1585
1586 aclk_400 = clk_get_rate(&exynos5_clk_aclk_400.clk);
1587 aclk_333 = clk_get_rate(&exynos5_clk_aclk_333.clk);
1588 aclk_266 = clk_get_rate(&exynos5_clk_aclk_266.clk);
1589 aclk_200 = clk_get_rate(&exynos5_clk_aclk_200.clk);
1590 aclk_166 = clk_get_rate(&exynos5_clk_aclk_166.clk);
1591 aclk_66 = clk_get_rate(&exynos5_clk_aclk_66.clk);
1592
1593 printk(KERN_INFO "EXYNOS5: ARMCLK=%ld, CDREX=%ld, ACLK400=%ld\n"
1594 "ACLK333=%ld, ACLK266=%ld, ACLK200=%ld\n"
1595 "ACLK166=%ld, ACLK66=%ld\n",
1596 armclk, mout_cdrex, aclk_400,
1597 aclk_333, aclk_266, aclk_200,
1598 aclk_166, aclk_66);
1599
1600
1601 clk_fout_epll.ops = &exynos5_epll_ops;
1602
1603 if (clk_set_parent(&exynos5_clk_mout_epll.clk, &clk_fout_epll))
1604 printk(KERN_ERR "Unable to set parent %s of clock %s.\n",
1605 clk_fout_epll.name, exynos5_clk_mout_epll.clk.name);
1606
1607 clk_set_rate(&exynos5_clk_sclk_apll.clk, 100000000);
1608 clk_set_rate(&exynos5_clk_aclk_266.clk, 300000000);
1609
1610 clk_set_rate(&exynos5_clk_aclk_acp.clk, 267000000);
1611 clk_set_rate(&exynos5_clk_pclk_acp.clk, 134000000);
1612
1613 for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clksrcs); ptr++)
1614 s3c_set_clksrc(&exynos5_clksrcs[ptr], true);
1615}
1616
1617void __init exynos5_register_clocks(void)
1618{
1619 int ptr;
1620
1621 s3c24xx_register_clocks(exynos5_clks, ARRAY_SIZE(exynos5_clks));
1622
1623 for (ptr = 0; ptr < ARRAY_SIZE(exynos5_sysclks); ptr++)
1624 s3c_register_clksrc(exynos5_sysclks[ptr], 1);
1625
1626 for (ptr = 0; ptr < ARRAY_SIZE(exynos5_sclk_tv); ptr++)
1627 s3c_register_clksrc(exynos5_sclk_tv[ptr], 1);
1628
1629 for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clksrc_cdev); ptr++)
1630 s3c_register_clksrc(exynos5_clksrc_cdev[ptr], 1);
1631
1632 s3c_register_clksrc(exynos5_clksrcs, ARRAY_SIZE(exynos5_clksrcs));
1633 s3c_register_clocks(exynos5_init_clocks_on, ARRAY_SIZE(exynos5_init_clocks_on));
1634
1635 s3c24xx_register_clocks(exynos5_clk_cdev, ARRAY_SIZE(exynos5_clk_cdev));
1636 for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clk_cdev); ptr++)
1637 s3c_disable_clocks(exynos5_clk_cdev[ptr], 1);
1638
1639 s3c_register_clocks(exynos5_init_clocks_off, ARRAY_SIZE(exynos5_init_clocks_off));
1640 s3c_disable_clocks(exynos5_init_clocks_off, ARRAY_SIZE(exynos5_init_clocks_off));
1641 clkdev_add_table(exynos5_clk_lookup, ARRAY_SIZE(exynos5_clk_lookup));
1642
1643 register_syscore_ops(&exynos5_clock_syscore_ops);
1644 s3c_pwmclk_init();
1645}
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-25 17:24:48 -0500