diff options
author | Ulrich Hecht <ulrich.hecht+renesas@gmail.com> | 2018-02-15 07:01:29 -0500 |
---|---|---|
committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2018-02-26 04:19:03 -0500 |
commit | 6b4de408105fc51e85e55937e049503f30f8c633 (patch) | |
tree | 55178ad5db0b5e03c15e203a6739bc71fc96ddfa | |
parent | 8db6cbabac4f2a02ccbce1dbf6845245f38d11f4 (diff) |
pinctrl: sh-pfc: r8a7795: Add VIN4, VIN5 pins, groups and functions
This patch adds VIN4 and VIN5 pins, groups and functions for the
R8A7795 SoC.
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
-rw-r--r-- | drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 454 |
1 files changed, 454 insertions, 0 deletions
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c index f6a0b8bd4f92..7c77ddc920c7 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c | |||
@@ -3928,6 +3928,400 @@ static const unsigned int usb30_mux[] = { | |||
3928 | USB30_PWEN_MARK, USB30_OVC_MARK, | 3928 | USB30_PWEN_MARK, USB30_OVC_MARK, |
3929 | }; | 3929 | }; |
3930 | 3930 | ||
3931 | /* - VIN4 ------------------------------------------------------------------- */ | ||
3932 | static const unsigned int vin4_data8_a_pins[] = { | ||
3933 | RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), | ||
3934 | RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), | ||
3935 | RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), | ||
3936 | RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), | ||
3937 | }; | ||
3938 | static const unsigned int vin4_data8_a_mux[] = { | ||
3939 | VI4_DATA0_A_MARK, VI4_DATA1_A_MARK, | ||
3940 | VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, | ||
3941 | VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, | ||
3942 | VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, | ||
3943 | }; | ||
3944 | static const unsigned int vin4_data8_b_pins[] = { | ||
3945 | RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), | ||
3946 | RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), | ||
3947 | RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), | ||
3948 | RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), | ||
3949 | }; | ||
3950 | static const unsigned int vin4_data8_b_mux[] = { | ||
3951 | VI4_DATA0_B_MARK, VI4_DATA1_B_MARK, | ||
3952 | VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, | ||
3953 | VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, | ||
3954 | VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, | ||
3955 | }; | ||
3956 | static const unsigned int vin4_data10_a_pins[] = { | ||
3957 | RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), | ||
3958 | RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), | ||
3959 | RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), | ||
3960 | RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), | ||
3961 | RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), | ||
3962 | }; | ||
3963 | static const unsigned int vin4_data10_a_mux[] = { | ||
3964 | VI4_DATA0_A_MARK, VI4_DATA1_A_MARK, | ||
3965 | VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, | ||
3966 | VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, | ||
3967 | VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, | ||
3968 | VI4_DATA8_MARK, VI4_DATA9_MARK, | ||
3969 | }; | ||
3970 | static const unsigned int vin4_data10_b_pins[] = { | ||
3971 | RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), | ||
3972 | RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), | ||
3973 | RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), | ||
3974 | RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), | ||
3975 | RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), | ||
3976 | }; | ||
3977 | static const unsigned int vin4_data10_b_mux[] = { | ||
3978 | VI4_DATA0_B_MARK, VI4_DATA1_B_MARK, | ||
3979 | VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, | ||
3980 | VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, | ||
3981 | VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, | ||
3982 | VI4_DATA8_MARK, VI4_DATA9_MARK, | ||
3983 | }; | ||
3984 | static const unsigned int vin4_data12_a_pins[] = { | ||
3985 | RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), | ||
3986 | RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), | ||
3987 | RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), | ||
3988 | RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), | ||
3989 | RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), | ||
3990 | RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), | ||
3991 | }; | ||
3992 | static const unsigned int vin4_data12_a_mux[] = { | ||
3993 | VI4_DATA0_A_MARK, VI4_DATA1_A_MARK, | ||
3994 | VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, | ||
3995 | VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, | ||
3996 | VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, | ||
3997 | VI4_DATA8_MARK, VI4_DATA9_MARK, | ||
3998 | VI4_DATA10_MARK, VI4_DATA11_MARK, | ||
3999 | }; | ||
4000 | static const unsigned int vin4_data12_b_pins[] = { | ||
4001 | RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), | ||
4002 | RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), | ||
4003 | RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), | ||
4004 | RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), | ||
4005 | RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), | ||
4006 | RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), | ||
4007 | }; | ||
4008 | static const unsigned int vin4_data12_b_mux[] = { | ||
4009 | VI4_DATA0_B_MARK, VI4_DATA1_B_MARK, | ||
4010 | VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, | ||
4011 | VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, | ||
4012 | VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, | ||
4013 | VI4_DATA8_MARK, VI4_DATA9_MARK, | ||
4014 | VI4_DATA10_MARK, VI4_DATA11_MARK, | ||
4015 | }; | ||
4016 | static const unsigned int vin4_data16_a_pins[] = { | ||
4017 | RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), | ||
4018 | RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), | ||
4019 | RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), | ||
4020 | RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), | ||
4021 | RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), | ||
4022 | RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), | ||
4023 | RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), | ||
4024 | RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), | ||
4025 | }; | ||
4026 | static const unsigned int vin4_data16_a_mux[] = { | ||
4027 | VI4_DATA0_A_MARK, VI4_DATA1_A_MARK, | ||
4028 | VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, | ||
4029 | VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, | ||
4030 | VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, | ||
4031 | VI4_DATA8_MARK, VI4_DATA9_MARK, | ||
4032 | VI4_DATA10_MARK, VI4_DATA11_MARK, | ||
4033 | VI4_DATA12_MARK, VI4_DATA13_MARK, | ||
4034 | VI4_DATA14_MARK, VI4_DATA15_MARK, | ||
4035 | }; | ||
4036 | static const unsigned int vin4_data16_b_pins[] = { | ||
4037 | RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), | ||
4038 | RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), | ||
4039 | RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), | ||
4040 | RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), | ||
4041 | RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), | ||
4042 | RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), | ||
4043 | RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), | ||
4044 | RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), | ||
4045 | }; | ||
4046 | static const unsigned int vin4_data16_b_mux[] = { | ||
4047 | VI4_DATA0_B_MARK, VI4_DATA1_B_MARK, | ||
4048 | VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, | ||
4049 | VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, | ||
4050 | VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, | ||
4051 | VI4_DATA8_MARK, VI4_DATA9_MARK, | ||
4052 | VI4_DATA10_MARK, VI4_DATA11_MARK, | ||
4053 | VI4_DATA12_MARK, VI4_DATA13_MARK, | ||
4054 | VI4_DATA14_MARK, VI4_DATA15_MARK, | ||
4055 | }; | ||
4056 | static const unsigned int vin4_data18_a_pins[] = { | ||
4057 | RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), | ||
4058 | RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), | ||
4059 | RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), | ||
4060 | RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), | ||
4061 | RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), | ||
4062 | RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), | ||
4063 | RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), | ||
4064 | RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), | ||
4065 | RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), | ||
4066 | }; | ||
4067 | static const unsigned int vin4_data18_a_mux[] = { | ||
4068 | VI4_DATA0_A_MARK, VI4_DATA1_A_MARK, | ||
4069 | VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, | ||
4070 | VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, | ||
4071 | VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, | ||
4072 | VI4_DATA8_MARK, VI4_DATA9_MARK, | ||
4073 | VI4_DATA10_MARK, VI4_DATA11_MARK, | ||
4074 | VI4_DATA12_MARK, VI4_DATA13_MARK, | ||
4075 | VI4_DATA14_MARK, VI4_DATA15_MARK, | ||
4076 | VI4_DATA16_MARK, VI4_DATA17_MARK, | ||
4077 | }; | ||
4078 | static const unsigned int vin4_data18_b_pins[] = { | ||
4079 | RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), | ||
4080 | RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), | ||
4081 | RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), | ||
4082 | RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), | ||
4083 | RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), | ||
4084 | RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), | ||
4085 | RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), | ||
4086 | RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), | ||
4087 | RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), | ||
4088 | }; | ||
4089 | static const unsigned int vin4_data18_b_mux[] = { | ||
4090 | VI4_DATA0_B_MARK, VI4_DATA1_B_MARK, | ||
4091 | VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, | ||
4092 | VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, | ||
4093 | VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, | ||
4094 | VI4_DATA8_MARK, VI4_DATA9_MARK, | ||
4095 | VI4_DATA10_MARK, VI4_DATA11_MARK, | ||
4096 | VI4_DATA12_MARK, VI4_DATA13_MARK, | ||
4097 | VI4_DATA14_MARK, VI4_DATA15_MARK, | ||
4098 | VI4_DATA16_MARK, VI4_DATA17_MARK, | ||
4099 | }; | ||
4100 | static const unsigned int vin4_data20_a_pins[] = { | ||
4101 | RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), | ||
4102 | RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), | ||
4103 | RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), | ||
4104 | RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), | ||
4105 | RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), | ||
4106 | RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), | ||
4107 | RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), | ||
4108 | RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), | ||
4109 | RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), | ||
4110 | RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), | ||
4111 | }; | ||
4112 | static const unsigned int vin4_data20_a_mux[] = { | ||
4113 | VI4_DATA0_A_MARK, VI4_DATA1_A_MARK, | ||
4114 | VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, | ||
4115 | VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, | ||
4116 | VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, | ||
4117 | VI4_DATA8_MARK, VI4_DATA9_MARK, | ||
4118 | VI4_DATA10_MARK, VI4_DATA11_MARK, | ||
4119 | VI4_DATA12_MARK, VI4_DATA13_MARK, | ||
4120 | VI4_DATA14_MARK, VI4_DATA15_MARK, | ||
4121 | VI4_DATA16_MARK, VI4_DATA17_MARK, | ||
4122 | VI4_DATA18_MARK, VI4_DATA19_MARK, | ||
4123 | }; | ||
4124 | static const unsigned int vin4_data20_b_pins[] = { | ||
4125 | RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), | ||
4126 | RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), | ||
4127 | RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), | ||
4128 | RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), | ||
4129 | RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), | ||
4130 | RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), | ||
4131 | RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), | ||
4132 | RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), | ||
4133 | RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), | ||
4134 | RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), | ||
4135 | }; | ||
4136 | static const unsigned int vin4_data20_b_mux[] = { | ||
4137 | VI4_DATA0_B_MARK, VI4_DATA1_B_MARK, | ||
4138 | VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, | ||
4139 | VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, | ||
4140 | VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, | ||
4141 | VI4_DATA8_MARK, VI4_DATA9_MARK, | ||
4142 | VI4_DATA10_MARK, VI4_DATA11_MARK, | ||
4143 | VI4_DATA12_MARK, VI4_DATA13_MARK, | ||
4144 | VI4_DATA14_MARK, VI4_DATA15_MARK, | ||
4145 | VI4_DATA16_MARK, VI4_DATA17_MARK, | ||
4146 | VI4_DATA18_MARK, VI4_DATA19_MARK, | ||
4147 | }; | ||
4148 | static const unsigned int vin4_data24_a_pins[] = { | ||
4149 | RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), | ||
4150 | RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), | ||
4151 | RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), | ||
4152 | RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), | ||
4153 | RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), | ||
4154 | RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), | ||
4155 | RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), | ||
4156 | RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), | ||
4157 | RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), | ||
4158 | RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), | ||
4159 | RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), | ||
4160 | RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), | ||
4161 | }; | ||
4162 | static const unsigned int vin4_data24_a_mux[] = { | ||
4163 | VI4_DATA0_A_MARK, VI4_DATA1_A_MARK, | ||
4164 | VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, | ||
4165 | VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, | ||
4166 | VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, | ||
4167 | VI4_DATA8_MARK, VI4_DATA9_MARK, | ||
4168 | VI4_DATA10_MARK, VI4_DATA11_MARK, | ||
4169 | VI4_DATA12_MARK, VI4_DATA13_MARK, | ||
4170 | VI4_DATA14_MARK, VI4_DATA15_MARK, | ||
4171 | VI4_DATA16_MARK, VI4_DATA17_MARK, | ||
4172 | VI4_DATA18_MARK, VI4_DATA19_MARK, | ||
4173 | VI4_DATA20_MARK, VI4_DATA21_MARK, | ||
4174 | VI4_DATA22_MARK, VI4_DATA23_MARK, | ||
4175 | }; | ||
4176 | static const unsigned int vin4_data24_b_pins[] = { | ||
4177 | RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), | ||
4178 | RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), | ||
4179 | RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), | ||
4180 | RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), | ||
4181 | RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), | ||
4182 | RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), | ||
4183 | RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), | ||
4184 | RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), | ||
4185 | RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), | ||
4186 | RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), | ||
4187 | RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), | ||
4188 | RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), | ||
4189 | }; | ||
4190 | static const unsigned int vin4_data24_b_mux[] = { | ||
4191 | VI4_DATA0_B_MARK, VI4_DATA1_B_MARK, | ||
4192 | VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, | ||
4193 | VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, | ||
4194 | VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, | ||
4195 | VI4_DATA8_MARK, VI4_DATA9_MARK, | ||
4196 | VI4_DATA10_MARK, VI4_DATA11_MARK, | ||
4197 | VI4_DATA12_MARK, VI4_DATA13_MARK, | ||
4198 | VI4_DATA14_MARK, VI4_DATA15_MARK, | ||
4199 | VI4_DATA16_MARK, VI4_DATA17_MARK, | ||
4200 | VI4_DATA18_MARK, VI4_DATA19_MARK, | ||
4201 | VI4_DATA20_MARK, VI4_DATA21_MARK, | ||
4202 | VI4_DATA22_MARK, VI4_DATA23_MARK, | ||
4203 | }; | ||
4204 | static const unsigned int vin4_sync_pins[] = { | ||
4205 | /* HSYNC#, VSYNC# */ | ||
4206 | RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 17), | ||
4207 | }; | ||
4208 | static const unsigned int vin4_sync_mux[] = { | ||
4209 | VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK, | ||
4210 | }; | ||
4211 | static const unsigned int vin4_field_pins[] = { | ||
4212 | /* FIELD */ | ||
4213 | RCAR_GP_PIN(1, 16), | ||
4214 | }; | ||
4215 | static const unsigned int vin4_field_mux[] = { | ||
4216 | VI4_FIELD_MARK, | ||
4217 | }; | ||
4218 | static const unsigned int vin4_clkenb_pins[] = { | ||
4219 | /* CLKENB */ | ||
4220 | RCAR_GP_PIN(1, 19), | ||
4221 | }; | ||
4222 | static const unsigned int vin4_clkenb_mux[] = { | ||
4223 | VI4_CLKENB_MARK, | ||
4224 | }; | ||
4225 | static const unsigned int vin4_clk_pins[] = { | ||
4226 | /* CLK */ | ||
4227 | RCAR_GP_PIN(1, 27), | ||
4228 | }; | ||
4229 | static const unsigned int vin4_clk_mux[] = { | ||
4230 | VI4_CLK_MARK, | ||
4231 | }; | ||
4232 | |||
4233 | /* - VIN5 ------------------------------------------------------------------- */ | ||
4234 | static const unsigned int vin5_data8_pins[] = { | ||
4235 | RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), | ||
4236 | RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), | ||
4237 | RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), | ||
4238 | RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), | ||
4239 | }; | ||
4240 | static const unsigned int vin5_data8_mux[] = { | ||
4241 | VI5_DATA0_MARK, VI5_DATA1_MARK, | ||
4242 | VI5_DATA2_MARK, VI5_DATA3_MARK, | ||
4243 | VI5_DATA4_MARK, VI5_DATA5_MARK, | ||
4244 | VI5_DATA6_MARK, VI5_DATA7_MARK, | ||
4245 | }; | ||
4246 | static const unsigned int vin5_data10_pins[] = { | ||
4247 | RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), | ||
4248 | RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), | ||
4249 | RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), | ||
4250 | RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), | ||
4251 | RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), | ||
4252 | }; | ||
4253 | static const unsigned int vin5_data10_mux[] = { | ||
4254 | VI5_DATA0_MARK, VI5_DATA1_MARK, | ||
4255 | VI5_DATA2_MARK, VI5_DATA3_MARK, | ||
4256 | VI5_DATA4_MARK, VI5_DATA5_MARK, | ||
4257 | VI5_DATA6_MARK, VI5_DATA7_MARK, | ||
4258 | VI5_DATA8_MARK, VI5_DATA9_MARK, | ||
4259 | }; | ||
4260 | static const unsigned int vin5_data12_pins[] = { | ||
4261 | RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), | ||
4262 | RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), | ||
4263 | RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), | ||
4264 | RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), | ||
4265 | RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), | ||
4266 | RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), | ||
4267 | }; | ||
4268 | static const unsigned int vin5_data12_mux[] = { | ||
4269 | VI5_DATA0_MARK, VI5_DATA1_MARK, | ||
4270 | VI5_DATA2_MARK, VI5_DATA3_MARK, | ||
4271 | VI5_DATA4_MARK, VI5_DATA5_MARK, | ||
4272 | VI5_DATA6_MARK, VI5_DATA7_MARK, | ||
4273 | VI5_DATA8_MARK, VI5_DATA9_MARK, | ||
4274 | VI5_DATA10_MARK, VI5_DATA11_MARK, | ||
4275 | }; | ||
4276 | static const unsigned int vin5_data16_pins[] = { | ||
4277 | RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), | ||
4278 | RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), | ||
4279 | RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), | ||
4280 | RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), | ||
4281 | RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), | ||
4282 | RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), | ||
4283 | RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), | ||
4284 | RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), | ||
4285 | }; | ||
4286 | static const unsigned int vin5_data16_mux[] = { | ||
4287 | VI5_DATA0_MARK, VI5_DATA1_MARK, | ||
4288 | VI5_DATA2_MARK, VI5_DATA3_MARK, | ||
4289 | VI5_DATA4_MARK, VI5_DATA5_MARK, | ||
4290 | VI5_DATA6_MARK, VI5_DATA7_MARK, | ||
4291 | VI5_DATA8_MARK, VI5_DATA9_MARK, | ||
4292 | VI5_DATA10_MARK, VI5_DATA11_MARK, | ||
4293 | VI5_DATA12_MARK, VI5_DATA13_MARK, | ||
4294 | VI5_DATA14_MARK, VI5_DATA15_MARK, | ||
4295 | }; | ||
4296 | static const unsigned int vin5_sync_pins[] = { | ||
4297 | /* HSYNC#, VSYNC# */ | ||
4298 | RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9), | ||
4299 | }; | ||
4300 | static const unsigned int vin5_sync_mux[] = { | ||
4301 | VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK, | ||
4302 | }; | ||
4303 | static const unsigned int vin5_field_pins[] = { | ||
4304 | RCAR_GP_PIN(1, 11), | ||
4305 | }; | ||
4306 | static const unsigned int vin5_field_mux[] = { | ||
4307 | /* FIELD */ | ||
4308 | VI5_FIELD_MARK, | ||
4309 | }; | ||
4310 | static const unsigned int vin5_clkenb_pins[] = { | ||
4311 | RCAR_GP_PIN(1, 20), | ||
4312 | }; | ||
4313 | static const unsigned int vin5_clkenb_mux[] = { | ||
4314 | /* CLKENB */ | ||
4315 | VI5_CLKENB_MARK, | ||
4316 | }; | ||
4317 | static const unsigned int vin5_clk_pins[] = { | ||
4318 | RCAR_GP_PIN(1, 21), | ||
4319 | }; | ||
4320 | static const unsigned int vin5_clk_mux[] = { | ||
4321 | /* CLK */ | ||
4322 | VI5_CLK_MARK, | ||
4323 | }; | ||
4324 | |||
3931 | static const struct sh_pfc_pin_group pinmux_groups[] = { | 4325 | static const struct sh_pfc_pin_group pinmux_groups[] = { |
3932 | SH_PFC_PIN_GROUP(audio_clk_a_a), | 4326 | SH_PFC_PIN_GROUP(audio_clk_a_a), |
3933 | SH_PFC_PIN_GROUP(audio_clk_a_b), | 4327 | SH_PFC_PIN_GROUP(audio_clk_a_b), |
@@ -4247,6 +4641,32 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { | |||
4247 | SH_PFC_PIN_GROUP(usb2), | 4641 | SH_PFC_PIN_GROUP(usb2), |
4248 | SH_PFC_PIN_GROUP(usb2_ch3), | 4642 | SH_PFC_PIN_GROUP(usb2_ch3), |
4249 | SH_PFC_PIN_GROUP(usb30), | 4643 | SH_PFC_PIN_GROUP(usb30), |
4644 | SH_PFC_PIN_GROUP(vin4_data8_a), | ||
4645 | SH_PFC_PIN_GROUP(vin4_data10_a), | ||
4646 | SH_PFC_PIN_GROUP(vin4_data12_a), | ||
4647 | SH_PFC_PIN_GROUP(vin4_data16_a), | ||
4648 | SH_PFC_PIN_GROUP(vin4_data18_a), | ||
4649 | SH_PFC_PIN_GROUP(vin4_data20_a), | ||
4650 | SH_PFC_PIN_GROUP(vin4_data24_a), | ||
4651 | SH_PFC_PIN_GROUP(vin4_data8_b), | ||
4652 | SH_PFC_PIN_GROUP(vin4_data10_b), | ||
4653 | SH_PFC_PIN_GROUP(vin4_data12_b), | ||
4654 | SH_PFC_PIN_GROUP(vin4_data16_b), | ||
4655 | SH_PFC_PIN_GROUP(vin4_data18_b), | ||
4656 | SH_PFC_PIN_GROUP(vin4_data20_b), | ||
4657 | SH_PFC_PIN_GROUP(vin4_data24_b), | ||
4658 | SH_PFC_PIN_GROUP(vin4_sync), | ||
4659 | SH_PFC_PIN_GROUP(vin4_field), | ||
4660 | SH_PFC_PIN_GROUP(vin4_clkenb), | ||
4661 | SH_PFC_PIN_GROUP(vin4_clk), | ||
4662 | SH_PFC_PIN_GROUP(vin5_data8), | ||
4663 | SH_PFC_PIN_GROUP(vin5_data10), | ||
4664 | SH_PFC_PIN_GROUP(vin5_data12), | ||
4665 | SH_PFC_PIN_GROUP(vin5_data16), | ||
4666 | SH_PFC_PIN_GROUP(vin5_sync), | ||
4667 | SH_PFC_PIN_GROUP(vin5_field), | ||
4668 | SH_PFC_PIN_GROUP(vin5_clkenb), | ||
4669 | SH_PFC_PIN_GROUP(vin5_clk), | ||
4250 | }; | 4670 | }; |
4251 | 4671 | ||
4252 | static const char * const audio_clk_groups[] = { | 4672 | static const char * const audio_clk_groups[] = { |
@@ -4726,6 +5146,38 @@ static const char * const usb30_groups[] = { | |||
4726 | "usb30", | 5146 | "usb30", |
4727 | }; | 5147 | }; |
4728 | 5148 | ||
5149 | static const char * const vin4_groups[] = { | ||
5150 | "vin4_data8_a", | ||
5151 | "vin4_data10_a", | ||
5152 | "vin4_data12_a", | ||
5153 | "vin4_data16_a", | ||
5154 | "vin4_data18_a", | ||
5155 | "vin4_data20_a", | ||
5156 | "vin4_data24_a", | ||
5157 | "vin4_data8_b", | ||
5158 | "vin4_data10_b", | ||
5159 | "vin4_data12_b", | ||
5160 | "vin4_data16_b", | ||
5161 | "vin4_data18_b", | ||
5162 | "vin4_data20_b", | ||
5163 | "vin4_data24_b", | ||
5164 | "vin4_sync", | ||
5165 | "vin4_field", | ||
5166 | "vin4_clkenb", | ||
5167 | "vin4_clk", | ||
5168 | }; | ||
5169 | |||
5170 | static const char * const vin5_groups[] = { | ||
5171 | "vin5_data8", | ||
5172 | "vin5_data10", | ||
5173 | "vin5_data12", | ||
5174 | "vin5_data16", | ||
5175 | "vin5_sync", | ||
5176 | "vin5_field", | ||
5177 | "vin5_clkenb", | ||
5178 | "vin5_clk", | ||
5179 | }; | ||
5180 | |||
4729 | static const struct sh_pfc_function pinmux_functions[] = { | 5181 | static const struct sh_pfc_function pinmux_functions[] = { |
4730 | SH_PFC_FUNCTION(audio_clk), | 5182 | SH_PFC_FUNCTION(audio_clk), |
4731 | SH_PFC_FUNCTION(avb), | 5183 | SH_PFC_FUNCTION(avb), |
@@ -4780,6 +5232,8 @@ static const struct sh_pfc_function pinmux_functions[] = { | |||
4780 | SH_PFC_FUNCTION(usb2), | 5232 | SH_PFC_FUNCTION(usb2), |
4781 | SH_PFC_FUNCTION(usb2_ch3), | 5233 | SH_PFC_FUNCTION(usb2_ch3), |
4782 | SH_PFC_FUNCTION(usb30), | 5234 | SH_PFC_FUNCTION(usb30), |
5235 | SH_PFC_FUNCTION(vin4), | ||
5236 | SH_PFC_FUNCTION(vin5), | ||
4783 | }; | 5237 | }; |
4784 | 5238 | ||
4785 | static const struct pinmux_cfg_reg pinmux_config_regs[] = { | 5239 | static const struct pinmux_cfg_reg pinmux_config_regs[] = { |