diff options
author | Ulrich Hecht <ulrich.hecht+renesas@gmail.com> | 2018-02-15 07:01:28 -0500 |
---|---|---|
committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2018-02-26 04:19:03 -0500 |
commit | 8db6cbabac4f2a02ccbce1dbf6845245f38d11f4 (patch) | |
tree | 210d3ecf3ffc31b8e4c8cfc196e521a43303a880 | |
parent | fa3e8b71b955af8691aa773da0e0d21f1cdc529b (diff) |
pinctrl: sh-pfc: r8a7796: Add VIN4, VIN5 pins, groups and functions
This patch adds VIN4 and VIN5 pins, groups and functions for the
R8A7796 SoC.
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
-rw-r--r-- | drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 454 |
1 files changed, 454 insertions, 0 deletions
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c index ad4a7883518a..e6fff5518a97 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c | |||
@@ -3896,6 +3896,400 @@ static const unsigned int usb30_mux[] = { | |||
3896 | USB30_PWEN_MARK, USB30_OVC_MARK, | 3896 | USB30_PWEN_MARK, USB30_OVC_MARK, |
3897 | }; | 3897 | }; |
3898 | 3898 | ||
3899 | /* - VIN4 ------------------------------------------------------------------- */ | ||
3900 | static const unsigned int vin4_data8_a_pins[] = { | ||
3901 | RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), | ||
3902 | RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), | ||
3903 | RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), | ||
3904 | RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), | ||
3905 | }; | ||
3906 | static const unsigned int vin4_data8_a_mux[] = { | ||
3907 | VI4_DATA0_A_MARK, VI4_DATA1_A_MARK, | ||
3908 | VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, | ||
3909 | VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, | ||
3910 | VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, | ||
3911 | }; | ||
3912 | static const unsigned int vin4_data8_b_pins[] = { | ||
3913 | RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), | ||
3914 | RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), | ||
3915 | RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), | ||
3916 | RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), | ||
3917 | }; | ||
3918 | static const unsigned int vin4_data8_b_mux[] = { | ||
3919 | VI4_DATA0_B_MARK, VI4_DATA1_B_MARK, | ||
3920 | VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, | ||
3921 | VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, | ||
3922 | VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, | ||
3923 | }; | ||
3924 | static const unsigned int vin4_data10_a_pins[] = { | ||
3925 | RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), | ||
3926 | RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), | ||
3927 | RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), | ||
3928 | RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), | ||
3929 | RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), | ||
3930 | }; | ||
3931 | static const unsigned int vin4_data10_a_mux[] = { | ||
3932 | VI4_DATA0_A_MARK, VI4_DATA1_A_MARK, | ||
3933 | VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, | ||
3934 | VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, | ||
3935 | VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, | ||
3936 | VI4_DATA8_MARK, VI4_DATA9_MARK, | ||
3937 | }; | ||
3938 | static const unsigned int vin4_data10_b_pins[] = { | ||
3939 | RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), | ||
3940 | RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), | ||
3941 | RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), | ||
3942 | RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), | ||
3943 | RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), | ||
3944 | }; | ||
3945 | static const unsigned int vin4_data10_b_mux[] = { | ||
3946 | VI4_DATA0_B_MARK, VI4_DATA1_B_MARK, | ||
3947 | VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, | ||
3948 | VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, | ||
3949 | VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, | ||
3950 | VI4_DATA8_MARK, VI4_DATA9_MARK, | ||
3951 | }; | ||
3952 | static const unsigned int vin4_data12_a_pins[] = { | ||
3953 | RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), | ||
3954 | RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), | ||
3955 | RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), | ||
3956 | RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), | ||
3957 | RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), | ||
3958 | RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), | ||
3959 | }; | ||
3960 | static const unsigned int vin4_data12_a_mux[] = { | ||
3961 | VI4_DATA0_A_MARK, VI4_DATA1_A_MARK, | ||
3962 | VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, | ||
3963 | VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, | ||
3964 | VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, | ||
3965 | VI4_DATA8_MARK, VI4_DATA9_MARK, | ||
3966 | VI4_DATA10_MARK, VI4_DATA11_MARK, | ||
3967 | }; | ||
3968 | static const unsigned int vin4_data12_b_pins[] = { | ||
3969 | RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), | ||
3970 | RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), | ||
3971 | RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), | ||
3972 | RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), | ||
3973 | RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), | ||
3974 | RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), | ||
3975 | }; | ||
3976 | static const unsigned int vin4_data12_b_mux[] = { | ||
3977 | VI4_DATA0_B_MARK, VI4_DATA1_B_MARK, | ||
3978 | VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, | ||
3979 | VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, | ||
3980 | VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, | ||
3981 | VI4_DATA8_MARK, VI4_DATA9_MARK, | ||
3982 | VI4_DATA10_MARK, VI4_DATA11_MARK, | ||
3983 | }; | ||
3984 | static const unsigned int vin4_data16_a_pins[] = { | ||
3985 | RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), | ||
3986 | RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), | ||
3987 | RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), | ||
3988 | RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), | ||
3989 | RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), | ||
3990 | RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), | ||
3991 | RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), | ||
3992 | RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), | ||
3993 | }; | ||
3994 | static const unsigned int vin4_data16_a_mux[] = { | ||
3995 | VI4_DATA0_A_MARK, VI4_DATA1_A_MARK, | ||
3996 | VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, | ||
3997 | VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, | ||
3998 | VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, | ||
3999 | VI4_DATA8_MARK, VI4_DATA9_MARK, | ||
4000 | VI4_DATA10_MARK, VI4_DATA11_MARK, | ||
4001 | VI4_DATA12_MARK, VI4_DATA13_MARK, | ||
4002 | VI4_DATA14_MARK, VI4_DATA15_MARK, | ||
4003 | }; | ||
4004 | static const unsigned int vin4_data16_b_pins[] = { | ||
4005 | RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), | ||
4006 | RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), | ||
4007 | RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), | ||
4008 | RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), | ||
4009 | RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), | ||
4010 | RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), | ||
4011 | RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), | ||
4012 | RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), | ||
4013 | }; | ||
4014 | static const unsigned int vin4_data16_b_mux[] = { | ||
4015 | VI4_DATA0_B_MARK, VI4_DATA1_B_MARK, | ||
4016 | VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, | ||
4017 | VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, | ||
4018 | VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, | ||
4019 | VI4_DATA8_MARK, VI4_DATA9_MARK, | ||
4020 | VI4_DATA10_MARK, VI4_DATA11_MARK, | ||
4021 | VI4_DATA12_MARK, VI4_DATA13_MARK, | ||
4022 | VI4_DATA14_MARK, VI4_DATA15_MARK, | ||
4023 | }; | ||
4024 | static const unsigned int vin4_data18_a_pins[] = { | ||
4025 | RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), | ||
4026 | RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), | ||
4027 | RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), | ||
4028 | RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), | ||
4029 | RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), | ||
4030 | RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), | ||
4031 | RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), | ||
4032 | RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), | ||
4033 | RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), | ||
4034 | }; | ||
4035 | static const unsigned int vin4_data18_a_mux[] = { | ||
4036 | VI4_DATA0_A_MARK, VI4_DATA1_A_MARK, | ||
4037 | VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, | ||
4038 | VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, | ||
4039 | VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, | ||
4040 | VI4_DATA8_MARK, VI4_DATA9_MARK, | ||
4041 | VI4_DATA10_MARK, VI4_DATA11_MARK, | ||
4042 | VI4_DATA12_MARK, VI4_DATA13_MARK, | ||
4043 | VI4_DATA14_MARK, VI4_DATA15_MARK, | ||
4044 | VI4_DATA16_MARK, VI4_DATA17_MARK, | ||
4045 | }; | ||
4046 | static const unsigned int vin4_data18_b_pins[] = { | ||
4047 | RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), | ||
4048 | RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), | ||
4049 | RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), | ||
4050 | RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), | ||
4051 | RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), | ||
4052 | RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), | ||
4053 | RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), | ||
4054 | RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), | ||
4055 | RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), | ||
4056 | }; | ||
4057 | static const unsigned int vin4_data18_b_mux[] = { | ||
4058 | VI4_DATA0_B_MARK, VI4_DATA1_B_MARK, | ||
4059 | VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, | ||
4060 | VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, | ||
4061 | VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, | ||
4062 | VI4_DATA8_MARK, VI4_DATA9_MARK, | ||
4063 | VI4_DATA10_MARK, VI4_DATA11_MARK, | ||
4064 | VI4_DATA12_MARK, VI4_DATA13_MARK, | ||
4065 | VI4_DATA14_MARK, VI4_DATA15_MARK, | ||
4066 | VI4_DATA16_MARK, VI4_DATA17_MARK, | ||
4067 | }; | ||
4068 | static const unsigned int vin4_data20_a_pins[] = { | ||
4069 | RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), | ||
4070 | RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), | ||
4071 | RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), | ||
4072 | RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), | ||
4073 | RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), | ||
4074 | RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), | ||
4075 | RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), | ||
4076 | RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), | ||
4077 | RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), | ||
4078 | RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), | ||
4079 | }; | ||
4080 | static const unsigned int vin4_data20_a_mux[] = { | ||
4081 | VI4_DATA0_A_MARK, VI4_DATA1_A_MARK, | ||
4082 | VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, | ||
4083 | VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, | ||
4084 | VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, | ||
4085 | VI4_DATA8_MARK, VI4_DATA9_MARK, | ||
4086 | VI4_DATA10_MARK, VI4_DATA11_MARK, | ||
4087 | VI4_DATA12_MARK, VI4_DATA13_MARK, | ||
4088 | VI4_DATA14_MARK, VI4_DATA15_MARK, | ||
4089 | VI4_DATA16_MARK, VI4_DATA17_MARK, | ||
4090 | VI4_DATA18_MARK, VI4_DATA19_MARK, | ||
4091 | }; | ||
4092 | static const unsigned int vin4_data20_b_pins[] = { | ||
4093 | RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), | ||
4094 | RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), | ||
4095 | RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), | ||
4096 | RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), | ||
4097 | RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), | ||
4098 | RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), | ||
4099 | RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), | ||
4100 | RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), | ||
4101 | RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), | ||
4102 | RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), | ||
4103 | }; | ||
4104 | static const unsigned int vin4_data20_b_mux[] = { | ||
4105 | VI4_DATA0_B_MARK, VI4_DATA1_B_MARK, | ||
4106 | VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, | ||
4107 | VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, | ||
4108 | VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, | ||
4109 | VI4_DATA8_MARK, VI4_DATA9_MARK, | ||
4110 | VI4_DATA10_MARK, VI4_DATA11_MARK, | ||
4111 | VI4_DATA12_MARK, VI4_DATA13_MARK, | ||
4112 | VI4_DATA14_MARK, VI4_DATA15_MARK, | ||
4113 | VI4_DATA16_MARK, VI4_DATA17_MARK, | ||
4114 | VI4_DATA18_MARK, VI4_DATA19_MARK, | ||
4115 | }; | ||
4116 | static const unsigned int vin4_data24_a_pins[] = { | ||
4117 | RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), | ||
4118 | RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), | ||
4119 | RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), | ||
4120 | RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), | ||
4121 | RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), | ||
4122 | RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), | ||
4123 | RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), | ||
4124 | RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), | ||
4125 | RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), | ||
4126 | RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), | ||
4127 | RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), | ||
4128 | RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), | ||
4129 | }; | ||
4130 | static const unsigned int vin4_data24_a_mux[] = { | ||
4131 | VI4_DATA0_A_MARK, VI4_DATA1_A_MARK, | ||
4132 | VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, | ||
4133 | VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, | ||
4134 | VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, | ||
4135 | VI4_DATA8_MARK, VI4_DATA9_MARK, | ||
4136 | VI4_DATA10_MARK, VI4_DATA11_MARK, | ||
4137 | VI4_DATA12_MARK, VI4_DATA13_MARK, | ||
4138 | VI4_DATA14_MARK, VI4_DATA15_MARK, | ||
4139 | VI4_DATA16_MARK, VI4_DATA17_MARK, | ||
4140 | VI4_DATA18_MARK, VI4_DATA19_MARK, | ||
4141 | VI4_DATA20_MARK, VI4_DATA21_MARK, | ||
4142 | VI4_DATA22_MARK, VI4_DATA23_MARK, | ||
4143 | }; | ||
4144 | static const unsigned int vin4_data24_b_pins[] = { | ||
4145 | RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), | ||
4146 | RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), | ||
4147 | RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), | ||
4148 | RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), | ||
4149 | RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), | ||
4150 | RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), | ||
4151 | RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), | ||
4152 | RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), | ||
4153 | RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), | ||
4154 | RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), | ||
4155 | RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), | ||
4156 | RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), | ||
4157 | }; | ||
4158 | static const unsigned int vin4_data24_b_mux[] = { | ||
4159 | VI4_DATA0_B_MARK, VI4_DATA1_B_MARK, | ||
4160 | VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, | ||
4161 | VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, | ||
4162 | VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, | ||
4163 | VI4_DATA8_MARK, VI4_DATA9_MARK, | ||
4164 | VI4_DATA10_MARK, VI4_DATA11_MARK, | ||
4165 | VI4_DATA12_MARK, VI4_DATA13_MARK, | ||
4166 | VI4_DATA14_MARK, VI4_DATA15_MARK, | ||
4167 | VI4_DATA16_MARK, VI4_DATA17_MARK, | ||
4168 | VI4_DATA18_MARK, VI4_DATA19_MARK, | ||
4169 | VI4_DATA20_MARK, VI4_DATA21_MARK, | ||
4170 | VI4_DATA22_MARK, VI4_DATA23_MARK, | ||
4171 | }; | ||
4172 | static const unsigned int vin4_sync_pins[] = { | ||
4173 | /* HSYNC#, VSYNC# */ | ||
4174 | RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 17), | ||
4175 | }; | ||
4176 | static const unsigned int vin4_sync_mux[] = { | ||
4177 | VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK, | ||
4178 | }; | ||
4179 | static const unsigned int vin4_field_pins[] = { | ||
4180 | /* FIELD */ | ||
4181 | RCAR_GP_PIN(1, 16), | ||
4182 | }; | ||
4183 | static const unsigned int vin4_field_mux[] = { | ||
4184 | VI4_FIELD_MARK, | ||
4185 | }; | ||
4186 | static const unsigned int vin4_clkenb_pins[] = { | ||
4187 | /* CLKENB */ | ||
4188 | RCAR_GP_PIN(1, 19), | ||
4189 | }; | ||
4190 | static const unsigned int vin4_clkenb_mux[] = { | ||
4191 | VI4_CLKENB_MARK, | ||
4192 | }; | ||
4193 | static const unsigned int vin4_clk_pins[] = { | ||
4194 | /* CLK */ | ||
4195 | RCAR_GP_PIN(1, 27), | ||
4196 | }; | ||
4197 | static const unsigned int vin4_clk_mux[] = { | ||
4198 | VI4_CLK_MARK, | ||
4199 | }; | ||
4200 | |||
4201 | /* - VIN5 ------------------------------------------------------------------- */ | ||
4202 | static const unsigned int vin5_data8_pins[] = { | ||
4203 | RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), | ||
4204 | RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), | ||
4205 | RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), | ||
4206 | RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), | ||
4207 | }; | ||
4208 | static const unsigned int vin5_data8_mux[] = { | ||
4209 | VI5_DATA0_MARK, VI5_DATA1_MARK, | ||
4210 | VI5_DATA2_MARK, VI5_DATA3_MARK, | ||
4211 | VI5_DATA4_MARK, VI5_DATA5_MARK, | ||
4212 | VI5_DATA6_MARK, VI5_DATA7_MARK, | ||
4213 | }; | ||
4214 | static const unsigned int vin5_data10_pins[] = { | ||
4215 | RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), | ||
4216 | RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), | ||
4217 | RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), | ||
4218 | RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), | ||
4219 | RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), | ||
4220 | }; | ||
4221 | static const unsigned int vin5_data10_mux[] = { | ||
4222 | VI5_DATA0_MARK, VI5_DATA1_MARK, | ||
4223 | VI5_DATA2_MARK, VI5_DATA3_MARK, | ||
4224 | VI5_DATA4_MARK, VI5_DATA5_MARK, | ||
4225 | VI5_DATA6_MARK, VI5_DATA7_MARK, | ||
4226 | VI5_DATA8_MARK, VI5_DATA9_MARK, | ||
4227 | }; | ||
4228 | static const unsigned int vin5_data12_pins[] = { | ||
4229 | RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), | ||
4230 | RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), | ||
4231 | RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), | ||
4232 | RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), | ||
4233 | RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), | ||
4234 | RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), | ||
4235 | }; | ||
4236 | static const unsigned int vin5_data12_mux[] = { | ||
4237 | VI5_DATA0_MARK, VI5_DATA1_MARK, | ||
4238 | VI5_DATA2_MARK, VI5_DATA3_MARK, | ||
4239 | VI5_DATA4_MARK, VI5_DATA5_MARK, | ||
4240 | VI5_DATA6_MARK, VI5_DATA7_MARK, | ||
4241 | VI5_DATA8_MARK, VI5_DATA9_MARK, | ||
4242 | VI5_DATA10_MARK, VI5_DATA11_MARK, | ||
4243 | }; | ||
4244 | static const unsigned int vin5_data16_pins[] = { | ||
4245 | RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), | ||
4246 | RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), | ||
4247 | RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), | ||
4248 | RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), | ||
4249 | RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), | ||
4250 | RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), | ||
4251 | RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), | ||
4252 | RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), | ||
4253 | }; | ||
4254 | static const unsigned int vin5_data16_mux[] = { | ||
4255 | VI5_DATA0_MARK, VI5_DATA1_MARK, | ||
4256 | VI5_DATA2_MARK, VI5_DATA3_MARK, | ||
4257 | VI5_DATA4_MARK, VI5_DATA5_MARK, | ||
4258 | VI5_DATA6_MARK, VI5_DATA7_MARK, | ||
4259 | VI5_DATA8_MARK, VI5_DATA9_MARK, | ||
4260 | VI5_DATA10_MARK, VI5_DATA11_MARK, | ||
4261 | VI5_DATA12_MARK, VI5_DATA13_MARK, | ||
4262 | VI5_DATA14_MARK, VI5_DATA15_MARK, | ||
4263 | }; | ||
4264 | static const unsigned int vin5_sync_pins[] = { | ||
4265 | /* HSYNC#, VSYNC# */ | ||
4266 | RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9), | ||
4267 | }; | ||
4268 | static const unsigned int vin5_sync_mux[] = { | ||
4269 | VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK, | ||
4270 | }; | ||
4271 | static const unsigned int vin5_field_pins[] = { | ||
4272 | RCAR_GP_PIN(1, 11), | ||
4273 | }; | ||
4274 | static const unsigned int vin5_field_mux[] = { | ||
4275 | /* FIELD */ | ||
4276 | VI5_FIELD_MARK, | ||
4277 | }; | ||
4278 | static const unsigned int vin5_clkenb_pins[] = { | ||
4279 | RCAR_GP_PIN(1, 20), | ||
4280 | }; | ||
4281 | static const unsigned int vin5_clkenb_mux[] = { | ||
4282 | /* CLKENB */ | ||
4283 | VI5_CLKENB_MARK, | ||
4284 | }; | ||
4285 | static const unsigned int vin5_clk_pins[] = { | ||
4286 | RCAR_GP_PIN(1, 21), | ||
4287 | }; | ||
4288 | static const unsigned int vin5_clk_mux[] = { | ||
4289 | /* CLK */ | ||
4290 | VI5_CLK_MARK, | ||
4291 | }; | ||
4292 | |||
3899 | static const struct sh_pfc_pin_group pinmux_groups[] = { | 4293 | static const struct sh_pfc_pin_group pinmux_groups[] = { |
3900 | SH_PFC_PIN_GROUP(audio_clk_a_a), | 4294 | SH_PFC_PIN_GROUP(audio_clk_a_a), |
3901 | SH_PFC_PIN_GROUP(audio_clk_a_b), | 4295 | SH_PFC_PIN_GROUP(audio_clk_a_b), |
@@ -4210,6 +4604,32 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { | |||
4210 | SH_PFC_PIN_GROUP(usb0), | 4604 | SH_PFC_PIN_GROUP(usb0), |
4211 | SH_PFC_PIN_GROUP(usb1), | 4605 | SH_PFC_PIN_GROUP(usb1), |
4212 | SH_PFC_PIN_GROUP(usb30), | 4606 | SH_PFC_PIN_GROUP(usb30), |
4607 | SH_PFC_PIN_GROUP(vin4_data8_a), | ||
4608 | SH_PFC_PIN_GROUP(vin4_data10_a), | ||
4609 | SH_PFC_PIN_GROUP(vin4_data12_a), | ||
4610 | SH_PFC_PIN_GROUP(vin4_data16_a), | ||
4611 | SH_PFC_PIN_GROUP(vin4_data18_a), | ||
4612 | SH_PFC_PIN_GROUP(vin4_data20_a), | ||
4613 | SH_PFC_PIN_GROUP(vin4_data24_a), | ||
4614 | SH_PFC_PIN_GROUP(vin4_data8_b), | ||
4615 | SH_PFC_PIN_GROUP(vin4_data10_b), | ||
4616 | SH_PFC_PIN_GROUP(vin4_data12_b), | ||
4617 | SH_PFC_PIN_GROUP(vin4_data16_b), | ||
4618 | SH_PFC_PIN_GROUP(vin4_data18_b), | ||
4619 | SH_PFC_PIN_GROUP(vin4_data20_b), | ||
4620 | SH_PFC_PIN_GROUP(vin4_data24_b), | ||
4621 | SH_PFC_PIN_GROUP(vin4_sync), | ||
4622 | SH_PFC_PIN_GROUP(vin4_field), | ||
4623 | SH_PFC_PIN_GROUP(vin4_clkenb), | ||
4624 | SH_PFC_PIN_GROUP(vin4_clk), | ||
4625 | SH_PFC_PIN_GROUP(vin5_data8), | ||
4626 | SH_PFC_PIN_GROUP(vin5_data10), | ||
4627 | SH_PFC_PIN_GROUP(vin5_data12), | ||
4628 | SH_PFC_PIN_GROUP(vin5_data16), | ||
4629 | SH_PFC_PIN_GROUP(vin5_sync), | ||
4630 | SH_PFC_PIN_GROUP(vin5_field), | ||
4631 | SH_PFC_PIN_GROUP(vin5_clkenb), | ||
4632 | SH_PFC_PIN_GROUP(vin5_clk), | ||
4213 | }; | 4633 | }; |
4214 | 4634 | ||
4215 | static const char * const audio_clk_groups[] = { | 4635 | static const char * const audio_clk_groups[] = { |
@@ -4672,6 +5092,38 @@ static const char * const usb30_groups[] = { | |||
4672 | "usb30", | 5092 | "usb30", |
4673 | }; | 5093 | }; |
4674 | 5094 | ||
5095 | static const char * const vin4_groups[] = { | ||
5096 | "vin4_data8_a", | ||
5097 | "vin4_data10_a", | ||
5098 | "vin4_data12_a", | ||
5099 | "vin4_data16_a", | ||
5100 | "vin4_data18_a", | ||
5101 | "vin4_data20_a", | ||
5102 | "vin4_data24_a", | ||
5103 | "vin4_data8_b", | ||
5104 | "vin4_data10_b", | ||
5105 | "vin4_data12_b", | ||
5106 | "vin4_data16_b", | ||
5107 | "vin4_data18_b", | ||
5108 | "vin4_data20_b", | ||
5109 | "vin4_data24_b", | ||
5110 | "vin4_sync", | ||
5111 | "vin4_field", | ||
5112 | "vin4_clkenb", | ||
5113 | "vin4_clk", | ||
5114 | }; | ||
5115 | |||
5116 | static const char * const vin5_groups[] = { | ||
5117 | "vin5_data8", | ||
5118 | "vin5_data10", | ||
5119 | "vin5_data12", | ||
5120 | "vin5_data16", | ||
5121 | "vin5_sync", | ||
5122 | "vin5_field", | ||
5123 | "vin5_clkenb", | ||
5124 | "vin5_clk", | ||
5125 | }; | ||
5126 | |||
4675 | static const struct sh_pfc_function pinmux_functions[] = { | 5127 | static const struct sh_pfc_function pinmux_functions[] = { |
4676 | SH_PFC_FUNCTION(audio_clk), | 5128 | SH_PFC_FUNCTION(audio_clk), |
4677 | SH_PFC_FUNCTION(avb), | 5129 | SH_PFC_FUNCTION(avb), |
@@ -4722,6 +5174,8 @@ static const struct sh_pfc_function pinmux_functions[] = { | |||
4722 | SH_PFC_FUNCTION(usb0), | 5174 | SH_PFC_FUNCTION(usb0), |
4723 | SH_PFC_FUNCTION(usb1), | 5175 | SH_PFC_FUNCTION(usb1), |
4724 | SH_PFC_FUNCTION(usb30), | 5176 | SH_PFC_FUNCTION(usb30), |
5177 | SH_PFC_FUNCTION(vin4), | ||
5178 | SH_PFC_FUNCTION(vin5), | ||
4725 | }; | 5179 | }; |
4726 | 5180 | ||
4727 | static const struct pinmux_cfg_reg pinmux_config_regs[] = { | 5181 | static const struct pinmux_cfg_reg pinmux_config_regs[] = { |