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authorChenglin Xu <chenglin.xu@mediatek.com>2017-10-18 04:28:48 -0400
committerMatthias Brugger <matthias.bgg@gmail.com>2017-10-20 05:54:39 -0400
commit69d0c060ac0cf61f25b35fb2c222c78168d04658 (patch)
treeb987dd20b00aa1ba6d4491bd7035f83a8190258f
parent68189ed59d34bf430790c026465b5489c7edad66 (diff)
soc: mediatek: pwrap: add support for MT7622 SoC
Add the registers, callbacks and data structures required to make the PMIC wrapper work on MT7622. Signed-off-by: Chenglin Xu <chenglin.xu@mediatek.com> Signed-off-by: Chen Zhong <chen.zhong@mediatek.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Diffstat
-rw-r--r--drivers/soc/mediatek/mtk-pmic-wrap.c170
1 files changed, 170 insertions, 0 deletions
diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
index cbc3f0e82337..5d61d127e1d7 100644
--- a/drivers/soc/mediatek/mtk-pmic-wrap.c
+++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
@@ -214,6 +214,36 @@ enum pwrap_regs {
214 PWRAP_ADC_RDATA_ADDR1, 214 PWRAP_ADC_RDATA_ADDR1,
215 PWRAP_ADC_RDATA_ADDR2, 215 PWRAP_ADC_RDATA_ADDR2,
216 216
217 /* MT7622 only regs */
218 PWRAP_EINT_STA0_ADR,
219 PWRAP_EINT_STA1_ADR,
220 PWRAP_STA,
221 PWRAP_CLR,
222 PWRAP_DVFS_ADR8,
223 PWRAP_DVFS_WDATA8,
224 PWRAP_DVFS_ADR9,
225 PWRAP_DVFS_WDATA9,
226 PWRAP_DVFS_ADR10,
227 PWRAP_DVFS_WDATA10,
228 PWRAP_DVFS_ADR11,
229 PWRAP_DVFS_WDATA11,
230 PWRAP_DVFS_ADR12,
231 PWRAP_DVFS_WDATA12,
232 PWRAP_DVFS_ADR13,
233 PWRAP_DVFS_WDATA13,
234 PWRAP_DVFS_ADR14,
235 PWRAP_DVFS_WDATA14,
236 PWRAP_DVFS_ADR15,
237 PWRAP_DVFS_WDATA15,
238 PWRAP_EXT_CK,
239 PWRAP_ADC_RDATA_ADDR,
240 PWRAP_GPS_STA,
241 PWRAP_SW_RST,
242 PWRAP_DVFS_STEP_CTRL0,
243 PWRAP_DVFS_STEP_CTRL1,
244 PWRAP_DVFS_STEP_CTRL2,
245 PWRAP_SPI2_CTRL,
246
217 /* MT8135 only regs */ 247 /* MT8135 only regs */
218 PWRAP_CSHEXT, 248 PWRAP_CSHEXT,
219 PWRAP_EVENT_IN_EN, 249 PWRAP_EVENT_IN_EN,
@@ -336,6 +366,118 @@ static int mt2701_regs[] = {
336 [PWRAP_ADC_RDATA_ADDR2] = 0x154, 366 [PWRAP_ADC_RDATA_ADDR2] = 0x154,
337}; 367};
338 368
369static int mt7622_regs[] = {
370 [PWRAP_MUX_SEL] = 0x0,
371 [PWRAP_WRAP_EN] = 0x4,
372 [PWRAP_DIO_EN] = 0x8,
373 [PWRAP_SIDLY] = 0xC,
374 [PWRAP_RDDMY] = 0x10,
375 [PWRAP_SI_CK_CON] = 0x14,
376 [PWRAP_CSHEXT_WRITE] = 0x18,
377 [PWRAP_CSHEXT_READ] = 0x1C,
378 [PWRAP_CSLEXT_START] = 0x20,
379 [PWRAP_CSLEXT_END] = 0x24,
380 [PWRAP_STAUPD_PRD] = 0x28,
381 [PWRAP_STAUPD_GRPEN] = 0x2C,
382 [PWRAP_EINT_STA0_ADR] = 0x30,
383 [PWRAP_EINT_STA1_ADR] = 0x34,
384 [PWRAP_STA] = 0x38,
385 [PWRAP_CLR] = 0x3C,
386 [PWRAP_STAUPD_MAN_TRIG] = 0x40,
387 [PWRAP_STAUPD_STA] = 0x44,
388 [PWRAP_WRAP_STA] = 0x48,
389 [PWRAP_HARB_INIT] = 0x4C,
390 [PWRAP_HARB_HPRIO] = 0x50,
391 [PWRAP_HIPRIO_ARB_EN] = 0x54,
392 [PWRAP_HARB_STA0] = 0x58,
393 [PWRAP_HARB_STA1] = 0x5C,
394 [PWRAP_MAN_EN] = 0x60,
395 [PWRAP_MAN_CMD] = 0x64,
396 [PWRAP_MAN_RDATA] = 0x68,
397 [PWRAP_MAN_VLDCLR] = 0x6C,
398 [PWRAP_WACS0_EN] = 0x70,
399 [PWRAP_INIT_DONE0] = 0x74,
400 [PWRAP_WACS0_CMD] = 0x78,
401 [PWRAP_WACS0_RDATA] = 0x7C,
402 [PWRAP_WACS0_VLDCLR] = 0x80,
403 [PWRAP_WACS1_EN] = 0x84,
404 [PWRAP_INIT_DONE1] = 0x88,
405 [PWRAP_WACS1_CMD] = 0x8C,
406 [PWRAP_WACS1_RDATA] = 0x90,
407 [PWRAP_WACS1_VLDCLR] = 0x94,
408 [PWRAP_WACS2_EN] = 0x98,
409 [PWRAP_INIT_DONE2] = 0x9C,
410 [PWRAP_WACS2_CMD] = 0xA0,
411 [PWRAP_WACS2_RDATA] = 0xA4,
412 [PWRAP_WACS2_VLDCLR] = 0xA8,
413 [PWRAP_INT_EN] = 0xAC,
414 [PWRAP_INT_FLG_RAW] = 0xB0,
415 [PWRAP_INT_FLG] = 0xB4,
416 [PWRAP_INT_CLR] = 0xB8,
417 [PWRAP_SIG_ADR] = 0xBC,
418 [PWRAP_SIG_MODE] = 0xC0,
419 [PWRAP_SIG_VALUE] = 0xC4,
420 [PWRAP_SIG_ERRVAL] = 0xC8,
421 [PWRAP_CRC_EN] = 0xCC,
422 [PWRAP_TIMER_EN] = 0xD0,
423 [PWRAP_TIMER_STA] = 0xD4,
424 [PWRAP_WDT_UNIT] = 0xD8,
425 [PWRAP_WDT_SRC_EN] = 0xDC,
426 [PWRAP_WDT_FLG] = 0xE0,
427 [PWRAP_DEBUG_INT_SEL] = 0xE4,
428 [PWRAP_DVFS_ADR0] = 0xE8,
429 [PWRAP_DVFS_WDATA0] = 0xEC,
430 [PWRAP_DVFS_ADR1] = 0xF0,
431 [PWRAP_DVFS_WDATA1] = 0xF4,
432 [PWRAP_DVFS_ADR2] = 0xF8,
433 [PWRAP_DVFS_WDATA2] = 0xFC,
434 [PWRAP_DVFS_ADR3] = 0x100,
435 [PWRAP_DVFS_WDATA3] = 0x104,
436 [PWRAP_DVFS_ADR4] = 0x108,
437 [PWRAP_DVFS_WDATA4] = 0x10C,
438 [PWRAP_DVFS_ADR5] = 0x110,
439 [PWRAP_DVFS_WDATA5] = 0x114,
440 [PWRAP_DVFS_ADR6] = 0x118,
441 [PWRAP_DVFS_WDATA6] = 0x11C,
442 [PWRAP_DVFS_ADR7] = 0x120,
443 [PWRAP_DVFS_WDATA7] = 0x124,
444 [PWRAP_DVFS_ADR8] = 0x128,
445 [PWRAP_DVFS_WDATA8] = 0x12C,
446 [PWRAP_DVFS_ADR9] = 0x130,
447 [PWRAP_DVFS_WDATA9] = 0x134,
448 [PWRAP_DVFS_ADR10] = 0x138,
449 [PWRAP_DVFS_WDATA10] = 0x13C,
450 [PWRAP_DVFS_ADR11] = 0x140,
451 [PWRAP_DVFS_WDATA11] = 0x144,
452 [PWRAP_DVFS_ADR12] = 0x148,
453 [PWRAP_DVFS_WDATA12] = 0x14C,
454 [PWRAP_DVFS_ADR13] = 0x150,
455 [PWRAP_DVFS_WDATA13] = 0x154,
456 [PWRAP_DVFS_ADR14] = 0x158,
457 [PWRAP_DVFS_WDATA14] = 0x15C,
458 [PWRAP_DVFS_ADR15] = 0x160,
459 [PWRAP_DVFS_WDATA15] = 0x164,
460 [PWRAP_SPMINF_STA] = 0x168,
461 [PWRAP_CIPHER_KEY_SEL] = 0x16C,
462 [PWRAP_CIPHER_IV_SEL] = 0x170,
463 [PWRAP_CIPHER_EN] = 0x174,
464 [PWRAP_CIPHER_RDY] = 0x178,
465 [PWRAP_CIPHER_MODE] = 0x17C,
466 [PWRAP_CIPHER_SWRST] = 0x180,
467 [PWRAP_DCM_EN] = 0x184,
468 [PWRAP_DCM_DBC_PRD] = 0x188,
469 [PWRAP_EXT_CK] = 0x18C,
470 [PWRAP_ADC_CMD_ADDR] = 0x190,
471 [PWRAP_PWRAP_ADC_CMD] = 0x194,
472 [PWRAP_ADC_RDATA_ADDR] = 0x198,
473 [PWRAP_GPS_STA] = 0x19C,
474 [PWRAP_SW_RST] = 0x1A0,
475 [PWRAP_DVFS_STEP_CTRL0] = 0x238,
476 [PWRAP_DVFS_STEP_CTRL1] = 0x23C,
477 [PWRAP_DVFS_STEP_CTRL2] = 0x240,
478 [PWRAP_SPI2_CTRL] = 0x244,
479};
480
339static int mt8173_regs[] = { 481static int mt8173_regs[] = {
340 [PWRAP_MUX_SEL] = 0x0, 482 [PWRAP_MUX_SEL] = 0x0,
341 [PWRAP_WRAP_EN] = 0x4, 483 [PWRAP_WRAP_EN] = 0x4,
@@ -499,6 +641,7 @@ enum pmic_type {
499 641
500enum pwrap_type { 642enum pwrap_type {
501 PWRAP_MT2701, 643 PWRAP_MT2701,
644 PWRAP_MT7622,
502 PWRAP_MT8135, 645 PWRAP_MT8135,
503 PWRAP_MT8173, 646 PWRAP_MT8173,
504}; 647};
@@ -927,6 +1070,9 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp)
927 case PWRAP_MT8173: 1070 case PWRAP_MT8173:
928 pwrap_writel(wrp, 1, PWRAP_CIPHER_EN); 1071 pwrap_writel(wrp, 1, PWRAP_CIPHER_EN);
929 break; 1072 break;
1073 case PWRAP_MT7622:
1074 pwrap_writel(wrp, 0, PWRAP_CIPHER_EN);
1075 break;
930 } 1076 }
931 1077
932 /* Config cipher mode @PMIC */ 1078 /* Config cipher mode @PMIC */
@@ -1071,6 +1217,15 @@ static int pwrap_mt2701_init_soc_specific(struct pmic_wrapper *wrp)
1071 return 0; 1217 return 0;
1072} 1218}
1073 1219
1220static int pwrap_mt7622_init_soc_specific(struct pmic_wrapper *wrp)
1221{
1222 pwrap_writel(wrp, 0, PWRAP_STAUPD_PRD);
1223 /* enable 2wire SPI master */
1224 pwrap_writel(wrp, 0x8000000, PWRAP_SPI2_CTRL);
1225
1226 return 0;
1227}
1228
1074static int pwrap_init(struct pmic_wrapper *wrp) 1229static int pwrap_init(struct pmic_wrapper *wrp)
1075{ 1230{
1076 int ret; 1231 int ret;
@@ -1242,6 +1397,18 @@ static const struct pmic_wrapper_type pwrap_mt2701 = {
1242 .init_soc_specific = pwrap_mt2701_init_soc_specific, 1397 .init_soc_specific = pwrap_mt2701_init_soc_specific,
1243}; 1398};
1244 1399
1400static const struct pmic_wrapper_type pwrap_mt7622 = {
1401 .regs = mt7622_regs,
1402 .type = PWRAP_MT7622,
1403 .arb_en_all = 0xff,
1404 .int_en_all = ~(u32)BIT(31),
1405 .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
1406 .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
1407 .has_bridge = 0,
1408 .init_reg_clock = pwrap_common_init_reg_clock,
1409 .init_soc_specific = pwrap_mt7622_init_soc_specific,
1410};
1411
1245static const struct pmic_wrapper_type pwrap_mt8135 = { 1412static const struct pmic_wrapper_type pwrap_mt8135 = {
1246 .regs = mt8135_regs, 1413 .regs = mt8135_regs,
1247 .type = PWRAP_MT8135, 1414 .type = PWRAP_MT8135,
@@ -1271,6 +1438,9 @@ static const struct of_device_id of_pwrap_match_tbl[] = {
1271 .compatible = "mediatek,mt2701-pwrap", 1438 .compatible = "mediatek,mt2701-pwrap",
1272 .data = &pwrap_mt2701, 1439 .data = &pwrap_mt2701,
1273 }, { 1440 }, {
1441 .compatible = "mediatek,mt7622-pwrap",
1442 .data = &pwrap_mt7622,
1443 }, {
1274 .compatible = "mediatek,mt8135-pwrap", 1444 .compatible = "mediatek,mt8135-pwrap",
1275 .data = &pwrap_mt8135, 1445 .data = &pwrap_mt8135,
1276 }, { 1446 }, {
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-19 06:39:33 -0400