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authorSean Wang <sean.wang@mediatek.com>2017-10-18 04:28:47 -0400
committerMatthias Brugger <matthias.bgg@gmail.com>2017-10-20 05:54:38 -0400
commit68189ed59d34bf430790c026465b5489c7edad66 (patch)
tree6dbc6cee9b72d387cc6c26ef1ea5495d36e1aa58
parent7f80f1007881f1d5c7c37010ecd435946b65061d (diff)
soc: mediatek: pwrap: add common way for setup CS timing extenstion
Multiple platforms would always use their own way handling CS timing extension on the bus which leads to a little bit code duplication. Therefore, the patch groups the similar logic to handle CS timing extension into the common function which allows the following SoCs have more reusability for configing CS timing. Signed-off-by: Chenglin Xu <chenglin.xu@mediatek.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
-rw-r--r--drivers/soc/mediatek/mtk-pmic-wrap.c59
1 files changed, 37 insertions, 22 deletions
diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
index 45c3e44d8f40..cbc3f0e82337 100644
--- a/drivers/soc/mediatek/mtk-pmic-wrap.c
+++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
@@ -827,23 +827,44 @@ static int pwrap_init_dual_io(struct pmic_wrapper *wrp)
827 return 0; 827 return 0;
828} 828}
829 829
830static int pwrap_mt8135_init_reg_clock(struct pmic_wrapper *wrp) 830/*
831 * pwrap_init_chip_select_ext is used to configure CS extension time for each
832 * phase during data transactions on the pwrap bus.
833 */
834static void pwrap_init_chip_select_ext(struct pmic_wrapper *wrp, u8 hext_write,
835 u8 hext_read, u8 lext_start,
836 u8 lext_end)
831{ 837{
832 pwrap_writel(wrp, 0x4, PWRAP_CSHEXT); 838 /*
833 pwrap_writel(wrp, 0x0, PWRAP_CSHEXT_WRITE); 839 * After finishing a write and read transaction, extends CS high time
834 pwrap_writel(wrp, 0x4, PWRAP_CSHEXT_READ); 840 * to be at least xT of BUS CLK as hext_write and hext_read specifies
835 pwrap_writel(wrp, 0x0, PWRAP_CSLEXT_START); 841 * respectively.
836 pwrap_writel(wrp, 0x0, PWRAP_CSLEXT_END); 842 */
843 pwrap_writel(wrp, hext_write, PWRAP_CSHEXT_WRITE);
844 pwrap_writel(wrp, hext_read, PWRAP_CSHEXT_READ);
837 845
838 return 0; 846 /*
847 * Extends CS low time after CSL and before CSH command to be at
848 * least xT of BUS CLK as lext_start and lext_end specifies
849 * respectively.
850 */
851 pwrap_writel(wrp, lext_start, PWRAP_CSLEXT_START);
852 pwrap_writel(wrp, lext_end, PWRAP_CSLEXT_END);
839} 853}
840 854
841static int pwrap_mt8173_init_reg_clock(struct pmic_wrapper *wrp) 855static int pwrap_common_init_reg_clock(struct pmic_wrapper *wrp)
842{ 856{
843 pwrap_writel(wrp, 0x0, PWRAP_CSHEXT_WRITE); 857 switch (wrp->master->type) {
844 pwrap_writel(wrp, 0x4, PWRAP_CSHEXT_READ); 858 case PWRAP_MT8173:
845 pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_START); 859 pwrap_init_chip_select_ext(wrp, 0, 4, 2, 2);
846 pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_END); 860 break;
861 case PWRAP_MT8135:
862 pwrap_writel(wrp, 0x4, PWRAP_CSHEXT);
863 pwrap_init_chip_select_ext(wrp, 0, 4, 0, 0);
864 break;
865 default:
866 break;
867 }
847 868
848 return 0; 869 return 0;
849} 870}
@@ -853,20 +874,14 @@ static int pwrap_mt2701_init_reg_clock(struct pmic_wrapper *wrp)
853 switch (wrp->slave->type) { 874 switch (wrp->slave->type) {
854 case PMIC_MT6397: 875 case PMIC_MT6397:
855 pwrap_writel(wrp, 0xc, PWRAP_RDDMY); 876 pwrap_writel(wrp, 0xc, PWRAP_RDDMY);
856 pwrap_writel(wrp, 0x4, PWRAP_CSHEXT_WRITE); 877 pwrap_init_chip_select_ext(wrp, 4, 0, 2, 2);
857 pwrap_writel(wrp, 0x0, PWRAP_CSHEXT_READ);
858 pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_START);
859 pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_END);
860 break; 878 break;
861 879
862 case PMIC_MT6323: 880 case PMIC_MT6323:
863 pwrap_writel(wrp, 0x8, PWRAP_RDDMY); 881 pwrap_writel(wrp, 0x8, PWRAP_RDDMY);
864 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_RDDMY_NO], 882 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_RDDMY_NO],
865 0x8); 883 0x8);
866 pwrap_writel(wrp, 0x5, PWRAP_CSHEXT_WRITE); 884 pwrap_init_chip_select_ext(wrp, 5, 0, 2, 2);
867 pwrap_writel(wrp, 0x0, PWRAP_CSHEXT_READ);
868 pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_START);
869 pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_END);
870 break; 885 break;
871 default: 886 default:
872 break; 887 break;
@@ -1235,7 +1250,7 @@ static const struct pmic_wrapper_type pwrap_mt8135 = {
1235 .spi_w = PWRAP_MAN_CMD_SPI_WRITE, 1250 .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
1236 .wdt_src = PWRAP_WDT_SRC_MASK_ALL, 1251 .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
1237 .has_bridge = 1, 1252 .has_bridge = 1,
1238 .init_reg_clock = pwrap_mt8135_init_reg_clock, 1253 .init_reg_clock = pwrap_common_init_reg_clock,
1239 .init_soc_specific = pwrap_mt8135_init_soc_specific, 1254 .init_soc_specific = pwrap_mt8135_init_soc_specific,
1240}; 1255};
1241 1256
@@ -1247,7 +1262,7 @@ static const struct pmic_wrapper_type pwrap_mt8173 = {
1247 .spi_w = PWRAP_MAN_CMD_SPI_WRITE, 1262 .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
1248 .wdt_src = PWRAP_WDT_SRC_MASK_NO_STAUPD, 1263 .wdt_src = PWRAP_WDT_SRC_MASK_NO_STAUPD,
1249 .has_bridge = 0, 1264 .has_bridge = 0,
1250 .init_reg_clock = pwrap_mt8173_init_reg_clock, 1265 .init_reg_clock = pwrap_common_init_reg_clock,
1251 .init_soc_specific = pwrap_mt8173_init_soc_specific, 1266 .init_soc_specific = pwrap_mt8173_init_soc_specific,
1252}; 1267};
1253 1268