diff options
author | Sean Wang <sean.wang@mediatek.com> | 2017-10-18 04:28:46 -0400 |
---|---|---|
committer | Matthias Brugger <matthias.bgg@gmail.com> | 2017-10-20 05:54:38 -0400 |
commit | 7f80f1007881f1d5c7c37010ecd435946b65061d (patch) | |
tree | 426eb7cff990db19a5c34595824bbb95e6f4848f | |
parent | d56b31e2eabfce7e41c3beb67be91f00a03d42ed (diff) |
soc: mediatek: pwrap: add MediaTek MT6380 as one slave of pwrap
Add MediaTek MT6380 regulator becoming one of PMIC wrapper slave
and also add extra new regmap_config of 32-bit mode for MT6380
since old regmap_config of 16-bit mode can't be fit into the need.
Signed-off-by: Chenglin Xu <chenglin.xu@mediatek.com>
Signed-off-by: Chen Zhong <chen.zhong@mediatek.com>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
-rw-r--r-- | drivers/soc/mediatek/mtk-pmic-wrap.c | 24 |
1 files changed, 21 insertions, 3 deletions
diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c index e3398e37a7a6..45c3e44d8f40 100644 --- a/drivers/soc/mediatek/mtk-pmic-wrap.c +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c | |||
@@ -507,6 +507,7 @@ struct pmic_wrapper; | |||
507 | struct pwrap_slv_type { | 507 | struct pwrap_slv_type { |
508 | const u32 *dew_regs; | 508 | const u32 *dew_regs; |
509 | enum pmic_type type; | 509 | enum pmic_type type; |
510 | const struct regmap_config *regmap; | ||
510 | /* Flags indicating the capability for the target slave */ | 511 | /* Flags indicating the capability for the target slave */ |
511 | u32 caps; | 512 | u32 caps; |
512 | /* | 513 | /* |
@@ -1149,7 +1150,7 @@ static irqreturn_t pwrap_interrupt(int irqno, void *dev_id) | |||
1149 | return IRQ_HANDLED; | 1150 | return IRQ_HANDLED; |
1150 | } | 1151 | } |
1151 | 1152 | ||
1152 | static const struct regmap_config pwrap_regmap_config = { | 1153 | static const struct regmap_config pwrap_regmap_config16 = { |
1153 | .reg_bits = 16, | 1154 | .reg_bits = 16, |
1154 | .val_bits = 16, | 1155 | .val_bits = 16, |
1155 | .reg_stride = 2, | 1156 | .reg_stride = 2, |
@@ -1158,9 +1159,19 @@ static const struct regmap_config pwrap_regmap_config = { | |||
1158 | .max_register = 0xffff, | 1159 | .max_register = 0xffff, |
1159 | }; | 1160 | }; |
1160 | 1161 | ||
1162 | static const struct regmap_config pwrap_regmap_config32 = { | ||
1163 | .reg_bits = 32, | ||
1164 | .val_bits = 32, | ||
1165 | .reg_stride = 4, | ||
1166 | .reg_read = pwrap_regmap_read, | ||
1167 | .reg_write = pwrap_regmap_write, | ||
1168 | .max_register = 0xffff, | ||
1169 | }; | ||
1170 | |||
1161 | static const struct pwrap_slv_type pmic_mt6323 = { | 1171 | static const struct pwrap_slv_type pmic_mt6323 = { |
1162 | .dew_regs = mt6323_regs, | 1172 | .dew_regs = mt6323_regs, |
1163 | .type = PMIC_MT6323, | 1173 | .type = PMIC_MT6323, |
1174 | .regmap = &pwrap_regmap_config16, | ||
1164 | .caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO | | 1175 | .caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO | |
1165 | PWRAP_SLV_CAP_SECURITY, | 1176 | PWRAP_SLV_CAP_SECURITY, |
1166 | .pwrap_read = pwrap_read16, | 1177 | .pwrap_read = pwrap_read16, |
@@ -1170,6 +1181,7 @@ static const struct pwrap_slv_type pmic_mt6323 = { | |||
1170 | static const struct pwrap_slv_type pmic_mt6380 = { | 1181 | static const struct pwrap_slv_type pmic_mt6380 = { |
1171 | .dew_regs = NULL, | 1182 | .dew_regs = NULL, |
1172 | .type = PMIC_MT6380, | 1183 | .type = PMIC_MT6380, |
1184 | .regmap = &pwrap_regmap_config32, | ||
1173 | .caps = 0, | 1185 | .caps = 0, |
1174 | .pwrap_read = pwrap_read32, | 1186 | .pwrap_read = pwrap_read32, |
1175 | .pwrap_write = pwrap_write32, | 1187 | .pwrap_write = pwrap_write32, |
@@ -1178,6 +1190,7 @@ static const struct pwrap_slv_type pmic_mt6380 = { | |||
1178 | static const struct pwrap_slv_type pmic_mt6397 = { | 1190 | static const struct pwrap_slv_type pmic_mt6397 = { |
1179 | .dew_regs = mt6397_regs, | 1191 | .dew_regs = mt6397_regs, |
1180 | .type = PMIC_MT6397, | 1192 | .type = PMIC_MT6397, |
1193 | .regmap = &pwrap_regmap_config16, | ||
1181 | .caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO | | 1194 | .caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO | |
1182 | PWRAP_SLV_CAP_SECURITY, | 1195 | PWRAP_SLV_CAP_SECURITY, |
1183 | .pwrap_read = pwrap_read16, | 1196 | .pwrap_read = pwrap_read16, |
@@ -1189,9 +1202,14 @@ static const struct of_device_id of_slave_match_tbl[] = { | |||
1189 | .compatible = "mediatek,mt6323", | 1202 | .compatible = "mediatek,mt6323", |
1190 | .data = &pmic_mt6323, | 1203 | .data = &pmic_mt6323, |
1191 | }, { | 1204 | }, { |
1205 | /* The MT6380 PMIC only implements a regulator, so we bind it | ||
1206 | * directly instead of using a MFD. | ||
1207 | */ | ||
1208 | .compatible = "mediatek,mt6380-regulator", | ||
1209 | .data = &pmic_mt6380, | ||
1210 | }, { | ||
1192 | .compatible = "mediatek,mt6397", | 1211 | .compatible = "mediatek,mt6397", |
1193 | .data = &pmic_mt6397, | 1212 | .data = &pmic_mt6397, |
1194 | }, { | ||
1195 | /* sentinel */ | 1213 | /* sentinel */ |
1196 | } | 1214 | } |
1197 | }; | 1215 | }; |
@@ -1372,7 +1390,7 @@ static int pwrap_probe(struct platform_device *pdev) | |||
1372 | if (ret) | 1390 | if (ret) |
1373 | goto err_out2; | 1391 | goto err_out2; |
1374 | 1392 | ||
1375 | wrp->regmap = devm_regmap_init(wrp->dev, NULL, wrp, &pwrap_regmap_config); | 1393 | wrp->regmap = devm_regmap_init(wrp->dev, NULL, wrp, wrp->slave->regmap); |
1376 | if (IS_ERR(wrp->regmap)) { | 1394 | if (IS_ERR(wrp->regmap)) { |
1377 | ret = PTR_ERR(wrp->regmap); | 1395 | ret = PTR_ERR(wrp->regmap); |
1378 | goto err_out2; | 1396 | goto err_out2; |