diff options
author | Joel Fernandes <joelf@ti.com> | 2016-10-18 03:55:22 -0400 |
---|---|---|
committer | Tony Lindgren <tony@atomide.com> | 2016-11-09 17:35:17 -0500 |
commit | 628d758731693ef3bfd883279b86a3350d1e553c (patch) | |
tree | 6ca4a24b4f5c3c5114d9b89f7f2097c9832943f0 | |
parent | c311864310ae04fe6c6588911f62fa747984864a (diff) |
ARM: DRA7: hwmod: Add data for AES IP
DRA7 SoC contains AES crypto hardware accelerator. Add hwmod data for
this IP so that it can be utilized by crypto frameworks.
Signed-off-by: Joel Fernandes <joelf@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
[t-kristo@ti.com: squash in support for both AES1 and AES2 cores]
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
-rw-r--r-- | arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 62 |
1 files changed, 62 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c index e89a7ecdc567..4988a9e1d3d3 100644 --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c | |||
@@ -690,6 +690,50 @@ static struct omap_hwmod dra7xx_dss_hdmi_hwmod = { | |||
690 | .parent_hwmod = &dra7xx_dss_hwmod, | 690 | .parent_hwmod = &dra7xx_dss_hwmod, |
691 | }; | 691 | }; |
692 | 692 | ||
693 | /* AES (the 'P' (public) device) */ | ||
694 | static struct omap_hwmod_class_sysconfig dra7xx_aes_sysc = { | ||
695 | .rev_offs = 0x0080, | ||
696 | .sysc_offs = 0x0084, | ||
697 | .syss_offs = 0x0088, | ||
698 | .sysc_flags = SYSS_HAS_RESET_STATUS, | ||
699 | }; | ||
700 | |||
701 | static struct omap_hwmod_class dra7xx_aes_hwmod_class = { | ||
702 | .name = "aes", | ||
703 | .sysc = &dra7xx_aes_sysc, | ||
704 | .rev = 2, | ||
705 | }; | ||
706 | |||
707 | /* AES1 */ | ||
708 | static struct omap_hwmod dra7xx_aes1_hwmod = { | ||
709 | .name = "aes1", | ||
710 | .class = &dra7xx_aes_hwmod_class, | ||
711 | .clkdm_name = "l4sec_clkdm", | ||
712 | .main_clk = "l3_iclk_div", | ||
713 | .prcm = { | ||
714 | .omap4 = { | ||
715 | .clkctrl_offs = DRA7XX_CM_L4SEC_AES1_CLKCTRL_OFFSET, | ||
716 | .context_offs = DRA7XX_RM_L4SEC_AES1_CONTEXT_OFFSET, | ||
717 | .modulemode = MODULEMODE_HWCTRL, | ||
718 | }, | ||
719 | }, | ||
720 | }; | ||
721 | |||
722 | /* AES2 */ | ||
723 | static struct omap_hwmod dra7xx_aes2_hwmod = { | ||
724 | .name = "aes2", | ||
725 | .class = &dra7xx_aes_hwmod_class, | ||
726 | .clkdm_name = "l4sec_clkdm", | ||
727 | .main_clk = "l3_iclk_div", | ||
728 | .prcm = { | ||
729 | .omap4 = { | ||
730 | .clkctrl_offs = DRA7XX_CM_L4SEC_AES2_CLKCTRL_OFFSET, | ||
731 | .context_offs = DRA7XX_RM_L4SEC_AES2_CONTEXT_OFFSET, | ||
732 | .modulemode = MODULEMODE_HWCTRL, | ||
733 | }, | ||
734 | }, | ||
735 | }; | ||
736 | |||
693 | /* | 737 | /* |
694 | * 'elm' class | 738 | * 'elm' class |
695 | * | 739 | * |
@@ -2957,6 +3001,22 @@ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = { | |||
2957 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 3001 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2958 | }; | 3002 | }; |
2959 | 3003 | ||
3004 | /* l3_main_1 -> aes1 */ | ||
3005 | static struct omap_hwmod_ocp_if dra7xx_l3_main_1__aes1 = { | ||
3006 | .master = &dra7xx_l3_main_1_hwmod, | ||
3007 | .slave = &dra7xx_aes1_hwmod, | ||
3008 | .clk = "l3_iclk_div", | ||
3009 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
3010 | }; | ||
3011 | |||
3012 | /* l3_main_1 -> aes2 */ | ||
3013 | static struct omap_hwmod_ocp_if dra7xx_l3_main_1__aes2 = { | ||
3014 | .master = &dra7xx_l3_main_1_hwmod, | ||
3015 | .slave = &dra7xx_aes2_hwmod, | ||
3016 | .clk = "l3_iclk_div", | ||
3017 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
3018 | }; | ||
3019 | |||
2960 | /* l4_per2 -> mcasp1 */ | 3020 | /* l4_per2 -> mcasp1 */ |
2961 | static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp1 = { | 3021 | static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp1 = { |
2962 | .master = &dra7xx_l4_per2_hwmod, | 3022 | .master = &dra7xx_l4_per2_hwmod, |
@@ -3836,6 +3896,8 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = { | |||
3836 | &dra7xx_l3_main_1__dss, | 3896 | &dra7xx_l3_main_1__dss, |
3837 | &dra7xx_l3_main_1__dispc, | 3897 | &dra7xx_l3_main_1__dispc, |
3838 | &dra7xx_l3_main_1__hdmi, | 3898 | &dra7xx_l3_main_1__hdmi, |
3899 | &dra7xx_l3_main_1__aes1, | ||
3900 | &dra7xx_l3_main_1__aes2, | ||
3839 | &dra7xx_l4_per1__elm, | 3901 | &dra7xx_l4_per1__elm, |
3840 | &dra7xx_l4_wkup__gpio1, | 3902 | &dra7xx_l4_wkup__gpio1, |
3841 | &dra7xx_l4_per1__gpio2, | 3903 | &dra7xx_l4_per1__gpio2, |