Merge tag 'drm-fixes-for-v4.15-rc2' of git://people.freedesktop.org/~airlied/linux

Pull drm fixes and cleanups from Dave Airlie:
 "The main thing are a bunch of fixes for the new amd display code, a
  bunch of smatch fixes.

  core:
   - Atomic helper regression fix.
   - Deferred fbdev fallout regression fix.

  amdgpu:
   - New display code (dc) dpms, suspend/resume and smatch fixes, along
     with some others
   - Some regression fixes for amdkfd/radeon.
   - Fix a ttm regression for swiotlb disabled

  bridge:
   - A bunch of fixes for the tc358767 bridge

  mali-dp + hdlcd:
   - some fixes and internal API catchups.

  imx-drm:
   -regression fix in atomic code.

  omapdrm:
   - platform detection regression fixes"

* tag 'drm-fixes-for-v4.15-rc2' of git://people.freedesktop.org/~airlied/linux: (76 commits)
  drm/imx: always call wait_for_flip_done in commit_tail
  omapdrm: hdmi4_cec: signedness bug in hdmi4_cec_init()
  drm: omapdrm: Fix DPI on platforms using the DSI VDDS
  omapdrm: hdmi4: Correct the SoC revision matching
  drm/omap: displays: panel-dpi: add backlight dependency
  drm/omap: Fix error handling path in 'omap_dmm_probe()'
  drm/i915: Disable THP until we have a GPU read BW W/A
  drm/bridge: tc358767: fix 1-lane behavior
  drm/bridge: tc358767: fix AUXDATAn registers access
  drm/bridge: tc358767: fix timing calculations
  drm/bridge: tc358767: fix DP0_MISC register set
  drm/bridge: tc358767: filter out too high modes
  drm/bridge: tc358767: do no fail on hi-res displays
  drm/bridge: Fix lvds-encoder since the panel_bridge rework.
  drm/bridge: synopsys/dw-hdmi: Enable cec clock
  drm/bridge: adv7511/33: Fix adv7511_cec_init() failure handling
  drm/radeon: remove init of CIK VMIDs 8-16 for amdkfd
  drm/ttm: fix populate_and_map() functions once more
  drm/fb_helper: Disable all crtc's when initial setup fails.
  drm/atomic: make drm_atomic_helper_wait_for_vblanks more agressive
  ...

67 files changed, 814 insertions, 483 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 5afaf6016b4a..0b14b5373783 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -717,7 +717,7 @@ int amdgpu_queue_mgr_fini(struct amdgpu_device *adev,
                           struct amdgpu_queue_mgr *mgr);
 int amdgpu_queue_mgr_map(struct amdgpu_device *adev,
                          struct amdgpu_queue_mgr *mgr,
-                         int hw_ip, int instance, int ring,
+                         u32 hw_ip, u32 instance, u32 ring,
                          struct amdgpu_ring **out_ring);
 
 /*
@@ -1572,18 +1572,14 @@ struct amdgpu_device {
         /* sdma */
         struct amdgpu_sdma              sdma;
 
-        union {
-                struct {
-                        /* uvd */
-                        struct amdgpu_uvd               uvd;
+        /* uvd */
+        struct amdgpu_uvd               uvd;
 
-                        /* vce */
-                        struct amdgpu_vce               vce;
-                };
+        /* vce */
+        struct amdgpu_vce               vce;
 
-                /* vcn */
-                struct amdgpu_vcn               vcn;
-        };
+        /* vcn */
+        struct amdgpu_vcn               vcn;
 
         /* firmwares */
         struct amdgpu_firmware          firmware;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
index 47d1c132ac40..1e3e9be7d77e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
@@ -379,29 +379,50 @@ static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd)
 {
         struct amdgpu_device *adev = get_amdgpu_device(kgd);
         struct cik_sdma_rlc_registers *m;
+        unsigned long end_jiffies;
         uint32_t sdma_base_addr;
+        uint32_t data;
 
         m = get_sdma_mqd(mqd);
         sdma_base_addr = get_sdma_base_addr(m);
 
-        WREG32(sdma_base_addr + mmSDMA0_RLC0_VIRTUAL_ADDR,
-                        m->sdma_rlc_virtual_addr);
+        WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
+                m->sdma_rlc_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK));
 
-        WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE,
-                        m->sdma_rlc_rb_base);
+        end_jiffies = msecs_to_jiffies(2000) + jiffies;
+        while (true) {
+                data = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
+                if (data & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
+                        break;
+                if (time_after(jiffies, end_jiffies))
+                        return -ETIME;
+                usleep_range(500, 1000);
+        }
+        if (m->sdma_engine_id) {
+                data = RREG32(mmSDMA1_GFX_CONTEXT_CNTL);
+                data = REG_SET_FIELD(data, SDMA1_GFX_CONTEXT_CNTL,
+                                RESUME_CTX, 0);
+                WREG32(mmSDMA1_GFX_CONTEXT_CNTL, data);
+        } else {
+                data = RREG32(mmSDMA0_GFX_CONTEXT_CNTL);
+                data = REG_SET_FIELD(data, SDMA0_GFX_CONTEXT_CNTL,
+                                RESUME_CTX, 0);
+                WREG32(mmSDMA0_GFX_CONTEXT_CNTL, data);
+        }
 
+        WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL,
+                                m->sdma_rlc_doorbell);
+        WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, 0);
+        WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, 0);
+        WREG32(sdma_base_addr + mmSDMA0_RLC0_VIRTUAL_ADDR,
+                                m->sdma_rlc_virtual_addr);
+        WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE, m->sdma_rlc_rb_base);
         WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE_HI,
                         m->sdma_rlc_rb_base_hi);
-
         WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_LO,
                         m->sdma_rlc_rb_rptr_addr_lo);
-
         WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_HI,
                         m->sdma_rlc_rb_rptr_addr_hi);
-
-        WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL,
-                        m->sdma_rlc_doorbell);
-
         WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
                         m->sdma_rlc_rb_cntl);
 
@@ -574,9 +595,9 @@ static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
         }
 
         WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, 0);
-        WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, 0);
-        WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, 0);
-        WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE, 0);
+        WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
+                RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL) |
+                SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK);
 
         return 0;
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index a57cec737c18..57abf7abd7a9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -409,6 +409,10 @@ static bool amdgpu_cs_try_evict(struct amdgpu_cs_parser *p,
                 if (candidate->robj == validated)
                         break;
 
+                /* We can't move pinned BOs here */
+                if (bo->pin_count)
+                        continue;
+
                 other = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
 
                 /* Check if this BO is in one of the domains we need space for */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 2c574374d9b6..3573ecdb06ee 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1837,9 +1837,6 @@ static int amdgpu_fini(struct amdgpu_device *adev)
                 adev->ip_blocks[i].status.hw = false;
         }
 
-        if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU)
-                amdgpu_ucode_fini_bo(adev);
-
         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
                 if (!adev->ip_blocks[i].status.sw)
                         continue;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index ec96bb1f9eaf..c2f414ffb2cc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -536,7 +536,7 @@ static const struct pci_device_id pciidlist[] = {
         {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
         {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
         /* Raven */
-        {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU|AMD_EXP_HW_SUPPORT},
+        {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU},
 
         {0, 0, 0}
 };
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
index 033fba2def6f..5f5aa5fddc16 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
@@ -164,6 +164,9 @@ static int amdgpu_pp_hw_fini(void *handle)
                 ret = adev->powerplay.ip_funcs->hw_fini(
                                         adev->powerplay.pp_handle);
 
+        if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU)
+                amdgpu_ucode_fini_bo(adev);
+
         return ret;
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 7714f4a6c8b0..447d446b5015 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -442,6 +442,8 @@ static int psp_hw_fini(void *handle)
         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
                 return 0;
 
+        amdgpu_ucode_fini_bo(adev);
+
         psp_ring_destroy(psp, PSP_RING_TYPE__KM);
 
         amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c
index 190e28cb827e..93d86619e802 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c
@@ -63,7 +63,7 @@ static int amdgpu_update_cached_map(struct amdgpu_queue_mapper *mapper,
 
 static int amdgpu_identity_map(struct amdgpu_device *adev,
                                struct amdgpu_queue_mapper *mapper,
-                               int ring,
+                               u32 ring,
                                struct amdgpu_ring **out_ring)
 {
         switch (mapper->hw_ip) {
@@ -121,7 +121,7 @@ static enum amdgpu_ring_type amdgpu_hw_ip_to_ring_type(int hw_ip)
 
 static int amdgpu_lru_map(struct amdgpu_device *adev,
                           struct amdgpu_queue_mapper *mapper,
-                          int user_ring, bool lru_pipe_order,
+                          u32 user_ring, bool lru_pipe_order,
                           struct amdgpu_ring **out_ring)
 {
         int r, i, j;
@@ -208,7 +208,7 @@ int amdgpu_queue_mgr_fini(struct amdgpu_device *adev,
  */
 int amdgpu_queue_mgr_map(struct amdgpu_device *adev,
                          struct amdgpu_queue_mgr *mgr,
-                         int hw_ip, int instance, int ring,
+                         u32 hw_ip, u32 instance, u32 ring,
                          struct amdgpu_ring **out_ring)
 {
         int r, ip_num_rings;
diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
index 793b1470284d..a296f7bbe57c 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
@@ -1023,22 +1023,101 @@ static const struct amdgpu_allowed_register_entry cik_allowed_read_registers[] =
         {mmPA_SC_RASTER_CONFIG_1, true},
 };
 
-static uint32_t cik_read_indexed_register(struct amdgpu_device *adev,
-                                          u32 se_num, u32 sh_num,
-                                          u32 reg_offset)
+
+static uint32_t cik_get_register_value(struct amdgpu_device *adev,
+                                       bool indexed, u32 se_num,
+                                       u32 sh_num, u32 reg_offset)
 {
-        uint32_t val;
+        if (indexed) {
+                uint32_t val;
+                unsigned se_idx = (se_num == 0xffffffff) ? 0 : se_num;
+                unsigned sh_idx = (sh_num == 0xffffffff) ? 0 : sh_num;
+
+                switch (reg_offset) {
+                case mmCC_RB_BACKEND_DISABLE:
+                        return adev->gfx.config.rb_config[se_idx][sh_idx].rb_backend_disable;
+                case mmGC_USER_RB_BACKEND_DISABLE:
+                        return adev->gfx.config.rb_config[se_idx][sh_idx].user_rb_backend_disable;
+                case mmPA_SC_RASTER_CONFIG:
+                        return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config;
+                case mmPA_SC_RASTER_CONFIG_1:
+                        return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config_1;
+                }
 
-        mutex_lock(&adev->grbm_idx_mutex);
-        if (se_num != 0xffffffff || sh_num != 0xffffffff)
-                amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
+                mutex_lock(&adev->grbm_idx_mutex);
+                if (se_num != 0xffffffff || sh_num != 0xffffffff)
+                        amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
 
-        val = RREG32(reg_offset);
+                val = RREG32(reg_offset);
 
-        if (se_num != 0xffffffff || sh_num != 0xffffffff)
-                amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
-        mutex_unlock(&adev->grbm_idx_mutex);
-        return val;
+                if (se_num != 0xffffffff || sh_num != 0xffffffff)
+                        amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
+                mutex_unlock(&adev->grbm_idx_mutex);
+                return val;
+        } else {
+                unsigned idx;
+
+                switch (reg_offset) {
+                case mmGB_ADDR_CONFIG:
+                        return adev->gfx.config.gb_addr_config;
+                case mmMC_ARB_RAMCFG:
+                        return adev->gfx.config.mc_arb_ramcfg;
+                case mmGB_TILE_MODE0:
+                case mmGB_TILE_MODE1:
+                case mmGB_TILE_MODE2:
+                case mmGB_TILE_MODE3:
+                case mmGB_TILE_MODE4:
+                case mmGB_TILE_MODE5:
+                case mmGB_TILE_MODE6:
+                case mmGB_TILE_MODE7:
+                case mmGB_TILE_MODE8:
+                case mmGB_TILE_MODE9:
+                case mmGB_TILE_MODE10:
+                case mmGB_TILE_MODE11:
+                case mmGB_TILE_MODE12:
+                case mmGB_TILE_MODE13:
+                case mmGB_TILE_MODE14:
+                case mmGB_TILE_MODE15:
+                case mmGB_TILE_MODE16:
+                case mmGB_TILE_MODE17:
+                case mmGB_TILE_MODE18:
+                case mmGB_TILE_MODE19:
+                case mmGB_TILE_MODE20:
+                case mmGB_TILE_MODE21:
+                case mmGB_TILE_MODE22:
+                case mmGB_TILE_MODE23:
+                case mmGB_TILE_MODE24:
+                case mmGB_TILE_MODE25:
+                case mmGB_TILE_MODE26:
+                case mmGB_TILE_MODE27:
+                case mmGB_TILE_MODE28:
+                case mmGB_TILE_MODE29:
+                case mmGB_TILE_MODE30:
+                case mmGB_TILE_MODE31:
+                        idx = (reg_offset - mmGB_TILE_MODE0);
+                        return adev->gfx.config.tile_mode_array[idx];
+                case mmGB_MACROTILE_MODE0:
+                case mmGB_MACROTILE_MODE1:
+                case mmGB_MACROTILE_MODE2:
+                case mmGB_MACROTILE_MODE3:
+                case mmGB_MACROTILE_MODE4:
+                case mmGB_MACROTILE_MODE5:
+                case mmGB_MACROTILE_MODE6:
+                case mmGB_MACROTILE_MODE7:
+                case mmGB_MACROTILE_MODE8:
+                case mmGB_MACROTILE_MODE9:
+                case mmGB_MACROTILE_MODE10:
+                case mmGB_MACROTILE_MODE11:
+                case mmGB_MACROTILE_MODE12:
+                case mmGB_MACROTILE_MODE13:
+                case mmGB_MACROTILE_MODE14:
+                case mmGB_MACROTILE_MODE15:
+                        idx = (reg_offset - mmGB_MACROTILE_MODE0);
+                        return adev->gfx.config.macrotile_mode_array[idx];
+                default:
+                        return RREG32(reg_offset);
+                }
+        }
 }
 
 static int cik_read_register(struct amdgpu_device *adev, u32 se_num,
@@ -1048,13 +1127,13 @@ static int cik_read_register(struct amdgpu_device *adev, u32 se_num,
 
         *value = 0;
         for (i = 0; i < ARRAY_SIZE(cik_allowed_read_registers); i++) {
+                bool indexed = cik_allowed_read_registers[i].grbm_indexed;
+
                 if (reg_offset != cik_allowed_read_registers[i].reg_offset)
                         continue;
 
-                *value = cik_allowed_read_registers[i].grbm_indexed ?
-                         cik_read_indexed_register(adev, se_num,
-                                                   sh_num, reg_offset) :
-                         RREG32(reg_offset);
+                *value = cik_get_register_value(adev, indexed, se_num, sh_num,
+                                                reg_offset);
                 return 0;
         }
         return -EINVAL;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index 5c8a7a48a4ad..419ba0ce7ee5 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -1819,6 +1819,22 @@ static void gfx_v7_0_setup_rb(struct amdgpu_device *adev)
                                                         adev->gfx.config.backend_enable_mask,
                                                         num_rb_pipes);
         }
+
+        /* cache the values for userspace */
+        for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
+                for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
+                        gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff);
+                        adev->gfx.config.rb_config[i][j].rb_backend_disable =
+                                RREG32(mmCC_RB_BACKEND_DISABLE);
+                        adev->gfx.config.rb_config[i][j].user_rb_backend_disable =
+                                RREG32(mmGC_USER_RB_BACKEND_DISABLE);
+                        adev->gfx.config.rb_config[i][j].raster_config =
+                                RREG32(mmPA_SC_RASTER_CONFIG);
+                        adev->gfx.config.rb_config[i][j].raster_config_1 =
+                                RREG32(mmPA_SC_RASTER_CONFIG_1);
+                }
+        }
+        gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
         mutex_unlock(&adev->grbm_idx_mutex);
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 1eb4d79d6e30..0450ac5ba6b6 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -1175,7 +1175,7 @@ static const struct amdgpu_irq_src_funcs vcn_v1_0_irq_funcs = {
 
 static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev)
 {
-        adev->uvd.irq.num_types = adev->vcn.num_enc_rings + 1;
+        adev->vcn.irq.num_types = adev->vcn.num_enc_rings + 1;
         adev->vcn.irq.funcs = &vcn_v1_0_irq_funcs;
 }
 
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_module.c b/drivers/gpu/drm/amd/amdkfd/kfd_module.c
index 6c5a9cab55de..f744caeaee04 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_module.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_module.c
@@ -24,6 +24,7 @@
 #include <linux/sched.h>
 #include <linux/moduleparam.h>
 #include <linux/device.h>
+#include <linux/printk.h>
 #include "kfd_priv.h"
 
 #define KFD_DRIVER_AUTHOR       "AMD Inc. and others"
@@ -132,7 +133,7 @@ static void __exit kfd_module_exit(void)
         kfd_process_destroy_wq();
         kfd_topology_shutdown();
         kfd_chardev_exit();
-        dev_info(kfd_device, "Removed module\n");
+        pr_info("amdkfd: Removed module\n");
 }
 
 module_init(kfd_module_init);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
index 4859d263fa2a..4728fad3fd74 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
@@ -202,8 +202,8 @@ static int update_mqd_sdma(struct mqd_manager *mm, void *mqd,
         struct cik_sdma_rlc_registers *m;
 
         m = get_sdma_mqd(mqd);
-        m->sdma_rlc_rb_cntl = ffs(q->queue_size / sizeof(unsigned int)) <<
-                        SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT |
+        m->sdma_rlc_rb_cntl = (ffs(q->queue_size / sizeof(unsigned int)) - 1)
+                        << SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT |
                         q->vmid << SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT |
                         1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT |
                         6 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
index 2bec902fc939..a3f1e62c60ba 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
@@ -191,6 +191,24 @@ int pqm_create_queue(struct process_queue_manager *pqm,
 
         switch (type) {
         case KFD_QUEUE_TYPE_SDMA:
+                if (dev->dqm->queue_count >=
+                        CIK_SDMA_QUEUES_PER_ENGINE * CIK_SDMA_ENGINE_NUM) {
+                        pr_err("Over-subscription is not allowed for SDMA.\n");
+                        retval = -EPERM;
+                        goto err_create_queue;
+                }
+
+                retval = create_cp_queue(pqm, dev, &q, properties, f, *qid);
+                if (retval != 0)
+                        goto err_create_queue;
+                pqn->q = q;
+                pqn->kq = NULL;
+                retval = dev->dqm->ops.create_queue(dev->dqm, q, &pdd->qpd,
+                                                &q->properties.vmid);
+                pr_debug("DQM returned %d for create_queue\n", retval);
+                print_queue(q);
+                break;
+
         case KFD_QUEUE_TYPE_COMPUTE:
                 /* check if there is over subscription */
                 if ((sched_policy == KFD_SCHED_POLICY_HWS_NO_OVERSUBSCRIPTION) &&
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 889ed24084e8..f71fe6d2ddda 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -520,7 +520,8 @@ static int detect_mst_link_for_all_connectors(struct drm_device *dev)
 
         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
                 aconnector = to_amdgpu_dm_connector(connector);
-                if (aconnector->dc_link->type == dc_connection_mst_branch) {
+                if (aconnector->dc_link->type == dc_connection_mst_branch &&
+                    aconnector->mst_mgr.aux) {
                         DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
                                         aconnector, aconnector->base.base.id);
 
@@ -677,6 +678,10 @@ int amdgpu_dm_display_resume(struct amdgpu_device *adev)
 
                 mutex_lock(&aconnector->hpd_lock);
                 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
+
+                if (aconnector->fake_enable && aconnector->dc_link->local_sink)
+                        aconnector->fake_enable = false;
+
                 aconnector->dc_sink = NULL;
                 amdgpu_dm_update_connector_after_detect(aconnector);
                 mutex_unlock(&aconnector->hpd_lock);
@@ -711,7 +716,6 @@ int amdgpu_dm_display_resume(struct amdgpu_device *adev)
 
         ret = drm_atomic_helper_resume(ddev, adev->dm.cached_state);
 
-        drm_atomic_state_put(adev->dm.cached_state);
         adev->dm.cached_state = NULL;
 
         amdgpu_dm_irq_resume_late(adev);
@@ -2704,7 +2708,7 @@ static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
                         .link = aconnector->dc_link,
                         .sink_signal = SIGNAL_TYPE_VIRTUAL
         };
-        struct edid *edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
+        struct edid *edid;
 
         if (!aconnector->base.edid_blob_ptr ||
                 !aconnector->base.edid_blob_ptr->data) {
@@ -2716,6 +2720,8 @@ static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
                 return;
         }
 
+        edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
+
         aconnector->edid = edid;
 
         aconnector->dc_em_sink = dc_link_add_remote_sink(
@@ -4193,13 +4199,13 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
                 update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
                                 dm_new_con_state, (struct dc_stream_state *)dm_new_crtc_state->stream);
 
+                if (!dm_new_crtc_state->stream)
+                        continue;
+
                 status = dc_stream_get_status(dm_new_crtc_state->stream);
                 WARN_ON(!status);
                 WARN_ON(!status->plane_count);
 
-                if (!dm_new_crtc_state->stream)
-                        continue;
-
                 /*TODO How it works with MPO ?*/
                 if (!dc_commit_planes_to_stream(
                                 dm->dc,
@@ -4253,7 +4259,7 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
         drm_atomic_helper_commit_hw_done(state);
 
         if (wait_for_vblank)
-                drm_atomic_helper_wait_for_vblanks(dev, state);
+                drm_atomic_helper_wait_for_flip_done(dev, state);
 
         drm_atomic_helper_cleanup_planes(dev, state);
 }
@@ -4332,9 +4338,11 @@ void dm_restore_drm_connector_state(struct drm_device *dev,
                 return;
 
         disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
-        acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
+        if (!disconnected_acrtc)
+                return;
 
-        if (!disconnected_acrtc || !acrtc_state->stream)
+        acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
+        if (!acrtc_state->stream)
                 return;
 
         /*
@@ -4455,7 +4463,7 @@ static int dm_update_crtcs_state(struct dc *dc,
                         }
                 }
 
-                if (dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
+                if (enable && dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
                                 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
 
                         new_crtc_state->mode_changed = false;
@@ -4709,7 +4717,8 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
                 }
         } else {
                 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
-                        if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
+                        if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
+                                        !new_crtc_state->color_mgmt_changed)
                                 continue;
 
                         if (!new_crtc_state->enable)
diff --git a/drivers/gpu/drm/amd/display/dc/basics/log_helpers.c b/drivers/gpu/drm/amd/display/dc/basics/log_helpers.c
index 785b943b60ed..6e43168fbdd6 100644
--- a/drivers/gpu/drm/amd/display/dc/basics/log_helpers.c
+++ b/drivers/gpu/drm/amd/display/dc/basics/log_helpers.c
@@ -75,6 +75,9 @@ void dc_conn_log(struct dc_context *ctx,
                 if (signal == signal_type_info_tbl[i].type)
                         break;
 
+        if (i == NUM_ELEMENTS(signal_type_info_tbl))
+                goto fail;
+
         dm_logger_append(&entry, "[%s][ConnIdx:%d] ",
                         signal_type_info_tbl[i].name,
                         link->link_index);
@@ -96,6 +99,8 @@ void dc_conn_log(struct dc_context *ctx,
 
         dm_logger_append(&entry, "^\n");
         dm_helpers_dc_conn_log(ctx, &entry, event);
+
+fail:
         dm_logger_close(&entry);
 
         va_end(args);
diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
index aaaebd06d7ee..86e6438c5cf3 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
@@ -249,7 +249,7 @@ static enum bp_result bios_parser_get_dst_obj(struct dc_bios *dcb,
         struct graphics_object_id *dest_object_id)
 {
         uint32_t number;
-        uint16_t *id;
+        uint16_t *id = NULL;
         ATOM_OBJECT *object;
         struct bios_parser *bp = BP_FROM_DCB(dcb);
 
@@ -260,7 +260,7 @@ static enum bp_result bios_parser_get_dst_obj(struct dc_bios *dcb,
 
         number = get_dest_obj_list(bp, object, &id);
 
-        if (number <= index)
+        if (number <= index || !id)
                 return BP_RESULT_BADINPUT;
 
         *dest_object_id = object_id_from_bios_object_id(id[index]);
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index fe63f5894d43..7240db2e6f09 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -121,6 +121,10 @@ static bool create_links(
                         goto failed_alloc;
                 }
 
+                link->link_index = dc->link_count;
+                dc->links[dc->link_count] = link;
+                dc->link_count++;
+
                 link->ctx = dc->ctx;
                 link->dc = dc;
                 link->connector_signal = SIGNAL_TYPE_VIRTUAL;
@@ -129,6 +133,13 @@ static bool create_links(
                 link->link_id.enum_id = ENUM_ID_1;
                 link->link_enc = kzalloc(sizeof(*link->link_enc), GFP_KERNEL);
 
+                if (!link->link_enc) {
+                        BREAK_TO_DEBUGGER();
+                        goto failed_alloc;
+                }
+
+                link->link_status.dpcd_caps = &link->dpcd_caps;
+
                 enc_init.ctx = dc->ctx;
                 enc_init.channel = CHANNEL_ID_UNKNOWN;
                 enc_init.hpd_source = HPD_SOURCEID_UNKNOWN;
@@ -138,10 +149,6 @@ static bool create_links(
                 enc_init.encoder.id = ENCODER_ID_INTERNAL_VIRTUAL;
                 enc_init.encoder.enum_id = ENUM_ID_1;
                 virtual_link_encoder_construct(link->link_enc, &enc_init);
-
-                link->link_index = dc->link_count;
-                dc->links[dc->link_count] = link;
-                dc->link_count++;
         }
 
         return true;
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 0602610489d7..e27ed4a45265 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -480,22 +480,6 @@ static void detect_dp(
                 sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
                 detect_dp_sink_caps(link);
 
-                /* DP active dongles */
-                if (is_dp_active_dongle(link)) {
-                        link->type = dc_connection_active_dongle;
-                        if (!link->dpcd_caps.sink_count.bits.SINK_COUNT) {
-                                /*
-                                 * active dongle unplug processing for short irq
-                                 */
-                                link_disconnect_sink(link);
-                                return;
-                        }
-
-                        if (link->dpcd_caps.dongle_type !=
-                        DISPLAY_DONGLE_DP_HDMI_CONVERTER) {
-                                *converter_disable_audio = true;
-                        }
-                }
                 if (is_mst_supported(link)) {
                         sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
                         link->type = dc_connection_mst_branch;
@@ -535,6 +519,22 @@ static void detect_dp(
                                 sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
                         }
                 }
+
+                if (link->type != dc_connection_mst_branch &&
+                        is_dp_active_dongle(link)) {
+                        /* DP active dongles */
+                        link->type = dc_connection_active_dongle;
+                        if (!link->dpcd_caps.sink_count.bits.SINK_COUNT) {
+                                /*
+                                 * active dongle unplug processing for short irq
+                                 */
+                                link_disconnect_sink(link);
+                                return;
+                        }
+
+                        if (link->dpcd_caps.dongle_type != DISPLAY_DONGLE_DP_HDMI_CONVERTER)
+                                *converter_disable_audio = true;
+                }
         } else {
                 /* DP passive dongles */
                 sink_caps->signal = dp_passive_dongle_detection(link->ddc,
@@ -1801,12 +1801,75 @@ static void disable_link(struct dc_link *link, enum signal_type signal)
                 link->link_enc->funcs->disable_output(link->link_enc, signal, link);
 }
 
+bool dp_active_dongle_validate_timing(
+                const struct dc_crtc_timing *timing,
+                const struct dc_dongle_caps *dongle_caps)
+{
+        unsigned int required_pix_clk = timing->pix_clk_khz;
+
+        if (dongle_caps->dongle_type != DISPLAY_DONGLE_DP_HDMI_CONVERTER ||
+                dongle_caps->extendedCapValid == false)
+                return true;
+
+        /* Check Pixel Encoding */
+        switch (timing->pixel_encoding) {
+        case PIXEL_ENCODING_RGB:
+        case PIXEL_ENCODING_YCBCR444:
+                break;
+        case PIXEL_ENCODING_YCBCR422:
+                if (!dongle_caps->is_dp_hdmi_ycbcr422_pass_through)
+                        return false;
+                break;
+        case PIXEL_ENCODING_YCBCR420:
+                if (!dongle_caps->is_dp_hdmi_ycbcr420_pass_through)
+                        return false;
+                break;
+        default:
+                /* Invalid Pixel Encoding*/
+                return false;
+        }
+
+
+        /* Check Color Depth and Pixel Clock */
+        if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
+                required_pix_clk /= 2;
+
+        switch (timing->display_color_depth) {
+        case COLOR_DEPTH_666:
+        case COLOR_DEPTH_888:
+                /*888 and 666 should always be supported*/
+                break;
+        case COLOR_DEPTH_101010:
+                if (dongle_caps->dp_hdmi_max_bpc < 10)
+                        return false;
+                required_pix_clk = required_pix_clk * 10 / 8;
+                break;
+        case COLOR_DEPTH_121212:
+                if (dongle_caps->dp_hdmi_max_bpc < 12)
+                        return false;
+                required_pix_clk = required_pix_clk * 12 / 8;
+                break;
+
+        case COLOR_DEPTH_141414:
+        case COLOR_DEPTH_161616:
+        default:
+                /* These color depths are currently not supported */
+                return false;
+        }
+
+        if (required_pix_clk > dongle_caps->dp_hdmi_max_pixel_clk)
+                return false;
+
+        return true;
+}
+
 enum dc_status dc_link_validate_mode_timing(
                 const struct dc_stream_state *stream,
                 struct dc_link *link,
                 const struct dc_crtc_timing *timing)
 {
         uint32_t max_pix_clk = stream->sink->dongle_max_pix_clk;
+        struct dc_dongle_caps *dongle_caps = &link->link_status.dpcd_caps->dongle_caps;
 
         /* A hack to avoid failing any modes for EDID override feature on
          * topology change such as lower quality cable for DP or different dongle
@@ -1814,8 +1877,13 @@ enum dc_status dc_link_validate_mode_timing(
         if (link->remote_sinks[0])
                 return DC_OK;
 
+        /* Passive Dongle */
         if (0 != max_pix_clk && timing->pix_clk_khz > max_pix_clk)
-                return DC_EXCEED_DONGLE_MAX_CLK;
+                return DC_EXCEED_DONGLE_CAP;
+
+        /* Active Dongle*/
+        if (!dp_active_dongle_validate_timing(timing, dongle_caps))
+                return DC_EXCEED_DONGLE_CAP;
 
         switch (stream->signal) {
         case SIGNAL_TYPE_EDP:
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index ced42484dcfc..e6bf05d76a94 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -1512,7 +1512,7 @@ static bool hpd_rx_irq_check_link_loss_status(
         struct dc_link *link,
         union hpd_irq_data *hpd_irq_dpcd_data)
 {
-        uint8_t irq_reg_rx_power_state;
+        uint8_t irq_reg_rx_power_state = 0;
         enum dc_status dpcd_result = DC_ERROR_UNEXPECTED;
         union lane_status lane_status;
         uint32_t lane;
@@ -1524,60 +1524,55 @@ static bool hpd_rx_irq_check_link_loss_status(
 
         if (link->cur_link_settings.lane_count == 0)
                 return return_code;
-        /*1. Check that we can handle interrupt: Not in FS DOS,
-         *  Not in "Display Timeout" state, Link is trained.
-         */
 
-        dpcd_result = core_link_read_dpcd(link,
-                DP_SET_POWER,
-                &irq_reg_rx_power_state,
-                sizeof(irq_reg_rx_power_state));
+        /*1. Check that Link Status changed, before re-training.*/
 
-        if (dpcd_result != DC_OK) {
-                irq_reg_rx_power_state = DP_SET_POWER_D0;
-                dm_logger_write(link->ctx->logger, LOG_HW_HPD_IRQ,
-                        "%s: DPCD read failed to obtain power state.\n",
-                        __func__);
+        /*parse lane status*/
+        for (lane = 0; lane < link->cur_link_settings.lane_count; lane++) {
+                /* check status of lanes 0,1
+                 * changed DpcdAddress_Lane01Status (0x202)
+                 */
+                lane_status.raw = get_nibble_at_index(
+                        &hpd_irq_dpcd_data->bytes.lane01_status.raw,
+                        lane);
+
+                if (!lane_status.bits.CHANNEL_EQ_DONE_0 ||
+                        !lane_status.bits.CR_DONE_0 ||
+                        !lane_status.bits.SYMBOL_LOCKED_0) {
+                        /* if one of the channel equalization, clock
+                         * recovery or symbol lock is dropped
+                         * consider it as (link has been
+                         * dropped) dp sink status has changed
+                         */
+                        sink_status_changed = true;
+                        break;
+                }
         }
 
-        if (irq_reg_rx_power_state == DP_SET_POWER_D0) {
-
-                /*2. Check that Link Status changed, before re-training.*/
-
-                /*parse lane status*/
-                for (lane = 0;
-                        lane < link->cur_link_settings.lane_count;
-                        lane++) {
+        /* Check interlane align.*/
+        if (sink_status_changed ||
+                !hpd_irq_dpcd_data->bytes.lane_status_updated.bits.INTERLANE_ALIGN_DONE) {
 
-                        /* check status of lanes 0,1
-                         * changed DpcdAddress_Lane01Status (0x202)*/
-                        lane_status.raw = get_nibble_at_index(
-                                &hpd_irq_dpcd_data->bytes.lane01_status.raw,
-                                lane);
-
-                        if (!lane_status.bits.CHANNEL_EQ_DONE_0 ||
-                                !lane_status.bits.CR_DONE_0 ||
-                                !lane_status.bits.SYMBOL_LOCKED_0) {
-                                /* if one of the channel equalization, clock
-                                 * recovery or symbol lock is dropped
-                                 * consider it as (link has been
-                                 * dropped) dp sink status has changed*/
-                                sink_status_changed = true;
-                                break;
-                        }
+                dm_logger_write(link->ctx->logger, LOG_HW_HPD_IRQ,
+                        "%s: Link Status changed.\n", __func__);
 
-                }
+                return_code = true;
 
-                /* Check interlane align.*/
-                if (sink_status_changed ||
-                        !hpd_irq_dpcd_data->bytes.lane_status_updated.bits.
-                        INTERLANE_ALIGN_DONE) {
+                /*2. Check that we can handle interrupt: Not in FS DOS,
+                 *  Not in "Display Timeout" state, Link is trained.
+                 */
+                dpcd_result = core_link_read_dpcd(link,
+                        DP_SET_POWER,
+                        &irq_reg_rx_power_state,
+                        sizeof(irq_reg_rx_power_state));
 
+                if (dpcd_result != DC_OK) {
                         dm_logger_write(link->ctx->logger, LOG_HW_HPD_IRQ,
-                                "%s: Link Status changed.\n",
+                                "%s: DPCD read failed to obtain power state.\n",
                                 __func__);
-
-                        return_code = true;
+                } else {
+                        if (irq_reg_rx_power_state != DP_SET_POWER_D0)
+                                return_code = false;
                 }
         }
 
@@ -2062,6 +2057,24 @@ bool is_dp_active_dongle(const struct dc_link *link)
                         (dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER);
 }
 
+static int translate_dpcd_max_bpc(enum dpcd_downstream_port_max_bpc bpc)
+{
+        switch (bpc) {
+        case DOWN_STREAM_MAX_8BPC:
+                return 8;
+        case DOWN_STREAM_MAX_10BPC:
+                return 10;
+        case DOWN_STREAM_MAX_12BPC:
+                return 12;
+        case DOWN_STREAM_MAX_16BPC:
+                return 16;
+        default:
+                break;
+        }
+
+        return -1;
+}
+
 static void get_active_converter_info(
         uint8_t data, struct dc_link *link)
 {
@@ -2131,7 +2144,8 @@ static void get_active_converter_info(
                                         hdmi_caps.bits.YCrCr420_CONVERSION;
 
                                 link->dpcd_caps.dongle_caps.dp_hdmi_max_bpc =
-                                        hdmi_color_caps.bits.MAX_BITS_PER_COLOR_COMPONENT;
+                                        translate_dpcd_max_bpc(
+                                                hdmi_color_caps.bits.MAX_BITS_PER_COLOR_COMPONENT);
 
                                 link->dpcd_caps.dongle_caps.extendedCapValid = true;
                         }
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index d1cdf9f8853d..b7422d3b71ef 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -516,13 +516,11 @@ static void calculate_viewport(struct pipe_ctx *pipe_ctx)
                         right_view = (plane_state->rotation == ROTATION_ANGLE_270) != sec_split;
 
                 if (right_view) {
-                        data->viewport.width /= 2;
-                        data->viewport_c.width /= 2;
-                        data->viewport.x +=  data->viewport.width;
-                        data->viewport_c.x +=  data->viewport_c.width;
+                        data->viewport.x +=  data->viewport.width / 2;
+                        data->viewport_c.x +=  data->viewport_c.width / 2;
                         /* Ceil offset pipe */
-                        data->viewport.width += data->viewport.width % 2;
-                        data->viewport_c.width += data->viewport_c.width % 2;
+                        data->viewport.width = (data->viewport.width + 1) / 2;
+                        data->viewport_c.width = (data->viewport_c.width + 1) / 2;
                 } else {
                         data->viewport.width /= 2;
                         data->viewport_c.width /= 2;
@@ -580,14 +578,12 @@ static void calculate_recout(struct pipe_ctx *pipe_ctx, struct view *recout_skip
         if (pipe_ctx->top_pipe && pipe_ctx->top_pipe->plane_state ==
                 pipe_ctx->plane_state) {
                 if (stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) {
-                        pipe_ctx->plane_res.scl_data.recout.height /= 2;
-                        pipe_ctx->plane_res.scl_data.recout.y += pipe_ctx->plane_res.scl_data.recout.height;
+                        pipe_ctx->plane_res.scl_data.recout.y += pipe_ctx->plane_res.scl_data.recout.height / 2;
                         /* Floor primary pipe, ceil 2ndary pipe */
-                        pipe_ctx->plane_res.scl_data.recout.height += pipe_ctx->plane_res.scl_data.recout.height % 2;
+                        pipe_ctx->plane_res.scl_data.recout.height = (pipe_ctx->plane_res.scl_data.recout.height + 1) / 2;
                 } else {
-                        pipe_ctx->plane_res.scl_data.recout.width /= 2;
-                        pipe_ctx->plane_res.scl_data.recout.x += pipe_ctx->plane_res.scl_data.recout.width;
-                        pipe_ctx->plane_res.scl_data.recout.width += pipe_ctx->plane_res.scl_data.recout.width % 2;
+                        pipe_ctx->plane_res.scl_data.recout.x += pipe_ctx->plane_res.scl_data.recout.width / 2;
+                        pipe_ctx->plane_res.scl_data.recout.width = (pipe_ctx->plane_res.scl_data.recout.width + 1) / 2;
                 }
         } else if (pipe_ctx->bottom_pipe &&
                         pipe_ctx->bottom_pipe->plane_state == pipe_ctx->plane_state) {
@@ -856,6 +852,7 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
         pipe_ctx->plane_res.scl_data.h_active = timing->h_addressable + timing->h_border_left + timing->h_border_right;
         pipe_ctx->plane_res.scl_data.v_active = timing->v_addressable + timing->v_border_top + timing->v_border_bottom;
 
+
         /* Taps calculations */
         if (pipe_ctx->plane_res.xfm != NULL)
                 res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(
@@ -864,16 +861,21 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
         if (pipe_ctx->plane_res.dpp != NULL)
                 res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(
                                 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
-
         if (!res) {
                 /* Try 24 bpp linebuffer */
                 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_24BPP;
 
-                res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(
-                        pipe_ctx->plane_res.xfm, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
+                if (pipe_ctx->plane_res.xfm != NULL)
+                        res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(
+                                        pipe_ctx->plane_res.xfm,
+                                        &pipe_ctx->plane_res.scl_data,
+                                        &plane_state->scaling_quality);
 
-                res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(
-                        pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
+                if (pipe_ctx->plane_res.dpp != NULL)
+                        res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(
+                                        pipe_ctx->plane_res.dpp,
+                                        &pipe_ctx->plane_res.scl_data,
+                                        &plane_state->scaling_quality);
         }
 
         if (res)
@@ -991,8 +993,10 @@ static struct pipe_ctx *acquire_free_pipe_for_stream(
 
         head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream);
 
-        if (!head_pipe)
+        if (!head_pipe) {
                 ASSERT(0);
+                return NULL;
+        }
 
         if (!head_pipe->plane_state)
                 return head_pipe;
@@ -1447,11 +1451,16 @@ static struct stream_encoder *find_first_free_match_stream_enc_for_link(
 
 static struct audio *find_first_free_audio(
                 struct resource_context *res_ctx,
-                const struct resource_pool *pool)
+                const struct resource_pool *pool,
+                enum engine_id id)
 {
         int i;
         for (i = 0; i < pool->audio_count; i++) {
                 if ((res_ctx->is_audio_acquired[i] == false) && (res_ctx->is_stream_enc_acquired[i] == true)) {
+                        /*we have enough audio endpoint, find the matching inst*/
+                        if (id != i)
+                                continue;
+
                         return pool->audios[i];
                 }
         }
@@ -1700,7 +1709,7 @@ enum dc_status resource_map_pool_resources(
             dc_is_audio_capable_signal(pipe_ctx->stream->signal) &&
             stream->audio_info.mode_count) {
                 pipe_ctx->stream_res.audio = find_first_free_audio(
-                &context->res_ctx, pool);
+                &context->res_ctx, pool, pipe_ctx->stream_res.stream_enc->id);
 
                 /*
                  * Audio assigned in order first come first get.
@@ -1765,13 +1774,16 @@ enum dc_status dc_validate_global_state(
         enum dc_status result = DC_ERROR_UNEXPECTED;
         int i, j;
 
+        if (!new_ctx)
+                return DC_ERROR_UNEXPECTED;
+
         if (dc->res_pool->funcs->validate_global) {
                         result = dc->res_pool->funcs->validate_global(dc, new_ctx);
                         if (result != DC_OK)
                                 return result;
         }
 
-        for (i = 0; new_ctx && i < new_ctx->stream_count; i++) {
+        for (i = 0; i < new_ctx->stream_count; i++) {
                 struct dc_stream_state *stream = new_ctx->streams[i];
 
                 for (j = 0; j < dc->res_pool->pipe_count; j++) {
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index b00a6040a697..e230cc44a0a7 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
@@ -263,7 +263,6 @@ bool dc_stream_set_cursor_position(
                 struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;
                 struct mem_input *mi = pipe_ctx->plane_res.mi;
                 struct hubp *hubp = pipe_ctx->plane_res.hubp;
-                struct transform *xfm = pipe_ctx->plane_res.xfm;
                 struct dpp *dpp = pipe_ctx->plane_res.dpp;
                 struct dc_cursor_position pos_cpy = *position;
                 struct dc_cursor_mi_param param = {
@@ -294,11 +293,11 @@ bool dc_stream_set_cursor_position(
                 if (mi != NULL && mi->funcs->set_cursor_position != NULL)
                         mi->funcs->set_cursor_position(mi, &pos_cpy, &param);
 
-                if (hubp != NULL && hubp->funcs->set_cursor_position != NULL)
-                        hubp->funcs->set_cursor_position(hubp, &pos_cpy, &param);
+                if (!hubp)
+                        continue;
 
-                if (xfm != NULL && xfm->funcs->set_cursor_position != NULL)
-                        xfm->funcs->set_cursor_position(xfm, &pos_cpy, &param, hubp->curs_attr.width);
+                if (hubp->funcs->set_cursor_position != NULL)
+                        hubp->funcs->set_cursor_position(hubp, &pos_cpy, &param);
 
                 if (dpp != NULL && dpp->funcs->set_cursor_position != NULL)
                         dpp->funcs->set_cursor_position(dpp, &pos_cpy, &param, hubp->curs_attr.width);
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
index 81c40f8864db..0df9ecb2710c 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
@@ -352,11 +352,11 @@ void dce_aud_az_enable(struct audio *audio)
         uint32_t value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
 
         set_reg_field_value(value, 1,
-                        AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
-                        CLOCK_GATING_DISABLE);
-                set_reg_field_value(value, 1,
-                        AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
-                        AUDIO_ENABLED);
+                            AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
+                            CLOCK_GATING_DISABLE);
+        set_reg_field_value(value, 1,
+                            AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
+                            AUDIO_ENABLED);
 
         AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
         value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
index 4fd49a16c3b6..e42b6eb1c1f0 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
@@ -87,6 +87,9 @@ static void dce110_update_generic_info_packet(
          */
         uint32_t max_retries = 50;
 
+        /*we need turn on clock before programming AFMT block*/
+        REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1);
+
         if (REG(AFMT_VBI_PACKET_CONTROL1)) {
                 if (packet_index >= 8)
                         ASSERT(0);
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 1229a3315018..07ff8d2faf3f 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -991,6 +991,16 @@ void dce110_disable_stream(struct pipe_ctx *pipe_ctx, int option)
         struct dc_link *link = stream->sink->link;
         struct dc *dc = pipe_ctx->stream->ctx->dc;
 
+        if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
+                pipe_ctx->stream_res.stream_enc->funcs->stop_hdmi_info_packets(
+                        pipe_ctx->stream_res.stream_enc);
+
+        if (dc_is_dp_signal(pipe_ctx->stream->signal))
+                pipe_ctx->stream_res.stream_enc->funcs->stop_dp_info_packets(
+                        pipe_ctx->stream_res.stream_enc);
+
+        pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control(
+                        pipe_ctx->stream_res.stream_enc, true);
         if (pipe_ctx->stream_res.audio) {
                 pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);
 
@@ -1015,18 +1025,6 @@ void dce110_disable_stream(struct pipe_ctx *pipe_ctx, int option)
                  */
         }
 
-        if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
-                pipe_ctx->stream_res.stream_enc->funcs->stop_hdmi_info_packets(
-                        pipe_ctx->stream_res.stream_enc);
-
-        if (dc_is_dp_signal(pipe_ctx->stream->signal))
-                pipe_ctx->stream_res.stream_enc->funcs->stop_dp_info_packets(
-                        pipe_ctx->stream_res.stream_enc);
-
-        pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control(
-                        pipe_ctx->stream_res.stream_enc, true);
-
-
         /* blank at encoder level */
         if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
                 if (pipe_ctx->stream->sink->link->connector_signal == SIGNAL_TYPE_EDP)
@@ -1774,6 +1772,10 @@ static enum dc_status validate_fbc(struct dc *dc,
         if (pipe_ctx->stream->sink->link->psr_enabled)
                 return DC_ERROR_UNEXPECTED;
 
+        /* Nothing to compress */
+        if (!pipe_ctx->plane_state)
+                return DC_ERROR_UNEXPECTED;
+
         /* Only for non-linear tiling */
         if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL)
                 return DC_ERROR_UNEXPECTED;
@@ -1868,8 +1870,10 @@ static void dce110_reset_hw_ctx_wrap(
                                 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
                         struct clock_source *old_clk = pipe_ctx_old->clock_source;
 
-                        /* disable already, no need to disable again */
-                        if (pipe_ctx->stream && !pipe_ctx->stream->dpms_off)
+                        /* Disable if new stream is null. O/w, if stream is
+                         * disabled already, no need to disable again.
+                         */
+                        if (!pipe_ctx->stream || !pipe_ctx->stream->dpms_off)
                                 core_link_disable_stream(pipe_ctx_old, FREE_ACQUIRED_RESOURCE);
 
                         pipe_ctx_old->stream_res.tg->funcs->set_blank(pipe_ctx_old->stream_res.tg, true);
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
index db96d2b47ff1..61adb8174ce0 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
@@ -1037,11 +1037,13 @@ static bool underlay_create(struct dc_context *ctx, struct resource_pool *pool)
         struct dce110_opp *dce110_oppv = kzalloc(sizeof(*dce110_oppv),
                                                  GFP_KERNEL);
 
-        if ((dce110_tgv == NULL) ||
-                (dce110_xfmv == NULL) ||
-                (dce110_miv == NULL) ||
-                (dce110_oppv == NULL))
-                        return false;
+        if (!dce110_tgv || !dce110_xfmv || !dce110_miv || !dce110_oppv) {
+                kfree(dce110_tgv);
+                kfree(dce110_xfmv);
+                kfree(dce110_miv);
+                kfree(dce110_oppv);
+                return false;
+        }
 
         dce110_opp_v_construct(dce110_oppv, ctx);
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
index 67ac737eaa7e..4befce6cd87a 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
@@ -1112,10 +1112,7 @@ bool dce110_timing_generator_validate_timing(
         enum signal_type signal)
 {
         uint32_t h_blank;
-        uint32_t h_back_porch;
-        uint32_t hsync_offset = timing->h_border_right +
-                        timing->h_front_porch;
-        uint32_t h_sync_start = timing->h_addressable + hsync_offset;
+        uint32_t h_back_porch, hsync_offset, h_sync_start;
 
         struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
 
@@ -1124,6 +1121,9 @@ bool dce110_timing_generator_validate_timing(
         if (!timing)
                 return false;
 
+        hsync_offset = timing->h_border_right + timing->h_front_porch;
+        h_sync_start = timing->h_addressable + hsync_offset;
+
         /* Currently we don't support 3D, so block all 3D timings */
         if (timing->timing_3d_format != TIMING_3D_FORMAT_NONE)
                 return false;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index 4c4bd72d4e40..9fc8f827f2a1 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -912,11 +912,13 @@ static struct pipe_ctx *dcn10_acquire_idle_pipe_for_layer(
         struct pipe_ctx *head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream);
         struct pipe_ctx *idle_pipe = find_idle_secondary_pipe(res_ctx, pool);
 
-        if (!head_pipe)
+        if (!head_pipe) {
                 ASSERT(0);
+                return NULL;
+        }
 
         if (!idle_pipe)
-                return false;
+                return NULL;
 
         idle_pipe->stream = head_pipe->stream;
         idle_pipe->stream_res.tg = head_pipe->stream_res.tg;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
index c7333cdf1802..fced178c8c79 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
@@ -496,9 +496,6 @@ static bool tgn10_validate_timing(
                 timing->timing_3d_format != TIMING_3D_FORMAT_INBAND_FA)
                 return false;
 
-        if (timing->timing_3d_format != TIMING_3D_FORMAT_NONE &&
-                tg->ctx->dc->debug.disable_stereo_support)
-                return false;
         /* Temporarily blocking interlacing mode until it's supported */
         if (timing->flags.INTERLACE == 1)
                 return false;
diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_status.h b/drivers/gpu/drm/amd/display/dc/inc/core_status.h
index 01df85641684..94fc31080fda 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/core_status.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/core_status.h
@@ -38,7 +38,7 @@ enum dc_status {
         DC_FAIL_DETACH_SURFACES = 8,
         DC_FAIL_SURFACE_VALIDATE = 9,
         DC_NO_DP_LINK_BANDWIDTH = 10,
-        DC_EXCEED_DONGLE_MAX_CLK = 11,
+        DC_EXCEED_DONGLE_CAP = 11,
         DC_SURFACE_PIXEL_FORMAT_UNSUPPORTED = 12,
         DC_FAIL_BANDWIDTH_VALIDATE = 13, /* BW and Watermark validation */
         DC_FAIL_SCALING = 14,
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h b/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h
index 7c08bc62c1f5..ea88997e1bbd 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h
@@ -259,13 +259,6 @@ struct transform_funcs {
                         struct transform *xfm_base,
                         const struct dc_cursor_attributes *attr);
 
-        void (*set_cursor_position)(
-                        struct transform *xfm_base,
-                        const struct dc_cursor_position *pos,
-                        const struct dc_cursor_mi_param *param,
-                        uint32_t width
-                        );
-
 };
 
 const uint16_t *get_filter_2tap_16p(void);
diff --git a/drivers/gpu/drm/arm/hdlcd_crtc.c b/drivers/gpu/drm/arm/hdlcd_crtc.c
index 72b22b805412..5a5427bbd70e 100644
--- a/drivers/gpu/drm/arm/hdlcd_crtc.c
+++ b/drivers/gpu/drm/arm/hdlcd_crtc.c
@@ -317,9 +317,8 @@ static struct drm_plane *hdlcd_plane_init(struct drm_device *drm)
                                        formats, ARRAY_SIZE(formats),
                                        NULL,
                                        DRM_PLANE_TYPE_PRIMARY, NULL);
-        if (ret) {
+        if (ret)
                 return ERR_PTR(ret);
-        }
 
         drm_plane_helper_add(plane, &hdlcd_plane_helper_funcs);
         hdlcd->plane = plane;
diff --git a/drivers/gpu/drm/arm/hdlcd_drv.c b/drivers/gpu/drm/arm/hdlcd_drv.c
index 764d0c83710c..0afb53b1f4e9 100644
--- a/drivers/gpu/drm/arm/hdlcd_drv.c
+++ b/drivers/gpu/drm/arm/hdlcd_drv.c
@@ -13,6 +13,7 @@
 #include <linux/spinlock.h>
 #include <linux/clk.h>
 #include <linux/component.h>
+#include <linux/console.h>
 #include <linux/list.h>
 #include <linux/of_graph.h>
 #include <linux/of_reserved_mem.h>
@@ -354,7 +355,7 @@ err_unload:
 err_free:
         drm_mode_config_cleanup(drm);
         dev_set_drvdata(dev, NULL);
-        drm_dev_unref(drm);
+        drm_dev_put(drm);
 
         return ret;
 }
@@ -379,7 +380,7 @@ static void hdlcd_drm_unbind(struct device *dev)
         pm_runtime_disable(drm->dev);
         of_reserved_mem_device_release(drm->dev);
         drm_mode_config_cleanup(drm);
-        drm_dev_unref(drm);
+        drm_dev_put(drm);
         drm->dev_private = NULL;
         dev_set_drvdata(dev, NULL);
 }
@@ -432,9 +433,11 @@ static int __maybe_unused hdlcd_pm_suspend(struct device *dev)
                 return 0;
 
         drm_kms_helper_poll_disable(drm);
+        drm_fbdev_cma_set_suspend_unlocked(hdlcd->fbdev, 1);
 
         hdlcd->state = drm_atomic_helper_suspend(drm);
         if (IS_ERR(hdlcd->state)) {
+                drm_fbdev_cma_set_suspend_unlocked(hdlcd->fbdev, 0);
                 drm_kms_helper_poll_enable(drm);
                 return PTR_ERR(hdlcd->state);
         }
@@ -451,8 +454,8 @@ static int __maybe_unused hdlcd_pm_resume(struct device *dev)
                 return 0;
 
         drm_atomic_helper_resume(drm, hdlcd->state);
+        drm_fbdev_cma_set_suspend_unlocked(hdlcd->fbdev, 0);
         drm_kms_helper_poll_enable(drm);
-        pm_runtime_set_active(dev);
 
         return 0;
 }
diff --git a/drivers/gpu/drm/arm/malidp_crtc.c b/drivers/gpu/drm/arm/malidp_crtc.c
index 3615d18a7ddf..904fff80917b 100644
--- a/drivers/gpu/drm/arm/malidp_crtc.c
+++ b/drivers/gpu/drm/arm/malidp_crtc.c
@@ -65,8 +65,8 @@ static void malidp_crtc_atomic_enable(struct drm_crtc *crtc,
         /* We rely on firmware to set mclk to a sensible level. */
         clk_set_rate(hwdev->pxlclk, crtc->state->adjusted_mode.crtc_clock * 1000);
 
-        hwdev->modeset(hwdev, &vm);
-        hwdev->leave_config_mode(hwdev);
+        hwdev->hw->modeset(hwdev, &vm);
+        hwdev->hw->leave_config_mode(hwdev);
         drm_crtc_vblank_on(crtc);
 }
 
@@ -77,8 +77,12 @@ static void malidp_crtc_atomic_disable(struct drm_crtc *crtc,
         struct malidp_hw_device *hwdev = malidp->dev;
         int err;
 
+        /* always disable planes on the CRTC that is being turned off */
+        drm_atomic_helper_disable_planes_on_crtc(old_state, false);
+
         drm_crtc_vblank_off(crtc);
-        hwdev->enter_config_mode(hwdev);
+        hwdev->hw->enter_config_mode(hwdev);
+
         clk_disable_unprepare(hwdev->pxlclk);
 
         err = pm_runtime_put(crtc->dev->dev);
@@ -319,7 +323,7 @@ static int malidp_crtc_atomic_check_scaling(struct drm_crtc *crtc,
 
 mclk_calc:
         drm_display_mode_to_videomode(&state->adjusted_mode, &vm);
-        ret = hwdev->se_calc_mclk(hwdev, s, &vm);
+        ret = hwdev->hw->se_calc_mclk(hwdev, s, &vm);
         if (ret < 0)
                 return -EINVAL;
         return 0;
@@ -475,7 +479,7 @@ static int malidp_crtc_enable_vblank(struct drm_crtc *crtc)
         struct malidp_hw_device *hwdev = malidp->dev;
 
         malidp_hw_enable_irq(hwdev, MALIDP_DE_BLOCK,
-                             hwdev->map.de_irq_map.vsync_irq);
+                             hwdev->hw->map.de_irq_map.vsync_irq);
         return 0;
 }
 
@@ -485,7 +489,7 @@ static void malidp_crtc_disable_vblank(struct drm_crtc *crtc)
         struct malidp_hw_device *hwdev = malidp->dev;
 
         malidp_hw_disable_irq(hwdev, MALIDP_DE_BLOCK,
-                              hwdev->map.de_irq_map.vsync_irq);
+                              hwdev->hw->map.de_irq_map.vsync_irq);
 }
 
 static const struct drm_crtc_funcs malidp_crtc_funcs = {
diff --git a/drivers/gpu/drm/arm/malidp_drv.c b/drivers/gpu/drm/arm/malidp_drv.c
index b8944666a18f..91f2b0191368 100644
--- a/drivers/gpu/drm/arm/malidp_drv.c
+++ b/drivers/gpu/drm/arm/malidp_drv.c
@@ -47,10 +47,10 @@ static void malidp_write_gamma_table(struct malidp_hw_device *hwdev,
          * directly.
          */
         malidp_hw_write(hwdev, gamma_write_mask,
-                        hwdev->map.coeffs_base + MALIDP_COEF_TABLE_ADDR);
+                        hwdev->hw->map.coeffs_base + MALIDP_COEF_TABLE_ADDR);
         for (i = 0; i < MALIDP_COEFFTAB_NUM_COEFFS; ++i)
                 malidp_hw_write(hwdev, data[i],
-                                hwdev->map.coeffs_base +
+                                hwdev->hw->map.coeffs_base +
                                 MALIDP_COEF_TABLE_DATA);
 }
 
@@ -103,7 +103,7 @@ void malidp_atomic_commit_update_coloradj(struct drm_crtc *crtc,
                         for (i = 0; i < MALIDP_COLORADJ_NUM_COEFFS; ++i)
                                 malidp_hw_write(hwdev,
                                                 mc->coloradj_coeffs[i],
-                                                hwdev->map.coeffs_base +
+                                                hwdev->hw->map.coeffs_base +
                                                 MALIDP_COLOR_ADJ_COEF + 4 * i);
 
                 malidp_hw_setbits(hwdev, MALIDP_DISP_FUNC_CADJ,
@@ -120,8 +120,8 @@ static void malidp_atomic_commit_se_config(struct drm_crtc *crtc,
         struct malidp_hw_device *hwdev = malidp->dev;
         struct malidp_se_config *s = &cs->scaler_config;
         struct malidp_se_config *old_s = &old_cs->scaler_config;
-        u32 se_control = hwdev->map.se_base +
-                         ((hwdev->map.features & MALIDP_REGMAP_HAS_CLEARIRQ) ?
+        u32 se_control = hwdev->hw->map.se_base +
+                         ((hwdev->hw->map.features & MALIDP_REGMAP_HAS_CLEARIRQ) ?
                          0x10 : 0xC);
         u32 layer_control = se_control + MALIDP_SE_LAYER_CONTROL;
         u32 scr = se_control + MALIDP_SE_SCALING_CONTROL;
@@ -135,7 +135,7 @@ static void malidp_atomic_commit_se_config(struct drm_crtc *crtc,
                 return;
         }
 
-        hwdev->se_set_scaling_coeffs(hwdev, s, old_s);
+        hwdev->hw->se_set_scaling_coeffs(hwdev, s, old_s);
         val = malidp_hw_read(hwdev, se_control);
         val |= MALIDP_SE_SCALING_EN | MALIDP_SE_ALPHA_EN;
 
@@ -170,9 +170,9 @@ static int malidp_set_and_wait_config_valid(struct drm_device *drm)
         int ret;
 
         atomic_set(&malidp->config_valid, 0);
-        hwdev->set_config_valid(hwdev);
+        hwdev->hw->set_config_valid(hwdev);
         /* don't wait for config_valid flag if we are in config mode */
-        if (hwdev->in_config_mode(hwdev))
+        if (hwdev->hw->in_config_mode(hwdev))
                 return 0;
 
         ret = wait_event_interruptible_timeout(malidp->wq,
@@ -455,7 +455,7 @@ static int malidp_runtime_pm_suspend(struct device *dev)
         struct malidp_hw_device *hwdev = malidp->dev;
 
         /* we can only suspend if the hardware is in config mode */
-        WARN_ON(!hwdev->in_config_mode(hwdev));
+        WARN_ON(!hwdev->hw->in_config_mode(hwdev));
 
         hwdev->pm_suspended = true;
         clk_disable_unprepare(hwdev->mclk);
@@ -500,11 +500,7 @@ static int malidp_bind(struct device *dev)
         if (!hwdev)
                 return -ENOMEM;
 
-        /*
-         * copy the associated data from malidp_drm_of_match to avoid
-         * having to keep a reference to the OF node after binding
-         */
-        memcpy(hwdev, of_device_get_match_data(dev), sizeof(*hwdev));
+        hwdev->hw = (struct malidp_hw *)of_device_get_match_data(dev);
         malidp->dev = hwdev;
 
         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -568,13 +564,13 @@ static int malidp_bind(struct device *dev)
                 goto query_hw_fail;
         }
 
-        ret = hwdev->query_hw(hwdev);
+        ret = hwdev->hw->query_hw(hwdev);
         if (ret) {
                 DRM_ERROR("Invalid HW configuration\n");
                 goto query_hw_fail;
         }
 
-        version = malidp_hw_read(hwdev, hwdev->map.dc_base + MALIDP_DE_CORE_ID);
+        version = malidp_hw_read(hwdev, hwdev->hw->map.dc_base + MALIDP_DE_CORE_ID);
         DRM_INFO("found ARM Mali-DP%3x version r%dp%d\n", version >> 16,
                  (version >> 12) & 0xf, (version >> 8) & 0xf);
 
@@ -589,7 +585,7 @@ static int malidp_bind(struct device *dev)
 
         for (i = 0; i < MAX_OUTPUT_CHANNELS; i++)
                 out_depth = (out_depth << 8) | (output_width[i] & 0xf);
-        malidp_hw_write(hwdev, out_depth, hwdev->map.out_depth_base);
+        malidp_hw_write(hwdev, out_depth, hwdev->hw->map.out_depth_base);
 
         atomic_set(&malidp->config_valid, 0);
         init_waitqueue_head(&malidp->wq);
@@ -671,7 +667,7 @@ query_hw_fail:
                 malidp_runtime_pm_suspend(dev);
         drm->dev_private = NULL;
         dev_set_drvdata(dev, NULL);
-        drm_dev_unref(drm);
+        drm_dev_put(drm);
 alloc_fail:
         of_reserved_mem_device_release(dev);
 
@@ -704,7 +700,7 @@ static void malidp_unbind(struct device *dev)
                 malidp_runtime_pm_suspend(dev);
         drm->dev_private = NULL;
         dev_set_drvdata(dev, NULL);
-        drm_dev_unref(drm);
+        drm_dev_put(drm);
         of_reserved_mem_device_release(dev);
 }
 
diff --git a/drivers/gpu/drm/arm/malidp_hw.c b/drivers/gpu/drm/arm/malidp_hw.c
index 17bca99e8ac8..2bfb542135ac 100644
--- a/drivers/gpu/drm/arm/malidp_hw.c
+++ b/drivers/gpu/drm/arm/malidp_hw.c
@@ -183,7 +183,7 @@ static void malidp500_enter_config_mode(struct malidp_hw_device *hwdev)
 
         malidp_hw_setbits(hwdev, MALIDP500_DC_CONFIG_REQ, MALIDP500_DC_CONTROL);
         while (count) {
-                status = malidp_hw_read(hwdev, hwdev->map.dc_base + MALIDP_REG_STATUS);
+                status = malidp_hw_read(hwdev, hwdev->hw->map.dc_base + MALIDP_REG_STATUS);
                 if ((status & MALIDP500_DC_CONFIG_REQ) == MALIDP500_DC_CONFIG_REQ)
                         break;
                 /*
@@ -203,7 +203,7 @@ static void malidp500_leave_config_mode(struct malidp_hw_device *hwdev)
         malidp_hw_clearbits(hwdev, MALIDP_CFG_VALID, MALIDP500_CONFIG_VALID);
         malidp_hw_clearbits(hwdev, MALIDP500_DC_CONFIG_REQ, MALIDP500_DC_CONTROL);
         while (count) {
-                status = malidp_hw_read(hwdev, hwdev->map.dc_base + MALIDP_REG_STATUS);
+                status = malidp_hw_read(hwdev, hwdev->hw->map.dc_base + MALIDP_REG_STATUS);
                 if ((status & MALIDP500_DC_CONFIG_REQ) == 0)
                         break;
                 usleep_range(100, 1000);
@@ -216,7 +216,7 @@ static bool malidp500_in_config_mode(struct malidp_hw_device *hwdev)
 {
         u32 status;
 
-        status = malidp_hw_read(hwdev, hwdev->map.dc_base + MALIDP_REG_STATUS);
+        status = malidp_hw_read(hwdev, hwdev->hw->map.dc_base + MALIDP_REG_STATUS);
         if ((status & MALIDP500_DC_CONFIG_REQ) == MALIDP500_DC_CONFIG_REQ)
                 return true;
 
@@ -407,7 +407,7 @@ static void malidp550_enter_config_mode(struct malidp_hw_device *hwdev)
 
         malidp_hw_setbits(hwdev, MALIDP550_DC_CONFIG_REQ, MALIDP550_DC_CONTROL);
         while (count) {
-                status = malidp_hw_read(hwdev, hwdev->map.dc_base + MALIDP_REG_STATUS);
+                status = malidp_hw_read(hwdev, hwdev->hw->map.dc_base + MALIDP_REG_STATUS);
                 if ((status & MALIDP550_DC_CONFIG_REQ) == MALIDP550_DC_CONFIG_REQ)
                         break;
                 /*
@@ -427,7 +427,7 @@ static void malidp550_leave_config_mode(struct malidp_hw_device *hwdev)
         malidp_hw_clearbits(hwdev, MALIDP_CFG_VALID, MALIDP550_CONFIG_VALID);
         malidp_hw_clearbits(hwdev, MALIDP550_DC_CONFIG_REQ, MALIDP550_DC_CONTROL);
         while (count) {
-                status = malidp_hw_read(hwdev, hwdev->map.dc_base + MALIDP_REG_STATUS);
+                status = malidp_hw_read(hwdev, hwdev->hw->map.dc_base + MALIDP_REG_STATUS);
                 if ((status & MALIDP550_DC_CONFIG_REQ) == 0)
                         break;
                 usleep_range(100, 1000);
@@ -440,7 +440,7 @@ static bool malidp550_in_config_mode(struct malidp_hw_device *hwdev)
 {
         u32 status;
 
-        status = malidp_hw_read(hwdev, hwdev->map.dc_base + MALIDP_REG_STATUS);
+        status = malidp_hw_read(hwdev, hwdev->hw->map.dc_base + MALIDP_REG_STATUS);
         if ((status & MALIDP550_DC_CONFIG_REQ) == MALIDP550_DC_CONFIG_REQ)
                 return true;
 
@@ -616,7 +616,7 @@ static int malidp650_query_hw(struct malidp_hw_device *hwdev)
         return 0;
 }
 
-const struct malidp_hw_device malidp_device[MALIDP_MAX_DEVICES] = {
+const struct malidp_hw malidp_device[MALIDP_MAX_DEVICES] = {
         [MALIDP_500] = {
                 .map = {
                         .coeffs_base = MALIDP500_COEFFS_BASE,
@@ -751,7 +751,7 @@ static void malidp_hw_clear_irq(struct malidp_hw_device *hwdev, u8 block, u32 ir
 {
         u32 base = malidp_get_block_base(hwdev, block);
 
-        if (hwdev->map.features & MALIDP_REGMAP_HAS_CLEARIRQ)
+        if (hwdev->hw->map.features & MALIDP_REGMAP_HAS_CLEARIRQ)
                 malidp_hw_write(hwdev, irq, base + MALIDP_REG_CLEARIRQ);
         else
                 malidp_hw_write(hwdev, irq, base + MALIDP_REG_STATUS);
@@ -762,12 +762,14 @@ static irqreturn_t malidp_de_irq(int irq, void *arg)
         struct drm_device *drm = arg;
         struct malidp_drm *malidp = drm->dev_private;
         struct malidp_hw_device *hwdev;
+        struct malidp_hw *hw;
         const struct malidp_irq_map *de;
         u32 status, mask, dc_status;
         irqreturn_t ret = IRQ_NONE;
 
         hwdev = malidp->dev;
-        de = &hwdev->map.de_irq_map;
+        hw = hwdev->hw;
+        de = &hw->map.de_irq_map;
 
         /*
          * if we are suspended it is likely that we were invoked because
@@ -778,8 +780,8 @@ static irqreturn_t malidp_de_irq(int irq, void *arg)
                 return IRQ_NONE;
 
         /* first handle the config valid IRQ */
-        dc_status = malidp_hw_read(hwdev, hwdev->map.dc_base + MALIDP_REG_STATUS);
-        if (dc_status & hwdev->map.dc_irq_map.vsync_irq) {
+        dc_status = malidp_hw_read(hwdev, hw->map.dc_base + MALIDP_REG_STATUS);
+        if (dc_status & hw->map.dc_irq_map.vsync_irq) {
                 /* we have a page flip event */
                 atomic_set(&malidp->config_valid, 1);
                 malidp_hw_clear_irq(hwdev, MALIDP_DC_BLOCK, dc_status);
@@ -832,11 +834,11 @@ int malidp_de_irq_init(struct drm_device *drm, int irq)
 
         /* first enable the DC block IRQs */
         malidp_hw_enable_irq(hwdev, MALIDP_DC_BLOCK,
-                             hwdev->map.dc_irq_map.irq_mask);
+                             hwdev->hw->map.dc_irq_map.irq_mask);
 
         /* now enable the DE block IRQs */
         malidp_hw_enable_irq(hwdev, MALIDP_DE_BLOCK,
-                             hwdev->map.de_irq_map.irq_mask);
+                             hwdev->hw->map.de_irq_map.irq_mask);
 
         return 0;
 }
@@ -847,9 +849,9 @@ void malidp_de_irq_fini(struct drm_device *drm)
         struct malidp_hw_device *hwdev = malidp->dev;
 
         malidp_hw_disable_irq(hwdev, MALIDP_DE_BLOCK,
-                              hwdev->map.de_irq_map.irq_mask);
+                              hwdev->hw->map.de_irq_map.irq_mask);
         malidp_hw_disable_irq(hwdev, MALIDP_DC_BLOCK,
-                              hwdev->map.dc_irq_map.irq_mask);
+                              hwdev->hw->map.dc_irq_map.irq_mask);
 }
 
 static irqreturn_t malidp_se_irq(int irq, void *arg)
@@ -857,6 +859,8 @@ static irqreturn_t malidp_se_irq(int irq, void *arg)
         struct drm_device *drm = arg;
         struct malidp_drm *malidp = drm->dev_private;
         struct malidp_hw_device *hwdev = malidp->dev;
+        struct malidp_hw *hw = hwdev->hw;
+        const struct malidp_irq_map *se = &hw->map.se_irq_map;
         u32 status, mask;
 
         /*
@@ -867,12 +871,12 @@ static irqreturn_t malidp_se_irq(int irq, void *arg)
         if (hwdev->pm_suspended)
                 return IRQ_NONE;
 
-        status = malidp_hw_read(hwdev, hwdev->map.se_base + MALIDP_REG_STATUS);
-        if (!(status & hwdev->map.se_irq_map.irq_mask))
+        status = malidp_hw_read(hwdev, hw->map.se_base + MALIDP_REG_STATUS);
+        if (!(status & se->irq_mask))
                 return IRQ_NONE;
 
-        mask = malidp_hw_read(hwdev, hwdev->map.se_base + MALIDP_REG_MASKIRQ);
-        status = malidp_hw_read(hwdev, hwdev->map.se_base + MALIDP_REG_STATUS);
+        mask = malidp_hw_read(hwdev, hw->map.se_base + MALIDP_REG_MASKIRQ);
+        status = malidp_hw_read(hwdev, hw->map.se_base + MALIDP_REG_STATUS);
         status &= mask;
         /* ToDo: status decoding and firing up of VSYNC and page flip events */
 
@@ -905,7 +909,7 @@ int malidp_se_irq_init(struct drm_device *drm, int irq)
         }
 
         malidp_hw_enable_irq(hwdev, MALIDP_SE_BLOCK,
-                             hwdev->map.se_irq_map.irq_mask);
+                             hwdev->hw->map.se_irq_map.irq_mask);
 
         return 0;
 }
@@ -916,5 +920,5 @@ void malidp_se_irq_fini(struct drm_device *drm)
         struct malidp_hw_device *hwdev = malidp->dev;
 
         malidp_hw_disable_irq(hwdev, MALIDP_SE_BLOCK,
-                              hwdev->map.se_irq_map.irq_mask);
+                              hwdev->hw->map.se_irq_map.irq_mask);
 }
diff --git a/drivers/gpu/drm/arm/malidp_hw.h b/drivers/gpu/drm/arm/malidp_hw.h
index 849ad9a30c3a..b0690ebb3565 100644
--- a/drivers/gpu/drm/arm/malidp_hw.h
+++ b/drivers/gpu/drm/arm/malidp_hw.h
@@ -120,18 +120,14 @@ struct malidp_hw_regmap {
 /* Unlike DP550/650, DP500 has 3 stride registers in its video layer. */
 #define MALIDP_DEVICE_LV_HAS_3_STRIDES  BIT(0)
 
-struct malidp_hw_device {
-        const struct malidp_hw_regmap map;
-        void __iomem *regs;
+struct malidp_hw_device;
 
-        /* APB clock */
-        struct clk *pclk;
-        /* AXI clock */
-        struct clk *aclk;
-        /* main clock for display core */
-        struct clk *mclk;
-        /* pixel clock for display core */
-        struct clk *pxlclk;
+/*
+ * Static structure containing hardware specific data and pointers to
+ * functions that behave differently between various versions of the IP.
+ */
+struct malidp_hw {
+        const struct malidp_hw_regmap map;
 
         /*
          * Validate the driver instance against the hardware bits
@@ -182,15 +178,6 @@ struct malidp_hw_device {
                              struct videomode *vm);
 
         u8 features;
-
-        u8 min_line_size;
-        u16 max_line_size;
-
-        /* track the device PM state */
-        bool pm_suspended;
-
-        /* size of memory used for rotating layers, up to two banks available */
-        u32 rotation_memory[2];
 };
 
 /* Supported variants of the hardware */
@@ -202,7 +189,33 @@ enum {
         MALIDP_MAX_DEVICES
 };
 
-extern const struct malidp_hw_device malidp_device[MALIDP_MAX_DEVICES];
+extern const struct malidp_hw malidp_device[MALIDP_MAX_DEVICES];
+
+/*
+ * Structure used by the driver during runtime operation.
+ */
+struct malidp_hw_device {
+        struct malidp_hw *hw;
+        void __iomem *regs;
+
+        /* APB clock */
+        struct clk *pclk;
+        /* AXI clock */
+        struct clk *aclk;
+        /* main clock for display core */
+        struct clk *mclk;
+        /* pixel clock for display core */
+        struct clk *pxlclk;
+
+        u8 min_line_size;
+        u16 max_line_size;
+
+        /* track the device PM state */
+        bool pm_suspended;
+
+        /* size of memory used for rotating layers, up to two banks available */
+        u32 rotation_memory[2];
+};
 
 static inline u32 malidp_hw_read(struct malidp_hw_device *hwdev, u32 reg)
 {
@@ -240,9 +253,9 @@ static inline u32 malidp_get_block_base(struct malidp_hw_device *hwdev,
 {
         switch (block) {
         case MALIDP_SE_BLOCK:
-                return hwdev->map.se_base;
+                return hwdev->hw->map.se_base;
         case MALIDP_DC_BLOCK:
-                return hwdev->map.dc_base;
+                return hwdev->hw->map.dc_base;
         }
 
         return 0;
@@ -275,7 +288,7 @@ u8 malidp_hw_get_format_id(const struct malidp_hw_regmap *map,
 static inline bool malidp_hw_pitch_valid(struct malidp_hw_device *hwdev,
                                          unsigned int pitch)
 {
-        return !(pitch & (hwdev->map.bus_align_bytes - 1));
+        return !(pitch & (hwdev->hw->map.bus_align_bytes - 1));
 }
 
 /* U16.16 */
@@ -308,8 +321,8 @@ static inline void malidp_se_set_enh_coeffs(struct malidp_hw_device *hwdev)
         };
         u32 val = MALIDP_SE_SET_ENH_LIMIT_LOW(MALIDP_SE_ENH_LOW_LEVEL) |
                   MALIDP_SE_SET_ENH_LIMIT_HIGH(MALIDP_SE_ENH_HIGH_LEVEL);
-        u32 image_enh = hwdev->map.se_base +
-                        ((hwdev->map.features & MALIDP_REGMAP_HAS_CLEARIRQ) ?
+        u32 image_enh = hwdev->hw->map.se_base +
+                        ((hwdev->hw->map.features & MALIDP_REGMAP_HAS_CLEARIRQ) ?
                          0x10 : 0xC) + MALIDP_SE_IMAGE_ENH;
         u32 enh_coeffs = image_enh + MALIDP_SE_ENH_COEFF0;
         int i;
diff --git a/drivers/gpu/drm/arm/malidp_planes.c b/drivers/gpu/drm/arm/malidp_planes.c
index 94e7e3fa3408..e7419797bbd1 100644
--- a/drivers/gpu/drm/arm/malidp_planes.c
+++ b/drivers/gpu/drm/arm/malidp_planes.c
@@ -57,7 +57,7 @@ static void malidp_de_plane_destroy(struct drm_plane *plane)
         struct malidp_plane *mp = to_malidp_plane(plane);
 
         if (mp->base.fb)
-                drm_framebuffer_unreference(mp->base.fb);
+                drm_framebuffer_put(mp->base.fb);
 
         drm_plane_helper_disable(plane);
         drm_plane_cleanup(plane);
@@ -185,8 +185,9 @@ static int malidp_de_plane_check(struct drm_plane *plane,
 
         fb = state->fb;
 
-        ms->format = malidp_hw_get_format_id(&mp->hwdev->map, mp->layer->id,
-                                            fb->format->format);
+        ms->format = malidp_hw_get_format_id(&mp->hwdev->hw->map,
+                                             mp->layer->id,
+                                             fb->format->format);
         if (ms->format == MALIDP_INVALID_FORMAT_ID)
                 return -EINVAL;
 
@@ -211,7 +212,7 @@ static int malidp_de_plane_check(struct drm_plane *plane,
          * third plane stride register.
          */
         if (ms->n_planes == 3 &&
-            !(mp->hwdev->features & MALIDP_DEVICE_LV_HAS_3_STRIDES) &&
+            !(mp->hwdev->hw->features & MALIDP_DEVICE_LV_HAS_3_STRIDES) &&
             (state->fb->pitches[1] != state->fb->pitches[2]))
                 return -EINVAL;
 
@@ -229,9 +230,9 @@ static int malidp_de_plane_check(struct drm_plane *plane,
         if (state->rotation & MALIDP_ROTATED_MASK) {
                 int val;
 
-                val = mp->hwdev->rotmem_required(mp->hwdev, state->crtc_h,
-                                                 state->crtc_w,
-                                                 fb->format->format);
+                val = mp->hwdev->hw->rotmem_required(mp->hwdev, state->crtc_h,
+                                                     state->crtc_w,
+                                                     fb->format->format);
                 if (val < 0)
                         return val;
 
@@ -251,7 +252,7 @@ static void malidp_de_set_plane_pitches(struct malidp_plane *mp,
                 return;
 
         if (num_planes == 3)
-                num_strides = (mp->hwdev->features &
+                num_strides = (mp->hwdev->hw->features &
                                MALIDP_DEVICE_LV_HAS_3_STRIDES) ? 3 : 2;
 
         for (i = 0; i < num_strides; ++i)
@@ -264,13 +265,11 @@ static void malidp_de_plane_update(struct drm_plane *plane,
                                    struct drm_plane_state *old_state)
 {
         struct malidp_plane *mp;
-        const struct malidp_hw_regmap *map;
         struct malidp_plane_state *ms = to_malidp_plane_state(plane->state);
         u32 src_w, src_h, dest_w, dest_h, val;
         int i;
 
         mp = to_malidp_plane(plane);
-        map = &mp->hwdev->map;
 
         /* convert src values from Q16 fixed point to integer */
         src_w = plane->state->src_w >> 16;
@@ -363,7 +362,7 @@ static const struct drm_plane_helper_funcs malidp_de_plane_helper_funcs = {
 int malidp_de_planes_init(struct drm_device *drm)
 {
         struct malidp_drm *malidp = drm->dev_private;
-        const struct malidp_hw_regmap *map = &malidp->dev->map;
+        const struct malidp_hw_regmap *map = &malidp->dev->hw->map;
         struct malidp_plane *plane = NULL;
         enum drm_plane_type plane_type;
         unsigned long crtcs = 1 << drm->mode_config.num_crtc;
diff --git a/drivers/gpu/drm/bridge/adv7511/adv7511.h b/drivers/gpu/drm/bridge/adv7511/adv7511.h
index b4efcbabf7f7..d034b2cb5eee 100644
--- a/drivers/gpu/drm/bridge/adv7511/adv7511.h
+++ b/drivers/gpu/drm/bridge/adv7511/adv7511.h
@@ -372,9 +372,18 @@ struct adv7511 {
 };
 
 #ifdef CONFIG_DRM_I2C_ADV7511_CEC
-int adv7511_cec_init(struct device *dev, struct adv7511 *adv7511,
-                     unsigned int offset);
+int adv7511_cec_init(struct device *dev, struct adv7511 *adv7511);
 void adv7511_cec_irq_process(struct adv7511 *adv7511, unsigned int irq1);
+#else
+static inline int adv7511_cec_init(struct device *dev, struct adv7511 *adv7511)
+{
+        unsigned int offset = adv7511->type == ADV7533 ?
+                                                ADV7533_REG_CEC_OFFSET : 0;
+
+        regmap_write(adv7511->regmap, ADV7511_REG_CEC_CTRL + offset,
+                     ADV7511_CEC_CTRL_POWER_DOWN);
+        return 0;
+}
 #endif
 
 #ifdef CONFIG_DRM_I2C_ADV7533
diff --git a/drivers/gpu/drm/bridge/adv7511/adv7511_cec.c b/drivers/gpu/drm/bridge/adv7511/adv7511_cec.c
index b33d730e4d73..a20a45c0b353 100644
--- a/drivers/gpu/drm/bridge/adv7511/adv7511_cec.c
+++ b/drivers/gpu/drm/bridge/adv7511/adv7511_cec.c
@@ -300,18 +300,21 @@ static int adv7511_cec_parse_dt(struct device *dev, struct adv7511 *adv7511)
         return 0;
 }
 
-int adv7511_cec_init(struct device *dev, struct adv7511 *adv7511,
-                     unsigned int offset)
+int adv7511_cec_init(struct device *dev, struct adv7511 *adv7511)
 {
+        unsigned int offset = adv7511->type == ADV7533 ?
+                                                ADV7533_REG_CEC_OFFSET : 0;
         int ret = adv7511_cec_parse_dt(dev, adv7511);
 
         if (ret)
-                return ret;
+                goto err_cec_parse_dt;
 
         adv7511->cec_adap = cec_allocate_adapter(&adv7511_cec_adap_ops,
                 adv7511, dev_name(dev), CEC_CAP_DEFAULTS, ADV7511_MAX_ADDRS);
-        if (IS_ERR(adv7511->cec_adap))
-                return PTR_ERR(adv7511->cec_adap);
+        if (IS_ERR(adv7511->cec_adap)) {
+                ret = PTR_ERR(adv7511->cec_adap);
+                goto err_cec_alloc;
+        }
 
         regmap_write(adv7511->regmap, ADV7511_REG_CEC_CTRL + offset, 0);
         /* cec soft reset */
@@ -329,9 +332,18 @@ int adv7511_cec_init(struct device *dev, struct adv7511 *adv7511,
                      ((adv7511->cec_clk_freq / 750000) - 1) << 2);
 
         ret = cec_register_adapter(adv7511->cec_adap, dev);
-        if (ret) {
-                cec_delete_adapter(adv7511->cec_adap);
-                adv7511->cec_adap = NULL;
-        }
-        return ret;
+        if (ret)
+                goto err_cec_register;
+        return 0;
+
+err_cec_register:
+        cec_delete_adapter(adv7511->cec_adap);
+        adv7511->cec_adap = NULL;
+err_cec_alloc:
+        dev_info(dev, "Initializing CEC failed with error %d, disabling CEC\n",
+                 ret);
+err_cec_parse_dt:
+        regmap_write(adv7511->regmap, ADV7511_REG_CEC_CTRL + offset,
+                     ADV7511_CEC_CTRL_POWER_DOWN);
+        return ret == -EPROBE_DEFER ? ret : 0;
 }
diff --git a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
index 0e14f1572d05..efa29db5fc2b 100644
--- a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
+++ b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
@@ -1084,7 +1084,6 @@ static int adv7511_probe(struct i2c_client *i2c, const struct i2c_device_id *id)
         struct device *dev = &i2c->dev;
         unsigned int main_i2c_addr = i2c->addr << 1;
         unsigned int edid_i2c_addr = main_i2c_addr + 4;
-        unsigned int offset;
         unsigned int val;
         int ret;
 
@@ -1192,24 +1191,16 @@ static int adv7511_probe(struct i2c_client *i2c, const struct i2c_device_id *id)
         if (adv7511->type == ADV7511)
                 adv7511_set_link_config(adv7511, &link_config);
 
+        ret = adv7511_cec_init(dev, adv7511);
+        if (ret)
+                goto err_unregister_cec;
+
         adv7511->bridge.funcs = &adv7511_bridge_funcs;
         adv7511->bridge.of_node = dev->of_node;
 
         drm_bridge_add(&adv7511->bridge);
 
         adv7511_audio_init(dev, adv7511);
-
-        offset = adv7511->type == ADV7533 ? ADV7533_REG_CEC_OFFSET : 0;
-
-#ifdef CONFIG_DRM_I2C_ADV7511_CEC
-        ret = adv7511_cec_init(dev, adv7511, offset);
-        if (ret)
-                goto err_unregister_cec;
-#else
-        regmap_write(adv7511->regmap, ADV7511_REG_CEC_CTRL + offset,
-                     ADV7511_CEC_CTRL_POWER_DOWN);
-#endif
-
         return 0;
 
 err_unregister_cec:
diff --git a/drivers/gpu/drm/bridge/lvds-encoder.c b/drivers/gpu/drm/bridge/lvds-encoder.c
index 0903ba574f61..75b0d3f6e4de 100644
--- a/drivers/gpu/drm/bridge/lvds-encoder.c
+++ b/drivers/gpu/drm/bridge/lvds-encoder.c
@@ -13,13 +13,37 @@
 
 #include <linux/of_graph.h>
 
+struct lvds_encoder {
+        struct drm_bridge bridge;
+        struct drm_bridge *panel_bridge;
+};
+
+static int lvds_encoder_attach(struct drm_bridge *bridge)
+{
+        struct lvds_encoder *lvds_encoder = container_of(bridge,
+                                                         struct lvds_encoder,
+                                                         bridge);
+
+        return drm_bridge_attach(bridge->encoder, lvds_encoder->panel_bridge,
+                                 bridge);
+}
+
+static struct drm_bridge_funcs funcs = {
+        .attach = lvds_encoder_attach,
+};
+
 static int lvds_encoder_probe(struct platform_device *pdev)
 {
         struct device_node *port;
         struct device_node *endpoint;
         struct device_node *panel_node;
         struct drm_panel *panel;
-        struct drm_bridge *bridge;
+        struct lvds_encoder *lvds_encoder;
+
+        lvds_encoder = devm_kzalloc(&pdev->dev, sizeof(*lvds_encoder),
+                                    GFP_KERNEL);
+        if (!lvds_encoder)
+                return -ENOMEM;
 
         /* Locate the panel DT node. */
         port = of_graph_get_port_by_id(pdev->dev.of_node, 1);
@@ -49,20 +73,30 @@ static int lvds_encoder_probe(struct platform_device *pdev)
                 return -EPROBE_DEFER;
         }
 
-        bridge = drm_panel_bridge_add(panel, DRM_MODE_CONNECTOR_LVDS);
-        if (IS_ERR(bridge))
-                return PTR_ERR(bridge);
+        lvds_encoder->panel_bridge =
+                devm_drm_panel_bridge_add(&pdev->dev,
+                                          panel, DRM_MODE_CONNECTOR_LVDS);
+        if (IS_ERR(lvds_encoder->panel_bridge))
+                return PTR_ERR(lvds_encoder->panel_bridge);
+
+        /* The panel_bridge bridge is attached to the panel's of_node,
+         * but we need a bridge attached to our of_node for our user
+         * to look up.
+         */
+        lvds_encoder->bridge.of_node = pdev->dev.of_node;
+        lvds_encoder->bridge.funcs = &funcs;
+        drm_bridge_add(&lvds_encoder->bridge);
 
-        platform_set_drvdata(pdev, bridge);
+        platform_set_drvdata(pdev, lvds_encoder);
 
         return 0;
 }
 
 static int lvds_encoder_remove(struct platform_device *pdev)
 {
-        struct drm_bridge *bridge = platform_get_drvdata(pdev);
+        struct lvds_encoder *lvds_encoder = platform_get_drvdata(pdev);
 
-        drm_bridge_remove(bridge);
+        drm_bridge_remove(&lvds_encoder->bridge);
 
         return 0;
 }
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
index bf14214fa464..b72259bf6e2f 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
@@ -138,6 +138,7 @@ struct dw_hdmi {
         struct device *dev;
         struct clk *isfr_clk;
         struct clk *iahb_clk;
+        struct clk *cec_clk;
         struct dw_hdmi_i2c *i2c;
 
         struct hdmi_data_info hdmi_data;
@@ -2382,6 +2383,26 @@ __dw_hdmi_probe(struct platform_device *pdev,
                 goto err_isfr;
         }
 
+        hdmi->cec_clk = devm_clk_get(hdmi->dev, "cec");
+        if (PTR_ERR(hdmi->cec_clk) == -ENOENT) {
+                hdmi->cec_clk = NULL;
+        } else if (IS_ERR(hdmi->cec_clk)) {
+                ret = PTR_ERR(hdmi->cec_clk);
+                if (ret != -EPROBE_DEFER)
+                        dev_err(hdmi->dev, "Cannot get HDMI cec clock: %d\n",
+                                ret);
+
+                hdmi->cec_clk = NULL;
+                goto err_iahb;
+        } else {
+                ret = clk_prepare_enable(hdmi->cec_clk);
+                if (ret) {
+                        dev_err(hdmi->dev, "Cannot enable HDMI cec clock: %d\n",
+                                ret);
+                        goto err_iahb;
+                }
+        }
+
         /* Product and revision IDs */
         hdmi->version = (hdmi_readb(hdmi, HDMI_DESIGN_ID) << 8)
                       | (hdmi_readb(hdmi, HDMI_REVISION_ID) << 0);
@@ -2518,6 +2539,8 @@ err_iahb:
                 cec_notifier_put(hdmi->cec_notifier);
 
         clk_disable_unprepare(hdmi->iahb_clk);
+        if (hdmi->cec_clk)
+                clk_disable_unprepare(hdmi->cec_clk);
 err_isfr:
         clk_disable_unprepare(hdmi->isfr_clk);
 err_res:
@@ -2541,6 +2564,8 @@ static void __dw_hdmi_remove(struct dw_hdmi *hdmi)
 
         clk_disable_unprepare(hdmi->iahb_clk);
         clk_disable_unprepare(hdmi->isfr_clk);
+        if (hdmi->cec_clk)
+                clk_disable_unprepare(hdmi->cec_clk);
 
         if (hdmi->i2c)
                 i2c_del_adapter(&hdmi->i2c->adap);
diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c
index 8571cfd877c5..8636e7eeb731 100644
--- a/drivers/gpu/drm/bridge/tc358767.c
+++ b/drivers/gpu/drm/bridge/tc358767.c
@@ -97,7 +97,7 @@
 #define DP0_ACTIVEVAL           0x0650
 #define DP0_SYNCVAL             0x0654
 #define DP0_MISC                0x0658
-#define TU_SIZE_RECOMMENDED             (0x3f << 16) /* LSCLK cycles per TU */
+#define TU_SIZE_RECOMMENDED             (63) /* LSCLK cycles per TU */
 #define BPC_6                           (0 << 5)
 #define BPC_8                           (1 << 5)
 
@@ -318,7 +318,7 @@ static ssize_t tc_aux_transfer(struct drm_dp_aux *aux,
                                 tmp = (tmp << 8) | buf[i];
                         i++;
                         if (((i % 4) == 0) || (i == size)) {
-                                tc_write(DP0_AUXWDATA(i >> 2), tmp);
+                                tc_write(DP0_AUXWDATA((i - 1) >> 2), tmp);
                                 tmp = 0;
                         }
                 }
@@ -603,8 +603,15 @@ static int tc_get_display_props(struct tc_data *tc)
         ret = drm_dp_link_probe(&tc->aux, &tc->link.base);
         if (ret < 0)
                 goto err_dpcd_read;
-        if ((tc->link.base.rate != 162000) && (tc->link.base.rate != 270000))
-                goto err_dpcd_inval;
+        if (tc->link.base.rate != 162000 && tc->link.base.rate != 270000) {
+                dev_dbg(tc->dev, "Falling to 2.7 Gbps rate\n");
+                tc->link.base.rate = 270000;
+        }
+
+        if (tc->link.base.num_lanes > 2) {
+                dev_dbg(tc->dev, "Falling to 2 lanes\n");
+                tc->link.base.num_lanes = 2;
+        }
 
         ret = drm_dp_dpcd_readb(&tc->aux, DP_MAX_DOWNSPREAD, tmp);
         if (ret < 0)
@@ -637,9 +644,6 @@ static int tc_get_display_props(struct tc_data *tc)
 err_dpcd_read:
         dev_err(tc->dev, "failed to read DPCD: %d\n", ret);
         return ret;
-err_dpcd_inval:
-        dev_err(tc->dev, "invalid DPCD\n");
-        return -EINVAL;
 }
 
 static int tc_set_video_mode(struct tc_data *tc, struct drm_display_mode *mode)
@@ -655,6 +659,14 @@ static int tc_set_video_mode(struct tc_data *tc, struct drm_display_mode *mode)
         int lower_margin = mode->vsync_start - mode->vdisplay;
         int vsync_len = mode->vsync_end - mode->vsync_start;
 
+        /*
+         * Recommended maximum number of symbols transferred in a transfer unit:
+         * DIV_ROUND_UP((input active video bandwidth in bytes) * tu_size,
+         *              (output active video bandwidth in bytes))
+         * Must be less than tu_size.
+         */
+        max_tu_symbol = TU_SIZE_RECOMMENDED - 1;
+
         dev_dbg(tc->dev, "set mode %dx%d\n",
                 mode->hdisplay, mode->vdisplay);
         dev_dbg(tc->dev, "H margin %d,%d sync %d\n",
@@ -664,13 +676,18 @@ static int tc_set_video_mode(struct tc_data *tc, struct drm_display_mode *mode)
         dev_dbg(tc->dev, "total: %dx%d\n", mode->htotal, mode->vtotal);
 
 
-        /* LCD Ctl Frame Size */
-        tc_write(VPCTRL0, (0x40 << 20) /* VSDELAY */ |
+        /*
+         * LCD Ctl Frame Size
+         * datasheet is not clear of vsdelay in case of DPI
+         * assume we do not need any delay when DPI is a source of
+         * sync signals
+         */
+        tc_write(VPCTRL0, (0 << 20) /* VSDELAY */ |
                  OPXLFMT_RGB888 | FRMSYNC_DISABLED | MSF_DISABLED);
-        tc_write(HTIM01, (left_margin << 16) |          /* H back porch */
-                         (hsync_len << 0));             /* Hsync */
-        tc_write(HTIM02, (right_margin << 16) |         /* H front porch */
-                         (mode->hdisplay << 0));        /* width */
+        tc_write(HTIM01, (ALIGN(left_margin, 2) << 16) | /* H back porch */
+                         (ALIGN(hsync_len, 2) << 0));    /* Hsync */
+        tc_write(HTIM02, (ALIGN(right_margin, 2) << 16) |  /* H front porch */
+                         (ALIGN(mode->hdisplay, 2) << 0)); /* width */
         tc_write(VTIM01, (upper_margin << 16) |         /* V back porch */
                          (vsync_len << 0));             /* Vsync */
         tc_write(VTIM02, (lower_margin << 16) |         /* V front porch */
@@ -689,7 +706,7 @@ static int tc_set_video_mode(struct tc_data *tc, struct drm_display_mode *mode)
         /* DP Main Stream Attributes */
         vid_sync_dly = hsync_len + left_margin + mode->hdisplay;
         tc_write(DP0_VIDSYNCDELAY,
-                 (0x003e << 16) |       /* thresh_dly */
+                 (max_tu_symbol << 16) |        /* thresh_dly */
                  (vid_sync_dly << 0));
 
         tc_write(DP0_TOTALVAL, (mode->vtotal << 16) | (mode->htotal));
@@ -705,14 +722,8 @@ static int tc_set_video_mode(struct tc_data *tc, struct drm_display_mode *mode)
         tc_write(DPIPXLFMT, VS_POL_ACTIVE_LOW | HS_POL_ACTIVE_LOW |
                  DE_POL_ACTIVE_HIGH | SUB_CFG_TYPE_CONFIG1 | DPI_BPP_RGB888);
 
-        /*
-         * Recommended maximum number of symbols transferred in a transfer unit:
-         * DIV_ROUND_UP((input active video bandwidth in bytes) * tu_size,
-         *              (output active video bandwidth in bytes))
-         * Must be less than tu_size.
-         */
-        max_tu_symbol = TU_SIZE_RECOMMENDED - 1;
-        tc_write(DP0_MISC, (max_tu_symbol << 23) | TU_SIZE_RECOMMENDED | BPC_8);
+        tc_write(DP0_MISC, (max_tu_symbol << 23) | (TU_SIZE_RECOMMENDED << 16) |
+                           BPC_8);
 
         return 0;
 err:
@@ -808,8 +819,6 @@ static int tc_main_link_setup(struct tc_data *tc)
         unsigned int rate;
         u32 dp_phy_ctrl;
         int timeout;
-        bool aligned;
-        bool ready;
         u32 value;
         int ret;
         u8 tmp[8];
@@ -954,16 +963,15 @@ static int tc_main_link_setup(struct tc_data *tc)
                 ret = drm_dp_dpcd_read_link_status(aux, tmp + 2);
                 if (ret < 0)
                         goto err_dpcd_read;
-                ready = (tmp[2] == ((DP_CHANNEL_EQ_BITS << 4) | /* Lane1 */
-                                     DP_CHANNEL_EQ_BITS));      /* Lane0 */
-                aligned = tmp[4] & DP_INTERLANE_ALIGN_DONE;
-        } while ((--timeout) && !(ready && aligned));
+        } while ((--timeout) &&
+                 !(drm_dp_channel_eq_ok(tmp + 2,  tc->link.base.num_lanes)));
 
         if (timeout == 0) {
                 /* Read DPCD 0x200-0x201 */
                 ret = drm_dp_dpcd_read(aux, DP_SINK_COUNT, tmp, 2);
                 if (ret < 0)
                         goto err_dpcd_read;
+                dev_err(dev, "channel(s) EQ not ok\n");
                 dev_info(dev, "0x0200 SINK_COUNT: 0x%02x\n", tmp[0]);
                 dev_info(dev, "0x0201 DEVICE_SERVICE_IRQ_VECTOR: 0x%02x\n",
                          tmp[1]);
@@ -974,10 +982,6 @@ static int tc_main_link_setup(struct tc_data *tc)
                 dev_info(dev, "0x0206 ADJUST_REQUEST_LANE0_1: 0x%02x\n",
                          tmp[6]);
 
-                if (!ready)
-                        dev_err(dev, "Lane0/1 not ready\n");
-                if (!aligned)
-                        dev_err(dev, "Lane0/1 not aligned\n");
                 return -EAGAIN;
         }
 
@@ -1099,7 +1103,10 @@ static bool tc_bridge_mode_fixup(struct drm_bridge *bridge,
 static int tc_connector_mode_valid(struct drm_connector *connector,
                                    struct drm_display_mode *mode)
 {
-        /* Accept any mode */
+        /* DPI interface clock limitation: upto 154 MHz */
+        if (mode->clock > 154000)
+                return MODE_CLOCK_HIGH;
+
         return MODE_OK;
 }
 
diff --git a/drivers/gpu/drm/drm_atomic_helper.c b/drivers/gpu/drm/drm_atomic_helper.c
index 71d712f1b56a..b16f1d69a0bb 100644
--- a/drivers/gpu/drm/drm_atomic_helper.c
+++ b/drivers/gpu/drm/drm_atomic_helper.c
@@ -1225,7 +1225,7 @@ drm_atomic_helper_wait_for_vblanks(struct drm_device *dev,
                 return;
 
         for_each_oldnew_crtc_in_state(old_state, crtc, old_crtc_state, new_crtc_state, i) {
-                if (!new_crtc_state->active || !new_crtc_state->planes_changed)
+                if (!new_crtc_state->active)
                         continue;
 
                 ret = drm_crtc_vblank_get(crtc);
diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c
index 07374008f146..e56166334455 100644
--- a/drivers/gpu/drm/drm_fb_helper.c
+++ b/drivers/gpu/drm/drm_fb_helper.c
@@ -1809,6 +1809,10 @@ static int drm_fb_helper_single_fb_probe(struct drm_fb_helper *fb_helper,
 
         if (crtc_count == 0 || sizes.fb_width == -1 || sizes.fb_height == -1) {
                 DRM_INFO("Cannot find any crtc or sizes\n");
+
+                /* First time: disable all crtc's.. */
+                if (!fb_helper->deferred_setup && !READ_ONCE(fb_helper->dev->master))
+                        restore_fbdev_mode(fb_helper);
                 return -EAGAIN;
         }
 
diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c
index 3c318439a659..355120865efd 100644
--- a/drivers/gpu/drm/i915/gvt/display.c
+++ b/drivers/gpu/drm/i915/gvt/display.c
@@ -282,6 +282,7 @@ static void clean_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num)
 static int setup_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num,
                                     int type, unsigned int resolution)
 {
+        struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
         struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num);
 
         if (WARN_ON(resolution >= GVT_EDID_NUM))
@@ -307,6 +308,7 @@ static int setup_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num,
         port->type = type;
 
         emulate_monitor_status_change(vgpu);
+        vgpu_vreg(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE;
         return 0;
 }
 
diff --git a/drivers/gpu/drm/i915/gvt/execlist.c b/drivers/gpu/drm/i915/gvt/execlist.c
index 4427be18e4a9..940cdaaa3f24 100644
--- a/drivers/gpu/drm/i915/gvt/execlist.c
+++ b/drivers/gpu/drm/i915/gvt/execlist.c
@@ -496,6 +496,12 @@ static int prepare_execlist_workload(struct intel_vgpu_workload *workload)
                 goto err_unpin_mm;
         }
 
+        ret = intel_gvt_generate_request(workload);
+        if (ret) {
+                gvt_vgpu_err("fail to generate request\n");
+                goto err_unpin_mm;
+        }
+
         ret = prepare_shadow_batch_buffer(workload);
         if (ret) {
                 gvt_vgpu_err("fail to prepare_shadow_batch_buffer\n");
diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
index 2801d70579d8..8e331142badb 100644
--- a/drivers/gpu/drm/i915/gvt/gtt.c
+++ b/drivers/gpu/drm/i915/gvt/gtt.c
@@ -311,9 +311,9 @@ static inline int gtt_set_entry64(void *pt,
 
 #define GTT_HAW 46
 
-#define ADDR_1G_MASK (((1UL << (GTT_HAW - 30 + 1)) - 1) << 30)
-#define ADDR_2M_MASK (((1UL << (GTT_HAW - 21 + 1)) - 1) << 21)
-#define ADDR_4K_MASK (((1UL << (GTT_HAW - 12 + 1)) - 1) << 12)
+#define ADDR_1G_MASK (((1UL << (GTT_HAW - 30)) - 1) << 30)
+#define ADDR_2M_MASK (((1UL << (GTT_HAW - 21)) - 1) << 21)
+#define ADDR_4K_MASK (((1UL << (GTT_HAW - 12)) - 1) << 12)
 
 static unsigned long gen8_gtt_get_pfn(struct intel_gvt_gtt_entry *e)
 {
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index a5bed2e71b92..44cd5ff5e97d 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -1381,40 +1381,6 @@ static int skl_power_well_ctl_write(struct intel_vgpu *vgpu,
         return intel_vgpu_default_mmio_write(vgpu, offset, &v, bytes);
 }
 
-static int skl_misc_ctl_write(struct intel_vgpu *vgpu, unsigned int offset,
-                void *p_data, unsigned int bytes)
-{
-        struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
-        u32 v = *(u32 *)p_data;
-
-        if (!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv))
-                return intel_vgpu_default_mmio_write(vgpu,
-                                offset, p_data, bytes);
-
-        switch (offset) {
-        case 0x4ddc:
-                /* bypass WaCompressedResourceSamplerPbeMediaNewHashMode */
-                vgpu_vreg(vgpu, offset) = v & ~(1 << 31);
-                break;
-        case 0x42080:
-                /* bypass WaCompressedResourceDisplayNewHashMode */
-                vgpu_vreg(vgpu, offset) = v & ~(1 << 15);
-                break;
-        case 0xe194:
-                /* bypass WaCompressedResourceSamplerPbeMediaNewHashMode */
-                vgpu_vreg(vgpu, offset) = v & ~(1 << 8);
-                break;
-        case 0x7014:
-                /* bypass WaCompressedResourceSamplerPbeMediaNewHashMode */
-                vgpu_vreg(vgpu, offset) = v & ~(1 << 13);
-                break;
-        default:
-                return -EINVAL;
-        }
-
-        return 0;
-}
-
 static int skl_lcpll_write(struct intel_vgpu *vgpu, unsigned int offset,
                 void *p_data, unsigned int bytes)
 {
@@ -1671,8 +1637,8 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
         MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL);
         MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
                 NULL, NULL);
-        MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL,
-                 skl_misc_ctl_write);
+        MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
+                 NULL, NULL);
         MMIO_DFH(0x9030, D_ALL, F_CMD_ACCESS, NULL, NULL);
         MMIO_DFH(0x20a0, D_ALL, F_CMD_ACCESS, NULL, NULL);
         MMIO_DFH(0x2420, D_ALL, F_CMD_ACCESS, NULL, NULL);
@@ -2564,8 +2530,7 @@ static int init_broadwell_mmio_info(struct intel_gvt *gvt)
         MMIO_D(0x6e570, D_BDW_PLUS);
         MMIO_D(0x65f10, D_BDW_PLUS);
 
-        MMIO_DFH(0xe194, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL,
-                 skl_misc_ctl_write);
+        MMIO_DFH(0xe194, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
         MMIO_DFH(0xe188, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
         MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
         MMIO_DFH(0x2580, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
@@ -2615,8 +2580,8 @@ static int init_skl_mmio_info(struct intel_gvt *gvt)
         MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
         MMIO_D(GEN9_RENDER_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
         MMIO_DFH(GEN9_GAMT_ECO_REG_RW_IA, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
-        MMIO_DH(0x4ddc, D_SKL_PLUS, NULL, skl_misc_ctl_write);
-        MMIO_DH(0x42080, D_SKL_PLUS, NULL, skl_misc_ctl_write);
+        MMIO_DH(0x4ddc, D_SKL_PLUS, NULL, NULL);
+        MMIO_DH(0x42080, D_SKL_PLUS, NULL, NULL);
         MMIO_D(0x45504, D_SKL_PLUS);
         MMIO_D(0x45520, D_SKL_PLUS);
         MMIO_D(0x46000, D_SKL_PLUS);
diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c
index f6ded475bb2c..3ac1dc97a7a0 100644
--- a/drivers/gpu/drm/i915/gvt/scheduler.c
+++ b/drivers/gpu/drm/i915/gvt/scheduler.c
@@ -140,9 +140,10 @@ static int shadow_context_status_change(struct notifier_block *nb,
         struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
         enum intel_engine_id ring_id = req->engine->id;
         struct intel_vgpu_workload *workload;
+        unsigned long flags;
 
         if (!is_gvt_request(req)) {
-                spin_lock_bh(&scheduler->mmio_context_lock);
+                spin_lock_irqsave(&scheduler->mmio_context_lock, flags);
                 if (action == INTEL_CONTEXT_SCHEDULE_IN &&
                     scheduler->engine_owner[ring_id]) {
                         /* Switch ring from vGPU to host. */
@@ -150,7 +151,7 @@ static int shadow_context_status_change(struct notifier_block *nb,
                                               NULL, ring_id);
                         scheduler->engine_owner[ring_id] = NULL;
                 }
-                spin_unlock_bh(&scheduler->mmio_context_lock);
+                spin_unlock_irqrestore(&scheduler->mmio_context_lock, flags);
 
                 return NOTIFY_OK;
         }
@@ -161,7 +162,7 @@ static int shadow_context_status_change(struct notifier_block *nb,
 
         switch (action) {
         case INTEL_CONTEXT_SCHEDULE_IN:
-                spin_lock_bh(&scheduler->mmio_context_lock);
+                spin_lock_irqsave(&scheduler->mmio_context_lock, flags);
                 if (workload->vgpu != scheduler->engine_owner[ring_id]) {
                         /* Switch ring from host to vGPU or vGPU to vGPU. */
                         intel_gvt_switch_mmio(scheduler->engine_owner[ring_id],
@@ -170,7 +171,7 @@ static int shadow_context_status_change(struct notifier_block *nb,
                 } else
                         gvt_dbg_sched("skip ring %d mmio switch for vgpu%d\n",
                                       ring_id, workload->vgpu->id);
-                spin_unlock_bh(&scheduler->mmio_context_lock);
+                spin_unlock_irqrestore(&scheduler->mmio_context_lock, flags);
                 atomic_set(&workload->shadow_ctx_active, 1);
                 break;
         case INTEL_CONTEXT_SCHEDULE_OUT:
@@ -253,7 +254,6 @@ int intel_gvt_scan_and_shadow_workload(struct intel_vgpu_workload *workload)
         struct i915_gem_context *shadow_ctx = workload->vgpu->shadow_ctx;
         struct drm_i915_private *dev_priv = workload->vgpu->gvt->dev_priv;
         struct intel_engine_cs *engine = dev_priv->engine[ring_id];
-        struct drm_i915_gem_request *rq;
         struct intel_vgpu *vgpu = workload->vgpu;
         struct intel_ring *ring;
         int ret;
@@ -299,6 +299,26 @@ int intel_gvt_scan_and_shadow_workload(struct intel_vgpu_workload *workload)
         ret = populate_shadow_context(workload);
         if (ret)
                 goto err_unpin;
+        workload->shadowed = true;
+        return 0;
+
+err_unpin:
+        engine->context_unpin(engine, shadow_ctx);
+err_shadow:
+        release_shadow_wa_ctx(&workload->wa_ctx);
+err_scan:
+        return ret;
+}
+
+int intel_gvt_generate_request(struct intel_vgpu_workload *workload)
+{
+        int ring_id = workload->ring_id;
+        struct drm_i915_private *dev_priv = workload->vgpu->gvt->dev_priv;
+        struct intel_engine_cs *engine = dev_priv->engine[ring_id];
+        struct drm_i915_gem_request *rq;
+        struct intel_vgpu *vgpu = workload->vgpu;
+        struct i915_gem_context *shadow_ctx = vgpu->shadow_ctx;
+        int ret;
 
         rq = i915_gem_request_alloc(dev_priv->engine[ring_id], shadow_ctx);
         if (IS_ERR(rq)) {
@@ -313,14 +333,11 @@ int intel_gvt_scan_and_shadow_workload(struct intel_vgpu_workload *workload)
         ret = copy_workload_to_ring_buffer(workload);
         if (ret)
                 goto err_unpin;
-        workload->shadowed = true;
         return 0;
 
 err_unpin:
         engine->context_unpin(engine, shadow_ctx);
-err_shadow:
         release_shadow_wa_ctx(&workload->wa_ctx);
-err_scan:
         return ret;
 }
 
diff --git a/drivers/gpu/drm/i915/gvt/scheduler.h b/drivers/gpu/drm/i915/gvt/scheduler.h
index 2d694f6c0907..b9f872204d7e 100644
--- a/drivers/gpu/drm/i915/gvt/scheduler.h
+++ b/drivers/gpu/drm/i915/gvt/scheduler.h
@@ -142,4 +142,7 @@ int intel_vgpu_init_gvt_context(struct intel_vgpu *vgpu);
 void intel_vgpu_clean_gvt_context(struct intel_vgpu *vgpu);
 
 void release_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx);
+
+int intel_gvt_generate_request(struct intel_vgpu_workload *workload);
+
 #endif
diff --git a/drivers/gpu/drm/i915/i915_gemfs.c b/drivers/gpu/drm/i915/i915_gemfs.c
index e2993857df37..888b7d3f04c3 100644
--- a/drivers/gpu/drm/i915/i915_gemfs.c
+++ b/drivers/gpu/drm/i915/i915_gemfs.c
@@ -52,7 +52,8 @@ int i915_gemfs_init(struct drm_i915_private *i915)
 
         if (has_transparent_hugepage()) {
                 struct super_block *sb = gemfs->mnt_sb;
-                char options[] = "huge=within_size";
+                /* FIXME: Disabled until we get W/A for read BW issue. */
+                char options[] = "huge=never";
                 int flags = 0;
                 int err;
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 7bc60c848940..6c7f8bca574e 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1736,7 +1736,7 @@ extern struct drm_display_mode *intel_find_panel_downclock(
 int intel_backlight_device_register(struct intel_connector *connector);
 void intel_backlight_device_unregister(struct intel_connector *connector);
 #else /* CONFIG_BACKLIGHT_CLASS_DEVICE */
-static int intel_backlight_device_register(struct intel_connector *connector)
+static inline int intel_backlight_device_register(struct intel_connector *connector)
 {
         return 0;
 }
diff --git a/drivers/gpu/drm/i915/intel_fbdev.c b/drivers/gpu/drm/i915/intel_fbdev.c
index b8af35187d22..ea96682568e8 100644
--- a/drivers/gpu/drm/i915/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/intel_fbdev.c
@@ -697,10 +697,8 @@ static void intel_fbdev_initial_config(void *data, async_cookie_t cookie)
 
         /* Due to peculiar init order wrt to hpd handling this is separate. */
         if (drm_fb_helper_initial_config(&ifbdev->helper,
-                                         ifbdev->preferred_bpp)) {
+                                         ifbdev->preferred_bpp))
                 intel_fbdev_unregister(to_i915(ifbdev->helper.dev));
-                intel_fbdev_fini(to_i915(ifbdev->helper.dev));
-        }
 }
 
 void intel_fbdev_initial_config_async(struct drm_device *dev)
@@ -800,7 +798,11 @@ void intel_fbdev_output_poll_changed(struct drm_device *dev)
 {
         struct intel_fbdev *ifbdev = to_i915(dev)->fbdev;
 
-        if (ifbdev)
+        if (!ifbdev)
+                return;
+
+        intel_fbdev_sync(ifbdev);
+        if (ifbdev->vma)
                 drm_fb_helper_hotplug_event(&ifbdev->helper);
 }
 
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index eb5827110d8f..49fdf09f9919 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -438,7 +438,9 @@ static bool
 gmbus_is_index_read(struct i2c_msg *msgs, int i, int num)
 {
         return (i + 1 < num &&
-                !(msgs[i].flags & I2C_M_RD) && msgs[i].len <= 2 &&
+                msgs[i].addr == msgs[i + 1].addr &&
+                !(msgs[i].flags & I2C_M_RD) &&
+                (msgs[i].len == 1 || msgs[i].len == 2) &&
                 (msgs[i + 1].flags & I2C_M_RD));
 }
 
diff --git a/drivers/gpu/drm/imx/imx-drm-core.c b/drivers/gpu/drm/imx/imx-drm-core.c
index 93c7e3f9b4a8..17d2f3a1c562 100644
--- a/drivers/gpu/drm/imx/imx-drm-core.c
+++ b/drivers/gpu/drm/imx/imx-drm-core.c
@@ -133,9 +133,16 @@ static void imx_drm_atomic_commit_tail(struct drm_atomic_state *state)
                         plane_disabling = true;
         }
 
-        if (plane_disabling) {
-                drm_atomic_helper_wait_for_vblanks(dev, state);
+        /*
+         * The flip done wait is only strictly required by imx-drm if a deferred
+         * plane disable is in-flight. As the core requires blocking commits
+         * to wait for the flip it is done here unconditionally. This keeps the
+         * workitem around a bit longer than required for the majority of
+         * non-blocking commits, but we accept that for the sake of simplicity.
+         */
+        drm_atomic_helper_wait_for_flip_done(dev, state);
 
+        if (plane_disabling) {
                 for_each_old_plane_in_state(state, plane, old_plane_state, i)
                         ipu_plane_disable_deferred(plane);
 
diff --git a/drivers/gpu/drm/omapdrm/displays/Kconfig b/drivers/gpu/drm/omapdrm/displays/Kconfig
index c226da145fb3..a349cb61961e 100644
--- a/drivers/gpu/drm/omapdrm/displays/Kconfig
+++ b/drivers/gpu/drm/omapdrm/displays/Kconfig
@@ -35,6 +35,7 @@ config DRM_OMAP_CONNECTOR_ANALOG_TV
 
 config DRM_OMAP_PANEL_DPI
         tristate "Generic DPI panel"
+        depends on BACKLIGHT_CLASS_DEVICE
         help
           Driver for generic DPI panels.
 
diff --git a/drivers/gpu/drm/omapdrm/dss/dpi.c b/drivers/gpu/drm/omapdrm/dss/dpi.c
index daf286fc8a40..ca1e3b489540 100644
--- a/drivers/gpu/drm/omapdrm/dss/dpi.c
+++ b/drivers/gpu/drm/omapdrm/dss/dpi.c
@@ -566,8 +566,8 @@ static int dpi_verify_pll(struct dss_pll *pll)
 }
 
 static const struct soc_device_attribute dpi_soc_devices[] = {
-        { .family = "OMAP3[456]*" },
-        { .family = "[AD]M37*" },
+        { .machine = "OMAP3[456]*" },
+        { .machine = "[AD]M37*" },
         { /* sentinel */ }
 };
 
diff --git a/drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c b/drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c
index d86873f2abe6..e626eddf24d5 100644
--- a/drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c
+++ b/drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c
@@ -352,7 +352,7 @@ int hdmi4_cec_init(struct platform_device *pdev, struct hdmi_core_data *core,
 {
         const u32 caps = CEC_CAP_TRANSMIT | CEC_CAP_LOG_ADDRS |
                          CEC_CAP_PASSTHROUGH | CEC_CAP_RC;
-        unsigned int ret;
+        int ret;
 
         core->adap = cec_allocate_adapter(&hdmi_cec_adap_ops, core,
                 "omap4", caps, CEC_MAX_LOG_ADDRS);
diff --git a/drivers/gpu/drm/omapdrm/dss/hdmi4_core.c b/drivers/gpu/drm/omapdrm/dss/hdmi4_core.c
index 62e451162d96..b06f9956e733 100644
--- a/drivers/gpu/drm/omapdrm/dss/hdmi4_core.c
+++ b/drivers/gpu/drm/omapdrm/dss/hdmi4_core.c
@@ -886,25 +886,36 @@ struct hdmi4_features {
         bool audio_use_mclk;
 };
 
-static const struct hdmi4_features hdmi4_es1_features = {
+static const struct hdmi4_features hdmi4430_es1_features = {
         .cts_swmode = false,
         .audio_use_mclk = false,
 };
 
-static const struct hdmi4_features hdmi4_es2_features = {
+static const struct hdmi4_features hdmi4430_es2_features = {
         .cts_swmode = true,
         .audio_use_mclk = false,
 };
 
-static const struct hdmi4_features hdmi4_es3_features = {
+static const struct hdmi4_features hdmi4_features = {
         .cts_swmode = true,
         .audio_use_mclk = true,
 };
 
 static const struct soc_device_attribute hdmi4_soc_devices[] = {
-        { .family = "OMAP4", .revision = "ES1.?", .data = &hdmi4_es1_features },
-        { .family = "OMAP4", .revision = "ES2.?", .data = &hdmi4_es2_features },
-        { .family = "OMAP4",                      .data = &hdmi4_es3_features },
+        {
+                .machine = "OMAP4430",
+                .revision = "ES1.?",
+                .data = &hdmi4430_es1_features,
+        },
+        {
+                .machine = "OMAP4430",
+                .revision = "ES2.?",
+                .data = &hdmi4430_es2_features,
+        },
+        {
+                .family = "OMAP4",
+                .data = &hdmi4_features,
+        },
         { /* sentinel */ }
 };
 
diff --git a/drivers/gpu/drm/omapdrm/omap_dmm_tiler.c b/drivers/gpu/drm/omapdrm/omap_dmm_tiler.c
index 1dd3dafc59af..c60a85e82c6d 100644
--- a/drivers/gpu/drm/omapdrm/omap_dmm_tiler.c
+++ b/drivers/gpu/drm/omapdrm/omap_dmm_tiler.c
@@ -638,7 +638,8 @@ static int omap_dmm_probe(struct platform_device *dev)
                 match = of_match_node(dmm_of_match, dev->dev.of_node);
                 if (!match) {
                         dev_err(&dev->dev, "failed to find matching device node\n");
-                        return -ENODEV;
+                        ret = -ENODEV;
+                        goto fail;
                 }
 
                 omap_dmm->plat_data = match->data;
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index 898f9a078830..a6511918f632 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -5451,28 +5451,6 @@ void cik_pcie_gart_tlb_flush(struct radeon_device *rdev)
         WREG32(VM_INVALIDATE_REQUEST, 0x1);
 }
 
-static void cik_pcie_init_compute_vmid(struct radeon_device *rdev)
-{
-        int i;
-        uint32_t sh_mem_bases, sh_mem_config;
-
-        sh_mem_bases = 0x6000 | 0x6000 << 16;
-        sh_mem_config = ALIGNMENT_MODE(SH_MEM_ALIGNMENT_MODE_UNALIGNED);
-        sh_mem_config |= DEFAULT_MTYPE(MTYPE_NONCACHED);
-
-        mutex_lock(&rdev->srbm_mutex);
-        for (i = 8; i < 16; i++) {
-                cik_srbm_select(rdev, 0, 0, 0, i);
-                /* CP and shaders */
-                WREG32(SH_MEM_CONFIG, sh_mem_config);
-                WREG32(SH_MEM_APE1_BASE, 1);
-                WREG32(SH_MEM_APE1_LIMIT, 0);
-                WREG32(SH_MEM_BASES, sh_mem_bases);
-        }
-        cik_srbm_select(rdev, 0, 0, 0, 0);
-        mutex_unlock(&rdev->srbm_mutex);
-}
-
 /**
  * cik_pcie_gart_enable - gart enable
  *
@@ -5586,8 +5564,6 @@ static int cik_pcie_gart_enable(struct radeon_device *rdev)
         cik_srbm_select(rdev, 0, 0, 0, 0);
         mutex_unlock(&rdev->srbm_mutex);
 
-        cik_pcie_init_compute_vmid(rdev);
-
         cik_pcie_gart_tlb_flush(rdev);
         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
                  (unsigned)(rdev->mc.gtt_size >> 20),
diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
index b15755b6129c..b1fe0639227e 100644
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
@@ -1285,8 +1285,6 @@ static int dw_mipi_dsi_bind(struct device *dev, struct device *master,
                 goto err_pllref;
         }
 
-        pm_runtime_enable(dev);
-
         dsi->dsi_host.ops = &dw_mipi_dsi_host_ops;
         dsi->dsi_host.dev = dev;
         ret = mipi_dsi_host_register(&dsi->dsi_host);
@@ -1301,6 +1299,7 @@ static int dw_mipi_dsi_bind(struct device *dev, struct device *master,
         }
 
         dev_set_drvdata(dev, dsi);
+        pm_runtime_enable(dev);
         return 0;
 
 err_mipi_dsi_host:
diff --git a/drivers/gpu/drm/ttm/ttm_page_alloc.c b/drivers/gpu/drm/ttm/ttm_page_alloc.c
index b0551aa677b8..8d7172e8381d 100644
--- a/drivers/gpu/drm/ttm/ttm_page_alloc.c
+++ b/drivers/gpu/drm/ttm/ttm_page_alloc.c
@@ -1062,7 +1062,6 @@ void ttm_pool_unpopulate(struct ttm_tt *ttm)
 }
 EXPORT_SYMBOL(ttm_pool_unpopulate);
 
-#if defined(CONFIG_SWIOTLB) || defined(CONFIG_INTEL_IOMMU)
 int ttm_populate_and_map_pages(struct device *dev, struct ttm_dma_tt *tt)
 {
         unsigned i, j;
@@ -1133,7 +1132,6 @@ void ttm_unmap_and_unpopulate_pages(struct device *dev, struct ttm_dma_tt *tt)
         ttm_pool_unpopulate(&tt->ttm);
 }
 EXPORT_SYMBOL(ttm_unmap_and_unpopulate_pages);
-#endif
 
 int ttm_page_alloc_debugfs(struct seq_file *m, void *data)
 {
diff --git a/include/drm/ttm/ttm_page_alloc.h b/include/drm/ttm/ttm_page_alloc.h
index 38a2b4770c35..593811362a91 100644
--- a/include/drm/ttm/ttm_page_alloc.h
+++ b/include/drm/ttm/ttm_page_alloc.h
@@ -59,11 +59,20 @@ int ttm_pool_populate(struct ttm_tt *ttm);
 void ttm_pool_unpopulate(struct ttm_tt *ttm);
 
 /**
+ * Populates and DMA maps pages to fullfil a ttm_dma_populate() request
+ */
+int ttm_populate_and_map_pages(struct device *dev, struct ttm_dma_tt *tt);
+
+/**
+ * Unpopulates and DMA unmaps pages as part of a
+ * ttm_dma_unpopulate() request */
+void ttm_unmap_and_unpopulate_pages(struct device *dev, struct ttm_dma_tt *tt);
+
+/**
  * Output the state of pools to debugfs file
  */
 int ttm_page_alloc_debugfs(struct seq_file *m, void *data);
 
-
 #if defined(CONFIG_SWIOTLB) || defined(CONFIG_INTEL_IOMMU)
 /**
  * Initialize pool allocator.
@@ -83,17 +92,6 @@ int ttm_dma_page_alloc_debugfs(struct seq_file *m, void *data);
 int ttm_dma_populate(struct ttm_dma_tt *ttm_dma, struct device *dev);
 void ttm_dma_unpopulate(struct ttm_dma_tt *ttm_dma, struct device *dev);
 
-
-/**
- * Populates and DMA maps pages to fullfil a ttm_dma_populate() request
- */
-int ttm_populate_and_map_pages(struct device *dev, struct ttm_dma_tt *tt);
-
-/**
- * Unpopulates and DMA unmaps pages as part of a
- * ttm_dma_unpopulate() request */
-void ttm_unmap_and_unpopulate_pages(struct device *dev, struct ttm_dma_tt *tt);
-
 #else
 static inline int ttm_dma_page_alloc_init(struct ttm_mem_global *glob,
                                           unsigned max_pages)
@@ -116,16 +114,6 @@ static inline void ttm_dma_unpopulate(struct ttm_dma_tt *ttm_dma,
                                       struct device *dev)
 {
 }
-
-static inline int ttm_populate_and_map_pages(struct device *dev, struct ttm_dma_tt *tt)
-{
-        return -ENOMEM;
-}
-
-static inline void ttm_unmap_and_unpopulate_pages(struct device *dev, struct ttm_dma_tt *tt)
-{
-}
-
 #endif
 
 #endif
diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h
index 731d0df722e3..6e80501368ae 100644
--- a/include/uapi/linux/kfd_ioctl.h
+++ b/include/uapi/linux/kfd_ioctl.h
@@ -233,29 +233,29 @@ struct kfd_ioctl_wait_events_args {
 };
 
 struct kfd_ioctl_set_scratch_backing_va_args {
-        uint64_t va_addr;       /* to KFD */
-        uint32_t gpu_id;        /* to KFD */
-        uint32_t pad;
+        __u64 va_addr;  /* to KFD */
+        __u32 gpu_id;   /* to KFD */
+        __u32 pad;
 };
 
 struct kfd_ioctl_get_tile_config_args {
         /* to KFD: pointer to tile array */
-        uint64_t tile_config_ptr;
+        __u64 tile_config_ptr;
         /* to KFD: pointer to macro tile array */
-        uint64_t macro_tile_config_ptr;
+        __u64 macro_tile_config_ptr;
         /* to KFD: array size allocated by user mode
          * from KFD: array size filled by kernel
          */
-        uint32_t num_tile_configs;
+        __u32 num_tile_configs;
         /* to KFD: array size allocated by user mode
          * from KFD: array size filled by kernel
          */
-        uint32_t num_macro_tile_configs;
+        __u32 num_macro_tile_configs;
 
-        uint32_t gpu_id;                /* to KFD */
-        uint32_t gb_addr_config;        /* from KFD */
-        uint32_t num_banks;             /* from KFD */
-        uint32_t num_ranks;             /* from KFD */
+        __u32 gpu_id;           /* to KFD */
+        __u32 gb_addr_config;   /* from KFD */
+        __u32 num_banks;                /* from KFD */
+        __u32 num_ranks;                /* from KFD */
         /* struct size can be extended later if needed
          * without breaking ABI compatibility
          */