Merge branch 'drm-fixes-4.15' of git://people.freedesktop.org/~agd5f/linux into drm-fixes

Fixes for 4.15.  Highlights:
- DC fixes for S3, gamma, audio, pageflipping, etc.
- fix a regression in radeon from kfd removal
- fix a ttm regression with swiotlb disabled
- misc other fixes

* 'drm-fixes-4.15' of git://people.freedesktop.org/~agd5f/linux: (36 commits)
  drm/radeon: remove init of CIK VMIDs 8-16 for amdkfd
  drm/ttm: fix populate_and_map() functions once more
  drm/amd/display: USB-C / thunderbolt dock specific workaround
  drm/amd/display: Switch to drm_atomic_helper_wait_for_flip_done
  drm/amd/display: fix gamma setting
  drm/amd/display: Do not put drm_atomic_state on resume
  drm/amd/display: Fix couple more inconsistent NULL checks in dc_resource
  drm/amd/display: Fix potential NULL and mem leak in create_links
  drm/amd/display: Fix hubp check in set_cursor_position
  drm/amd/display: Fix use before NULL check in validate_timing
  drm/amd/display: Bunch of smatch error and warning fixes in DC
  drm/amd/display: Fix amdgpu_dm bugs found by smatch
  drm/amd/display: try to find matching audio inst for enc inst first
  drm/amd/display: fix seq issue: turn on clock before programming afmt.
  drm/amd/display: fix memory leaks on error exit return
  drm/amd/display: check plane state before validating fbc
  drm/amd/display: Do DC mode-change check when adding CRTCs
  drm/amd/display: Revert noisy assert messages
  drm/amd/display: fix split viewport rounding error
  drm/amd/display: Check aux channel before MST resume
  ...

30 files changed, 404 insertions, 230 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 5afaf6016b4a..0b14b5373783 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -717,7 +717,7 @@ int amdgpu_queue_mgr_fini(struct amdgpu_device *adev,
                           struct amdgpu_queue_mgr *mgr);
 int amdgpu_queue_mgr_map(struct amdgpu_device *adev,
                          struct amdgpu_queue_mgr *mgr,
-                         int hw_ip, int instance, int ring,
+                         u32 hw_ip, u32 instance, u32 ring,
                          struct amdgpu_ring **out_ring);
 
 /*
@@ -1572,18 +1572,14 @@ struct amdgpu_device {
         /* sdma */
         struct amdgpu_sdma              sdma;
 
-        union {
-                struct {
-                        /* uvd */
-                        struct amdgpu_uvd               uvd;
+        /* uvd */
+        struct amdgpu_uvd               uvd;
 
-                        /* vce */
-                        struct amdgpu_vce               vce;
-                };
+        /* vce */
+        struct amdgpu_vce               vce;
 
-                /* vcn */
-                struct amdgpu_vcn               vcn;
-        };
+        /* vcn */
+        struct amdgpu_vcn               vcn;
 
         /* firmwares */
         struct amdgpu_firmware          firmware;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index a57cec737c18..57abf7abd7a9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -409,6 +409,10 @@ static bool amdgpu_cs_try_evict(struct amdgpu_cs_parser *p,
                 if (candidate->robj == validated)
                         break;
 
+                /* We can't move pinned BOs here */
+                if (bo->pin_count)
+                        continue;
+
                 other = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
 
                 /* Check if this BO is in one of the domains we need space for */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 2c574374d9b6..3573ecdb06ee 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1837,9 +1837,6 @@ static int amdgpu_fini(struct amdgpu_device *adev)
                 adev->ip_blocks[i].status.hw = false;
         }
 
-        if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU)
-                amdgpu_ucode_fini_bo(adev);
-
         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
                 if (!adev->ip_blocks[i].status.sw)
                         continue;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index ec96bb1f9eaf..c2f414ffb2cc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -536,7 +536,7 @@ static const struct pci_device_id pciidlist[] = {
         {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
         {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
         /* Raven */
-        {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU|AMD_EXP_HW_SUPPORT},
+        {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU},
 
         {0, 0, 0}
 };
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
index 033fba2def6f..5f5aa5fddc16 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
@@ -164,6 +164,9 @@ static int amdgpu_pp_hw_fini(void *handle)
                 ret = adev->powerplay.ip_funcs->hw_fini(
                                         adev->powerplay.pp_handle);
 
+        if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU)
+                amdgpu_ucode_fini_bo(adev);
+
         return ret;
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 7714f4a6c8b0..447d446b5015 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -442,6 +442,8 @@ static int psp_hw_fini(void *handle)
         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
                 return 0;
 
+        amdgpu_ucode_fini_bo(adev);
+
         psp_ring_destroy(psp, PSP_RING_TYPE__KM);
 
         amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c
index 190e28cb827e..93d86619e802 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c
@@ -63,7 +63,7 @@ static int amdgpu_update_cached_map(struct amdgpu_queue_mapper *mapper,
 
 static int amdgpu_identity_map(struct amdgpu_device *adev,
                                struct amdgpu_queue_mapper *mapper,
-                               int ring,
+                               u32 ring,
                                struct amdgpu_ring **out_ring)
 {
         switch (mapper->hw_ip) {
@@ -121,7 +121,7 @@ static enum amdgpu_ring_type amdgpu_hw_ip_to_ring_type(int hw_ip)
 
 static int amdgpu_lru_map(struct amdgpu_device *adev,
                           struct amdgpu_queue_mapper *mapper,
-                          int user_ring, bool lru_pipe_order,
+                          u32 user_ring, bool lru_pipe_order,
                           struct amdgpu_ring **out_ring)
 {
         int r, i, j;
@@ -208,7 +208,7 @@ int amdgpu_queue_mgr_fini(struct amdgpu_device *adev,
  */
 int amdgpu_queue_mgr_map(struct amdgpu_device *adev,
                          struct amdgpu_queue_mgr *mgr,
-                         int hw_ip, int instance, int ring,
+                         u32 hw_ip, u32 instance, u32 ring,
                          struct amdgpu_ring **out_ring)
 {
         int r, ip_num_rings;
diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
index 793b1470284d..a296f7bbe57c 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
@@ -1023,22 +1023,101 @@ static const struct amdgpu_allowed_register_entry cik_allowed_read_registers[] =
         {mmPA_SC_RASTER_CONFIG_1, true},
 };
 
-static uint32_t cik_read_indexed_register(struct amdgpu_device *adev,
-                                          u32 se_num, u32 sh_num,
-                                          u32 reg_offset)
+
+static uint32_t cik_get_register_value(struct amdgpu_device *adev,
+                                       bool indexed, u32 se_num,
+                                       u32 sh_num, u32 reg_offset)
 {
-        uint32_t val;
+        if (indexed) {
+                uint32_t val;
+                unsigned se_idx = (se_num == 0xffffffff) ? 0 : se_num;
+                unsigned sh_idx = (sh_num == 0xffffffff) ? 0 : sh_num;
+
+                switch (reg_offset) {
+                case mmCC_RB_BACKEND_DISABLE:
+                        return adev->gfx.config.rb_config[se_idx][sh_idx].rb_backend_disable;
+                case mmGC_USER_RB_BACKEND_DISABLE:
+                        return adev->gfx.config.rb_config[se_idx][sh_idx].user_rb_backend_disable;
+                case mmPA_SC_RASTER_CONFIG:
+                        return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config;
+                case mmPA_SC_RASTER_CONFIG_1:
+                        return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config_1;
+                }
 
-        mutex_lock(&adev->grbm_idx_mutex);
-        if (se_num != 0xffffffff || sh_num != 0xffffffff)
-                amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
+                mutex_lock(&adev->grbm_idx_mutex);
+                if (se_num != 0xffffffff || sh_num != 0xffffffff)
+                        amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
 
-        val = RREG32(reg_offset);
+                val = RREG32(reg_offset);
 
-        if (se_num != 0xffffffff || sh_num != 0xffffffff)
-                amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
-        mutex_unlock(&adev->grbm_idx_mutex);
-        return val;
+                if (se_num != 0xffffffff || sh_num != 0xffffffff)
+                        amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
+                mutex_unlock(&adev->grbm_idx_mutex);
+                return val;
+        } else {
+                unsigned idx;
+
+                switch (reg_offset) {
+                case mmGB_ADDR_CONFIG:
+                        return adev->gfx.config.gb_addr_config;
+                case mmMC_ARB_RAMCFG:
+                        return adev->gfx.config.mc_arb_ramcfg;
+                case mmGB_TILE_MODE0:
+                case mmGB_TILE_MODE1:
+                case mmGB_TILE_MODE2:
+                case mmGB_TILE_MODE3:
+                case mmGB_TILE_MODE4:
+                case mmGB_TILE_MODE5:
+                case mmGB_TILE_MODE6:
+                case mmGB_TILE_MODE7:
+                case mmGB_TILE_MODE8:
+                case mmGB_TILE_MODE9:
+                case mmGB_TILE_MODE10:
+                case mmGB_TILE_MODE11:
+                case mmGB_TILE_MODE12:
+                case mmGB_TILE_MODE13:
+                case mmGB_TILE_MODE14:
+                case mmGB_TILE_MODE15:
+                case mmGB_TILE_MODE16:
+                case mmGB_TILE_MODE17:
+                case mmGB_TILE_MODE18:
+                case mmGB_TILE_MODE19:
+                case mmGB_TILE_MODE20:
+                case mmGB_TILE_MODE21:
+                case mmGB_TILE_MODE22:
+                case mmGB_TILE_MODE23:
+                case mmGB_TILE_MODE24:
+                case mmGB_TILE_MODE25:
+                case mmGB_TILE_MODE26:
+                case mmGB_TILE_MODE27:
+                case mmGB_TILE_MODE28:
+                case mmGB_TILE_MODE29:
+                case mmGB_TILE_MODE30:
+                case mmGB_TILE_MODE31:
+                        idx = (reg_offset - mmGB_TILE_MODE0);
+                        return adev->gfx.config.tile_mode_array[idx];
+                case mmGB_MACROTILE_MODE0:
+                case mmGB_MACROTILE_MODE1:
+                case mmGB_MACROTILE_MODE2:
+                case mmGB_MACROTILE_MODE3:
+                case mmGB_MACROTILE_MODE4:
+                case mmGB_MACROTILE_MODE5:
+                case mmGB_MACROTILE_MODE6:
+                case mmGB_MACROTILE_MODE7:
+                case mmGB_MACROTILE_MODE8:
+                case mmGB_MACROTILE_MODE9:
+                case mmGB_MACROTILE_MODE10:
+                case mmGB_MACROTILE_MODE11:
+                case mmGB_MACROTILE_MODE12:
+                case mmGB_MACROTILE_MODE13:
+                case mmGB_MACROTILE_MODE14:
+                case mmGB_MACROTILE_MODE15:
+                        idx = (reg_offset - mmGB_MACROTILE_MODE0);
+                        return adev->gfx.config.macrotile_mode_array[idx];
+                default:
+                        return RREG32(reg_offset);
+                }
+        }
 }
 
 static int cik_read_register(struct amdgpu_device *adev, u32 se_num,
@@ -1048,13 +1127,13 @@ static int cik_read_register(struct amdgpu_device *adev, u32 se_num,
 
         *value = 0;
         for (i = 0; i < ARRAY_SIZE(cik_allowed_read_registers); i++) {
+                bool indexed = cik_allowed_read_registers[i].grbm_indexed;
+
                 if (reg_offset != cik_allowed_read_registers[i].reg_offset)
                         continue;
 
-                *value = cik_allowed_read_registers[i].grbm_indexed ?
-                         cik_read_indexed_register(adev, se_num,
-                                                   sh_num, reg_offset) :
-                         RREG32(reg_offset);
+                *value = cik_get_register_value(adev, indexed, se_num, sh_num,
+                                                reg_offset);
                 return 0;
         }
         return -EINVAL;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index 5c8a7a48a4ad..419ba0ce7ee5 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -1819,6 +1819,22 @@ static void gfx_v7_0_setup_rb(struct amdgpu_device *adev)
                                                         adev->gfx.config.backend_enable_mask,
                                                         num_rb_pipes);
         }
+
+        /* cache the values for userspace */
+        for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
+                for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
+                        gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff);
+                        adev->gfx.config.rb_config[i][j].rb_backend_disable =
+                                RREG32(mmCC_RB_BACKEND_DISABLE);
+                        adev->gfx.config.rb_config[i][j].user_rb_backend_disable =
+                                RREG32(mmGC_USER_RB_BACKEND_DISABLE);
+                        adev->gfx.config.rb_config[i][j].raster_config =
+                                RREG32(mmPA_SC_RASTER_CONFIG);
+                        adev->gfx.config.rb_config[i][j].raster_config_1 =
+                                RREG32(mmPA_SC_RASTER_CONFIG_1);
+                }
+        }
+        gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
         mutex_unlock(&adev->grbm_idx_mutex);
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 1eb4d79d6e30..0450ac5ba6b6 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -1175,7 +1175,7 @@ static const struct amdgpu_irq_src_funcs vcn_v1_0_irq_funcs = {
 
 static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev)
 {
-        adev->uvd.irq.num_types = adev->vcn.num_enc_rings + 1;
+        adev->vcn.irq.num_types = adev->vcn.num_enc_rings + 1;
         adev->vcn.irq.funcs = &vcn_v1_0_irq_funcs;
 }
 
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 889ed24084e8..f71fe6d2ddda 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -520,7 +520,8 @@ static int detect_mst_link_for_all_connectors(struct drm_device *dev)
 
         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
                 aconnector = to_amdgpu_dm_connector(connector);
-                if (aconnector->dc_link->type == dc_connection_mst_branch) {
+                if (aconnector->dc_link->type == dc_connection_mst_branch &&
+                    aconnector->mst_mgr.aux) {
                         DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
                                         aconnector, aconnector->base.base.id);
 
@@ -677,6 +678,10 @@ int amdgpu_dm_display_resume(struct amdgpu_device *adev)
 
                 mutex_lock(&aconnector->hpd_lock);
                 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
+
+                if (aconnector->fake_enable && aconnector->dc_link->local_sink)
+                        aconnector->fake_enable = false;
+
                 aconnector->dc_sink = NULL;
                 amdgpu_dm_update_connector_after_detect(aconnector);
                 mutex_unlock(&aconnector->hpd_lock);
@@ -711,7 +716,6 @@ int amdgpu_dm_display_resume(struct amdgpu_device *adev)
 
         ret = drm_atomic_helper_resume(ddev, adev->dm.cached_state);
 
-        drm_atomic_state_put(adev->dm.cached_state);
         adev->dm.cached_state = NULL;
 
         amdgpu_dm_irq_resume_late(adev);
@@ -2704,7 +2708,7 @@ static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
                         .link = aconnector->dc_link,
                         .sink_signal = SIGNAL_TYPE_VIRTUAL
         };
-        struct edid *edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
+        struct edid *edid;
 
         if (!aconnector->base.edid_blob_ptr ||
                 !aconnector->base.edid_blob_ptr->data) {
@@ -2716,6 +2720,8 @@ static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
                 return;
         }
 
+        edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
+
         aconnector->edid = edid;
 
         aconnector->dc_em_sink = dc_link_add_remote_sink(
@@ -4193,13 +4199,13 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
                 update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
                                 dm_new_con_state, (struct dc_stream_state *)dm_new_crtc_state->stream);
 
+                if (!dm_new_crtc_state->stream)
+                        continue;
+
                 status = dc_stream_get_status(dm_new_crtc_state->stream);
                 WARN_ON(!status);
                 WARN_ON(!status->plane_count);
 
-                if (!dm_new_crtc_state->stream)
-                        continue;
-
                 /*TODO How it works with MPO ?*/
                 if (!dc_commit_planes_to_stream(
                                 dm->dc,
@@ -4253,7 +4259,7 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
         drm_atomic_helper_commit_hw_done(state);
 
         if (wait_for_vblank)
-                drm_atomic_helper_wait_for_vblanks(dev, state);
+                drm_atomic_helper_wait_for_flip_done(dev, state);
 
         drm_atomic_helper_cleanup_planes(dev, state);
 }
@@ -4332,9 +4338,11 @@ void dm_restore_drm_connector_state(struct drm_device *dev,
                 return;
 
         disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
-        acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
+        if (!disconnected_acrtc)
+                return;
 
-        if (!disconnected_acrtc || !acrtc_state->stream)
+        acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
+        if (!acrtc_state->stream)
                 return;
 
         /*
@@ -4455,7 +4463,7 @@ static int dm_update_crtcs_state(struct dc *dc,
                         }
                 }
 
-                if (dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
+                if (enable && dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
                                 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
 
                         new_crtc_state->mode_changed = false;
@@ -4709,7 +4717,8 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
                 }
         } else {
                 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
-                        if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
+                        if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
+                                        !new_crtc_state->color_mgmt_changed)
                                 continue;
 
                         if (!new_crtc_state->enable)
diff --git a/drivers/gpu/drm/amd/display/dc/basics/log_helpers.c b/drivers/gpu/drm/amd/display/dc/basics/log_helpers.c
index 785b943b60ed..6e43168fbdd6 100644
--- a/drivers/gpu/drm/amd/display/dc/basics/log_helpers.c
+++ b/drivers/gpu/drm/amd/display/dc/basics/log_helpers.c
@@ -75,6 +75,9 @@ void dc_conn_log(struct dc_context *ctx,
                 if (signal == signal_type_info_tbl[i].type)
                         break;
 
+        if (i == NUM_ELEMENTS(signal_type_info_tbl))
+                goto fail;
+
         dm_logger_append(&entry, "[%s][ConnIdx:%d] ",
                         signal_type_info_tbl[i].name,
                         link->link_index);
@@ -96,6 +99,8 @@ void dc_conn_log(struct dc_context *ctx,
 
         dm_logger_append(&entry, "^\n");
         dm_helpers_dc_conn_log(ctx, &entry, event);
+
+fail:
         dm_logger_close(&entry);
 
         va_end(args);
diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
index aaaebd06d7ee..86e6438c5cf3 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
@@ -249,7 +249,7 @@ static enum bp_result bios_parser_get_dst_obj(struct dc_bios *dcb,
         struct graphics_object_id *dest_object_id)
 {
         uint32_t number;
-        uint16_t *id;
+        uint16_t *id = NULL;
         ATOM_OBJECT *object;
         struct bios_parser *bp = BP_FROM_DCB(dcb);
 
@@ -260,7 +260,7 @@ static enum bp_result bios_parser_get_dst_obj(struct dc_bios *dcb,
 
         number = get_dest_obj_list(bp, object, &id);
 
-        if (number <= index)
+        if (number <= index || !id)
                 return BP_RESULT_BADINPUT;
 
         *dest_object_id = object_id_from_bios_object_id(id[index]);
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index fe63f5894d43..7240db2e6f09 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -121,6 +121,10 @@ static bool create_links(
                         goto failed_alloc;
                 }
 
+                link->link_index = dc->link_count;
+                dc->links[dc->link_count] = link;
+                dc->link_count++;
+
                 link->ctx = dc->ctx;
                 link->dc = dc;
                 link->connector_signal = SIGNAL_TYPE_VIRTUAL;
@@ -129,6 +133,13 @@ static bool create_links(
                 link->link_id.enum_id = ENUM_ID_1;
                 link->link_enc = kzalloc(sizeof(*link->link_enc), GFP_KERNEL);
 
+                if (!link->link_enc) {
+                        BREAK_TO_DEBUGGER();
+                        goto failed_alloc;
+                }
+
+                link->link_status.dpcd_caps = &link->dpcd_caps;
+
                 enc_init.ctx = dc->ctx;
                 enc_init.channel = CHANNEL_ID_UNKNOWN;
                 enc_init.hpd_source = HPD_SOURCEID_UNKNOWN;
@@ -138,10 +149,6 @@ static bool create_links(
                 enc_init.encoder.id = ENCODER_ID_INTERNAL_VIRTUAL;
                 enc_init.encoder.enum_id = ENUM_ID_1;
                 virtual_link_encoder_construct(link->link_enc, &enc_init);
-
-                link->link_index = dc->link_count;
-                dc->links[dc->link_count] = link;
-                dc->link_count++;
         }
 
         return true;
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 0602610489d7..e27ed4a45265 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -480,22 +480,6 @@ static void detect_dp(
                 sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
                 detect_dp_sink_caps(link);
 
-                /* DP active dongles */
-                if (is_dp_active_dongle(link)) {
-                        link->type = dc_connection_active_dongle;
-                        if (!link->dpcd_caps.sink_count.bits.SINK_COUNT) {
-                                /*
-                                 * active dongle unplug processing for short irq
-                                 */
-                                link_disconnect_sink(link);
-                                return;
-                        }
-
-                        if (link->dpcd_caps.dongle_type !=
-                        DISPLAY_DONGLE_DP_HDMI_CONVERTER) {
-                                *converter_disable_audio = true;
-                        }
-                }
                 if (is_mst_supported(link)) {
                         sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
                         link->type = dc_connection_mst_branch;
@@ -535,6 +519,22 @@ static void detect_dp(
                                 sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
                         }
                 }
+
+                if (link->type != dc_connection_mst_branch &&
+                        is_dp_active_dongle(link)) {
+                        /* DP active dongles */
+                        link->type = dc_connection_active_dongle;
+                        if (!link->dpcd_caps.sink_count.bits.SINK_COUNT) {
+                                /*
+                                 * active dongle unplug processing for short irq
+                                 */
+                                link_disconnect_sink(link);
+                                return;
+                        }
+
+                        if (link->dpcd_caps.dongle_type != DISPLAY_DONGLE_DP_HDMI_CONVERTER)
+                                *converter_disable_audio = true;
+                }
         } else {
                 /* DP passive dongles */
                 sink_caps->signal = dp_passive_dongle_detection(link->ddc,
@@ -1801,12 +1801,75 @@ static void disable_link(struct dc_link *link, enum signal_type signal)
                 link->link_enc->funcs->disable_output(link->link_enc, signal, link);
 }
 
+bool dp_active_dongle_validate_timing(
+                const struct dc_crtc_timing *timing,
+                const struct dc_dongle_caps *dongle_caps)
+{
+        unsigned int required_pix_clk = timing->pix_clk_khz;
+
+        if (dongle_caps->dongle_type != DISPLAY_DONGLE_DP_HDMI_CONVERTER ||
+                dongle_caps->extendedCapValid == false)
+                return true;
+
+        /* Check Pixel Encoding */
+        switch (timing->pixel_encoding) {
+        case PIXEL_ENCODING_RGB:
+        case PIXEL_ENCODING_YCBCR444:
+                break;
+        case PIXEL_ENCODING_YCBCR422:
+                if (!dongle_caps->is_dp_hdmi_ycbcr422_pass_through)
+                        return false;
+                break;
+        case PIXEL_ENCODING_YCBCR420:
+                if (!dongle_caps->is_dp_hdmi_ycbcr420_pass_through)
+                        return false;
+                break;
+        default:
+                /* Invalid Pixel Encoding*/
+                return false;
+        }
+
+
+        /* Check Color Depth and Pixel Clock */
+        if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
+                required_pix_clk /= 2;
+
+        switch (timing->display_color_depth) {
+        case COLOR_DEPTH_666:
+        case COLOR_DEPTH_888:
+                /*888 and 666 should always be supported*/
+                break;
+        case COLOR_DEPTH_101010:
+                if (dongle_caps->dp_hdmi_max_bpc < 10)
+                        return false;
+                required_pix_clk = required_pix_clk * 10 / 8;
+                break;
+        case COLOR_DEPTH_121212:
+                if (dongle_caps->dp_hdmi_max_bpc < 12)
+                        return false;
+                required_pix_clk = required_pix_clk * 12 / 8;
+                break;
+
+        case COLOR_DEPTH_141414:
+        case COLOR_DEPTH_161616:
+        default:
+                /* These color depths are currently not supported */
+                return false;
+        }
+
+        if (required_pix_clk > dongle_caps->dp_hdmi_max_pixel_clk)
+                return false;
+
+        return true;
+}
+
 enum dc_status dc_link_validate_mode_timing(
                 const struct dc_stream_state *stream,
                 struct dc_link *link,
                 const struct dc_crtc_timing *timing)
 {
         uint32_t max_pix_clk = stream->sink->dongle_max_pix_clk;
+        struct dc_dongle_caps *dongle_caps = &link->link_status.dpcd_caps->dongle_caps;
 
         /* A hack to avoid failing any modes for EDID override feature on
          * topology change such as lower quality cable for DP or different dongle
@@ -1814,8 +1877,13 @@ enum dc_status dc_link_validate_mode_timing(
         if (link->remote_sinks[0])
                 return DC_OK;
 
+        /* Passive Dongle */
         if (0 != max_pix_clk && timing->pix_clk_khz > max_pix_clk)
-                return DC_EXCEED_DONGLE_MAX_CLK;
+                return DC_EXCEED_DONGLE_CAP;
+
+        /* Active Dongle*/
+        if (!dp_active_dongle_validate_timing(timing, dongle_caps))
+                return DC_EXCEED_DONGLE_CAP;
 
         switch (stream->signal) {
         case SIGNAL_TYPE_EDP:
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index ced42484dcfc..e6bf05d76a94 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -1512,7 +1512,7 @@ static bool hpd_rx_irq_check_link_loss_status(
         struct dc_link *link,
         union hpd_irq_data *hpd_irq_dpcd_data)
 {
-        uint8_t irq_reg_rx_power_state;
+        uint8_t irq_reg_rx_power_state = 0;
         enum dc_status dpcd_result = DC_ERROR_UNEXPECTED;
         union lane_status lane_status;
         uint32_t lane;
@@ -1524,60 +1524,55 @@ static bool hpd_rx_irq_check_link_loss_status(
 
         if (link->cur_link_settings.lane_count == 0)
                 return return_code;
-        /*1. Check that we can handle interrupt: Not in FS DOS,
-         *  Not in "Display Timeout" state, Link is trained.
-         */
 
-        dpcd_result = core_link_read_dpcd(link,
-                DP_SET_POWER,
-                &irq_reg_rx_power_state,
-                sizeof(irq_reg_rx_power_state));
+        /*1. Check that Link Status changed, before re-training.*/
 
-        if (dpcd_result != DC_OK) {
-                irq_reg_rx_power_state = DP_SET_POWER_D0;
-                dm_logger_write(link->ctx->logger, LOG_HW_HPD_IRQ,
-                        "%s: DPCD read failed to obtain power state.\n",
-                        __func__);
+        /*parse lane status*/
+        for (lane = 0; lane < link->cur_link_settings.lane_count; lane++) {
+                /* check status of lanes 0,1
+                 * changed DpcdAddress_Lane01Status (0x202)
+                 */
+                lane_status.raw = get_nibble_at_index(
+                        &hpd_irq_dpcd_data->bytes.lane01_status.raw,
+                        lane);
+
+                if (!lane_status.bits.CHANNEL_EQ_DONE_0 ||
+                        !lane_status.bits.CR_DONE_0 ||
+                        !lane_status.bits.SYMBOL_LOCKED_0) {
+                        /* if one of the channel equalization, clock
+                         * recovery or symbol lock is dropped
+                         * consider it as (link has been
+                         * dropped) dp sink status has changed
+                         */
+                        sink_status_changed = true;
+                        break;
+                }
         }
 
-        if (irq_reg_rx_power_state == DP_SET_POWER_D0) {
-
-                /*2. Check that Link Status changed, before re-training.*/
-
-                /*parse lane status*/
-                for (lane = 0;
-                        lane < link->cur_link_settings.lane_count;
-                        lane++) {
+        /* Check interlane align.*/
+        if (sink_status_changed ||
+                !hpd_irq_dpcd_data->bytes.lane_status_updated.bits.INTERLANE_ALIGN_DONE) {
 
-                        /* check status of lanes 0,1
-                         * changed DpcdAddress_Lane01Status (0x202)*/
-                        lane_status.raw = get_nibble_at_index(
-                                &hpd_irq_dpcd_data->bytes.lane01_status.raw,
-                                lane);
-
-                        if (!lane_status.bits.CHANNEL_EQ_DONE_0 ||
-                                !lane_status.bits.CR_DONE_0 ||
-                                !lane_status.bits.SYMBOL_LOCKED_0) {
-                                /* if one of the channel equalization, clock
-                                 * recovery or symbol lock is dropped
-                                 * consider it as (link has been
-                                 * dropped) dp sink status has changed*/
-                                sink_status_changed = true;
-                                break;
-                        }
+                dm_logger_write(link->ctx->logger, LOG_HW_HPD_IRQ,
+                        "%s: Link Status changed.\n", __func__);
 
-                }
+                return_code = true;
 
-                /* Check interlane align.*/
-                if (sink_status_changed ||
-                        !hpd_irq_dpcd_data->bytes.lane_status_updated.bits.
-                        INTERLANE_ALIGN_DONE) {
+                /*2. Check that we can handle interrupt: Not in FS DOS,
+                 *  Not in "Display Timeout" state, Link is trained.
+                 */
+                dpcd_result = core_link_read_dpcd(link,
+                        DP_SET_POWER,
+                        &irq_reg_rx_power_state,
+                        sizeof(irq_reg_rx_power_state));
 
+                if (dpcd_result != DC_OK) {
                         dm_logger_write(link->ctx->logger, LOG_HW_HPD_IRQ,
-                                "%s: Link Status changed.\n",
+                                "%s: DPCD read failed to obtain power state.\n",
                                 __func__);
-
-                        return_code = true;
+                } else {
+                        if (irq_reg_rx_power_state != DP_SET_POWER_D0)
+                                return_code = false;
                 }
         }
 
@@ -2062,6 +2057,24 @@ bool is_dp_active_dongle(const struct dc_link *link)
                         (dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER);
 }
 
+static int translate_dpcd_max_bpc(enum dpcd_downstream_port_max_bpc bpc)
+{
+        switch (bpc) {
+        case DOWN_STREAM_MAX_8BPC:
+                return 8;
+        case DOWN_STREAM_MAX_10BPC:
+                return 10;
+        case DOWN_STREAM_MAX_12BPC:
+                return 12;
+        case DOWN_STREAM_MAX_16BPC:
+                return 16;
+        default:
+                break;
+        }
+
+        return -1;
+}
+
 static void get_active_converter_info(
         uint8_t data, struct dc_link *link)
 {
@@ -2131,7 +2144,8 @@ static void get_active_converter_info(
                                         hdmi_caps.bits.YCrCr420_CONVERSION;
 
                                 link->dpcd_caps.dongle_caps.dp_hdmi_max_bpc =
-                                        hdmi_color_caps.bits.MAX_BITS_PER_COLOR_COMPONENT;
+                                        translate_dpcd_max_bpc(
+                                                hdmi_color_caps.bits.MAX_BITS_PER_COLOR_COMPONENT);
 
                                 link->dpcd_caps.dongle_caps.extendedCapValid = true;
                         }
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index d1cdf9f8853d..b7422d3b71ef 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -516,13 +516,11 @@ static void calculate_viewport(struct pipe_ctx *pipe_ctx)
                         right_view = (plane_state->rotation == ROTATION_ANGLE_270) != sec_split;
 
                 if (right_view) {
-                        data->viewport.width /= 2;
-                        data->viewport_c.width /= 2;
-                        data->viewport.x +=  data->viewport.width;
-                        data->viewport_c.x +=  data->viewport_c.width;
+                        data->viewport.x +=  data->viewport.width / 2;
+                        data->viewport_c.x +=  data->viewport_c.width / 2;
                         /* Ceil offset pipe */
-                        data->viewport.width += data->viewport.width % 2;
-                        data->viewport_c.width += data->viewport_c.width % 2;
+                        data->viewport.width = (data->viewport.width + 1) / 2;
+                        data->viewport_c.width = (data->viewport_c.width + 1) / 2;
                 } else {
                         data->viewport.width /= 2;
                         data->viewport_c.width /= 2;
@@ -580,14 +578,12 @@ static void calculate_recout(struct pipe_ctx *pipe_ctx, struct view *recout_skip
         if (pipe_ctx->top_pipe && pipe_ctx->top_pipe->plane_state ==
                 pipe_ctx->plane_state) {
                 if (stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) {
-                        pipe_ctx->plane_res.scl_data.recout.height /= 2;
-                        pipe_ctx->plane_res.scl_data.recout.y += pipe_ctx->plane_res.scl_data.recout.height;
+                        pipe_ctx->plane_res.scl_data.recout.y += pipe_ctx->plane_res.scl_data.recout.height / 2;
                         /* Floor primary pipe, ceil 2ndary pipe */
-                        pipe_ctx->plane_res.scl_data.recout.height += pipe_ctx->plane_res.scl_data.recout.height % 2;
+                        pipe_ctx->plane_res.scl_data.recout.height = (pipe_ctx->plane_res.scl_data.recout.height + 1) / 2;
                 } else {
-                        pipe_ctx->plane_res.scl_data.recout.width /= 2;
-                        pipe_ctx->plane_res.scl_data.recout.x += pipe_ctx->plane_res.scl_data.recout.width;
-                        pipe_ctx->plane_res.scl_data.recout.width += pipe_ctx->plane_res.scl_data.recout.width % 2;
+                        pipe_ctx->plane_res.scl_data.recout.x += pipe_ctx->plane_res.scl_data.recout.width / 2;
+                        pipe_ctx->plane_res.scl_data.recout.width = (pipe_ctx->plane_res.scl_data.recout.width + 1) / 2;
                 }
         } else if (pipe_ctx->bottom_pipe &&
                         pipe_ctx->bottom_pipe->plane_state == pipe_ctx->plane_state) {
@@ -856,6 +852,7 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
         pipe_ctx->plane_res.scl_data.h_active = timing->h_addressable + timing->h_border_left + timing->h_border_right;
         pipe_ctx->plane_res.scl_data.v_active = timing->v_addressable + timing->v_border_top + timing->v_border_bottom;
 
+
         /* Taps calculations */
         if (pipe_ctx->plane_res.xfm != NULL)
                 res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(
@@ -864,16 +861,21 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
         if (pipe_ctx->plane_res.dpp != NULL)
                 res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(
                                 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
-
         if (!res) {
                 /* Try 24 bpp linebuffer */
                 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_24BPP;
 
-                res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(
-                        pipe_ctx->plane_res.xfm, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
+                if (pipe_ctx->plane_res.xfm != NULL)
+                        res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(
+                                        pipe_ctx->plane_res.xfm,
+                                        &pipe_ctx->plane_res.scl_data,
+                                        &plane_state->scaling_quality);
 
-                res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(
-                        pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
+                if (pipe_ctx->plane_res.dpp != NULL)
+                        res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(
+                                        pipe_ctx->plane_res.dpp,
+                                        &pipe_ctx->plane_res.scl_data,
+                                        &plane_state->scaling_quality);
         }
 
         if (res)
@@ -991,8 +993,10 @@ static struct pipe_ctx *acquire_free_pipe_for_stream(
 
         head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream);
 
-        if (!head_pipe)
+        if (!head_pipe) {
                 ASSERT(0);
+                return NULL;
+        }
 
         if (!head_pipe->plane_state)
                 return head_pipe;
@@ -1447,11 +1451,16 @@ static struct stream_encoder *find_first_free_match_stream_enc_for_link(
 
 static struct audio *find_first_free_audio(
                 struct resource_context *res_ctx,
-                const struct resource_pool *pool)
+                const struct resource_pool *pool,
+                enum engine_id id)
 {
         int i;
         for (i = 0; i < pool->audio_count; i++) {
                 if ((res_ctx->is_audio_acquired[i] == false) && (res_ctx->is_stream_enc_acquired[i] == true)) {
+                        /*we have enough audio endpoint, find the matching inst*/
+                        if (id != i)
+                                continue;
+
                         return pool->audios[i];
                 }
         }
@@ -1700,7 +1709,7 @@ enum dc_status resource_map_pool_resources(
             dc_is_audio_capable_signal(pipe_ctx->stream->signal) &&
             stream->audio_info.mode_count) {
                 pipe_ctx->stream_res.audio = find_first_free_audio(
-                &context->res_ctx, pool);
+                &context->res_ctx, pool, pipe_ctx->stream_res.stream_enc->id);
 
                 /*
                  * Audio assigned in order first come first get.
@@ -1765,13 +1774,16 @@ enum dc_status dc_validate_global_state(
         enum dc_status result = DC_ERROR_UNEXPECTED;
         int i, j;
 
+        if (!new_ctx)
+                return DC_ERROR_UNEXPECTED;
+
         if (dc->res_pool->funcs->validate_global) {
                         result = dc->res_pool->funcs->validate_global(dc, new_ctx);
                         if (result != DC_OK)
                                 return result;
         }
 
-        for (i = 0; new_ctx && i < new_ctx->stream_count; i++) {
+        for (i = 0; i < new_ctx->stream_count; i++) {
                 struct dc_stream_state *stream = new_ctx->streams[i];
 
                 for (j = 0; j < dc->res_pool->pipe_count; j++) {
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index b00a6040a697..e230cc44a0a7 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
@@ -263,7 +263,6 @@ bool dc_stream_set_cursor_position(
                 struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;
                 struct mem_input *mi = pipe_ctx->plane_res.mi;
                 struct hubp *hubp = pipe_ctx->plane_res.hubp;
-                struct transform *xfm = pipe_ctx->plane_res.xfm;
                 struct dpp *dpp = pipe_ctx->plane_res.dpp;
                 struct dc_cursor_position pos_cpy = *position;
                 struct dc_cursor_mi_param param = {
@@ -294,11 +293,11 @@ bool dc_stream_set_cursor_position(
                 if (mi != NULL && mi->funcs->set_cursor_position != NULL)
                         mi->funcs->set_cursor_position(mi, &pos_cpy, &param);
 
-                if (hubp != NULL && hubp->funcs->set_cursor_position != NULL)
-                        hubp->funcs->set_cursor_position(hubp, &pos_cpy, &param);
+                if (!hubp)
+                        continue;
 
-                if (xfm != NULL && xfm->funcs->set_cursor_position != NULL)
-                        xfm->funcs->set_cursor_position(xfm, &pos_cpy, &param, hubp->curs_attr.width);
+                if (hubp->funcs->set_cursor_position != NULL)
+                        hubp->funcs->set_cursor_position(hubp, &pos_cpy, &param);
 
                 if (dpp != NULL && dpp->funcs->set_cursor_position != NULL)
                         dpp->funcs->set_cursor_position(dpp, &pos_cpy, &param, hubp->curs_attr.width);
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
index 81c40f8864db..0df9ecb2710c 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
@@ -352,11 +352,11 @@ void dce_aud_az_enable(struct audio *audio)
         uint32_t value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
 
         set_reg_field_value(value, 1,
-                        AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
-                        CLOCK_GATING_DISABLE);
-                set_reg_field_value(value, 1,
-                        AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
-                        AUDIO_ENABLED);
+                            AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
+                            CLOCK_GATING_DISABLE);
+        set_reg_field_value(value, 1,
+                            AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
+                            AUDIO_ENABLED);
 
         AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
         value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
index 4fd49a16c3b6..e42b6eb1c1f0 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
@@ -87,6 +87,9 @@ static void dce110_update_generic_info_packet(
          */
         uint32_t max_retries = 50;
 
+        /*we need turn on clock before programming AFMT block*/
+        REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1);
+
         if (REG(AFMT_VBI_PACKET_CONTROL1)) {
                 if (packet_index >= 8)
                         ASSERT(0);
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 1229a3315018..07ff8d2faf3f 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -991,6 +991,16 @@ void dce110_disable_stream(struct pipe_ctx *pipe_ctx, int option)
         struct dc_link *link = stream->sink->link;
         struct dc *dc = pipe_ctx->stream->ctx->dc;
 
+        if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
+                pipe_ctx->stream_res.stream_enc->funcs->stop_hdmi_info_packets(
+                        pipe_ctx->stream_res.stream_enc);
+
+        if (dc_is_dp_signal(pipe_ctx->stream->signal))
+                pipe_ctx->stream_res.stream_enc->funcs->stop_dp_info_packets(
+                        pipe_ctx->stream_res.stream_enc);
+
+        pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control(
+                        pipe_ctx->stream_res.stream_enc, true);
         if (pipe_ctx->stream_res.audio) {
                 pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);
 
@@ -1015,18 +1025,6 @@ void dce110_disable_stream(struct pipe_ctx *pipe_ctx, int option)
                  */
         }
 
-        if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
-                pipe_ctx->stream_res.stream_enc->funcs->stop_hdmi_info_packets(
-                        pipe_ctx->stream_res.stream_enc);
-
-        if (dc_is_dp_signal(pipe_ctx->stream->signal))
-                pipe_ctx->stream_res.stream_enc->funcs->stop_dp_info_packets(
-                        pipe_ctx->stream_res.stream_enc);
-
-        pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control(
-                        pipe_ctx->stream_res.stream_enc, true);
-
-
         /* blank at encoder level */
         if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
                 if (pipe_ctx->stream->sink->link->connector_signal == SIGNAL_TYPE_EDP)
@@ -1774,6 +1772,10 @@ static enum dc_status validate_fbc(struct dc *dc,
         if (pipe_ctx->stream->sink->link->psr_enabled)
                 return DC_ERROR_UNEXPECTED;
 
+        /* Nothing to compress */
+        if (!pipe_ctx->plane_state)
+                return DC_ERROR_UNEXPECTED;
+
         /* Only for non-linear tiling */
         if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL)
                 return DC_ERROR_UNEXPECTED;
@@ -1868,8 +1870,10 @@ static void dce110_reset_hw_ctx_wrap(
                                 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
                         struct clock_source *old_clk = pipe_ctx_old->clock_source;
 
-                        /* disable already, no need to disable again */
-                        if (pipe_ctx->stream && !pipe_ctx->stream->dpms_off)
+                        /* Disable if new stream is null. O/w, if stream is
+                         * disabled already, no need to disable again.
+                         */
+                        if (!pipe_ctx->stream || !pipe_ctx->stream->dpms_off)
                                 core_link_disable_stream(pipe_ctx_old, FREE_ACQUIRED_RESOURCE);
 
                         pipe_ctx_old->stream_res.tg->funcs->set_blank(pipe_ctx_old->stream_res.tg, true);
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
index db96d2b47ff1..61adb8174ce0 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
@@ -1037,11 +1037,13 @@ static bool underlay_create(struct dc_context *ctx, struct resource_pool *pool)
         struct dce110_opp *dce110_oppv = kzalloc(sizeof(*dce110_oppv),
                                                  GFP_KERNEL);
 
-        if ((dce110_tgv == NULL) ||
-                (dce110_xfmv == NULL) ||
-                (dce110_miv == NULL) ||
-                (dce110_oppv == NULL))
-                        return false;
+        if (!dce110_tgv || !dce110_xfmv || !dce110_miv || !dce110_oppv) {
+                kfree(dce110_tgv);
+                kfree(dce110_xfmv);
+                kfree(dce110_miv);
+                kfree(dce110_oppv);
+                return false;
+        }
 
         dce110_opp_v_construct(dce110_oppv, ctx);
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
index 67ac737eaa7e..4befce6cd87a 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
@@ -1112,10 +1112,7 @@ bool dce110_timing_generator_validate_timing(
         enum signal_type signal)
 {
         uint32_t h_blank;
-        uint32_t h_back_porch;
-        uint32_t hsync_offset = timing->h_border_right +
-                        timing->h_front_porch;
-        uint32_t h_sync_start = timing->h_addressable + hsync_offset;
+        uint32_t h_back_porch, hsync_offset, h_sync_start;
 
         struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
 
@@ -1124,6 +1121,9 @@ bool dce110_timing_generator_validate_timing(
         if (!timing)
                 return false;
 
+        hsync_offset = timing->h_border_right + timing->h_front_porch;
+        h_sync_start = timing->h_addressable + hsync_offset;
+
         /* Currently we don't support 3D, so block all 3D timings */
         if (timing->timing_3d_format != TIMING_3D_FORMAT_NONE)
                 return false;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index 4c4bd72d4e40..9fc8f827f2a1 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -912,11 +912,13 @@ static struct pipe_ctx *dcn10_acquire_idle_pipe_for_layer(
         struct pipe_ctx *head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream);
         struct pipe_ctx *idle_pipe = find_idle_secondary_pipe(res_ctx, pool);
 
-        if (!head_pipe)
+        if (!head_pipe) {
                 ASSERT(0);
+                return NULL;
+        }
 
         if (!idle_pipe)
-                return false;
+                return NULL;
 
         idle_pipe->stream = head_pipe->stream;
         idle_pipe->stream_res.tg = head_pipe->stream_res.tg;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
index c7333cdf1802..fced178c8c79 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
@@ -496,9 +496,6 @@ static bool tgn10_validate_timing(
                 timing->timing_3d_format != TIMING_3D_FORMAT_INBAND_FA)
                 return false;
 
-        if (timing->timing_3d_format != TIMING_3D_FORMAT_NONE &&
-                tg->ctx->dc->debug.disable_stereo_support)
-                return false;
         /* Temporarily blocking interlacing mode until it's supported */
         if (timing->flags.INTERLACE == 1)
                 return false;
diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_status.h b/drivers/gpu/drm/amd/display/dc/inc/core_status.h
index 01df85641684..94fc31080fda 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/core_status.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/core_status.h
@@ -38,7 +38,7 @@ enum dc_status {
         DC_FAIL_DETACH_SURFACES = 8,
         DC_FAIL_SURFACE_VALIDATE = 9,
         DC_NO_DP_LINK_BANDWIDTH = 10,
-        DC_EXCEED_DONGLE_MAX_CLK = 11,
+        DC_EXCEED_DONGLE_CAP = 11,
         DC_SURFACE_PIXEL_FORMAT_UNSUPPORTED = 12,
         DC_FAIL_BANDWIDTH_VALIDATE = 13, /* BW and Watermark validation */
         DC_FAIL_SCALING = 14,
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h b/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h
index 7c08bc62c1f5..ea88997e1bbd 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h
@@ -259,13 +259,6 @@ struct transform_funcs {
                         struct transform *xfm_base,
                         const struct dc_cursor_attributes *attr);
 
-        void (*set_cursor_position)(
-                        struct transform *xfm_base,
-                        const struct dc_cursor_position *pos,
-                        const struct dc_cursor_mi_param *param,
-                        uint32_t width
-                        );
-
 };
 
 const uint16_t *get_filter_2tap_16p(void);
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index 898f9a078830..a6511918f632 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -5451,28 +5451,6 @@ void cik_pcie_gart_tlb_flush(struct radeon_device *rdev)
         WREG32(VM_INVALIDATE_REQUEST, 0x1);
 }
 
-static void cik_pcie_init_compute_vmid(struct radeon_device *rdev)
-{
-        int i;
-        uint32_t sh_mem_bases, sh_mem_config;
-
-        sh_mem_bases = 0x6000 | 0x6000 << 16;
-        sh_mem_config = ALIGNMENT_MODE(SH_MEM_ALIGNMENT_MODE_UNALIGNED);
-        sh_mem_config |= DEFAULT_MTYPE(MTYPE_NONCACHED);
-
-        mutex_lock(&rdev->srbm_mutex);
-        for (i = 8; i < 16; i++) {
-                cik_srbm_select(rdev, 0, 0, 0, i);
-                /* CP and shaders */
-                WREG32(SH_MEM_CONFIG, sh_mem_config);
-                WREG32(SH_MEM_APE1_BASE, 1);
-                WREG32(SH_MEM_APE1_LIMIT, 0);
-                WREG32(SH_MEM_BASES, sh_mem_bases);
-        }
-        cik_srbm_select(rdev, 0, 0, 0, 0);
-        mutex_unlock(&rdev->srbm_mutex);
-}
-
 /**
  * cik_pcie_gart_enable - gart enable
  *
@@ -5586,8 +5564,6 @@ static int cik_pcie_gart_enable(struct radeon_device *rdev)
         cik_srbm_select(rdev, 0, 0, 0, 0);
         mutex_unlock(&rdev->srbm_mutex);
 
-        cik_pcie_init_compute_vmid(rdev);
-
         cik_pcie_gart_tlb_flush(rdev);
         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
                  (unsigned)(rdev->mc.gtt_size >> 20),
diff --git a/drivers/gpu/drm/ttm/ttm_page_alloc.c b/drivers/gpu/drm/ttm/ttm_page_alloc.c
index b0551aa677b8..8d7172e8381d 100644
--- a/drivers/gpu/drm/ttm/ttm_page_alloc.c
+++ b/drivers/gpu/drm/ttm/ttm_page_alloc.c
@@ -1062,7 +1062,6 @@ void ttm_pool_unpopulate(struct ttm_tt *ttm)
 }
 EXPORT_SYMBOL(ttm_pool_unpopulate);
 
-#if defined(CONFIG_SWIOTLB) || defined(CONFIG_INTEL_IOMMU)
 int ttm_populate_and_map_pages(struct device *dev, struct ttm_dma_tt *tt)
 {
         unsigned i, j;
@@ -1133,7 +1132,6 @@ void ttm_unmap_and_unpopulate_pages(struct device *dev, struct ttm_dma_tt *tt)
         ttm_pool_unpopulate(&tt->ttm);
 }
 EXPORT_SYMBOL(ttm_unmap_and_unpopulate_pages);
-#endif
 
 int ttm_page_alloc_debugfs(struct seq_file *m, void *data)
 {
diff --git a/include/drm/ttm/ttm_page_alloc.h b/include/drm/ttm/ttm_page_alloc.h
index 38a2b4770c35..593811362a91 100644
--- a/include/drm/ttm/ttm_page_alloc.h
+++ b/include/drm/ttm/ttm_page_alloc.h
@@ -59,11 +59,20 @@ int ttm_pool_populate(struct ttm_tt *ttm);
 void ttm_pool_unpopulate(struct ttm_tt *ttm);
 
 /**
+ * Populates and DMA maps pages to fullfil a ttm_dma_populate() request
+ */
+int ttm_populate_and_map_pages(struct device *dev, struct ttm_dma_tt *tt);
+
+/**
+ * Unpopulates and DMA unmaps pages as part of a
+ * ttm_dma_unpopulate() request */
+void ttm_unmap_and_unpopulate_pages(struct device *dev, struct ttm_dma_tt *tt);
+
+/**
  * Output the state of pools to debugfs file
  */
 int ttm_page_alloc_debugfs(struct seq_file *m, void *data);
 
-
 #if defined(CONFIG_SWIOTLB) || defined(CONFIG_INTEL_IOMMU)
 /**
  * Initialize pool allocator.
@@ -83,17 +92,6 @@ int ttm_dma_page_alloc_debugfs(struct seq_file *m, void *data);
 int ttm_dma_populate(struct ttm_dma_tt *ttm_dma, struct device *dev);
 void ttm_dma_unpopulate(struct ttm_dma_tt *ttm_dma, struct device *dev);
 
-
-/**
- * Populates and DMA maps pages to fullfil a ttm_dma_populate() request
- */
-int ttm_populate_and_map_pages(struct device *dev, struct ttm_dma_tt *tt);
-
-/**
- * Unpopulates and DMA unmaps pages as part of a
- * ttm_dma_unpopulate() request */
-void ttm_unmap_and_unpopulate_pages(struct device *dev, struct ttm_dma_tt *tt);
-
 #else
 static inline int ttm_dma_page_alloc_init(struct ttm_mem_global *glob,
                                           unsigned max_pages)
@@ -116,16 +114,6 @@ static inline void ttm_dma_unpopulate(struct ttm_dma_tt *ttm_dma,
                                       struct device *dev)
 {
 }
-
-static inline int ttm_populate_and_map_pages(struct device *dev, struct ttm_dma_tt *tt)
-{
-        return -ENOMEM;
-}
-
-static inline void ttm_unmap_and_unpopulate_pages(struct device *dev, struct ttm_dma_tt *tt)
-{
-}
-
 #endif
 
 #endif