diff options
author | Rajendra Nayak <rnayak@codeaurora.org> | 2016-08-17 01:18:47 -0400 |
---|---|---|
committer | Andy Gross <andy.gross@linaro.org> | 2016-08-23 23:57:35 -0400 |
commit | 4f6e4892ea9a1af23e352628e491e9cbb124bc5f (patch) | |
tree | 3b97663c64c5b952ad962d7f363f2e8336318554 | |
parent | 0f6625fd00a534b47add4134c1fc760c9ef2cb58 (diff) |
arm64: dts: msm8916: Add thermal zones, tsens and qfprom nodes
Add thermal zones, tsens and qfprom nodes
Acked-by: Eduardo Valentin <edubezval@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
-rw-r--r-- | arch/arm64/boot/dts/qcom/msm8916.dtsi | 64 |
1 files changed, 64 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index d07b2dd61bc6..74daf89d977d 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi | |||
@@ -160,6 +160,49 @@ | |||
160 | interrupts = <GIC_PPI 7 GIC_CPU_MASK_SIMPLE(4)>; | 160 | interrupts = <GIC_PPI 7 GIC_CPU_MASK_SIMPLE(4)>; |
161 | }; | 161 | }; |
162 | 162 | ||
163 | thermal-zones { | ||
164 | cpu-thermal0 { | ||
165 | polling-delay-passive = <250>; | ||
166 | polling-delay = <1000>; | ||
167 | |||
168 | thermal-sensors = <&tsens 4>; | ||
169 | |||
170 | trips { | ||
171 | cpu_alert0: trip0 { | ||
172 | temperature = <75000>; | ||
173 | hysteresis = <2000>; | ||
174 | type = "passive"; | ||
175 | }; | ||
176 | cpu_crit0: trip1 { | ||
177 | temperature = <110000>; | ||
178 | hysteresis = <2000>; | ||
179 | type = "critical"; | ||
180 | }; | ||
181 | }; | ||
182 | }; | ||
183 | |||
184 | cpu-thermal1 { | ||
185 | polling-delay-passive = <250>; | ||
186 | polling-delay = <1000>; | ||
187 | |||
188 | thermal-sensors = <&tsens 3>; | ||
189 | |||
190 | trips { | ||
191 | cpu_alert1: trip0 { | ||
192 | temperature = <75000>; | ||
193 | hysteresis = <2000>; | ||
194 | type = "passive"; | ||
195 | }; | ||
196 | cpu_crit1: trip1 { | ||
197 | temperature = <110000>; | ||
198 | hysteresis = <2000>; | ||
199 | type = "critical"; | ||
200 | }; | ||
201 | }; | ||
202 | }; | ||
203 | |||
204 | }; | ||
205 | |||
163 | timer { | 206 | timer { |
164 | compatible = "arm,armv8-timer"; | 207 | compatible = "arm,armv8-timer"; |
165 | interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | 208 | interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
@@ -620,6 +663,27 @@ | |||
620 | clocks = <&gcc GCC_PRNG_AHB_CLK>; | 663 | clocks = <&gcc GCC_PRNG_AHB_CLK>; |
621 | clock-names = "core"; | 664 | clock-names = "core"; |
622 | }; | 665 | }; |
666 | |||
667 | qfprom: qfprom@5c000 { | ||
668 | compatible = "qcom,qfprom"; | ||
669 | reg = <0x5c000 0x1000>; | ||
670 | #address-cells = <1>; | ||
671 | #size-cells = <1>; | ||
672 | tsens_caldata: caldata@d0 { | ||
673 | reg = <0xd0 0x8>; | ||
674 | }; | ||
675 | tsens_calsel: calsel@ec { | ||
676 | reg = <0xec 0x4>; | ||
677 | }; | ||
678 | }; | ||
679 | |||
680 | tsens: thermal-sensor@4a8000 { | ||
681 | compatible = "qcom,msm8916-tsens"; | ||
682 | reg = <0x4a8000 0x2000>; | ||
683 | nvmem-cells = <&tsens_caldata>, <&tsens_calsel>; | ||
684 | nvmem-cell-names = "calib", "calib_sel"; | ||
685 | #thermal-sensor-cells = <1>; | ||
686 | }; | ||
623 | }; | 687 | }; |
624 | 688 | ||
625 | smd { | 689 | smd { |