aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorOlof Johansson <olof@lixom.net>2017-01-29 23:59:55 -0500
committerOlof Johansson <olof@lixom.net>2017-01-29 23:59:55 -0500
commit4c8cb9c40a5eb50ad4edbdea69b3c0a40dfc8f57 (patch)
tree9600616eb53bb98fecd36e43d438e2a398d891df
parent9cbcb077bfb451206a1743613e87b2567a8a4d13 (diff)
parent7bcf266462da736ae4b42d5c73cd5dc0da540772 (diff)
Merge tag 'tegra-for-4.11-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/dt64
arm64: tegra: Device tree changes for v4.11-rc1 This contains three patches that reintroduce symbolic identifiers for clocks, resets and mailboxes. These had been converted to literals in the v4.10 release to avoid complicated dependencies between branches. * tag 'tegra-for-4.11-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: arm64: tegra: Use symbolic reset identifiers arm64: tegra: Use symbolic clock identifiers arm64: tegra: Use symbolic HSP identifiers Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra186.dtsi86
1 files changed, 45 insertions, 41 deletions
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index a918e10240fd..62fa85ae0271 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -1,5 +1,8 @@
1#include <dt-bindings/clock/tegra186-clock.h>
1#include <dt-bindings/gpio/tegra186-gpio.h> 2#include <dt-bindings/gpio/tegra186-gpio.h>
2#include <dt-bindings/interrupt-controller/arm-gic.h> 3#include <dt-bindings/interrupt-controller/arm-gic.h>
4#include <dt-bindings/mailbox/tegra186-hsp.h>
5#include <dt-bindings/reset/tegra186-reset.h>
3 6
4/ { 7/ {
5 compatible = "nvidia,tegra186"; 8 compatible = "nvidia,tegra186";
@@ -29,9 +32,9 @@
29 reg = <0x0 0x03100000 0x0 0x40>; 32 reg = <0x0 0x03100000 0x0 0x40>;
30 reg-shift = <2>; 33 reg-shift = <2>;
31 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 34 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
32 clocks = <&bpmp 55>; 35 clocks = <&bpmp TEGRA186_CLK_UARTA>;
33 clock-names = "serial"; 36 clock-names = "serial";
34 resets = <&bpmp 47>; 37 resets = <&bpmp TEGRA186_RESET_UARTA>;
35 reset-names = "serial"; 38 reset-names = "serial";
36 status = "disabled"; 39 status = "disabled";
37 }; 40 };
@@ -41,9 +44,9 @@
41 reg = <0x0 0x03110000 0x0 0x40>; 44 reg = <0x0 0x03110000 0x0 0x40>;
42 reg-shift = <2>; 45 reg-shift = <2>;
43 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 46 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
44 clocks = <&bpmp 56>; 47 clocks = <&bpmp TEGRA186_CLK_UARTB>;
45 clock-names = "serial"; 48 clock-names = "serial";
46 resets = <&bpmp 48>; 49 resets = <&bpmp TEGRA186_RESET_UARTB>;
47 reset-names = "serial"; 50 reset-names = "serial";
48 status = "disabled"; 51 status = "disabled";
49 }; 52 };
@@ -53,9 +56,9 @@
53 reg = <0x0 0x03130000 0x0 0x40>; 56 reg = <0x0 0x03130000 0x0 0x40>;
54 reg-shift = <2>; 57 reg-shift = <2>;
55 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 58 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
56 clocks = <&bpmp 77>; 59 clocks = <&bpmp TEGRA186_CLK_UARTD>;
57 clock-names = "serial"; 60 clock-names = "serial";
58 resets = <&bpmp 50>; 61 resets = <&bpmp TEGRA186_RESET_UARTD>;
59 reset-names = "serial"; 62 reset-names = "serial";
60 status = "disabled"; 63 status = "disabled";
61 }; 64 };
@@ -65,9 +68,9 @@
65 reg = <0x0 0x03140000 0x0 0x40>; 68 reg = <0x0 0x03140000 0x0 0x40>;
66 reg-shift = <2>; 69 reg-shift = <2>;
67 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 70 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
68 clocks = <&bpmp 194>; 71 clocks = <&bpmp TEGRA186_CLK_UARTE>;
69 clock-names = "serial"; 72 clock-names = "serial";
70 resets = <&bpmp 132>; 73 resets = <&bpmp TEGRA186_RESET_UARTE>;
71 reset-names = "serial"; 74 reset-names = "serial";
72 status = "disabled"; 75 status = "disabled";
73 }; 76 };
@@ -77,9 +80,9 @@
77 reg = <0x0 0x03150000 0x0 0x40>; 80 reg = <0x0 0x03150000 0x0 0x40>;
78 reg-shift = <2>; 81 reg-shift = <2>;
79 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 82 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
80 clocks = <&bpmp 195>; 83 clocks = <&bpmp TEGRA186_CLK_UARTF>;
81 clock-names = "serial"; 84 clock-names = "serial";
82 resets = <&bpmp 111>; 85 resets = <&bpmp TEGRA186_RESET_UARTF>;
83 reset-names = "serial"; 86 reset-names = "serial";
84 status = "disabled"; 87 status = "disabled";
85 }; 88 };
@@ -90,9 +93,9 @@
90 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 93 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
91 #address-cells = <1>; 94 #address-cells = <1>;
92 #size-cells = <0>; 95 #size-cells = <0>;
93 clocks = <&bpmp 47>; 96 clocks = <&bpmp TEGRA186_CLK_I2C1>;
94 clock-names = "div-clk"; 97 clock-names = "div-clk";
95 resets = <&bpmp 19>; 98 resets = <&bpmp TEGRA186_RESET_I2C1>;
96 reset-names = "i2c"; 99 reset-names = "i2c";
97 status = "disabled"; 100 status = "disabled";
98 }; 101 };
@@ -103,9 +106,9 @@
103 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 106 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
104 #address-cells = <1>; 107 #address-cells = <1>;
105 #size-cells = <0>; 108 #size-cells = <0>;
106 clocks = <&bpmp 75>; 109 clocks = <&bpmp TEGRA186_CLK_I2C3>;
107 clock-names = "div-clk"; 110 clock-names = "div-clk";
108 resets = <&bpmp 21>; 111 resets = <&bpmp TEGRA186_RESET_I2C3>;
109 reset-names = "i2c"; 112 reset-names = "i2c";
110 status = "disabled"; 113 status = "disabled";
111 }; 114 };
@@ -117,9 +120,9 @@
117 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 120 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
118 #address-cells = <1>; 121 #address-cells = <1>;
119 #size-cells = <0>; 122 #size-cells = <0>;
120 clocks = <&bpmp 86>; 123 clocks = <&bpmp TEGRA186_CLK_I2C4>;
121 clock-names = "div-clk"; 124 clock-names = "div-clk";
122 resets = <&bpmp 22>; 125 resets = <&bpmp TEGRA186_RESET_I2C4>;
123 reset-names = "i2c"; 126 reset-names = "i2c";
124 status = "disabled"; 127 status = "disabled";
125 }; 128 };
@@ -131,9 +134,9 @@
131 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 134 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
132 #address-cells = <1>; 135 #address-cells = <1>;
133 #size-cells = <0>; 136 #size-cells = <0>;
134 clocks = <&bpmp 48>; 137 clocks = <&bpmp TEGRA186_CLK_I2C5>;
135 clock-names = "div-clk"; 138 clock-names = "div-clk";
136 resets = <&bpmp 23>; 139 resets = <&bpmp TEGRA186_RESET_I2C5>;
137 reset-names = "i2c"; 140 reset-names = "i2c";
138 status = "disabled"; 141 status = "disabled";
139 }; 142 };
@@ -145,9 +148,9 @@
145 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 148 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
146 #address-cells = <1>; 149 #address-cells = <1>;
147 #size-cells = <0>; 150 #size-cells = <0>;
148 clocks = <&bpmp 125>; 151 clocks = <&bpmp TEGRA186_CLK_I2C6>;
149 clock-names = "div-clk"; 152 clock-names = "div-clk";
150 resets = <&bpmp 24>; 153 resets = <&bpmp TEGRA186_RESET_I2C6>;
151 reset-names = "i2c"; 154 reset-names = "i2c";
152 status = "disabled"; 155 status = "disabled";
153 }; 156 };
@@ -158,9 +161,9 @@
158 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 161 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
159 #address-cells = <1>; 162 #address-cells = <1>;
160 #size-cells = <0>; 163 #size-cells = <0>;
161 clocks = <&bpmp 182>; 164 clocks = <&bpmp TEGRA186_CLK_I2C7>;
162 clock-names = "div-clk"; 165 clock-names = "div-clk";
163 resets = <&bpmp 81>; 166 resets = <&bpmp TEGRA186_RESET_I2C7>;
164 reset-names = "i2c"; 167 reset-names = "i2c";
165 status = "disabled"; 168 status = "disabled";
166 }; 169 };
@@ -171,9 +174,9 @@
171 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 174 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
172 #address-cells = <1>; 175 #address-cells = <1>;
173 #size-cells = <0>; 176 #size-cells = <0>;
174 clocks = <&bpmp 183>; 177 clocks = <&bpmp TEGRA186_CLK_I2C9>;
175 clock-names = "div-clk"; 178 clock-names = "div-clk";
176 resets = <&bpmp 83>; 179 resets = <&bpmp TEGRA186_RESET_I2C9>;
177 reset-names = "i2c"; 180 reset-names = "i2c";
178 status = "disabled"; 181 status = "disabled";
179 }; 182 };
@@ -182,9 +185,9 @@
182 compatible = "nvidia,tegra186-sdhci"; 185 compatible = "nvidia,tegra186-sdhci";
183 reg = <0x0 0x03400000 0x0 0x10000>; 186 reg = <0x0 0x03400000 0x0 0x10000>;
184 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 187 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
185 clocks = <&bpmp 52>; 188 clocks = <&bpmp TEGRA186_CLK_SDMMC1>;
186 clock-names = "sdhci"; 189 clock-names = "sdhci";
187 resets = <&bpmp 33>; 190 resets = <&bpmp TEGRA186_RESET_SDMMC1>;
188 reset-names = "sdhci"; 191 reset-names = "sdhci";
189 status = "disabled"; 192 status = "disabled";
190 }; 193 };
@@ -193,9 +196,9 @@
193 compatible = "nvidia,tegra186-sdhci"; 196 compatible = "nvidia,tegra186-sdhci";
194 reg = <0x0 0x03420000 0x0 0x10000>; 197 reg = <0x0 0x03420000 0x0 0x10000>;
195 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 198 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
196 clocks = <&bpmp 53>; 199 clocks = <&bpmp TEGRA186_CLK_SDMMC2>;
197 clock-names = "sdhci"; 200 clock-names = "sdhci";
198 resets = <&bpmp 34>; 201 resets = <&bpmp TEGRA186_RESET_SDMMC2>;
199 reset-names = "sdhci"; 202 reset-names = "sdhci";
200 status = "disabled"; 203 status = "disabled";
201 }; 204 };
@@ -204,9 +207,9 @@
204 compatible = "nvidia,tegra186-sdhci"; 207 compatible = "nvidia,tegra186-sdhci";
205 reg = <0x0 0x03440000 0x0 0x10000>; 208 reg = <0x0 0x03440000 0x0 0x10000>;
206 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 209 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
207 clocks = <&bpmp 76>; 210 clocks = <&bpmp TEGRA186_CLK_SDMMC3>;
208 clock-names = "sdhci"; 211 clock-names = "sdhci";
209 resets = <&bpmp 35>; 212 resets = <&bpmp TEGRA186_RESET_SDMMC3>;
210 reset-names = "sdhci"; 213 reset-names = "sdhci";
211 status = "disabled"; 214 status = "disabled";
212 }; 215 };
@@ -215,9 +218,9 @@
215 compatible = "nvidia,tegra186-sdhci"; 218 compatible = "nvidia,tegra186-sdhci";
216 reg = <0x0 0x03460000 0x0 0x10000>; 219 reg = <0x0 0x03460000 0x0 0x10000>;
217 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 220 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
218 clocks = <&bpmp 54>; 221 clocks = <&bpmp TEGRA186_CLK_SDMMC4>;
219 clock-names = "sdhci"; 222 clock-names = "sdhci";
220 resets = <&bpmp 36>; 223 resets = <&bpmp TEGRA186_RESET_SDMMC4>;
221 reset-names = "sdhci"; 224 reset-names = "sdhci";
222 status = "disabled"; 225 status = "disabled";
223 }; 226 };
@@ -248,9 +251,9 @@
248 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 251 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
249 #address-cells = <1>; 252 #address-cells = <1>;
250 #size-cells = <0>; 253 #size-cells = <0>;
251 clocks = <&bpmp 218>; 254 clocks = <&bpmp TEGRA186_CLK_I2C2>;
252 clock-names = "div-clk"; 255 clock-names = "div-clk";
253 resets = <&bpmp 20>; 256 resets = <&bpmp TEGRA186_RESET_I2C2>;
254 reset-names = "i2c"; 257 reset-names = "i2c";
255 status = "disabled"; 258 status = "disabled";
256 }; 259 };
@@ -261,9 +264,9 @@
261 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 264 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
262 #address-cells = <1>; 265 #address-cells = <1>;
263 #size-cells = <0>; 266 #size-cells = <0>;
264 clocks = <&bpmp 219>; 267 clocks = <&bpmp TEGRA186_CLK_I2C8>;
265 clock-names = "div-clk"; 268 clock-names = "div-clk";
266 resets = <&bpmp 82>; 269 resets = <&bpmp TEGRA186_RESET_I2C8>;
267 reset-names = "i2c"; 270 reset-names = "i2c";
268 status = "disabled"; 271 status = "disabled";
269 }; 272 };
@@ -273,9 +276,9 @@
273 reg = <0x0 0x0c280000 0x0 0x40>; 276 reg = <0x0 0x0c280000 0x0 0x40>;
274 reg-shift = <2>; 277 reg-shift = <2>;
275 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 278 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
276 clocks = <&bpmp 215>; 279 clocks = <&bpmp TEGRA186_CLK_UARTC>;
277 clock-names = "serial"; 280 clock-names = "serial";
278 resets = <&bpmp 49>; 281 resets = <&bpmp TEGRA186_RESET_UARTC>;
279 reset-names = "serial"; 282 reset-names = "serial";
280 status = "disabled"; 283 status = "disabled";
281 }; 284 };
@@ -285,9 +288,9 @@
285 reg = <0x0 0x0c290000 0x0 0x40>; 288 reg = <0x0 0x0c290000 0x0 0x40>;
286 reg-shift = <2>; 289 reg-shift = <2>;
287 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 290 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
288 clocks = <&bpmp 216>; 291 clocks = <&bpmp TEGRA186_CLK_UARTG>;
289 clock-names = "serial"; 292 clock-names = "serial";
290 resets = <&bpmp 112>; 293 resets = <&bpmp TEGRA186_RESET_UARTG>;
291 reset-names = "serial"; 294 reset-names = "serial";
292 status = "disabled"; 295 status = "disabled";
293 }; 296 };
@@ -369,7 +372,8 @@
369 372
370 bpmp: bpmp { 373 bpmp: bpmp {
371 compatible = "nvidia,tegra186-bpmp"; 374 compatible = "nvidia,tegra186-bpmp";
372 mboxes = <&hsp_top0 0 19>; 375 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
376 TEGRA_HSP_DB_MASTER_BPMP>;
373 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 377 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;
374 #clock-cells = <1>; 378 #clock-cells = <1>;
375 #reset-cells = <1>; 379 #reset-cells = <1>;
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-26 01:12:00 -0400