diff options
author | Olof Johansson <olof@lixom.net> | 2017-01-29 23:57:26 -0500 |
---|---|---|
committer | Olof Johansson <olof@lixom.net> | 2017-01-29 23:57:26 -0500 |
commit | 9cbcb077bfb451206a1743613e87b2567a8a4d13 (patch) | |
tree | 15ec7ae22cd7856975a925e88d42566391639b34 | |
parent | 656b532ffc60590cfc3433eb4d6ccdfd1741a1f5 (diff) | |
parent | 7e1c23b94ed7f0d2719795a9828402003de5335d (diff) |
Merge tag 'renesas-arm64-dt2-for-v4.11' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt64
Second Round of Renesas ARM64 Based SoC DT Updates for v4.11
r8a779[56] SoCs:
* Mark EthernetAVB device node disabled in DT for r8a779[56] SoCs
- They are enabled as appropriate in board DT files
* Link ARM GIC to clock and clock domain on r8a779[56] SoCs
* Add thermal support
r8a7795 SoC:
* Tidyup audma definition order on r8a7795 SoC
* Add missing power-domains property for SATA
r8a7795/h3ulcb board:
* Add MIX/CTU support as per support present in DT for r8a7796
* tag 'renesas-arm64-dt2-for-v4.11' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
arm64: dts: r8a7796: Mark EthernetAVB device node disabled
arm64: dts: r8a7795: Mark EthernetAVB device node disabled
arm64: dts: r8a7795: tidyup audma definition order
arm64: dts: r8a7796: Link ARM GIC to clock and clock domain
arm64: dts: r8a7795: Link ARM GIC to clock and clock domain
arm64: dts: r8a7796: Add R-Car Gen3 thermal support
arm64: dts: r8a7795: Add R-Car Gen3 thermal support
arm64: dts: r8a7795: Add missing power-domains property for sata
arm64: dts: h3ulcb: follow sound CTU/MIX supports
Signed-off-by: Olof Johansson <olof@lixom.net>
-rw-r--r-- | arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts | 2 | ||||
-rw-r--r-- | arch/arm64/boot/dts/renesas/r8a7795.dtsi | 195 | ||||
-rw-r--r-- | arch/arm64/boot/dts/renesas/r8a7796.dtsi | 62 |
3 files changed, 193 insertions, 66 deletions
diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts index dbea2c3d8f0c..c5f8f69a4f5f 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts +++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts | |||
@@ -277,6 +277,8 @@ | |||
277 | <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, | 277 | <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, |
278 | <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, | 278 | <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, |
279 | <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, | 279 | <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, |
280 | <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, | ||
281 | <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, | ||
280 | <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, | 282 | <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, |
281 | <&audio_clk_a>, <&cs2000>, | 283 | <&audio_clk_a>, <&cs2000>, |
282 | <&audio_clk_c>, | 284 | <&audio_clk_c>, |
diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index 972e379c0596..eac4f29aa5cd 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi | |||
@@ -166,6 +166,9 @@ | |||
166 | <0x0 0xf1060000 0 0x20000>; | 166 | <0x0 0xf1060000 0 0x20000>; |
167 | interrupts = <GIC_PPI 9 | 167 | interrupts = <GIC_PPI 9 |
168 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; | 168 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; |
169 | clocks = <&cpg CPG_MOD 408>; | ||
170 | clock-names = "clk"; | ||
171 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | ||
169 | }; | 172 | }; |
170 | 173 | ||
171 | wdt0: watchdog@e6020000 { | 174 | wdt0: watchdog@e6020000 { |
@@ -337,72 +340,6 @@ | |||
337 | #power-domain-cells = <1>; | 340 | #power-domain-cells = <1>; |
338 | }; | 341 | }; |
339 | 342 | ||
340 | audma0: dma-controller@ec700000 { | ||
341 | compatible = "renesas,dmac-r8a7795", | ||
342 | "renesas,rcar-dmac"; | ||
343 | reg = <0 0xec700000 0 0x10000>; | ||
344 | interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH | ||
345 | GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH | ||
346 | GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH | ||
347 | GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH | ||
348 | GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH | ||
349 | GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH | ||
350 | GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH | ||
351 | GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH | ||
352 | GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH | ||
353 | GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH | ||
354 | GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH | ||
355 | GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH | ||
356 | GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH | ||
357 | GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH | ||
358 | GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH | ||
359 | GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH | ||
360 | GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; | ||
361 | interrupt-names = "error", | ||
362 | "ch0", "ch1", "ch2", "ch3", | ||
363 | "ch4", "ch5", "ch6", "ch7", | ||
364 | "ch8", "ch9", "ch10", "ch11", | ||
365 | "ch12", "ch13", "ch14", "ch15"; | ||
366 | clocks = <&cpg CPG_MOD 502>; | ||
367 | clock-names = "fck"; | ||
368 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | ||
369 | #dma-cells = <1>; | ||
370 | dma-channels = <16>; | ||
371 | }; | ||
372 | |||
373 | audma1: dma-controller@ec720000 { | ||
374 | compatible = "renesas,dmac-r8a7795", | ||
375 | "renesas,rcar-dmac"; | ||
376 | reg = <0 0xec720000 0 0x10000>; | ||
377 | interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH | ||
378 | GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH | ||
379 | GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH | ||
380 | GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH | ||
381 | GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH | ||
382 | GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH | ||
383 | GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH | ||
384 | GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH | ||
385 | GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH | ||
386 | GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH | ||
387 | GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH | ||
388 | GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH | ||
389 | GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH | ||
390 | GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH | ||
391 | GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH | ||
392 | GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH | ||
393 | GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>; | ||
394 | interrupt-names = "error", | ||
395 | "ch0", "ch1", "ch2", "ch3", | ||
396 | "ch4", "ch5", "ch6", "ch7", | ||
397 | "ch8", "ch9", "ch10", "ch11", | ||
398 | "ch12", "ch13", "ch14", "ch15"; | ||
399 | clocks = <&cpg CPG_MOD 501>; | ||
400 | clock-names = "fck"; | ||
401 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | ||
402 | #dma-cells = <1>; | ||
403 | dma-channels = <16>; | ||
404 | }; | ||
405 | |||
406 | pfc: pfc@e6060000 { | 343 | pfc: pfc@e6060000 { |
407 | compatible = "renesas,pfc-r8a7795"; | 344 | compatible = "renesas,pfc-r8a7795"; |
408 | reg = <0 0xe6060000 0 0x50c>; | 345 | reg = <0 0xe6060000 0 0x50c>; |
@@ -522,6 +459,72 @@ | |||
522 | dma-channels = <16>; | 459 | dma-channels = <16>; |
523 | }; | 460 | }; |
524 | 461 | ||
462 | audma0: dma-controller@ec700000 { | ||
463 | compatible = "renesas,dmac-r8a7795", | ||
464 | "renesas,rcar-dmac"; | ||
465 | reg = <0 0xec700000 0 0x10000>; | ||
466 | interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH | ||
467 | GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH | ||
468 | GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH | ||
469 | GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH | ||
470 | GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH | ||
471 | GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH | ||
472 | GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH | ||
473 | GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH | ||
474 | GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH | ||
475 | GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH | ||
476 | GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH | ||
477 | GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH | ||
478 | GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH | ||
479 | GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH | ||
480 | GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH | ||
481 | GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH | ||
482 | GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; | ||
483 | interrupt-names = "error", | ||
484 | "ch0", "ch1", "ch2", "ch3", | ||
485 | "ch4", "ch5", "ch6", "ch7", | ||
486 | "ch8", "ch9", "ch10", "ch11", | ||
487 | "ch12", "ch13", "ch14", "ch15"; | ||
488 | clocks = <&cpg CPG_MOD 502>; | ||
489 | clock-names = "fck"; | ||
490 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | ||
491 | #dma-cells = <1>; | ||
492 | dma-channels = <16>; | ||
493 | }; | ||
494 | |||
495 | audma1: dma-controller@ec720000 { | ||
496 | compatible = "renesas,dmac-r8a7795", | ||
497 | "renesas,rcar-dmac"; | ||
498 | reg = <0 0xec720000 0 0x10000>; | ||
499 | interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH | ||
500 | GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH | ||
501 | GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH | ||
502 | GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH | ||
503 | GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH | ||
504 | GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH | ||
505 | GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH | ||
506 | GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH | ||
507 | GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH | ||
508 | GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH | ||
509 | GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH | ||
510 | GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH | ||
511 | GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH | ||
512 | GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH | ||
513 | GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH | ||
514 | GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH | ||
515 | GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>; | ||
516 | interrupt-names = "error", | ||
517 | "ch0", "ch1", "ch2", "ch3", | ||
518 | "ch4", "ch5", "ch6", "ch7", | ||
519 | "ch8", "ch9", "ch10", "ch11", | ||
520 | "ch12", "ch13", "ch14", "ch15"; | ||
521 | clocks = <&cpg CPG_MOD 501>; | ||
522 | clock-names = "fck"; | ||
523 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | ||
524 | #dma-cells = <1>; | ||
525 | dma-channels = <16>; | ||
526 | }; | ||
527 | |||
525 | avb: ethernet@e6800000 { | 528 | avb: ethernet@e6800000 { |
526 | compatible = "renesas,etheravb-r8a7795", | 529 | compatible = "renesas,etheravb-r8a7795", |
527 | "renesas,etheravb-rcar-gen3"; | 530 | "renesas,etheravb-rcar-gen3"; |
@@ -563,6 +566,7 @@ | |||
563 | phy-mode = "rgmii-id"; | 566 | phy-mode = "rgmii-id"; |
564 | #address-cells = <1>; | 567 | #address-cells = <1>; |
565 | #size-cells = <0>; | 568 | #size-cells = <0>; |
569 | status = "disabled"; | ||
566 | }; | 570 | }; |
567 | 571 | ||
568 | can0: can@e6c30000 { | 572 | can0: can@e6c30000 { |
@@ -1148,6 +1152,7 @@ | |||
1148 | reg = <0 0xee300000 0 0x1fff>; | 1152 | reg = <0 0xee300000 0 0x1fff>; |
1149 | interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; | 1153 | interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; |
1150 | clocks = <&cpg CPG_MOD 815>; | 1154 | clocks = <&cpg CPG_MOD 815>; |
1155 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | ||
1151 | status = "disabled"; | 1156 | status = "disabled"; |
1152 | }; | 1157 | }; |
1153 | 1158 | ||
@@ -1646,5 +1651,63 @@ | |||
1646 | }; | 1651 | }; |
1647 | }; | 1652 | }; |
1648 | }; | 1653 | }; |
1654 | |||
1655 | tsc: thermal@e6198000 { | ||
1656 | compatible = "renesas,r8a7795-thermal"; | ||
1657 | reg = <0 0xe6198000 0 0x68>, | ||
1658 | <0 0xe61a0000 0 0x5c>, | ||
1659 | <0 0xe61a8000 0 0x5c>; | ||
1660 | interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, | ||
1661 | <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, | ||
1662 | <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; | ||
1663 | clocks = <&cpg CPG_MOD 522>; | ||
1664 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | ||
1665 | #thermal-sensor-cells = <1>; | ||
1666 | status = "okay"; | ||
1667 | }; | ||
1668 | |||
1669 | thermal-zones { | ||
1670 | sensor_thermal1: sensor-thermal1 { | ||
1671 | polling-delay-passive = <250>; | ||
1672 | polling-delay = <1000>; | ||
1673 | thermal-sensors = <&tsc 0>; | ||
1674 | |||
1675 | trips { | ||
1676 | sensor1_crit: sensor1-crit { | ||
1677 | temperature = <120000>; | ||
1678 | hysteresis = <2000>; | ||
1679 | type = "critical"; | ||
1680 | }; | ||
1681 | }; | ||
1682 | }; | ||
1683 | |||
1684 | sensor_thermal2: sensor-thermal2 { | ||
1685 | polling-delay-passive = <250>; | ||
1686 | polling-delay = <1000>; | ||
1687 | thermal-sensors = <&tsc 1>; | ||
1688 | |||
1689 | trips { | ||
1690 | sensor2_crit: sensor2-crit { | ||
1691 | temperature = <120000>; | ||
1692 | hysteresis = <2000>; | ||
1693 | type = "critical"; | ||
1694 | }; | ||
1695 | }; | ||
1696 | }; | ||
1697 | |||
1698 | sensor_thermal3: sensor-thermal3 { | ||
1699 | polling-delay-passive = <250>; | ||
1700 | polling-delay = <1000>; | ||
1701 | thermal-sensors = <&tsc 2>; | ||
1702 | |||
1703 | trips { | ||
1704 | sensor3_crit: sensor3-crit { | ||
1705 | temperature = <120000>; | ||
1706 | hysteresis = <2000>; | ||
1707 | type = "critical"; | ||
1708 | }; | ||
1709 | }; | ||
1710 | }; | ||
1711 | }; | ||
1649 | }; | 1712 | }; |
1650 | }; | 1713 | }; |
diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi index eb446d966621..f7120cdedd0d 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi | |||
@@ -101,6 +101,9 @@ | |||
101 | <0x0 0xf1060000 0 0x20000>; | 101 | <0x0 0xf1060000 0 0x20000>; |
102 | interrupts = <GIC_PPI 9 | 102 | interrupts = <GIC_PPI 9 |
103 | (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; | 103 | (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; |
104 | clocks = <&cpg CPG_MOD 408>; | ||
105 | clock-names = "clk"; | ||
106 | power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; | ||
104 | }; | 107 | }; |
105 | 108 | ||
106 | timer { | 109 | timer { |
@@ -469,6 +472,7 @@ | |||
469 | phy-mode = "rgmii-id"; | 472 | phy-mode = "rgmii-id"; |
470 | #address-cells = <1>; | 473 | #address-cells = <1>; |
471 | #size-cells = <0>; | 474 | #size-cells = <0>; |
475 | status = "disabled"; | ||
472 | }; | 476 | }; |
473 | 477 | ||
474 | scif2: serial@e6e88000 { | 478 | scif2: serial@e6e88000 { |
@@ -680,5 +684,63 @@ | |||
680 | power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; | 684 | power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; |
681 | status = "disabled"; | 685 | status = "disabled"; |
682 | }; | 686 | }; |
687 | |||
688 | tsc: thermal@e6198000 { | ||
689 | compatible = "renesas,r8a7796-thermal"; | ||
690 | reg = <0 0xe6198000 0 0x68>, | ||
691 | <0 0xe61a0000 0 0x5c>, | ||
692 | <0 0xe61a8000 0 0x5c>; | ||
693 | interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, | ||
694 | <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, | ||
695 | <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; | ||
696 | clocks = <&cpg CPG_MOD 522>; | ||
697 | power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; | ||
698 | #thermal-sensor-cells = <1>; | ||
699 | status = "okay"; | ||
700 | }; | ||
701 | |||
702 | thermal-zones { | ||
703 | sensor_thermal1: sensor-thermal1 { | ||
704 | polling-delay-passive = <250>; | ||
705 | polling-delay = <1000>; | ||
706 | thermal-sensors = <&tsc 0>; | ||
707 | |||
708 | trips { | ||
709 | sensor1_crit: sensor1-crit { | ||
710 | temperature = <120000>; | ||
711 | hysteresis = <2000>; | ||
712 | type = "critical"; | ||
713 | }; | ||
714 | }; | ||
715 | }; | ||
716 | |||
717 | sensor_thermal2: sensor-thermal2 { | ||
718 | polling-delay-passive = <250>; | ||
719 | polling-delay = <1000>; | ||
720 | thermal-sensors = <&tsc 1>; | ||
721 | |||
722 | trips { | ||
723 | sensor2_crit: sensor2-crit { | ||
724 | temperature = <120000>; | ||
725 | hysteresis = <2000>; | ||
726 | type = "critical"; | ||
727 | }; | ||
728 | }; | ||
729 | }; | ||
730 | |||
731 | sensor_thermal3: sensor-thermal3 { | ||
732 | polling-delay-passive = <250>; | ||
733 | polling-delay = <1000>; | ||
734 | thermal-sensors = <&tsc 2>; | ||
735 | |||
736 | trips { | ||
737 | sensor3_crit: sensor3-crit { | ||
738 | temperature = <120000>; | ||
739 | hysteresis = <2000>; | ||
740 | type = "critical"; | ||
741 | }; | ||
742 | }; | ||
743 | }; | ||
744 | }; | ||
683 | }; | 745 | }; |
684 | }; | 746 | }; |