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authorNiklas Söderlund <niklas.soderlund+renesas@ragnatech.se>2016-11-17 10:26:31 -0500
committerGeert Uytterhoeven <geert+renesas@glider.be>2016-12-27 04:57:38 -0500
commit4c2fb44d60b92c4e3e744f49767da23f4eaf1b98 (patch)
tree5f71313407172c77b9a72b635610299ebbf0d7ab
parent2d40bd24274d257796291804a82a0b07564a11f1 (diff)
pinctrl: sh-pfc: r8a7795: Support none GPIO pins bias setting
There are pins on the r8a7795 which are not part of a GPIO bank nor can be muxed between different functions. They do however allow for the bias to be configured. Add those pins to the list of pins and to the bias configuration array. The pins can now be referred to in DT by function names and their bias setting set. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7795.c450
1 files changed, 249 insertions, 201 deletions
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
index 135ed5cbeb44..504d0c3d7f74 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
@@ -538,7 +538,7 @@ MOD_SEL0_2_1 MOD_SEL1_2 \
538 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \ 538 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
539 FM(CLKOUT) FM(PRESETOUT) \ 539 FM(CLKOUT) FM(PRESETOUT) \
540 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \ 540 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \
541 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) 541 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
542 542
543enum { 543enum {
544 PINMUX_RESERVED = 0, 544 PINMUX_RESERVED = 0,
@@ -1461,46 +1461,50 @@ static const struct sh_pfc_pin pinmux_pins[] = {
1461 * number for each pin. To this end use the pin layout from 1461 * number for each pin. To this end use the pin layout from
1462 * R-Car H3SiP to calculate a unique number for each pin. 1462 * R-Car H3SiP to calculate a unique number for each pin.
1463 */ 1463 */
1464 SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, SH_PFC_PIN_CFG_DRIVE_STRENGTH), 1464 SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, CFG_FLAGS),
1465 SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, SH_PFC_PIN_CFG_DRIVE_STRENGTH), 1465 SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, CFG_FLAGS),
1466 SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, SH_PFC_PIN_CFG_DRIVE_STRENGTH), 1466 SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS),
1467 SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, SH_PFC_PIN_CFG_DRIVE_STRENGTH), 1467 SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS),
1468 SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, SH_PFC_PIN_CFG_DRIVE_STRENGTH), 1468 SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS),
1469 SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, SH_PFC_PIN_CFG_DRIVE_STRENGTH), 1469 SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS),
1470 SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, SH_PFC_PIN_CFG_DRIVE_STRENGTH), 1470 SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS),
1471 SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, SH_PFC_PIN_CFG_DRIVE_STRENGTH), 1471 SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS),
1472 SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, SH_PFC_PIN_CFG_DRIVE_STRENGTH), 1472 SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS),
1473 SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, SH_PFC_PIN_CFG_DRIVE_STRENGTH), 1473 SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS),
1474 SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, SH_PFC_PIN_CFG_DRIVE_STRENGTH), 1474 SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS),
1475 SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, SH_PFC_PIN_CFG_DRIVE_STRENGTH), 1475 SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS),
1476 SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, SH_PFC_PIN_CFG_DRIVE_STRENGTH), 1476 SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS),
1477 SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, SH_PFC_PIN_CFG_DRIVE_STRENGTH), 1477 SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS),
1478 SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, SH_PFC_PIN_CFG_DRIVE_STRENGTH), 1478 SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, CFG_FLAGS),
1479 SH_PFC_PIN_NAMED_CFG('F', 1, CLKOUT, SH_PFC_PIN_CFG_DRIVE_STRENGTH), 1479 SH_PFC_PIN_NAMED_CFG('F', 1, CLKOUT, CFG_FLAGS),
1480 SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, SH_PFC_PIN_CFG_DRIVE_STRENGTH), 1480 SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS),
1481 SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, SH_PFC_PIN_CFG_DRIVE_STRENGTH), 1481 SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, CFG_FLAGS),
1482 SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, SH_PFC_PIN_CFG_DRIVE_STRENGTH), 1482 SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, CFG_FLAGS),
1483 SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, SH_PFC_PIN_CFG_DRIVE_STRENGTH), 1483 SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, CFG_FLAGS),
1484 SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, SH_PFC_PIN_CFG_DRIVE_STRENGTH), 1484 SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, CFG_FLAGS),
1485 SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, SH_PFC_PIN_CFG_DRIVE_STRENGTH), 1485 SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, CFG_FLAGS),
1486 SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, SH_PFC_PIN_CFG_DRIVE_STRENGTH), 1486 SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, CFG_FLAGS),
1487 SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, SH_PFC_PIN_CFG_DRIVE_STRENGTH), 1487 SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, CFG_FLAGS),
1488 SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, SH_PFC_PIN_CFG_DRIVE_STRENGTH), 1488 SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, CFG_FLAGS),
1489 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, SH_PFC_PIN_CFG_DRIVE_STRENGTH), 1489 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, CFG_FLAGS),
1490 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, SH_PFC_PIN_CFG_DRIVE_STRENGTH), 1490 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, CFG_FLAGS),
1491 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, SH_PFC_PIN_CFG_DRIVE_STRENGTH), 1491 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, CFG_FLAGS),
1492 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, SH_PFC_PIN_CFG_DRIVE_STRENGTH), 1492 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, CFG_FLAGS),
1493 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, SH_PFC_PIN_CFG_DRIVE_STRENGTH), 1493 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, CFG_FLAGS),
1494 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST#, SH_PFC_PIN_CFG_DRIVE_STRENGTH), 1494 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST#, CFG_FLAGS),
1495 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, SH_PFC_PIN_CFG_DRIVE_STRENGTH), 1495 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1496 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, SH_PFC_PIN_CFG_DRIVE_STRENGTH), 1496 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, CFG_FLAGS),
1497 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, SH_PFC_PIN_CFG_DRIVE_STRENGTH), 1497 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, CFG_FLAGS),
1498 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, SH_PFC_PIN_CFG_DRIVE_STRENGTH), 1498 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, CFG_FLAGS),
1499 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 7, DU_DOTCLKIN2, SH_PFC_PIN_CFG_DRIVE_STRENGTH), 1499 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, CFG_FLAGS),
1500 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN3, SH_PFC_PIN_CFG_DRIVE_STRENGTH), 1500 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 7, DU_DOTCLKIN2, CFG_FLAGS),
1501 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, SH_PFC_PIN_CFG_DRIVE_STRENGTH), 1501 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN3, CFG_FLAGS),
1502 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1503 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1504 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS),
1505 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1502 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH), 1506 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1503 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, SH_PFC_PIN_CFG_DRIVE_STRENGTH), 1507 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
1504}; 1508};
1505 1509
1506/* - AUDIO CLOCK ------------------------------------------------------------ */ 1510/* - AUDIO CLOCK ------------------------------------------------------------ */
@@ -5415,167 +5419,211 @@ static int r8a7795_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *poc
5415#define PU6 0x18 5419#define PU6 0x18
5416 5420
5417static const struct sh_pfc_bias_info bias_info[] = { 5421static const struct sh_pfc_bias_info bias_info[] = {
5418 { RCAR_GP_PIN(2, 11), PU0, 31 }, /* AVB_PHY_INT */ 5422 { RCAR_GP_PIN(2, 11), PU0, 31 }, /* AVB_PHY_INT */
5419 { RCAR_GP_PIN(2, 10), PU0, 30 }, /* AVB_MAGIC */ 5423 { RCAR_GP_PIN(2, 10), PU0, 30 }, /* AVB_MAGIC */
5420 { RCAR_GP_PIN(2, 9), PU0, 29 }, /* AVB_MDC */ 5424 { RCAR_GP_PIN(2, 9), PU0, 29 }, /* AVB_MDC */
5421 5425 { PIN_NUMBER('A', 9), PU0, 28 }, /* AVB_MDIO */
5422 { RCAR_GP_PIN(1, 19), PU1, 31 }, /* A19 */ 5426 { PIN_NUMBER('A', 12), PU0, 27 }, /* AVB_TXCREFCLK */
5423 { RCAR_GP_PIN(1, 18), PU1, 30 }, /* A18 */ 5427 { PIN_NUMBER('B', 17), PU0, 26 }, /* AVB_TD3 */
5424 { RCAR_GP_PIN(1, 17), PU1, 29 }, /* A17 */ 5428 { PIN_NUMBER('A', 17), PU0, 25 }, /* AVB_TD2 */
5425 { RCAR_GP_PIN(1, 16), PU1, 28 }, /* A16 */ 5429 { PIN_NUMBER('B', 18), PU0, 24 }, /* AVB_TD1 */
5426 { RCAR_GP_PIN(1, 15), PU1, 27 }, /* A15 */ 5430 { PIN_NUMBER('A', 18), PU0, 23 }, /* AVB_TD0 */
5427 { RCAR_GP_PIN(1, 14), PU1, 26 }, /* A14 */ 5431 { PIN_NUMBER('A', 19), PU0, 22 }, /* AVB_TXC */
5428 { RCAR_GP_PIN(1, 13), PU1, 25 }, /* A13 */ 5432 { PIN_NUMBER('A', 8), PU0, 21 }, /* AVB_TX_CTL */
5429 { RCAR_GP_PIN(1, 12), PU1, 24 }, /* A12 */ 5433 { PIN_NUMBER('B', 14), PU0, 20 }, /* AVB_RD3 */
5430 { RCAR_GP_PIN(1, 11), PU1, 23 }, /* A11 */ 5434 { PIN_NUMBER('A', 14), PU0, 19 }, /* AVB_RD2 */
5431 { RCAR_GP_PIN(1, 10), PU1, 22 }, /* A10 */ 5435 { PIN_NUMBER('B', 13), PU0, 18 }, /* AVB_RD1 */
5432 { RCAR_GP_PIN(1, 9), PU1, 21 }, /* A9 */ 5436 { PIN_NUMBER('A', 13), PU0, 17 }, /* AVB_RD0 */
5433 { RCAR_GP_PIN(1, 8), PU1, 20 }, /* A8 */ 5437 { PIN_NUMBER('B', 19), PU0, 16 }, /* AVB_RXC */
5434 { RCAR_GP_PIN(1, 7), PU1, 19 }, /* A7 */ 5438 { PIN_NUMBER('A', 16), PU0, 15 }, /* AVB_RX_CTL */
5435 { RCAR_GP_PIN(1, 6), PU1, 18 }, /* A6 */ 5439 { PIN_NUMBER('V', 7), PU0, 14 }, /* RPC_RESET# */
5436 { RCAR_GP_PIN(1, 5), PU1, 17 }, /* A5 */ 5440 { PIN_NUMBER('V', 6), PU0, 13 }, /* RPC_WP# */
5437 { RCAR_GP_PIN(1, 4), PU1, 16 }, /* A4 */ 5441 { PIN_NUMBER('Y', 7), PU0, 12 }, /* RPC_INT# */
5438 { RCAR_GP_PIN(1, 3), PU1, 15 }, /* A3 */ 5442 { PIN_NUMBER('V', 5), PU0, 11 }, /* QSPI1_SSL */
5439 { RCAR_GP_PIN(1, 2), PU1, 14 }, /* A2 */ 5443 { PIN_A_NUMBER('C', 3), PU0, 10 }, /* QSPI1_IO3 */
5440 { RCAR_GP_PIN(1, 1), PU1, 13 }, /* A1 */ 5444 { PIN_A_NUMBER('E', 4), PU0, 9 }, /* QSPI1_IO2 */
5441 { RCAR_GP_PIN(1, 0), PU1, 12 }, /* A0 */ 5445 { PIN_A_NUMBER('E', 5), PU0, 8 }, /* QSPI1_MISO_IO1 */
5442 { RCAR_GP_PIN(2, 8), PU1, 11 }, /* PWM2_A */ 5446 { PIN_A_NUMBER('C', 7), PU0, 7 }, /* QSPI1_MOSI_IO0 */
5443 { RCAR_GP_PIN(2, 7), PU1, 10 }, /* PWM1_A */ 5447 { PIN_NUMBER('V', 3), PU0, 6 }, /* QSPI1_SPCLK */
5444 { RCAR_GP_PIN(2, 6), PU1, 9 }, /* PWM0 */ 5448 { PIN_NUMBER('Y', 3), PU0, 5 }, /* QSPI0_SSL */
5445 { RCAR_GP_PIN(2, 5), PU1, 8 }, /* IRQ5 */ 5449 { PIN_A_NUMBER('B', 6), PU0, 4 }, /* QSPI0_IO3 */
5446 { RCAR_GP_PIN(2, 4), PU1, 7 }, /* IRQ4 */ 5450 { PIN_NUMBER('Y', 6), PU0, 3 }, /* QSPI0_IO2 */
5447 { RCAR_GP_PIN(2, 3), PU1, 6 }, /* IRQ3 */ 5451 { PIN_A_NUMBER('B', 4), PU0, 2 }, /* QSPI0_MISO_IO1 */
5448 { RCAR_GP_PIN(2, 2), PU1, 5 }, /* IRQ2 */ 5452 { PIN_A_NUMBER('C', 5), PU0, 1 }, /* QSPI0_MOSI_IO0 */
5449 { RCAR_GP_PIN(2, 1), PU1, 4 }, /* IRQ1 */ 5453 { PIN_NUMBER('W', 3), PU0, 0 }, /* QSPI0_SPCLK */
5450 { RCAR_GP_PIN(2, 0), PU1, 3 }, /* IRQ0 */ 5454
5451 { RCAR_GP_PIN(2, 14), PU1, 2 }, /* AVB_AVTP_CAPTURE_A */ 5455 { RCAR_GP_PIN(1, 19), PU1, 31 }, /* A19 */
5452 { RCAR_GP_PIN(2, 13), PU1, 1 }, /* AVB_AVTP_MATCH_A */ 5456 { RCAR_GP_PIN(1, 18), PU1, 30 }, /* A18 */
5453 { RCAR_GP_PIN(2, 12), PU1, 0 }, /* AVB_LINK */ 5457 { RCAR_GP_PIN(1, 17), PU1, 29 }, /* A17 */
5454 5458 { RCAR_GP_PIN(1, 16), PU1, 28 }, /* A16 */
5455 { RCAR_GP_PIN(7, 3), PU2, 29 }, /* HDMI1_CEC */ 5459 { RCAR_GP_PIN(1, 15), PU1, 27 }, /* A15 */
5456 { RCAR_GP_PIN(7, 2), PU2, 28 }, /* HDMI0_CEC */ 5460 { RCAR_GP_PIN(1, 14), PU1, 26 }, /* A14 */
5457 { RCAR_GP_PIN(7, 1), PU2, 27 }, /* AVS2 */ 5461 { RCAR_GP_PIN(1, 13), PU1, 25 }, /* A13 */
5458 { RCAR_GP_PIN(7, 0), PU2, 26 }, /* AVS1 */ 5462 { RCAR_GP_PIN(1, 12), PU1, 24 }, /* A12 */
5459 { RCAR_GP_PIN(0, 15), PU2, 25 }, /* D15 */ 5463 { RCAR_GP_PIN(1, 11), PU1, 23 }, /* A11 */
5460 { RCAR_GP_PIN(0, 14), PU2, 24 }, /* D14 */ 5464 { RCAR_GP_PIN(1, 10), PU1, 22 }, /* A10 */
5461 { RCAR_GP_PIN(0, 13), PU2, 23 }, /* D13 */ 5465 { RCAR_GP_PIN(1, 9), PU1, 21 }, /* A9 */
5462 { RCAR_GP_PIN(0, 12), PU2, 22 }, /* D12 */ 5466 { RCAR_GP_PIN(1, 8), PU1, 20 }, /* A8 */
5463 { RCAR_GP_PIN(0, 11), PU2, 21 }, /* D11 */ 5467 { RCAR_GP_PIN(1, 7), PU1, 19 }, /* A7 */
5464 { RCAR_GP_PIN(0, 10), PU2, 20 }, /* D10 */ 5468 { RCAR_GP_PIN(1, 6), PU1, 18 }, /* A6 */
5465 { RCAR_GP_PIN(0, 9), PU2, 19 }, /* D9 */ 5469 { RCAR_GP_PIN(1, 5), PU1, 17 }, /* A5 */
5466 { RCAR_GP_PIN(0, 8), PU2, 18 }, /* D8 */ 5470 { RCAR_GP_PIN(1, 4), PU1, 16 }, /* A4 */
5467 { RCAR_GP_PIN(0, 7), PU2, 17 }, /* D7 */ 5471 { RCAR_GP_PIN(1, 3), PU1, 15 }, /* A3 */
5468 { RCAR_GP_PIN(0, 6), PU2, 16 }, /* D6 */ 5472 { RCAR_GP_PIN(1, 2), PU1, 14 }, /* A2 */
5469 { RCAR_GP_PIN(0, 5), PU2, 15 }, /* D5 */ 5473 { RCAR_GP_PIN(1, 1), PU1, 13 }, /* A1 */
5470 { RCAR_GP_PIN(0, 4), PU2, 14 }, /* D4 */ 5474 { RCAR_GP_PIN(1, 0), PU1, 12 }, /* A0 */
5471 { RCAR_GP_PIN(0, 3), PU2, 13 }, /* D3 */ 5475 { RCAR_GP_PIN(2, 8), PU1, 11 }, /* PWM2_A */
5472 { RCAR_GP_PIN(0, 2), PU2, 12 }, /* D2 */ 5476 { RCAR_GP_PIN(2, 7), PU1, 10 }, /* PWM1_A */
5473 { RCAR_GP_PIN(0, 1), PU2, 11 }, /* D1 */ 5477 { RCAR_GP_PIN(2, 6), PU1, 9 }, /* PWM0 */
5474 { RCAR_GP_PIN(0, 0), PU2, 10 }, /* D0 */ 5478 { RCAR_GP_PIN(2, 5), PU1, 8 }, /* IRQ5 */
5475 { RCAR_GP_PIN(1, 27), PU2, 8 }, /* EX_WAIT0_A */ 5479 { RCAR_GP_PIN(2, 4), PU1, 7 }, /* IRQ4 */
5476 { RCAR_GP_PIN(1, 26), PU2, 7 }, /* WE1_N */ 5480 { RCAR_GP_PIN(2, 3), PU1, 6 }, /* IRQ3 */
5477 { RCAR_GP_PIN(1, 25), PU2, 6 }, /* WE0_N */ 5481 { RCAR_GP_PIN(2, 2), PU1, 5 }, /* IRQ2 */
5478 { RCAR_GP_PIN(1, 24), PU2, 5 }, /* RD_WR_N */ 5482 { RCAR_GP_PIN(2, 1), PU1, 4 }, /* IRQ1 */
5479 { RCAR_GP_PIN(1, 23), PU2, 4 }, /* RD_N */ 5483 { RCAR_GP_PIN(2, 0), PU1, 3 }, /* IRQ0 */
5480 { RCAR_GP_PIN(1, 22), PU2, 3 }, /* BS_N */ 5484 { RCAR_GP_PIN(2, 14), PU1, 2 }, /* AVB_AVTP_CAPTURE_A */
5481 { RCAR_GP_PIN(1, 21), PU2, 2 }, /* CS1_N_A26 */ 5485 { RCAR_GP_PIN(2, 13), PU1, 1 }, /* AVB_AVTP_MATCH_A */
5482 { RCAR_GP_PIN(1, 20), PU2, 1 }, /* CS0_N */ 5486 { RCAR_GP_PIN(2, 12), PU1, 0 }, /* AVB_LINK */
5483 5487
5484 { RCAR_GP_PIN(4, 9), PU3, 31 }, /* SD3_DAT0 */ 5488 { PIN_A_NUMBER('P', 8), PU2, 31 }, /* DU_DOTCLKIN1 */
5485 { RCAR_GP_PIN(4, 8), PU3, 30 }, /* SD3_CMD */ 5489 { PIN_A_NUMBER('P', 7), PU2, 30 }, /* DU_DOTCLKIN0 */
5486 { RCAR_GP_PIN(4, 7), PU3, 29 }, /* SD3_CLK */ 5490 { RCAR_GP_PIN(7, 3), PU2, 29 }, /* HDMI1_CEC */
5487 { RCAR_GP_PIN(4, 6), PU3, 28 }, /* SD2_DS */ 5491 { RCAR_GP_PIN(7, 2), PU2, 28 }, /* HDMI0_CEC */
5488 { RCAR_GP_PIN(4, 5), PU3, 27 }, /* SD2_DAT3 */ 5492 { RCAR_GP_PIN(7, 1), PU2, 27 }, /* AVS2 */
5489 { RCAR_GP_PIN(4, 4), PU3, 26 }, /* SD2_DAT2 */ 5493 { RCAR_GP_PIN(7, 0), PU2, 26 }, /* AVS1 */
5490 { RCAR_GP_PIN(4, 3), PU3, 25 }, /* SD2_DAT1 */ 5494 { RCAR_GP_PIN(0, 15), PU2, 25 }, /* D15 */
5491 { RCAR_GP_PIN(4, 2), PU3, 24 }, /* SD2_DAT0 */ 5495 { RCAR_GP_PIN(0, 14), PU2, 24 }, /* D14 */
5492 { RCAR_GP_PIN(4, 1), PU3, 23 }, /* SD2_CMD */ 5496 { RCAR_GP_PIN(0, 13), PU2, 23 }, /* D13 */
5493 { RCAR_GP_PIN(4, 0), PU3, 22 }, /* SD2_CLK */ 5497 { RCAR_GP_PIN(0, 12), PU2, 22 }, /* D12 */
5494 { RCAR_GP_PIN(3, 11), PU3, 21 }, /* SD1_DAT3 */ 5498 { RCAR_GP_PIN(0, 11), PU2, 21 }, /* D11 */
5495 { RCAR_GP_PIN(3, 10), PU3, 20 }, /* SD1_DAT2 */ 5499 { RCAR_GP_PIN(0, 10), PU2, 20 }, /* D10 */
5496 { RCAR_GP_PIN(3, 9), PU3, 19 }, /* SD1_DAT1 */ 5500 { RCAR_GP_PIN(0, 9), PU2, 19 }, /* D9 */
5497 { RCAR_GP_PIN(3, 8), PU3, 18 }, /* SD1_DAT0 */ 5501 { RCAR_GP_PIN(0, 8), PU2, 18 }, /* D8 */
5498 { RCAR_GP_PIN(3, 7), PU3, 17 }, /* SD1_CMD */ 5502 { RCAR_GP_PIN(0, 7), PU2, 17 }, /* D7 */
5499 { RCAR_GP_PIN(3, 6), PU3, 16 }, /* SD1_CLK */ 5503 { RCAR_GP_PIN(0, 6), PU2, 16 }, /* D6 */
5500 { RCAR_GP_PIN(3, 5), PU3, 15 }, /* SD0_DAT3 */ 5504 { RCAR_GP_PIN(0, 5), PU2, 15 }, /* D5 */
5501 { RCAR_GP_PIN(3, 4), PU3, 14 }, /* SD0_DAT2 */ 5505 { RCAR_GP_PIN(0, 4), PU2, 14 }, /* D4 */
5502 { RCAR_GP_PIN(3, 3), PU3, 13 }, /* SD0_DAT1 */ 5506 { RCAR_GP_PIN(0, 3), PU2, 13 }, /* D3 */
5503 { RCAR_GP_PIN(3, 2), PU3, 12 }, /* SD0_DAT0 */ 5507 { RCAR_GP_PIN(0, 2), PU2, 12 }, /* D2 */
5504 { RCAR_GP_PIN(3, 1), PU3, 11 }, /* SD0_CMD */ 5508 { RCAR_GP_PIN(0, 1), PU2, 11 }, /* D1 */
5505 { RCAR_GP_PIN(3, 0), PU3, 10 }, /* SD0_CLK */ 5509 { RCAR_GP_PIN(0, 0), PU2, 10 }, /* D0 */
5506 5510 { PIN_NUMBER('C', 1), PU2, 9 }, /* PRESETOUT# */
5507 { RCAR_GP_PIN(5, 19), PU4, 31 }, /* MSIOF0_SS1 */ 5511 { RCAR_GP_PIN(1, 27), PU2, 8 }, /* EX_WAIT0_A */
5508 { RCAR_GP_PIN(5, 18), PU4, 30 }, /* MSIOF0_SYNC */ 5512 { RCAR_GP_PIN(1, 26), PU2, 7 }, /* WE1_N */
5509 { RCAR_GP_PIN(5, 17), PU4, 29 }, /* MSIOF0_SCK */ 5513 { RCAR_GP_PIN(1, 25), PU2, 6 }, /* WE0_N */
5510 { RCAR_GP_PIN(5, 16), PU4, 28 }, /* HRTS0_N */ 5514 { RCAR_GP_PIN(1, 24), PU2, 5 }, /* RD_WR_N */
5511 { RCAR_GP_PIN(5, 15), PU4, 27 }, /* HCTS0_N */ 5515 { RCAR_GP_PIN(1, 23), PU2, 4 }, /* RD_N */
5512 { RCAR_GP_PIN(5, 14), PU4, 26 }, /* HTX0 */ 5516 { RCAR_GP_PIN(1, 22), PU2, 3 }, /* BS_N */
5513 { RCAR_GP_PIN(5, 13), PU4, 25 }, /* HRX0 */ 5517 { RCAR_GP_PIN(1, 21), PU2, 2 }, /* CS1_N_A26 */
5514 { RCAR_GP_PIN(5, 12), PU4, 24 }, /* HSCK0 */ 5518 { RCAR_GP_PIN(1, 20), PU2, 1 }, /* CS0_N */
5515 { RCAR_GP_PIN(5, 11), PU4, 23 }, /* RX2_A */ 5519 { PIN_NUMBER('F', 1), PU2, 0 }, /* CLKOUT */
5516 { RCAR_GP_PIN(5, 10), PU4, 22 }, /* TX2_A */ 5520
5517 { RCAR_GP_PIN(5, 9), PU4, 21 }, /* SCK2 */ 5521 { RCAR_GP_PIN(4, 9), PU3, 31 }, /* SD3_DAT0 */
5518 { RCAR_GP_PIN(5, 8), PU4, 20 }, /* RTS1_N_TANS */ 5522 { RCAR_GP_PIN(4, 8), PU3, 30 }, /* SD3_CMD */
5519 { RCAR_GP_PIN(5, 7), PU4, 19 }, /* CTS1_N */ 5523 { RCAR_GP_PIN(4, 7), PU3, 29 }, /* SD3_CLK */
5520 { RCAR_GP_PIN(5, 6), PU4, 18 }, /* TX1_A */ 5524 { RCAR_GP_PIN(4, 6), PU3, 28 }, /* SD2_DS */
5521 { RCAR_GP_PIN(5, 5), PU4, 17 }, /* RX1_A */ 5525 { RCAR_GP_PIN(4, 5), PU3, 27 }, /* SD2_DAT3 */
5522 { RCAR_GP_PIN(5, 4), PU4, 16 }, /* RTS0_N_TANS */ 5526 { RCAR_GP_PIN(4, 4), PU3, 26 }, /* SD2_DAT2 */
5523 { RCAR_GP_PIN(5, 3), PU4, 15 }, /* CTS0_N */ 5527 { RCAR_GP_PIN(4, 3), PU3, 25 }, /* SD2_DAT1 */
5524 { RCAR_GP_PIN(5, 2), PU4, 14 }, /* TX0 */ 5528 { RCAR_GP_PIN(4, 2), PU3, 24 }, /* SD2_DAT0 */
5525 { RCAR_GP_PIN(5, 1), PU4, 13 }, /* RX0 */ 5529 { RCAR_GP_PIN(4, 1), PU3, 23 }, /* SD2_CMD */
5526 { RCAR_GP_PIN(5, 0), PU4, 12 }, /* SCK0 */ 5530 { RCAR_GP_PIN(4, 0), PU3, 22 }, /* SD2_CLK */
5527 { RCAR_GP_PIN(3, 15), PU4, 11 }, /* SD1_WP */ 5531 { RCAR_GP_PIN(3, 11), PU3, 21 }, /* SD1_DAT3 */
5528 { RCAR_GP_PIN(3, 14), PU4, 10 }, /* SD1_CD */ 5532 { RCAR_GP_PIN(3, 10), PU3, 20 }, /* SD1_DAT2 */
5529 { RCAR_GP_PIN(3, 13), PU4, 9 }, /* SD0_WP */ 5533 { RCAR_GP_PIN(3, 9), PU3, 19 }, /* SD1_DAT1 */
5530 { RCAR_GP_PIN(3, 12), PU4, 8 }, /* SD0_CD */ 5534 { RCAR_GP_PIN(3, 8), PU3, 18 }, /* SD1_DAT0 */
5531 { RCAR_GP_PIN(4, 17), PU4, 7 }, /* SD3_DS */ 5535 { RCAR_GP_PIN(3, 7), PU3, 17 }, /* SD1_CMD */
5532 { RCAR_GP_PIN(4, 16), PU4, 6 }, /* SD3_DAT7 */ 5536 { RCAR_GP_PIN(3, 6), PU3, 16 }, /* SD1_CLK */
5533 { RCAR_GP_PIN(4, 15), PU4, 5 }, /* SD3_DAT6 */ 5537 { RCAR_GP_PIN(3, 5), PU3, 15 }, /* SD0_DAT3 */
5534 { RCAR_GP_PIN(4, 14), PU4, 4 }, /* SD3_DAT5 */ 5538 { RCAR_GP_PIN(3, 4), PU3, 14 }, /* SD0_DAT2 */
5535 { RCAR_GP_PIN(4, 13), PU4, 3 }, /* SD3_DAT4 */ 5539 { RCAR_GP_PIN(3, 3), PU3, 13 }, /* SD0_DAT1 */
5536 { RCAR_GP_PIN(4, 12), PU4, 2 }, /* SD3_DAT3 */ 5540 { RCAR_GP_PIN(3, 2), PU3, 12 }, /* SD0_DAT0 */
5537 { RCAR_GP_PIN(4, 11), PU4, 1 }, /* SD3_DAT2 */ 5541 { RCAR_GP_PIN(3, 1), PU3, 11 }, /* SD0_CMD */
5538 { RCAR_GP_PIN(4, 10), PU4, 0 }, /* SD3_DAT1 */ 5542 { RCAR_GP_PIN(3, 0), PU3, 10 }, /* SD0_CLK */
5539 5543 { PIN_A_NUMBER('T', 30), PU3, 9 }, /* ASEBRK */
5540 { RCAR_GP_PIN(6, 24), PU5, 31 }, /* USB0_PWEN */ 5544 /* bit 8 n/a */
5541 { RCAR_GP_PIN(6, 23), PU5, 30 }, /* AUDIO_CLKB_B */ 5545 { PIN_A_NUMBER('R', 29), PU3, 7 }, /* TDI */
5542 { RCAR_GP_PIN(6, 22), PU5, 29 }, /* AUDIO_CLKA_A */ 5546 { PIN_A_NUMBER('R', 30), PU3, 6 }, /* TMS */
5543 { RCAR_GP_PIN(6, 21), PU5, 28 }, /* SSI_SDATA9_A */ 5547 { PIN_A_NUMBER('T', 27), PU3, 5 }, /* TCK */
5544 { RCAR_GP_PIN(6, 20), PU5, 27 }, /* SSI_SDATA8 */ 5548 { PIN_A_NUMBER('R', 26), PU3, 4 }, /* TRST# */
5545 { RCAR_GP_PIN(6, 19), PU5, 26 }, /* SSI_SDATA7 */ 5549 { PIN_A_NUMBER('D', 39), PU3, 3 }, /* EXTALR*/
5546 { RCAR_GP_PIN(6, 18), PU5, 25 }, /* SSI_WS78 */ 5550 { PIN_A_NUMBER('D', 38), PU3, 2 }, /* FSCLKST# */
5547 { RCAR_GP_PIN(6, 17), PU5, 24 }, /* SSI_SCK78 */ 5551 { PIN_A_NUMBER('R', 8), PU3, 1 }, /* DU_DOTCLKIN3 */
5548 { RCAR_GP_PIN(6, 16), PU5, 23 }, /* SSI_SDATA6 */ 5552 { PIN_A_NUMBER('R', 7), PU3, 0 }, /* DU_DOTCLKIN2 */
5549 { RCAR_GP_PIN(6, 15), PU5, 22 }, /* SSI_WS6 */ 5553
5550 { RCAR_GP_PIN(6, 14), PU5, 21 }, /* SSI_SCK6 */ 5554 { RCAR_GP_PIN(5, 19), PU4, 31 }, /* MSIOF0_SS1 */
5551 { RCAR_GP_PIN(6, 13), PU5, 20 }, /* SSI_SDATA5 */ 5555 { RCAR_GP_PIN(5, 18), PU4, 30 }, /* MSIOF0_SYNC */
5552 { RCAR_GP_PIN(6, 12), PU5, 19 }, /* SSI_WS5 */ 5556 { RCAR_GP_PIN(5, 17), PU4, 29 }, /* MSIOF0_SCK */
5553 { RCAR_GP_PIN(6, 11), PU5, 18 }, /* SSI_SCK5 */ 5557 { RCAR_GP_PIN(5, 16), PU4, 28 }, /* HRTS0_N */
5554 { RCAR_GP_PIN(6, 10), PU5, 17 }, /* SSI_SDATA4 */ 5558 { RCAR_GP_PIN(5, 15), PU4, 27 }, /* HCTS0_N */
5555 { RCAR_GP_PIN(6, 9), PU5, 16 }, /* SSI_WS4 */ 5559 { RCAR_GP_PIN(5, 14), PU4, 26 }, /* HTX0 */
5556 { RCAR_GP_PIN(6, 8), PU5, 15 }, /* SSI_SCK4 */ 5560 { RCAR_GP_PIN(5, 13), PU4, 25 }, /* HRX0 */
5557 { RCAR_GP_PIN(6, 7), PU5, 14 }, /* SSI_SDATA3 */ 5561 { RCAR_GP_PIN(5, 12), PU4, 24 }, /* HSCK0 */
5558 { RCAR_GP_PIN(6, 6), PU5, 13 }, /* SSI_WS34 */ 5562 { RCAR_GP_PIN(5, 11), PU4, 23 }, /* RX2_A */
5559 { RCAR_GP_PIN(6, 5), PU5, 12 }, /* SSI_SCK34 */ 5563 { RCAR_GP_PIN(5, 10), PU4, 22 }, /* TX2_A */
5560 { RCAR_GP_PIN(6, 4), PU5, 11 }, /* SSI_SDATA2_A */ 5564 { RCAR_GP_PIN(5, 9), PU4, 21 }, /* SCK2 */
5561 { RCAR_GP_PIN(6, 3), PU5, 10 }, /* SSI_SDATA1_A */ 5565 { RCAR_GP_PIN(5, 8), PU4, 20 }, /* RTS1_N_TANS */
5562 { RCAR_GP_PIN(6, 2), PU5, 9 }, /* SSI_SDATA0 */ 5566 { RCAR_GP_PIN(5, 7), PU4, 19 }, /* CTS1_N */
5563 { RCAR_GP_PIN(6, 1), PU5, 8 }, /* SSI_WS01239 */ 5567 { RCAR_GP_PIN(5, 6), PU4, 18 }, /* TX1_A */
5564 { RCAR_GP_PIN(6, 0), PU5, 7 }, /* SSI_SCK01239 */ 5568 { RCAR_GP_PIN(5, 5), PU4, 17 }, /* RX1_A */
5565 { RCAR_GP_PIN(5, 25), PU5, 5 }, /* MLB_DAT */ 5569 { RCAR_GP_PIN(5, 4), PU4, 16 }, /* RTS0_N_TANS */
5566 { RCAR_GP_PIN(5, 24), PU5, 4 }, /* MLB_SIG */ 5570 { RCAR_GP_PIN(5, 3), PU4, 15 }, /* CTS0_N */
5567 { RCAR_GP_PIN(5, 23), PU5, 3 }, /* MLB_CLK */ 5571 { RCAR_GP_PIN(5, 2), PU4, 14 }, /* TX0 */
5568 { RCAR_GP_PIN(5, 22), PU5, 2 }, /* MSIOF0_RXD */ 5572 { RCAR_GP_PIN(5, 1), PU4, 13 }, /* RX0 */
5569 { RCAR_GP_PIN(5, 21), PU5, 1 }, /* MSIOF0_SS2 */ 5573 { RCAR_GP_PIN(5, 0), PU4, 12 }, /* SCK0 */
5570 { RCAR_GP_PIN(5, 20), PU5, 0 }, /* MSIOF0_TXD */ 5574 { RCAR_GP_PIN(3, 15), PU4, 11 }, /* SD1_WP */
5571 5575 { RCAR_GP_PIN(3, 14), PU4, 10 }, /* SD1_CD */
5572 { RCAR_GP_PIN(6, 31), PU6, 6 }, /* USB31_OVC */ 5576 { RCAR_GP_PIN(3, 13), PU4, 9 }, /* SD0_WP */
5573 { RCAR_GP_PIN(6, 30), PU6, 5 }, /* USB31_PWEN */ 5577 { RCAR_GP_PIN(3, 12), PU4, 8 }, /* SD0_CD */
5574 { RCAR_GP_PIN(6, 29), PU6, 4 }, /* USB30_OVC */ 5578 { RCAR_GP_PIN(4, 17), PU4, 7 }, /* SD3_DS */
5575 { RCAR_GP_PIN(6, 28), PU6, 3 }, /* USB30_PWEN */ 5579 { RCAR_GP_PIN(4, 16), PU4, 6 }, /* SD3_DAT7 */
5576 { RCAR_GP_PIN(6, 27), PU6, 2 }, /* USB1_OVC */ 5580 { RCAR_GP_PIN(4, 15), PU4, 5 }, /* SD3_DAT6 */
5577 { RCAR_GP_PIN(6, 26), PU6, 1 }, /* USB1_PWEN */ 5581 { RCAR_GP_PIN(4, 14), PU4, 4 }, /* SD3_DAT5 */
5578 { RCAR_GP_PIN(6, 25), PU6, 0 }, /* USB0_OVC */ 5582 { RCAR_GP_PIN(4, 13), PU4, 3 }, /* SD3_DAT4 */
5583 { RCAR_GP_PIN(4, 12), PU4, 2 }, /* SD3_DAT3 */
5584 { RCAR_GP_PIN(4, 11), PU4, 1 }, /* SD3_DAT2 */
5585 { RCAR_GP_PIN(4, 10), PU4, 0 }, /* SD3_DAT1 */
5586
5587 { RCAR_GP_PIN(6, 24), PU5, 31 }, /* USB0_PWEN */
5588 { RCAR_GP_PIN(6, 23), PU5, 30 }, /* AUDIO_CLKB_B */
5589 { RCAR_GP_PIN(6, 22), PU5, 29 }, /* AUDIO_CLKA_A */
5590 { RCAR_GP_PIN(6, 21), PU5, 28 }, /* SSI_SDATA9_A */
5591 { RCAR_GP_PIN(6, 20), PU5, 27 }, /* SSI_SDATA8 */
5592 { RCAR_GP_PIN(6, 19), PU5, 26 }, /* SSI_SDATA7 */
5593 { RCAR_GP_PIN(6, 18), PU5, 25 }, /* SSI_WS78 */
5594 { RCAR_GP_PIN(6, 17), PU5, 24 }, /* SSI_SCK78 */
5595 { RCAR_GP_PIN(6, 16), PU5, 23 }, /* SSI_SDATA6 */
5596 { RCAR_GP_PIN(6, 15), PU5, 22 }, /* SSI_WS6 */
5597 { RCAR_GP_PIN(6, 14), PU5, 21 }, /* SSI_SCK6 */
5598 { RCAR_GP_PIN(6, 13), PU5, 20 }, /* SSI_SDATA5 */
5599 { RCAR_GP_PIN(6, 12), PU5, 19 }, /* SSI_WS5 */
5600 { RCAR_GP_PIN(6, 11), PU5, 18 }, /* SSI_SCK5 */
5601 { RCAR_GP_PIN(6, 10), PU5, 17 }, /* SSI_SDATA4 */
5602 { RCAR_GP_PIN(6, 9), PU5, 16 }, /* SSI_WS4 */
5603 { RCAR_GP_PIN(6, 8), PU5, 15 }, /* SSI_SCK4 */
5604 { RCAR_GP_PIN(6, 7), PU5, 14 }, /* SSI_SDATA3 */
5605 { RCAR_GP_PIN(6, 6), PU5, 13 }, /* SSI_WS34 */
5606 { RCAR_GP_PIN(6, 5), PU5, 12 }, /* SSI_SCK34 */
5607 { RCAR_GP_PIN(6, 4), PU5, 11 }, /* SSI_SDATA2_A */
5608 { RCAR_GP_PIN(6, 3), PU5, 10 }, /* SSI_SDATA1_A */
5609 { RCAR_GP_PIN(6, 2), PU5, 9 }, /* SSI_SDATA0 */
5610 { RCAR_GP_PIN(6, 1), PU5, 8 }, /* SSI_WS01239 */
5611 { RCAR_GP_PIN(6, 0), PU5, 7 }, /* SSI_SCK01239 */
5612 { PIN_NUMBER('H', 37), PU5, 6 }, /* MLB_REF */
5613 { RCAR_GP_PIN(5, 25), PU5, 5 }, /* MLB_DAT */
5614 { RCAR_GP_PIN(5, 24), PU5, 4 }, /* MLB_SIG */
5615 { RCAR_GP_PIN(5, 23), PU5, 3 }, /* MLB_CLK */
5616 { RCAR_GP_PIN(5, 22), PU5, 2 }, /* MSIOF0_RXD */
5617 { RCAR_GP_PIN(5, 21), PU5, 1 }, /* MSIOF0_SS2 */
5618 { RCAR_GP_PIN(5, 20), PU5, 0 }, /* MSIOF0_TXD */
5619
5620 { RCAR_GP_PIN(6, 31), PU6, 6 }, /* USB31_OVC */
5621 { RCAR_GP_PIN(6, 30), PU6, 5 }, /* USB31_PWEN */
5622 { RCAR_GP_PIN(6, 29), PU6, 4 }, /* USB30_OVC */
5623 { RCAR_GP_PIN(6, 28), PU6, 3 }, /* USB30_PWEN */
5624 { RCAR_GP_PIN(6, 27), PU6, 2 }, /* USB1_OVC */
5625 { RCAR_GP_PIN(6, 26), PU6, 1 }, /* USB1_PWEN */
5626 { RCAR_GP_PIN(6, 25), PU6, 0 }, /* USB0_OVC */
5579}; 5627};
5580 5628
5581static unsigned int r8a7795_pinmux_get_bias(struct sh_pfc *pfc, 5629static unsigned int r8a7795_pinmux_get_bias(struct sh_pfc *pfc,
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-24 13:50:39 -0400