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authorNiklas Söderlund <niklas.soderlund+renesas@ragnatech.se>2016-11-17 10:09:20 -0500
committerGeert Uytterhoeven <geert+renesas@glider.be>2016-12-27 04:57:38 -0500
commit2d40bd24274d257796291804a82a0b07564a11f1 (patch)
tree934cbacfd555f089267f5c9dcf321d840ab743aa
parent9e35d6fa825c02bdd00c24cb32299355702130bd (diff)
pinctrl: sh-pfc: r8a7796: Add bias pinconf support
Implements pull-up and pull-down. On this SoC there is no simple mapping of GP pins to bias register bits, so we need a table. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7796.c354
1 files changed, 315 insertions, 39 deletions
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
index 21599ad891f0..e0fe3753963d 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
@@ -19,7 +19,9 @@
19#include "core.h" 19#include "core.h"
20#include "sh_pfc.h" 20#include "sh_pfc.h"
21 21
22#define CFG_FLAGS SH_PFC_PIN_CFG_DRIVE_STRENGTH 22#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \
23 SH_PFC_PIN_CFG_PULL_UP | \
24 SH_PFC_PIN_CFG_PULL_DOWN)
23 25
24#define CPU_ALL_PORT(fn, sfx) \ 26#define CPU_ALL_PORT(fn, sfx) \
25 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \ 27 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
@@ -558,7 +560,7 @@ MOD_SEL0_2 MOD_SEL1_2 \
558 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \ 560 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
559 FM(PRESETOUT) \ 561 FM(PRESETOUT) \
560 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) \ 562 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) \
561 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) 563 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
562 564
563enum { 565enum {
564 PINMUX_RESERVED = 0, 566 PINMUX_RESERVED = 0,
@@ -1536,44 +1538,48 @@ static const struct sh_pfc_pin pinmux_pins[] = {
1536 * number for each pin. To this end use the pin layout from 1538 * number for each pin. To this end use the pin layout from
1537 * R-Car M3SiP to calculate a unique number for each pin. 1539 * R-Car M3SiP to calculate a unique number for each pin.
1538 */ 1540 */
1539 SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, SH_PFC_PIN_CFG_DRIVE_STRENGTH), 1541 SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, CFG_FLAGS),
1540 SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, SH_PFC_PIN_CFG_DRIVE_STRENGTH), 1542 SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, CFG_FLAGS),
1541 SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, SH_PFC_PIN_CFG_DRIVE_STRENGTH), 1543 SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS),
1542 SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, SH_PFC_PIN_CFG_DRIVE_STRENGTH), 1544 SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS),
1543 SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, SH_PFC_PIN_CFG_DRIVE_STRENGTH), 1545 SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS),
1544 SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, SH_PFC_PIN_CFG_DRIVE_STRENGTH), 1546 SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS),
1545 SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, SH_PFC_PIN_CFG_DRIVE_STRENGTH), 1547 SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS),
1546 SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, SH_PFC_PIN_CFG_DRIVE_STRENGTH), 1548 SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS),
1547 SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, SH_PFC_PIN_CFG_DRIVE_STRENGTH), 1549 SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS),
1548 SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, SH_PFC_PIN_CFG_DRIVE_STRENGTH), 1550 SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS),
1549 SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, SH_PFC_PIN_CFG_DRIVE_STRENGTH), 1551 SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS),
1550 SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, SH_PFC_PIN_CFG_DRIVE_STRENGTH), 1552 SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS),
1551 SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, SH_PFC_PIN_CFG_DRIVE_STRENGTH), 1553 SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS),
1552 SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, SH_PFC_PIN_CFG_DRIVE_STRENGTH), 1554 SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS),
1553 SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, SH_PFC_PIN_CFG_DRIVE_STRENGTH), 1555 SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, CFG_FLAGS),
1554 SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, SH_PFC_PIN_CFG_DRIVE_STRENGTH), 1556 SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS),
1555 SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, SH_PFC_PIN_CFG_DRIVE_STRENGTH), 1557 SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, CFG_FLAGS),
1556 SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, SH_PFC_PIN_CFG_DRIVE_STRENGTH), 1558 SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, CFG_FLAGS),
1557 SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, SH_PFC_PIN_CFG_DRIVE_STRENGTH), 1559 SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, CFG_FLAGS),
1558 SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, SH_PFC_PIN_CFG_DRIVE_STRENGTH), 1560 SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, CFG_FLAGS),
1559 SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, SH_PFC_PIN_CFG_DRIVE_STRENGTH), 1561 SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, CFG_FLAGS),
1560 SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, SH_PFC_PIN_CFG_DRIVE_STRENGTH), 1562 SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, CFG_FLAGS),
1561 SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, SH_PFC_PIN_CFG_DRIVE_STRENGTH), 1563 SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, CFG_FLAGS),
1562 SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, SH_PFC_PIN_CFG_DRIVE_STRENGTH), 1564 SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, CFG_FLAGS),
1563 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, SH_PFC_PIN_CFG_DRIVE_STRENGTH), 1565 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, CFG_FLAGS),
1564 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, SH_PFC_PIN_CFG_DRIVE_STRENGTH), 1566 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, CFG_FLAGS),
1565 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, SH_PFC_PIN_CFG_DRIVE_STRENGTH), 1567 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, CFG_FLAGS),
1566 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, SH_PFC_PIN_CFG_DRIVE_STRENGTH), 1568 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, CFG_FLAGS),
1567 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, SH_PFC_PIN_CFG_DRIVE_STRENGTH), 1569 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, CFG_FLAGS),
1568 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST, SH_PFC_PIN_CFG_DRIVE_STRENGTH), 1570 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST, CFG_FLAGS),
1569 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, SH_PFC_PIN_CFG_DRIVE_STRENGTH), 1571 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1570 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, SH_PFC_PIN_CFG_DRIVE_STRENGTH), 1572 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, CFG_FLAGS),
1571 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, SH_PFC_PIN_CFG_DRIVE_STRENGTH), 1573 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, CFG_FLAGS),
1572 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, SH_PFC_PIN_CFG_DRIVE_STRENGTH), 1574 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, CFG_FLAGS),
1573 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN2, SH_PFC_PIN_CFG_DRIVE_STRENGTH), 1575 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, CFG_FLAGS),
1574 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, SH_PFC_PIN_CFG_DRIVE_STRENGTH), 1576 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN2, CFG_FLAGS),
1577 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1578 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1579 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS),
1580 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1575 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH), 1581 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1576 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, SH_PFC_PIN_CFG_DRIVE_STRENGTH), 1582 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
1577}; 1583};
1578 1584
1579/* - EtherAVB --------------------------------------------------------------- */ 1585/* - EtherAVB --------------------------------------------------------------- */
@@ -3536,8 +3542,278 @@ static int r8a7796_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *poc
3536 return bit; 3542 return bit;
3537} 3543}
3538 3544
3545#define PUEN 0xe6060400
3546#define PUD 0xe6060440
3547
3548#define PU0 0x00
3549#define PU1 0x04
3550#define PU2 0x08
3551#define PU3 0x0c
3552#define PU4 0x10
3553#define PU5 0x14
3554#define PU6 0x18
3555
3556static const struct sh_pfc_bias_info bias_info[] = {
3557 { RCAR_GP_PIN(2, 11), PU0, 31 }, /* AVB_PHY_INT */
3558 { RCAR_GP_PIN(2, 10), PU0, 30 }, /* AVB_MAGIC */
3559 { RCAR_GP_PIN(2, 9), PU0, 29 }, /* AVB_MDC */
3560 { PIN_NUMBER('A', 9), PU0, 28 }, /* AVB_MDIO */
3561 { PIN_NUMBER('A', 12), PU0, 27 }, /* AVB_TXCREFCLK */
3562 { PIN_NUMBER('B', 17), PU0, 26 }, /* AVB_TD3 */
3563 { PIN_NUMBER('A', 17), PU0, 25 }, /* AVB_TD2 */
3564 { PIN_NUMBER('B', 18), PU0, 24 }, /* AVB_TD1 */
3565 { PIN_NUMBER('A', 18), PU0, 23 }, /* AVB_TD0 */
3566 { PIN_NUMBER('A', 19), PU0, 22 }, /* AVB_TXC */
3567 { PIN_NUMBER('A', 8), PU0, 21 }, /* AVB_TX_CTL */
3568 { PIN_NUMBER('B', 14), PU0, 20 }, /* AVB_RD3 */
3569 { PIN_NUMBER('A', 14), PU0, 19 }, /* AVB_RD2 */
3570 { PIN_NUMBER('B', 13), PU0, 18 }, /* AVB_RD1 */
3571 { PIN_NUMBER('A', 13), PU0, 17 }, /* AVB_RD0 */
3572 { PIN_NUMBER('B', 19), PU0, 16 }, /* AVB_RXC */
3573 { PIN_NUMBER('A', 16), PU0, 15 }, /* AVB_RX_CTL */
3574 { PIN_NUMBER('V', 7), PU0, 14 }, /* RPC_RESET# */
3575 { PIN_NUMBER('V', 6), PU0, 13 }, /* RPC_WP# */
3576 { PIN_NUMBER('Y', 7), PU0, 12 }, /* RPC_INT# */
3577 { PIN_NUMBER('V', 5), PU0, 11 }, /* QSPI1_SSL */
3578 { PIN_A_NUMBER('C', 3), PU0, 10 }, /* QSPI1_IO3 */
3579 { PIN_A_NUMBER('E', 4), PU0, 9 }, /* QSPI1_IO2 */
3580 { PIN_A_NUMBER('E', 5), PU0, 8 }, /* QSPI1_MISO_IO1 */
3581 { PIN_A_NUMBER('C', 7), PU0, 7 }, /* QSPI1_MOSI_IO0 */
3582 { PIN_NUMBER('V', 3), PU0, 6 }, /* QSPI1_SPCLK */
3583 { PIN_NUMBER('Y', 3), PU0, 5 }, /* QSPI0_SSL */
3584 { PIN_A_NUMBER('B', 6), PU0, 4 }, /* QSPI0_IO3 */
3585 { PIN_NUMBER('Y', 6), PU0, 3 }, /* QSPI0_IO2 */
3586 { PIN_A_NUMBER('B', 4), PU0, 2 }, /* QSPI0_MISO_IO1 */
3587 { PIN_A_NUMBER('C', 5), PU0, 1 }, /* QSPI0_MOSI_IO0 */
3588 { PIN_NUMBER('W', 3), PU0, 0 }, /* QSPI0_SPCLK */
3589
3590 { RCAR_GP_PIN(1, 19), PU1, 31 }, /* A19 */
3591 { RCAR_GP_PIN(1, 18), PU1, 30 }, /* A18 */
3592 { RCAR_GP_PIN(1, 17), PU1, 29 }, /* A17 */
3593 { RCAR_GP_PIN(1, 16), PU1, 28 }, /* A16 */
3594 { RCAR_GP_PIN(1, 15), PU1, 27 }, /* A15 */
3595 { RCAR_GP_PIN(1, 14), PU1, 26 }, /* A14 */
3596 { RCAR_GP_PIN(1, 13), PU1, 25 }, /* A13 */
3597 { RCAR_GP_PIN(1, 12), PU1, 24 }, /* A12 */
3598 { RCAR_GP_PIN(1, 11), PU1, 23 }, /* A11 */
3599 { RCAR_GP_PIN(1, 10), PU1, 22 }, /* A10 */
3600 { RCAR_GP_PIN(1, 9), PU1, 21 }, /* A9 */
3601 { RCAR_GP_PIN(1, 8), PU1, 20 }, /* A8 */
3602 { RCAR_GP_PIN(1, 7), PU1, 19 }, /* A7 */
3603 { RCAR_GP_PIN(1, 6), PU1, 18 }, /* A6 */
3604 { RCAR_GP_PIN(1, 5), PU1, 17 }, /* A5 */
3605 { RCAR_GP_PIN(1, 4), PU1, 16 }, /* A4 */
3606 { RCAR_GP_PIN(1, 3), PU1, 15 }, /* A3 */
3607 { RCAR_GP_PIN(1, 2), PU1, 14 }, /* A2 */
3608 { RCAR_GP_PIN(1, 1), PU1, 13 }, /* A1 */
3609 { RCAR_GP_PIN(1, 0), PU1, 12 }, /* A0 */
3610 { RCAR_GP_PIN(2, 8), PU1, 11 }, /* PWM2_A */
3611 { RCAR_GP_PIN(2, 7), PU1, 10 }, /* PWM1_A */
3612 { RCAR_GP_PIN(2, 6), PU1, 9 }, /* PWM0 */
3613 { RCAR_GP_PIN(2, 5), PU1, 8 }, /* IRQ5 */
3614 { RCAR_GP_PIN(2, 4), PU1, 7 }, /* IRQ4 */
3615 { RCAR_GP_PIN(2, 3), PU1, 6 }, /* IRQ3 */
3616 { RCAR_GP_PIN(2, 2), PU1, 5 }, /* IRQ2 */
3617 { RCAR_GP_PIN(2, 1), PU1, 4 }, /* IRQ1 */
3618 { RCAR_GP_PIN(2, 0), PU1, 3 }, /* IRQ0 */
3619 { RCAR_GP_PIN(2, 14), PU1, 2 }, /* AVB_AVTP_CAPTURE_A */
3620 { RCAR_GP_PIN(2, 13), PU1, 1 }, /* AVB_AVTP_MATCH_A */
3621 { RCAR_GP_PIN(2, 12), PU1, 0 }, /* AVB_LINK */
3622
3623 { PIN_A_NUMBER('P', 8), PU2, 31 }, /* DU_DOTCLKIN1 */
3624 { PIN_A_NUMBER('P', 7), PU2, 30 }, /* DU_DOTCLKIN0 */
3625 { RCAR_GP_PIN(7, 3), PU2, 29 }, /* GP7_03 */
3626 { RCAR_GP_PIN(7, 2), PU2, 28 }, /* HDMI0_CEC */
3627 { RCAR_GP_PIN(7, 1), PU2, 27 }, /* AVS2 */
3628 { RCAR_GP_PIN(7, 0), PU2, 26 }, /* AVS1 */
3629 { RCAR_GP_PIN(0, 15), PU2, 25 }, /* D15 */
3630 { RCAR_GP_PIN(0, 14), PU2, 24 }, /* D14 */
3631 { RCAR_GP_PIN(0, 13), PU2, 23 }, /* D13 */
3632 { RCAR_GP_PIN(0, 12), PU2, 22 }, /* D12 */
3633 { RCAR_GP_PIN(0, 11), PU2, 21 }, /* D11 */
3634 { RCAR_GP_PIN(0, 10), PU2, 20 }, /* D10 */
3635 { RCAR_GP_PIN(0, 9), PU2, 19 }, /* D9 */
3636 { RCAR_GP_PIN(0, 8), PU2, 18 }, /* D8 */
3637 { RCAR_GP_PIN(0, 7), PU2, 17 }, /* D7 */
3638 { RCAR_GP_PIN(0, 6), PU2, 16 }, /* D6 */
3639 { RCAR_GP_PIN(0, 5), PU2, 15 }, /* D5 */
3640 { RCAR_GP_PIN(0, 4), PU2, 14 }, /* D4 */
3641 { RCAR_GP_PIN(0, 3), PU2, 13 }, /* D3 */
3642 { RCAR_GP_PIN(0, 2), PU2, 12 }, /* D2 */
3643 { RCAR_GP_PIN(0, 1), PU2, 11 }, /* D1 */
3644 { RCAR_GP_PIN(0, 0), PU2, 10 }, /* D0 */
3645 { PIN_NUMBER('C', 1), PU2, 9 }, /* PRESETOUT# */
3646 { RCAR_GP_PIN(1, 27), PU2, 8 }, /* EX_WAIT0_A */
3647 { RCAR_GP_PIN(1, 26), PU2, 7 }, /* WE1_N */
3648 { RCAR_GP_PIN(1, 25), PU2, 6 }, /* WE0_N */
3649 { RCAR_GP_PIN(1, 24), PU2, 5 }, /* RD_WR_N */
3650 { RCAR_GP_PIN(1, 23), PU2, 4 }, /* RD_N */
3651 { RCAR_GP_PIN(1, 22), PU2, 3 }, /* BS_N */
3652 { RCAR_GP_PIN(1, 21), PU2, 2 }, /* CS1_N_A26 */
3653 { RCAR_GP_PIN(1, 20), PU2, 1 }, /* CS0_N */
3654 { RCAR_GP_PIN(1, 28), PU2, 0 }, /* CLKOUT */
3655
3656 { RCAR_GP_PIN(4, 9), PU3, 31 }, /* SD3_DAT0 */
3657 { RCAR_GP_PIN(4, 8), PU3, 30 }, /* SD3_CMD */
3658 { RCAR_GP_PIN(4, 7), PU3, 29 }, /* SD3_CLK */
3659 { RCAR_GP_PIN(4, 6), PU3, 28 }, /* SD2_DS */
3660 { RCAR_GP_PIN(4, 5), PU3, 27 }, /* SD2_DAT3 */
3661 { RCAR_GP_PIN(4, 4), PU3, 26 }, /* SD2_DAT2 */
3662 { RCAR_GP_PIN(4, 3), PU3, 25 }, /* SD2_DAT1 */
3663 { RCAR_GP_PIN(4, 2), PU3, 24 }, /* SD2_DAT0 */
3664 { RCAR_GP_PIN(4, 1), PU3, 23 }, /* SD2_CMD */
3665 { RCAR_GP_PIN(4, 0), PU3, 22 }, /* SD2_CLK */
3666 { RCAR_GP_PIN(3, 11), PU3, 21 }, /* SD1_DAT3 */
3667 { RCAR_GP_PIN(3, 10), PU3, 20 }, /* SD1_DAT2 */
3668 { RCAR_GP_PIN(3, 9), PU3, 19 }, /* SD1_DAT1 */
3669 { RCAR_GP_PIN(3, 8), PU3, 18 }, /* SD1_DAT0 */
3670 { RCAR_GP_PIN(3, 7), PU3, 17 }, /* SD1_CMD */
3671 { RCAR_GP_PIN(3, 6), PU3, 16 }, /* SD1_CLK */
3672 { RCAR_GP_PIN(3, 5), PU3, 15 }, /* SD0_DAT3 */
3673 { RCAR_GP_PIN(3, 4), PU3, 14 }, /* SD0_DAT2 */
3674 { RCAR_GP_PIN(3, 3), PU3, 13 }, /* SD0_DAT1 */
3675 { RCAR_GP_PIN(3, 2), PU3, 12 }, /* SD0_DAT0 */
3676 { RCAR_GP_PIN(3, 1), PU3, 11 }, /* SD0_CMD */
3677 { RCAR_GP_PIN(3, 0), PU3, 10 }, /* SD0_CLK */
3678 { PIN_A_NUMBER('T', 30), PU3, 9 }, /* ASEBRK */
3679 /* bit 8 n/a */
3680 { PIN_A_NUMBER('R', 29), PU3, 7 }, /* TDI */
3681 { PIN_A_NUMBER('R', 30), PU3, 6 }, /* TMS */
3682 { PIN_A_NUMBER('T', 27), PU3, 5 }, /* TCK */
3683 { PIN_A_NUMBER('R', 26), PU3, 4 }, /* TRST# */
3684 { PIN_A_NUMBER('D', 39), PU3, 3 }, /* EXTALR*/
3685 { PIN_A_NUMBER('D', 38), PU3, 2 }, /* FSCLKST */
3686 /* bit 1 n/a on M3*/
3687 { PIN_A_NUMBER('R', 8), PU3, 0 }, /* DU_DOTCLKIN2 */
3688
3689 { RCAR_GP_PIN(5, 19), PU4, 31 }, /* MSIOF0_SS1 */
3690 { RCAR_GP_PIN(5, 18), PU4, 30 }, /* MSIOF0_SYNC */
3691 { RCAR_GP_PIN(5, 17), PU4, 29 }, /* MSIOF0_SCK */
3692 { RCAR_GP_PIN(5, 16), PU4, 28 }, /* HRTS0_N */
3693 { RCAR_GP_PIN(5, 15), PU4, 27 }, /* HCTS0_N */
3694 { RCAR_GP_PIN(5, 14), PU4, 26 }, /* HTX0 */
3695 { RCAR_GP_PIN(5, 13), PU4, 25 }, /* HRX0 */
3696 { RCAR_GP_PIN(5, 12), PU4, 24 }, /* HSCK0 */
3697 { RCAR_GP_PIN(5, 11), PU4, 23 }, /* RX2_A */
3698 { RCAR_GP_PIN(5, 10), PU4, 22 }, /* TX2_A */
3699 { RCAR_GP_PIN(5, 9), PU4, 21 }, /* SCK2 */
3700 { RCAR_GP_PIN(5, 8), PU4, 20 }, /* RTS1_N_TANS */
3701 { RCAR_GP_PIN(5, 7), PU4, 19 }, /* CTS1_N */
3702 { RCAR_GP_PIN(5, 6), PU4, 18 }, /* TX1_A */
3703 { RCAR_GP_PIN(5, 5), PU4, 17 }, /* RX1_A */
3704 { RCAR_GP_PIN(5, 4), PU4, 16 }, /* RTS0_N_TANS */
3705 { RCAR_GP_PIN(5, 3), PU4, 15 }, /* CTS0_N */
3706 { RCAR_GP_PIN(5, 2), PU4, 14 }, /* TX0 */
3707 { RCAR_GP_PIN(5, 1), PU4, 13 }, /* RX0 */
3708 { RCAR_GP_PIN(5, 0), PU4, 12 }, /* SCK0 */
3709 { RCAR_GP_PIN(3, 15), PU4, 11 }, /* SD1_WP */
3710 { RCAR_GP_PIN(3, 14), PU4, 10 }, /* SD1_CD */
3711 { RCAR_GP_PIN(3, 13), PU4, 9 }, /* SD0_WP */
3712 { RCAR_GP_PIN(3, 12), PU4, 8 }, /* SD0_CD */
3713 { RCAR_GP_PIN(4, 17), PU4, 7 }, /* SD3_DS */
3714 { RCAR_GP_PIN(4, 16), PU4, 6 }, /* SD3_DAT7 */
3715 { RCAR_GP_PIN(4, 15), PU4, 5 }, /* SD3_DAT6 */
3716 { RCAR_GP_PIN(4, 14), PU4, 4 }, /* SD3_DAT5 */
3717 { RCAR_GP_PIN(4, 13), PU4, 3 }, /* SD3_DAT4 */
3718 { RCAR_GP_PIN(4, 12), PU4, 2 }, /* SD3_DAT3 */
3719 { RCAR_GP_PIN(4, 11), PU4, 1 }, /* SD3_DAT2 */
3720 { RCAR_GP_PIN(4, 10), PU4, 0 }, /* SD3_DAT1 */
3721
3722 { RCAR_GP_PIN(6, 24), PU5, 31 }, /* USB0_PWEN */
3723 { RCAR_GP_PIN(6, 23), PU5, 30 }, /* AUDIO_CLKB_B */
3724 { RCAR_GP_PIN(6, 22), PU5, 29 }, /* AUDIO_CLKA_A */
3725 { RCAR_GP_PIN(6, 21), PU5, 28 }, /* SSI_SDATA9_A */
3726 { RCAR_GP_PIN(6, 20), PU5, 27 }, /* SSI_SDATA8 */
3727 { RCAR_GP_PIN(6, 19), PU5, 26 }, /* SSI_SDATA7 */
3728 { RCAR_GP_PIN(6, 18), PU5, 25 }, /* SSI_WS78 */
3729 { RCAR_GP_PIN(6, 17), PU5, 24 }, /* SSI_SCK78 */
3730 { RCAR_GP_PIN(6, 16), PU5, 23 }, /* SSI_SDATA6 */
3731 { RCAR_GP_PIN(6, 15), PU5, 22 }, /* SSI_WS6 */
3732 { RCAR_GP_PIN(6, 14), PU5, 21 }, /* SSI_SCK6 */
3733 { RCAR_GP_PIN(6, 13), PU5, 20 }, /* SSI_SDATA5 */
3734 { RCAR_GP_PIN(6, 12), PU5, 19 }, /* SSI_WS5 */
3735 { RCAR_GP_PIN(6, 11), PU5, 18 }, /* SSI_SCK5 */
3736 { RCAR_GP_PIN(6, 10), PU5, 17 }, /* SSI_SDATA4 */
3737 { RCAR_GP_PIN(6, 9), PU5, 16 }, /* SSI_WS4 */
3738 { RCAR_GP_PIN(6, 8), PU5, 15 }, /* SSI_SCK4 */
3739 { RCAR_GP_PIN(6, 7), PU5, 14 }, /* SSI_SDATA3 */
3740 { RCAR_GP_PIN(6, 6), PU5, 13 }, /* SSI_WS34 */
3741 { RCAR_GP_PIN(6, 5), PU5, 12 }, /* SSI_SCK34 */
3742 { RCAR_GP_PIN(6, 4), PU5, 11 }, /* SSI_SDATA2_A */
3743 { RCAR_GP_PIN(6, 3), PU5, 10 }, /* SSI_SDATA1_A */
3744 { RCAR_GP_PIN(6, 2), PU5, 9 }, /* SSI_SDATA0 */
3745 { RCAR_GP_PIN(6, 1), PU5, 8 }, /* SSI_WS01239 */
3746 { RCAR_GP_PIN(6, 0), PU5, 7 }, /* SSI_SCK01239 */
3747 { PIN_NUMBER('H', 37), PU5, 6 }, /* MLB_REF */
3748 { RCAR_GP_PIN(5, 25), PU5, 5 }, /* MLB_DAT */
3749 { RCAR_GP_PIN(5, 24), PU5, 4 }, /* MLB_SIG */
3750 { RCAR_GP_PIN(5, 23), PU5, 3 }, /* MLB_CLK */
3751 { RCAR_GP_PIN(5, 22), PU5, 2 }, /* MSIOF0_RXD */
3752 { RCAR_GP_PIN(5, 21), PU5, 1 }, /* MSIOF0_SS2 */
3753 { RCAR_GP_PIN(5, 20), PU5, 0 }, /* MSIOF0_TXD */
3754
3755 { RCAR_GP_PIN(6, 31), PU6, 6 }, /* GP6_31 */
3756 { RCAR_GP_PIN(6, 30), PU6, 5 }, /* GP6_30 */
3757 { RCAR_GP_PIN(6, 29), PU6, 4 }, /* USB30_OVC */
3758 { RCAR_GP_PIN(6, 28), PU6, 3 }, /* USB30_PWEN */
3759 { RCAR_GP_PIN(6, 27), PU6, 2 }, /* USB1_OVC */
3760 { RCAR_GP_PIN(6, 26), PU6, 1 }, /* USB1_PWEN */
3761 { RCAR_GP_PIN(6, 25), PU6, 0 }, /* USB0_OVC */
3762};
3763
3764static unsigned int r8a7796_pinmux_get_bias(struct sh_pfc *pfc,
3765 unsigned int pin)
3766{
3767 const struct sh_pfc_bias_info *info;
3768 u32 reg;
3769 u32 bit;
3770
3771 info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin);
3772 if (!info)
3773 return PIN_CONFIG_BIAS_DISABLE;
3774
3775 reg = info->reg;
3776 bit = BIT(info->bit);
3777
3778 if (!(sh_pfc_read_reg(pfc, PUEN + reg, 32) & bit))
3779 return PIN_CONFIG_BIAS_DISABLE;
3780 else if (sh_pfc_read_reg(pfc, PUD + reg, 32) & bit)
3781 return PIN_CONFIG_BIAS_PULL_UP;
3782 else
3783 return PIN_CONFIG_BIAS_PULL_DOWN;
3784}
3785
3786static void r8a7796_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
3787 unsigned int bias)
3788{
3789 const struct sh_pfc_bias_info *info;
3790 u32 enable, updown;
3791 u32 reg;
3792 u32 bit;
3793
3794 info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin);
3795 if (!info)
3796 return;
3797
3798 reg = info->reg;
3799 bit = BIT(info->bit);
3800
3801 enable = sh_pfc_read_reg(pfc, PUEN + reg, 32) & ~bit;
3802 if (bias != PIN_CONFIG_BIAS_DISABLE)
3803 enable |= bit;
3804
3805 updown = sh_pfc_read_reg(pfc, PUD + reg, 32) & ~bit;
3806 if (bias == PIN_CONFIG_BIAS_PULL_UP)
3807 updown |= bit;
3808
3809 sh_pfc_write_reg(pfc, PUD + reg, 32, updown);
3810 sh_pfc_write_reg(pfc, PUEN + reg, 32, enable);
3811}
3812
3539static const struct sh_pfc_soc_operations r8a7796_pinmux_ops = { 3813static const struct sh_pfc_soc_operations r8a7796_pinmux_ops = {
3540 .pin_to_pocctrl = r8a7796_pin_to_pocctrl, 3814 .pin_to_pocctrl = r8a7796_pin_to_pocctrl,
3815 .get_bias = r8a7796_pinmux_get_bias,
3816 .set_bias = r8a7796_pinmux_set_bias,
3541}; 3817};
3542 3818
3543const struct sh_pfc_soc_info r8a7796_pinmux_info = { 3819const struct sh_pfc_soc_info r8a7796_pinmux_info = {
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-24 15:55:09 -0400