diff options
author | Dave Airlie <airlied@redhat.com> | 2017-11-15 21:39:40 -0500 |
---|---|---|
committer | Dave Airlie <airlied@redhat.com> | 2017-11-15 21:39:40 -0500 |
commit | 49e37ba07a3ae697086c0a1a32c113a1f177d138 (patch) | |
tree | 492fc0db4fc5d7b417cb9e6a39580bce0ccbc33a | |
parent | 4479ed411cf41b42b1c548f73099287fff2330ff (diff) | |
parent | 00f713c6dc657397ba37b42d7f6887f526c730c6 (diff) |
Merge branch 'drm-next-4.15-dc' of git://people.freedesktop.org/~agd5f/linux into drm-next
Various fixes for DC for 4.15.
* 'drm-next-4.15-dc' of git://people.freedesktop.org/~agd5f/linux:
drm/amd/display: fix MST link training fail division by 0
drm/amd/display: Fix formatting for null pointer dereference fix
drm/amd/display: Remove dangling planes on dc commit state
drm/amd/display: add flip_immediate to commit update for stream
drm/amd/display: Miss register MST encoder cbs
drm/amd/display: Fix warnings on S3 resume
drm/amd/display: use num_timing_generator instead of pipe_count
drm/amd/display: use configurable FBC option in dm
drm/amd/display: fix AZ clock not enabled before program AZ endpoint
amdgpu/dm: Don't use DRM_ERROR in amdgpu_dm_atomic_check
-rw-r--r-- | drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 44 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 4 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 12 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/core/dc.c | 42 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/core/dc_link.c | 6 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/dce/dce_audio.c | 31 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 2 |
8 files changed, 122 insertions, 21 deletions
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 8ed6767b4616..889ed24084e8 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | |||
@@ -344,7 +344,7 @@ static void hotplug_notify_work_func(struct work_struct *work) | |||
344 | drm_kms_helper_hotplug_event(dev); | 344 | drm_kms_helper_hotplug_event(dev); |
345 | } | 345 | } |
346 | 346 | ||
347 | #ifdef ENABLE_FBC | 347 | #if defined(CONFIG_DRM_AMD_DC_FBC) |
348 | #include "dal_asic_id.h" | 348 | #include "dal_asic_id.h" |
349 | /* Allocate memory for FBC compressed data */ | 349 | /* Allocate memory for FBC compressed data */ |
350 | /* TODO: Dynamic allocation */ | 350 | /* TODO: Dynamic allocation */ |
@@ -422,7 +422,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev) | |||
422 | else | 422 | else |
423 | init_data.log_mask = DC_MIN_LOG_MASK; | 423 | init_data.log_mask = DC_MIN_LOG_MASK; |
424 | 424 | ||
425 | #ifdef ENABLE_FBC | 425 | #if defined(CONFIG_DRM_AMD_DC_FBC) |
426 | if (adev->family == FAMILY_CZ) | 426 | if (adev->family == FAMILY_CZ) |
427 | amdgpu_dm_initialize_fbc(adev); | 427 | amdgpu_dm_initialize_fbc(adev); |
428 | init_data.fbc_gpu_addr = adev->dm.compressor.gpu_addr; | 428 | init_data.fbc_gpu_addr = adev->dm.compressor.gpu_addr; |
@@ -643,6 +643,11 @@ int amdgpu_dm_display_resume(struct amdgpu_device *adev) | |||
643 | struct drm_connector *connector; | 643 | struct drm_connector *connector; |
644 | struct drm_crtc *crtc; | 644 | struct drm_crtc *crtc; |
645 | struct drm_crtc_state *new_crtc_state; | 645 | struct drm_crtc_state *new_crtc_state; |
646 | struct dm_crtc_state *dm_new_crtc_state; | ||
647 | struct drm_plane *plane; | ||
648 | struct drm_plane_state *new_plane_state; | ||
649 | struct dm_plane_state *dm_new_plane_state; | ||
650 | |||
646 | int ret = 0; | 651 | int ret = 0; |
647 | int i; | 652 | int i; |
648 | 653 | ||
@@ -681,6 +686,29 @@ int amdgpu_dm_display_resume(struct amdgpu_device *adev) | |||
681 | for_each_new_crtc_in_state(adev->dm.cached_state, crtc, new_crtc_state, i) | 686 | for_each_new_crtc_in_state(adev->dm.cached_state, crtc, new_crtc_state, i) |
682 | new_crtc_state->active_changed = true; | 687 | new_crtc_state->active_changed = true; |
683 | 688 | ||
689 | /* | ||
690 | * atomic_check is expected to create the dc states. We need to release | ||
691 | * them here, since they were duplicated as part of the suspend | ||
692 | * procedure. | ||
693 | */ | ||
694 | for_each_new_crtc_in_state(adev->dm.cached_state, crtc, new_crtc_state, i) { | ||
695 | dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); | ||
696 | if (dm_new_crtc_state->stream) { | ||
697 | WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1); | ||
698 | dc_stream_release(dm_new_crtc_state->stream); | ||
699 | dm_new_crtc_state->stream = NULL; | ||
700 | } | ||
701 | } | ||
702 | |||
703 | for_each_new_plane_in_state(adev->dm.cached_state, plane, new_plane_state, i) { | ||
704 | dm_new_plane_state = to_dm_plane_state(new_plane_state); | ||
705 | if (dm_new_plane_state->dc_state) { | ||
706 | WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1); | ||
707 | dc_plane_state_release(dm_new_plane_state->dc_state); | ||
708 | dm_new_plane_state->dc_state = NULL; | ||
709 | } | ||
710 | } | ||
711 | |||
684 | ret = drm_atomic_helper_resume(ddev, adev->dm.cached_state); | 712 | ret = drm_atomic_helper_resume(ddev, adev->dm.cached_state); |
685 | 713 | ||
686 | drm_atomic_state_put(adev->dm.cached_state); | 714 | drm_atomic_state_put(adev->dm.cached_state); |
@@ -4662,10 +4690,8 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, | |||
4662 | bool lock_and_validation_needed = false; | 4690 | bool lock_and_validation_needed = false; |
4663 | 4691 | ||
4664 | ret = drm_atomic_helper_check_modeset(dev, state); | 4692 | ret = drm_atomic_helper_check_modeset(dev, state); |
4665 | if (ret) { | 4693 | if (ret) |
4666 | DRM_ERROR("Atomic state validation failed with error :%d !\n", ret); | 4694 | goto fail; |
4667 | return ret; | ||
4668 | } | ||
4669 | 4695 | ||
4670 | /* | 4696 | /* |
4671 | * legacy_cursor_update should be made false for SoC's having | 4697 | * legacy_cursor_update should be made false for SoC's having |
@@ -4782,11 +4808,11 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, | |||
4782 | 4808 | ||
4783 | fail: | 4809 | fail: |
4784 | if (ret == -EDEADLK) | 4810 | if (ret == -EDEADLK) |
4785 | DRM_DEBUG_DRIVER("Atomic check stopped due to to deadlock.\n"); | 4811 | DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n"); |
4786 | else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS) | 4812 | else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS) |
4787 | DRM_DEBUG_DRIVER("Atomic check stopped due to to signal.\n"); | 4813 | DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n"); |
4788 | else | 4814 | else |
4789 | DRM_ERROR("Atomic check failed with err: %d \n", ret); | 4815 | DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret); |
4790 | 4816 | ||
4791 | return ret; | 4817 | return ret; |
4792 | } | 4818 | } |
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index f42f8357b676..117521c6a6ed 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | |||
@@ -72,7 +72,7 @@ struct irq_list_head { | |||
72 | struct work_struct work; | 72 | struct work_struct work; |
73 | }; | 73 | }; |
74 | 74 | ||
75 | #ifdef ENABLE_FBC | 75 | #if defined(CONFIG_DRM_AMD_DC_FBC) |
76 | struct dm_comressor_info { | 76 | struct dm_comressor_info { |
77 | void *cpu_addr; | 77 | void *cpu_addr; |
78 | struct amdgpu_bo *bo_ptr; | 78 | struct amdgpu_bo *bo_ptr; |
@@ -142,7 +142,7 @@ struct amdgpu_display_manager { | |||
142 | * Caches device atomic state for suspend/resume | 142 | * Caches device atomic state for suspend/resume |
143 | */ | 143 | */ |
144 | struct drm_atomic_state *cached_state; | 144 | struct drm_atomic_state *cached_state; |
145 | #ifdef ENABLE_FBC | 145 | #if defined(CONFIG_DRM_AMD_DC_FBC) |
146 | struct dm_comressor_info compressor; | 146 | struct dm_comressor_info compressor; |
147 | #endif | 147 | #endif |
148 | }; | 148 | }; |
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 3b05da7a90e8..f8efb98b1fa7 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | |||
@@ -245,6 +245,16 @@ static const struct drm_connector_helper_funcs dm_dp_mst_connector_helper_funcs | |||
245 | .best_encoder = dm_mst_best_encoder, | 245 | .best_encoder = dm_mst_best_encoder, |
246 | }; | 246 | }; |
247 | 247 | ||
248 | static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder) | ||
249 | { | ||
250 | drm_encoder_cleanup(encoder); | ||
251 | kfree(encoder); | ||
252 | } | ||
253 | |||
254 | static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = { | ||
255 | .destroy = amdgpu_dm_encoder_destroy, | ||
256 | }; | ||
257 | |||
248 | static struct amdgpu_encoder * | 258 | static struct amdgpu_encoder * |
249 | dm_dp_create_fake_mst_encoder(struct amdgpu_dm_connector *connector) | 259 | dm_dp_create_fake_mst_encoder(struct amdgpu_dm_connector *connector) |
250 | { | 260 | { |
@@ -268,7 +278,7 @@ dm_dp_create_fake_mst_encoder(struct amdgpu_dm_connector *connector) | |||
268 | drm_encoder_init( | 278 | drm_encoder_init( |
269 | dev, | 279 | dev, |
270 | &amdgpu_encoder->base, | 280 | &amdgpu_encoder->base, |
271 | NULL, | 281 | &amdgpu_dm_encoder_funcs, |
272 | DRM_MODE_ENCODER_DPMST, | 282 | DRM_MODE_ENCODER_DPMST, |
273 | NULL); | 283 | NULL); |
274 | 284 | ||
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index ce3c57b38bc0..fe63f5894d43 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c | |||
@@ -619,6 +619,39 @@ fail: | |||
619 | return false; | 619 | return false; |
620 | } | 620 | } |
621 | 621 | ||
622 | static void disable_dangling_plane(struct dc *dc, struct dc_state *context) | ||
623 | { | ||
624 | int i, j; | ||
625 | struct dc_state *dangling_context = dc_create_state(); | ||
626 | struct dc_state *current_ctx; | ||
627 | |||
628 | if (dangling_context == NULL) | ||
629 | return; | ||
630 | |||
631 | dc_resource_state_copy_construct(dc->current_state, dangling_context); | ||
632 | |||
633 | for (i = 0; i < dc->res_pool->pipe_count; i++) { | ||
634 | struct dc_stream_state *old_stream = | ||
635 | dc->current_state->res_ctx.pipe_ctx[i].stream; | ||
636 | bool should_disable = true; | ||
637 | |||
638 | for (j = 0; j < context->stream_count; j++) { | ||
639 | if (old_stream == context->streams[j]) { | ||
640 | should_disable = false; | ||
641 | break; | ||
642 | } | ||
643 | } | ||
644 | if (should_disable && old_stream) { | ||
645 | dc_rem_all_planes_for_stream(dc, old_stream, dangling_context); | ||
646 | dc->hwss.apply_ctx_for_surface(dc, old_stream, 0, dangling_context); | ||
647 | } | ||
648 | } | ||
649 | |||
650 | current_ctx = dc->current_state; | ||
651 | dc->current_state = dangling_context; | ||
652 | dc_release_state(current_ctx); | ||
653 | } | ||
654 | |||
622 | /******************************************************************************* | 655 | /******************************************************************************* |
623 | * Public functions | 656 | * Public functions |
624 | ******************************************************************************/ | 657 | ******************************************************************************/ |
@@ -801,6 +834,8 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c | |||
801 | int i, j, k, l; | 834 | int i, j, k, l; |
802 | struct dc_stream_state *dc_streams[MAX_STREAMS] = {0}; | 835 | struct dc_stream_state *dc_streams[MAX_STREAMS] = {0}; |
803 | 836 | ||
837 | disable_dangling_plane(dc, context); | ||
838 | |||
804 | for (i = 0; i < context->stream_count; i++) | 839 | for (i = 0; i < context->stream_count; i++) |
805 | dc_streams[i] = context->streams[i]; | 840 | dc_streams[i] = context->streams[i]; |
806 | 841 | ||
@@ -830,8 +865,6 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c | |||
830 | } | 865 | } |
831 | } | 866 | } |
832 | 867 | ||
833 | |||
834 | |||
835 | CONN_MSG_MODE(sink->link, "{%dx%d, %dx%d@%dKhz}", | 868 | CONN_MSG_MODE(sink->link, "{%dx%d, %dx%d@%dKhz}", |
836 | context->streams[i]->timing.h_addressable, | 869 | context->streams[i]->timing.h_addressable, |
837 | context->streams[i]->timing.v_addressable, | 870 | context->streams[i]->timing.v_addressable, |
@@ -1414,8 +1447,11 @@ void dc_commit_updates_for_stream(struct dc *dc, | |||
1414 | /* TODO: On flip we don't build the state, so it still has the | 1447 | /* TODO: On flip we don't build the state, so it still has the |
1415 | * old address. Which is why we are updating the address here | 1448 | * old address. Which is why we are updating the address here |
1416 | */ | 1449 | */ |
1417 | if (srf_updates[i].flip_addr) | 1450 | if (srf_updates[i].flip_addr) { |
1418 | surface->address = srf_updates[i].flip_addr->address; | 1451 | surface->address = srf_updates[i].flip_addr->address; |
1452 | surface->flip_immediate = srf_updates[i].flip_addr->flip_immediate; | ||
1453 | |||
1454 | } | ||
1419 | 1455 | ||
1420 | if (update_type >= UPDATE_TYPE_MED) { | 1456 | if (update_type >= UPDATE_TYPE_MED) { |
1421 | for (j = 0; j < dc->res_pool->pipe_count; j++) { | 1457 | for (j = 0; j < dc->res_pool->pipe_count; j++) { |
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index e70612eaf257..0602610489d7 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c | |||
@@ -2318,9 +2318,11 @@ void core_link_enable_stream( | |||
2318 | 2318 | ||
2319 | /* Abort stream enable *unless* the failure was due to | 2319 | /* Abort stream enable *unless* the failure was due to |
2320 | * DP link training - some DP monitors will recover and | 2320 | * DP link training - some DP monitors will recover and |
2321 | * show the stream anyway. | 2321 | * show the stream anyway. But MST displays can't proceed |
2322 | * without link training. | ||
2322 | */ | 2323 | */ |
2323 | if (status != DC_FAIL_DP_LINK_TRAINING) { | 2324 | if (status != DC_FAIL_DP_LINK_TRAINING || |
2325 | pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { | ||
2324 | BREAK_TO_DEBUGGER(); | 2326 | BREAK_TO_DEBUGGER(); |
2325 | return; | 2327 | return; |
2326 | } | 2328 | } |
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index de04b95e103a..b00a6040a697 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c | |||
@@ -288,7 +288,7 @@ bool dc_stream_set_cursor_position( | |||
288 | pos_cpy.enable = false; | 288 | pos_cpy.enable = false; |
289 | 289 | ||
290 | 290 | ||
291 | if (ipp !=NULL && ipp->funcs->ipp_cursor_set_position != NULL) | 291 | if (ipp != NULL && ipp->funcs->ipp_cursor_set_position != NULL) |
292 | ipp->funcs->ipp_cursor_set_position(ipp, &pos_cpy, ¶m); | 292 | ipp->funcs->ipp_cursor_set_position(ipp, &pos_cpy, ¶m); |
293 | 293 | ||
294 | if (mi != NULL && mi->funcs->set_cursor_position != NULL) | 294 | if (mi != NULL && mi->funcs->set_cursor_position != NULL) |
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c index d882adf746a5..81c40f8864db 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c | |||
@@ -348,29 +348,44 @@ static void set_audio_latency( | |||
348 | 348 | ||
349 | void dce_aud_az_enable(struct audio *audio) | 349 | void dce_aud_az_enable(struct audio *audio) |
350 | { | 350 | { |
351 | struct dce_audio *aud = DCE_AUD(audio); | ||
351 | uint32_t value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL); | 352 | uint32_t value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL); |
352 | 353 | ||
353 | if (get_reg_field_value(value, | 354 | set_reg_field_value(value, 1, |
354 | AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, | 355 | AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, |
355 | AUDIO_ENABLED) != 1) | 356 | CLOCK_GATING_DISABLE); |
356 | set_reg_field_value(value, 1, | 357 | set_reg_field_value(value, 1, |
357 | AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, | 358 | AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, |
358 | AUDIO_ENABLED); | 359 | AUDIO_ENABLED); |
359 | 360 | ||
360 | AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); | 361 | AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); |
362 | value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL); | ||
363 | |||
364 | dm_logger_write(CTX->logger, LOG_HW_AUDIO, | ||
365 | "\n\t========= AUDIO:dce_aud_az_enable: index: %u data: 0x%x\n", | ||
366 | audio->inst, value); | ||
361 | } | 367 | } |
362 | 368 | ||
363 | void dce_aud_az_disable(struct audio *audio) | 369 | void dce_aud_az_disable(struct audio *audio) |
364 | { | 370 | { |
365 | uint32_t value; | 371 | uint32_t value; |
372 | struct dce_audio *aud = DCE_AUD(audio); | ||
366 | 373 | ||
367 | value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL); | 374 | value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL); |
368 | 375 | ||
369 | set_reg_field_value(value, 0, | 376 | set_reg_field_value(value, 0, |
370 | AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, | 377 | AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, |
371 | AUDIO_ENABLED); | 378 | AUDIO_ENABLED); |
379 | AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); | ||
372 | 380 | ||
381 | set_reg_field_value(value, 0, | ||
382 | AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, | ||
383 | CLOCK_GATING_DISABLE); | ||
373 | AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); | 384 | AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); |
385 | value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL); | ||
386 | dm_logger_write(CTX->logger, LOG_HW_AUDIO, | ||
387 | "\n\t========= AUDIO:dce_aud_az_disable: index: %u data: 0x%x\n", | ||
388 | audio->inst, value); | ||
374 | } | 389 | } |
375 | 390 | ||
376 | void dce_aud_az_configure( | 391 | void dce_aud_az_configure( |
@@ -390,6 +405,11 @@ void dce_aud_az_configure( | |||
390 | bool is_ac3_supported = false; | 405 | bool is_ac3_supported = false; |
391 | union audio_sample_rates sample_rate; | 406 | union audio_sample_rates sample_rate; |
392 | uint32_t strlen = 0; | 407 | uint32_t strlen = 0; |
408 | value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL); | ||
409 | set_reg_field_value(value, 1, | ||
410 | AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, | ||
411 | CLOCK_GATING_DISABLE); | ||
412 | AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); | ||
393 | 413 | ||
394 | /* Speaker Allocation */ | 414 | /* Speaker Allocation */ |
395 | /* | 415 | /* |
@@ -852,6 +872,7 @@ static bool dce_aud_endpoint_valid(struct audio *audio) | |||
852 | void dce_aud_hw_init( | 872 | void dce_aud_hw_init( |
853 | struct audio *audio) | 873 | struct audio *audio) |
854 | { | 874 | { |
875 | uint32_t value; | ||
855 | struct dce_audio *aud = DCE_AUD(audio); | 876 | struct dce_audio *aud = DCE_AUD(audio); |
856 | 877 | ||
857 | /* we only need to program the following registers once, so we only do | 878 | /* we only need to program the following registers once, so we only do |
@@ -863,6 +884,12 @@ void dce_aud_hw_init( | |||
863 | * Suport R6 - 44.1khz | 884 | * Suport R6 - 44.1khz |
864 | * Suport R7 - 48khz | 885 | * Suport R7 - 48khz |
865 | */ | 886 | */ |
887 | /*disable clock gating before write to endpoint register*/ | ||
888 | value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL); | ||
889 | set_reg_field_value(value, 1, | ||
890 | AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, | ||
891 | CLOCK_GATING_DISABLE); | ||
892 | AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); | ||
866 | REG_UPDATE(AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES, | 893 | REG_UPDATE(AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES, |
867 | AUDIO_RATE_CAPABILITIES, 0x70); | 894 | AUDIO_RATE_CAPABILITIES, 0x70); |
868 | 895 | ||
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 63c2f5266142..961ad5c3b454 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | |||
@@ -202,7 +202,7 @@ static void dcn10_log_hw_state(struct dc *dc) | |||
202 | DTN_INFO("OTG:\t v_bs \t v_be \t v_ss \t v_se \t vpol \t vmax \t vmin \t " | 202 | DTN_INFO("OTG:\t v_bs \t v_be \t v_ss \t v_se \t vpol \t vmax \t vmin \t " |
203 | "h_bs \t h_be \t h_ss \t h_se \t hpol \t htot \t vtot \t underflow\n"); | 203 | "h_bs \t h_be \t h_ss \t h_se \t hpol \t htot \t vtot \t underflow\n"); |
204 | 204 | ||
205 | for (i = 0; i < pool->pipe_count; i++) { | 205 | for (i = 0; i < pool->res_cap->num_timing_generator; i++) { |
206 | struct timing_generator *tg = pool->timing_generators[i]; | 206 | struct timing_generator *tg = pool->timing_generators[i]; |
207 | struct dcn_otg_state s = {0}; | 207 | struct dcn_otg_state s = {0}; |
208 | 208 | ||