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authorBjorn Helgaas <bhelgaas@google.com>2018-06-06 17:10:51 -0400
committerBjorn Helgaas <bhelgaas@google.com>2018-06-06 17:10:51 -0400
commit488ad6d3678beee65bcd74e6a9764bd7cee9d3d3 (patch)
treee63ac18a413c7711d835b72543117fb24274eebe
parent0ecda3a087462eb89c1d9227deea998d8cd014e8 (diff)
parent82e1719c4cd65bd7f7847d6c02376cfca3d5e793 (diff)
Merge branch 'pci/trivial'
- clean up quirks.c organization and whitespace (Bjorn Helgaas) * pci/trivial: PCI: Clean up whitespace in quirks.c PCI: Reorder quirks infrastructure code
Diffstat
-rw-r--r--drivers/pci/quirks.c978
1 files changed, 485 insertions, 493 deletions
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 341d3a138217..f439de848658 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -30,6 +30,162 @@
30#include <asm/dma.h> /* isa_dma_bridge_buggy */ 30#include <asm/dma.h> /* isa_dma_bridge_buggy */
31#include "pci.h" 31#include "pci.h"
32 32
33static ktime_t fixup_debug_start(struct pci_dev *dev,
34 void (*fn)(struct pci_dev *dev))
35{
36 if (initcall_debug)
37 pci_info(dev, "calling %pF @ %i\n", fn, task_pid_nr(current));
38
39 return ktime_get();
40}
41
42static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime,
43 void (*fn)(struct pci_dev *dev))
44{
45 ktime_t delta, rettime;
46 unsigned long long duration;
47
48 rettime = ktime_get();
49 delta = ktime_sub(rettime, calltime);
50 duration = (unsigned long long) ktime_to_ns(delta) >> 10;
51 if (initcall_debug || duration > 10000)
52 pci_info(dev, "%pF took %lld usecs\n", fn, duration);
53}
54
55static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
56 struct pci_fixup *end)
57{
58 ktime_t calltime;
59
60 for (; f < end; f++)
61 if ((f->class == (u32) (dev->class >> f->class_shift) ||
62 f->class == (u32) PCI_ANY_ID) &&
63 (f->vendor == dev->vendor ||
64 f->vendor == (u16) PCI_ANY_ID) &&
65 (f->device == dev->device ||
66 f->device == (u16) PCI_ANY_ID)) {
67 calltime = fixup_debug_start(dev, f->hook);
68 f->hook(dev);
69 fixup_debug_report(dev, calltime, f->hook);
70 }
71}
72
73extern struct pci_fixup __start_pci_fixups_early[];
74extern struct pci_fixup __end_pci_fixups_early[];
75extern struct pci_fixup __start_pci_fixups_header[];
76extern struct pci_fixup __end_pci_fixups_header[];
77extern struct pci_fixup __start_pci_fixups_final[];
78extern struct pci_fixup __end_pci_fixups_final[];
79extern struct pci_fixup __start_pci_fixups_enable[];
80extern struct pci_fixup __end_pci_fixups_enable[];
81extern struct pci_fixup __start_pci_fixups_resume[];
82extern struct pci_fixup __end_pci_fixups_resume[];
83extern struct pci_fixup __start_pci_fixups_resume_early[];
84extern struct pci_fixup __end_pci_fixups_resume_early[];
85extern struct pci_fixup __start_pci_fixups_suspend[];
86extern struct pci_fixup __end_pci_fixups_suspend[];
87extern struct pci_fixup __start_pci_fixups_suspend_late[];
88extern struct pci_fixup __end_pci_fixups_suspend_late[];
89
90static bool pci_apply_fixup_final_quirks;
91
92void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
93{
94 struct pci_fixup *start, *end;
95
96 switch (pass) {
97 case pci_fixup_early:
98 start = __start_pci_fixups_early;
99 end = __end_pci_fixups_early;
100 break;
101
102 case pci_fixup_header:
103 start = __start_pci_fixups_header;
104 end = __end_pci_fixups_header;
105 break;
106
107 case pci_fixup_final:
108 if (!pci_apply_fixup_final_quirks)
109 return;
110 start = __start_pci_fixups_final;
111 end = __end_pci_fixups_final;
112 break;
113
114 case pci_fixup_enable:
115 start = __start_pci_fixups_enable;
116 end = __end_pci_fixups_enable;
117 break;
118
119 case pci_fixup_resume:
120 start = __start_pci_fixups_resume;
121 end = __end_pci_fixups_resume;
122 break;
123
124 case pci_fixup_resume_early:
125 start = __start_pci_fixups_resume_early;
126 end = __end_pci_fixups_resume_early;
127 break;
128
129 case pci_fixup_suspend:
130 start = __start_pci_fixups_suspend;
131 end = __end_pci_fixups_suspend;
132 break;
133
134 case pci_fixup_suspend_late:
135 start = __start_pci_fixups_suspend_late;
136 end = __end_pci_fixups_suspend_late;
137 break;
138
139 default:
140 /* stupid compiler warning, you would think with an enum... */
141 return;
142 }
143 pci_do_fixups(dev, start, end);
144}
145EXPORT_SYMBOL(pci_fixup_device);
146
147static int __init pci_apply_final_quirks(void)
148{
149 struct pci_dev *dev = NULL;
150 u8 cls = 0;
151 u8 tmp;
152
153 if (pci_cache_line_size)
154 printk(KERN_DEBUG "PCI: CLS %u bytes\n",
155 pci_cache_line_size << 2);
156
157 pci_apply_fixup_final_quirks = true;
158 for_each_pci_dev(dev) {
159 pci_fixup_device(pci_fixup_final, dev);
160 /*
161 * If arch hasn't set it explicitly yet, use the CLS
162 * value shared by all PCI devices. If there's a
163 * mismatch, fall back to the default value.
164 */
165 if (!pci_cache_line_size) {
166 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp);
167 if (!cls)
168 cls = tmp;
169 if (!tmp || cls == tmp)
170 continue;
171
172 printk(KERN_DEBUG "PCI: CLS mismatch (%u != %u), using %u bytes\n",
173 cls << 2, tmp << 2,
174 pci_dfl_cache_line_size << 2);
175 pci_cache_line_size = pci_dfl_cache_line_size;
176 }
177 }
178
179 if (!pci_cache_line_size) {
180 printk(KERN_DEBUG "PCI: CLS %u bytes, default %u\n",
181 cls << 2, pci_dfl_cache_line_size << 2);
182 pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size;
183 }
184
185 return 0;
186}
187fs_initcall_sync(pci_apply_final_quirks);
188
33/* 189/*
34 * Decoding should be disabled for a PCI device during BAR sizing to avoid 190 * Decoding should be disabled for a PCI device during BAR sizing to avoid
35 * conflict. But doing so may cause problems on host bridge and perhaps other 191 * conflict. But doing so may cause problems on host bridge and perhaps other
@@ -43,9 +199,10 @@ static void quirk_mmio_always_on(struct pci_dev *dev)
43DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID, 199DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID,
44 PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on); 200 PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on);
45 201
46/* The Mellanox Tavor device gives false positive parity errors 202/*
47 * Mark this device with a broken_parity_status, to allow 203 * The Mellanox Tavor device gives false positive parity errors. Mark this
48 * PCI scanning code to "skip" this now blacklisted device. 204 * device with a broken_parity_status to allow PCI scanning code to "skip"
205 * this now blacklisted device.
49 */ 206 */
50static void quirk_mellanox_tavor(struct pci_dev *dev) 207static void quirk_mellanox_tavor(struct pci_dev *dev)
51{ 208{
@@ -54,15 +211,19 @@ static void quirk_mellanox_tavor(struct pci_dev *dev)
54DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR, quirk_mellanox_tavor); 211DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR, quirk_mellanox_tavor);
55DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE, quirk_mellanox_tavor); 212DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE, quirk_mellanox_tavor);
56 213
57/* Deal with broken BIOSes that neglect to enable passive release, 214/*
58 which can cause problems in combination with the 82441FX/PPro MTRRs */ 215 * Deal with broken BIOSes that neglect to enable passive release,
216 * which can cause problems in combination with the 82441FX/PPro MTRRs
217 */
59static void quirk_passive_release(struct pci_dev *dev) 218static void quirk_passive_release(struct pci_dev *dev)
60{ 219{
61 struct pci_dev *d = NULL; 220 struct pci_dev *d = NULL;
62 unsigned char dlc; 221 unsigned char dlc;
63 222
64 /* We have to make sure a particular bit is set in the PIIX3 223 /*
65 ISA bridge, so we have to go out and find it. */ 224 * We have to make sure a particular bit is set in the PIIX3
225 * ISA bridge, so we have to go out and find it.
226 */
66 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) { 227 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
67 pci_read_config_byte(d, 0x82, &dlc); 228 pci_read_config_byte(d, 0x82, &dlc);
68 if (!(dlc & 1<<1)) { 229 if (!(dlc & 1<<1)) {
@@ -75,13 +236,14 @@ static void quirk_passive_release(struct pci_dev *dev)
75DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); 236DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
76DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); 237DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
77 238
78/* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround 239/*
79 but VIA don't answer queries. If you happen to have good contacts at VIA 240 * The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a
80 ask them for me please -- Alan 241 * workaround but VIA don't answer queries. If you happen to have good
81 242 * contacts at VIA ask them for me please -- Alan
82 This appears to be BIOS not version dependent. So presumably there is a 243 *
83 chipset level fix */ 244 * This appears to be BIOS not version dependent. So presumably there is a
84 245 * chipset level fix.
246 */
85static void quirk_isa_dma_hangs(struct pci_dev *dev) 247static void quirk_isa_dma_hangs(struct pci_dev *dev)
86{ 248{
87 if (!isa_dma_bridge_buggy) { 249 if (!isa_dma_bridge_buggy) {
@@ -89,10 +251,10 @@ static void quirk_isa_dma_hangs(struct pci_dev *dev)
89 pci_info(dev, "Activating ISA DMA hang workarounds\n"); 251 pci_info(dev, "Activating ISA DMA hang workarounds\n");
90 } 252 }
91} 253}
92 /* 254/*
93 * Its not totally clear which chipsets are the problematic ones 255 * It's not totally clear which chipsets are the problematic ones. We know
94 * We know 82C586 and 82C596 variants are affected. 256 * 82C586 and 82C596 variants are affected.
95 */ 257 */
96DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs); 258DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs);
97DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs); 259DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs);
98DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs); 260DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs);
@@ -121,9 +283,7 @@ static void quirk_tigerpoint_bm_sts(struct pci_dev *dev)
121} 283}
122DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts); 284DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts);
123 285
124/* 286/* Chipsets where PCI->PCI transfers vanish or hang */
125 * Chipsets where PCI->PCI transfers vanish or hang
126 */
127static void quirk_nopcipci(struct pci_dev *dev) 287static void quirk_nopcipci(struct pci_dev *dev)
128{ 288{
129 if ((pci_pci_problems & PCIPCI_FAIL) == 0) { 289 if ((pci_pci_problems & PCIPCI_FAIL) == 0) {
@@ -146,9 +306,7 @@ static void quirk_nopciamd(struct pci_dev *dev)
146} 306}
147DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd); 307DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd);
148 308
149/* 309/* Triton requires workarounds to be used by the drivers */
150 * Triton requires workarounds to be used by the drivers
151 */
152static void quirk_triton(struct pci_dev *dev) 310static void quirk_triton(struct pci_dev *dev)
153{ 311{
154 if ((pci_pci_problems&PCIPCI_TRITON) == 0) { 312 if ((pci_pci_problems&PCIPCI_TRITON) == 0) {
@@ -162,53 +320,62 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_tr
162DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton); 320DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton);
163 321
164/* 322/*
165 * VIA Apollo KT133 needs PCI latency patch 323 * VIA Apollo KT133 needs PCI latency patch
166 * Made according to a windows driver based patch by George E. Breese 324 * Made according to a Windows driver-based patch by George E. Breese;
167 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm 325 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
168 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for 326 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for the info on
169 * the info on which Mr Breese based his work. 327 * which Mr Breese based his work.
170 * 328 *
171 * Updated based on further information from the site and also on 329 * Updated based on further information from the site and also on
172 * information provided by VIA 330 * information provided by VIA
173 */ 331 */
174static void quirk_vialatency(struct pci_dev *dev) 332static void quirk_vialatency(struct pci_dev *dev)
175{ 333{
176 struct pci_dev *p; 334 struct pci_dev *p;
177 u8 busarb; 335 u8 busarb;
178 /* Ok we have a potential problem chipset here. Now see if we have
179 a buggy southbridge */
180 336
337 /*
338 * Ok, we have a potential problem chipset here. Now see if we have
339 * a buggy southbridge.
340 */
181 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL); 341 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
182 if (p != NULL) { 342 if (p != NULL) {
183 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */ 343
184 /* Check for buggy part revisions */ 344 /*
345 * 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A;
346 * thanks Dan Hollis.
347 * Check for buggy part revisions
348 */
185 if (p->revision < 0x40 || p->revision > 0x42) 349 if (p->revision < 0x40 || p->revision > 0x42)
186 goto exit; 350 goto exit;
187 } else { 351 } else {
188 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL); 352 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
189 if (p == NULL) /* No problem parts */ 353 if (p == NULL) /* No problem parts */
190 goto exit; 354 goto exit;
355
191 /* Check for buggy part revisions */ 356 /* Check for buggy part revisions */
192 if (p->revision < 0x10 || p->revision > 0x12) 357 if (p->revision < 0x10 || p->revision > 0x12)
193 goto exit; 358 goto exit;
194 } 359 }
195 360
196 /* 361 /*
197 * Ok we have the problem. Now set the PCI master grant to 362 * Ok we have the problem. Now set the PCI master grant to occur
198 * occur every master grant. The apparent bug is that under high 363 * every master grant. The apparent bug is that under high PCI load
199 * PCI load (quite common in Linux of course) you can get data 364 * (quite common in Linux of course) you can get data loss when the
200 * loss when the CPU is held off the bus for 3 bus master requests 365 * CPU is held off the bus for 3 bus master requests. This happens
201 * This happens to include the IDE controllers.... 366 * to include the IDE controllers....
202 * 367 *
203 * VIA only apply this fix when an SB Live! is present but under 368 * VIA only apply this fix when an SB Live! is present but under
204 * both Linux and Windows this isn't enough, and we have seen 369 * both Linux and Windows this isn't enough, and we have seen
205 * corruption without SB Live! but with things like 3 UDMA IDE 370 * corruption without SB Live! but with things like 3 UDMA IDE
206 * controllers. So we ignore that bit of the VIA recommendation.. 371 * controllers. So we ignore that bit of the VIA recommendation..
207 */ 372 */
208
209 pci_read_config_byte(dev, 0x76, &busarb); 373 pci_read_config_byte(dev, 0x76, &busarb);
210 /* Set bit 4 and bi 5 of byte 76 to 0x01 374
211 "Master priority rotation on every PCI master grant */ 375 /*
376 * Set bit 4 and bit 5 of byte 76 to 0x01
377 * "Master priority rotation on every PCI master grant"
378 */
212 busarb &= ~(1<<5); 379 busarb &= ~(1<<5);
213 busarb |= (1<<4); 380 busarb |= (1<<4);
214 pci_write_config_byte(dev, 0x76, busarb); 381 pci_write_config_byte(dev, 0x76, busarb);
@@ -224,9 +391,7 @@ DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vial
224DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency); 391DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
225DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency); 392DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
226 393
227/* 394/* VIA Apollo VP3 needs ETBF on BT848/878 */
228 * VIA Apollo VP3 needs ETBF on BT848/878
229 */
230static void quirk_viaetbf(struct pci_dev *dev) 395static void quirk_viaetbf(struct pci_dev *dev)
231{ 396{
232 if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) { 397 if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) {
@@ -246,10 +411,9 @@ static void quirk_vsfx(struct pci_dev *dev)
246DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx); 411DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx);
247 412
248/* 413/*
249 * Ali Magik requires workarounds to be used by the drivers 414 * ALi Magik requires workarounds to be used by the drivers that DMA to AGP
250 * that DMA to AGP space. Latency must be set to 0xA and triton 415 * space. Latency must be set to 0xA and Triton workaround applied too.
251 * workaround applied too 416 * [Info kindly provided by ALi]
252 * [Info kindly provided by ALi]
253 */ 417 */
254static void quirk_alimagik(struct pci_dev *dev) 418static void quirk_alimagik(struct pci_dev *dev)
255{ 419{
@@ -261,10 +425,7 @@ static void quirk_alimagik(struct pci_dev *dev)
261DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik); 425DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik);
262DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik); 426DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik);
263 427
264/* 428/* Natoma has some interesting boundary conditions with Zoran stuff at least */
265 * Natoma has some interesting boundary conditions with Zoran stuff
266 * at least
267 */
268static void quirk_natoma(struct pci_dev *dev) 429static void quirk_natoma(struct pci_dev *dev)
269{ 430{
270 if ((pci_pci_problems&PCIPCI_NATOMA) == 0) { 431 if ((pci_pci_problems&PCIPCI_NATOMA) == 0) {
@@ -280,8 +441,8 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quir
280DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma); 441DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma);
281 442
282/* 443/*
283 * This chip can cause PCI parity errors if config register 0xA0 is read 444 * This chip can cause PCI parity errors if config register 0xA0 is read
284 * while DMAs are occurring. 445 * while DMAs are occurring.
285 */ 446 */
286static void quirk_citrine(struct pci_dev *dev) 447static void quirk_citrine(struct pci_dev *dev)
287{ 448{
@@ -321,8 +482,8 @@ static void quirk_extend_bar_to_page(struct pci_dev *dev)
321DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, 0x034a, quirk_extend_bar_to_page); 482DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, 0x034a, quirk_extend_bar_to_page);
322 483
323/* 484/*
324 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M. 485 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
325 * If it's needed, re-allocate the region. 486 * If it's needed, re-allocate the region.
326 */ 487 */
327static void quirk_s3_64M(struct pci_dev *dev) 488static void quirk_s3_64M(struct pci_dev *dev)
328{ 489{
@@ -413,8 +574,8 @@ static void quirk_io_region(struct pci_dev *dev, int port,
413} 574}
414 575
415/* 576/*
416 * ATI Northbridge setups MCE the processor if you even 577 * ATI Northbridge setups MCE the processor if you even read somewhere
417 * read somewhere between 0x3b0->0x3bb or read 0x3d3 578 * between 0x3b0->0x3bb or read 0x3d3
418 */ 579 */
419static void quirk_ati_exploding_mce(struct pci_dev *dev) 580static void quirk_ati_exploding_mce(struct pci_dev *dev)
420{ 581{
@@ -429,6 +590,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_
429 * In the AMD NL platform, this device ([1022:7912]) has a class code of 590 * In the AMD NL platform, this device ([1022:7912]) has a class code of
430 * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will 591 * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will
431 * claim it. 592 * claim it.
593 *
432 * But the dwc3 driver is a more specific driver for this device, and we'd 594 * But the dwc3 driver is a more specific driver for this device, and we'd
433 * prefer to use it instead of xhci. To prevent xhci from claiming the 595 * prefer to use it instead of xhci. To prevent xhci from claiming the
434 * device, change the class code to 0x0c03fe, which the PCI r3.0 spec 596 * device, change the class code to 0x0c03fe, which the PCI r3.0 spec
@@ -448,11 +610,10 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB,
448 quirk_amd_nl_class); 610 quirk_amd_nl_class);
449 611
450/* 612/*
451 * Let's make the southbridge information explicit instead 613 * Let's make the southbridge information explicit instead of having to
452 * of having to worry about people probing the ACPI areas, 614 * worry about people probing the ACPI areas, for example.. (Yes, it
453 * for example.. (Yes, it happens, and if you read the wrong 615 * happens, and if you read the wrong ACPI register it will put the machine
454 * ACPI register it will put the machine to sleep with no 616 * to sleep with no way of waking it up again. Bummer).
455 * way of waking it up again. Bummer).
456 * 617 *
457 * ALI M7101: Two IO regions pointed to by words at 618 * ALI M7101: Two IO regions pointed to by words at
458 * 0xE0 (64 bytes of ACPI registers) 619 * 0xE0 (64 bytes of ACPI registers)
@@ -508,6 +669,7 @@ static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int
508 break; 669 break;
509 size = bit; 670 size = bit;
510 } 671 }
672
511 /* 673 /*
512 * For now we only print it out. Eventually we'll want to 674 * For now we only print it out. Eventually we'll want to
513 * reserve it, but let's get enough confirmation reports first. 675 * reserve it, but let's get enough confirmation reports first.
@@ -579,8 +741,7 @@ static void quirk_ich4_lpc_acpi(struct pci_dev *dev)
579 * priority and can't tell whether the legacy device or the one created 741 * priority and can't tell whether the legacy device or the one created
580 * here is really at that address. This happens on boards with broken 742 * here is really at that address. This happens on boards with broken
581 * BIOSes. 743 * BIOSes.
582 */ 744 */
583
584 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable); 745 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
585 if (enable & ICH4_ACPI_EN) 746 if (enable & ICH4_ACPI_EN)
586 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES, 747 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
@@ -617,7 +778,8 @@ static void ich6_lpc_acpi_gpio(struct pci_dev *dev)
617 "ICH6 GPIO"); 778 "ICH6 GPIO");
618} 779}
619 780
620static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name, int dynsize) 781static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg,
782 const char *name, int dynsize)
621{ 783{
622 u32 val; 784 u32 val;
623 u32 size, base; 785 u32 size, base;
@@ -641,7 +803,10 @@ static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const cha
641 } 803 }
642 base &= ~(size-1); 804 base &= ~(size-1);
643 805
644 /* Just print it out for now. We should reserve it after more debugging */ 806 /*
807 * Just print it out for now. We should reserve it after more
808 * debugging.
809 */
645 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base+size-1); 810 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base+size-1);
646} 811}
647 812
@@ -657,7 +822,8 @@ static void quirk_ich6_lpc(struct pci_dev *dev)
657DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc); 822DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc);
658DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc); 823DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc);
659 824
660static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name) 825static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg,
826 const char *name)
661{ 827{
662 u32 val; 828 u32 val;
663 u32 mask, base; 829 u32 mask, base;
@@ -668,15 +834,15 @@ static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const cha
668 if (!(val & 1)) 834 if (!(val & 1))
669 return; 835 return;
670 836
671 /* 837 /* IO base in bits 15:2, mask in bits 23:18, both are dword-based */
672 * IO base in bits 15:2, mask in bits 23:18, both
673 * are dword-based
674 */
675 base = val & 0xfffc; 838 base = val & 0xfffc;
676 mask = (val >> 16) & 0xfc; 839 mask = (val >> 16) & 0xfc;
677 mask |= 3; 840 mask |= 3;
678 841
679 /* Just print it out for now. We should reserve it after more debugging */ 842 /*
843 * Just print it out for now. We should reserve it after more
844 * debugging.
845 */
680 pci_info(dev, "%s PIO at %04x (mask %04x)\n", name, base, mask); 846 pci_info(dev, "%s PIO at %04x (mask %04x)\n", name, base, mask);
681} 847}
682 848
@@ -748,8 +914,8 @@ static void quirk_vt8235_acpi(struct pci_dev *dev)
748DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi); 914DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
749 915
750/* 916/*
751 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast back-to-back: 917 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast
752 * Disable fast back-to-back on the secondary bus segment 918 * back-to-back: Disable fast back-to-back on the secondary bus segment
753 */ 919 */
754static void quirk_xio2000a(struct pci_dev *dev) 920static void quirk_xio2000a(struct pci_dev *dev)
755{ 921{
@@ -774,8 +940,8 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A,
774 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip 940 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
775 * devices to the external APIC. 941 * devices to the external APIC.
776 * 942 *
777 * TODO: When we have device-specific interrupt routers, 943 * TODO: When we have device-specific interrupt routers, this code will go
778 * this code will go away from quirks. 944 * away from quirks.
779 */ 945 */
780static void quirk_via_ioapic(struct pci_dev *dev) 946static void quirk_via_ioapic(struct pci_dev *dev)
781{ 947{
@@ -816,13 +982,13 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt
816DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); 982DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
817 983
818/* 984/*
819 * The AMD io apic can hang the box when an apic irq is masked. 985 * The AMD IO-APIC can hang the box when an APIC IRQ is masked.
820 * We check all revs >= B0 (yet not in the pre production!) as the bug 986 * We check all revs >= B0 (yet not in the pre production!) as the bug
821 * is currently marked NoFix 987 * is currently marked NoFix
822 * 988 *
823 * We have multiple reports of hangs with this chipset that went away with 989 * We have multiple reports of hangs with this chipset that went away with
824 * noapic specified. For the moment we assume it's the erratum. We may be wrong 990 * noapic specified. For the moment we assume it's the erratum. We may be wrong
825 * of course. However the advice is demonstrably good even if so.. 991 * of course. However the advice is demonstrably good even if so.
826 */ 992 */
827static void quirk_amd_ioapic(struct pci_dev *dev) 993static void quirk_amd_ioapic(struct pci_dev *dev)
828{ 994{
@@ -838,7 +1004,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_a
838 1004
839static void quirk_cavium_sriov_rnm_link(struct pci_dev *dev) 1005static void quirk_cavium_sriov_rnm_link(struct pci_dev *dev)
840{ 1006{
841 /* Fix for improper SRIOV configuration on Cavium cn88xx RNM device */ 1007 /* Fix for improper SR-IOV configuration on Cavium cn88xx RNM device */
842 if (dev->subsystem_device == 0xa118) 1008 if (dev->subsystem_device == 0xa118)
843 dev->sriov->link = dev->devfn; 1009 dev->sriov->link = dev->devfn;
844} 1010}
@@ -860,19 +1026,17 @@ static void quirk_amd_8131_mmrbc(struct pci_dev *dev)
860DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc); 1026DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);
861 1027
862/* 1028/*
863 * FIXME: it is questionable that quirk_via_acpi 1029 * FIXME: it is questionable that quirk_via_acpi() is needed. It shows up
864 * is needed. It shows up as an ISA bridge, and does not 1030 * as an ISA bridge, and does not support the PCI_INTERRUPT_LINE register
865 * support the PCI_INTERRUPT_LINE register at all. Therefore 1031 * at all. Therefore it seems like setting the pci_dev's IRQ to the value
866 * it seems like setting the pci_dev's 'irq' to the 1032 * of the ACPI SCI interrupt is only done for convenience.
867 * value of the ACPI SCI interrupt is only done for convenience.
868 * -jgarzik 1033 * -jgarzik
869 */ 1034 */
870static void quirk_via_acpi(struct pci_dev *d) 1035static void quirk_via_acpi(struct pci_dev *d)
871{ 1036{
872 /*
873 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
874 */
875 u8 irq; 1037 u8 irq;
1038
1039 /* VIA ACPI device: SCI IRQ line in PCI config byte 0x42 */
876 pci_read_config_byte(d, 0x42, &irq); 1040 pci_read_config_byte(d, 0x42, &irq);
877 irq &= 0xf; 1041 irq &= 0xf;
878 if (irq && (irq != 2)) 1042 if (irq && (irq != 2))
@@ -881,11 +1045,7 @@ static void quirk_via_acpi(struct pci_dev *d)
881DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi); 1045DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi);
882DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi); 1046DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi);
883 1047
884 1048/* VIA bridges which have VLink */
885/*
886 * VIA bridges which have VLink
887 */
888
889static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18; 1049static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
890 1050
891static void quirk_via_bridge(struct pci_dev *dev) 1051static void quirk_via_bridge(struct pci_dev *dev)
@@ -893,9 +1053,11 @@ static void quirk_via_bridge(struct pci_dev *dev)
893 /* See what bridge we have and find the device ranges */ 1053 /* See what bridge we have and find the device ranges */
894 switch (dev->device) { 1054 switch (dev->device) {
895 case PCI_DEVICE_ID_VIA_82C686: 1055 case PCI_DEVICE_ID_VIA_82C686:
896 /* The VT82C686 is special, it attaches to PCI and can have 1056 /*
897 any device number. All its subdevices are functions of 1057 * The VT82C686 is special; it attaches to PCI and can have
898 that single device. */ 1058 * any device number. All its subdevices are functions of
1059 * that single device.
1060 */
899 via_vlink_dev_lo = PCI_SLOT(dev->devfn); 1061 via_vlink_dev_lo = PCI_SLOT(dev->devfn);
900 via_vlink_dev_hi = PCI_SLOT(dev->devfn); 1062 via_vlink_dev_hi = PCI_SLOT(dev->devfn);
901 break; 1063 break;
@@ -923,19 +1085,17 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_b
923DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge); 1085DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge);
924DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge); 1086DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge);
925 1087
926/** 1088/*
927 * quirk_via_vlink - VIA VLink IRQ number update 1089 * quirk_via_vlink - VIA VLink IRQ number update
928 * @dev: PCI device 1090 * @dev: PCI device
929 * 1091 *
930 * If the device we are dealing with is on a PIC IRQ we need to 1092 * If the device we are dealing with is on a PIC IRQ we need to ensure that
931 * ensure that the IRQ line register which usually is not relevant 1093 * the IRQ line register which usually is not relevant for PCI cards, is
932 * for PCI cards, is actually written so that interrupts get sent 1094 * actually written so that interrupts get sent to the right place.
933 * to the right place. 1095 *
934 * We only do this on systems where a VIA south bridge was detected, 1096 * We only do this on systems where a VIA south bridge was detected, and
935 * and only for VIA devices on the motherboard (see quirk_via_bridge 1097 * only for VIA devices on the motherboard (see quirk_via_bridge above).
936 * above).
937 */ 1098 */
938
939static void quirk_via_vlink(struct pci_dev *dev) 1099static void quirk_via_vlink(struct pci_dev *dev)
940{ 1100{
941 u8 irq, new_irq; 1101 u8 irq, new_irq;
@@ -955,9 +1115,10 @@ static void quirk_via_vlink(struct pci_dev *dev)
955 PCI_SLOT(dev->devfn) < via_vlink_dev_lo) 1115 PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
956 return; 1116 return;
957 1117
958 /* This is an internal VLink device on a PIC interrupt. The BIOS 1118 /*
959 ought to have set this but may not have, so we redo it */ 1119 * This is an internal VLink device on a PIC interrupt. The BIOS
960 1120 * ought to have set this but may not have, so we redo it.
1121 */
961 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); 1122 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
962 if (new_irq != irq) { 1123 if (new_irq != irq) {
963 pci_info(dev, "VIA VLink IRQ fixup, from %d to %d\n", 1124 pci_info(dev, "VIA VLink IRQ fixup, from %d to %d\n",
@@ -969,10 +1130,9 @@ static void quirk_via_vlink(struct pci_dev *dev)
969DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink); 1130DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);
970 1131
971/* 1132/*
972 * VIA VT82C598 has its device ID settable and many BIOSes 1133 * VIA VT82C598 has its device ID settable and many BIOSes set it to the ID
973 * set it to the ID of VT82C597 for backward compatibility. 1134 * of VT82C597 for backward compatibility. We need to switch it off to be
974 * We need to switch it off to be able to recognize the real 1135 * able to recognize the real type of the chip.
975 * type of the chip.
976 */ 1136 */
977static void quirk_vt82c598_id(struct pci_dev *dev) 1137static void quirk_vt82c598_id(struct pci_dev *dev)
978{ 1138{
@@ -982,10 +1142,10 @@ static void quirk_vt82c598_id(struct pci_dev *dev)
982DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id); 1142DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id);
983 1143
984/* 1144/*
985 * CardBus controllers have a legacy base address that enables them 1145 * CardBus controllers have a legacy base address that enables them to
986 * to respond as i82365 pcmcia controllers. We don't want them to 1146 * respond as i82365 pcmcia controllers. We don't want them to do this
987 * do this even if the Linux CardBus driver is not loaded, because 1147 * even if the Linux CardBus driver is not loaded, because the Linux i82365
988 * the Linux i82365 driver does not (and should not) handle CardBus. 1148 * driver does not (and should not) handle CardBus.
989 */ 1149 */
990static void quirk_cardbus_legacy(struct pci_dev *dev) 1150static void quirk_cardbus_legacy(struct pci_dev *dev)
991{ 1151{
@@ -997,11 +1157,11 @@ DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID,
997 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy); 1157 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
998 1158
999/* 1159/*
1000 * Following the PCI ordering rules is optional on the AMD762. I'm not 1160 * Following the PCI ordering rules is optional on the AMD762. I'm not sure
1001 * sure what the designers were smoking but let's not inhale... 1161 * what the designers were smoking but let's not inhale...
1002 * 1162 *
1003 * To be fair to AMD, it follows the spec by default, its BIOS people 1163 * To be fair to AMD, it follows the spec by default, it's BIOS people who
1004 * who turn it off! 1164 * turn it off!
1005 */ 1165 */
1006static void quirk_amd_ordering(struct pci_dev *dev) 1166static void quirk_amd_ordering(struct pci_dev *dev)
1007{ 1167{
@@ -1020,11 +1180,11 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk
1020DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); 1180DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
1021 1181
1022/* 1182/*
1023 * DreamWorks provided workaround for Dunord I-3000 problem 1183 * DreamWorks-provided workaround for Dunord I-3000 problem
1024 * 1184 *
1025 * This card decodes and responds to addresses not apparently 1185 * This card decodes and responds to addresses not apparently assigned to
1026 * assigned to it. We force a larger allocation to ensure that 1186 * it. We force a larger allocation to ensure that nothing gets put too
1027 * nothing gets put too close to it. 1187 * close to it.
1028 */ 1188 */
1029static void quirk_dunord(struct pci_dev *dev) 1189static void quirk_dunord(struct pci_dev *dev)
1030{ 1190{
@@ -1037,10 +1197,9 @@ static void quirk_dunord(struct pci_dev *dev)
1037DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord); 1197DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord);
1038 1198
1039/* 1199/*
1040 * i82380FB mobile docking controller: its PCI-to-PCI bridge 1200 * i82380FB mobile docking controller: its PCI-to-PCI bridge is subtractive
1041 * is subtractive decoding (transparent), and does indicate this 1201 * decoding (transparent), and does indicate this in the ProgIf.
1042 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80 1202 * Unfortunately, the ProgIf value is wrong - 0x80 instead of 0x01.
1043 * instead of 0x01.
1044 */ 1203 */
1045static void quirk_transparent_bridge(struct pci_dev *dev) 1204static void quirk_transparent_bridge(struct pci_dev *dev)
1046{ 1205{
@@ -1050,10 +1209,10 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk
1050DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge); 1209DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge);
1051 1210
1052/* 1211/*
1053 * Common misconfiguration of the MediaGX/Geode PCI master that will 1212 * Common misconfiguration of the MediaGX/Geode PCI master that will reduce
1054 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1 1213 * PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1 datasheets
1055 * datasheets found at http://www.national.com/analog for info on what 1214 * found at http://www.national.com/analog for info on what these bits do.
1056 * these bits do. <christer@weinigel.se> 1215 * <christer@weinigel.se>
1057 */ 1216 */
1058static void quirk_mediagx_master(struct pci_dev *dev) 1217static void quirk_mediagx_master(struct pci_dev *dev)
1059{ 1218{
@@ -1071,9 +1230,9 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, qui
1071DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master); 1230DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1072 1231
1073/* 1232/*
1074 * Ensure C0 rev restreaming is off. This is normally done by 1233 * Ensure C0 rev restreaming is off. This is normally done by the BIOS but
1075 * the BIOS but in the odd case it is not the results are corruption 1234 * in the odd case it is not the results are corruption hence the presence
1076 * hence the presence of a Linux check 1235 * of a Linux check.
1077 */ 1236 */
1078static void quirk_disable_pxb(struct pci_dev *pdev) 1237static void quirk_disable_pxb(struct pci_dev *pdev)
1079{ 1238{
@@ -1117,9 +1276,7 @@ DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA
1117DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode); 1276DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1118DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode); 1277DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1119 1278
1120/* 1279/* Serverworks CSB5 IDE does not fully support native mode */
1121 * Serverworks CSB5 IDE does not fully support native mode
1122 */
1123static void quirk_svwks_csb5ide(struct pci_dev *pdev) 1280static void quirk_svwks_csb5ide(struct pci_dev *pdev)
1124{ 1281{
1125 u8 prog; 1282 u8 prog;
@@ -1133,9 +1290,7 @@ static void quirk_svwks_csb5ide(struct pci_dev *pdev)
1133} 1290}
1134DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide); 1291DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);
1135 1292
1136/* 1293/* Intel 82801CAM ICH3-M datasheet says IDE modes must be the same */
1137 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
1138 */
1139static void quirk_ide_samemode(struct pci_dev *pdev) 1294static void quirk_ide_samemode(struct pci_dev *pdev)
1140{ 1295{
1141 u8 prog; 1296 u8 prog;
@@ -1151,10 +1306,7 @@ static void quirk_ide_samemode(struct pci_dev *pdev)
1151} 1306}
1152DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode); 1307DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
1153 1308
1154/* 1309/* Some ATA devices break if put into D3 */
1155 * Some ATA devices break if put into D3
1156 */
1157
1158static void quirk_no_ata_d3(struct pci_dev *pdev) 1310static void quirk_no_ata_d3(struct pci_dev *pdev)
1159{ 1311{
1160 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3; 1312 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;
@@ -1172,7 +1324,8 @@ DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID,
1172DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID, 1324DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID,
1173 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1325 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1174 1326
1175/* This was originally an Alpha specific thing, but it really fits here. 1327/*
1328 * This was originally an Alpha-specific thing, but it really fits here.
1176 * The i82375 PCI/EISA bridge appears as non-classified. Fix that. 1329 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1177 */ 1330 */
1178static void quirk_eisa_bridge(struct pci_dev *dev) 1331static void quirk_eisa_bridge(struct pci_dev *dev)
@@ -1181,7 +1334,6 @@ static void quirk_eisa_bridge(struct pci_dev *dev)
1181} 1334}
1182DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge); 1335DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge);
1183 1336
1184
1185/* 1337/*
1186 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge 1338 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
1187 * is not activated. The myth is that Asus said that they do not want the 1339 * is not activated. The myth is that Asus said that they do not want the
@@ -1398,15 +1550,19 @@ static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev)
1398 1550
1399 if (likely(!asus_hides_smbus || !asus_rcba_base)) 1551 if (likely(!asus_hides_smbus || !asus_rcba_base))
1400 return; 1552 return;
1553
1401 /* read the Function Disable register, dword mode only */ 1554 /* read the Function Disable register, dword mode only */
1402 val = readl(asus_rcba_base + 0x3418); 1555 val = readl(asus_rcba_base + 0x3418);
1403 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); /* enable the SMBus device */ 1556
1557 /* enable the SMBus device */
1558 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418);
1404} 1559}
1405 1560
1406static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev) 1561static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
1407{ 1562{
1408 if (likely(!asus_hides_smbus || !asus_rcba_base)) 1563 if (likely(!asus_hides_smbus || !asus_rcba_base))
1409 return; 1564 return;
1565
1410 iounmap(asus_rcba_base); 1566 iounmap(asus_rcba_base);
1411 asus_rcba_base = NULL; 1567 asus_rcba_base = NULL;
1412 pci_info(dev, "Enabled ICH6/i801 SMBus device\n"); 1568 pci_info(dev, "Enabled ICH6/i801 SMBus device\n");
@@ -1423,9 +1579,7 @@ DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_
1423DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume); 1579DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume);
1424DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early); 1580DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early);
1425 1581
1426/* 1582/* SiS 96x south bridge: BIOS typically hides SMBus device... */
1427 * SiS 96x south bridge: BIOS typically hides SMBus device...
1428 */
1429static void quirk_sis_96x_smbus(struct pci_dev *dev) 1583static void quirk_sis_96x_smbus(struct pci_dev *dev)
1430{ 1584{
1431 u8 val = 0; 1585 u8 val = 0;
@@ -1448,7 +1602,7 @@ DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_si
1448 * ... This is further complicated by the fact that some SiS96x south 1602 * ... This is further complicated by the fact that some SiS96x south
1449 * bridges pretend to be 85C503/5513 instead. In that case see if we 1603 * bridges pretend to be 85C503/5513 instead. In that case see if we
1450 * spotted a compatible north bridge to make sure. 1604 * spotted a compatible north bridge to make sure.
1451 * (pci_find_device doesn't work yet) 1605 * (pci_find_device() doesn't work yet)
1452 * 1606 *
1453 * We can also enable the sis96x bit in the discovery register.. 1607 * We can also enable the sis96x bit in the discovery register..
1454 */ 1608 */
@@ -1468,9 +1622,9 @@ static void quirk_sis_503(struct pci_dev *dev)
1468 } 1622 }
1469 1623
1470 /* 1624 /*
1471 * Ok, it now shows up as a 96x.. run the 96x quirk by 1625 * Ok, it now shows up as a 96x. Run the 96x quirk by hand in case
1472 * hand in case it has already been processed. 1626 * it has already been processed. (Depends on link order, which is
1473 * (depends on link order, which is apparently not guaranteed) 1627 * apparently not guaranteed)
1474 */ 1628 */
1475 dev->device = devid; 1629 dev->device = devid;
1476 quirk_sis_96x_smbus(dev); 1630 quirk_sis_96x_smbus(dev);
@@ -1478,7 +1632,6 @@ static void quirk_sis_503(struct pci_dev *dev)
1478DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); 1632DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1479DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); 1633DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1480 1634
1481
1482/* 1635/*
1483 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller 1636 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1484 * and MC97 modem controller are disabled when a second PCI soundcard is 1637 * and MC97 modem controller are disabled when a second PCI soundcard is
@@ -1515,9 +1668,8 @@ DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_h
1515#if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE) 1668#if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
1516 1669
1517/* 1670/*
1518 * If we are using libata we can drive this chip properly but must 1671 * If we are using libata we can drive this chip properly but must do this
1519 * do this early on to make the additional device appear during 1672 * early on to make the additional device appear during the PCI scanning.
1520 * the PCI scanning.
1521 */ 1673 */
1522static void quirk_jmicron_ata(struct pci_dev *pdev) 1674static void quirk_jmicron_ata(struct pci_dev *pdev)
1523{ 1675{
@@ -1613,14 +1765,18 @@ static void quirk_alder_ioapic(struct pci_dev *pdev)
1613 if ((pdev->class >> 8) != 0xff00) 1765 if ((pdev->class >> 8) != 0xff00)
1614 return; 1766 return;
1615 1767
1616 /* the first BAR is the location of the IO APIC...we must 1768 /*
1769 * The first BAR is the location of the IO-APIC... we must
1617 * not touch this (and it's already covered by the fixmap), so 1770 * not touch this (and it's already covered by the fixmap), so
1618 * forcibly insert it into the resource tree */ 1771 * forcibly insert it into the resource tree.
1772 */
1619 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0)) 1773 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1620 insert_resource(&iomem_resource, &pdev->resource[0]); 1774 insert_resource(&iomem_resource, &pdev->resource[0]);
1621 1775
1622 /* The next five BARs all seem to be rubbish, so just clean 1776 /*
1623 * them out */ 1777 * The next five BARs all seem to be rubbish, so just clean
1778 * them out.
1779 */
1624 for (i = 1; i < 6; i++) 1780 for (i = 1; i < 6; i++)
1625 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i])); 1781 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1626} 1782}
@@ -1638,8 +1794,8 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quir
1638DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1610, PCI_CLASS_BRIDGE_PCI, 8, quirk_pcie_mch); 1794DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1610, PCI_CLASS_BRIDGE_PCI, 8, quirk_pcie_mch);
1639 1795
1640/* 1796/*
1641 * It's possible for the MSI to get corrupted if shpc and acpi 1797 * It's possible for the MSI to get corrupted if SHPC and ACPI are used
1642 * are used together on certain PXH-based systems. 1798 * together on certain PXH-based systems.
1643 */ 1799 */
1644static void quirk_pcie_pxh(struct pci_dev *dev) 1800static void quirk_pcie_pxh(struct pci_dev *dev)
1645{ 1801{
@@ -1653,15 +1809,14 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pc
1653DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh); 1809DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1654 1810
1655/* 1811/*
1656 * Some Intel PCI Express chipsets have trouble with downstream 1812 * Some Intel PCI Express chipsets have trouble with downstream device
1657 * device power management. 1813 * power management.
1658 */ 1814 */
1659static void quirk_intel_pcie_pm(struct pci_dev *dev) 1815static void quirk_intel_pcie_pm(struct pci_dev *dev)
1660{ 1816{
1661 pci_pm_d3_delay = 120; 1817 pci_pm_d3_delay = 120;
1662 dev->no_d1d2 = 1; 1818 dev->no_d1d2 = 1;
1663} 1819}
1664
1665DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm); 1820DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
1666DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm); 1821DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
1667DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm); 1822DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
@@ -1723,7 +1878,7 @@ static const struct dmi_system_id boot_interrupt_dmi_table[] = {
1723 1878
1724/* 1879/*
1725 * Boot interrupts on some chipsets cannot be turned off. For these chipsets, 1880 * Boot interrupts on some chipsets cannot be turned off. For these chipsets,
1726 * remap the original interrupt in the linux kernel to the boot interrupt, so 1881 * remap the original interrupt in the Linux kernel to the boot interrupt, so
1727 * that a PCI device's interrupt handler is installed on the boot interrupt 1882 * that a PCI device's interrupt handler is installed on the boot interrupt
1728 * line instead. 1883 * line instead.
1729 */ 1884 */
@@ -1760,7 +1915,7 @@ DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk
1760 */ 1915 */
1761 1916
1762/* 1917/*
1763 * IO-APIC1 on 6300ESB generates boot interrupts, see intel order no 1918 * IO-APIC1 on 6300ESB generates boot interrupts, see Intel order no
1764 * 300641-004US, section 5.7.3. 1919 * 300641-004US, section 5.7.3.
1765 */ 1920 */
1766#define INTEL_6300_IOAPIC_ABAR 0x40 1921#define INTEL_6300_IOAPIC_ABAR 0x40
@@ -1783,9 +1938,7 @@ static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
1783DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt); 1938DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1784DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt); 1939DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1785 1940
1786/* 1941/* Disable boot interrupts on HT-1000 */
1787 * disable boot interrupts on HT-1000
1788 */
1789#define BC_HT1000_FEATURE_REG 0x64 1942#define BC_HT1000_FEATURE_REG 0x64
1790#define BC_HT1000_PIC_REGS_ENABLE (1<<0) 1943#define BC_HT1000_PIC_REGS_ENABLE (1<<0)
1791#define BC_HT1000_MAP_IDX 0xC00 1944#define BC_HT1000_MAP_IDX 0xC00
@@ -1816,9 +1969,8 @@ static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev)
1816DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); 1969DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1817DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); 1970DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1818 1971
1819/* 1972/* Disable boot interrupts on AMD and ATI chipsets */
1820 * disable boot interrupts on AMD and ATI chipsets 1973
1821 */
1822/* 1974/*
1823 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131 1975 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131
1824 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode 1976 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
@@ -1894,7 +2046,7 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
1894 quirk_tc86c001_ide); 2046 quirk_tc86c001_ide);
1895 2047
1896/* 2048/*
1897 * PLX PCI 9050 PCI Target bridge controller has an errata that prevents the 2049 * PLX PCI 9050 PCI Target bridge controller has an erratum that prevents the
1898 * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o) 2050 * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o)
1899 * being read correctly if bit 7 of the base address is set. 2051 * being read correctly if bit 7 of the base address is set.
1900 * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128). 2052 * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128).
@@ -2087,15 +2239,17 @@ static void quirk_p64h2_1k_io(struct pci_dev *dev)
2087 dev->io_window_1k = 1; 2239 dev->io_window_1k = 1;
2088 } 2240 }
2089} 2241}
2090DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io); 2242DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
2091 2243
2092/* Under some circumstances, AER is not linked with extended capabilities. 2244/*
2245 * Under some circumstances, AER is not linked with extended capabilities.
2093 * Force it to be linked by setting the corresponding control bit in the 2246 * Force it to be linked by setting the corresponding control bit in the
2094 * config space. 2247 * config space.
2095 */ 2248 */
2096static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev) 2249static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
2097{ 2250{
2098 uint8_t b; 2251 uint8_t b;
2252
2099 if (pci_read_config_byte(dev, 0xf41, &b) == 0) { 2253 if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
2100 if (!(b & 0x20)) { 2254 if (!(b & 0x20)) {
2101 pci_write_config_byte(dev, 0xf41, b | 0x20); 2255 pci_write_config_byte(dev, 0xf41, b | 0x20);
@@ -2125,8 +2279,10 @@ static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
2125 PCI_DEVICE_ID_VIA_8235_USB_2, NULL); 2279 PCI_DEVICE_ID_VIA_8235_USB_2, NULL);
2126 uint8_t b; 2280 uint8_t b;
2127 2281
2128 /* p should contain the first (internal) VT6212L -- see if we have 2282 /*
2129 an external one by searching again */ 2283 * p should contain the first (internal) VT6212L -- see if we have
2284 * an external one by searching again.
2285 */
2130 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p); 2286 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p);
2131 if (!p) 2287 if (!p)
2132 return; 2288 return;
@@ -2171,7 +2327,6 @@ static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev)
2171 pcie_set_readrq(dev, 2048); 2327 pcie_set_readrq(dev, 2048);
2172 } 2328 }
2173} 2329}
2174
2175DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM, 2330DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM,
2176 PCI_DEVICE_ID_TIGON3_5719, 2331 PCI_DEVICE_ID_TIGON3_5719,
2177 quirk_brcm_5719_limit_mrrs); 2332 quirk_brcm_5719_limit_mrrs);
@@ -2179,14 +2334,16 @@ DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM,
2179#ifdef CONFIG_PCIE_IPROC_PLATFORM 2334#ifdef CONFIG_PCIE_IPROC_PLATFORM
2180static void quirk_paxc_bridge(struct pci_dev *pdev) 2335static void quirk_paxc_bridge(struct pci_dev *pdev)
2181{ 2336{
2182 /* The PCI config space is shared with the PAXC root port and the first 2337 /*
2338 * The PCI config space is shared with the PAXC root port and the first
2183 * Ethernet device. So, we need to workaround this by telling the PCI 2339 * Ethernet device. So, we need to workaround this by telling the PCI
2184 * code that the bridge is not an Ethernet device. 2340 * code that the bridge is not an Ethernet device.
2185 */ 2341 */
2186 if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE) 2342 if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE)
2187 pdev->class = PCI_CLASS_BRIDGE_PCI << 8; 2343 pdev->class = PCI_CLASS_BRIDGE_PCI << 8;
2188 2344
2189 /* MPSS is not being set properly (as it is currently 0). This is 2345 /*
2346 * MPSS is not being set properly (as it is currently 0). This is
2190 * because that area of the PCI config space is hard coded to zero, and 2347 * because that area of the PCI config space is hard coded to zero, and
2191 * is not modifiable by firmware. Set this to 2 (e.g., 512 byte MPS) 2348 * is not modifiable by firmware. Set this to 2 (e.g., 512 byte MPS)
2192 * so that the MPS can be set to the real max value. 2349 * so that the MPS can be set to the real max value.
@@ -2197,10 +2354,10 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16cd, quirk_paxc_bridge);
2197DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16f0, quirk_paxc_bridge); 2354DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16f0, quirk_paxc_bridge);
2198#endif 2355#endif
2199 2356
2200/* Originally in EDAC sources for i82875P: 2357/*
2201 * Intel tells BIOS developers to hide device 6 which 2358 * Originally in EDAC sources for i82875P: Intel tells BIOS developers to
2202 * configures the overflow device access containing 2359 * hide device 6 which configures the overflow device access containing the
2203 * the DRBs - this is where we expose device 6. 2360 * DRBs - this is where we expose device 6.
2204 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm 2361 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
2205 */ 2362 */
2206static void quirk_unhide_mch_dev6(struct pci_dev *dev) 2363static void quirk_unhide_mch_dev6(struct pci_dev *dev)
@@ -2212,18 +2369,18 @@ static void quirk_unhide_mch_dev6(struct pci_dev *dev)
2212 pci_write_config_byte(dev, 0xF4, reg | 0x02); 2369 pci_write_config_byte(dev, 0xF4, reg | 0x02);
2213 } 2370 }
2214} 2371}
2215
2216DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, 2372DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB,
2217 quirk_unhide_mch_dev6); 2373 quirk_unhide_mch_dev6);
2218DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, 2374DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB,
2219 quirk_unhide_mch_dev6); 2375 quirk_unhide_mch_dev6);
2220 2376
2221#ifdef CONFIG_PCI_MSI 2377#ifdef CONFIG_PCI_MSI
2222/* Some chipsets do not support MSI. We cannot easily rely on setting 2378/*
2223 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually 2379 * Some chipsets do not support MSI. We cannot easily rely on setting
2224 * some other buses controlled by the chipset even if Linux is not 2380 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually some
2225 * aware of it. Instead of setting the flag on all buses in the 2381 * other buses controlled by the chipset even if Linux is not aware of it.
2226 * machine, simply disable MSI globally. 2382 * Instead of setting the flag on all buses in the machine, simply disable
2383 * MSI globally.
2227 */ 2384 */
2228static void quirk_disable_all_msi(struct pci_dev *dev) 2385static void quirk_disable_all_msi(struct pci_dev *dev)
2229{ 2386{
@@ -2271,8 +2428,10 @@ static void quirk_amd_780_apc_msi(struct pci_dev *host_bridge)
2271DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi); 2428DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi);
2272DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi); 2429DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi);
2273 2430
2274/* Go through the list of Hypertransport capabilities and 2431/*
2275 * return 1 if a HT MSI capability is found and enabled */ 2432 * Go through the list of HyperTransport capabilities and return 1 if a HT
2433 * MSI capability is found and enabled.
2434 */
2276static int msi_ht_cap_enabled(struct pci_dev *dev) 2435static int msi_ht_cap_enabled(struct pci_dev *dev)
2277{ 2436{
2278 int pos, ttl = PCI_FIND_CAP_TTL; 2437 int pos, ttl = PCI_FIND_CAP_TTL;
@@ -2295,7 +2454,7 @@ static int msi_ht_cap_enabled(struct pci_dev *dev)
2295 return 0; 2454 return 0;
2296} 2455}
2297 2456
2298/* Check the hypertransport MSI mapping to know whether MSI is enabled or not */ 2457/* Check the HyperTransport MSI mapping to know whether MSI is enabled or not */
2299static void quirk_msi_ht_cap(struct pci_dev *dev) 2458static void quirk_msi_ht_cap(struct pci_dev *dev)
2300{ 2459{
2301 if (dev->subordinate && !msi_ht_cap_enabled(dev)) { 2460 if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
@@ -2306,8 +2465,9 @@ static void quirk_msi_ht_cap(struct pci_dev *dev)
2306DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE, 2465DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
2307 quirk_msi_ht_cap); 2466 quirk_msi_ht_cap);
2308 2467
2309/* The nVidia CK804 chipset may have 2 HT MSI mappings. 2468/*
2310 * MSI are supported if the MSI capability set in any of these mappings. 2469 * The nVidia CK804 chipset may have 2 HT MSI mappings. MSI is supported
2470 * if the MSI capability is set in any of these mappings.
2311 */ 2471 */
2312static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev) 2472static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
2313{ 2473{
@@ -2316,8 +2476,9 @@ static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
2316 if (!dev->subordinate) 2476 if (!dev->subordinate)
2317 return; 2477 return;
2318 2478
2319 /* check HT MSI cap on this chipset and the root one. 2479 /*
2320 * a single one having MSI is enough to be sure that MSI are supported. 2480 * Check HT MSI cap on this chipset and the root one. A single one
2481 * having MSI is enough to be sure that MSI is supported.
2321 */ 2482 */
2322 pdev = pci_get_slot(dev->bus, 0); 2483 pdev = pci_get_slot(dev->bus, 0);
2323 if (!pdev) 2484 if (!pdev)
@@ -2354,13 +2515,13 @@ static void ht_enable_msi_mapping(struct pci_dev *dev)
2354DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, 2515DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
2355 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB, 2516 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
2356 ht_enable_msi_mapping); 2517 ht_enable_msi_mapping);
2357
2358DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, 2518DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE,
2359 ht_enable_msi_mapping); 2519 ht_enable_msi_mapping);
2360 2520
2361/* The P5N32-SLI motherboards from Asus have a problem with msi 2521/*
2362 * for the MCP55 NIC. It is not yet determined whether the msi problem 2522 * The P5N32-SLI motherboards from Asus have a problem with MSI
2363 * also affects other devices. As for now, turn off msi for this device. 2523 * for the MCP55 NIC. It is not yet determined whether the MSI problem
2524 * also affects other devices. As for now, turn off MSI for this device.
2364 */ 2525 */
2365static void nvenet_msi_disable(struct pci_dev *dev) 2526static void nvenet_msi_disable(struct pci_dev *dev)
2366{ 2527{
@@ -2397,16 +2558,14 @@ static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev)
2397 pci_read_config_dword(dev, 0x74, &cfg); 2558 pci_read_config_dword(dev, 0x74, &cfg);
2398 2559
2399 if (cfg & ((1 << 2) | (1 << 15))) { 2560 if (cfg & ((1 << 2) | (1 << 15))) {
2400 printk(KERN_INFO "Rewriting irq routing register on MCP55\n"); 2561 printk(KERN_INFO "Rewriting IRQ routing register on MCP55\n");
2401 cfg &= ~((1 << 2) | (1 << 15)); 2562 cfg &= ~((1 << 2) | (1 << 15));
2402 pci_write_config_dword(dev, 0x74, cfg); 2563 pci_write_config_dword(dev, 0x74, cfg);
2403 } 2564 }
2404} 2565}
2405
2406DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2566DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2407 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0, 2567 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0,
2408 nvbridge_check_legacy_irq_routing); 2568 nvbridge_check_legacy_irq_routing);
2409
2410DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2569DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2411 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4, 2570 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4,
2412 nvbridge_check_legacy_irq_routing); 2571 nvbridge_check_legacy_irq_routing);
@@ -2416,7 +2575,7 @@ static int ht_check_msi_mapping(struct pci_dev *dev)
2416 int pos, ttl = PCI_FIND_CAP_TTL; 2575 int pos, ttl = PCI_FIND_CAP_TTL;
2417 int found = 0; 2576 int found = 0;
2418 2577
2419 /* check if there is HT MSI cap or enabled on this device */ 2578 /* Check if there is HT MSI cap or enabled on this device */
2420 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2579 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2421 while (pos && ttl--) { 2580 while (pos && ttl--) {
2422 u8 flags; 2581 u8 flags;
@@ -2452,7 +2611,7 @@ static int host_bridge_with_leaf(struct pci_dev *host_bridge)
2452 if (!dev) 2611 if (!dev)
2453 continue; 2612 continue;
2454 2613
2455 /* found next host bridge ?*/ 2614 /* found next host bridge? */
2456 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); 2615 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2457 if (pos != 0) { 2616 if (pos != 0) {
2458 pci_dev_put(dev); 2617 pci_dev_put(dev);
@@ -2611,27 +2770,27 @@ static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev)
2611{ 2770{
2612 return __nv_msi_ht_cap_quirk(dev, 1); 2771 return __nv_msi_ht_cap_quirk(dev, 1);
2613} 2772}
2773DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2774DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2614 2775
2615static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev) 2776static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev)
2616{ 2777{
2617 return __nv_msi_ht_cap_quirk(dev, 0); 2778 return __nv_msi_ht_cap_quirk(dev, 0);
2618} 2779}
2619
2620DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf); 2780DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2621DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf); 2781DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2622 2782
2623DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2624DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2625
2626static void quirk_msi_intx_disable_bug(struct pci_dev *dev) 2783static void quirk_msi_intx_disable_bug(struct pci_dev *dev)
2627{ 2784{
2628 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 2785 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2629} 2786}
2787
2630static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev) 2788static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
2631{ 2789{
2632 struct pci_dev *p; 2790 struct pci_dev *p;
2633 2791
2634 /* SB700 MSI issue will be fixed at HW level from revision A21, 2792 /*
2793 * SB700 MSI issue will be fixed at HW level from revision A21;
2635 * we need check PCI REVISION ID of SMBus controller to get SB700 2794 * we need check PCI REVISION ID of SMBus controller to get SB700
2636 * revision. 2795 * revision.
2637 */ 2796 */
@@ -2644,6 +2803,7 @@ static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
2644 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 2803 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2645 pci_dev_put(p); 2804 pci_dev_put(p);
2646} 2805}
2806
2647static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev) 2807static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev)
2648{ 2808{
2649 /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */ 2809 /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */
@@ -2713,55 +2873,56 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091,
2713 quirk_msi_intx_disable_qca_bug); 2873 quirk_msi_intx_disable_qca_bug);
2714#endif /* CONFIG_PCI_MSI */ 2874#endif /* CONFIG_PCI_MSI */
2715 2875
2716/* Allow manual resource allocation for PCI hotplug bridges 2876/*
2717 * via pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For 2877 * Allow manual resource allocation for PCI hotplug bridges via
2718 * some PCI-PCI hotplug bridges, like PLX 6254 (former HINT HB6), 2878 * pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For some PCI-PCI
2719 * kernel fails to allocate resources when hotplug device is 2879 * hotplug bridges, like PLX 6254 (former HINT HB6), kernel fails to
2720 * inserted and PCI bus is rescanned. 2880 * allocate resources when hotplug device is inserted and PCI bus is
2881 * rescanned.
2721 */ 2882 */
2722static void quirk_hotplug_bridge(struct pci_dev *dev) 2883static void quirk_hotplug_bridge(struct pci_dev *dev)
2723{ 2884{
2724 dev->is_hotplug_bridge = 1; 2885 dev->is_hotplug_bridge = 1;
2725} 2886}
2726
2727DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge); 2887DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge);
2728 2888
2729/* 2889/*
2730 * This is a quirk for the Ricoh MMC controller found as a part of 2890 * This is a quirk for the Ricoh MMC controller found as a part of some
2731 * some mulifunction chips. 2891 * multifunction chips.
2732 2892 *
2733 * This is very similar and based on the ricoh_mmc driver written by 2893 * This is very similar and based on the ricoh_mmc driver written by
2734 * Philip Langdale. Thank you for these magic sequences. 2894 * Philip Langdale. Thank you for these magic sequences.
2735 * 2895 *
2736 * These chips implement the four main memory card controllers (SD, MMC, MS, xD) 2896 * These chips implement the four main memory card controllers (SD, MMC,
2737 * and one or both of cardbus or firewire. 2897 * MS, xD) and one or both of CardBus or FireWire.
2738 * 2898 *
2739 * It happens that they implement SD and MMC 2899 * It happens that they implement SD and MMC support as separate
2740 * support as separate controllers (and PCI functions). The linux SDHCI 2900 * controllers (and PCI functions). The Linux SDHCI driver supports MMC
2741 * driver supports MMC cards but the chip detects MMC cards in hardware 2901 * cards but the chip detects MMC cards in hardware and directs them to the
2742 * and directs them to the MMC controller - so the SDHCI driver never sees 2902 * MMC controller - so the SDHCI driver never sees them.
2743 * them.
2744 * 2903 *
2745 * To get around this, we must disable the useless MMC controller. 2904 * To get around this, we must disable the useless MMC controller. At that
2746 * At that point, the SDHCI controller will start seeing them 2905 * point, the SDHCI controller will start seeing them. It seems to be the
2747 * It seems to be the case that the relevant PCI registers to deactivate the 2906 * case that the relevant PCI registers to deactivate the MMC controller
2748 * MMC controller live on PCI function 0, which might be the cardbus controller 2907 * live on PCI function 0, which might be the CardBus controller or the
2749 * or the firewire controller, depending on the particular chip in question 2908 * FireWire controller, depending on the particular chip in question
2750 * 2909 *
2751 * This has to be done early, because as soon as we disable the MMC controller 2910 * This has to be done early, because as soon as we disable the MMC controller
2752 * other pci functions shift up one level, e.g. function #2 becomes function 2911 * other PCI functions shift up one level, e.g. function #2 becomes function
2753 * #1, and this will confuse the pci core. 2912 * #1, and this will confuse the PCI core.
2754 */ 2913 */
2755
2756#ifdef CONFIG_MMC_RICOH_MMC 2914#ifdef CONFIG_MMC_RICOH_MMC
2757static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev) 2915static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev)
2758{ 2916{
2759 /* disable via cardbus interface */
2760 u8 write_enable; 2917 u8 write_enable;
2761 u8 write_target; 2918 u8 write_target;
2762 u8 disable; 2919 u8 disable;
2763 2920
2764 /* disable must be done via function #0 */ 2921 /*
2922 * Disable via CardBus interface
2923 *
2924 * This must be done via function #0
2925 */
2765 if (PCI_FUNC(dev->devfn)) 2926 if (PCI_FUNC(dev->devfn))
2766 return; 2927 return;
2767 2928
@@ -2777,7 +2938,7 @@ static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev)
2777 pci_write_config_byte(dev, 0x8E, write_enable); 2938 pci_write_config_byte(dev, 0x8E, write_enable);
2778 pci_write_config_byte(dev, 0x8D, write_target); 2939 pci_write_config_byte(dev, 0x8D, write_target);
2779 2940
2780 pci_notice(dev, "proprietary Ricoh MMC controller disabled (via cardbus function)\n"); 2941 pci_notice(dev, "proprietary Ricoh MMC controller disabled (via CardBus function)\n");
2781 pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n"); 2942 pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n");
2782} 2943}
2783DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476); 2944DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
@@ -2785,17 +2946,20 @@ DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476,
2785 2946
2786static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev) 2947static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev)
2787{ 2948{
2788 /* disable via firewire interface */
2789 u8 write_enable; 2949 u8 write_enable;
2790 u8 disable; 2950 u8 disable;
2791 2951
2792 /* disable must be done via function #0 */ 2952 /*
2953 * Disable via FireWire interface
2954 *
2955 * This must be done via function #0
2956 */
2793 if (PCI_FUNC(dev->devfn)) 2957 if (PCI_FUNC(dev->devfn))
2794 return; 2958 return;
2795 /* 2959 /*
2796 * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize 2960 * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize
2797 * certain types of SD/MMC cards. Lowering the SD base 2961 * certain types of SD/MMC cards. Lowering the SD base clock
2798 * clock frequency from 200Mhz to 50Mhz fixes this issue. 2962 * frequency from 200Mhz to 50Mhz fixes this issue.
2799 * 2963 *
2800 * 0x150 - SD2.0 mode enable for changing base clock 2964 * 0x150 - SD2.0 mode enable for changing base clock
2801 * frequency to 50Mhz 2965 * frequency to 50Mhz
@@ -2826,7 +2990,7 @@ static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev)
2826 pci_write_config_byte(dev, 0xCB, disable | 0x02); 2990 pci_write_config_byte(dev, 0xCB, disable | 0x02);
2827 pci_write_config_byte(dev, 0xCA, write_enable); 2991 pci_write_config_byte(dev, 0xCA, write_enable);
2828 2992
2829 pci_notice(dev, "proprietary Ricoh MMC controller disabled (via firewire function)\n"); 2993 pci_notice(dev, "proprietary Ricoh MMC controller disabled (via FireWire function)\n");
2830 pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n"); 2994 pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n");
2831 2995
2832} 2996}
@@ -2842,13 +3006,13 @@ DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823,
2842#define VTUNCERRMSK_REG 0x1ac 3006#define VTUNCERRMSK_REG 0x1ac
2843#define VTD_MSK_SPEC_ERRORS (1 << 31) 3007#define VTD_MSK_SPEC_ERRORS (1 << 31)
2844/* 3008/*
2845 * This is a quirk for masking vt-d spec defined errors to platform error 3009 * This is a quirk for masking VT-d spec-defined errors to platform error
2846 * handling logic. With out this, platforms using Intel 7500, 5500 chipsets 3010 * handling logic. Without this, platforms using Intel 7500, 5500 chipsets
2847 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based 3011 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based
2848 * on the RAS config settings of the platform) when a vt-d fault happens. 3012 * on the RAS config settings of the platform) when a VT-d fault happens.
2849 * The resulting SMI caused the system to hang. 3013 * The resulting SMI caused the system to hang.
2850 * 3014 *
2851 * VT-d spec related errors are already handled by the VT-d OS code, so no 3015 * VT-d spec-related errors are already handled by the VT-d OS code, so no
2852 * need to report the same error through other channels. 3016 * need to report the same error through other channels.
2853 */ 3017 */
2854static void vtd_mask_spec_errors(struct pci_dev *dev) 3018static void vtd_mask_spec_errors(struct pci_dev *dev)
@@ -2874,7 +3038,8 @@ static void fixup_ti816x_class(struct pci_dev *dev)
2874DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800, 3038DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800,
2875 PCI_CLASS_NOT_DEFINED, 8, fixup_ti816x_class); 3039 PCI_CLASS_NOT_DEFINED, 8, fixup_ti816x_class);
2876 3040
2877/* Some PCIe devices do not work reliably with the claimed maximum 3041/*
3042 * Some PCIe devices do not work reliably with the claimed maximum
2878 * payload size supported. 3043 * payload size supported.
2879 */ 3044 */
2880static void fixup_mpss_256(struct pci_dev *dev) 3045static void fixup_mpss_256(struct pci_dev *dev)
@@ -2888,9 +3053,10 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2888DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE, 3053DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2889 PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256); 3054 PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256);
2890 3055
2891/* Intel 5000 and 5100 Memory controllers have an errata with read completion 3056/*
3057 * Intel 5000 and 5100 Memory controllers have an erratum with read completion
2892 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B. 3058 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B.
2893 * Since there is no way of knowing what the PCIE MPS on each fabric will be 3059 * Since there is no way of knowing what the PCIe MPS on each fabric will be
2894 * until all of the devices are discovered and buses walked, read completion 3060 * until all of the devices are discovered and buses walked, read completion
2895 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because 3061 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because
2896 * it is possible to hotplug a device with MPS of 256B. 3062 * it is possible to hotplug a device with MPS of 256B.
@@ -2904,9 +3070,10 @@ static void quirk_intel_mc_errata(struct pci_dev *dev)
2904 pcie_bus_config == PCIE_BUS_DEFAULT) 3070 pcie_bus_config == PCIE_BUS_DEFAULT)
2905 return; 3071 return;
2906 3072
2907 /* Intel errata specifies bits to change but does not say what they are. 3073 /*
2908 * Keeping them magical until such time as the registers and values can 3074 * Intel erratum specifies bits to change but does not say what
2909 * be explained. 3075 * they are. Keeping them magical until such time as the registers
3076 * and values can be explained.
2910 */ 3077 */
2911 err = pci_read_config_word(dev, 0x48, &rcc); 3078 err = pci_read_config_word(dev, 0x48, &rcc);
2912 if (err) { 3079 if (err) {
@@ -2925,7 +3092,7 @@ static void quirk_intel_mc_errata(struct pci_dev *dev)
2925 return; 3092 return;
2926 } 3093 }
2927 3094
2928 pr_info_once("Read completion coalescing disabled due to hardware errata relating to 256B MPS\n"); 3095 pr_info_once("Read completion coalescing disabled due to hardware erratum relating to 256B MPS\n");
2929} 3096}
2930/* Intel 5000 series memory controllers and ports 2-7 */ 3097/* Intel 5000 series memory controllers and ports 2-7 */
2931DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata); 3098DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata);
@@ -2955,11 +3122,10 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata);
2955DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata); 3122DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata);
2956DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata); 3123DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata);
2957 3124
2958
2959/* 3125/*
2960 * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum. To 3126 * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum.
2961 * work around this, query the size it should be configured to by the device and 3127 * To work around this, query the size it should be configured to by the
2962 * modify the resource end to correspond to this new size. 3128 * device and modify the resource end to correspond to this new size.
2963 */ 3129 */
2964static void quirk_intel_ntb(struct pci_dev *dev) 3130static void quirk_intel_ntb(struct pci_dev *dev)
2965{ 3131{
@@ -2981,39 +3147,17 @@ static void quirk_intel_ntb(struct pci_dev *dev)
2981DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb); 3147DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb);
2982DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb); 3148DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb);
2983 3149
2984static ktime_t fixup_debug_start(struct pci_dev *dev,
2985 void (*fn)(struct pci_dev *dev))
2986{
2987 if (initcall_debug)
2988 pci_info(dev, "calling %pF @ %i\n", fn, task_pid_nr(current));
2989
2990 return ktime_get();
2991}
2992
2993static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime,
2994 void (*fn)(struct pci_dev *dev))
2995{
2996 ktime_t delta, rettime;
2997 unsigned long long duration;
2998
2999 rettime = ktime_get();
3000 delta = ktime_sub(rettime, calltime);
3001 duration = (unsigned long long) ktime_to_ns(delta) >> 10;
3002 if (initcall_debug || duration > 10000)
3003 pci_info(dev, "%pF took %lld usecs\n", fn, duration);
3004}
3005
3006/* 3150/*
3007 * Some BIOS implementations leave the Intel GPU interrupts enabled, 3151 * Some BIOS implementations leave the Intel GPU interrupts enabled, even
3008 * even though no one is handling them (f.e. i915 driver is never loaded). 3152 * though no one is handling them (e.g., if the i915 driver is never
3009 * Additionally the interrupt destination is not set up properly 3153 * loaded). Additionally the interrupt destination is not set up properly
3010 * and the interrupt ends up -somewhere-. 3154 * and the interrupt ends up -somewhere-.
3011 * 3155 *
3012 * These spurious interrupts are "sticky" and the kernel disables 3156 * These spurious interrupts are "sticky" and the kernel disables the
3013 * the (shared) interrupt line after 100.000+ generated interrupts. 3157 * (shared) interrupt line after 100,000+ generated interrupts.
3014 * 3158 *
3015 * Fix it by disabling the still enabled interrupts. 3159 * Fix it by disabling the still enabled interrupts. This resolves crashes
3016 * This resolves crashes often seen on monitor unplug. 3160 * often seen on monitor unplug.
3017 */ 3161 */
3018#define I915_DEIER_REG 0x4400c 3162#define I915_DEIER_REG 0x4400c
3019static void disable_igfx_irq(struct pci_dev *dev) 3163static void disable_igfx_irq(struct pci_dev *dev)
@@ -3101,38 +3245,22 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REALTEK, 0x8169,
3101 * Intel i40e (XL710/X710) 10/20/40GbE NICs all have broken INTx masking, 3245 * Intel i40e (XL710/X710) 10/20/40GbE NICs all have broken INTx masking,
3102 * DisINTx can be set but the interrupt status bit is non-functional. 3246 * DisINTx can be set but the interrupt status bit is non-functional.
3103 */ 3247 */
3104DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1572, 3248DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1572, quirk_broken_intx_masking);
3105 quirk_broken_intx_masking); 3249DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1574, quirk_broken_intx_masking);
3106DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1574, 3250DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1580, quirk_broken_intx_masking);
3107 quirk_broken_intx_masking); 3251DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1581, quirk_broken_intx_masking);
3108DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1580, 3252DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1583, quirk_broken_intx_masking);
3109 quirk_broken_intx_masking); 3253DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1584, quirk_broken_intx_masking);
3110DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1581, 3254DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1585, quirk_broken_intx_masking);
3111 quirk_broken_intx_masking); 3255DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1586, quirk_broken_intx_masking);
3112DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1583, 3256DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1587, quirk_broken_intx_masking);
3113 quirk_broken_intx_masking); 3257DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1588, quirk_broken_intx_masking);
3114DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1584, 3258DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1589, quirk_broken_intx_masking);
3115 quirk_broken_intx_masking); 3259DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158a, quirk_broken_intx_masking);
3116DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1585, 3260DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158b, quirk_broken_intx_masking);
3117 quirk_broken_intx_masking); 3261DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d0, quirk_broken_intx_masking);
3118DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1586, 3262DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d1, quirk_broken_intx_masking);
3119 quirk_broken_intx_masking); 3263DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d2, quirk_broken_intx_masking);
3120DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1587,
3121 quirk_broken_intx_masking);
3122DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1588,
3123 quirk_broken_intx_masking);
3124DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1589,
3125 quirk_broken_intx_masking);
3126DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158a,
3127 quirk_broken_intx_masking);
3128DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158b,
3129 quirk_broken_intx_masking);
3130DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d0,
3131 quirk_broken_intx_masking);
3132DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d1,
3133 quirk_broken_intx_masking);
3134DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d2,
3135 quirk_broken_intx_masking);
3136 3264
3137static u16 mellanox_broken_intx_devs[] = { 3265static u16 mellanox_broken_intx_devs[] = {
3138 PCI_DEVICE_ID_MELLANOX_HERMON_SDR, 3266 PCI_DEVICE_ID_MELLANOX_HERMON_SDR,
@@ -3177,7 +3305,8 @@ static void mellanox_check_broken_intx_masking(struct pci_dev *pdev)
3177 } 3305 }
3178 } 3306 }
3179 3307
3180 /* Getting here means Connect-IB cards and up. Connect-IB has no INTx 3308 /*
3309 * Getting here means Connect-IB cards and up. Connect-IB has no INTx
3181 * support so shouldn't be checked further 3310 * support so shouldn't be checked further
3182 */ 3311 */
3183 if (pdev->device == PCI_DEVICE_ID_MELLANOX_CONNECTIB) 3312 if (pdev->device == PCI_DEVICE_ID_MELLANOX_CONNECTIB)
@@ -3297,8 +3426,8 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PORT_RIDGE,
3297 * shutdown before suspend. Otherwise the native host interface (NHI) will not 3426 * shutdown before suspend. Otherwise the native host interface (NHI) will not
3298 * be present after resume if a device was plugged in before suspend. 3427 * be present after resume if a device was plugged in before suspend.
3299 * 3428 *
3300 * The thunderbolt controller consists of a pcie switch with downstream 3429 * The Thunderbolt controller consists of a PCIe switch with downstream
3301 * bridges leading to the NHI and to the tunnel pci bridges. 3430 * bridges leading to the NHI and to the tunnel PCI bridges.
3302 * 3431 *
3303 * This quirk cuts power to the whole chip. Therefore we have to apply it 3432 * This quirk cuts power to the whole chip. Therefore we have to apply it
3304 * during suspend_noirq of the upstream bridge. 3433 * during suspend_noirq of the upstream bridge.
@@ -3316,17 +3445,19 @@ static void quirk_apple_poweroff_thunderbolt(struct pci_dev *dev)
3316 bridge = ACPI_HANDLE(&dev->dev); 3445 bridge = ACPI_HANDLE(&dev->dev);
3317 if (!bridge) 3446 if (!bridge)
3318 return; 3447 return;
3448
3319 /* 3449 /*
3320 * SXIO and SXLV are present only on machines requiring this quirk. 3450 * SXIO and SXLV are present only on machines requiring this quirk.
3321 * TB bridges in external devices might have the same device id as those 3451 * Thunderbolt bridges in external devices might have the same
3322 * on the host, but they will not have the associated ACPI methods. This 3452 * device ID as those on the host, but they will not have the
3323 * implicitly checks that we are at the right bridge. 3453 * associated ACPI methods. This implicitly checks that we are at
3454 * the right bridge.
3324 */ 3455 */
3325 if (ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXIO", &SXIO)) 3456 if (ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXIO", &SXIO))
3326 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXFP", &SXFP)) 3457 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXFP", &SXFP))
3327 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXLV", &SXLV))) 3458 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXLV", &SXLV)))
3328 return; 3459 return;
3329 pci_info(dev, "quirk: cutting power to thunderbolt controller...\n"); 3460 pci_info(dev, "quirk: cutting power to Thunderbolt controller...\n");
3330 3461
3331 /* magic sequence */ 3462 /* magic sequence */
3332 acpi_execute_simple_method(SXIO, NULL, 1); 3463 acpi_execute_simple_method(SXIO, NULL, 1);
@@ -3341,9 +3472,9 @@ DECLARE_PCI_FIXUP_SUSPEND_LATE(PCI_VENDOR_ID_INTEL,
3341 quirk_apple_poweroff_thunderbolt); 3472 quirk_apple_poweroff_thunderbolt);
3342 3473
3343/* 3474/*
3344 * Apple: Wait for the thunderbolt controller to reestablish pci tunnels. 3475 * Apple: Wait for the Thunderbolt controller to reestablish PCI tunnels
3345 * 3476 *
3346 * During suspend the thunderbolt controller is reset and all pci 3477 * During suspend the Thunderbolt controller is reset and all PCI
3347 * tunnels are lost. The NHI driver will try to reestablish all tunnels 3478 * tunnels are lost. The NHI driver will try to reestablish all tunnels
3348 * during resume. We have to manually wait for the NHI since there is 3479 * during resume. We have to manually wait for the NHI since there is
3349 * no parent child relationship between the NHI and the tunneled 3480 * no parent child relationship between the NHI and the tunneled
@@ -3358,9 +3489,10 @@ static void quirk_apple_wait_for_thunderbolt(struct pci_dev *dev)
3358 return; 3489 return;
3359 if (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM) 3490 if (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM)
3360 return; 3491 return;
3492
3361 /* 3493 /*
3362 * Find the NHI and confirm that we are a bridge on the tb host 3494 * Find the NHI and confirm that we are a bridge on the Thunderbolt
3363 * controller and not on a tb endpoint. 3495 * host controller and not on a Thunderbolt endpoint.
3364 */ 3496 */
3365 sibling = pci_get_slot(dev->bus, 0x0); 3497 sibling = pci_get_slot(dev->bus, 0x0);
3366 if (sibling == dev) 3498 if (sibling == dev)
@@ -3377,7 +3509,7 @@ static void quirk_apple_wait_for_thunderbolt(struct pci_dev *dev)
3377 nhi->device != PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI) 3509 nhi->device != PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI)
3378 || nhi->class != PCI_CLASS_SYSTEM_OTHER << 8) 3510 || nhi->class != PCI_CLASS_SYSTEM_OTHER << 8)
3379 goto out; 3511 goto out;
3380 pci_info(dev, "quirk: waiting for thunderbolt to reestablish PCI tunnels...\n"); 3512 pci_info(dev, "quirk: waiting for Thunderbolt to reestablish PCI tunnels...\n");
3381 device_pm_wait_for_dev(&dev->dev, &nhi->dev); 3513 device_pm_wait_for_dev(&dev->dev, &nhi->dev);
3382out: 3514out:
3383 pci_dev_put(nhi); 3515 pci_dev_put(nhi);
@@ -3397,142 +3529,6 @@ DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3397 quirk_apple_wait_for_thunderbolt); 3529 quirk_apple_wait_for_thunderbolt);
3398#endif 3530#endif
3399 3531
3400static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
3401 struct pci_fixup *end)
3402{
3403 ktime_t calltime;
3404
3405 for (; f < end; f++)
3406 if ((f->class == (u32) (dev->class >> f->class_shift) ||
3407 f->class == (u32) PCI_ANY_ID) &&
3408 (f->vendor == dev->vendor ||
3409 f->vendor == (u16) PCI_ANY_ID) &&
3410 (f->device == dev->device ||
3411 f->device == (u16) PCI_ANY_ID)) {
3412 calltime = fixup_debug_start(dev, f->hook);
3413 f->hook(dev);
3414 fixup_debug_report(dev, calltime, f->hook);
3415 }
3416}
3417
3418extern struct pci_fixup __start_pci_fixups_early[];
3419extern struct pci_fixup __end_pci_fixups_early[];
3420extern struct pci_fixup __start_pci_fixups_header[];
3421extern struct pci_fixup __end_pci_fixups_header[];
3422extern struct pci_fixup __start_pci_fixups_final[];
3423extern struct pci_fixup __end_pci_fixups_final[];
3424extern struct pci_fixup __start_pci_fixups_enable[];
3425extern struct pci_fixup __end_pci_fixups_enable[];
3426extern struct pci_fixup __start_pci_fixups_resume[];
3427extern struct pci_fixup __end_pci_fixups_resume[];
3428extern struct pci_fixup __start_pci_fixups_resume_early[];
3429extern struct pci_fixup __end_pci_fixups_resume_early[];
3430extern struct pci_fixup __start_pci_fixups_suspend[];
3431extern struct pci_fixup __end_pci_fixups_suspend[];
3432extern struct pci_fixup __start_pci_fixups_suspend_late[];
3433extern struct pci_fixup __end_pci_fixups_suspend_late[];
3434
3435static bool pci_apply_fixup_final_quirks;
3436
3437void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
3438{
3439 struct pci_fixup *start, *end;
3440
3441 switch (pass) {
3442 case pci_fixup_early:
3443 start = __start_pci_fixups_early;
3444 end = __end_pci_fixups_early;
3445 break;
3446
3447 case pci_fixup_header:
3448 start = __start_pci_fixups_header;
3449 end = __end_pci_fixups_header;
3450 break;
3451
3452 case pci_fixup_final:
3453 if (!pci_apply_fixup_final_quirks)
3454 return;
3455 start = __start_pci_fixups_final;
3456 end = __end_pci_fixups_final;
3457 break;
3458
3459 case pci_fixup_enable:
3460 start = __start_pci_fixups_enable;
3461 end = __end_pci_fixups_enable;
3462 break;
3463
3464 case pci_fixup_resume:
3465 start = __start_pci_fixups_resume;
3466 end = __end_pci_fixups_resume;
3467 break;
3468
3469 case pci_fixup_resume_early:
3470 start = __start_pci_fixups_resume_early;
3471 end = __end_pci_fixups_resume_early;
3472 break;
3473
3474 case pci_fixup_suspend:
3475 start = __start_pci_fixups_suspend;
3476 end = __end_pci_fixups_suspend;
3477 break;
3478
3479 case pci_fixup_suspend_late:
3480 start = __start_pci_fixups_suspend_late;
3481 end = __end_pci_fixups_suspend_late;
3482 break;
3483
3484 default:
3485 /* stupid compiler warning, you would think with an enum... */
3486 return;
3487 }
3488 pci_do_fixups(dev, start, end);
3489}
3490EXPORT_SYMBOL(pci_fixup_device);
3491
3492
3493static int __init pci_apply_final_quirks(void)
3494{
3495 struct pci_dev *dev = NULL;
3496 u8 cls = 0;
3497 u8 tmp;
3498
3499 if (pci_cache_line_size)
3500 printk(KERN_DEBUG "PCI: CLS %u bytes\n",
3501 pci_cache_line_size << 2);
3502
3503 pci_apply_fixup_final_quirks = true;
3504 for_each_pci_dev(dev) {
3505 pci_fixup_device(pci_fixup_final, dev);
3506 /*
3507 * If arch hasn't set it explicitly yet, use the CLS
3508 * value shared by all PCI devices. If there's a
3509 * mismatch, fall back to the default value.
3510 */
3511 if (!pci_cache_line_size) {
3512 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp);
3513 if (!cls)
3514 cls = tmp;
3515 if (!tmp || cls == tmp)
3516 continue;
3517
3518 printk(KERN_DEBUG "PCI: CLS mismatch (%u != %u), using %u bytes\n",
3519 cls << 2, tmp << 2,
3520 pci_dfl_cache_line_size << 2);
3521 pci_cache_line_size = pci_dfl_cache_line_size;
3522 }
3523 }
3524
3525 if (!pci_cache_line_size) {
3526 printk(KERN_DEBUG "PCI: CLS %u bytes, default %u\n",
3527 cls << 2, pci_dfl_cache_line_size << 2);
3528 pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size;
3529 }
3530
3531 return 0;
3532}
3533
3534fs_initcall_sync(pci_apply_final_quirks);
3535
3536/* 3532/*
3537 * Following are device-specific reset methods which can be used to 3533 * Following are device-specific reset methods which can be used to
3538 * reset a single function if other methods (e.g. FLR, PM D0->D3) are 3534 * reset a single function if other methods (e.g. FLR, PM D0->D3) are
@@ -3602,9 +3598,7 @@ reset_complete:
3602 return 0; 3598 return 0;
3603} 3599}
3604 3600
3605/* 3601/* Device-specific reset method for Chelsio T4-based adapters */
3606 * Device-specific reset method for Chelsio T4-based adapters.
3607 */
3608static int reset_chelsio_generic_dev(struct pci_dev *dev, int probe) 3602static int reset_chelsio_generic_dev(struct pci_dev *dev, int probe)
3609{ 3603{
3610 u16 old_command; 3604 u16 old_command;
@@ -3887,7 +3881,7 @@ DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, PCI_CLASS_NOT_DEFINED, 8,
3887/* 3881/*
3888 * Some devices have problems with Transaction Layer Packets with the Relaxed 3882 * Some devices have problems with Transaction Layer Packets with the Relaxed
3889 * Ordering Attribute set. Such devices should mark themselves and other 3883 * Ordering Attribute set. Such devices should mark themselves and other
3890 * Device Drivers should check before sending TLPs with RO set. 3884 * device drivers should check before sending TLPs with RO set.
3891 */ 3885 */
3892static void quirk_relaxedordering_disable(struct pci_dev *dev) 3886static void quirk_relaxedordering_disable(struct pci_dev *dev)
3893{ 3887{
@@ -3897,7 +3891,7 @@ static void quirk_relaxedordering_disable(struct pci_dev *dev)
3897 3891
3898/* 3892/*
3899 * Intel Xeon processors based on Broadwell/Haswell microarchitecture Root 3893 * Intel Xeon processors based on Broadwell/Haswell microarchitecture Root
3900 * Complex has a Flow Control Credit issue which can cause performance 3894 * Complex have a Flow Control Credit issue which can cause performance
3901 * problems with Upstream Transaction Layer Packets with Relaxed Ordering set. 3895 * problems with Upstream Transaction Layer Packets with Relaxed Ordering set.
3902 */ 3896 */
3903DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f01, PCI_CLASS_NOT_DEFINED, 8, 3897DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f01, PCI_CLASS_NOT_DEFINED, 8,
@@ -3958,7 +3952,7 @@ DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0e, PCI_CLASS_NOT_DEFINED
3958 quirk_relaxedordering_disable); 3952 quirk_relaxedordering_disable);
3959 3953
3960/* 3954/*
3961 * The AMD ARM A1100 (AKA "SEATTLE") SoC has a bug in its PCIe Root Complex 3955 * The AMD ARM A1100 (aka "SEATTLE") SoC has a bug in its PCIe Root Complex
3962 * where Upstream Transaction Layer Packets with the Relaxed Ordering 3956 * where Upstream Transaction Layer Packets with the Relaxed Ordering
3963 * Attribute clear are allowed to bypass earlier TLPs with Relaxed Ordering 3957 * Attribute clear are allowed to bypass earlier TLPs with Relaxed Ordering
3964 * set. This is a violation of the PCIe 3.0 Transaction Ordering Rules 3958 * set. This is a violation of the PCIe 3.0 Transaction Ordering Rules
@@ -4022,7 +4016,7 @@ static void quirk_chelsio_T5_disable_root_port_attributes(struct pci_dev *pdev)
4022 * This mask/compare operation selects for Physical Function 4 on a 4016 * This mask/compare operation selects for Physical Function 4 on a
4023 * T5. We only need to fix up the Root Port once for any of the 4017 * T5. We only need to fix up the Root Port once for any of the
4024 * PFs. PF[0..3] have PCI Device IDs of 0x50xx, but PF4 is uniquely 4018 * PFs. PF[0..3] have PCI Device IDs of 0x50xx, but PF4 is uniquely
4025 * 0x54xx so we use that one, 4019 * 0x54xx so we use that one.
4026 */ 4020 */
4027 if ((pdev->device & 0xff00) == 0x5400) 4021 if ((pdev->device & 0xff00) == 0x5400)
4028 quirk_disable_root_port_attributes(pdev); 4022 quirk_disable_root_port_attributes(pdev);
@@ -4113,7 +4107,7 @@ static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags)
4113static int pci_quirk_xgene_acs(struct pci_dev *dev, u16 acs_flags) 4107static int pci_quirk_xgene_acs(struct pci_dev *dev, u16 acs_flags)
4114{ 4108{
4115 /* 4109 /*
4116 * X-Gene root matching this quirk do not allow peer-to-peer 4110 * X-Gene Root Ports matching this quirk do not allow peer-to-peer
4117 * transactions with others, allowing masking out these bits as if they 4111 * transactions with others, allowing masking out these bits as if they
4118 * were unimplemented in the ACS capability. 4112 * were unimplemented in the ACS capability.
4119 */ 4113 */
@@ -4456,7 +4450,7 @@ static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev)
4456 /* 4450 /*
4457 * Read the RCBA register from the LPC (D31:F0). PCH root ports 4451 * Read the RCBA register from the LPC (D31:F0). PCH root ports
4458 * are D28:F* and therefore get probed before LPC, thus we can't 4452 * are D28:F* and therefore get probed before LPC, thus we can't
4459 * use pci_get_slot/pci_read_config_dword here. 4453 * use pci_get_slot()/pci_read_config_dword() here.
4460 */ 4454 */
4461 pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0), 4455 pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0),
4462 INTEL_LPC_RCBA_REG, &rcba); 4456 INTEL_LPC_RCBA_REG, &rcba);
@@ -4589,7 +4583,7 @@ int pci_dev_specific_enable_acs(struct pci_dev *dev)
4589} 4583}
4590 4584
4591/* 4585/*
4592 * The PCI capabilities list for Intel DH895xCC VFs (device id 0x0443) with 4586 * The PCI capabilities list for Intel DH895xCC VFs (device ID 0x0443) with
4593 * QuickAssist Technology (QAT) is prematurely terminated in hardware. The 4587 * QuickAssist Technology (QAT) is prematurely terminated in hardware. The
4594 * Next Capability pointer in the MSI Capability Structure should point to 4588 * Next Capability pointer in the MSI Capability Structure should point to
4595 * the PCIe Capability Structure but is incorrectly hardwired as 0 terminating 4589 * the PCIe Capability Structure but is incorrectly hardwired as 0 terminating
@@ -4650,9 +4644,7 @@ static void quirk_intel_qat_vf_cap(struct pci_dev *pdev)
4650 if (pci_find_saved_cap(pdev, PCI_CAP_ID_EXP)) 4644 if (pci_find_saved_cap(pdev, PCI_CAP_ID_EXP))
4651 return; 4645 return;
4652 4646
4653 /* 4647 /* Save PCIe cap */
4654 * Save PCIE cap
4655 */
4656 state = kzalloc(sizeof(*state) + size, GFP_KERNEL); 4648 state = kzalloc(sizeof(*state) + size, GFP_KERNEL);
4657 if (!state) 4649 if (!state)
4658 return; 4650 return;
@@ -4673,7 +4665,7 @@ static void quirk_intel_qat_vf_cap(struct pci_dev *pdev)
4673} 4665}
4674DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap); 4666DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap);
4675 4667
4676/* FLR may cause some 82579 devices to hang. */ 4668/* FLR may cause some 82579 devices to hang */
4677static void quirk_intel_no_flr(struct pci_dev *dev) 4669static void quirk_intel_no_flr(struct pci_dev *dev)
4678{ 4670{
4679 dev->dev_flags |= PCI_DEV_FLAGS_NO_FLR_RESET; 4671 dev->dev_flags |= PCI_DEV_FLAGS_NO_FLR_RESET;
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-26 02:43:48 -0400