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authorBjorn Helgaas <bhelgaas@google.com>2018-05-02 09:53:19 -0400
committerBjorn Helgaas <helgaas@kernel.org>2018-05-10 17:50:18 -0400
commit82e1719c4cd65bd7f7847d6c02376cfca3d5e793 (patch)
treeed0e8c028a78f52196fdce7af96eee2d4856db0c
parent780473508ace12fa58fb50339d3899c055ec4cad (diff)
PCI: Clean up whitespace in quirks.c
Clean up whitespace, capitalization, etc. in comments. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Diffstat
-rw-r--r--drivers/pci/quirks.c664
1 files changed, 329 insertions, 335 deletions
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 0f2b117cc59c..de7c77e2ebbd 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -199,9 +199,10 @@ static void quirk_mmio_always_on(struct pci_dev *dev)
199DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID, 199DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID,
200 PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on); 200 PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on);
201 201
202/* The Mellanox Tavor device gives false positive parity errors 202/*
203 * Mark this device with a broken_parity_status, to allow 203 * The Mellanox Tavor device gives false positive parity errors. Mark this
204 * PCI scanning code to "skip" this now blacklisted device. 204 * device with a broken_parity_status to allow PCI scanning code to "skip"
205 * this now blacklisted device.
205 */ 206 */
206static void quirk_mellanox_tavor(struct pci_dev *dev) 207static void quirk_mellanox_tavor(struct pci_dev *dev)
207{ 208{
@@ -210,15 +211,19 @@ static void quirk_mellanox_tavor(struct pci_dev *dev)
210DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR, quirk_mellanox_tavor); 211DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR, quirk_mellanox_tavor);
211DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE, quirk_mellanox_tavor); 212DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE, quirk_mellanox_tavor);
212 213
213/* Deal with broken BIOSes that neglect to enable passive release, 214/*
214 which can cause problems in combination with the 82441FX/PPro MTRRs */ 215 * Deal with broken BIOSes that neglect to enable passive release,
216 * which can cause problems in combination with the 82441FX/PPro MTRRs
217 */
215static void quirk_passive_release(struct pci_dev *dev) 218static void quirk_passive_release(struct pci_dev *dev)
216{ 219{
217 struct pci_dev *d = NULL; 220 struct pci_dev *d = NULL;
218 unsigned char dlc; 221 unsigned char dlc;
219 222
220 /* We have to make sure a particular bit is set in the PIIX3 223 /*
221 ISA bridge, so we have to go out and find it. */ 224 * We have to make sure a particular bit is set in the PIIX3
225 * ISA bridge, so we have to go out and find it.
226 */
222 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) { 227 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
223 pci_read_config_byte(d, 0x82, &dlc); 228 pci_read_config_byte(d, 0x82, &dlc);
224 if (!(dlc & 1<<1)) { 229 if (!(dlc & 1<<1)) {
@@ -231,13 +236,14 @@ static void quirk_passive_release(struct pci_dev *dev)
231DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); 236DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
232DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); 237DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
233 238
234/* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround 239/*
235 but VIA don't answer queries. If you happen to have good contacts at VIA 240 * The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a
236 ask them for me please -- Alan 241 * workaround but VIA don't answer queries. If you happen to have good
237 242 * contacts at VIA ask them for me please -- Alan
238 This appears to be BIOS not version dependent. So presumably there is a 243 *
239 chipset level fix */ 244 * This appears to be BIOS not version dependent. So presumably there is a
240 245 * chipset level fix.
246 */
241static void quirk_isa_dma_hangs(struct pci_dev *dev) 247static void quirk_isa_dma_hangs(struct pci_dev *dev)
242{ 248{
243 if (!isa_dma_bridge_buggy) { 249 if (!isa_dma_bridge_buggy) {
@@ -245,10 +251,10 @@ static void quirk_isa_dma_hangs(struct pci_dev *dev)
245 pci_info(dev, "Activating ISA DMA hang workarounds\n"); 251 pci_info(dev, "Activating ISA DMA hang workarounds\n");
246 } 252 }
247} 253}
248 /* 254/*
249 * Its not totally clear which chipsets are the problematic ones 255 * It's not totally clear which chipsets are the problematic ones. We know
250 * We know 82C586 and 82C596 variants are affected. 256 * 82C586 and 82C596 variants are affected.
251 */ 257 */
252DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs); 258DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs);
253DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs); 259DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs);
254DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs); 260DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs);
@@ -277,9 +283,7 @@ static void quirk_tigerpoint_bm_sts(struct pci_dev *dev)
277} 283}
278DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts); 284DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts);
279 285
280/* 286/* Chipsets where PCI->PCI transfers vanish or hang */
281 * Chipsets where PCI->PCI transfers vanish or hang
282 */
283static void quirk_nopcipci(struct pci_dev *dev) 287static void quirk_nopcipci(struct pci_dev *dev)
284{ 288{
285 if ((pci_pci_problems & PCIPCI_FAIL) == 0) { 289 if ((pci_pci_problems & PCIPCI_FAIL) == 0) {
@@ -302,9 +306,7 @@ static void quirk_nopciamd(struct pci_dev *dev)
302} 306}
303DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd); 307DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd);
304 308
305/* 309/* Triton requires workarounds to be used by the drivers */
306 * Triton requires workarounds to be used by the drivers
307 */
308static void quirk_triton(struct pci_dev *dev) 310static void quirk_triton(struct pci_dev *dev)
309{ 311{
310 if ((pci_pci_problems&PCIPCI_TRITON) == 0) { 312 if ((pci_pci_problems&PCIPCI_TRITON) == 0) {
@@ -318,53 +320,62 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_tr
318DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton); 320DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton);
319 321
320/* 322/*
321 * VIA Apollo KT133 needs PCI latency patch 323 * VIA Apollo KT133 needs PCI latency patch
322 * Made according to a windows driver based patch by George E. Breese 324 * Made according to a Windows driver-based patch by George E. Breese;
323 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm 325 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
324 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for 326 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for the info on
325 * the info on which Mr Breese based his work. 327 * which Mr Breese based his work.
326 * 328 *
327 * Updated based on further information from the site and also on 329 * Updated based on further information from the site and also on
328 * information provided by VIA 330 * information provided by VIA
329 */ 331 */
330static void quirk_vialatency(struct pci_dev *dev) 332static void quirk_vialatency(struct pci_dev *dev)
331{ 333{
332 struct pci_dev *p; 334 struct pci_dev *p;
333 u8 busarb; 335 u8 busarb;
334 /* Ok we have a potential problem chipset here. Now see if we have
335 a buggy southbridge */
336 336
337 /*
338 * Ok, we have a potential problem chipset here. Now see if we have
339 * a buggy southbridge.
340 */
337 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL); 341 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
338 if (p != NULL) { 342 if (p != NULL) {
339 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */ 343
340 /* Check for buggy part revisions */ 344 /*
345 * 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A;
346 * thanks Dan Hollis.
347 * Check for buggy part revisions
348 */
341 if (p->revision < 0x40 || p->revision > 0x42) 349 if (p->revision < 0x40 || p->revision > 0x42)
342 goto exit; 350 goto exit;
343 } else { 351 } else {
344 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL); 352 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
345 if (p == NULL) /* No problem parts */ 353 if (p == NULL) /* No problem parts */
346 goto exit; 354 goto exit;
355
347 /* Check for buggy part revisions */ 356 /* Check for buggy part revisions */
348 if (p->revision < 0x10 || p->revision > 0x12) 357 if (p->revision < 0x10 || p->revision > 0x12)
349 goto exit; 358 goto exit;
350 } 359 }
351 360
352 /* 361 /*
353 * Ok we have the problem. Now set the PCI master grant to 362 * Ok we have the problem. Now set the PCI master grant to occur
354 * occur every master grant. The apparent bug is that under high 363 * every master grant. The apparent bug is that under high PCI load
355 * PCI load (quite common in Linux of course) you can get data 364 * (quite common in Linux of course) you can get data loss when the
356 * loss when the CPU is held off the bus for 3 bus master requests 365 * CPU is held off the bus for 3 bus master requests. This happens
357 * This happens to include the IDE controllers.... 366 * to include the IDE controllers....
358 * 367 *
359 * VIA only apply this fix when an SB Live! is present but under 368 * VIA only apply this fix when an SB Live! is present but under
360 * both Linux and Windows this isn't enough, and we have seen 369 * both Linux and Windows this isn't enough, and we have seen
361 * corruption without SB Live! but with things like 3 UDMA IDE 370 * corruption without SB Live! but with things like 3 UDMA IDE
362 * controllers. So we ignore that bit of the VIA recommendation.. 371 * controllers. So we ignore that bit of the VIA recommendation..
363 */ 372 */
364
365 pci_read_config_byte(dev, 0x76, &busarb); 373 pci_read_config_byte(dev, 0x76, &busarb);
366 /* Set bit 4 and bi 5 of byte 76 to 0x01 374
367 "Master priority rotation on every PCI master grant */ 375 /*
376 * Set bit 4 and bit 5 of byte 76 to 0x01
377 * "Master priority rotation on every PCI master grant"
378 */
368 busarb &= ~(1<<5); 379 busarb &= ~(1<<5);
369 busarb |= (1<<4); 380 busarb |= (1<<4);
370 pci_write_config_byte(dev, 0x76, busarb); 381 pci_write_config_byte(dev, 0x76, busarb);
@@ -380,9 +391,7 @@ DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vial
380DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency); 391DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
381DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency); 392DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
382 393
383/* 394/* VIA Apollo VP3 needs ETBF on BT848/878 */
384 * VIA Apollo VP3 needs ETBF on BT848/878
385 */
386static void quirk_viaetbf(struct pci_dev *dev) 395static void quirk_viaetbf(struct pci_dev *dev)
387{ 396{
388 if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) { 397 if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) {
@@ -402,10 +411,9 @@ static void quirk_vsfx(struct pci_dev *dev)
402DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx); 411DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx);
403 412
404/* 413/*
405 * Ali Magik requires workarounds to be used by the drivers 414 * ALi Magik requires workarounds to be used by the drivers that DMA to AGP
406 * that DMA to AGP space. Latency must be set to 0xA and triton 415 * space. Latency must be set to 0xA and Triton workaround applied too.
407 * workaround applied too 416 * [Info kindly provided by ALi]
408 * [Info kindly provided by ALi]
409 */ 417 */
410static void quirk_alimagik(struct pci_dev *dev) 418static void quirk_alimagik(struct pci_dev *dev)
411{ 419{
@@ -417,10 +425,7 @@ static void quirk_alimagik(struct pci_dev *dev)
417DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik); 425DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik);
418DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik); 426DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik);
419 427
420/* 428/* Natoma has some interesting boundary conditions with Zoran stuff at least */
421 * Natoma has some interesting boundary conditions with Zoran stuff
422 * at least
423 */
424static void quirk_natoma(struct pci_dev *dev) 429static void quirk_natoma(struct pci_dev *dev)
425{ 430{
426 if ((pci_pci_problems&PCIPCI_NATOMA) == 0) { 431 if ((pci_pci_problems&PCIPCI_NATOMA) == 0) {
@@ -436,8 +441,8 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quir
436DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma); 441DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma);
437 442
438/* 443/*
439 * This chip can cause PCI parity errors if config register 0xA0 is read 444 * This chip can cause PCI parity errors if config register 0xA0 is read
440 * while DMAs are occurring. 445 * while DMAs are occurring.
441 */ 446 */
442static void quirk_citrine(struct pci_dev *dev) 447static void quirk_citrine(struct pci_dev *dev)
443{ 448{
@@ -477,8 +482,8 @@ static void quirk_extend_bar_to_page(struct pci_dev *dev)
477DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, 0x034a, quirk_extend_bar_to_page); 482DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, 0x034a, quirk_extend_bar_to_page);
478 483
479/* 484/*
480 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M. 485 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
481 * If it's needed, re-allocate the region. 486 * If it's needed, re-allocate the region.
482 */ 487 */
483static void quirk_s3_64M(struct pci_dev *dev) 488static void quirk_s3_64M(struct pci_dev *dev)
484{ 489{
@@ -569,8 +574,8 @@ static void quirk_io_region(struct pci_dev *dev, int port,
569} 574}
570 575
571/* 576/*
572 * ATI Northbridge setups MCE the processor if you even 577 * ATI Northbridge setups MCE the processor if you even read somewhere
573 * read somewhere between 0x3b0->0x3bb or read 0x3d3 578 * between 0x3b0->0x3bb or read 0x3d3
574 */ 579 */
575static void quirk_ati_exploding_mce(struct pci_dev *dev) 580static void quirk_ati_exploding_mce(struct pci_dev *dev)
576{ 581{
@@ -585,6 +590,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_
585 * In the AMD NL platform, this device ([1022:7912]) has a class code of 590 * In the AMD NL platform, this device ([1022:7912]) has a class code of
586 * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will 591 * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will
587 * claim it. 592 * claim it.
593 *
588 * But the dwc3 driver is a more specific driver for this device, and we'd 594 * But the dwc3 driver is a more specific driver for this device, and we'd
589 * prefer to use it instead of xhci. To prevent xhci from claiming the 595 * prefer to use it instead of xhci. To prevent xhci from claiming the
590 * device, change the class code to 0x0c03fe, which the PCI r3.0 spec 596 * device, change the class code to 0x0c03fe, which the PCI r3.0 spec
@@ -604,11 +610,10 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB,
604 quirk_amd_nl_class); 610 quirk_amd_nl_class);
605 611
606/* 612/*
607 * Let's make the southbridge information explicit instead 613 * Let's make the southbridge information explicit instead of having to
608 * of having to worry about people probing the ACPI areas, 614 * worry about people probing the ACPI areas, for example.. (Yes, it
609 * for example.. (Yes, it happens, and if you read the wrong 615 * happens, and if you read the wrong ACPI register it will put the machine
610 * ACPI register it will put the machine to sleep with no 616 * to sleep with no way of waking it up again. Bummer).
611 * way of waking it up again. Bummer).
612 * 617 *
613 * ALI M7101: Two IO regions pointed to by words at 618 * ALI M7101: Two IO regions pointed to by words at
614 * 0xE0 (64 bytes of ACPI registers) 619 * 0xE0 (64 bytes of ACPI registers)
@@ -664,6 +669,7 @@ static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int
664 break; 669 break;
665 size = bit; 670 size = bit;
666 } 671 }
672
667 /* 673 /*
668 * For now we only print it out. Eventually we'll want to 674 * For now we only print it out. Eventually we'll want to
669 * reserve it, but let's get enough confirmation reports first. 675 * reserve it, but let's get enough confirmation reports first.
@@ -735,8 +741,7 @@ static void quirk_ich4_lpc_acpi(struct pci_dev *dev)
735 * priority and can't tell whether the legacy device or the one created 741 * priority and can't tell whether the legacy device or the one created
736 * here is really at that address. This happens on boards with broken 742 * here is really at that address. This happens on boards with broken
737 * BIOSes. 743 * BIOSes.
738 */ 744 */
739
740 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable); 745 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
741 if (enable & ICH4_ACPI_EN) 746 if (enable & ICH4_ACPI_EN)
742 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES, 747 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
@@ -773,7 +778,8 @@ static void ich6_lpc_acpi_gpio(struct pci_dev *dev)
773 "ICH6 GPIO"); 778 "ICH6 GPIO");
774} 779}
775 780
776static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name, int dynsize) 781static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg,
782 const char *name, int dynsize)
777{ 783{
778 u32 val; 784 u32 val;
779 u32 size, base; 785 u32 size, base;
@@ -797,7 +803,10 @@ static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const cha
797 } 803 }
798 base &= ~(size-1); 804 base &= ~(size-1);
799 805
800 /* Just print it out for now. We should reserve it after more debugging */ 806 /*
807 * Just print it out for now. We should reserve it after more
808 * debugging.
809 */
801 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base+size-1); 810 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base+size-1);
802} 811}
803 812
@@ -813,7 +822,8 @@ static void quirk_ich6_lpc(struct pci_dev *dev)
813DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc); 822DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc);
814DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc); 823DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc);
815 824
816static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name) 825static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg,
826 const char *name)
817{ 827{
818 u32 val; 828 u32 val;
819 u32 mask, base; 829 u32 mask, base;
@@ -824,15 +834,15 @@ static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const cha
824 if (!(val & 1)) 834 if (!(val & 1))
825 return; 835 return;
826 836
827 /* 837 /* IO base in bits 15:2, mask in bits 23:18, both are dword-based */
828 * IO base in bits 15:2, mask in bits 23:18, both
829 * are dword-based
830 */
831 base = val & 0xfffc; 838 base = val & 0xfffc;
832 mask = (val >> 16) & 0xfc; 839 mask = (val >> 16) & 0xfc;
833 mask |= 3; 840 mask |= 3;
834 841
835 /* Just print it out for now. We should reserve it after more debugging */ 842 /*
843 * Just print it out for now. We should reserve it after more
844 * debugging.
845 */
836 pci_info(dev, "%s PIO at %04x (mask %04x)\n", name, base, mask); 846 pci_info(dev, "%s PIO at %04x (mask %04x)\n", name, base, mask);
837} 847}
838 848
@@ -904,8 +914,8 @@ static void quirk_vt8235_acpi(struct pci_dev *dev)
904DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi); 914DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
905 915
906/* 916/*
907 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast back-to-back: 917 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast
908 * Disable fast back-to-back on the secondary bus segment 918 * back-to-back: Disable fast back-to-back on the secondary bus segment
909 */ 919 */
910static void quirk_xio2000a(struct pci_dev *dev) 920static void quirk_xio2000a(struct pci_dev *dev)
911{ 921{
@@ -930,8 +940,8 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A,
930 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip 940 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
931 * devices to the external APIC. 941 * devices to the external APIC.
932 * 942 *
933 * TODO: When we have device-specific interrupt routers, 943 * TODO: When we have device-specific interrupt routers, this code will go
934 * this code will go away from quirks. 944 * away from quirks.
935 */ 945 */
936static void quirk_via_ioapic(struct pci_dev *dev) 946static void quirk_via_ioapic(struct pci_dev *dev)
937{ 947{
@@ -972,13 +982,13 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt
972DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); 982DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
973 983
974/* 984/*
975 * The AMD io apic can hang the box when an apic irq is masked. 985 * The AMD IO-APIC can hang the box when an APIC IRQ is masked.
976 * We check all revs >= B0 (yet not in the pre production!) as the bug 986 * We check all revs >= B0 (yet not in the pre production!) as the bug
977 * is currently marked NoFix 987 * is currently marked NoFix
978 * 988 *
979 * We have multiple reports of hangs with this chipset that went away with 989 * We have multiple reports of hangs with this chipset that went away with
980 * noapic specified. For the moment we assume it's the erratum. We may be wrong 990 * noapic specified. For the moment we assume it's the erratum. We may be wrong
981 * of course. However the advice is demonstrably good even if so.. 991 * of course. However the advice is demonstrably good even if so.
982 */ 992 */
983static void quirk_amd_ioapic(struct pci_dev *dev) 993static void quirk_amd_ioapic(struct pci_dev *dev)
984{ 994{
@@ -994,7 +1004,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_a
994 1004
995static void quirk_cavium_sriov_rnm_link(struct pci_dev *dev) 1005static void quirk_cavium_sriov_rnm_link(struct pci_dev *dev)
996{ 1006{
997 /* Fix for improper SRIOV configuration on Cavium cn88xx RNM device */ 1007 /* Fix for improper SR-IOV configuration on Cavium cn88xx RNM device */
998 if (dev->subsystem_device == 0xa118) 1008 if (dev->subsystem_device == 0xa118)
999 dev->sriov->link = dev->devfn; 1009 dev->sriov->link = dev->devfn;
1000} 1010}
@@ -1016,19 +1026,17 @@ static void quirk_amd_8131_mmrbc(struct pci_dev *dev)
1016DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc); 1026DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);
1017 1027
1018/* 1028/*
1019 * FIXME: it is questionable that quirk_via_acpi 1029 * FIXME: it is questionable that quirk_via_acpi() is needed. It shows up
1020 * is needed. It shows up as an ISA bridge, and does not 1030 * as an ISA bridge, and does not support the PCI_INTERRUPT_LINE register
1021 * support the PCI_INTERRUPT_LINE register at all. Therefore 1031 * at all. Therefore it seems like setting the pci_dev's IRQ to the value
1022 * it seems like setting the pci_dev's 'irq' to the 1032 * of the ACPI SCI interrupt is only done for convenience.
1023 * value of the ACPI SCI interrupt is only done for convenience.
1024 * -jgarzik 1033 * -jgarzik
1025 */ 1034 */
1026static void quirk_via_acpi(struct pci_dev *d) 1035static void quirk_via_acpi(struct pci_dev *d)
1027{ 1036{
1028 /*
1029 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
1030 */
1031 u8 irq; 1037 u8 irq;
1038
1039 /* VIA ACPI device: SCI IRQ line in PCI config byte 0x42 */
1032 pci_read_config_byte(d, 0x42, &irq); 1040 pci_read_config_byte(d, 0x42, &irq);
1033 irq &= 0xf; 1041 irq &= 0xf;
1034 if (irq && (irq != 2)) 1042 if (irq && (irq != 2))
@@ -1037,11 +1045,7 @@ static void quirk_via_acpi(struct pci_dev *d)
1037DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi); 1045DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi);
1038DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi); 1046DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi);
1039 1047
1040 1048/* VIA bridges which have VLink */
1041/*
1042 * VIA bridges which have VLink
1043 */
1044
1045static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18; 1049static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
1046 1050
1047static void quirk_via_bridge(struct pci_dev *dev) 1051static void quirk_via_bridge(struct pci_dev *dev)
@@ -1049,9 +1053,11 @@ static void quirk_via_bridge(struct pci_dev *dev)
1049 /* See what bridge we have and find the device ranges */ 1053 /* See what bridge we have and find the device ranges */
1050 switch (dev->device) { 1054 switch (dev->device) {
1051 case PCI_DEVICE_ID_VIA_82C686: 1055 case PCI_DEVICE_ID_VIA_82C686:
1052 /* The VT82C686 is special, it attaches to PCI and can have 1056 /*
1053 any device number. All its subdevices are functions of 1057 * The VT82C686 is special; it attaches to PCI and can have
1054 that single device. */ 1058 * any device number. All its subdevices are functions of
1059 * that single device.
1060 */
1055 via_vlink_dev_lo = PCI_SLOT(dev->devfn); 1061 via_vlink_dev_lo = PCI_SLOT(dev->devfn);
1056 via_vlink_dev_hi = PCI_SLOT(dev->devfn); 1062 via_vlink_dev_hi = PCI_SLOT(dev->devfn);
1057 break; 1063 break;
@@ -1079,19 +1085,17 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_b
1079DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge); 1085DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge);
1080DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge); 1086DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge);
1081 1087
1082/** 1088/*
1083 * quirk_via_vlink - VIA VLink IRQ number update 1089 * quirk_via_vlink - VIA VLink IRQ number update
1084 * @dev: PCI device 1090 * @dev: PCI device
1085 * 1091 *
1086 * If the device we are dealing with is on a PIC IRQ we need to 1092 * If the device we are dealing with is on a PIC IRQ we need to ensure that
1087 * ensure that the IRQ line register which usually is not relevant 1093 * the IRQ line register which usually is not relevant for PCI cards, is
1088 * for PCI cards, is actually written so that interrupts get sent 1094 * actually written so that interrupts get sent to the right place.
1089 * to the right place. 1095 *
1090 * We only do this on systems where a VIA south bridge was detected, 1096 * We only do this on systems where a VIA south bridge was detected, and
1091 * and only for VIA devices on the motherboard (see quirk_via_bridge 1097 * only for VIA devices on the motherboard (see quirk_via_bridge above).
1092 * above).
1093 */ 1098 */
1094
1095static void quirk_via_vlink(struct pci_dev *dev) 1099static void quirk_via_vlink(struct pci_dev *dev)
1096{ 1100{
1097 u8 irq, new_irq; 1101 u8 irq, new_irq;
@@ -1111,9 +1115,10 @@ static void quirk_via_vlink(struct pci_dev *dev)
1111 PCI_SLOT(dev->devfn) < via_vlink_dev_lo) 1115 PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
1112 return; 1116 return;
1113 1117
1114 /* This is an internal VLink device on a PIC interrupt. The BIOS 1118 /*
1115 ought to have set this but may not have, so we redo it */ 1119 * This is an internal VLink device on a PIC interrupt. The BIOS
1116 1120 * ought to have set this but may not have, so we redo it.
1121 */
1117 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); 1122 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
1118 if (new_irq != irq) { 1123 if (new_irq != irq) {
1119 pci_info(dev, "VIA VLink IRQ fixup, from %d to %d\n", 1124 pci_info(dev, "VIA VLink IRQ fixup, from %d to %d\n",
@@ -1125,10 +1130,9 @@ static void quirk_via_vlink(struct pci_dev *dev)
1125DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink); 1130DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);
1126 1131
1127/* 1132/*
1128 * VIA VT82C598 has its device ID settable and many BIOSes 1133 * VIA VT82C598 has its device ID settable and many BIOSes set it to the ID
1129 * set it to the ID of VT82C597 for backward compatibility. 1134 * of VT82C597 for backward compatibility. We need to switch it off to be
1130 * We need to switch it off to be able to recognize the real 1135 * able to recognize the real type of the chip.
1131 * type of the chip.
1132 */ 1136 */
1133static void quirk_vt82c598_id(struct pci_dev *dev) 1137static void quirk_vt82c598_id(struct pci_dev *dev)
1134{ 1138{
@@ -1138,10 +1142,10 @@ static void quirk_vt82c598_id(struct pci_dev *dev)
1138DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id); 1142DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id);
1139 1143
1140/* 1144/*
1141 * CardBus controllers have a legacy base address that enables them 1145 * CardBus controllers have a legacy base address that enables them to
1142 * to respond as i82365 pcmcia controllers. We don't want them to 1146 * respond as i82365 pcmcia controllers. We don't want them to do this
1143 * do this even if the Linux CardBus driver is not loaded, because 1147 * even if the Linux CardBus driver is not loaded, because the Linux i82365
1144 * the Linux i82365 driver does not (and should not) handle CardBus. 1148 * driver does not (and should not) handle CardBus.
1145 */ 1149 */
1146static void quirk_cardbus_legacy(struct pci_dev *dev) 1150static void quirk_cardbus_legacy(struct pci_dev *dev)
1147{ 1151{
@@ -1153,11 +1157,11 @@ DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID,
1153 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy); 1157 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
1154 1158
1155/* 1159/*
1156 * Following the PCI ordering rules is optional on the AMD762. I'm not 1160 * Following the PCI ordering rules is optional on the AMD762. I'm not sure
1157 * sure what the designers were smoking but let's not inhale... 1161 * what the designers were smoking but let's not inhale...
1158 * 1162 *
1159 * To be fair to AMD, it follows the spec by default, its BIOS people 1163 * To be fair to AMD, it follows the spec by default, it's BIOS people who
1160 * who turn it off! 1164 * turn it off!
1161 */ 1165 */
1162static void quirk_amd_ordering(struct pci_dev *dev) 1166static void quirk_amd_ordering(struct pci_dev *dev)
1163{ 1167{
@@ -1176,11 +1180,11 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk
1176DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); 1180DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
1177 1181
1178/* 1182/*
1179 * DreamWorks provided workaround for Dunord I-3000 problem 1183 * DreamWorks-provided workaround for Dunord I-3000 problem
1180 * 1184 *
1181 * This card decodes and responds to addresses not apparently 1185 * This card decodes and responds to addresses not apparently assigned to
1182 * assigned to it. We force a larger allocation to ensure that 1186 * it. We force a larger allocation to ensure that nothing gets put too
1183 * nothing gets put too close to it. 1187 * close to it.
1184 */ 1188 */
1185static void quirk_dunord(struct pci_dev *dev) 1189static void quirk_dunord(struct pci_dev *dev)
1186{ 1190{
@@ -1193,10 +1197,9 @@ static void quirk_dunord(struct pci_dev *dev)
1193DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord); 1197DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord);
1194 1198
1195/* 1199/*
1196 * i82380FB mobile docking controller: its PCI-to-PCI bridge 1200 * i82380FB mobile docking controller: its PCI-to-PCI bridge is subtractive
1197 * is subtractive decoding (transparent), and does indicate this 1201 * decoding (transparent), and does indicate this in the ProgIf.
1198 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80 1202 * Unfortunately, the ProgIf value is wrong - 0x80 instead of 0x01.
1199 * instead of 0x01.
1200 */ 1203 */
1201static void quirk_transparent_bridge(struct pci_dev *dev) 1204static void quirk_transparent_bridge(struct pci_dev *dev)
1202{ 1205{
@@ -1206,10 +1209,10 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk
1206DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge); 1209DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge);
1207 1210
1208/* 1211/*
1209 * Common misconfiguration of the MediaGX/Geode PCI master that will 1212 * Common misconfiguration of the MediaGX/Geode PCI master that will reduce
1210 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1 1213 * PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1 datasheets
1211 * datasheets found at http://www.national.com/analog for info on what 1214 * found at http://www.national.com/analog for info on what these bits do.
1212 * these bits do. <christer@weinigel.se> 1215 * <christer@weinigel.se>
1213 */ 1216 */
1214static void quirk_mediagx_master(struct pci_dev *dev) 1217static void quirk_mediagx_master(struct pci_dev *dev)
1215{ 1218{
@@ -1227,9 +1230,9 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, qui
1227DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master); 1230DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1228 1231
1229/* 1232/*
1230 * Ensure C0 rev restreaming is off. This is normally done by 1233 * Ensure C0 rev restreaming is off. This is normally done by the BIOS but
1231 * the BIOS but in the odd case it is not the results are corruption 1234 * in the odd case it is not the results are corruption hence the presence
1232 * hence the presence of a Linux check 1235 * of a Linux check.
1233 */ 1236 */
1234static void quirk_disable_pxb(struct pci_dev *pdev) 1237static void quirk_disable_pxb(struct pci_dev *pdev)
1235{ 1238{
@@ -1273,9 +1276,7 @@ DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA
1273DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode); 1276DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1274DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode); 1277DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1275 1278
1276/* 1279/* Serverworks CSB5 IDE does not fully support native mode */
1277 * Serverworks CSB5 IDE does not fully support native mode
1278 */
1279static void quirk_svwks_csb5ide(struct pci_dev *pdev) 1280static void quirk_svwks_csb5ide(struct pci_dev *pdev)
1280{ 1281{
1281 u8 prog; 1282 u8 prog;
@@ -1289,9 +1290,7 @@ static void quirk_svwks_csb5ide(struct pci_dev *pdev)
1289} 1290}
1290DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide); 1291DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);
1291 1292
1292/* 1293/* Intel 82801CAM ICH3-M datasheet says IDE modes must be the same */
1293 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
1294 */
1295static void quirk_ide_samemode(struct pci_dev *pdev) 1294static void quirk_ide_samemode(struct pci_dev *pdev)
1296{ 1295{
1297 u8 prog; 1296 u8 prog;
@@ -1307,10 +1306,7 @@ static void quirk_ide_samemode(struct pci_dev *pdev)
1307} 1306}
1308DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode); 1307DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
1309 1308
1310/* 1309/* Some ATA devices break if put into D3 */
1311 * Some ATA devices break if put into D3
1312 */
1313
1314static void quirk_no_ata_d3(struct pci_dev *pdev) 1310static void quirk_no_ata_d3(struct pci_dev *pdev)
1315{ 1311{
1316 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3; 1312 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;
@@ -1328,7 +1324,8 @@ DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID,
1328DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID, 1324DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID,
1329 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1325 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1330 1326
1331/* This was originally an Alpha specific thing, but it really fits here. 1327/*
1328 * This was originally an Alpha-specific thing, but it really fits here.
1332 * The i82375 PCI/EISA bridge appears as non-classified. Fix that. 1329 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1333 */ 1330 */
1334static void quirk_eisa_bridge(struct pci_dev *dev) 1331static void quirk_eisa_bridge(struct pci_dev *dev)
@@ -1337,7 +1334,6 @@ static void quirk_eisa_bridge(struct pci_dev *dev)
1337} 1334}
1338DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge); 1335DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge);
1339 1336
1340
1341/* 1337/*
1342 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge 1338 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
1343 * is not activated. The myth is that Asus said that they do not want the 1339 * is not activated. The myth is that Asus said that they do not want the
@@ -1554,15 +1550,19 @@ static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev)
1554 1550
1555 if (likely(!asus_hides_smbus || !asus_rcba_base)) 1551 if (likely(!asus_hides_smbus || !asus_rcba_base))
1556 return; 1552 return;
1553
1557 /* read the Function Disable register, dword mode only */ 1554 /* read the Function Disable register, dword mode only */
1558 val = readl(asus_rcba_base + 0x3418); 1555 val = readl(asus_rcba_base + 0x3418);
1559 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); /* enable the SMBus device */ 1556
1557 /* enable the SMBus device */
1558 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418);
1560} 1559}
1561 1560
1562static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev) 1561static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
1563{ 1562{
1564 if (likely(!asus_hides_smbus || !asus_rcba_base)) 1563 if (likely(!asus_hides_smbus || !asus_rcba_base))
1565 return; 1564 return;
1565
1566 iounmap(asus_rcba_base); 1566 iounmap(asus_rcba_base);
1567 asus_rcba_base = NULL; 1567 asus_rcba_base = NULL;
1568 pci_info(dev, "Enabled ICH6/i801 SMBus device\n"); 1568 pci_info(dev, "Enabled ICH6/i801 SMBus device\n");
@@ -1579,9 +1579,7 @@ DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_
1579DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume); 1579DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume);
1580DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early); 1580DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early);
1581 1581
1582/* 1582/* SiS 96x south bridge: BIOS typically hides SMBus device... */
1583 * SiS 96x south bridge: BIOS typically hides SMBus device...
1584 */
1585static void quirk_sis_96x_smbus(struct pci_dev *dev) 1583static void quirk_sis_96x_smbus(struct pci_dev *dev)
1586{ 1584{
1587 u8 val = 0; 1585 u8 val = 0;
@@ -1604,7 +1602,7 @@ DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_si
1604 * ... This is further complicated by the fact that some SiS96x south 1602 * ... This is further complicated by the fact that some SiS96x south
1605 * bridges pretend to be 85C503/5513 instead. In that case see if we 1603 * bridges pretend to be 85C503/5513 instead. In that case see if we
1606 * spotted a compatible north bridge to make sure. 1604 * spotted a compatible north bridge to make sure.
1607 * (pci_find_device doesn't work yet) 1605 * (pci_find_device() doesn't work yet)
1608 * 1606 *
1609 * We can also enable the sis96x bit in the discovery register.. 1607 * We can also enable the sis96x bit in the discovery register..
1610 */ 1608 */
@@ -1624,9 +1622,9 @@ static void quirk_sis_503(struct pci_dev *dev)
1624 } 1622 }
1625 1623
1626 /* 1624 /*
1627 * Ok, it now shows up as a 96x.. run the 96x quirk by 1625 * Ok, it now shows up as a 96x. Run the 96x quirk by hand in case
1628 * hand in case it has already been processed. 1626 * it has already been processed. (Depends on link order, which is
1629 * (depends on link order, which is apparently not guaranteed) 1627 * apparently not guaranteed)
1630 */ 1628 */
1631 dev->device = devid; 1629 dev->device = devid;
1632 quirk_sis_96x_smbus(dev); 1630 quirk_sis_96x_smbus(dev);
@@ -1634,7 +1632,6 @@ static void quirk_sis_503(struct pci_dev *dev)
1634DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); 1632DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1635DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); 1633DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1636 1634
1637
1638/* 1635/*
1639 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller 1636 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1640 * and MC97 modem controller are disabled when a second PCI soundcard is 1637 * and MC97 modem controller are disabled when a second PCI soundcard is
@@ -1671,9 +1668,8 @@ DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_h
1671#if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE) 1668#if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
1672 1669
1673/* 1670/*
1674 * If we are using libata we can drive this chip properly but must 1671 * If we are using libata we can drive this chip properly but must do this
1675 * do this early on to make the additional device appear during 1672 * early on to make the additional device appear during the PCI scanning.
1676 * the PCI scanning.
1677 */ 1673 */
1678static void quirk_jmicron_ata(struct pci_dev *pdev) 1674static void quirk_jmicron_ata(struct pci_dev *pdev)
1679{ 1675{
@@ -1769,14 +1765,18 @@ static void quirk_alder_ioapic(struct pci_dev *pdev)
1769 if ((pdev->class >> 8) != 0xff00) 1765 if ((pdev->class >> 8) != 0xff00)
1770 return; 1766 return;
1771 1767
1772 /* the first BAR is the location of the IO APIC...we must 1768 /*
1769 * The first BAR is the location of the IO-APIC... we must
1773 * not touch this (and it's already covered by the fixmap), so 1770 * not touch this (and it's already covered by the fixmap), so
1774 * forcibly insert it into the resource tree */ 1771 * forcibly insert it into the resource tree.
1772 */
1775 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0)) 1773 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1776 insert_resource(&iomem_resource, &pdev->resource[0]); 1774 insert_resource(&iomem_resource, &pdev->resource[0]);
1777 1775
1778 /* The next five BARs all seem to be rubbish, so just clean 1776 /*
1779 * them out */ 1777 * The next five BARs all seem to be rubbish, so just clean
1778 * them out.
1779 */
1780 for (i = 1; i < 6; i++) 1780 for (i = 1; i < 6; i++)
1781 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i])); 1781 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1782} 1782}
@@ -1794,8 +1794,8 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quir
1794DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1610, PCI_CLASS_BRIDGE_PCI, 8, quirk_pcie_mch); 1794DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1610, PCI_CLASS_BRIDGE_PCI, 8, quirk_pcie_mch);
1795 1795
1796/* 1796/*
1797 * It's possible for the MSI to get corrupted if shpc and acpi 1797 * It's possible for the MSI to get corrupted if SHPC and ACPI are used
1798 * are used together on certain PXH-based systems. 1798 * together on certain PXH-based systems.
1799 */ 1799 */
1800static void quirk_pcie_pxh(struct pci_dev *dev) 1800static void quirk_pcie_pxh(struct pci_dev *dev)
1801{ 1801{
@@ -1809,15 +1809,14 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pc
1809DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh); 1809DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1810 1810
1811/* 1811/*
1812 * Some Intel PCI Express chipsets have trouble with downstream 1812 * Some Intel PCI Express chipsets have trouble with downstream device
1813 * device power management. 1813 * power management.
1814 */ 1814 */
1815static void quirk_intel_pcie_pm(struct pci_dev *dev) 1815static void quirk_intel_pcie_pm(struct pci_dev *dev)
1816{ 1816{
1817 pci_pm_d3_delay = 120; 1817 pci_pm_d3_delay = 120;
1818 dev->no_d1d2 = 1; 1818 dev->no_d1d2 = 1;
1819} 1819}
1820
1821DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm); 1820DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
1822DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm); 1821DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
1823DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm); 1822DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
@@ -1879,7 +1878,7 @@ static const struct dmi_system_id boot_interrupt_dmi_table[] = {
1879 1878
1880/* 1879/*
1881 * Boot interrupts on some chipsets cannot be turned off. For these chipsets, 1880 * Boot interrupts on some chipsets cannot be turned off. For these chipsets,
1882 * remap the original interrupt in the linux kernel to the boot interrupt, so 1881 * remap the original interrupt in the Linux kernel to the boot interrupt, so
1883 * that a PCI device's interrupt handler is installed on the boot interrupt 1882 * that a PCI device's interrupt handler is installed on the boot interrupt
1884 * line instead. 1883 * line instead.
1885 */ 1884 */
@@ -1916,7 +1915,7 @@ DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk
1916 */ 1915 */
1917 1916
1918/* 1917/*
1919 * IO-APIC1 on 6300ESB generates boot interrupts, see intel order no 1918 * IO-APIC1 on 6300ESB generates boot interrupts, see Intel order no
1920 * 300641-004US, section 5.7.3. 1919 * 300641-004US, section 5.7.3.
1921 */ 1920 */
1922#define INTEL_6300_IOAPIC_ABAR 0x40 1921#define INTEL_6300_IOAPIC_ABAR 0x40
@@ -1939,9 +1938,7 @@ static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
1939DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt); 1938DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1940DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt); 1939DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1941 1940
1942/* 1941/* Disable boot interrupts on HT-1000 */
1943 * disable boot interrupts on HT-1000
1944 */
1945#define BC_HT1000_FEATURE_REG 0x64 1942#define BC_HT1000_FEATURE_REG 0x64
1946#define BC_HT1000_PIC_REGS_ENABLE (1<<0) 1943#define BC_HT1000_PIC_REGS_ENABLE (1<<0)
1947#define BC_HT1000_MAP_IDX 0xC00 1944#define BC_HT1000_MAP_IDX 0xC00
@@ -1972,9 +1969,8 @@ static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev)
1972DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); 1969DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1973DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); 1970DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1974 1971
1975/* 1972/* Disable boot interrupts on AMD and ATI chipsets */
1976 * disable boot interrupts on AMD and ATI chipsets 1973
1977 */
1978/* 1974/*
1979 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131 1975 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131
1980 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode 1976 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
@@ -2050,7 +2046,7 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
2050 quirk_tc86c001_ide); 2046 quirk_tc86c001_ide);
2051 2047
2052/* 2048/*
2053 * PLX PCI 9050 PCI Target bridge controller has an errata that prevents the 2049 * PLX PCI 9050 PCI Target bridge controller has an erratum that prevents the
2054 * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o) 2050 * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o)
2055 * being read correctly if bit 7 of the base address is set. 2051 * being read correctly if bit 7 of the base address is set.
2056 * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128). 2052 * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128).
@@ -2243,15 +2239,17 @@ static void quirk_p64h2_1k_io(struct pci_dev *dev)
2243 dev->io_window_1k = 1; 2239 dev->io_window_1k = 1;
2244 } 2240 }
2245} 2241}
2246DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io); 2242DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
2247 2243
2248/* Under some circumstances, AER is not linked with extended capabilities. 2244/*
2245 * Under some circumstances, AER is not linked with extended capabilities.
2249 * Force it to be linked by setting the corresponding control bit in the 2246 * Force it to be linked by setting the corresponding control bit in the
2250 * config space. 2247 * config space.
2251 */ 2248 */
2252static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev) 2249static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
2253{ 2250{
2254 uint8_t b; 2251 uint8_t b;
2252
2255 if (pci_read_config_byte(dev, 0xf41, &b) == 0) { 2253 if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
2256 if (!(b & 0x20)) { 2254 if (!(b & 0x20)) {
2257 pci_write_config_byte(dev, 0xf41, b | 0x20); 2255 pci_write_config_byte(dev, 0xf41, b | 0x20);
@@ -2281,8 +2279,10 @@ static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
2281 PCI_DEVICE_ID_VIA_8235_USB_2, NULL); 2279 PCI_DEVICE_ID_VIA_8235_USB_2, NULL);
2282 uint8_t b; 2280 uint8_t b;
2283 2281
2284 /* p should contain the first (internal) VT6212L -- see if we have 2282 /*
2285 an external one by searching again */ 2283 * p should contain the first (internal) VT6212L -- see if we have
2284 * an external one by searching again.
2285 */
2286 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p); 2286 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p);
2287 if (!p) 2287 if (!p)
2288 return; 2288 return;
@@ -2327,7 +2327,6 @@ static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev)
2327 pcie_set_readrq(dev, 2048); 2327 pcie_set_readrq(dev, 2048);
2328 } 2328 }
2329} 2329}
2330
2331DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM, 2330DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM,
2332 PCI_DEVICE_ID_TIGON3_5719, 2331 PCI_DEVICE_ID_TIGON3_5719,
2333 quirk_brcm_5719_limit_mrrs); 2332 quirk_brcm_5719_limit_mrrs);
@@ -2335,14 +2334,16 @@ DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM,
2335#ifdef CONFIG_PCIE_IPROC_PLATFORM 2334#ifdef CONFIG_PCIE_IPROC_PLATFORM
2336static void quirk_paxc_bridge(struct pci_dev *pdev) 2335static void quirk_paxc_bridge(struct pci_dev *pdev)
2337{ 2336{
2338 /* The PCI config space is shared with the PAXC root port and the first 2337 /*
2338 * The PCI config space is shared with the PAXC root port and the first
2339 * Ethernet device. So, we need to workaround this by telling the PCI 2339 * Ethernet device. So, we need to workaround this by telling the PCI
2340 * code that the bridge is not an Ethernet device. 2340 * code that the bridge is not an Ethernet device.
2341 */ 2341 */
2342 if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE) 2342 if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE)
2343 pdev->class = PCI_CLASS_BRIDGE_PCI << 8; 2343 pdev->class = PCI_CLASS_BRIDGE_PCI << 8;
2344 2344
2345 /* MPSS is not being set properly (as it is currently 0). This is 2345 /*
2346 * MPSS is not being set properly (as it is currently 0). This is
2346 * because that area of the PCI config space is hard coded to zero, and 2347 * because that area of the PCI config space is hard coded to zero, and
2347 * is not modifiable by firmware. Set this to 2 (e.g., 512 byte MPS) 2348 * is not modifiable by firmware. Set this to 2 (e.g., 512 byte MPS)
2348 * so that the MPS can be set to the real max value. 2349 * so that the MPS can be set to the real max value.
@@ -2353,10 +2354,10 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16cd, quirk_paxc_bridge);
2353DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16f0, quirk_paxc_bridge); 2354DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16f0, quirk_paxc_bridge);
2354#endif 2355#endif
2355 2356
2356/* Originally in EDAC sources for i82875P: 2357/*
2357 * Intel tells BIOS developers to hide device 6 which 2358 * Originally in EDAC sources for i82875P: Intel tells BIOS developers to
2358 * configures the overflow device access containing 2359 * hide device 6 which configures the overflow device access containing the
2359 * the DRBs - this is where we expose device 6. 2360 * DRBs - this is where we expose device 6.
2360 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm 2361 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
2361 */ 2362 */
2362static void quirk_unhide_mch_dev6(struct pci_dev *dev) 2363static void quirk_unhide_mch_dev6(struct pci_dev *dev)
@@ -2368,18 +2369,18 @@ static void quirk_unhide_mch_dev6(struct pci_dev *dev)
2368 pci_write_config_byte(dev, 0xF4, reg | 0x02); 2369 pci_write_config_byte(dev, 0xF4, reg | 0x02);
2369 } 2370 }
2370} 2371}
2371
2372DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, 2372DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB,
2373 quirk_unhide_mch_dev6); 2373 quirk_unhide_mch_dev6);
2374DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, 2374DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB,
2375 quirk_unhide_mch_dev6); 2375 quirk_unhide_mch_dev6);
2376 2376
2377#ifdef CONFIG_PCI_MSI 2377#ifdef CONFIG_PCI_MSI
2378/* Some chipsets do not support MSI. We cannot easily rely on setting 2378/*
2379 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually 2379 * Some chipsets do not support MSI. We cannot easily rely on setting
2380 * some other buses controlled by the chipset even if Linux is not 2380 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually some
2381 * aware of it. Instead of setting the flag on all buses in the 2381 * other buses controlled by the chipset even if Linux is not aware of it.
2382 * machine, simply disable MSI globally. 2382 * Instead of setting the flag on all buses in the machine, simply disable
2383 * MSI globally.
2383 */ 2384 */
2384static void quirk_disable_all_msi(struct pci_dev *dev) 2385static void quirk_disable_all_msi(struct pci_dev *dev)
2385{ 2386{
@@ -2427,8 +2428,10 @@ static void quirk_amd_780_apc_msi(struct pci_dev *host_bridge)
2427DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi); 2428DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi);
2428DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi); 2429DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi);
2429 2430
2430/* Go through the list of Hypertransport capabilities and 2431/*
2431 * return 1 if a HT MSI capability is found and enabled */ 2432 * Go through the list of HyperTransport capabilities and return 1 if a HT
2433 * MSI capability is found and enabled.
2434 */
2432static int msi_ht_cap_enabled(struct pci_dev *dev) 2435static int msi_ht_cap_enabled(struct pci_dev *dev)
2433{ 2436{
2434 int pos, ttl = PCI_FIND_CAP_TTL; 2437 int pos, ttl = PCI_FIND_CAP_TTL;
@@ -2451,7 +2454,7 @@ static int msi_ht_cap_enabled(struct pci_dev *dev)
2451 return 0; 2454 return 0;
2452} 2455}
2453 2456
2454/* Check the hypertransport MSI mapping to know whether MSI is enabled or not */ 2457/* Check the HyperTransport MSI mapping to know whether MSI is enabled or not */
2455static void quirk_msi_ht_cap(struct pci_dev *dev) 2458static void quirk_msi_ht_cap(struct pci_dev *dev)
2456{ 2459{
2457 if (dev->subordinate && !msi_ht_cap_enabled(dev)) { 2460 if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
@@ -2462,8 +2465,9 @@ static void quirk_msi_ht_cap(struct pci_dev *dev)
2462DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE, 2465DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
2463 quirk_msi_ht_cap); 2466 quirk_msi_ht_cap);
2464 2467
2465/* The nVidia CK804 chipset may have 2 HT MSI mappings. 2468/*
2466 * MSI are supported if the MSI capability set in any of these mappings. 2469 * The nVidia CK804 chipset may have 2 HT MSI mappings. MSI is supported
2470 * if the MSI capability is set in any of these mappings.
2467 */ 2471 */
2468static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev) 2472static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
2469{ 2473{
@@ -2472,8 +2476,9 @@ static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
2472 if (!dev->subordinate) 2476 if (!dev->subordinate)
2473 return; 2477 return;
2474 2478
2475 /* check HT MSI cap on this chipset and the root one. 2479 /*
2476 * a single one having MSI is enough to be sure that MSI are supported. 2480 * Check HT MSI cap on this chipset and the root one. A single one
2481 * having MSI is enough to be sure that MSI is supported.
2477 */ 2482 */
2478 pdev = pci_get_slot(dev->bus, 0); 2483 pdev = pci_get_slot(dev->bus, 0);
2479 if (!pdev) 2484 if (!pdev)
@@ -2510,13 +2515,13 @@ static void ht_enable_msi_mapping(struct pci_dev *dev)
2510DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, 2515DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
2511 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB, 2516 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
2512 ht_enable_msi_mapping); 2517 ht_enable_msi_mapping);
2513
2514DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, 2518DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE,
2515 ht_enable_msi_mapping); 2519 ht_enable_msi_mapping);
2516 2520
2517/* The P5N32-SLI motherboards from Asus have a problem with msi 2521/*
2518 * for the MCP55 NIC. It is not yet determined whether the msi problem 2522 * The P5N32-SLI motherboards from Asus have a problem with MSI
2519 * also affects other devices. As for now, turn off msi for this device. 2523 * for the MCP55 NIC. It is not yet determined whether the MSI problem
2524 * also affects other devices. As for now, turn off MSI for this device.
2520 */ 2525 */
2521static void nvenet_msi_disable(struct pci_dev *dev) 2526static void nvenet_msi_disable(struct pci_dev *dev)
2522{ 2527{
@@ -2553,16 +2558,14 @@ static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev)
2553 pci_read_config_dword(dev, 0x74, &cfg); 2558 pci_read_config_dword(dev, 0x74, &cfg);
2554 2559
2555 if (cfg & ((1 << 2) | (1 << 15))) { 2560 if (cfg & ((1 << 2) | (1 << 15))) {
2556 printk(KERN_INFO "Rewriting irq routing register on MCP55\n"); 2561 printk(KERN_INFO "Rewriting IRQ routing register on MCP55\n");
2557 cfg &= ~((1 << 2) | (1 << 15)); 2562 cfg &= ~((1 << 2) | (1 << 15));
2558 pci_write_config_dword(dev, 0x74, cfg); 2563 pci_write_config_dword(dev, 0x74, cfg);
2559 } 2564 }
2560} 2565}
2561
2562DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2566DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2563 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0, 2567 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0,
2564 nvbridge_check_legacy_irq_routing); 2568 nvbridge_check_legacy_irq_routing);
2565
2566DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2569DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2567 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4, 2570 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4,
2568 nvbridge_check_legacy_irq_routing); 2571 nvbridge_check_legacy_irq_routing);
@@ -2572,7 +2575,7 @@ static int ht_check_msi_mapping(struct pci_dev *dev)
2572 int pos, ttl = PCI_FIND_CAP_TTL; 2575 int pos, ttl = PCI_FIND_CAP_TTL;
2573 int found = 0; 2576 int found = 0;
2574 2577
2575 /* check if there is HT MSI cap or enabled on this device */ 2578 /* Check if there is HT MSI cap or enabled on this device */
2576 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2579 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2577 while (pos && ttl--) { 2580 while (pos && ttl--) {
2578 u8 flags; 2581 u8 flags;
@@ -2608,7 +2611,7 @@ static int host_bridge_with_leaf(struct pci_dev *host_bridge)
2608 if (!dev) 2611 if (!dev)
2609 continue; 2612 continue;
2610 2613
2611 /* found next host bridge ?*/ 2614 /* found next host bridge? */
2612 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); 2615 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2613 if (pos != 0) { 2616 if (pos != 0) {
2614 pci_dev_put(dev); 2617 pci_dev_put(dev);
@@ -2767,27 +2770,27 @@ static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev)
2767{ 2770{
2768 return __nv_msi_ht_cap_quirk(dev, 1); 2771 return __nv_msi_ht_cap_quirk(dev, 1);
2769} 2772}
2773DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2774DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2770 2775
2771static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev) 2776static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev)
2772{ 2777{
2773 return __nv_msi_ht_cap_quirk(dev, 0); 2778 return __nv_msi_ht_cap_quirk(dev, 0);
2774} 2779}
2775
2776DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf); 2780DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2777DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf); 2781DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2778 2782
2779DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2780DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2781
2782static void quirk_msi_intx_disable_bug(struct pci_dev *dev) 2783static void quirk_msi_intx_disable_bug(struct pci_dev *dev)
2783{ 2784{
2784 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 2785 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2785} 2786}
2787
2786static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev) 2788static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
2787{ 2789{
2788 struct pci_dev *p; 2790 struct pci_dev *p;
2789 2791
2790 /* SB700 MSI issue will be fixed at HW level from revision A21, 2792 /*
2793 * SB700 MSI issue will be fixed at HW level from revision A21;
2791 * we need check PCI REVISION ID of SMBus controller to get SB700 2794 * we need check PCI REVISION ID of SMBus controller to get SB700
2792 * revision. 2795 * revision.
2793 */ 2796 */
@@ -2800,6 +2803,7 @@ static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
2800 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 2803 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2801 pci_dev_put(p); 2804 pci_dev_put(p);
2802} 2805}
2806
2803static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev) 2807static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev)
2804{ 2808{
2805 /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */ 2809 /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */
@@ -2869,55 +2873,56 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091,
2869 quirk_msi_intx_disable_qca_bug); 2873 quirk_msi_intx_disable_qca_bug);
2870#endif /* CONFIG_PCI_MSI */ 2874#endif /* CONFIG_PCI_MSI */
2871 2875
2872/* Allow manual resource allocation for PCI hotplug bridges 2876/*
2873 * via pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For 2877 * Allow manual resource allocation for PCI hotplug bridges via
2874 * some PCI-PCI hotplug bridges, like PLX 6254 (former HINT HB6), 2878 * pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For some PCI-PCI
2875 * kernel fails to allocate resources when hotplug device is 2879 * hotplug bridges, like PLX 6254 (former HINT HB6), kernel fails to
2876 * inserted and PCI bus is rescanned. 2880 * allocate resources when hotplug device is inserted and PCI bus is
2881 * rescanned.
2877 */ 2882 */
2878static void quirk_hotplug_bridge(struct pci_dev *dev) 2883static void quirk_hotplug_bridge(struct pci_dev *dev)
2879{ 2884{
2880 dev->is_hotplug_bridge = 1; 2885 dev->is_hotplug_bridge = 1;
2881} 2886}
2882
2883DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge); 2887DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge);
2884 2888
2885/* 2889/*
2886 * This is a quirk for the Ricoh MMC controller found as a part of 2890 * This is a quirk for the Ricoh MMC controller found as a part of some
2887 * some mulifunction chips. 2891 * multifunction chips.
2888 2892 *
2889 * This is very similar and based on the ricoh_mmc driver written by 2893 * This is very similar and based on the ricoh_mmc driver written by
2890 * Philip Langdale. Thank you for these magic sequences. 2894 * Philip Langdale. Thank you for these magic sequences.
2891 * 2895 *
2892 * These chips implement the four main memory card controllers (SD, MMC, MS, xD) 2896 * These chips implement the four main memory card controllers (SD, MMC,
2893 * and one or both of cardbus or firewire. 2897 * MS, xD) and one or both of CardBus or FireWire.
2894 * 2898 *
2895 * It happens that they implement SD and MMC 2899 * It happens that they implement SD and MMC support as separate
2896 * support as separate controllers (and PCI functions). The linux SDHCI 2900 * controllers (and PCI functions). The Linux SDHCI driver supports MMC
2897 * driver supports MMC cards but the chip detects MMC cards in hardware 2901 * cards but the chip detects MMC cards in hardware and directs them to the
2898 * and directs them to the MMC controller - so the SDHCI driver never sees 2902 * MMC controller - so the SDHCI driver never sees them.
2899 * them.
2900 * 2903 *
2901 * To get around this, we must disable the useless MMC controller. 2904 * To get around this, we must disable the useless MMC controller. At that
2902 * At that point, the SDHCI controller will start seeing them 2905 * point, the SDHCI controller will start seeing them. It seems to be the
2903 * It seems to be the case that the relevant PCI registers to deactivate the 2906 * case that the relevant PCI registers to deactivate the MMC controller
2904 * MMC controller live on PCI function 0, which might be the cardbus controller 2907 * live on PCI function 0, which might be the CardBus controller or the
2905 * or the firewire controller, depending on the particular chip in question 2908 * FireWire controller, depending on the particular chip in question
2906 * 2909 *
2907 * This has to be done early, because as soon as we disable the MMC controller 2910 * This has to be done early, because as soon as we disable the MMC controller
2908 * other pci functions shift up one level, e.g. function #2 becomes function 2911 * other PCI functions shift up one level, e.g. function #2 becomes function
2909 * #1, and this will confuse the pci core. 2912 * #1, and this will confuse the PCI core.
2910 */ 2913 */
2911
2912#ifdef CONFIG_MMC_RICOH_MMC 2914#ifdef CONFIG_MMC_RICOH_MMC
2913static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev) 2915static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev)
2914{ 2916{
2915 /* disable via cardbus interface */
2916 u8 write_enable; 2917 u8 write_enable;
2917 u8 write_target; 2918 u8 write_target;
2918 u8 disable; 2919 u8 disable;
2919 2920
2920 /* disable must be done via function #0 */ 2921 /*
2922 * Disable via CardBus interface
2923 *
2924 * This must be done via function #0
2925 */
2921 if (PCI_FUNC(dev->devfn)) 2926 if (PCI_FUNC(dev->devfn))
2922 return; 2927 return;
2923 2928
@@ -2933,7 +2938,7 @@ static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev)
2933 pci_write_config_byte(dev, 0x8E, write_enable); 2938 pci_write_config_byte(dev, 0x8E, write_enable);
2934 pci_write_config_byte(dev, 0x8D, write_target); 2939 pci_write_config_byte(dev, 0x8D, write_target);
2935 2940
2936 pci_notice(dev, "proprietary Ricoh MMC controller disabled (via cardbus function)\n"); 2941 pci_notice(dev, "proprietary Ricoh MMC controller disabled (via CardBus function)\n");
2937 pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n"); 2942 pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n");
2938} 2943}
2939DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476); 2944DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
@@ -2941,17 +2946,20 @@ DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476,
2941 2946
2942static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev) 2947static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev)
2943{ 2948{
2944 /* disable via firewire interface */
2945 u8 write_enable; 2949 u8 write_enable;
2946 u8 disable; 2950 u8 disable;
2947 2951
2948 /* disable must be done via function #0 */ 2952 /*
2953 * Disable via FireWire interface
2954 *
2955 * This must be done via function #0
2956 */
2949 if (PCI_FUNC(dev->devfn)) 2957 if (PCI_FUNC(dev->devfn))
2950 return; 2958 return;
2951 /* 2959 /*
2952 * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize 2960 * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize
2953 * certain types of SD/MMC cards. Lowering the SD base 2961 * certain types of SD/MMC cards. Lowering the SD base clock
2954 * clock frequency from 200Mhz to 50Mhz fixes this issue. 2962 * frequency from 200Mhz to 50Mhz fixes this issue.
2955 * 2963 *
2956 * 0x150 - SD2.0 mode enable for changing base clock 2964 * 0x150 - SD2.0 mode enable for changing base clock
2957 * frequency to 50Mhz 2965 * frequency to 50Mhz
@@ -2982,7 +2990,7 @@ static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev)
2982 pci_write_config_byte(dev, 0xCB, disable | 0x02); 2990 pci_write_config_byte(dev, 0xCB, disable | 0x02);
2983 pci_write_config_byte(dev, 0xCA, write_enable); 2991 pci_write_config_byte(dev, 0xCA, write_enable);
2984 2992
2985 pci_notice(dev, "proprietary Ricoh MMC controller disabled (via firewire function)\n"); 2993 pci_notice(dev, "proprietary Ricoh MMC controller disabled (via FireWire function)\n");
2986 pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n"); 2994 pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n");
2987 2995
2988} 2996}
@@ -2998,13 +3006,13 @@ DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823,
2998#define VTUNCERRMSK_REG 0x1ac 3006#define VTUNCERRMSK_REG 0x1ac
2999#define VTD_MSK_SPEC_ERRORS (1 << 31) 3007#define VTD_MSK_SPEC_ERRORS (1 << 31)
3000/* 3008/*
3001 * This is a quirk for masking vt-d spec defined errors to platform error 3009 * This is a quirk for masking VT-d spec-defined errors to platform error
3002 * handling logic. With out this, platforms using Intel 7500, 5500 chipsets 3010 * handling logic. Without this, platforms using Intel 7500, 5500 chipsets
3003 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based 3011 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based
3004 * on the RAS config settings of the platform) when a vt-d fault happens. 3012 * on the RAS config settings of the platform) when a VT-d fault happens.
3005 * The resulting SMI caused the system to hang. 3013 * The resulting SMI caused the system to hang.
3006 * 3014 *
3007 * VT-d spec related errors are already handled by the VT-d OS code, so no 3015 * VT-d spec-related errors are already handled by the VT-d OS code, so no
3008 * need to report the same error through other channels. 3016 * need to report the same error through other channels.
3009 */ 3017 */
3010static void vtd_mask_spec_errors(struct pci_dev *dev) 3018static void vtd_mask_spec_errors(struct pci_dev *dev)
@@ -3030,7 +3038,8 @@ static void fixup_ti816x_class(struct pci_dev *dev)
3030DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800, 3038DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800,
3031 PCI_CLASS_NOT_DEFINED, 8, fixup_ti816x_class); 3039 PCI_CLASS_NOT_DEFINED, 8, fixup_ti816x_class);
3032 3040
3033/* Some PCIe devices do not work reliably with the claimed maximum 3041/*
3042 * Some PCIe devices do not work reliably with the claimed maximum
3034 * payload size supported. 3043 * payload size supported.
3035 */ 3044 */
3036static void fixup_mpss_256(struct pci_dev *dev) 3045static void fixup_mpss_256(struct pci_dev *dev)
@@ -3044,9 +3053,10 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
3044DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE, 3053DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
3045 PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256); 3054 PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256);
3046 3055
3047/* Intel 5000 and 5100 Memory controllers have an errata with read completion 3056/*
3057 * Intel 5000 and 5100 Memory controllers have an erratum with read completion
3048 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B. 3058 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B.
3049 * Since there is no way of knowing what the PCIE MPS on each fabric will be 3059 * Since there is no way of knowing what the PCIe MPS on each fabric will be
3050 * until all of the devices are discovered and buses walked, read completion 3060 * until all of the devices are discovered and buses walked, read completion
3051 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because 3061 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because
3052 * it is possible to hotplug a device with MPS of 256B. 3062 * it is possible to hotplug a device with MPS of 256B.
@@ -3060,9 +3070,10 @@ static void quirk_intel_mc_errata(struct pci_dev *dev)
3060 pcie_bus_config == PCIE_BUS_DEFAULT) 3070 pcie_bus_config == PCIE_BUS_DEFAULT)
3061 return; 3071 return;
3062 3072
3063 /* Intel errata specifies bits to change but does not say what they are. 3073 /*
3064 * Keeping them magical until such time as the registers and values can 3074 * Intel erratum specifies bits to change but does not say what
3065 * be explained. 3075 * they are. Keeping them magical until such time as the registers
3076 * and values can be explained.
3066 */ 3077 */
3067 err = pci_read_config_word(dev, 0x48, &rcc); 3078 err = pci_read_config_word(dev, 0x48, &rcc);
3068 if (err) { 3079 if (err) {
@@ -3081,7 +3092,7 @@ static void quirk_intel_mc_errata(struct pci_dev *dev)
3081 return; 3092 return;
3082 } 3093 }
3083 3094
3084 pr_info_once("Read completion coalescing disabled due to hardware errata relating to 256B MPS\n"); 3095 pr_info_once("Read completion coalescing disabled due to hardware erratum relating to 256B MPS\n");
3085} 3096}
3086/* Intel 5000 series memory controllers and ports 2-7 */ 3097/* Intel 5000 series memory controllers and ports 2-7 */
3087DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata); 3098DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata);
@@ -3111,11 +3122,10 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata);
3111DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata); 3122DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata);
3112DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata); 3123DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata);
3113 3124
3114
3115/* 3125/*
3116 * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum. To 3126 * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum.
3117 * work around this, query the size it should be configured to by the device and 3127 * To work around this, query the size it should be configured to by the
3118 * modify the resource end to correspond to this new size. 3128 * device and modify the resource end to correspond to this new size.
3119 */ 3129 */
3120static void quirk_intel_ntb(struct pci_dev *dev) 3130static void quirk_intel_ntb(struct pci_dev *dev)
3121{ 3131{
@@ -3138,16 +3148,16 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb);
3138DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb); 3148DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb);
3139 3149
3140/* 3150/*
3141 * Some BIOS implementations leave the Intel GPU interrupts enabled, 3151 * Some BIOS implementations leave the Intel GPU interrupts enabled, even
3142 * even though no one is handling them (f.e. i915 driver is never loaded). 3152 * though no one is handling them (e.g., if the i915 driver is never
3143 * Additionally the interrupt destination is not set up properly 3153 * loaded). Additionally the interrupt destination is not set up properly
3144 * and the interrupt ends up -somewhere-. 3154 * and the interrupt ends up -somewhere-.
3145 * 3155 *
3146 * These spurious interrupts are "sticky" and the kernel disables 3156 * These spurious interrupts are "sticky" and the kernel disables the
3147 * the (shared) interrupt line after 100.000+ generated interrupts. 3157 * (shared) interrupt line after 100,000+ generated interrupts.
3148 * 3158 *
3149 * Fix it by disabling the still enabled interrupts. 3159 * Fix it by disabling the still enabled interrupts. This resolves crashes
3150 * This resolves crashes often seen on monitor unplug. 3160 * often seen on monitor unplug.
3151 */ 3161 */
3152#define I915_DEIER_REG 0x4400c 3162#define I915_DEIER_REG 0x4400c
3153static void disable_igfx_irq(struct pci_dev *dev) 3163static void disable_igfx_irq(struct pci_dev *dev)
@@ -3235,38 +3245,22 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REALTEK, 0x8169,
3235 * Intel i40e (XL710/X710) 10/20/40GbE NICs all have broken INTx masking, 3245 * Intel i40e (XL710/X710) 10/20/40GbE NICs all have broken INTx masking,
3236 * DisINTx can be set but the interrupt status bit is non-functional. 3246 * DisINTx can be set but the interrupt status bit is non-functional.
3237 */ 3247 */
3238DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1572, 3248DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1572, quirk_broken_intx_masking);
3239 quirk_broken_intx_masking); 3249DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1574, quirk_broken_intx_masking);
3240DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1574, 3250DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1580, quirk_broken_intx_masking);
3241 quirk_broken_intx_masking); 3251DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1581, quirk_broken_intx_masking);
3242DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1580, 3252DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1583, quirk_broken_intx_masking);
3243 quirk_broken_intx_masking); 3253DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1584, quirk_broken_intx_masking);
3244DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1581, 3254DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1585, quirk_broken_intx_masking);
3245 quirk_broken_intx_masking); 3255DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1586, quirk_broken_intx_masking);
3246DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1583, 3256DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1587, quirk_broken_intx_masking);
3247 quirk_broken_intx_masking); 3257DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1588, quirk_broken_intx_masking);
3248DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1584, 3258DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1589, quirk_broken_intx_masking);
3249 quirk_broken_intx_masking); 3259DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158a, quirk_broken_intx_masking);
3250DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1585, 3260DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158b, quirk_broken_intx_masking);
3251 quirk_broken_intx_masking); 3261DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d0, quirk_broken_intx_masking);
3252DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1586, 3262DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d1, quirk_broken_intx_masking);
3253 quirk_broken_intx_masking); 3263DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d2, quirk_broken_intx_masking);
3254DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1587,
3255 quirk_broken_intx_masking);
3256DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1588,
3257 quirk_broken_intx_masking);
3258DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1589,
3259 quirk_broken_intx_masking);
3260DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158a,
3261 quirk_broken_intx_masking);
3262DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158b,
3263 quirk_broken_intx_masking);
3264DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d0,
3265 quirk_broken_intx_masking);
3266DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d1,
3267 quirk_broken_intx_masking);
3268DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d2,
3269 quirk_broken_intx_masking);
3270 3264
3271static u16 mellanox_broken_intx_devs[] = { 3265static u16 mellanox_broken_intx_devs[] = {
3272 PCI_DEVICE_ID_MELLANOX_HERMON_SDR, 3266 PCI_DEVICE_ID_MELLANOX_HERMON_SDR,
@@ -3311,7 +3305,8 @@ static void mellanox_check_broken_intx_masking(struct pci_dev *pdev)
3311 } 3305 }
3312 } 3306 }
3313 3307
3314 /* Getting here means Connect-IB cards and up. Connect-IB has no INTx 3308 /*
3309 * Getting here means Connect-IB cards and up. Connect-IB has no INTx
3315 * support so shouldn't be checked further 3310 * support so shouldn't be checked further
3316 */ 3311 */
3317 if (pdev->device == PCI_DEVICE_ID_MELLANOX_CONNECTIB) 3312 if (pdev->device == PCI_DEVICE_ID_MELLANOX_CONNECTIB)
@@ -3431,8 +3426,8 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PORT_RIDGE,
3431 * shutdown before suspend. Otherwise the native host interface (NHI) will not 3426 * shutdown before suspend. Otherwise the native host interface (NHI) will not
3432 * be present after resume if a device was plugged in before suspend. 3427 * be present after resume if a device was plugged in before suspend.
3433 * 3428 *
3434 * The thunderbolt controller consists of a pcie switch with downstream 3429 * The Thunderbolt controller consists of a PCIe switch with downstream
3435 * bridges leading to the NHI and to the tunnel pci bridges. 3430 * bridges leading to the NHI and to the tunnel PCI bridges.
3436 * 3431 *
3437 * This quirk cuts power to the whole chip. Therefore we have to apply it 3432 * This quirk cuts power to the whole chip. Therefore we have to apply it
3438 * during suspend_noirq of the upstream bridge. 3433 * during suspend_noirq of the upstream bridge.
@@ -3450,17 +3445,19 @@ static void quirk_apple_poweroff_thunderbolt(struct pci_dev *dev)
3450 bridge = ACPI_HANDLE(&dev->dev); 3445 bridge = ACPI_HANDLE(&dev->dev);
3451 if (!bridge) 3446 if (!bridge)
3452 return; 3447 return;
3448
3453 /* 3449 /*
3454 * SXIO and SXLV are present only on machines requiring this quirk. 3450 * SXIO and SXLV are present only on machines requiring this quirk.
3455 * TB bridges in external devices might have the same device id as those 3451 * Thunderbolt bridges in external devices might have the same
3456 * on the host, but they will not have the associated ACPI methods. This 3452 * device ID as those on the host, but they will not have the
3457 * implicitly checks that we are at the right bridge. 3453 * associated ACPI methods. This implicitly checks that we are at
3454 * the right bridge.
3458 */ 3455 */
3459 if (ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXIO", &SXIO)) 3456 if (ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXIO", &SXIO))
3460 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXFP", &SXFP)) 3457 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXFP", &SXFP))
3461 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXLV", &SXLV))) 3458 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXLV", &SXLV)))
3462 return; 3459 return;
3463 pci_info(dev, "quirk: cutting power to thunderbolt controller...\n"); 3460 pci_info(dev, "quirk: cutting power to Thunderbolt controller...\n");
3464 3461
3465 /* magic sequence */ 3462 /* magic sequence */
3466 acpi_execute_simple_method(SXIO, NULL, 1); 3463 acpi_execute_simple_method(SXIO, NULL, 1);
@@ -3475,9 +3472,9 @@ DECLARE_PCI_FIXUP_SUSPEND_LATE(PCI_VENDOR_ID_INTEL,
3475 quirk_apple_poweroff_thunderbolt); 3472 quirk_apple_poweroff_thunderbolt);
3476 3473
3477/* 3474/*
3478 * Apple: Wait for the thunderbolt controller to reestablish pci tunnels. 3475 * Apple: Wait for the Thunderbolt controller to reestablish PCI tunnels
3479 * 3476 *
3480 * During suspend the thunderbolt controller is reset and all pci 3477 * During suspend the Thunderbolt controller is reset and all PCI
3481 * tunnels are lost. The NHI driver will try to reestablish all tunnels 3478 * tunnels are lost. The NHI driver will try to reestablish all tunnels
3482 * during resume. We have to manually wait for the NHI since there is 3479 * during resume. We have to manually wait for the NHI since there is
3483 * no parent child relationship between the NHI and the tunneled 3480 * no parent child relationship between the NHI and the tunneled
@@ -3492,9 +3489,10 @@ static void quirk_apple_wait_for_thunderbolt(struct pci_dev *dev)
3492 return; 3489 return;
3493 if (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM) 3490 if (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM)
3494 return; 3491 return;
3492
3495 /* 3493 /*
3496 * Find the NHI and confirm that we are a bridge on the tb host 3494 * Find the NHI and confirm that we are a bridge on the Thunderbolt
3497 * controller and not on a tb endpoint. 3495 * host controller and not on a Thunderbolt endpoint.
3498 */ 3496 */
3499 sibling = pci_get_slot(dev->bus, 0x0); 3497 sibling = pci_get_slot(dev->bus, 0x0);
3500 if (sibling == dev) 3498 if (sibling == dev)
@@ -3511,7 +3509,7 @@ static void quirk_apple_wait_for_thunderbolt(struct pci_dev *dev)
3511 nhi->device != PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI) 3509 nhi->device != PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI)
3512 || nhi->class != PCI_CLASS_SYSTEM_OTHER << 8) 3510 || nhi->class != PCI_CLASS_SYSTEM_OTHER << 8)
3513 goto out; 3511 goto out;
3514 pci_info(dev, "quirk: waiting for thunderbolt to reestablish PCI tunnels...\n"); 3512 pci_info(dev, "quirk: waiting for Thunderbolt to reestablish PCI tunnels...\n");
3515 device_pm_wait_for_dev(&dev->dev, &nhi->dev); 3513 device_pm_wait_for_dev(&dev->dev, &nhi->dev);
3516out: 3514out:
3517 pci_dev_put(nhi); 3515 pci_dev_put(nhi);
@@ -3600,9 +3598,7 @@ reset_complete:
3600 return 0; 3598 return 0;
3601} 3599}
3602 3600
3603/* 3601/* Device-specific reset method for Chelsio T4-based adapters */
3604 * Device-specific reset method for Chelsio T4-based adapters.
3605 */
3606static int reset_chelsio_generic_dev(struct pci_dev *dev, int probe) 3602static int reset_chelsio_generic_dev(struct pci_dev *dev, int probe)
3607{ 3603{
3608 u16 old_command; 3604 u16 old_command;
@@ -3885,7 +3881,7 @@ DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, PCI_CLASS_NOT_DEFINED, 8,
3885/* 3881/*
3886 * Some devices have problems with Transaction Layer Packets with the Relaxed 3882 * Some devices have problems with Transaction Layer Packets with the Relaxed
3887 * Ordering Attribute set. Such devices should mark themselves and other 3883 * Ordering Attribute set. Such devices should mark themselves and other
3888 * Device Drivers should check before sending TLPs with RO set. 3884 * device drivers should check before sending TLPs with RO set.
3889 */ 3885 */
3890static void quirk_relaxedordering_disable(struct pci_dev *dev) 3886static void quirk_relaxedordering_disable(struct pci_dev *dev)
3891{ 3887{
@@ -3895,7 +3891,7 @@ static void quirk_relaxedordering_disable(struct pci_dev *dev)
3895 3891
3896/* 3892/*
3897 * Intel Xeon processors based on Broadwell/Haswell microarchitecture Root 3893 * Intel Xeon processors based on Broadwell/Haswell microarchitecture Root
3898 * Complex has a Flow Control Credit issue which can cause performance 3894 * Complex have a Flow Control Credit issue which can cause performance
3899 * problems with Upstream Transaction Layer Packets with Relaxed Ordering set. 3895 * problems with Upstream Transaction Layer Packets with Relaxed Ordering set.
3900 */ 3896 */
3901DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f01, PCI_CLASS_NOT_DEFINED, 8, 3897DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f01, PCI_CLASS_NOT_DEFINED, 8,
@@ -3956,7 +3952,7 @@ DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0e, PCI_CLASS_NOT_DEFINED
3956 quirk_relaxedordering_disable); 3952 quirk_relaxedordering_disable);
3957 3953
3958/* 3954/*
3959 * The AMD ARM A1100 (AKA "SEATTLE") SoC has a bug in its PCIe Root Complex 3955 * The AMD ARM A1100 (aka "SEATTLE") SoC has a bug in its PCIe Root Complex
3960 * where Upstream Transaction Layer Packets with the Relaxed Ordering 3956 * where Upstream Transaction Layer Packets with the Relaxed Ordering
3961 * Attribute clear are allowed to bypass earlier TLPs with Relaxed Ordering 3957 * Attribute clear are allowed to bypass earlier TLPs with Relaxed Ordering
3962 * set. This is a violation of the PCIe 3.0 Transaction Ordering Rules 3958 * set. This is a violation of the PCIe 3.0 Transaction Ordering Rules
@@ -4020,7 +4016,7 @@ static void quirk_chelsio_T5_disable_root_port_attributes(struct pci_dev *pdev)
4020 * This mask/compare operation selects for Physical Function 4 on a 4016 * This mask/compare operation selects for Physical Function 4 on a
4021 * T5. We only need to fix up the Root Port once for any of the 4017 * T5. We only need to fix up the Root Port once for any of the
4022 * PFs. PF[0..3] have PCI Device IDs of 0x50xx, but PF4 is uniquely 4018 * PFs. PF[0..3] have PCI Device IDs of 0x50xx, but PF4 is uniquely
4023 * 0x54xx so we use that one, 4019 * 0x54xx so we use that one.
4024 */ 4020 */
4025 if ((pdev->device & 0xff00) == 0x5400) 4021 if ((pdev->device & 0xff00) == 0x5400)
4026 quirk_disable_root_port_attributes(pdev); 4022 quirk_disable_root_port_attributes(pdev);
@@ -4111,7 +4107,7 @@ static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags)
4111static int pci_quirk_xgene_acs(struct pci_dev *dev, u16 acs_flags) 4107static int pci_quirk_xgene_acs(struct pci_dev *dev, u16 acs_flags)
4112{ 4108{
4113 /* 4109 /*
4114 * X-Gene root matching this quirk do not allow peer-to-peer 4110 * X-Gene Root Ports matching this quirk do not allow peer-to-peer
4115 * transactions with others, allowing masking out these bits as if they 4111 * transactions with others, allowing masking out these bits as if they
4116 * were unimplemented in the ACS capability. 4112 * were unimplemented in the ACS capability.
4117 */ 4113 */
@@ -4434,7 +4430,7 @@ static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev)
4434 /* 4430 /*
4435 * Read the RCBA register from the LPC (D31:F0). PCH root ports 4431 * Read the RCBA register from the LPC (D31:F0). PCH root ports
4436 * are D28:F* and therefore get probed before LPC, thus we can't 4432 * are D28:F* and therefore get probed before LPC, thus we can't
4437 * use pci_get_slot/pci_read_config_dword here. 4433 * use pci_get_slot()/pci_read_config_dword() here.
4438 */ 4434 */
4439 pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0), 4435 pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0),
4440 INTEL_LPC_RCBA_REG, &rcba); 4436 INTEL_LPC_RCBA_REG, &rcba);
@@ -4567,7 +4563,7 @@ int pci_dev_specific_enable_acs(struct pci_dev *dev)
4567} 4563}
4568 4564
4569/* 4565/*
4570 * The PCI capabilities list for Intel DH895xCC VFs (device id 0x0443) with 4566 * The PCI capabilities list for Intel DH895xCC VFs (device ID 0x0443) with
4571 * QuickAssist Technology (QAT) is prematurely terminated in hardware. The 4567 * QuickAssist Technology (QAT) is prematurely terminated in hardware. The
4572 * Next Capability pointer in the MSI Capability Structure should point to 4568 * Next Capability pointer in the MSI Capability Structure should point to
4573 * the PCIe Capability Structure but is incorrectly hardwired as 0 terminating 4569 * the PCIe Capability Structure but is incorrectly hardwired as 0 terminating
@@ -4628,9 +4624,7 @@ static void quirk_intel_qat_vf_cap(struct pci_dev *pdev)
4628 if (pci_find_saved_cap(pdev, PCI_CAP_ID_EXP)) 4624 if (pci_find_saved_cap(pdev, PCI_CAP_ID_EXP))
4629 return; 4625 return;
4630 4626
4631 /* 4627 /* Save PCIe cap */
4632 * Save PCIE cap
4633 */
4634 state = kzalloc(sizeof(*state) + size, GFP_KERNEL); 4628 state = kzalloc(sizeof(*state) + size, GFP_KERNEL);
4635 if (!state) 4629 if (!state)
4636 return; 4630 return;
@@ -4651,7 +4645,7 @@ static void quirk_intel_qat_vf_cap(struct pci_dev *pdev)
4651} 4645}
4652DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap); 4646DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap);
4653 4647
4654/* FLR may cause some 82579 devices to hang. */ 4648/* FLR may cause some 82579 devices to hang */
4655static void quirk_intel_no_flr(struct pci_dev *dev) 4649static void quirk_intel_no_flr(struct pci_dev *dev)
4656{ 4650{
4657 dev->dev_flags |= PCI_DEV_FLAGS_NO_FLR_RESET; 4651 dev->dev_flags |= PCI_DEV_FLAGS_NO_FLR_RESET;
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-23 17:57:26 -0400