diff options
author | Thomas Gleixner <tglx@linutronix.de> | 2018-05-10 14:42:48 -0400 |
---|---|---|
committer | Thomas Gleixner <tglx@linutronix.de> | 2018-05-17 11:09:21 -0400 |
commit | 47c61b3955cf712cadfc25635bf9bc174af030ea (patch) | |
tree | d25d09aa3b84755bd8296a9e0e6a32c3884cd5ac | |
parent | be6fcb5478e95bb1c91f489121238deb3abca46a (diff) |
x86/speculation, KVM: Implement support for VIRT_SPEC_CTRL/LS_CFG
Add the necessary logic for supporting the emulated VIRT_SPEC_CTRL MSR to
x86_virt_spec_ctrl(). If either X86_FEATURE_LS_CFG_SSBD or
X86_FEATURE_VIRT_SPEC_CTRL is set then use the new guest_virt_spec_ctrl
argument to check whether the state must be modified on the host. The
update reuses speculative_store_bypass_update() so the ZEN-specific sibling
coordination can be reused.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
-rw-r--r-- | arch/x86/include/asm/spec-ctrl.h | 6 | ||||
-rw-r--r-- | arch/x86/kernel/cpu/bugs.c | 30 |
2 files changed, 36 insertions, 0 deletions
diff --git a/arch/x86/include/asm/spec-ctrl.h b/arch/x86/include/asm/spec-ctrl.h index 763d49710329..ae7c2c5cd7f0 100644 --- a/arch/x86/include/asm/spec-ctrl.h +++ b/arch/x86/include/asm/spec-ctrl.h | |||
@@ -53,6 +53,12 @@ static inline u64 ssbd_tif_to_spec_ctrl(u64 tifn) | |||
53 | return (tifn & _TIF_SSBD) >> (TIF_SSBD - SPEC_CTRL_SSBD_SHIFT); | 53 | return (tifn & _TIF_SSBD) >> (TIF_SSBD - SPEC_CTRL_SSBD_SHIFT); |
54 | } | 54 | } |
55 | 55 | ||
56 | static inline unsigned long ssbd_spec_ctrl_to_tif(u64 spec_ctrl) | ||
57 | { | ||
58 | BUILD_BUG_ON(TIF_SSBD < SPEC_CTRL_SSBD_SHIFT); | ||
59 | return (spec_ctrl & SPEC_CTRL_SSBD) << (TIF_SSBD - SPEC_CTRL_SSBD_SHIFT); | ||
60 | } | ||
61 | |||
56 | static inline u64 ssbd_tif_to_amd_ls_cfg(u64 tifn) | 62 | static inline u64 ssbd_tif_to_amd_ls_cfg(u64 tifn) |
57 | { | 63 | { |
58 | return (tifn & _TIF_SSBD) ? x86_amd_ls_cfg_ssbd_mask : 0ULL; | 64 | return (tifn & _TIF_SSBD) ? x86_amd_ls_cfg_ssbd_mask : 0ULL; |
diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index 8e327bfec513..7416fc206b4a 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c | |||
@@ -162,6 +162,36 @@ x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool setguest) | |||
162 | wrmsrl(MSR_IA32_SPEC_CTRL, msrval); | 162 | wrmsrl(MSR_IA32_SPEC_CTRL, msrval); |
163 | } | 163 | } |
164 | } | 164 | } |
165 | |||
166 | /* | ||
167 | * If SSBD is not handled in MSR_SPEC_CTRL on AMD, update | ||
168 | * MSR_AMD64_L2_CFG or MSR_VIRT_SPEC_CTRL if supported. | ||
169 | */ | ||
170 | if (!static_cpu_has(X86_FEATURE_LS_CFG_SSBD) && | ||
171 | !static_cpu_has(X86_FEATURE_VIRT_SSBD)) | ||
172 | return; | ||
173 | |||
174 | /* | ||
175 | * If the host has SSBD mitigation enabled, force it in the host's | ||
176 | * virtual MSR value. If its not permanently enabled, evaluate | ||
177 | * current's TIF_SSBD thread flag. | ||
178 | */ | ||
179 | if (static_cpu_has(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE)) | ||
180 | hostval = SPEC_CTRL_SSBD; | ||
181 | else | ||
182 | hostval = ssbd_tif_to_spec_ctrl(ti->flags); | ||
183 | |||
184 | /* Sanitize the guest value */ | ||
185 | guestval = guest_virt_spec_ctrl & SPEC_CTRL_SSBD; | ||
186 | |||
187 | if (hostval != guestval) { | ||
188 | unsigned long tif; | ||
189 | |||
190 | tif = setguest ? ssbd_spec_ctrl_to_tif(guestval) : | ||
191 | ssbd_spec_ctrl_to_tif(hostval); | ||
192 | |||
193 | speculative_store_bypass_update(tif); | ||
194 | } | ||
165 | } | 195 | } |
166 | EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl); | 196 | EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl); |
167 | 197 | ||