1 files changed, 30 insertions, 0 deletions

diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c
index 8e327bfec513..7416fc206b4a 100644
--- a/arch/x86/kernel/cpu/bugs.c
+++ b/arch/x86/kernel/cpu/bugs.c
@@ -162,6 +162,36 @@ x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool setguest)
                         wrmsrl(MSR_IA32_SPEC_CTRL, msrval);
                 }
         }
+
+        /*
+         * If SSBD is not handled in MSR_SPEC_CTRL on AMD, update
+         * MSR_AMD64_L2_CFG or MSR_VIRT_SPEC_CTRL if supported.
+         */
+        if (!static_cpu_has(X86_FEATURE_LS_CFG_SSBD) &&
+            !static_cpu_has(X86_FEATURE_VIRT_SSBD))
+                return;
+
+        /*
+         * If the host has SSBD mitigation enabled, force it in the host's
+         * virtual MSR value. If its not permanently enabled, evaluate
+         * current's TIF_SSBD thread flag.
+         */
+        if (static_cpu_has(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE))
+                hostval = SPEC_CTRL_SSBD;
+        else
+                hostval = ssbd_tif_to_spec_ctrl(ti->flags);
+
+        /* Sanitize the guest value */
+        guestval = guest_virt_spec_ctrl & SPEC_CTRL_SSBD;
+
+        if (hostval != guestval) {
+                unsigned long tif;
+
+                tif = setguest ? ssbd_spec_ctrl_to_tif(guestval) :
+                                 ssbd_spec_ctrl_to_tif(hostval);
+
+                speculative_store_bypass_update(tif);
+        }
 }
 EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl);