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authorArnd Bergmann <arnd@arndb.de>2018-10-02 05:36:53 -0400
committerArnd Bergmann <arnd@arndb.de>2018-10-02 05:41:29 -0400
commit476ca77f0f13d0dd30cdaf91d797cddab4976848 (patch)
tree6a3e5c2f3696e5b45b4323a744e70cdcba4dc965
parent55dc97235b6553d27661ee1fb05d882c7c776b96 (diff)
parent04007fe4c65f4cf3133dd256d9fd82169b7f2f22 (diff)
Merge tag 'imx-dt-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt
i.MX device tree update for 4.20: - New board support: Engicam's i.Core MX6 CPU module v1.5; ConnectCore 6UL Single Board Computer (SBC) Pro; i.MX6 ULZ based EVK board. - Add Add SFF interface support for vf610-zii board. - Disable unneeded devices like VPU and internal watchdog for imx51-zii boards. - Add 'no-sdio' and 'no-sd' property for vf610-zii-cfu1 board. - Improve i.MX6 SLL GPIO support by adding gpio-ranges property and clocks information. - Update iomux header for i.MX7 Solo and i.MX6 ULL. - Enable GPIO buttons as wakeup source for imx7d-sdb and imx6sx-sdb. - Add GPIO keys and egalax touch screen support for imx6qdl-sabreauto. - Switch to use SPDX-License-Identifier for more boards - vf610-twr, imx7s-warp, Engicam boards. - Add device tree bindings of 'fsl,pmic-stby-poweroff' property and add the support for i.MX6 RIoTboard. - DTC has new checks for SPI buses which will be landed on 4.20. A patch from Rob to fix those 100+ warnings on i.MX boards. (Thanks!) - Switch i.MX7 device tree to use updated coresight binding for hardware ports. - Misc small or random update and cleanup. * tag 'imx-dt-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (50 commits) ARM: dts: imx: add i.mx6ulz and i.mx6ulz 14x14 evk support dt-bindings: arm: add compatible for i.MX6ULZ 14x14 EVK board ARM: dts: imx53-ppd: Remove 'num-chipselects' property ARM: dts: vf610-twr: Switch to SPDX identifier ARM: dts: vf: Switch to SPDX identifier ARM: dts: imx6qdl-zii-rdu2: Disable the internal RTC ARM: dts: imx51-zii-rdu1: Fix the rtc compatible string ARM: dts: imx6ul: use nvmem-cells for cpu speed grading ARM: dts: imx: Fix SPI bus warnings ARM: dts: imx7: Update coresight binding for hardware ports ARM: dts: vf610-zii-cfu1: Pass the 'no-sd' property ARM: dts: vf610-zii-cfu1: Pass the 'no-sdio' property ARM: dts: imx51-zii-scu2-mezz: Disable the internal watchdog ARM: dts: imx51-zii-scu2-mezz: Disable VPU ARM: dts: imx51-zii-scu3-esb: Disable VPU ARM: dts: imx51: Add label for VPU node ARM: dts: imx6ull: update vdd_soc voltage for 900MHz operating point ARM: dts: imx6ul: Add DTS for ConnectCore 6UL SBC Pro ARM: dts: imx6: RIoTboard provide standby on power off option dt-bindings: imx6q-clock: add new fsl,pmic-stby-poweroff property ... Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat
-rw-r--r--Documentation/devicetree/bindings/arm/fsl.txt44
-rw-r--r--Documentation/devicetree/bindings/clock/imx6q-clock.txt8
-rw-r--r--arch/arm/boot/dts/Makefile4
-rw-r--r--arch/arm/boot/dts/imx1.dtsi4
-rw-r--r--arch/arm/boot/dts/imx23-evk.dts2
-rw-r--r--arch/arm/boot/dts/imx23-olinuxino.dts4
-rw-r--r--arch/arm/boot/dts/imx23-sansa.dts4
-rw-r--r--arch/arm/boot/dts/imx23-stmp378x_devb.dts2
-rw-r--r--arch/arm/boot/dts/imx23-xfi3.dts4
-rw-r--r--arch/arm/boot/dts/imx23.dtsi4
-rw-r--r--arch/arm/boot/dts/imx25.dtsi6
-rw-r--r--arch/arm/boot/dts/imx27.dtsi6
-rw-r--r--arch/arm/boot/dts/imx28-apf28dev.dts4
-rw-r--r--arch/arm/boot/dts/imx28-apx4devkit.dts4
-rw-r--r--arch/arm/boot/dts/imx28-cfa10036.dts2
-rw-r--r--arch/arm/boot/dts/imx28-duckbill-2-485.dts4
-rw-r--r--arch/arm/boot/dts/imx28-duckbill-2-enocean.dts4
-rw-r--r--arch/arm/boot/dts/imx28-duckbill-2-spi.dts4
-rw-r--r--arch/arm/boot/dts/imx28-duckbill-2.dts4
-rw-r--r--arch/arm/boot/dts/imx28-duckbill.dts4
-rw-r--r--arch/arm/boot/dts/imx28-evk.dts6
-rw-r--r--arch/arm/boot/dts/imx28-m28cu3.dts4
-rw-r--r--arch/arm/boot/dts/imx28-m28evk.dts4
-rw-r--r--arch/arm/boot/dts/imx28-sps1.dts4
-rw-r--r--arch/arm/boot/dts/imx28-ts4600.dts2
-rw-r--r--arch/arm/boot/dts/imx28.dtsi8
-rw-r--r--arch/arm/boot/dts/imx31.dtsi4
-rw-r--r--arch/arm/boot/dts/imx35.dtsi4
-rw-r--r--arch/arm/boot/dts/imx50.dtsi6
-rw-r--r--arch/arm/boot/dts/imx51-babbage.dts1
-rw-r--r--arch/arm/boot/dts/imx51-zii-rdu1.dts2
-rw-r--r--arch/arm/boot/dts/imx51-zii-scu2-mezz.dts8
-rw-r--r--arch/arm/boot/dts/imx51-zii-scu3-esb.dts4
-rw-r--r--arch/arm/boot/dts/imx51.dtsi8
-rw-r--r--arch/arm/boot/dts/imx53-ppd.dts1
-rw-r--r--arch/arm/boot/dts/imx53.dtsi6
-rw-r--r--arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts2
-rw-r--r--arch/arm/boot/dts/imx6dl-icore-mipi.dts2
-rw-r--r--arch/arm/boot/dts/imx6dl-icore-rqs.dts38
-rw-r--r--arch/arm/boot/dts/imx6dl-icore.dts38
-rw-r--r--arch/arm/boot/dts/imx6dl-riotboard.dts5
-rw-r--r--arch/arm/boot/dts/imx6q-apalis-eval.dts2
-rw-r--r--arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts2
-rw-r--r--arch/arm/boot/dts/imx6q-apalis-ixora.dts2
-rw-r--r--arch/arm/boot/dts/imx6q-icore-mipi.dts6
-rw-r--r--arch/arm/boot/dts/imx6q-icore-ofcap10.dts38
-rw-r--r--arch/arm/boot/dts/imx6q-icore-ofcap12.dts38
-rw-r--r--arch/arm/boot/dts/imx6q-icore-rqs.dts39
-rw-r--r--arch/arm/boot/dts/imx6q-icore.dts38
-rw-r--r--arch/arm/boot/dts/imx6q.dtsi2
-rw-r--r--arch/arm/boot/dts/imx6qdl-apalis.dtsi4
-rw-r--r--arch/arm/boot/dts/imx6qdl-icore-1.5.dtsi34
-rw-r--r--arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi41
-rw-r--r--arch/arm/boot/dts/imx6qdl-icore.dtsi42
-rw-r--r--arch/arm/boot/dts/imx6qdl-sabreauto.dtsi67
-rw-r--r--arch/arm/boot/dts/imx6qdl-wandboard.dtsi4
-rw-r--r--arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi4
-rw-r--r--arch/arm/boot/dts/imx6qdl.dtsi8
-rw-r--r--arch/arm/boot/dts/imx6sl.dtsi8
-rw-r--r--arch/arm/boot/dts/imx6sll.dtsi31
-rw-r--r--arch/arm/boot/dts/imx6sx-sdb.dtsi2
-rw-r--r--arch/arm/boot/dts/imx6sx.dtsi14
-rw-r--r--arch/arm/boot/dts/imx6ul-ccimx6ulsbcpro.dts390
-rw-r--r--arch/arm/boot/dts/imx6ul-geam.dts40
-rw-r--r--arch/arm/boot/dts/imx6ul-isiot-emmc.dts61
-rw-r--r--arch/arm/boot/dts/imx6ul-isiot-nand.dts63
-rw-r--r--arch/arm/boot/dts/imx6ul-isiot.dtsi90
-rw-r--r--arch/arm/boot/dts/imx6ul.dtsi28
-rw-r--r--arch/arm/boot/dts/imx6ull-14x14-evk.dts2
-rw-r--r--arch/arm/boot/dts/imx6ull-pinfunc.h39
-rw-r--r--arch/arm/boot/dts/imx6ull.dtsi2
-rw-r--r--arch/arm/boot/dts/imx6ulz-14x14-evk.dts20
-rw-r--r--arch/arm/boot/dts/imx6ulz.dtsi38
-rw-r--r--arch/arm/boot/dts/imx7d-sdb.dts2
-rw-r--r--arch/arm/boot/dts/imx7d.dtsi15
-rw-r--r--arch/arm/boot/dts/imx7s-warp.dts53
-rw-r--r--arch/arm/boot/dts/imx7s.dtsi131
-rw-r--r--arch/arm/boot/dts/imx7ulp-pinfunc.h16
-rw-r--r--arch/arm/boot/dts/ls1021a-qds.dts2
-rw-r--r--arch/arm/boot/dts/ls1021a-twr.dts2
-rw-r--r--arch/arm/boot/dts/ls1021a.dtsi12
-rw-r--r--arch/arm/boot/dts/vf500.dtsi43
-rw-r--r--arch/arm/boot/dts/vf610-twr.dts43
-rw-r--r--arch/arm/boot/dts/vf610-zii-cfu1.dts30
-rw-r--r--arch/arm/boot/dts/vf610-zii-dev-rev-c.dts44
-rw-r--r--arch/arm/boot/dts/vf610.dtsi44
-rw-r--r--arch/arm/boot/dts/vfxxx.dtsi55
87 files changed, 1081 insertions, 889 deletions
diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt
index 8a1baa2b9723..7b964d8772e6 100644
--- a/Documentation/devicetree/bindings/arm/fsl.txt
+++ b/Documentation/devicetree/bindings/arm/fsl.txt
@@ -57,6 +57,50 @@ i.MX6SLL EVK board
57Required root node properties: 57Required root node properties:
58 - compatible = "fsl,imx6sll-evk", "fsl,imx6sll"; 58 - compatible = "fsl,imx6sll-evk", "fsl,imx6sll";
59 59
60i.MX6 Quad Plus SABRE Smart Device Board
61Required root node properties:
62 - compatible = "fsl,imx6qp-sabresd", "fsl,imx6qp";
63
64i.MX6 Quad Plus SABRE Automotive Board
65Required root node properties:
66 - compatible = "fsl,imx6qp-sabreauto", "fsl,imx6qp";
67
68i.MX6 DualLite SABRE Smart Device Board
69Required root node properties:
70 - compatible = "fsl,imx6dl-sabresd", "fsl,imx6dl";
71
72i.MX6 DualLite/Solo SABRE Automotive Board
73Required root node properties:
74 - compatible = "fsl,imx6dl-sabreauto", "fsl,imx6dl";
75
76i.MX6 SoloLite EVK Board
77Required root node properties:
78 - compatible = "fsl,imx6sl-evk", "fsl,imx6sl";
79
80i.MX6 UltraLite 14x14 EVK Board
81Required root node properties:
82 - compatible = "fsl,imx6ul-14x14-evk", "fsl,imx6ul";
83
84i.MX6 UltraLiteLite 14x14 EVK Board
85Required root node properties:
86 - compatible = "fsl,imx6ull-14x14-evk", "fsl,imx6ull";
87
88i.MX6 ULZ 14x14 EVK Board
89Required root node properties:
90 - compatible = "fsl,imx6ulz-14x14-evk", "fsl,imx6ull", "fsl,imx6ulz";
91
92i.MX6 SoloX SDB Board
93Required root node properties:
94 - compatible = "fsl,imx6sx-sdb", "fsl,imx6sx";
95
96i.MX6 SoloX Sabre Auto Board
97Required root node properties:
98 - compatible = "fsl,imx6sx-sabreauto", "fsl,imx6sx";
99
100i.MX7 SabreSD Board
101Required root node properties:
102 - compatible = "fsl,imx7d-sdb", "fsl,imx7d";
103
60Generic i.MX boards 104Generic i.MX boards
61------------------- 105-------------------
62 106
diff --git a/Documentation/devicetree/bindings/clock/imx6q-clock.txt b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
index a45ca67a9d5f..e1308346e00d 100644
--- a/Documentation/devicetree/bindings/clock/imx6q-clock.txt
+++ b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
@@ -6,6 +6,14 @@ Required properties:
6- interrupts: Should contain CCM interrupt 6- interrupts: Should contain CCM interrupt
7- #clock-cells: Should be <1> 7- #clock-cells: Should be <1>
8 8
9Optional properties:
10- fsl,pmic-stby-poweroff: Configure CCM to assert PMIC_STBY_REQ signal
11 on power off.
12 Use this property if the SoC should be powered off by external power
13 management IC (PMIC) triggered via PMIC_STBY_REQ signal.
14 Boards that are designed to initiate poweroff on PMIC_ON_REQ signal should
15 be using "syscon-poweroff" driver instead.
16
9The clock consumer should specify the desired clock by having the clock 17The clock consumer should specify the desired clock by having the clock
10ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx6qdl-clock.h 18ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx6qdl-clock.h
11for the full list of i.MX6 Quad and DualLite clock IDs. 19for the full list of i.MX6 Quad and DualLite clock IDs.
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 7edf93d1ba73..b16bfb32dda5 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -550,6 +550,7 @@ dtb-$(CONFIG_SOC_IMX6SX) += \
550dtb-$(CONFIG_SOC_IMX6UL) += \ 550dtb-$(CONFIG_SOC_IMX6UL) += \
551 imx6ul-14x14-evk.dtb \ 551 imx6ul-14x14-evk.dtb \
552 imx6ul-ccimx6ulsbcexpress.dtb \ 552 imx6ul-ccimx6ulsbcexpress.dtb \
553 imx6ul-ccimx6ulsbcpro.dtb \
553 imx6ul-geam.dtb \ 554 imx6ul-geam.dtb \
554 imx6ul-isiot-emmc.dtb \ 555 imx6ul-isiot-emmc.dtb \
555 imx6ul-isiot-nand.dtb \ 556 imx6ul-isiot-nand.dtb \
@@ -561,7 +562,8 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
561 imx6ul-tx6ul-mainboard.dtb \ 562 imx6ul-tx6ul-mainboard.dtb \
562 imx6ull-14x14-evk.dtb \ 563 imx6ull-14x14-evk.dtb \
563 imx6ull-colibri-eval-v3.dtb \ 564 imx6ull-colibri-eval-v3.dtb \
564 imx6ull-colibri-wifi-eval-v3.dtb 565 imx6ull-colibri-wifi-eval-v3.dtb \
566 imx6ulz-14x14-evk.dtb
565dtb-$(CONFIG_SOC_IMX7D) += \ 567dtb-$(CONFIG_SOC_IMX7D) += \
566 imx7d-cl-som-imx7.dtb \ 568 imx7d-cl-som-imx7.dtb \
567 imx7d-colibri-emmc-eval-v3.dtb \ 569 imx7d-colibri-emmc-eval-v3.dtb \
diff --git a/arch/arm/boot/dts/imx1.dtsi b/arch/arm/boot/dts/imx1.dtsi
index 3edc7b5550d8..b00ece16b853 100644
--- a/arch/arm/boot/dts/imx1.dtsi
+++ b/arch/arm/boot/dts/imx1.dtsi
@@ -164,7 +164,7 @@
164 reg = <0x00210000 0x10000>; 164 reg = <0x00210000 0x10000>;
165 ranges; 165 ranges;
166 166
167 cspi1: cspi@213000 { 167 cspi1: spi@213000 {
168 #address-cells = <1>; 168 #address-cells = <1>;
169 #size-cells = <0>; 169 #size-cells = <0>;
170 compatible = "fsl,imx1-cspi"; 170 compatible = "fsl,imx1-cspi";
@@ -186,7 +186,7 @@
186 status = "disabled"; 186 status = "disabled";
187 }; 187 };
188 188
189 cspi2: cspi@219000 { 189 cspi2: spi@219000 {
190 #address-cells = <1>; 190 #address-cells = <1>;
191 #size-cells = <0>; 191 #size-cells = <0>;
192 compatible = "fsl,imx1-cspi"; 192 compatible = "fsl,imx1-cspi";
diff --git a/arch/arm/boot/dts/imx23-evk.dts b/arch/arm/boot/dts/imx23-evk.dts
index ad2ae25b7b4d..98efe1aeb26a 100644
--- a/arch/arm/boot/dts/imx23-evk.dts
+++ b/arch/arm/boot/dts/imx23-evk.dts
@@ -58,7 +58,7 @@
58 status = "okay"; 58 status = "okay";
59 }; 59 };
60 60
61 ssp0: ssp@80010000 { 61 ssp0: spi@80010000 {
62 compatible = "fsl,imx23-mmc"; 62 compatible = "fsl,imx23-mmc";
63 pinctrl-names = "default"; 63 pinctrl-names = "default";
64 pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>; 64 pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>;
diff --git a/arch/arm/boot/dts/imx23-olinuxino.dts b/arch/arm/boot/dts/imx23-olinuxino.dts
index e9351774c619..31b1e3581ac0 100644
--- a/arch/arm/boot/dts/imx23-olinuxino.dts
+++ b/arch/arm/boot/dts/imx23-olinuxino.dts
@@ -25,7 +25,7 @@
25 25
26 apb@80000000 { 26 apb@80000000 {
27 apbh@80000000 { 27 apbh@80000000 {
28 ssp0: ssp@80010000 { 28 ssp0: spi@80010000 {
29 compatible = "fsl,imx23-mmc"; 29 compatible = "fsl,imx23-mmc";
30 pinctrl-names = "default"; 30 pinctrl-names = "default";
31 pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>; 31 pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>;
@@ -59,7 +59,7 @@
59 }; 59 };
60 }; 60 };
61 61
62 ssp1: ssp@80034000 { 62 ssp1: spi@80034000 {
63 #address-cells = <1>; 63 #address-cells = <1>;
64 #size-cells = <0>; 64 #size-cells = <0>;
65 compatible = "fsl,imx23-spi"; 65 compatible = "fsl,imx23-spi";
diff --git a/arch/arm/boot/dts/imx23-sansa.dts b/arch/arm/boot/dts/imx23-sansa.dts
index 67de7863ad79..faf701b2adb2 100644
--- a/arch/arm/boot/dts/imx23-sansa.dts
+++ b/arch/arm/boot/dts/imx23-sansa.dts
@@ -55,7 +55,7 @@
55 55
56 apb@80000000 { 56 apb@80000000 {
57 apbh@80000000 { 57 apbh@80000000 {
58 ssp0: ssp@80010000 { 58 ssp0: spi@80010000 {
59 compatible = "fsl,imx23-mmc"; 59 compatible = "fsl,imx23-mmc";
60 pinctrl-names = "default"; 60 pinctrl-names = "default";
61 pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>; 61 pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>;
@@ -65,7 +65,7 @@
65 status = "okay"; 65 status = "okay";
66 }; 66 };
67 67
68 ssp1: ssp@80034000 { 68 ssp1: spi@80034000 {
69 compatible = "fsl,imx23-mmc"; 69 compatible = "fsl,imx23-mmc";
70 pinctrl-names = "default"; 70 pinctrl-names = "default";
71 pinctrl-0 = <&mmc1_8bit_pins_a>; 71 pinctrl-0 = <&mmc1_8bit_pins_a>;
diff --git a/arch/arm/boot/dts/imx23-stmp378x_devb.dts b/arch/arm/boot/dts/imx23-stmp378x_devb.dts
index 95c7b918f6d6..2ff6cdf71a55 100644
--- a/arch/arm/boot/dts/imx23-stmp378x_devb.dts
+++ b/arch/arm/boot/dts/imx23-stmp378x_devb.dts
@@ -22,7 +22,7 @@
22 22
23 apb@80000000 { 23 apb@80000000 {
24 apbh@80000000 { 24 apbh@80000000 {
25 ssp0: ssp@80010000 { 25 ssp0: spi@80010000 {
26 compatible = "fsl,imx23-mmc"; 26 compatible = "fsl,imx23-mmc";
27 pinctrl-names = "default"; 27 pinctrl-names = "default";
28 pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>; 28 pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>;
diff --git a/arch/arm/boot/dts/imx23-xfi3.dts b/arch/arm/boot/dts/imx23-xfi3.dts
index 9616e500b996..db53089fb7fb 100644
--- a/arch/arm/boot/dts/imx23-xfi3.dts
+++ b/arch/arm/boot/dts/imx23-xfi3.dts
@@ -54,7 +54,7 @@
54 54
55 apb@80000000 { 55 apb@80000000 {
56 apbh@80000000 { 56 apbh@80000000 {
57 ssp0: ssp@80010000 { 57 ssp0: spi@80010000 {
58 compatible = "fsl,imx23-mmc"; 58 compatible = "fsl,imx23-mmc";
59 pinctrl-names = "default"; 59 pinctrl-names = "default";
60 pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>; 60 pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>;
@@ -64,7 +64,7 @@
64 status = "okay"; 64 status = "okay";
65 }; 65 };
66 66
67 ssp1: ssp@80034000 { 67 ssp1: spi@80034000 {
68 compatible = "fsl,imx23-mmc"; 68 compatible = "fsl,imx23-mmc";
69 pinctrl-names = "default"; 69 pinctrl-names = "default";
70 pinctrl-0 = <&mmc1_4bit_pins_a>; 70 pinctrl-0 = <&mmc1_4bit_pins_a>;
diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi
index 71bfd2b15609..ea259927eef6 100644
--- a/arch/arm/boot/dts/imx23.dtsi
+++ b/arch/arm/boot/dts/imx23.dtsi
@@ -93,7 +93,7 @@
93 status = "disabled"; 93 status = "disabled";
94 }; 94 };
95 95
96 ssp0: ssp@80010000 { 96 ssp0: spi@80010000 {
97 reg = <0x80010000 0x2000>; 97 reg = <0x80010000 0x2000>;
98 interrupts = <15>; 98 interrupts = <15>;
99 clocks = <&clks 33>; 99 clocks = <&clks 33>;
@@ -457,7 +457,7 @@
457 status = "disabled"; 457 status = "disabled";
458 }; 458 };
459 459
460 ssp1: ssp@80034000 { 460 ssp1: spi@80034000 {
461 reg = <0x80034000 0x2000>; 461 reg = <0x80034000 0x2000>;
462 interrupts = <2>; 462 interrupts = <2>;
463 clocks = <&clks 33>; 463 clocks = <&clks 33>;
diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi
index 85c15ee63272..b25309d26ea5 100644
--- a/arch/arm/boot/dts/imx25.dtsi
+++ b/arch/arm/boot/dts/imx25.dtsi
@@ -168,7 +168,7 @@
168 status = "disabled"; 168 status = "disabled";
169 }; 169 };
170 170
171 spi1: cspi@43fa4000 { 171 spi1: spi@43fa4000 {
172 #address-cells = <1>; 172 #address-cells = <1>;
173 #size-cells = <0>; 173 #size-cells = <0>;
174 compatible = "fsl,imx25-cspi", "fsl,imx35-cspi"; 174 compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
@@ -209,7 +209,7 @@
209 reg = <0x50000000 0x40000>; 209 reg = <0x50000000 0x40000>;
210 ranges; 210 ranges;
211 211
212 spi3: cspi@50004000 { 212 spi3: spi@50004000 {
213 #address-cells = <1>; 213 #address-cells = <1>;
214 #size-cells = <0>; 214 #size-cells = <0>;
215 compatible = "fsl,imx25-cspi", "fsl,imx35-cspi"; 215 compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
@@ -238,7 +238,7 @@
238 status = "disabled"; 238 status = "disabled";
239 }; 239 };
240 240
241 spi2: cspi@50010000 { 241 spi2: spi@50010000 {
242 #address-cells = <1>; 242 #address-cells = <1>;
243 #size-cells = <0>; 243 #size-cells = <0>;
244 compatible = "fsl,imx25-cspi", "fsl,imx35-cspi"; 244 compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi
index 753d88df1627..151b0eb17dda 100644
--- a/arch/arm/boot/dts/imx27.dtsi
+++ b/arch/arm/boot/dts/imx27.dtsi
@@ -209,7 +209,7 @@
209 status = "disabled"; 209 status = "disabled";
210 }; 210 };
211 211
212 cspi1: cspi@1000e000 { 212 cspi1: spi@1000e000 {
213 #address-cells = <1>; 213 #address-cells = <1>;
214 #size-cells = <0>; 214 #size-cells = <0>;
215 compatible = "fsl,imx27-cspi"; 215 compatible = "fsl,imx27-cspi";
@@ -221,7 +221,7 @@
221 status = "disabled"; 221 status = "disabled";
222 }; 222 };
223 223
224 cspi2: cspi@1000f000 { 224 cspi2: spi@1000f000 {
225 #address-cells = <1>; 225 #address-cells = <1>;
226 #size-cells = <0>; 226 #size-cells = <0>;
227 compatible = "fsl,imx27-cspi"; 227 compatible = "fsl,imx27-cspi";
@@ -373,7 +373,7 @@
373 status = "disabled"; 373 status = "disabled";
374 }; 374 };
375 375
376 cspi3: cspi@10017000 { 376 cspi3: spi@10017000 {
377 #address-cells = <1>; 377 #address-cells = <1>;
378 #size-cells = <0>; 378 #size-cells = <0>;
379 compatible = "fsl,imx27-cspi"; 379 compatible = "fsl,imx27-cspi";
diff --git a/arch/arm/boot/dts/imx28-apf28dev.dts b/arch/arm/boot/dts/imx28-apf28dev.dts
index c4fadbc1b400..8df5ec470376 100644
--- a/arch/arm/boot/dts/imx28-apf28dev.dts
+++ b/arch/arm/boot/dts/imx28-apf28dev.dts
@@ -18,7 +18,7 @@
18 18
19 apb@80000000 { 19 apb@80000000 {
20 apbh@80000000 { 20 apbh@80000000 {
21 ssp0: ssp@80010000 { 21 ssp0: spi@80010000 {
22 compatible = "fsl,imx28-mmc"; 22 compatible = "fsl,imx28-mmc";
23 pinctrl-names = "default"; 23 pinctrl-names = "default";
24 pinctrl-0 = <&mmc0_4bit_pins_a 24 pinctrl-0 = <&mmc0_4bit_pins_a
@@ -27,7 +27,7 @@
27 status = "okay"; 27 status = "okay";
28 }; 28 };
29 29
30 ssp2: ssp@80014000 { 30 ssp2: spi@80014000 {
31 compatible = "fsl,imx28-spi"; 31 compatible = "fsl,imx28-spi";
32 pinctrl-names = "default"; 32 pinctrl-names = "default";
33 pinctrl-0 = <&spi2_pins_a>; 33 pinctrl-0 = <&spi2_pins_a>;
diff --git a/arch/arm/boot/dts/imx28-apx4devkit.dts b/arch/arm/boot/dts/imx28-apx4devkit.dts
index 96faa53ba44c..6c9b498305c0 100644
--- a/arch/arm/boot/dts/imx28-apx4devkit.dts
+++ b/arch/arm/boot/dts/imx28-apx4devkit.dts
@@ -18,7 +18,7 @@
18 status = "okay"; 18 status = "okay";
19 }; 19 };
20 20
21 ssp0: ssp@80010000 { 21 ssp0: spi@80010000 {
22 compatible = "fsl,imx28-mmc"; 22 compatible = "fsl,imx28-mmc";
23 pinctrl-names = "default"; 23 pinctrl-names = "default";
24 pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_sck_cfg>; 24 pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_sck_cfg>;
@@ -26,7 +26,7 @@
26 status = "okay"; 26 status = "okay";
27 }; 27 };
28 28
29 ssp2: ssp@80014000 { 29 ssp2: spi@80014000 {
30 compatible = "fsl,imx28-mmc"; 30 compatible = "fsl,imx28-mmc";
31 pinctrl-names = "default"; 31 pinctrl-names = "default";
32 pinctrl-0 = <&mmc2_4bit_pins_apx4 &mmc2_sck_cfg_apx4>; 32 pinctrl-0 = <&mmc2_4bit_pins_apx4 &mmc2_sck_cfg_apx4>;
diff --git a/arch/arm/boot/dts/imx28-cfa10036.dts b/arch/arm/boot/dts/imx28-cfa10036.dts
index e54f5aba7091..8337ca21e281 100644
--- a/arch/arm/boot/dts/imx28-cfa10036.dts
+++ b/arch/arm/boot/dts/imx28-cfa10036.dts
@@ -66,7 +66,7 @@
66 66
67 }; 67 };
68 68
69 ssp0: ssp@80010000 { 69 ssp0: spi@80010000 {
70 compatible = "fsl,imx28-mmc"; 70 compatible = "fsl,imx28-mmc";
71 pinctrl-names = "default"; 71 pinctrl-names = "default";
72 pinctrl-0 = <&mmc0_4bit_pins_a 72 pinctrl-0 = <&mmc0_4bit_pins_a
diff --git a/arch/arm/boot/dts/imx28-duckbill-2-485.dts b/arch/arm/boot/dts/imx28-duckbill-2-485.dts
index 97084e463d7c..f4f2b3d16c8e 100644
--- a/arch/arm/boot/dts/imx28-duckbill-2-485.dts
+++ b/arch/arm/boot/dts/imx28-duckbill-2-485.dts
@@ -25,7 +25,7 @@
25 25
26 apb@80000000 { 26 apb@80000000 {
27 apbh@80000000 { 27 apbh@80000000 {
28 ssp0: ssp@80010000 { 28 ssp0: spi@80010000 {
29 compatible = "fsl,imx28-mmc"; 29 compatible = "fsl,imx28-mmc";
30 pinctrl-names = "default"; 30 pinctrl-names = "default";
31 pinctrl-0 = <&mmc0_8bit_pins_a 31 pinctrl-0 = <&mmc0_8bit_pins_a
@@ -36,7 +36,7 @@
36 non-removable; 36 non-removable;
37 }; 37 };
38 38
39 ssp2: ssp@80014000 { 39 ssp2: spi@80014000 {
40 compatible = "fsl,imx28-mmc"; 40 compatible = "fsl,imx28-mmc";
41 pinctrl-names = "default"; 41 pinctrl-names = "default";
42 pinctrl-0 = <&mmc2_4bit_pins_b 42 pinctrl-0 = <&mmc2_4bit_pins_b
diff --git a/arch/arm/boot/dts/imx28-duckbill-2-enocean.dts b/arch/arm/boot/dts/imx28-duckbill-2-enocean.dts
index 22215337f72a..71d0fcbc2d8c 100644
--- a/arch/arm/boot/dts/imx28-duckbill-2-enocean.dts
+++ b/arch/arm/boot/dts/imx28-duckbill-2-enocean.dts
@@ -26,7 +26,7 @@
26 26
27 apb@80000000 { 27 apb@80000000 {
28 apbh@80000000 { 28 apbh@80000000 {
29 ssp0: ssp@80010000 { 29 ssp0: spi@80010000 {
30 compatible = "fsl,imx28-mmc"; 30 compatible = "fsl,imx28-mmc";
31 pinctrl-names = "default"; 31 pinctrl-names = "default";
32 pinctrl-0 = <&mmc0_8bit_pins_a 32 pinctrl-0 = <&mmc0_8bit_pins_a
@@ -37,7 +37,7 @@
37 non-removable; 37 non-removable;
38 }; 38 };
39 39
40 ssp2: ssp@80014000 { 40 ssp2: spi@80014000 {
41 compatible = "fsl,imx28-mmc"; 41 compatible = "fsl,imx28-mmc";
42 pinctrl-names = "default"; 42 pinctrl-names = "default";
43 pinctrl-0 = <&mmc2_4bit_pins_b 43 pinctrl-0 = <&mmc2_4bit_pins_b
diff --git a/arch/arm/boot/dts/imx28-duckbill-2-spi.dts b/arch/arm/boot/dts/imx28-duckbill-2-spi.dts
index 13e7b134da9e..6580ec6e26ba 100644
--- a/arch/arm/boot/dts/imx28-duckbill-2-spi.dts
+++ b/arch/arm/boot/dts/imx28-duckbill-2-spi.dts
@@ -29,7 +29,7 @@
29 29
30 apb@80000000 { 30 apb@80000000 {
31 apbh@80000000 { 31 apbh@80000000 {
32 ssp0: ssp@80010000 { 32 ssp0: spi@80010000 {
33 compatible = "fsl,imx28-mmc"; 33 compatible = "fsl,imx28-mmc";
34 pinctrl-names = "default"; 34 pinctrl-names = "default";
35 pinctrl-0 = <&mmc0_8bit_pins_a 35 pinctrl-0 = <&mmc0_8bit_pins_a
@@ -40,7 +40,7 @@
40 non-removable; 40 non-removable;
41 }; 41 };
42 42
43 ssp2: ssp@80014000 { 43 ssp2: spi@80014000 {
44 compatible = "fsl,imx28-spi"; 44 compatible = "fsl,imx28-spi";
45 pinctrl-names = "default"; 45 pinctrl-names = "default";
46 pinctrl-0 = <&spi2_pins_a>; 46 pinctrl-0 = <&spi2_pins_a>;
diff --git a/arch/arm/boot/dts/imx28-duckbill-2.dts b/arch/arm/boot/dts/imx28-duckbill-2.dts
index 88556c93b00f..693634edae99 100644
--- a/arch/arm/boot/dts/imx28-duckbill-2.dts
+++ b/arch/arm/boot/dts/imx28-duckbill-2.dts
@@ -25,7 +25,7 @@
25 25
26 apb@80000000 { 26 apb@80000000 {
27 apbh@80000000 { 27 apbh@80000000 {
28 ssp0: ssp@80010000 { 28 ssp0: spi@80010000 {
29 compatible = "fsl,imx28-mmc"; 29 compatible = "fsl,imx28-mmc";
30 pinctrl-names = "default"; 30 pinctrl-names = "default";
31 pinctrl-0 = <&mmc0_8bit_pins_a 31 pinctrl-0 = <&mmc0_8bit_pins_a
@@ -36,7 +36,7 @@
36 non-removable; 36 non-removable;
37 }; 37 };
38 38
39 ssp2: ssp@80014000 { 39 ssp2: spi@80014000 {
40 compatible = "fsl,imx28-mmc"; 40 compatible = "fsl,imx28-mmc";
41 pinctrl-names = "default"; 41 pinctrl-names = "default";
42 pinctrl-0 = <&mmc2_4bit_pins_b 42 pinctrl-0 = <&mmc2_4bit_pins_b
diff --git a/arch/arm/boot/dts/imx28-duckbill.dts b/arch/arm/boot/dts/imx28-duckbill.dts
index f286bfe699be..16f524428ed7 100644
--- a/arch/arm/boot/dts/imx28-duckbill.dts
+++ b/arch/arm/boot/dts/imx28-duckbill.dts
@@ -24,7 +24,7 @@
24 24
25 apb@80000000 { 25 apb@80000000 {
26 apbh@80000000 { 26 apbh@80000000 {
27 ssp0: ssp@80010000 { 27 ssp0: spi@80010000 {
28 compatible = "fsl,imx28-mmc"; 28 compatible = "fsl,imx28-mmc";
29 pinctrl-names = "default"; 29 pinctrl-names = "default";
30 pinctrl-0 = <&mmc0_4bit_pins_a 30 pinctrl-0 = <&mmc0_4bit_pins_a
@@ -34,7 +34,7 @@
34 status = "okay"; 34 status = "okay";
35 }; 35 };
36 36
37 ssp2: ssp@80014000 { 37 ssp2: spi@80014000 {
38 compatible = "fsl,imx28-spi"; 38 compatible = "fsl,imx28-spi";
39 pinctrl-names = "default"; 39 pinctrl-names = "default";
40 pinctrl-0 = <&spi2_pins_a>; 40 pinctrl-0 = <&spi2_pins_a>;
diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts
index 93ab5bdfe068..5778300f44e8 100644
--- a/arch/arm/boot/dts/imx28-evk.dts
+++ b/arch/arm/boot/dts/imx28-evk.dts
@@ -103,7 +103,7 @@
103 status = "okay"; 103 status = "okay";
104 }; 104 };
105 105
106 ssp0: ssp@80010000 { 106 ssp0: spi@80010000 {
107 compatible = "fsl,imx28-mmc"; 107 compatible = "fsl,imx28-mmc";
108 pinctrl-names = "default"; 108 pinctrl-names = "default";
109 pinctrl-0 = <&mmc0_8bit_pins_a 109 pinctrl-0 = <&mmc0_8bit_pins_a
@@ -114,13 +114,13 @@
114 status = "okay"; 114 status = "okay";
115 }; 115 };
116 116
117 ssp1: ssp@80012000 { 117 ssp1: spi@80012000 {
118 compatible = "fsl,imx28-mmc"; 118 compatible = "fsl,imx28-mmc";
119 bus-width = <8>; 119 bus-width = <8>;
120 wp-gpios = <&gpio0 28 0>; 120 wp-gpios = <&gpio0 28 0>;
121 }; 121 };
122 122
123 ssp2: ssp@80014000 { 123 ssp2: spi@80014000 {
124 #address-cells = <1>; 124 #address-cells = <1>;
125 #size-cells = <0>; 125 #size-cells = <0>;
126 compatible = "fsl,imx28-spi"; 126 compatible = "fsl,imx28-spi";
diff --git a/arch/arm/boot/dts/imx28-m28cu3.dts b/arch/arm/boot/dts/imx28-m28cu3.dts
index 3bb5ffc644d6..8883d36a51b5 100644
--- a/arch/arm/boot/dts/imx28-m28cu3.dts
+++ b/arch/arm/boot/dts/imx28-m28cu3.dts
@@ -41,7 +41,7 @@
41 }; 41 };
42 }; 42 };
43 43
44 ssp0: ssp@80010000 { 44 ssp0: spi@80010000 {
45 compatible = "fsl,imx28-mmc"; 45 compatible = "fsl,imx28-mmc";
46 pinctrl-names = "default"; 46 pinctrl-names = "default";
47 pinctrl-0 = <&mmc0_4bit_pins_a 47 pinctrl-0 = <&mmc0_4bit_pins_a
@@ -52,7 +52,7 @@
52 status = "okay"; 52 status = "okay";
53 }; 53 };
54 54
55 ssp2: ssp@80014000 { 55 ssp2: spi@80014000 {
56 compatible = "fsl,imx28-mmc"; 56 compatible = "fsl,imx28-mmc";
57 pinctrl-names = "default"; 57 pinctrl-names = "default";
58 pinctrl-0 = <&mmc2_4bit_pins_a 58 pinctrl-0 = <&mmc2_4bit_pins_a
diff --git a/arch/arm/boot/dts/imx28-m28evk.dts b/arch/arm/boot/dts/imx28-m28evk.dts
index 7d97a0ce74a3..893886d17b2d 100644
--- a/arch/arm/boot/dts/imx28-m28evk.dts
+++ b/arch/arm/boot/dts/imx28-m28evk.dts
@@ -18,7 +18,7 @@
18 18
19 apb@80000000 { 19 apb@80000000 {
20 apbh@80000000 { 20 apbh@80000000 {
21 ssp0: ssp@80010000 { 21 ssp0: spi@80010000 {
22 compatible = "fsl,imx28-mmc"; 22 compatible = "fsl,imx28-mmc";
23 pinctrl-names = "default"; 23 pinctrl-names = "default";
24 pinctrl-0 = <&mmc0_8bit_pins_a 24 pinctrl-0 = <&mmc0_8bit_pins_a
@@ -30,7 +30,7 @@
30 status = "okay"; 30 status = "okay";
31 }; 31 };
32 32
33 ssp2: ssp@80014000 { 33 ssp2: spi@80014000 {
34 #address-cells = <1>; 34 #address-cells = <1>;
35 #size-cells = <0>; 35 #size-cells = <0>;
36 compatible = "fsl,imx28-spi"; 36 compatible = "fsl,imx28-spi";
diff --git a/arch/arm/boot/dts/imx28-sps1.dts b/arch/arm/boot/dts/imx28-sps1.dts
index 2393e83979e0..ea9212f6ecda 100644
--- a/arch/arm/boot/dts/imx28-sps1.dts
+++ b/arch/arm/boot/dts/imx28-sps1.dts
@@ -40,7 +40,7 @@
40 40
41 }; 41 };
42 42
43 ssp0: ssp@80010000 { 43 ssp0: spi@80010000 {
44 compatible = "fsl,imx28-mmc"; 44 compatible = "fsl,imx28-mmc";
45 pinctrl-names = "default"; 45 pinctrl-names = "default";
46 pinctrl-0 = <&mmc0_4bit_pins_a>; 46 pinctrl-0 = <&mmc0_4bit_pins_a>;
@@ -48,7 +48,7 @@
48 status = "okay"; 48 status = "okay";
49 }; 49 };
50 50
51 ssp2: ssp@80014000 { 51 ssp2: spi@80014000 {
52 #address-cells = <1>; 52 #address-cells = <1>;
53 #size-cells = <0>; 53 #size-cells = <0>;
54 compatible = "fsl,imx28-spi"; 54 compatible = "fsl,imx28-spi";
diff --git a/arch/arm/boot/dts/imx28-ts4600.dts b/arch/arm/boot/dts/imx28-ts4600.dts
index f8a09a8c2c36..dccdd6bcd0b2 100644
--- a/arch/arm/boot/dts/imx28-ts4600.dts
+++ b/arch/arm/boot/dts/imx28-ts4600.dts
@@ -25,7 +25,7 @@
25 25
26 apb@80000000 { 26 apb@80000000 {
27 apbh@80000000 { 27 apbh@80000000 {
28 ssp0: ssp@80010000 { 28 ssp0: spi@80010000 {
29 compatible = "fsl,imx28-mmc"; 29 compatible = "fsl,imx28-mmc";
30 pinctrl-names = "default"; 30 pinctrl-names = "default";
31 pinctrl-0 = <&mmc0_4bit_pins_a 31 pinctrl-0 = <&mmc0_4bit_pins_a
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index 5107fdc482ea..2b7efb659fc0 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -117,7 +117,7 @@
117 status = "disabled"; 117 status = "disabled";
118 }; 118 };
119 119
120 ssp0: ssp@80010000 { 120 ssp0: spi@80010000 {
121 #address-cells = <1>; 121 #address-cells = <1>;
122 #size-cells = <0>; 122 #size-cells = <0>;
123 reg = <0x80010000 0x2000>; 123 reg = <0x80010000 0x2000>;
@@ -128,7 +128,7 @@
128 status = "disabled"; 128 status = "disabled";
129 }; 129 };
130 130
131 ssp1: ssp@80012000 { 131 ssp1: spi@80012000 {
132 #address-cells = <1>; 132 #address-cells = <1>;
133 #size-cells = <0>; 133 #size-cells = <0>;
134 reg = <0x80012000 0x2000>; 134 reg = <0x80012000 0x2000>;
@@ -139,7 +139,7 @@
139 status = "disabled"; 139 status = "disabled";
140 }; 140 };
141 141
142 ssp2: ssp@80014000 { 142 ssp2: spi@80014000 {
143 #address-cells = <1>; 143 #address-cells = <1>;
144 #size-cells = <0>; 144 #size-cells = <0>;
145 reg = <0x80014000 0x2000>; 145 reg = <0x80014000 0x2000>;
@@ -150,7 +150,7 @@
150 status = "disabled"; 150 status = "disabled";
151 }; 151 };
152 152
153 ssp3: ssp@80016000 { 153 ssp3: spi@80016000 {
154 #address-cells = <1>; 154 #address-cells = <1>;
155 #size-cells = <0>; 155 #size-cells = <0>;
156 reg = <0x80016000 0x2000>; 156 reg = <0x80016000 0x2000>;
diff --git a/arch/arm/boot/dts/imx31.dtsi b/arch/arm/boot/dts/imx31.dtsi
index ca1419ca303c..af7afccf5f2f 100644
--- a/arch/arm/boot/dts/imx31.dtsi
+++ b/arch/arm/boot/dts/imx31.dtsi
@@ -206,7 +206,7 @@
206 status = "disabled"; 206 status = "disabled";
207 }; 207 };
208 208
209 spi2: cspi@50010000 { 209 spi2: spi@50010000 {
210 compatible = "fsl,imx31-cspi"; 210 compatible = "fsl,imx31-cspi";
211 reg = <0x50010000 0x4000>; 211 reg = <0x50010000 0x4000>;
212 interrupts = <13>; 212 interrupts = <13>;
@@ -241,7 +241,7 @@
241 #clock-cells = <1>; 241 #clock-cells = <1>;
242 }; 242 };
243 243
244 spi3: cspi@53f84000 { 244 spi3: spi@53f84000 {
245 compatible = "fsl,imx31-cspi"; 245 compatible = "fsl,imx31-cspi";
246 reg = <0x53f84000 0x4000>; 246 reg = <0x53f84000 0x4000>;
247 interrupts = <17>; 247 interrupts = <17>;
diff --git a/arch/arm/boot/dts/imx35.dtsi b/arch/arm/boot/dts/imx35.dtsi
index 1c50b785cad4..a1c3d28e8771 100644
--- a/arch/arm/boot/dts/imx35.dtsi
+++ b/arch/arm/boot/dts/imx35.dtsi
@@ -133,7 +133,7 @@
133 status = "disabled"; 133 status = "disabled";
134 }; 134 };
135 135
136 spi1: cspi@43fa4000 { 136 spi1: spi@43fa4000 {
137 #address-cells = <1>; 137 #address-cells = <1>;
138 #size-cells = <0>; 138 #size-cells = <0>;
139 compatible = "fsl,imx35-cspi"; 139 compatible = "fsl,imx35-cspi";
@@ -174,7 +174,7 @@
174 status = "disabled"; 174 status = "disabled";
175 }; 175 };
176 176
177 spi2: cspi@50010000 { 177 spi2: spi@50010000 {
178 #address-cells = <1>; 178 #address-cells = <1>;
179 #size-cells = <0>; 179 #size-cells = <0>;
180 compatible = "fsl,imx35-cspi"; 180 compatible = "fsl,imx35-cspi";
diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi
index 7fae2ffb76fe..95b7fba58300 100644
--- a/arch/arm/boot/dts/imx50.dtsi
+++ b/arch/arm/boot/dts/imx50.dtsi
@@ -140,7 +140,7 @@
140 status = "disabled"; 140 status = "disabled";
141 }; 141 };
142 142
143 ecspi1: ecspi@50010000 { 143 ecspi1: spi@50010000 {
144 #address-cells = <1>; 144 #address-cells = <1>;
145 #size-cells = <0>; 145 #size-cells = <0>;
146 compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi"; 146 compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi";
@@ -403,7 +403,7 @@
403 status = "disabled"; 403 status = "disabled";
404 }; 404 };
405 405
406 ecspi2: ecspi@63fac000 { 406 ecspi2: spi@63fac000 {
407 #address-cells = <1>; 407 #address-cells = <1>;
408 #size-cells = <0>; 408 #size-cells = <0>;
409 compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi"; 409 compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi";
@@ -426,7 +426,7 @@
426 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx50.bin"; 426 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx50.bin";
427 }; 427 };
428 428
429 cspi: cspi@63fc0000 { 429 cspi: spi@63fc0000 {
430 #address-cells = <1>; 430 #address-cells = <1>;
431 #size-cells = <0>; 431 #size-cells = <0>;
432 compatible = "fsl,imx50-cspi", "fsl,imx35-cspi"; 432 compatible = "fsl,imx50-cspi", "fsl,imx35-cspi";
diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts
index ba60b0cb3cc1..35ee1b4247c3 100644
--- a/arch/arm/boot/dts/imx51-babbage.dts
+++ b/arch/arm/boot/dts/imx51-babbage.dts
@@ -204,6 +204,7 @@
204 reg = <0>; 204 reg = <0>;
205 interrupt-parent = <&gpio1>; 205 interrupt-parent = <&gpio1>;
206 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; 206 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
207 fsl,mc13xxx-uses-adc;
207 fsl,mc13xxx-uses-rtc; 208 fsl,mc13xxx-uses-rtc;
208 209
209 regulators { 210 regulators {
diff --git a/arch/arm/boot/dts/imx51-zii-rdu1.dts b/arch/arm/boot/dts/imx51-zii-rdu1.dts
index 469cce2c0357..e45a15ceb94b 100644
--- a/arch/arm/boot/dts/imx51-zii-rdu1.dts
+++ b/arch/arm/boot/dts/imx51-zii-rdu1.dts
@@ -508,7 +508,7 @@
508 }; 508 };
509 509
510 ds1341: rtc@68 { 510 ds1341: rtc@68 {
511 compatible = "maxim,ds1341"; 511 compatible = "dallas,ds1341";
512 reg = <0x68>; 512 reg = <0x68>;
513 }; 513 };
514 514
diff --git a/arch/arm/boot/dts/imx51-zii-scu2-mezz.dts b/arch/arm/boot/dts/imx51-zii-scu2-mezz.dts
index 26cf08549df4..243d1c8cab0a 100644
--- a/arch/arm/boot/dts/imx51-zii-scu2-mezz.dts
+++ b/arch/arm/boot/dts/imx51-zii-scu2-mezz.dts
@@ -342,6 +342,14 @@
342 vcc-supply = <&vusb2_reg>; 342 vcc-supply = <&vusb2_reg>;
343}; 343};
344 344
345&vpu {
346 status = "disabled";
347};
348
349&wdog1 {
350 status = "disabled";
351};
352
345&iomuxc { 353&iomuxc {
346 pinctrl_ecspi1: ecspi1grp { 354 pinctrl_ecspi1: ecspi1grp {
347 fsl,pins = < 355 fsl,pins = <
diff --git a/arch/arm/boot/dts/imx51-zii-scu3-esb.dts b/arch/arm/boot/dts/imx51-zii-scu3-esb.dts
index e6ebac8f43e4..14b207778114 100644
--- a/arch/arm/boot/dts/imx51-zii-scu3-esb.dts
+++ b/arch/arm/boot/dts/imx51-zii-scu3-esb.dts
@@ -350,6 +350,10 @@
350 vcc-supply = <&vusb2_reg>; 350 vcc-supply = <&vusb2_reg>;
351}; 351};
352 352
353&vpu {
354 status = "disabled";
355};
356
353&wdog1 { 357&wdog1 {
354 status = "disabled"; 358 status = "disabled";
355}; 359};
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index 5c4ba91e43ba..67d462715048 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -197,7 +197,7 @@
197 status = "disabled"; 197 status = "disabled";
198 }; 198 };
199 199
200 ecspi1: ecspi@70010000 { 200 ecspi1: spi@70010000 {
201 #address-cells = <1>; 201 #address-cells = <1>;
202 #size-cells = <0>; 202 #size-cells = <0>;
203 compatible = "fsl,imx51-ecspi"; 203 compatible = "fsl,imx51-ecspi";
@@ -464,7 +464,7 @@
464 status = "disabled"; 464 status = "disabled";
465 }; 465 };
466 466
467 ecspi2: ecspi@83fac000 { 467 ecspi2: spi@83fac000 {
468 #address-cells = <1>; 468 #address-cells = <1>;
469 #size-cells = <0>; 469 #size-cells = <0>;
470 compatible = "fsl,imx51-ecspi"; 470 compatible = "fsl,imx51-ecspi";
@@ -487,7 +487,7 @@
487 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin"; 487 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
488 }; 488 };
489 489
490 cspi: cspi@83fc0000 { 490 cspi: spi@83fc0000 {
491 #address-cells = <1>; 491 #address-cells = <1>;
492 #size-cells = <0>; 492 #size-cells = <0>;
493 compatible = "fsl,imx51-cspi", "fsl,imx35-cspi"; 493 compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
@@ -608,7 +608,7 @@
608 status = "disabled"; 608 status = "disabled";
609 }; 609 };
610 610
611 vpu@83ff4000 { 611 vpu: vpu@83ff4000 {
612 compatible = "fsl,imx51-vpu", "cnm,codahx4"; 612 compatible = "fsl,imx51-vpu", "cnm,codahx4";
613 reg = <0x83ff4000 0x1000>; 613 reg = <0x83ff4000 0x1000>;
614 interrupts = <9>; 614 interrupts = <9>;
diff --git a/arch/arm/boot/dts/imx53-ppd.dts b/arch/arm/boot/dts/imx53-ppd.dts
index cdb90bee7b4a..b560ff88459b 100644
--- a/arch/arm/boot/dts/imx53-ppd.dts
+++ b/arch/arm/boot/dts/imx53-ppd.dts
@@ -319,7 +319,6 @@
319&ecspi2 { 319&ecspi2 {
320 pinctrl-names = "default"; 320 pinctrl-names = "default";
321 pinctrl-0 = <&pinctrl_ecspi2>; 321 pinctrl-0 = <&pinctrl_ecspi2>;
322 num-chipselects = <1>;
323 cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>; 322 cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>;
324 status = "okay"; 323 status = "okay";
325 324
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index 6386185ae234..207eb557c90e 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -259,7 +259,7 @@
259 status = "disabled"; 259 status = "disabled";
260 }; 260 };
261 261
262 ecspi1: ecspi@50010000 { 262 ecspi1: spi@50010000 {
263 #address-cells = <1>; 263 #address-cells = <1>;
264 #size-cells = <0>; 264 #size-cells = <0>;
265 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; 265 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
@@ -684,7 +684,7 @@
684 status = "disabled"; 684 status = "disabled";
685 }; 685 };
686 686
687 ecspi2: ecspi@63fac000 { 687 ecspi2: spi@63fac000 {
688 #address-cells = <1>; 688 #address-cells = <1>;
689 #size-cells = <0>; 689 #size-cells = <0>;
690 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; 690 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
@@ -707,7 +707,7 @@
707 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; 707 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
708 }; 708 };
709 709
710 cspi: cspi@63fc0000 { 710 cspi: spi@63fc0000 {
711 #address-cells = <1>; 711 #address-cells = <1>;
712 #size-cells = <0>; 712 #size-cells = <0>;
713 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi"; 713 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
diff --git a/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts
index 9de45a717356..d08e0402793b 100644
--- a/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts
+++ b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts
@@ -146,7 +146,7 @@
146&ecspi4 { 146&ecspi4 {
147 status = "okay"; 147 status = "okay";
148 148
149 mcp251x0: mcp251x@1 { 149 mcp251x0: mcp251x@0 {
150 compatible = "microchip,mcp2515"; 150 compatible = "microchip,mcp2515";
151 reg = <0>; 151 reg = <0>;
152 clocks = <&clk16m>; 152 clocks = <&clk16m>;
diff --git a/arch/arm/boot/dts/imx6dl-icore-mipi.dts b/arch/arm/boot/dts/imx6dl-icore-mipi.dts
index bf53f0552aa1..e43bccb78ab2 100644
--- a/arch/arm/boot/dts/imx6dl-icore-mipi.dts
+++ b/arch/arm/boot/dts/imx6dl-icore-mipi.dts
@@ -1,4 +1,4 @@
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1// SPDX-License-Identifier: GPL-2.0 OR X11
2/* 2/*
3 * Copyright (C) 2018 Engicam S.r.l. 3 * Copyright (C) 2018 Engicam S.r.l.
4 * Copyright (C) 2018 Amarula Solutions B.V. 4 * Copyright (C) 2018 Amarula Solutions B.V.
diff --git a/arch/arm/boot/dts/imx6dl-icore-rqs.dts b/arch/arm/boot/dts/imx6dl-icore-rqs.dts
index 1281bc39b7ab..73d710d34b9d 100644
--- a/arch/arm/boot/dts/imx6dl-icore-rqs.dts
+++ b/arch/arm/boot/dts/imx6dl-icore-rqs.dts
@@ -1,43 +1,7 @@
1// SPDX-License-Identifier: GPL-2.0 OR X11
1/* 2/*
2 * Copyright (C) 2016 Amarula Solutions B.V. 3 * Copyright (C) 2016 Amarula Solutions B.V.
3 * Copyright (C) 2016 Engicam S.r.l. 4 * Copyright (C) 2016 Engicam S.r.l.
4 *
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
8 * whole.
9 *
10 * a) This file is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * version 2 as published by the Free Software Foundation.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */ 5 */
42 6
43/dts-v1/; 7/dts-v1/;
diff --git a/arch/arm/boot/dts/imx6dl-icore.dts b/arch/arm/boot/dts/imx6dl-icore.dts
index 971f9fc39c66..80fa60607ab1 100644
--- a/arch/arm/boot/dts/imx6dl-icore.dts
+++ b/arch/arm/boot/dts/imx6dl-icore.dts
@@ -1,43 +1,7 @@
1// SPDX-License-Identifier: GPL-2.0 OR X11
1/* 2/*
2 * Copyright (C) 2016 Amarula Solutions B.V. 3 * Copyright (C) 2016 Amarula Solutions B.V.
3 * Copyright (C) 2016 Engicam S.r.l. 4 * Copyright (C) 2016 Engicam S.r.l.
4 *
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
8 * whole.
9 *
10 * a) This file is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * version 2 as published by the Free Software Foundation.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */ 5 */
42 6
43/dts-v1/; 7/dts-v1/;
diff --git a/arch/arm/boot/dts/imx6dl-riotboard.dts b/arch/arm/boot/dts/imx6dl-riotboard.dts
index dd3226fe5ecd..8e51491e68cf 100644
--- a/arch/arm/boot/dts/imx6dl-riotboard.dts
+++ b/arch/arm/boot/dts/imx6dl-riotboard.dts
@@ -84,6 +84,10 @@
84 status = "okay"; 84 status = "okay";
85}; 85};
86 86
87&clks {
88 fsl,pmic-stby-poweroff;
89};
90
87&fec { 91&fec {
88 pinctrl-names = "default"; 92 pinctrl-names = "default";
89 pinctrl-0 = <&pinctrl_enet>; 93 pinctrl-0 = <&pinctrl_enet>;
@@ -164,6 +168,7 @@
164 reg = <0x08>; 168 reg = <0x08>;
165 interrupt-parent = <&gpio5>; 169 interrupt-parent = <&gpio5>;
166 interrupts = <16 8>; 170 interrupts = <16 8>;
171 fsl,pmic-stby-poweroff;
167 172
168 regulators { 173 regulators {
169 reg_vddcore: sw1ab { /* VDDARM_IN */ 174 reg_vddcore: sw1ab { /* VDDARM_IN */
diff --git a/arch/arm/boot/dts/imx6q-apalis-eval.dts b/arch/arm/boot/dts/imx6q-apalis-eval.dts
index 707ac9a46115..0edd3043d9c1 100644
--- a/arch/arm/boot/dts/imx6q-apalis-eval.dts
+++ b/arch/arm/boot/dts/imx6q-apalis-eval.dts
@@ -196,6 +196,8 @@
196}; 196};
197 197
198&pcie { 198&pcie {
199 pinctrl-names = "default";
200 pinctrl-0 = <&pinctrl_reset_moci>;
199 /* active-high meaning opposite of regular PERST# active-low polarity */ 201 /* active-high meaning opposite of regular PERST# active-low polarity */
200 reset-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>; 202 reset-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;
201 reset-gpio-active-high; 203 reset-gpio-active-high;
diff --git a/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts b/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts
index 4e1c8feaef82..b94bb687be6b 100644
--- a/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts
+++ b/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts
@@ -196,6 +196,8 @@
196}; 196};
197 197
198&pcie { 198&pcie {
199 pinctrl-names = "default";
200 pinctrl-0 = <&pinctrl_reset_moci>;
199 /* active-high meaning opposite of regular PERST# active-low polarity */ 201 /* active-high meaning opposite of regular PERST# active-low polarity */
200 reset-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>; 202 reset-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;
201 reset-gpio-active-high; 203 reset-gpio-active-high;
diff --git a/arch/arm/boot/dts/imx6q-apalis-ixora.dts b/arch/arm/boot/dts/imx6q-apalis-ixora.dts
index 469e3d0e2827..302fd6adc8a7 100644
--- a/arch/arm/boot/dts/imx6q-apalis-ixora.dts
+++ b/arch/arm/boot/dts/imx6q-apalis-ixora.dts
@@ -200,6 +200,8 @@
200}; 200};
201 201
202&pcie { 202&pcie {
203 pinctrl-names = "default";
204 pinctrl-0 = <&pinctrl_reset_moci>;
203 /* active-high meaning opposite of regular PERST# active-low polarity */ 205 /* active-high meaning opposite of regular PERST# active-low polarity */
204 reset-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>; 206 reset-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;
205 reset-gpio-active-high; 207 reset-gpio-active-high;
diff --git a/arch/arm/boot/dts/imx6q-icore-mipi.dts b/arch/arm/boot/dts/imx6q-icore-mipi.dts
index 95b2efda17b4..d51745268dbf 100644
--- a/arch/arm/boot/dts/imx6q-icore-mipi.dts
+++ b/arch/arm/boot/dts/imx6q-icore-mipi.dts
@@ -1,4 +1,4 @@
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1// SPDX-License-Identifier: GPL-2.0 OR X11
2/* 2/*
3 * Copyright (C) 2017 Engicam S.r.l. 3 * Copyright (C) 2017 Engicam S.r.l.
4 * Copyright (C) 2017 Amarula Solutions B.V. 4 * Copyright (C) 2017 Amarula Solutions B.V.
@@ -8,10 +8,10 @@
8/dts-v1/; 8/dts-v1/;
9 9
10#include "imx6q.dtsi" 10#include "imx6q.dtsi"
11#include "imx6qdl-icore.dtsi" 11#include "imx6qdl-icore-1.5.dtsi"
12 12
13/ { 13/ {
14 model = "Engicam i.CoreM6 Quad/Dual MIPI Starter Kit"; 14 model = "Engicam i.CoreM6 1.5 Quad/Dual MIPI Starter Kit";
15 compatible = "engicam,imx6-icore", "fsl,imx6q"; 15 compatible = "engicam,imx6-icore", "fsl,imx6q";
16}; 16};
17 17
diff --git a/arch/arm/boot/dts/imx6q-icore-ofcap10.dts b/arch/arm/boot/dts/imx6q-icore-ofcap10.dts
index 49b60ca20e6d..81cc346dd149 100644
--- a/arch/arm/boot/dts/imx6q-icore-ofcap10.dts
+++ b/arch/arm/boot/dts/imx6q-icore-ofcap10.dts
@@ -1,43 +1,7 @@
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
1/* 2/*
2 * Copyright (C) 2016 Amarula Solutions B.V. 3 * Copyright (C) 2016 Amarula Solutions B.V.
3 * Copyright (C) 2016 Engicam S.r.l. 4 * Copyright (C) 2016 Engicam S.r.l.
4 *
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
8 * whole.
9 *
10 * a) This file is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * version 2 as published by the Free Software Foundation.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */ 5 */
42 6
43/dts-v1/; 7/dts-v1/;
diff --git a/arch/arm/boot/dts/imx6q-icore-ofcap12.dts b/arch/arm/boot/dts/imx6q-icore-ofcap12.dts
index 6e27c8143f82..241811c52b62 100644
--- a/arch/arm/boot/dts/imx6q-icore-ofcap12.dts
+++ b/arch/arm/boot/dts/imx6q-icore-ofcap12.dts
@@ -1,43 +1,7 @@
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
1/* 2/*
2 * Copyright (C) 2016 Amarula Solutions B.V. 3 * Copyright (C) 2016 Amarula Solutions B.V.
3 * Copyright (C) 2016 Engicam S.r.l. 4 * Copyright (C) 2016 Engicam S.r.l.
4 *
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
8 * whole.
9 *
10 * a) This file is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * version 2 as published by the Free Software Foundation.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */ 5 */
42 6
43/dts-v1/; 7/dts-v1/;
diff --git a/arch/arm/boot/dts/imx6q-icore-rqs.dts b/arch/arm/boot/dts/imx6q-icore-rqs.dts
index b81f48c6a8c6..cf6ba724f497 100644
--- a/arch/arm/boot/dts/imx6q-icore-rqs.dts
+++ b/arch/arm/boot/dts/imx6q-icore-rqs.dts
@@ -1,42 +1,7 @@
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
1/* 2/*
2 * Copyright (C) 2015 Amarula Solutions B.V. 3 * Copyright (C) 2015 Amarula Solutions B.V.
3 * 4 * Copyright (C) 2015 Engicam S.r.l.
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * Or, alternatively,
19 *
20 * b) Permission is hereby granted, free of charge, to any person
21 * obtaining a copy of this software and associated documentation
22 * files (the "Software"), to deal in the Software without
23 * restriction, including without limitation the rights to use,
24 * copy, modify, merge, publish, distribute, sublicense, and/or
25 * sell copies of the Software, and to permit persons to whom the
26 * Software is furnished to do so, subject to the following
27 * conditions:
28 *
29 * The above copyright notice and this permission notice shall be
30 * included in all copies or substantial portions of the Software.
31 *
32 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
33 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
34 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
35 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
36 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
37 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
38 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
39 * OTHER DEALINGS IN THE SOFTWARE.
40 */ 5 */
41 6
42/dts-v1/; 7/dts-v1/;
diff --git a/arch/arm/boot/dts/imx6q-icore.dts b/arch/arm/boot/dts/imx6q-icore.dts
index 5613dd9dc469..fe28c3cf54c0 100644
--- a/arch/arm/boot/dts/imx6q-icore.dts
+++ b/arch/arm/boot/dts/imx6q-icore.dts
@@ -1,43 +1,7 @@
1// SPDX-License-Identifier: GPL-2.0 OR X11
1/* 2/*
2 * Copyright (C) 2016 Amarula Solutions B.V. 3 * Copyright (C) 2016 Amarula Solutions B.V.
3 * Copyright (C) 2016 Engicam S.r.l. 4 * Copyright (C) 2016 Engicam S.r.l.
4 *
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
8 * whole.
9 *
10 * a) This file is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * version 2 as published by the Free Software Foundation.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */ 5 */
42 6
43/dts-v1/; 7/dts-v1/;
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 0193ee6fe964..8381d24eff7d 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -163,7 +163,7 @@
163 163
164 aips-bus@2000000 { /* AIPS1 */ 164 aips-bus@2000000 { /* AIPS1 */
165 spba-bus@2000000 { 165 spba-bus@2000000 {
166 ecspi5: ecspi@2018000 { 166 ecspi5: spi@2018000 {
167 #address-cells = <1>; 167 #address-cells = <1>;
168 #size-cells = <0>; 168 #size-cells = <0>;
169 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; 169 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
diff --git a/arch/arm/boot/dts/imx6qdl-apalis.dtsi b/arch/arm/boot/dts/imx6qdl-apalis.dtsi
index 05f07ea3e8c8..3dc99dd8dde1 100644
--- a/arch/arm/boot/dts/imx6qdl-apalis.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-apalis.dtsi
@@ -482,10 +482,6 @@
482}; 482};
483 483
484&iomuxc { 484&iomuxc {
485 /* pins used on module */
486 pinctrl-names = "default";
487 pinctrl-0 = <&pinctrl_reset_moci>;
488
489 pinctrl_apalis_gpio1: gpio2io04grp { 485 pinctrl_apalis_gpio1: gpio2io04grp {
490 fsl,pins = < 486 fsl,pins = <
491 MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x130b0 487 MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x130b0
diff --git a/arch/arm/boot/dts/imx6qdl-icore-1.5.dtsi b/arch/arm/boot/dts/imx6qdl-icore-1.5.dtsi
new file mode 100644
index 000000000000..d91d46b5898f
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-icore-1.5.dtsi
@@ -0,0 +1,34 @@
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2018 Jacopo Mondi <jacopo@jmondi.org>
4 */
5
6#include "imx6qdl-icore.dtsi"
7
8&iomuxc {
9 pinctrl_enet: enetgrp {
10 fsl,pins = <
11 MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
12 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0b0
13 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
14 MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
15 MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
16 MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
17 MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
18 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
19 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
20 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0
21 >;
22 };
23};
24
25&fec {
26 pinctrl-names = "default";
27 pinctrl-0 = <&pinctrl_enet>;
28 phy-reset-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
29 clocks = <&clks IMX6QDL_CLK_ENET>,
30 <&clks IMX6QDL_CLK_ENET>,
31 <&clks IMX6QDL_CLK_ENET_REF>;
32 phy-mode = "rmii";
33 status = "okay";
34};
diff --git a/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi b/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi
index acc3b11fba2a..ba93026ecee8 100644
--- a/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi
@@ -1,42 +1,7 @@
1// SPDX-License-Identifier: GPL-2.0 OR X11
1/* 2/*
2 * Copyright (C) 2015 Amarula Solutions B.V. 3 * Copyright (C) 2015 Amarula Solutions B.V.
3 * 4 * Copyright (C) 2015 Engicam S.r.l.
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * Or, alternatively,
19 *
20 * b) Permission is hereby granted, free of charge, to any person
21 * obtaining a copy of this software and associated documentation
22 * files (the "Software"), to deal in the Software without
23 * restriction, including without limitation the rights to use,
24 * copy, modify, merge, publish, distribute, sublicense, and/or
25 * sell copies of the Software, and to permit persons to whom the
26 * Software is furnished to do so, subject to the following
27 * conditions:
28 *
29 * The above copyright notice and this permission notice shall be
30 * included in all copies or substantial portions of the Software.
31 *
32 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
33 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
34 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
35 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
36 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
37 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
38 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
39 * OTHER DEALINGS IN THE SOFTWARE.
40 */ 5 */
41 6
42#include <dt-bindings/gpio/gpio.h> 7#include <dt-bindings/gpio/gpio.h>
@@ -316,7 +281,7 @@
316}; 281};
317 282
318&iomuxc { 283&iomuxc {
319 pinctrl_audmux: audmux { 284 pinctrl_audmux: audmuxgrp {
320 fsl,pins = < 285 fsl,pins = <
321 MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0 286 MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0
322 MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x110b0 287 MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x110b0
diff --git a/arch/arm/boot/dts/imx6qdl-icore.dtsi b/arch/arm/boot/dts/imx6qdl-icore.dtsi
index 9ce993776160..84d03c65f4c8 100644
--- a/arch/arm/boot/dts/imx6qdl-icore.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-icore.dtsi
@@ -1,43 +1,7 @@
1// SPDX-License-Identifier: GPL-2.0 OR X11
1/* 2/*
2 * Copyright (C) 2016 Amarula Solutions B.V. 3 * Copyright (C) 2016 Amarula Solutions B.V.
3 * Copyright (C) 2016 Engicam S.r.l. 4 * Copyright (C) 2016 Engicam S.r.l.
4 *
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
8 * whole.
9 *
10 * a) This file is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * version 2 as published by the Free Software Foundation.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */ 5 */
42 6
43#include <dt-bindings/gpio/gpio.h> 7#include <dt-bindings/gpio/gpio.h>
@@ -310,7 +274,7 @@
310}; 274};
311 275
312&iomuxc { 276&iomuxc {
313 pinctrl_audmux: audmux { 277 pinctrl_audmux: audmuxgrp {
314 fsl,pins = < 278 fsl,pins = <
315 MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0 279 MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0
316 MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x110b0 280 MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x110b0
@@ -349,7 +313,7 @@
349 >; 313 >;
350 }; 314 };
351 315
352 pinctrl_gpmi_nand: gpmi-nand { 316 pinctrl_gpmi_nand: gpminandgrp {
353 fsl,pins = < 317 fsl,pins = <
354 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 318 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
355 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 319 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
index 9f11f1fcc3e6..a6dc5c42c632 100644
--- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
@@ -4,6 +4,7 @@
4// Copyright 2011 Linaro Ltd. 4// Copyright 2011 Linaro Ltd.
5 5
6#include <dt-bindings/gpio/gpio.h> 6#include <dt-bindings/gpio/gpio.h>
7#include <dt-bindings/input/input.h>
7 8
8/ { 9/ {
9 chosen { 10 chosen {
@@ -25,6 +26,47 @@
25 }; 26 };
26 }; 27 };
27 28
29 gpio-keys {
30 compatible = "gpio-keys";
31 pinctrl-names = "default";
32 pinctrl-0 = <&pinctrl_gpio_keys>;
33
34 home {
35 label = "Home";
36 gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
37 linux,code = <KEY_HOME>;
38 wakeup-source;
39 };
40
41 back {
42 label = "Back";
43 gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
44 linux,code = <KEY_BACK>;
45 wakeup-source;
46 };
47
48 program {
49 label = "Program";
50 gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
51 linux,code = <KEY_PROGRAM>;
52 wakeup-source;
53 };
54
55 volume-up {
56 label = "Volume Up";
57 gpios = <&gpio2 15 GPIO_ACTIVE_LOW>;
58 linux,code = <KEY_VOLUMEUP>;
59 wakeup-source;
60 };
61
62 volume-down {
63 label = "Volume Down";
64 gpios = <&gpio5 14 GPIO_ACTIVE_LOW>;
65 linux,code = <KEY_VOLUMEDOWN>;
66 wakeup-source;
67 };
68 };
69
28 clocks { 70 clocks {
29 codec_osc: anaclk2 { 71 codec_osc: anaclk2 {
30 compatible = "fixed-clock"; 72 compatible = "fixed-clock";
@@ -375,6 +417,15 @@
375 VLC-supply = <&reg_audio>; 417 VLC-supply = <&reg_audio>;
376 }; 418 };
377 419
420 touchscreen@4 {
421 compatible = "eeti,egalax_ts";
422 reg = <0x04>;
423 pinctrl-names = "default";
424 pinctrl-0 = <&pinctrl_egalax_int>;
425 interrupt-parent = <&gpio2>;
426 interrupts = <28 IRQ_TYPE_EDGE_FALLING>;
427 wakeup-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>;
428 };
378}; 429};
379 430
380&i2c3 { 431&i2c3 {
@@ -410,6 +461,12 @@
410 >; 461 >;
411 }; 462 };
412 463
464 pinctrl_egalax_int: egalax-intgrp {
465 fsl,pins = <
466 MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0xb0b1
467 >;
468 };
469
413 pinctrl_enet: enetgrp { 470 pinctrl_enet: enetgrp {
414 fsl,pins = < 471 fsl,pins = <
415 MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0 472 MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
@@ -446,6 +503,16 @@
446 >; 503 >;
447 }; 504 };
448 505
506 pinctrl_gpio_keys: gpiokeysgrp {
507 fsl,pins = <
508 MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x1b0b0
509 MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x1b0b0
510 MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x1b0b0
511 MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x1b0b0
512 MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0
513 >;
514 };
515
449 pinctrl_gpio_leds: gpioledsgrp { 516 pinctrl_gpio_leds: gpioledsgrp {
450 fsl,pins = < 517 fsl,pins = <
451 MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x80000000 518 MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x80000000
diff --git a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
index 381bf61fcd28..b7d5fb421404 100644
--- a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
@@ -8,6 +8,10 @@
8#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/gpio/gpio.h>
9 9
10/ { 10/ {
11 chosen {
12 stdout-path = &uart1;
13 };
14
11 sound { 15 sound {
12 compatible = "fsl,imx6-wandboard-sgtl5000", 16 compatible = "fsl,imx6-wandboard-sgtl5000",
13 "fsl,imx-audio-sgtl5000"; 17 "fsl,imx-audio-sgtl5000";
diff --git a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi
index 7fff3717cf7c..85e79a33bcd4 100644
--- a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi
@@ -813,6 +813,10 @@
813 status = "okay"; 813 status = "okay";
814}; 814};
815 815
816&snvs_rtc {
817 status = "disabled";
818};
819
816&ssi1 { 820&ssi1 {
817 status = "okay"; 821 status = "okay";
818}; 822};
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 61d2d26afbf4..e4daf150881a 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -317,7 +317,7 @@
317 status = "disabled"; 317 status = "disabled";
318 }; 318 };
319 319
320 ecspi1: ecspi@2008000 { 320 ecspi1: spi@2008000 {
321 #address-cells = <1>; 321 #address-cells = <1>;
322 #size-cells = <0>; 322 #size-cells = <0>;
323 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; 323 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
@@ -331,7 +331,7 @@
331 status = "disabled"; 331 status = "disabled";
332 }; 332 };
333 333
334 ecspi2: ecspi@200c000 { 334 ecspi2: spi@200c000 {
335 #address-cells = <1>; 335 #address-cells = <1>;
336 #size-cells = <0>; 336 #size-cells = <0>;
337 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; 337 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
@@ -345,7 +345,7 @@
345 status = "disabled"; 345 status = "disabled";
346 }; 346 };
347 347
348 ecspi3: ecspi@2010000 { 348 ecspi3: spi@2010000 {
349 #address-cells = <1>; 349 #address-cells = <1>;
350 #size-cells = <0>; 350 #size-cells = <0>;
351 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; 351 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
@@ -359,7 +359,7 @@
359 status = "disabled"; 359 status = "disabled";
360 }; 360 };
361 361
362 ecspi4: ecspi@2014000 { 362 ecspi4: spi@2014000 {
363 #address-cells = <1>; 363 #address-cells = <1>;
364 #size-cells = <0>; 364 #size-cells = <0>;
365 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; 365 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index 7a4f5dace902..7a3ae7160c12 100644
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -168,7 +168,7 @@
168 status = "disabled"; 168 status = "disabled";
169 }; 169 };
170 170
171 ecspi1: ecspi@2008000 { 171 ecspi1: spi@2008000 {
172 #address-cells = <1>; 172 #address-cells = <1>;
173 #size-cells = <0>; 173 #size-cells = <0>;
174 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi"; 174 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
@@ -180,7 +180,7 @@
180 status = "disabled"; 180 status = "disabled";
181 }; 181 };
182 182
183 ecspi2: ecspi@200c000 { 183 ecspi2: spi@200c000 {
184 #address-cells = <1>; 184 #address-cells = <1>;
185 #size-cells = <0>; 185 #size-cells = <0>;
186 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi"; 186 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
@@ -192,7 +192,7 @@
192 status = "disabled"; 192 status = "disabled";
193 }; 193 };
194 194
195 ecspi3: ecspi@2010000 { 195 ecspi3: spi@2010000 {
196 #address-cells = <1>; 196 #address-cells = <1>;
197 #size-cells = <0>; 197 #size-cells = <0>;
198 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi"; 198 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
@@ -204,7 +204,7 @@
204 status = "disabled"; 204 status = "disabled";
205 }; 205 };
206 206
207 ecspi4: ecspi@2014000 { 207 ecspi4: spi@2014000 {
208 #address-cells = <1>; 208 #address-cells = <1>;
209 #size-cells = <0>; 209 #size-cells = <0>;
210 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi"; 210 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
diff --git a/arch/arm/boot/dts/imx6sll.dtsi b/arch/arm/boot/dts/imx6sll.dtsi
index 000e6136a9d6..ed9a980bce85 100644
--- a/arch/arm/boot/dts/imx6sll.dtsi
+++ b/arch/arm/boot/dts/imx6sll.dtsi
@@ -375,10 +375,12 @@
375 reg = <0x0209c000 0x4000>; 375 reg = <0x0209c000 0x4000>;
376 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 376 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
377 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 377 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
378 clocks = <&clks IMX6SLL_CLK_GPIO1>;
378 gpio-controller; 379 gpio-controller;
379 #gpio-cells = <2>; 380 #gpio-cells = <2>;
380 interrupt-controller; 381 interrupt-controller;
381 #interrupt-cells = <2>; 382 #interrupt-cells = <2>;
383 gpio-ranges = <&iomuxc 0 94 7>, <&iomuxc 7 25 25>;
382 }; 384 };
383 385
384 gpio2: gpio@20a0000 { 386 gpio2: gpio@20a0000 {
@@ -386,10 +388,12 @@
386 reg = <0x020a0000 0x4000>; 388 reg = <0x020a0000 0x4000>;
387 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 389 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
388 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 390 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
391 clocks = <&clks IMX6SLL_CLK_GPIO2>;
389 gpio-controller; 392 gpio-controller;
390 #gpio-cells = <2>; 393 #gpio-cells = <2>;
391 interrupt-controller; 394 interrupt-controller;
392 #interrupt-cells = <2>; 395 #interrupt-cells = <2>;
396 gpio-ranges = <&iomuxc 0 50 32>;
393 }; 397 };
394 398
395 gpio3: gpio@20a4000 { 399 gpio3: gpio@20a4000 {
@@ -397,10 +401,14 @@
397 reg = <0x020a4000 0x4000>; 401 reg = <0x020a4000 0x4000>;
398 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 402 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
399 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 403 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
404 clocks = <&clks IMX6SLL_CLK_GPIO3>;
400 gpio-controller; 405 gpio-controller;
401 #gpio-cells = <2>; 406 #gpio-cells = <2>;
402 interrupt-controller; 407 interrupt-controller;
403 #interrupt-cells = <2>; 408 #interrupt-cells = <2>;
409 gpio-ranges = <&iomuxc 0 82 12>, <&iomuxc 12 103 4>,
410 <&iomuxc 16 101 2>, <&iomuxc 18 5 1>,
411 <&iomuxc 21 6 11>;
404 }; 412 };
405 413
406 gpio4: gpio@20a8000 { 414 gpio4: gpio@20a8000 {
@@ -408,10 +416,20 @@
408 reg = <0x020a8000 0x4000>; 416 reg = <0x020a8000 0x4000>;
409 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 417 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
410 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 418 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
419 clocks = <&clks IMX6SLL_CLK_GPIO4>;
411 gpio-controller; 420 gpio-controller;
412 #gpio-cells = <2>; 421 #gpio-cells = <2>;
413 interrupt-controller; 422 interrupt-controller;
414 #interrupt-cells = <2>; 423 #interrupt-cells = <2>;
424 gpio-ranges = <&iomuxc 0 17 8>, <&iomuxc 8 107 8>,
425 <&iomuxc 16 151 1>, <&iomuxc 17 149 1>,
426 <&iomuxc 18 146 1>, <&iomuxc 19 144 1>,
427 <&iomuxc 20 142 1>, <&iomuxc 21 143 1>,
428 <&iomuxc 22 150 1>, <&iomuxc 23 148 1>,
429 <&iomuxc 24 147 1>, <&iomuxc 25 145 1>,
430 <&iomuxc 26 152 1>, <&iomuxc 27 125 1>,
431 <&iomuxc 28 131 1>, <&iomuxc 29 134 1>,
432 <&iomuxc 30 129 1>, <&iomuxc 31 133 1>;
415 }; 433 };
416 434
417 gpio5: gpio@20ac000 { 435 gpio5: gpio@20ac000 {
@@ -419,10 +437,22 @@
419 reg = <0x020ac000 0x4000>; 437 reg = <0x020ac000 0x4000>;
420 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 438 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
421 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 439 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
440 clocks = <&clks IMX6SLL_CLK_GPIO5>;
422 gpio-controller; 441 gpio-controller;
423 #gpio-cells = <2>; 442 #gpio-cells = <2>;
424 interrupt-controller; 443 interrupt-controller;
425 #interrupt-cells = <2>; 444 #interrupt-cells = <2>;
445 gpio-ranges = <&iomuxc 0 135 1>, <&iomuxc 1 128 1>,
446 <&iomuxc 2 132 1>, <&iomuxc 3 130 1>,
447 <&iomuxc 4 127 1>, <&iomuxc 5 126 1>,
448 <&iomuxc 6 120 1>, <&iomuxc 7 123 1>,
449 <&iomuxc 8 118 1>, <&iomuxc 9 122 1>,
450 <&iomuxc 10 124 1>, <&iomuxc 11 117 1>,
451 <&iomuxc 12 121 1>, <&iomuxc 13 119 1>,
452 <&iomuxc 14 116 1>, <&iomuxc 15 115 1>,
453 <&iomuxc 16 140 2>, <&iomuxc 18 136 1>,
454 <&iomuxc 19 138 1>, <&iomuxc 20 139 1>,
455 <&iomuxc 21 137 1>;
426 }; 456 };
427 457
428 gpio6: gpio@20b0000 { 458 gpio6: gpio@20b0000 {
@@ -430,6 +460,7 @@
430 reg = <0x020b0000 0x4000>; 460 reg = <0x020b0000 0x4000>;
431 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 461 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
432 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 462 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
463 clocks = <&clks IMX6SLL_CLK_GPIO6>;
433 gpio-controller; 464 gpio-controller;
434 #gpio-cells = <2>; 465 #gpio-cells = <2>;
435 interrupt-controller; 466 interrupt-controller;
diff --git a/arch/arm/boot/dts/imx6sx-sdb.dtsi b/arch/arm/boot/dts/imx6sx-sdb.dtsi
index f8f31872fa14..53b3408b5fab 100644
--- a/arch/arm/boot/dts/imx6sx-sdb.dtsi
+++ b/arch/arm/boot/dts/imx6sx-sdb.dtsi
@@ -40,12 +40,14 @@
40 label = "Volume Up"; 40 label = "Volume Up";
41 gpios = <&gpio1 18 GPIO_ACTIVE_LOW>; 41 gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
42 linux,code = <KEY_VOLUMEUP>; 42 linux,code = <KEY_VOLUMEUP>;
43 wakeup-source;
43 }; 44 };
44 45
45 volume-down { 46 volume-down {
46 label = "Volume Down"; 47 label = "Volume Down";
47 gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; 48 gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
48 linux,code = <KEY_VOLUMEDOWN>; 49 linux,code = <KEY_VOLUMEDOWN>;
50 wakeup-source;
49 }; 51 };
50 }; 52 };
51 53
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index 844caa39364f..95a3c1cb877d 100644
--- a/arch/arm/boot/dts/imx6sx.dtsi
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -268,7 +268,7 @@
268 status = "disabled"; 268 status = "disabled";
269 }; 269 };
270 270
271 ecspi1: ecspi@2008000 { 271 ecspi1: spi@2008000 {
272 #address-cells = <1>; 272 #address-cells = <1>;
273 #size-cells = <0>; 273 #size-cells = <0>;
274 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; 274 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
@@ -280,7 +280,7 @@
280 status = "disabled"; 280 status = "disabled";
281 }; 281 };
282 282
283 ecspi2: ecspi@200c000 { 283 ecspi2: spi@200c000 {
284 #address-cells = <1>; 284 #address-cells = <1>;
285 #size-cells = <0>; 285 #size-cells = <0>;
286 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; 286 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
@@ -292,7 +292,7 @@
292 status = "disabled"; 292 status = "disabled";
293 }; 293 };
294 294
295 ecspi3: ecspi@2010000 { 295 ecspi3: spi@2010000 {
296 #address-cells = <1>; 296 #address-cells = <1>;
297 #size-cells = <0>; 297 #size-cells = <0>;
298 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; 298 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
@@ -304,7 +304,7 @@
304 status = "disabled"; 304 status = "disabled";
305 }; 305 };
306 306
307 ecspi4: ecspi@2014000 { 307 ecspi4: spi@2014000 {
308 #address-cells = <1>; 308 #address-cells = <1>;
309 #size-cells = <0>; 309 #size-cells = <0>;
310 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; 310 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
@@ -1079,7 +1079,7 @@
1079 status = "disabled"; 1079 status = "disabled";
1080 }; 1080 };
1081 1081
1082 qspi1: qspi@21e0000 { 1082 qspi1: spi@21e0000 {
1083 #address-cells = <1>; 1083 #address-cells = <1>;
1084 #size-cells = <0>; 1084 #size-cells = <0>;
1085 compatible = "fsl,imx6sx-qspi"; 1085 compatible = "fsl,imx6sx-qspi";
@@ -1092,7 +1092,7 @@
1092 status = "disabled"; 1092 status = "disabled";
1093 }; 1093 };
1094 1094
1095 qspi2: qspi@21e4000 { 1095 qspi2: spi@21e4000 {
1096 #address-cells = <1>; 1096 #address-cells = <1>;
1097 #size-cells = <0>; 1097 #size-cells = <0>;
1098 compatible = "fsl,imx6sx-qspi"; 1098 compatible = "fsl,imx6sx-qspi";
@@ -1273,7 +1273,7 @@
1273 status = "disabled"; 1273 status = "disabled";
1274 }; 1274 };
1275 1275
1276 ecspi5: ecspi@228c000 { 1276 ecspi5: spi@228c000 {
1277 #address-cells = <1>; 1277 #address-cells = <1>;
1278 #size-cells = <0>; 1278 #size-cells = <0>;
1279 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; 1279 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
diff --git a/arch/arm/boot/dts/imx6ul-ccimx6ulsbcpro.dts b/arch/arm/boot/dts/imx6ul-ccimx6ulsbcpro.dts
new file mode 100644
index 000000000000..11966d12af76
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ul-ccimx6ulsbcpro.dts
@@ -0,0 +1,390 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Digi International's ConnectCore6UL SBC Pro board device tree source
4 *
5 * Copyright 2018 Digi International, Inc.
6 *
7 */
8
9/dts-v1/;
10#include <dt-bindings/input/input.h>
11#include <dt-bindings/interrupt-controller/irq.h>
12#include "imx6ul.dtsi"
13#include "imx6ul-ccimx6ulsom.dtsi"
14
15/ {
16 model = "Digi International ConnectCore 6UL SBC Pro.";
17 compatible = "digi,ccimx6ulsbcpro", "digi,ccimx6ulsom", "fsl,imx6ul";
18
19 lcd_backlight: backlight {
20 compatible = "pwm-backlight";
21 pwms = <&pwm5 0 50000>;
22 brightness-levels = <0 4 8 16 32 64 128 255>;
23 default-brightness-level = <6>;
24 status = "okay";
25 };
26
27 reg_usb_otg1_vbus: regulator-usb-otg1 {
28 compatible = "regulator-fixed";
29 regulator-name = "usb_otg1_vbus";
30 regulator-min-microvolt = <5000000>;
31 regulator-max-microvolt = <5000000>;
32 gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
33 enable-active-high;
34 };
35};
36
37&adc1 {
38 pinctrl-names = "default";
39 pinctrl-0 = <&pinctrl_adc1>;
40 status = "okay";
41};
42
43&can1 {
44 pinctrl-names = "default";
45 pinctrl-0 = <&pinctrl_flexcan1>;
46 xceiver-supply = <&ext_3v3>;
47 status = "okay";
48};
49
50/* CAN2 is multiplexed with UART2 RTS/CTS */
51&can2 {
52 pinctrl-names = "default";
53 pinctrl-0 = <&pinctrl_flexcan2>;
54 xceiver-supply = <&ext_3v3>;
55 status = "disabled";
56};
57
58&ecspi1 {
59 cs-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
60 pinctrl-names = "default";
61 pinctrl-0 = <&pinctrl_ecspi1_master>;
62 status = "okay";
63};
64
65&fec1 {
66 pinctrl-names = "default";
67 pinctrl-0 = <&pinctrl_enet1>;
68 phy-mode = "rmii";
69 phy-handle = <&ethphy0>;
70 status = "okay";
71};
72
73&fec2 {
74 pinctrl-names = "default";
75 pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio>;
76 phy-mode = "rmii";
77 phy-handle = <&ethphy1>;
78 phy-reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>;
79 phy-reset-duration = <26>;
80 status = "okay";
81
82 mdio {
83 #address-cells = <1>;
84 #size-cells = <0>;
85
86 ethphy0: ethernet-phy@0 {
87 compatible = "ethernet-phy-ieee802.3-c22";
88 smsc,disable-energy-detect;
89 reg = <0>;
90 };
91
92 ethphy1: ethernet-phy@1 {
93 compatible = "ethernet-phy-ieee802.3-c22";
94 smsc,disable-energy-detect;
95 reg = <1>;
96 };
97 };
98};
99
100&gpio5 {
101 emmc-usd-mux {
102 gpio-hog;
103 gpios = <1 GPIO_ACTIVE_LOW>;
104 output-high;
105 };
106};
107
108&lcdif {
109 pinctrl-names = "default";
110 pinctrl-0 = <&pinctrl_lcdif_dat0_17
111 &pinctrl_lcdif_clken
112 &pinctrl_lcdif_hvsync>;
113 lcd-supply = <&ldo4_ext>; /* BU90T82 LVDS bridge power */
114 status = "okay";
115};
116
117&ldo4_ext {
118 regulator-max-microvolt = <1800000>;
119};
120
121&pwm1 {
122 status = "okay";
123};
124
125&pwm2 {
126 status = "okay";
127};
128
129&pwm3 {
130 status = "okay";
131};
132
133&pwm4 {
134 pinctrl-names = "default";
135 pinctrl-0 = <&pinctrl_pwm4>;
136 status = "okay";
137};
138
139&pwm5 {
140 pinctrl-names = "default";
141 pinctrl-0 = <&pinctrl_pwm5>;
142 status = "okay";
143};
144
145&pwm6 {
146 status = "okay";
147};
148
149&pwm7 {
150 status = "okay";
151};
152
153&pwm8 {
154 status = "okay";
155};
156
157&sai2 {
158 pinctrl-names = "default", "sleep";
159 pinctrl-0 = <&pinctrl_sai2>;
160 pinctrl-1 = <&pinctrl_sai2_sleep>;
161 assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>,
162 <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>,
163 <&clks IMX6UL_CLK_SAI2>;
164 assigned-clock-rates = <0>, <786432000>, <12288000>;
165 assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
166 status = "okay";
167};
168
169/* UART2 RTS/CTS muxed with CAN2 */
170&uart2 {
171 pinctrl-names = "default";
172 pinctrl-0 = <&pinctrl_uart2_4wires>;
173 uart-has-rtscts;
174 status = "okay";
175};
176
177/* UART3 RTS/CTS muxed with CAN 1 */
178&uart3 {
179 pinctrl-names = "default";
180 pinctrl-0 = <&pinctrl_uart3_2wires>;
181 status = "okay";
182};
183
184&uart5 {
185 pinctrl-names = "default";
186 pinctrl-0 = <&pinctrl_uart5>;
187 status = "okay";
188};
189
190&usbotg1 {
191 dr_mode = "otg";
192 vbus-supply = <&reg_usb_otg1_vbus>;
193 pinctrl-0 = <&pinctrl_usbotg1>;
194 status = "okay";
195};
196
197&usbotg2 {
198 dr_mode = "host";
199 disable-over-current;
200 status = "okay";
201};
202
203/* USDHC2 (microSD conflicts with eMMC) */
204&usdhc2 {
205 pinctrl-names = "default";
206 pinctrl-0 = <&pinctrl_usdhc2>;
207 no-1-8-v;
208 broken-cd; /* no carrier detect line (use polling) */
209 status = "okay";
210};
211
212&iomuxc {
213 pinctrl_adc1: adc1grp {
214 fsl,pins = <
215 /* EXP_GPIO_2 -> GPIO1_3/ADC1_IN3 */
216 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
217 >;
218 };
219
220 pinctrl_ecspi1_master: ecspi1grp1 {
221 fsl,pins = <
222 MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x10b0
223 MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x10b0
224 MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x10b0
225 MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x10b0
226 >;
227 };
228
229 pinctrl_enet1: enet1grp {
230 fsl,pins = <
231 MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
232 MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
233 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
234 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
235 MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
236 MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
237 MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
238 MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x40017051
239 >;
240 };
241
242 pinctrl_enet2: enet2grp {
243 fsl,pins = <
244 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
245 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
246 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
247 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
248 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
249 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
250 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
251 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x40017051
252 >;
253 };
254
255 pinctrl_enet2_mdio: mdioenet2grp {
256 fsl,pins = <
257 MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
258 MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
259 >;
260 };
261
262 pinctrl_flexcan1: flexcan1grp{
263 fsl,pins = <
264 MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020
265 MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020
266 >;
267 };
268 pinctrl_flexcan2: flexcan2grp{
269 fsl,pins = <
270 MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020
271 MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020
272 >;
273 };
274
275 pinctrl_lcdif_dat0_17: lcdifdatgrp0-17 {
276 fsl,pins = <
277 MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
278 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
279 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
280 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
281 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
282 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
283 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
284 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
285 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
286 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
287 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
288 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
289 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
290 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
291 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
292 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
293 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
294 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
295 >;
296 };
297
298 pinctrl_lcdif_clken: lcdifctrlgrp1 {
299 fsl,pins = <
300 MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x17050
301 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
302 >;
303 };
304
305 pinctrl_lcdif_hvsync: lcdifctrlgrp2 {
306 fsl,pins = <
307 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
308 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
309 >;
310 };
311
312 pinctrl_pwm4: pwm4grp {
313 fsl,pins = <
314 MX6UL_PAD_GPIO1_IO05__PWM4_OUT 0x110b0
315 >;
316 };
317
318 pinctrl_pwm5: pwm5grp {
319 fsl,pins = <
320 MX6UL_PAD_NAND_DQS__PWM5_OUT 0x110b0
321 >;
322 };
323
324 pinctrl_sai2: sai2grp {
325 fsl,pins = <
326 MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088
327 MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088
328 MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088
329 MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088
330 MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088
331 /* Interrupt */
332 MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x10b0
333 >;
334 };
335
336 pinctrl_sai2_sleep: sai2grp-sleep {
337 fsl,pins = <
338 MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x3000
339 MX6UL_PAD_JTAG_TCK__GPIO1_IO14 0x3000
340 MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x3000
341 MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x3000
342 /* Interrupt */
343 MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x3000
344 >;
345 };
346
347 pinctrl_uart2_4wires: uart2grp-4wires {
348 fsl,pins = <
349 MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
350 MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
351 MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x1b0b1
352 MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x1b0b1
353 >;
354 };
355
356 pinctrl_uart3_2wires: uart3grp-2wires {
357 fsl,pins = <
358 MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1
359 MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1
360 >;
361 };
362
363 pinctrl_uart5: uart5grp {
364 fsl,pins = <
365 MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x1b0b1
366 MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x1b0b1
367 >;
368 };
369
370 pinctrl_usdhc2: usdhc2grp {
371 fsl,pins = <
372 MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x17059
373 MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x10039
374 MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17059
375 MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17059
376 MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17059
377 MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17059
378 /* Mux selector between eMMC/SD# */
379 MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x79
380 >;
381 };
382
383 pinctrl_usbotg1: usbotg1grp {
384 fsl,pins = <
385 MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
386 MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x17059
387 MX6UL_PAD_GPIO1_IO01__USB_OTG1_OC 0x17059
388 >;
389 };
390};
diff --git a/arch/arm/boot/dts/imx6ul-geam.dts b/arch/arm/boot/dts/imx6ul-geam.dts
index d81d20f8fc8d..e22ec5be2b78 100644
--- a/arch/arm/boot/dts/imx6ul-geam.dts
+++ b/arch/arm/boot/dts/imx6ul-geam.dts
@@ -1,43 +1,7 @@
1// SPDX-License-Identifier: GPL-2.0 OR X11
1/* 2/*
2 * Copyright (C) 2016 Amarula Solutions B.V. 3 * Copyright (C) 2016 Amarula Solutions B.V.
3 * Copyright (C) 2016 Engicam S.r.l. 4 * Copyright (C) 2016 Engicam S.r.l.
4 *
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
8 * whole.
9 *
10 * a) This file is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * version 2 as published by the Free Software Foundation.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */ 5 */
42 6
43/dts-v1/; 7/dts-v1/;
@@ -328,7 +292,7 @@
328 >; 292 >;
329 }; 293 };
330 294
331 pinctrl_gpmi_nand: gpmi-nand { 295 pinctrl_gpmi_nand: gpminandgrp {
332 fsl,pins = < 296 fsl,pins = <
333 MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 297 MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1
334 MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 298 MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1
diff --git a/arch/arm/boot/dts/imx6ul-isiot-emmc.dts b/arch/arm/boot/dts/imx6ul-isiot-emmc.dts
index f5b422898e61..1df3e376ae2c 100644
--- a/arch/arm/boot/dts/imx6ul-isiot-emmc.dts
+++ b/arch/arm/boot/dts/imx6ul-isiot-emmc.dts
@@ -1,43 +1,7 @@
1// SPDX-License-Identifier: GPL-2.0 OR X11
1/* 2/*
2 * Copyright (C) 2016 Amarula Solutions B.V. 3 * Copyright (C) 2016 Amarula Solutions B.V.
3 * Copyright (C) 2016 Engicam S.r.l. 4 * Copyright (C) 2016 Engicam S.r.l.
4 *
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
8 * whole.
9 *
10 * a) This file is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * version 2 as published by the Free Software Foundation.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */ 5 */
42 6
43/dts-v1/; 7/dts-v1/;
@@ -50,28 +14,5 @@
50}; 14};
51 15
52&usdhc2 { 16&usdhc2 {
53 pinctrl-names = "default";
54 pinctrl-0 = <&pinctrl_usdhc2>;
55 cd-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>;
56 bus-width = <8>;
57 no-1-8-v;
58 status = "okay"; 17 status = "okay";
59}; 18};
60
61&iomuxc {
62 pinctrl_usdhc2: usdhc2grp {
63 fsl,pins = <
64 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17070
65 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x10070
66 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17070
67 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17070
68 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17070
69 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17070
70 MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17070
71 MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17070
72 MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17070
73 MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17070
74 MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x17070
75 >;
76 };
77};
diff --git a/arch/arm/boot/dts/imx6ul-isiot-nand.dts b/arch/arm/boot/dts/imx6ul-isiot-nand.dts
index de15e1c75dd1..8c26d4d1a7bf 100644
--- a/arch/arm/boot/dts/imx6ul-isiot-nand.dts
+++ b/arch/arm/boot/dts/imx6ul-isiot-nand.dts
@@ -1,43 +1,7 @@
1// SPDX-License-Identifier: GPL-2.0 OR X11
1/* 2/*
2 * Copyright (C) 2016 Amarula Solutions B.V. 3 * Copyright (C) 2016 Amarula Solutions B.V.
3 * Copyright (C) 2016 Engicam S.r.l. 4 * Copyright (C) 2016 Engicam S.r.l.
4 *
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
8 * whole.
9 *
10 * a) This file is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * version 2 as published by the Free Software Foundation.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */ 5 */
42 6
43/dts-v1/; 7/dts-v1/;
@@ -50,30 +14,5 @@
50}; 14};
51 15
52&gpmi { 16&gpmi {
53 pinctrl-names = "default";
54 pinctrl-0 = <&pinctrl_gpmi_nand>;
55 nand-on-flash-bbt;
56 status = "okay"; 17 status = "okay";
57}; 18};
58
59&iomuxc {
60 pinctrl_gpmi_nand: gpmi-nand {
61 fsl,pins = <
62 MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1
63 MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1
64 MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1
65 MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000
66 MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1
67 MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1
68 MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1
69 MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1
70 MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1
71 MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1
72 MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1
73 MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1
74 MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1
75 MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1
76 MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1
77 >;
78 };
79};
diff --git a/arch/arm/boot/dts/imx6ul-isiot.dtsi b/arch/arm/boot/dts/imx6ul-isiot.dtsi
index cd9928551154..b1fa3f0a684d 100644
--- a/arch/arm/boot/dts/imx6ul-isiot.dtsi
+++ b/arch/arm/boot/dts/imx6ul-isiot.dtsi
@@ -1,43 +1,7 @@
1// SPDX-License-Identifier: GPL-2.0 OR X11
1/* 2/*
2 * Copyright (C) 2016 Amarula Solutions B.V. 3 * Copyright (C) 2016 Amarula Solutions B.V.
3 * Copyright (C) 2016 Engicam S.r.l. 4 * Copyright (C) 2016 Engicam S.r.l.
4 *
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
8 * whole.
9 *
10 * a) This file is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * version 2 as published by the Free Software Foundation.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */ 5 */
42 6
43#include <dt-bindings/gpio/gpio.h> 7#include <dt-bindings/gpio/gpio.h>
@@ -133,6 +97,13 @@
133 }; 97 };
134}; 98};
135 99
100&gpmi {
101 pinctrl-names = "default";
102 pinctrl-0 = <&pinctrl_gpmi_nand>;
103 nand-on-flash-bbt;
104 status = "disabled";
105};
106
136&i2c1 { 107&i2c1 {
137 clock-frequency = <100000>; 108 clock-frequency = <100000>;
138 pinctrl-names = "default"; 109 pinctrl-names = "default";
@@ -243,6 +214,15 @@
243 status = "okay"; 214 status = "okay";
244}; 215};
245 216
217&usdhc2 {
218 pinctrl-names = "default";
219 pinctrl-0 = <&pinctrl_usdhc2>;
220 cd-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>;
221 bus-width = <8>;
222 no-1-8-v;
223 status = "disabled";
224};
225
246&iomuxc { 226&iomuxc {
247 pinctrl_enet1: enet1grp { 227 pinctrl_enet1: enet1grp {
248 fsl,pins = < 228 fsl,pins = <
@@ -259,6 +239,26 @@
259 >; 239 >;
260 }; 240 };
261 241
242 pinctrl_gpmi_nand: gpminandgrp {
243 fsl,pins = <
244 MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1
245 MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1
246 MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1
247 MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000
248 MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1
249 MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1
250 MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1
251 MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1
252 MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1
253 MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1
254 MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1
255 MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1
256 MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1
257 MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1
258 MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1
259 >;
260 };
261
262 pinctrl_i2c1: i2c1grp { 262 pinctrl_i2c1: i2c1grp {
263 fsl,pins = < 263 fsl,pins = <
264 MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 264 MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
@@ -366,4 +366,20 @@
366 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 366 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
367 >; 367 >;
368 }; 368 };
369
370 pinctrl_usdhc2: usdhc2grp {
371 fsl,pins = <
372 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17070
373 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x10070
374 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17070
375 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17070
376 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17070
377 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17070
378 MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17070
379 MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17070
380 MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17070
381 MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17070
382 MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x17070
383 >;
384 };
369}; 385};
diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi
index 6dc0b569acdf..083d3446c41d 100644
--- a/arch/arm/boot/dts/imx6ul.dtsi
+++ b/arch/arm/boot/dts/imx6ul.dtsi
@@ -89,6 +89,8 @@
89 "pll1_sys"; 89 "pll1_sys";
90 arm-supply = <&reg_arm>; 90 arm-supply = <&reg_arm>;
91 soc-supply = <&reg_soc>; 91 soc-supply = <&reg_soc>;
92 nvmem-cells = <&cpu_speed_grade>;
93 nvmem-cell-names = "speed_grade";
92 }; 94 };
93 }; 95 };
94 96
@@ -156,7 +158,6 @@
156 compatible = "arm,cortex-a7-pmu"; 158 compatible = "arm,cortex-a7-pmu";
157 interrupt-parent = <&gpc>; 159 interrupt-parent = <&gpc>;
158 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 160 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
159 status = "disabled";
160 }; 161 };
161 162
162 soc { 163 soc {
@@ -218,7 +219,7 @@
218 reg = <0x02000000 0x40000>; 219 reg = <0x02000000 0x40000>;
219 ranges; 220 ranges;
220 221
221 ecspi1: ecspi@2008000 { 222 ecspi1: spi@2008000 {
222 #address-cells = <1>; 223 #address-cells = <1>;
223 #size-cells = <0>; 224 #size-cells = <0>;
224 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; 225 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
@@ -230,7 +231,7 @@
230 status = "disabled"; 231 status = "disabled";
231 }; 232 };
232 233
233 ecspi2: ecspi@200c000 { 234 ecspi2: spi@200c000 {
234 #address-cells = <1>; 235 #address-cells = <1>;
235 #size-cells = <0>; 236 #size-cells = <0>;
236 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; 237 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
@@ -242,7 +243,7 @@
242 status = "disabled"; 243 status = "disabled";
243 }; 244 };
244 245
245 ecspi3: ecspi@2010000 { 246 ecspi3: spi@2010000 {
246 #address-cells = <1>; 247 #address-cells = <1>;
247 #size-cells = <0>; 248 #size-cells = <0>;
248 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; 249 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
@@ -254,7 +255,7 @@
254 status = "disabled"; 255 status = "disabled";
255 }; 256 };
256 257
257 ecspi4: ecspi@2014000 { 258 ecspi4: spi@2014000 {
258 #address-cells = <1>; 259 #address-cells = <1>;
259 #size-cells = <0>; 260 #size-cells = <0>;
260 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; 261 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
@@ -918,6 +919,17 @@
918 reg = <0x021b0000 0x4000>; 919 reg = <0x021b0000 0x4000>;
919 }; 920 };
920 921
922 weim: weim@21b8000 {
923 #address-cells = <2>;
924 #size-cells = <1>;
925 compatible = "fsl,imx6ul-weim", "fsl,imx6q-weim";
926 reg = <0x021b8000 0x4000>;
927 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
928 clocks = <&clks IMX6UL_CLK_EIM>;
929 fsl,weim-cs-gpr = <&gpr>;
930 status = "disabled";
931 };
932
921 ocotp: ocotp-ctrl@21bc000 { 933 ocotp: ocotp-ctrl@21bc000 {
922 #address-cells = <1>; 934 #address-cells = <1>;
923 #size-cells = <1>; 935 #size-cells = <1>;
@@ -932,6 +944,10 @@
932 tempmon_temp_grade: temp-grade@20 { 944 tempmon_temp_grade: temp-grade@20 {
933 reg = <0x20 4>; 945 reg = <0x20 4>;
934 }; 946 };
947
948 cpu_speed_grade: speed-grade@10 {
949 reg = <0x10 4>;
950 };
935 }; 951 };
936 952
937 lcdif: lcdif@21c8000 { 953 lcdif: lcdif@21c8000 {
@@ -945,7 +961,7 @@
945 status = "disabled"; 961 status = "disabled";
946 }; 962 };
947 963
948 qspi: qspi@21e0000 { 964 qspi: spi@21e0000 {
949 #address-cells = <1>; 965 #address-cells = <1>;
950 #size-cells = <0>; 966 #size-cells = <0>;
951 compatible = "fsl,imx6ul-qspi", "fsl,imx6sx-qspi"; 967 compatible = "fsl,imx6ul-qspi", "fsl,imx6sx-qspi";
diff --git a/arch/arm/boot/dts/imx6ull-14x14-evk.dts b/arch/arm/boot/dts/imx6ull-14x14-evk.dts
index 30ef60344af3..0ba64546c13b 100644
--- a/arch/arm/boot/dts/imx6ull-14x14-evk.dts
+++ b/arch/arm/boot/dts/imx6ull-14x14-evk.dts
@@ -45,7 +45,7 @@
45#include "imx6ul-14x14-evk.dtsi" 45#include "imx6ul-14x14-evk.dtsi"
46 46
47/ { 47/ {
48 model = "Freescale i.MX6 UlltraLite 14x14 EVK Board"; 48 model = "Freescale i.MX6 UltraLiteLite 14x14 EVK Board";
49 compatible = "fsl,imx6ull-14x14-evk", "fsl,imx6ull"; 49 compatible = "fsl,imx6ull-14x14-evk", "fsl,imx6ull";
50}; 50};
51 51
diff --git a/arch/arm/boot/dts/imx6ull-pinfunc.h b/arch/arm/boot/dts/imx6ull-pinfunc.h
index fdc46bb09cc1..a282a31a4bae 100644
--- a/arch/arm/boot/dts/imx6ull-pinfunc.h
+++ b/arch/arm/boot/dts/imx6ull-pinfunc.h
@@ -14,14 +14,38 @@
14 * The pin function ID is a tuple of 14 * The pin function ID is a tuple of
15 * <mux_reg conf_reg input_reg mux_mode input_val> 15 * <mux_reg conf_reg input_reg mux_mode input_val>
16 */ 16 */
17/* signals common for i.MX6UL and i.MX6ULL */
18#undef MX6UL_PAD_UART5_TX_DATA__UART5_DTE_RX
19#define MX6UL_PAD_UART5_TX_DATA__UART5_DTE_RX 0x00BC 0x0348 0x0644 0x0 0x6
20#undef MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX
21#define MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x00C0 0x034C 0x0644 0x0 0x7
22#undef MX6UL_PAD_ENET1_RX_EN__UART5_DCE_RTS
23#define MX6UL_PAD_ENET1_RX_EN__UART5_DCE_RTS 0x00CC 0x0358 0x0640 0x1 0x5
24#undef MX6UL_PAD_ENET1_TX_DATA0__UART5_DTE_RTS
25#define MX6UL_PAD_ENET1_TX_DATA0__UART5_DTE_RTS 0x00D0 0x035C 0x0640 0x1 0x6
26#undef MX6UL_PAD_CSI_DATA02__UART5_DCE_RTS
27#define MX6UL_PAD_CSI_DATA02__UART5_DCE_RTS 0x01EC 0x0478 0x0640 0x8 0x7
28
29/* signals for i.MX6ULL only */
30#define MX6ULL_PAD_UART1_TX_DATA__UART5_DCE_TX 0x0084 0x0310 0x0000 0x9 0x0
17#define MX6ULL_PAD_UART1_TX_DATA__UART5_DTE_RX 0x0084 0x0310 0x0644 0x9 0x4 31#define MX6ULL_PAD_UART1_TX_DATA__UART5_DTE_RX 0x0084 0x0310 0x0644 0x9 0x4
18#define MX6ULL_PAD_UART1_RX_DATA__UART5_DCE_RX 0x0088 0x0314 0x0644 0x9 0x5 32#define MX6ULL_PAD_UART1_RX_DATA__UART5_DCE_RX 0x0088 0x0314 0x0644 0x9 0x5
19#define MX6ULL_PAD_UART1_CTS_B__UART5_DCE_RTS 0x008C 0x0318 0x0640 0x9 0x3 33#define MX6ULL_PAD_UART1_RX_DATA__UART5_DTE_TX 0x0088 0x0314 0x0000 0x9 0x0
20#define MX6ULL_PAD_UART1_RTS_B__UART5_DTE_RTS 0x0090 0x031C 0x0640 0x9 0x4 34#define MX6ULL_PAD_UART1_CTS_B__UART5_DCE_CTS 0x008C 0x0318 0x0000 0x9 0x0
21#define MX6ULL_PAD_UART5_TX_DATA__UART5_DTE_RX 0x00BC 0x0348 0x0644 0x0 0x6 35#define MX6ULL_PAD_UART1_CTS_B__UART5_DTE_RTS 0x008C 0x0318 0x0640 0x9 0x3
22#define MX6ULL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x00C0 0x034C 0x0644 0x0 0x7 36#define MX6ULL_PAD_UART1_RTS_B__UART5_DCE_RTS 0x0090 0x031C 0x0640 0x9 0x4
23#define MX6ULL_PAD_ENET1_RX_EN__UART5_DCE_RTS 0x00CC 0x0358 0x0640 0x1 0x5 37#define MX6ULL_PAD_UART1_RTS_B__UART5_DTE_CTS 0x0090 0x031C 0x0000 0x9 0x0
24#define MX6ULL_PAD_ENET1_TX_DATA0__UART5_DTE_RTS 0x00D0 0x035C 0x0640 0x1 0x6 38#define MX6ULL_PAD_UART4_RX_DATA__EPDC_PWRCTRL01 0x00B8 0x0344 0x0000 0x9 0x0
39#define MX6ULL_PAD_UART5_TX_DATA__EPDC_PWRCTRL02 0x00BC 0x0348 0x0000 0x9 0x0
40#define MX6ULL_PAD_UART5_RX_DATA__EPDC_PWRCTRL03 0x00C0 0x034C 0x0000 0x9 0x0
41#define MX6ULL_PAD_ENET1_RX_DATA0__EPDC_SDCE04 0x00C4 0x0350 0x0000 0x9 0x0
42#define MX6ULL_PAD_ENET1_RX_DATA1__EPDC_SDCE05 0x00C8 0x0354 0x0000 0x9 0x0
43#define MX6ULL_PAD_ENET1_RX_EN__EPDC_SDCE06 0x00CC 0x0358 0x0000 0x9 0x0
44#define MX6ULL_PAD_ENET1_TX_DATA0__EPDC_SDCE07 0x00D0 0x035C 0x0000 0x9 0x0
45#define MX6ULL_PAD_ENET1_TX_DATA1__EPDC_SDCE08 0x00D4 0x0360 0x0000 0x9 0x0
46#define MX6ULL_PAD_ENET1_TX_EN__EPDC_SDCE09 0x00D8 0x0364 0x0000 0x9 0x0
47#define MX6ULL_PAD_ENET1_TX_CLK__EPDC_SDOED 0x00DC 0x0368 0x0000 0x9 0x0
48#define MX6ULL_PAD_ENET1_RX_ER__EPDC_SDOEZ 0x00E0 0x036C 0x0000 0x9 0x0
25#define MX6ULL_PAD_ENET2_RX_DATA0__EPDC_SDDO08 0x00E4 0x0370 0x0000 0x9 0x0 49#define MX6ULL_PAD_ENET2_RX_DATA0__EPDC_SDDO08 0x00E4 0x0370 0x0000 0x9 0x0
26#define MX6ULL_PAD_ENET2_RX_DATA1__EPDC_SDDO09 0x00E8 0x0374 0x0000 0x9 0x0 50#define MX6ULL_PAD_ENET2_RX_DATA1__EPDC_SDDO09 0x00E8 0x0374 0x0000 0x9 0x0
27#define MX6ULL_PAD_ENET2_RX_EN__EPDC_SDDO10 0x00EC 0x0378 0x0000 0x9 0x0 51#define MX6ULL_PAD_ENET2_RX_EN__EPDC_SDDO10 0x00EC 0x0378 0x0000 0x9 0x0
@@ -48,6 +72,8 @@
48#define MX6ULL_PAD_LCD_DATA16__EPDC_GDCLK 0x0158 0x03E4 0x0000 0x9 0x0 72#define MX6ULL_PAD_LCD_DATA16__EPDC_GDCLK 0x0158 0x03E4 0x0000 0x9 0x0
49#define MX6ULL_PAD_LCD_DATA17__EPDC_GDSP 0x015C 0x03E8 0x0000 0x9 0x0 73#define MX6ULL_PAD_LCD_DATA17__EPDC_GDSP 0x015C 0x03E8 0x0000 0x9 0x0
50#define MX6ULL_PAD_LCD_DATA21__EPDC_SDCE1 0x016C 0x03F8 0x0000 0x9 0x0 74#define MX6ULL_PAD_LCD_DATA21__EPDC_SDCE1 0x016C 0x03F8 0x0000 0x9 0x0
75#define MX6ULL_PAD_LCD_DATA22__EPDC_SDCE02 0x0170 0x03FC 0x0000 0x9 0x0
76#define MX6ULL_PAD_LCD_DATA23__EPDC_SDCE03 0x0174 0x0400 0x0000 0x9 0x0
51#define MX6ULL_PAD_CSI_MCLK__ESAI_TX3_RX2 0x01D4 0x0460 0x0000 0x9 0x0 77#define MX6ULL_PAD_CSI_MCLK__ESAI_TX3_RX2 0x01D4 0x0460 0x0000 0x9 0x0
52#define MX6ULL_PAD_CSI_PIXCLK__ESAI_TX2_RX3 0x01D8 0x0464 0x0000 0x9 0x0 78#define MX6ULL_PAD_CSI_PIXCLK__ESAI_TX2_RX3 0x01D8 0x0464 0x0000 0x9 0x0
53#define MX6ULL_PAD_CSI_VSYNC__ESAI_TX4_RX1 0x01DC 0x0468 0x0000 0x9 0x0 79#define MX6ULL_PAD_CSI_VSYNC__ESAI_TX4_RX1 0x01DC 0x0468 0x0000 0x9 0x0
@@ -55,7 +81,6 @@
55#define MX6ULL_PAD_CSI_DATA00__ESAI_TX_HF_CLK 0x01E4 0x0470 0x0000 0x9 0x0 81#define MX6ULL_PAD_CSI_DATA00__ESAI_TX_HF_CLK 0x01E4 0x0470 0x0000 0x9 0x0
56#define MX6ULL_PAD_CSI_DATA01__ESAI_RX_HF_CLK 0x01E8 0x0474 0x0000 0x9 0x0 82#define MX6ULL_PAD_CSI_DATA01__ESAI_RX_HF_CLK 0x01E8 0x0474 0x0000 0x9 0x0
57#define MX6ULL_PAD_CSI_DATA02__ESAI_RX_FS 0x01EC 0x0478 0x0000 0x9 0x0 83#define MX6ULL_PAD_CSI_DATA02__ESAI_RX_FS 0x01EC 0x0478 0x0000 0x9 0x0
58#define MX6ULL_PAD_CSI_DATA02__UART5_DCE_RTS 0x01EC 0x0478 0x0640 0x8 0x7
59#define MX6ULL_PAD_CSI_DATA03__ESAI_RX_CLK 0x01F0 0x047C 0x0000 0x9 0x0 84#define MX6ULL_PAD_CSI_DATA03__ESAI_RX_CLK 0x01F0 0x047C 0x0000 0x9 0x0
60#define MX6ULL_PAD_CSI_DATA04__ESAI_TX_FS 0x01F4 0x0480 0x0000 0x9 0x0 85#define MX6ULL_PAD_CSI_DATA04__ESAI_TX_FS 0x01F4 0x0480 0x0000 0x9 0x0
61#define MX6ULL_PAD_CSI_DATA05__ESAI_TX_CLK 0x01F8 0x0484 0x0000 0x9 0x0 86#define MX6ULL_PAD_CSI_DATA05__ESAI_TX_CLK 0x01F8 0x0484 0x0000 0x9 0x0
diff --git a/arch/arm/boot/dts/imx6ull.dtsi b/arch/arm/boot/dts/imx6ull.dtsi
index cd1776a7015a..796ed35d4ac9 100644
--- a/arch/arm/boot/dts/imx6ull.dtsi
+++ b/arch/arm/boot/dts/imx6ull.dtsi
@@ -22,7 +22,7 @@
22 >; 22 >;
23 fsl,soc-operating-points = < 23 fsl,soc-operating-points = <
24 /* KHz uV */ 24 /* KHz uV */
25 900000 1175000 25 900000 1250000
26 792000 1175000 26 792000 1175000
27 528000 1175000 27 528000 1175000
28 396000 1175000 28 396000 1175000
diff --git a/arch/arm/boot/dts/imx6ulz-14x14-evk.dts b/arch/arm/boot/dts/imx6ulz-14x14-evk.dts
new file mode 100644
index 000000000000..6f1af240e0ce
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ulz-14x14-evk.dts
@@ -0,0 +1,20 @@
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2//
3// Copyright 2018 NXP.
4
5/dts-v1/;
6
7#include "imx6ulz.dtsi"
8#include "imx6ul-14x14-evk.dtsi"
9
10/delete-node/ &fec1;
11/delete-node/ &fec2;
12/delete-node/ &lcdif;
13/delete-node/ &tsc;
14
15/ {
16 model = "Freescale i.MX6 ULZ 14x14 EVK Board";
17 compatible = "fsl,imx6ulz-14x14-evk", "fsl,imx6ull", "fsl,imx6ulz";
18
19 /delete-node/ panel;
20};
diff --git a/arch/arm/boot/dts/imx6ulz.dtsi b/arch/arm/boot/dts/imx6ulz.dtsi
new file mode 100644
index 000000000000..ae6d7e593769
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ulz.dtsi
@@ -0,0 +1,38 @@
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2//
3// Copyright 2018 NXP.
4
5#include "imx6ull.dtsi"
6
7/ {
8 aliases {
9 /delete-property/ ethernet0;
10 /delete-property/ ethernet1;
11 /delete-property/ i2c2;
12 /delete-property/ i2c3;
13 /delete-property/ serial4;
14 /delete-property/ serial5;
15 /delete-property/ serial6;
16 /delete-property/ serial7;
17 /delete-property/ spi2;
18 /delete-property/ spi3;
19 };
20};
21
22/delete-node/ &adc1;
23/delete-node/ &can1;
24/delete-node/ &can2;
25/delete-node/ &ecspi3;
26/delete-node/ &ecspi4;
27/delete-node/ &epit2;
28/delete-node/ &gpt2;
29/delete-node/ &i2c3;
30/delete-node/ &i2c4;
31/delete-node/ &pwm5;
32/delete-node/ &pwm6;
33/delete-node/ &pwm7;
34/delete-node/ &pwm8;
35/delete-node/ &uart5;
36/delete-node/ &uart6;
37/delete-node/ &uart7;
38/delete-node/ &uart8;
diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts
index c9b3c60b0eb2..f1bafdaa7e1a 100644
--- a/arch/arm/boot/dts/imx7d-sdb.dts
+++ b/arch/arm/boot/dts/imx7d-sdb.dts
@@ -27,12 +27,14 @@
27 label = "Volume Up"; 27 label = "Volume Up";
28 gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; 28 gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
29 linux,code = <KEY_VOLUMEUP>; 29 linux,code = <KEY_VOLUMEUP>;
30 wakeup-source;
30 }; 31 };
31 32
32 volume-down { 33 volume-down {
33 label = "Volume Down"; 34 label = "Volume Down";
34 gpios = <&gpio5 10 GPIO_ACTIVE_LOW>; 35 gpios = <&gpio5 10 GPIO_ACTIVE_LOW>;
35 linux,code = <KEY_VOLUMEDOWN>; 36 linux,code = <KEY_VOLUMEDOWN>;
37 wakeup-source;
36 }; 38 };
37 }; 39 };
38 40
diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi
index 7234e8330a57..73c35939e07c 100644
--- a/arch/arm/boot/dts/imx7d.dtsi
+++ b/arch/arm/boot/dts/imx7d.dtsi
@@ -20,6 +20,7 @@
20 reg = <1>; 20 reg = <1>;
21 clock-frequency = <996000000>; 21 clock-frequency = <996000000>;
22 operating-points-v2 = <&cpu0_opp_table>; 22 operating-points-v2 = <&cpu0_opp_table>;
23 cpu-idle-states = <&cpu_sleep_wait>;
23 }; 24 };
24 }; 25 };
25 26
@@ -63,9 +64,11 @@
63 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 64 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
64 clock-names = "apb_pclk"; 65 clock-names = "apb_pclk";
65 66
66 port { 67 out-ports {
67 etm1_out_port: endpoint { 68 port {
68 remote-endpoint = <&ca_funnel_in_port1>; 69 etm1_out_port: endpoint {
70 remote-endpoint = <&ca_funnel_in_port1>;
71 };
69 }; 72 };
70 }; 73 };
71 }; 74 };
@@ -152,11 +155,13 @@
152 }; 155 };
153}; 156};
154 157
155&ca_funnel_ports { 158&ca_funnel_in_ports {
159 #address-cells = <1>;
160 #size-cells = <0>;
161
156 port@1 { 162 port@1 {
157 reg = <1>; 163 reg = <1>;
158 ca_funnel_in_port1: endpoint { 164 ca_funnel_in_port1: endpoint {
159 slave-mode;
160 remote-endpoint = <&etm1_out_port>; 165 remote-endpoint = <&etm1_out_port>;
161 }; 166 };
162 }; 167 };
diff --git a/arch/arm/boot/dts/imx7s-warp.dts b/arch/arm/boot/dts/imx7s-warp.dts
index fa390da636de..f7ba2c0a24ad 100644
--- a/arch/arm/boot/dts/imx7s-warp.dts
+++ b/arch/arm/boot/dts/imx7s-warp.dts
@@ -1,44 +1,7 @@
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
1/* 2/*
2 * Copyright (C) 2016 NXP Semiconductors. 3 * Copyright (C) 2016 NXP Semiconductors.
3 * Author: Fabio Estevam <fabio.estevam@nxp.com> 4 * Author: Fabio Estevam <fabio.estevam@nxp.com>
4 *
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
8 * whole.
9 *
10 * a) This file is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of the
13 * License, or (at your option) any later version.
14 *
15 * This file is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * Or, alternatively,
21 *
22 * b) Permission is hereby granted, free of charge, to any person
23 * obtaining a copy of this software and associated documentation
24 * files (the "Software"), to deal in the Software without
25 * restriction, including without limitation the rights to use,
26 * copy, modify, merge, publish, distribute, sublicense, and/or
27 * sell copies of the Software, and to permit persons to whom the
28 * Software is furnished to do so, subject to the following
29 * conditions:
30 *
31 * The above copyright notice and this permission notice shall be
32 * included in all copies or substantial portions of the Software.
33 *
34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41 * OTHER DEALINGS IN THE SOFTWARE.
42 */ 5 */
43 6
44/dts-v1/; 7/dts-v1/;
@@ -216,6 +179,13 @@
216 status = "okay"; 179 status = "okay";
217}; 180};
218 181
182&i2c3 {
183 clock-frequency = <100000>;
184 pinctrl-names = "default";
185 pinctrl-0 = <&pinctrl_i2c3>;
186 status = "okay";
187};
188
219&i2c4 { 189&i2c4 {
220 clock-frequency = <100000>; 190 clock-frequency = <100000>;
221 pinctrl-names = "default"; 191 pinctrl-names = "default";
@@ -346,6 +316,13 @@
346 >; 316 >;
347 }; 317 };
348 318
319 pinctrl_i2c3: i2c3grp {
320 fsl,pins = <
321 MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f
322 MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f
323 >;
324 };
325
349 pinctrl_i2c4: i2c4grp { 326 pinctrl_i2c4: i2c4grp {
350 fsl,pins = < 327 fsl,pins = <
351 MX7D_PAD_I2C4_SCL__I2C4_SCL 0x4000007f 328 MX7D_PAD_I2C4_SCL__I2C4_SCL 0x4000007f
diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi
index a052198f6e96..aa8df7d93b2e 100644
--- a/arch/arm/boot/dts/imx7s.dtsi
+++ b/arch/arm/boot/dts/imx7s.dtsi
@@ -54,6 +54,19 @@
54 #address-cells = <1>; 54 #address-cells = <1>;
55 #size-cells = <0>; 55 #size-cells = <0>;
56 56
57 idle-states {
58 entry-method = "psci";
59
60 cpu_sleep_wait: cpu-sleep-wait {
61 compatible = "arm,idle-state";
62 arm,psci-suspend-param = <0x0010000>;
63 local-timer-stop;
64 entry-latency-us = <100>;
65 exit-latency-us = <50>;
66 min-residency-us = <1000>;
67 };
68 };
69
57 cpu0: cpu@0 { 70 cpu0: cpu@0 {
58 compatible = "arm,cortex-a7"; 71 compatible = "arm,cortex-a7";
59 device_type = "cpu"; 72 device_type = "cpu";
@@ -61,6 +74,7 @@
61 clock-frequency = <792000000>; 74 clock-frequency = <792000000>;
62 clock-latency = <61036>; /* two CLK32 periods */ 75 clock-latency = <61036>; /* two CLK32 periods */
63 clocks = <&clks IMX7D_CLK_ARM>; 76 clocks = <&clks IMX7D_CLK_ARM>;
77 cpu-idle-states = <&cpu_sleep_wait>;
64 }; 78 };
65 }; 79 };
66 80
@@ -106,7 +120,7 @@
106 */ 120 */
107 compatible = "arm,coresight-replicator"; 121 compatible = "arm,coresight-replicator";
108 122
109 ports { 123 out-ports {
110 #address-cells = <1>; 124 #address-cells = <1>;
111 #size-cells = <0>; 125 #size-cells = <0>;
112 /* replicator output ports */ 126 /* replicator output ports */
@@ -123,12 +137,11 @@
123 remote-endpoint = <&etr_in_port>; 137 remote-endpoint = <&etr_in_port>;
124 }; 138 };
125 }; 139 };
140 };
126 141
127 /* replicator input port */ 142 in-ports {
128 port@2 { 143 port {
129 reg = <0>;
130 replicator_in_port0: endpoint { 144 replicator_in_port0: endpoint {
131 slave-mode;
132 remote-endpoint = <&etf_out_port>; 145 remote-endpoint = <&etf_out_port>;
133 }; 146 };
134 }; 147 };
@@ -168,28 +181,23 @@
168 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 181 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
169 clock-names = "apb_pclk"; 182 clock-names = "apb_pclk";
170 183
171 ca_funnel_ports: ports { 184 ca_funnel_in_ports: in-ports {
172 #address-cells = <1>; 185 port {
173 #size-cells = <0>;
174
175 /* funnel input ports */
176 port@0 {
177 reg = <0>;
178 ca_funnel_in_port0: endpoint { 186 ca_funnel_in_port0: endpoint {
179 slave-mode;
180 remote-endpoint = <&etm0_out_port>; 187 remote-endpoint = <&etm0_out_port>;
181 }; 188 };
182 }; 189 };
183 190
184 /* funnel output port */ 191 /* the other input ports are not connect to anything */
185 port@2 { 192 };
186 reg = <0>; 193
194 out-ports {
195 port {
187 ca_funnel_out_port0: endpoint { 196 ca_funnel_out_port0: endpoint {
188 remote-endpoint = <&hugo_funnel_in_port0>; 197 remote-endpoint = <&hugo_funnel_in_port0>;
189 }; 198 };
190 }; 199 };
191 200
192 /* the other input ports are not connect to anything */
193 }; 201 };
194 }; 202 };
195 203
@@ -200,9 +208,11 @@
200 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 208 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
201 clock-names = "apb_pclk"; 209 clock-names = "apb_pclk";
202 210
203 port { 211 out-ports {
204 etm0_out_port: endpoint { 212 port {
205 remote-endpoint = <&ca_funnel_in_port0>; 213 etm0_out_port: endpoint {
214 remote-endpoint = <&ca_funnel_in_port0>;
215 };
206 }; 216 };
207 }; 217 };
208 }; 218 };
@@ -213,15 +223,13 @@
213 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 223 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
214 clock-names = "apb_pclk"; 224 clock-names = "apb_pclk";
215 225
216 ports { 226 in-ports {
217 #address-cells = <1>; 227 #address-cells = <1>;
218 #size-cells = <0>; 228 #size-cells = <0>;
219 229
220 /* funnel input ports */
221 port@0 { 230 port@0 {
222 reg = <0>; 231 reg = <0>;
223 hugo_funnel_in_port0: endpoint { 232 hugo_funnel_in_port0: endpoint {
224 slave-mode;
225 remote-endpoint = <&ca_funnel_out_port0>; 233 remote-endpoint = <&ca_funnel_out_port0>;
226 }; 234 };
227 }; 235 };
@@ -229,18 +237,18 @@
229 port@1 { 237 port@1 {
230 reg = <1>; 238 reg = <1>;
231 hugo_funnel_in_port1: endpoint { 239 hugo_funnel_in_port1: endpoint {
232 slave-mode; /* M4 input */ 240 /* M4 input */
233 }; 241 };
234 }; 242 };
243 /* the other input ports are not connect to anything */
244 };
235 245
236 port@2 { 246 out-ports {
237 reg = <0>; 247 port {
238 hugo_funnel_out_port0: endpoint { 248 hugo_funnel_out_port0: endpoint {
239 remote-endpoint = <&etf_in_port>; 249 remote-endpoint = <&etf_in_port>;
240 }; 250 };
241 }; 251 };
242
243 /* the other input ports are not connect to anything */
244 }; 252 };
245 }; 253 };
246 254
@@ -250,20 +258,16 @@
250 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 258 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
251 clock-names = "apb_pclk"; 259 clock-names = "apb_pclk";
252 260
253 ports { 261 in-ports {
254 #address-cells = <1>; 262 port {
255 #size-cells = <0>;
256
257 port@0 {
258 reg = <0>;
259 etf_in_port: endpoint { 263 etf_in_port: endpoint {
260 slave-mode;
261 remote-endpoint = <&hugo_funnel_out_port0>; 264 remote-endpoint = <&hugo_funnel_out_port0>;
262 }; 265 };
263 }; 266 };
267 };
264 268
265 port@1 { 269 out-ports {
266 reg = <0>; 270 port {
267 etf_out_port: endpoint { 271 etf_out_port: endpoint {
268 remote-endpoint = <&replicator_in_port0>; 272 remote-endpoint = <&replicator_in_port0>;
269 }; 273 };
@@ -277,10 +281,11 @@
277 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 281 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
278 clock-names = "apb_pclk"; 282 clock-names = "apb_pclk";
279 283
280 port { 284 in-ports {
281 etr_in_port: endpoint { 285 port {
282 slave-mode; 286 etr_in_port: endpoint {
283 remote-endpoint = <&replicator_out_port1>; 287 remote-endpoint = <&replicator_out_port1>;
288 };
284 }; 289 };
285 }; 290 };
286 }; 291 };
@@ -291,10 +296,11 @@
291 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 296 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
292 clock-names = "apb_pclk"; 297 clock-names = "apb_pclk";
293 298
294 port { 299 in-ports {
295 tpiu_in_port: endpoint { 300 port {
296 slave-mode; 301 tpiu_in_port: endpoint {
297 remote-endpoint = <&replicator_out_port0>; 302 remote-endpoint = <&replicator_out_port0>;
303 };
298 }; 304 };
299 }; 305 };
300 }; 306 };
@@ -563,14 +569,6 @@
563 clock-names = "snvs-rtc"; 569 clock-names = "snvs-rtc";
564 }; 570 };
565 571
566 snvs_poweroff: snvs-poweroff {
567 compatible = "syscon-poweroff";
568 regmap = <&snvs>;
569 offset = <0x38>;
570 value = <0x60>;
571 mask = <0x60>;
572 };
573
574 snvs_pwrkey: snvs-powerkey { 572 snvs_pwrkey: snvs-powerkey {
575 compatible = "fsl,sec-v4.0-pwrkey"; 573 compatible = "fsl,sec-v4.0-pwrkey";
576 regmap = <&snvs>; 574 regmap = <&snvs>;
@@ -644,7 +642,7 @@
644 status = "disabled"; 642 status = "disabled";
645 }; 643 };
646 644
647 ecspi4: ecspi@30630000 { 645 ecspi4: spi@30630000 {
648 #address-cells = <1>; 646 #address-cells = <1>;
649 #size-cells = <0>; 647 #size-cells = <0>;
650 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; 648 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
@@ -725,7 +723,7 @@
725 reg = <0x30800000 0x100000>; 723 reg = <0x30800000 0x100000>;
726 ranges; 724 ranges;
727 725
728 ecspi1: ecspi@30820000 { 726 ecspi1: spi@30820000 {
729 #address-cells = <1>; 727 #address-cells = <1>;
730 #size-cells = <0>; 728 #size-cells = <0>;
731 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; 729 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
@@ -737,7 +735,7 @@
737 status = "disabled"; 735 status = "disabled";
738 }; 736 };
739 737
740 ecspi2: ecspi@30830000 { 738 ecspi2: spi@30830000 {
741 #address-cells = <1>; 739 #address-cells = <1>;
742 #size-cells = <0>; 740 #size-cells = <0>;
743 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; 741 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
@@ -749,7 +747,7 @@
749 status = "disabled"; 747 status = "disabled";
750 }; 748 };
751 749
752 ecspi3: ecspi@30840000 { 750 ecspi3: spi@30840000 {
753 #address-cells = <1>; 751 #address-cells = <1>;
754 #size-cells = <0>; 752 #size-cells = <0>;
755 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; 753 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
@@ -974,6 +972,25 @@
974 status = "disabled"; 972 status = "disabled";
975 }; 973 };
976 974
975 mu0a: mailbox@30aa0000 {
976 compatible = "fsl,imx7s-mu", "fsl,imx6sx-mu";
977 reg = <0x30aa0000 0x10000>;
978 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
979 clocks = <&clks IMX7D_MU_ROOT_CLK>;
980 #mbox-cells = <2>;
981 status = "disabled";
982 };
983
984 mu0b: mailbox@30ab0000 {
985 compatible = "fsl,imx7s-mu", "fsl,imx6sx-mu";
986 reg = <0x30ab0000 0x10000>;
987 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
988 clocks = <&clks IMX7D_MU_ROOT_CLK>;
989 #mbox-cells = <2>;
990 fsl,mu-side-b;
991 status = "disabled";
992 };
993
977 usbotg1: usb@30b10000 { 994 usbotg1: usb@30b10000 {
978 compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; 995 compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
979 reg = <0x30b10000 0x200>; 996 reg = <0x30b10000 0x200>;
diff --git a/arch/arm/boot/dts/imx7ulp-pinfunc.h b/arch/arm/boot/dts/imx7ulp-pinfunc.h
index fe511775b518..85f6b017803a 100644
--- a/arch/arm/boot/dts/imx7ulp-pinfunc.h
+++ b/arch/arm/boot/dts/imx7ulp-pinfunc.h
@@ -116,6 +116,7 @@
116#define IMX7ULP_PAD_PTC13__LPI2C7_SDA 0x0034 0x030c 0x5 0x1 116#define IMX7ULP_PAD_PTC13__LPI2C7_SDA 0x0034 0x030c 0x5 0x1
117#define IMX7ULP_PAD_PTC13__TPM7_CLKIN 0x0034 0x02f4 0x6 0x1 117#define IMX7ULP_PAD_PTC13__TPM7_CLKIN 0x0034 0x02f4 0x6 0x1
118#define IMX7ULP_PAD_PTC13__FB_AD13 0x0034 0x0000 0x9 0x0 118#define IMX7ULP_PAD_PTC13__FB_AD13 0x0034 0x0000 0x9 0x0
119#define IMX7ULP_PAD_PTC13__USB0_ID 0x0034 0x0338 0xb 0x1
119#define IMX7ULP_PAD_PTC14__PTC14 0x0038 0x0000 0x1 0x0 120#define IMX7ULP_PAD_PTC14__PTC14 0x0038 0x0000 0x1 0x0
120#define IMX7ULP_PAD_PTC14__TRACE_D1 0x0038 0x0000 0xa 0x0 121#define IMX7ULP_PAD_PTC14__TRACE_D1 0x0038 0x0000 0xa 0x0
121#define IMX7ULP_PAD_PTC14__FXIO1_D10 0x0038 0x022c 0x2 0x1 122#define IMX7ULP_PAD_PTC14__FXIO1_D10 0x0038 0x022c 0x2 0x1
@@ -136,6 +137,7 @@
136#define IMX7ULP_PAD_PTC16__LPSPI3_SIN 0x0040 0x0324 0x3 0x1 137#define IMX7ULP_PAD_PTC16__LPSPI3_SIN 0x0040 0x0324 0x3 0x1
137#define IMX7ULP_PAD_PTC16__TPM7_CH2 0x0040 0x02e4 0x6 0x1 138#define IMX7ULP_PAD_PTC16__TPM7_CH2 0x0040 0x02e4 0x6 0x1
138#define IMX7ULP_PAD_PTC16__FB_ALE_FB_CS1_B_FB_TS_B 0x0040 0x0000 0x9 0x0 139#define IMX7ULP_PAD_PTC16__FB_ALE_FB_CS1_B_FB_TS_B 0x0040 0x0000 0x9 0x0
140#define IMX7ULP_PAD_PTC16__USB1_OC2 0x0040 0x0334 0xb 0x1
139#define IMX7ULP_PAD_PTC17__PTC17 0x0044 0x0000 0x1 0x0 141#define IMX7ULP_PAD_PTC17__PTC17 0x0044 0x0000 0x1 0x0
140#define IMX7ULP_PAD_PTC17__FXIO1_D13 0x0044 0x0238 0x2 0x1 142#define IMX7ULP_PAD_PTC17__FXIO1_D13 0x0044 0x0238 0x2 0x1
141#define IMX7ULP_PAD_PTC17__LPSPI3_SOUT 0x0044 0x0328 0x3 0x1 143#define IMX7ULP_PAD_PTC17__LPSPI3_SOUT 0x0044 0x0328 0x3 0x1
@@ -146,11 +148,16 @@
146#define IMX7ULP_PAD_PTC18__LPSPI3_SCK 0x0048 0x0320 0x3 0x1 148#define IMX7ULP_PAD_PTC18__LPSPI3_SCK 0x0048 0x0320 0x3 0x1
147#define IMX7ULP_PAD_PTC18__TPM6_CH0 0x0048 0x02d0 0x6 0x1 149#define IMX7ULP_PAD_PTC18__TPM6_CH0 0x0048 0x02d0 0x6 0x1
148#define IMX7ULP_PAD_PTC18__FB_OE_B 0x0048 0x0000 0x9 0x0 150#define IMX7ULP_PAD_PTC18__FB_OE_B 0x0048 0x0000 0x9 0x0
151#define IMX7ULP_PAD_PTC18__USB0_ID 0x0048 0x0338 0xb 0x2
152#define IMX7ULP_PAD_PTC18__VIU_DE 0x0048 0x033c 0xc 0x1
149#define IMX7ULP_PAD_PTC19__PTC19 0x004c 0x0000 0x1 0x0 153#define IMX7ULP_PAD_PTC19__PTC19 0x004c 0x0000 0x1 0x0
150#define IMX7ULP_PAD_PTC19__FXIO1_D15 0x004c 0x0240 0x2 0x1 154#define IMX7ULP_PAD_PTC19__FXIO1_D15 0x004c 0x0240 0x2 0x1
151#define IMX7ULP_PAD_PTC19__LPSPI3_PCS0 0x004c 0x0310 0x3 0x1 155#define IMX7ULP_PAD_PTC19__LPSPI3_PCS0 0x004c 0x0310 0x3 0x1
152#define IMX7ULP_PAD_PTC19__TPM6_CH1 0x004c 0x02d4 0x6 0x1 156#define IMX7ULP_PAD_PTC19__TPM6_CH1 0x004c 0x02d4 0x6 0x1
153#define IMX7ULP_PAD_PTC19__FB_A16 0x004c 0x0000 0x9 0x0 157#define IMX7ULP_PAD_PTC19__FB_A16 0x004c 0x0000 0x9 0x0
158#define IMX7ULP_PAD_PTC19__USB0_ID 0x004c 0x0338 0xa 0x3
159#define IMX7ULP_PAD_PTC19__USB1_PWR2 0x004c 0x0000 0xb 0x0
160#define IMX7ULP_PAD_PTC19__VIU_DE 0x004c 0x033c 0xc 0x3
154#define IMX7ULP_PAD_PTD0__PTD0 0x0080 0x0000 0x1 0x0 161#define IMX7ULP_PAD_PTD0__PTD0 0x0080 0x0000 0x1 0x0
155#define IMX7ULP_PAD_PTD0__SDHC0_RESET_B 0x0080 0x0000 0x8 0x0 162#define IMX7ULP_PAD_PTD0__SDHC0_RESET_B 0x0080 0x0000 0x8 0x0
156#define IMX7ULP_PAD_PTD1__PTD1 0x0084 0x0000 0x1 0x0 163#define IMX7ULP_PAD_PTD1__PTD1 0x0084 0x0000 0x1 0x0
@@ -218,6 +225,7 @@
218#define IMX7ULP_PAD_PTE5__LPI2C5_SDA 0x0114 0x02c0 0x5 0x2 225#define IMX7ULP_PAD_PTE5__LPI2C5_SDA 0x0114 0x02c0 0x5 0x2
219#define IMX7ULP_PAD_PTE5__TPM5_CH0 0x0114 0x02c4 0x6 0x2 226#define IMX7ULP_PAD_PTE5__TPM5_CH0 0x0114 0x02c4 0x6 0x2
220#define IMX7ULP_PAD_PTE5__SDHC1_D2 0x0114 0x0000 0x8 0x0 227#define IMX7ULP_PAD_PTE5__SDHC1_D2 0x0114 0x0000 0x8 0x0
228#define IMX7ULP_PAD_PTE5__VIU_DE 0x0114 0x033c 0xc 0x2
221#define IMX7ULP_PAD_PTE6__PTE6 0x0118 0x0000 0x1 0x0 229#define IMX7ULP_PAD_PTE6__PTE6 0x0118 0x0000 0x1 0x0
222#define IMX7ULP_PAD_PTE6__FXIO1_D25 0x0118 0x0000 0x2 0x0 230#define IMX7ULP_PAD_PTE6__FXIO1_D25 0x0118 0x0000 0x2 0x0
223#define IMX7ULP_PAD_PTE6__LPSPI2_SCK 0x0118 0x02ac 0x3 0x2 231#define IMX7ULP_PAD_PTE6__LPSPI2_SCK 0x0118 0x02ac 0x3 0x2
@@ -226,8 +234,10 @@
226#define IMX7ULP_PAD_PTE6__TPM7_CH3 0x0118 0x02e8 0x6 0x2 234#define IMX7ULP_PAD_PTE6__TPM7_CH3 0x0118 0x02e8 0x6 0x2
227#define IMX7ULP_PAD_PTE6__SDHC1_D4 0x0118 0x0000 0x8 0x0 235#define IMX7ULP_PAD_PTE6__SDHC1_D4 0x0118 0x0000 0x8 0x0
228#define IMX7ULP_PAD_PTE6__FB_A17 0x0118 0x0000 0x9 0x0 236#define IMX7ULP_PAD_PTE6__FB_A17 0x0118 0x0000 0x9 0x0
237#define IMX7ULP_PAD_PTE6__USB0_OC 0x0118 0x0330 0xb 0x1
229#define IMX7ULP_PAD_PTE7__PTE7 0x011c 0x0000 0x1 0x0 238#define IMX7ULP_PAD_PTE7__PTE7 0x011c 0x0000 0x1 0x0
230#define IMX7ULP_PAD_PTE7__TRACE_D7 0x011c 0x0000 0xa 0x0 239#define IMX7ULP_PAD_PTE7__TRACE_D7 0x011c 0x0000 0xa 0x0
240#define IMX7ULP_PAD_PTE7__USB0_PWR 0x011c 0x0000 0xb 0x0
231#define IMX7ULP_PAD_PTE7__VIU_FID 0x011c 0x0000 0xc 0x0 241#define IMX7ULP_PAD_PTE7__VIU_FID 0x011c 0x0000 0xc 0x0
232#define IMX7ULP_PAD_PTE7__FXIO1_D24 0x011c 0x0000 0x2 0x0 242#define IMX7ULP_PAD_PTE7__FXIO1_D24 0x011c 0x0000 0x2 0x0
233#define IMX7ULP_PAD_PTE7__LPSPI2_PCS0 0x011c 0x029c 0x3 0x2 243#define IMX7ULP_PAD_PTE7__LPSPI2_PCS0 0x011c 0x029c 0x3 0x2
@@ -278,6 +288,7 @@
278#define IMX7ULP_PAD_PTE11__FB_A20 0x012c 0x0000 0x9 0x0 288#define IMX7ULP_PAD_PTE11__FB_A20 0x012c 0x0000 0x9 0x0
279#define IMX7ULP_PAD_PTE12__PTE12 0x0130 0x0000 0x1 0x0 289#define IMX7ULP_PAD_PTE12__PTE12 0x0130 0x0000 0x1 0x0
280#define IMX7ULP_PAD_PTE12__TRACE_D2 0x0130 0x0000 0xa 0x0 290#define IMX7ULP_PAD_PTE12__TRACE_D2 0x0130 0x0000 0xa 0x0
291#define IMX7ULP_PAD_PTE12__USB1_OC2 0x0130 0x0334 0xb 0x2
281#define IMX7ULP_PAD_PTE12__VIU_D20 0x0130 0x0000 0xc 0x0 292#define IMX7ULP_PAD_PTE12__VIU_D20 0x0130 0x0000 0xc 0x0
282#define IMX7ULP_PAD_PTE12__FXIO1_D19 0x0130 0x0000 0x2 0x0 293#define IMX7ULP_PAD_PTE12__FXIO1_D19 0x0130 0x0000 0x2 0x0
283#define IMX7ULP_PAD_PTE12__LPSPI3_SIN 0x0130 0x0324 0x3 0x2 294#define IMX7ULP_PAD_PTE12__LPSPI3_SIN 0x0130 0x0324 0x3 0x2
@@ -288,6 +299,7 @@
288#define IMX7ULP_PAD_PTE12__FB_A21 0x0130 0x0000 0x9 0x0 299#define IMX7ULP_PAD_PTE12__FB_A21 0x0130 0x0000 0x9 0x0
289#define IMX7ULP_PAD_PTE13__PTE13 0x0134 0x0000 0x1 0x0 300#define IMX7ULP_PAD_PTE13__PTE13 0x0134 0x0000 0x1 0x0
290#define IMX7ULP_PAD_PTE13__TRACE_D1 0x0134 0x0000 0xa 0x0 301#define IMX7ULP_PAD_PTE13__TRACE_D1 0x0134 0x0000 0xa 0x0
302#define IMX7ULP_PAD_PTE13__USB1_PWR2 0x0134 0x0000 0xb 0x0
291#define IMX7ULP_PAD_PTE13__VIU_D21 0x0134 0x0000 0xc 0x0 303#define IMX7ULP_PAD_PTE13__VIU_D21 0x0134 0x0000 0xc 0x0
292#define IMX7ULP_PAD_PTE13__FXIO1_D18 0x0134 0x0000 0x2 0x0 304#define IMX7ULP_PAD_PTE13__FXIO1_D18 0x0134 0x0000 0x2 0x0
293#define IMX7ULP_PAD_PTE13__LPSPI3_SOUT 0x0134 0x0328 0x3 0x2 305#define IMX7ULP_PAD_PTE13__LPSPI3_SOUT 0x0134 0x0328 0x3 0x2
@@ -298,6 +310,7 @@
298#define IMX7ULP_PAD_PTE13__FB_A22 0x0134 0x0000 0x9 0x0 310#define IMX7ULP_PAD_PTE13__FB_A22 0x0134 0x0000 0x9 0x0
299#define IMX7ULP_PAD_PTE14__PTE14 0x0138 0x0000 0x1 0x0 311#define IMX7ULP_PAD_PTE14__PTE14 0x0138 0x0000 0x1 0x0
300#define IMX7ULP_PAD_PTE14__TRACE_D0 0x0138 0x0000 0xa 0x0 312#define IMX7ULP_PAD_PTE14__TRACE_D0 0x0138 0x0000 0xa 0x0
313#define IMX7ULP_PAD_PTE14__USB0_OC 0x0138 0x0330 0xb 0x2
301#define IMX7ULP_PAD_PTE14__VIU_D22 0x0138 0x0000 0xc 0x0 314#define IMX7ULP_PAD_PTE14__VIU_D22 0x0138 0x0000 0xc 0x0
302#define IMX7ULP_PAD_PTE14__FXIO1_D17 0x0138 0x0000 0x2 0x0 315#define IMX7ULP_PAD_PTE14__FXIO1_D17 0x0138 0x0000 0x2 0x0
303#define IMX7ULP_PAD_PTE14__LPSPI3_SCK 0x0138 0x0320 0x3 0x2 316#define IMX7ULP_PAD_PTE14__LPSPI3_SCK 0x0138 0x0320 0x3 0x2
@@ -308,6 +321,7 @@
308#define IMX7ULP_PAD_PTE14__FB_A23 0x0138 0x0000 0x9 0x0 321#define IMX7ULP_PAD_PTE14__FB_A23 0x0138 0x0000 0x9 0x0
309#define IMX7ULP_PAD_PTE15__PTE15 0x013c 0x0000 0x1 0x0 322#define IMX7ULP_PAD_PTE15__PTE15 0x013c 0x0000 0x1 0x0
310#define IMX7ULP_PAD_PTE15__TRACE_CLKOUT 0x013c 0x0000 0xa 0x0 323#define IMX7ULP_PAD_PTE15__TRACE_CLKOUT 0x013c 0x0000 0xa 0x0
324#define IMX7ULP_PAD_PTE15__USB0_PWR 0x013c 0x0000 0xb 0x0
311#define IMX7ULP_PAD_PTE15__VIU_D23 0x013c 0x0000 0xc 0x0 325#define IMX7ULP_PAD_PTE15__VIU_D23 0x013c 0x0000 0xc 0x0
312#define IMX7ULP_PAD_PTE15__FXIO1_D16 0x013c 0x0000 0x2 0x0 326#define IMX7ULP_PAD_PTE15__FXIO1_D16 0x013c 0x0000 0x2 0x0
313#define IMX7ULP_PAD_PTE15__LPSPI3_PCS0 0x013c 0x0310 0x3 0x2 327#define IMX7ULP_PAD_PTE15__LPSPI3_PCS0 0x013c 0x0310 0x3 0x2
@@ -315,7 +329,7 @@
315#define IMX7ULP_PAD_PTE15__TPM6_CH1 0x013c 0x02d4 0x6 0x2 329#define IMX7ULP_PAD_PTE15__TPM6_CH1 0x013c 0x02d4 0x6 0x2
316#define IMX7ULP_PAD_PTE15__FB_A24 0x013c 0x0000 0x9 0x0 330#define IMX7ULP_PAD_PTE15__FB_A24 0x013c 0x0000 0x9 0x0
317#define IMX7ULP_PAD_PTF0__PTF0 0x0180 0x0000 0x1 0x0 331#define IMX7ULP_PAD_PTF0__PTF0 0x0180 0x0000 0x1 0x0
318#define IMX7ULP_PAD_PTF0__VIU_DE 0x0180 0x0000 0xc 0x0 332#define IMX7ULP_PAD_PTF0__VIU_DE 0x0180 0x033c 0xc 0x0
319#define IMX7ULP_PAD_PTF0__LPUART4_CTS_B 0x0180 0x0244 0x4 0x3 333#define IMX7ULP_PAD_PTF0__LPUART4_CTS_B 0x0180 0x0244 0x4 0x3
320#define IMX7ULP_PAD_PTF0__LPI2C4_SCL 0x0180 0x0278 0x5 0x3 334#define IMX7ULP_PAD_PTF0__LPI2C4_SCL 0x0180 0x0278 0x5 0x3
321#define IMX7ULP_PAD_PTF0__TPM4_CLKIN 0x0180 0x0298 0x6 0x3 335#define IMX7ULP_PAD_PTF0__TPM4_CLKIN 0x0180 0x0298 0x6 0x3
diff --git a/arch/arm/boot/dts/ls1021a-qds.dts b/arch/arm/boot/dts/ls1021a-qds.dts
index 499f41a2c6f0..923a25760516 100644
--- a/arch/arm/boot/dts/ls1021a-qds.dts
+++ b/arch/arm/boot/dts/ls1021a-qds.dts
@@ -1,5 +1,6 @@
1/* 1/*
2 * Copyright 2013-2014 Freescale Semiconductor, Inc. 2 * Copyright 2013-2014 Freescale Semiconductor, Inc.
3 * Copyright 2018 NXP
3 * 4 *
4 * This file is dual-licensed: you can use it either under the terms 5 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual 6 * of the GPL or the X11 license, at your option. Note that this dual
@@ -235,6 +236,7 @@
235 #size-cells = <1>; 236 #size-cells = <1>;
236 compatible = "cfi-flash"; 237 compatible = "cfi-flash";
237 reg = <0x0 0x0 0x8000000>; 238 reg = <0x0 0x0 0x8000000>;
239 big-endian;
238 bank-width = <2>; 240 bank-width = <2>;
239 device-width = <1>; 241 device-width = <1>;
240 }; 242 };
diff --git a/arch/arm/boot/dts/ls1021a-twr.dts b/arch/arm/boot/dts/ls1021a-twr.dts
index f0c949d74833..8b48c3c7cd21 100644
--- a/arch/arm/boot/dts/ls1021a-twr.dts
+++ b/arch/arm/boot/dts/ls1021a-twr.dts
@@ -1,5 +1,6 @@
1/* 1/*
2 * Copyright 2013-2014 Freescale Semiconductor, Inc. 2 * Copyright 2013-2014 Freescale Semiconductor, Inc.
3 * Copyright 2018 NXP
3 * 4 *
4 * This file is dual-licensed: you can use it either under the terms 5 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual 6 * of the GPL or the X11 license, at your option. Note that this dual
@@ -203,6 +204,7 @@
203 #size-cells = <1>; 204 #size-cells = <1>;
204 compatible = "cfi-flash"; 205 compatible = "cfi-flash";
205 reg = <0x0 0x0 0x8000000>; 206 reg = <0x0 0x0 0x8000000>;
207 big-endian;
206 bank-width = <2>; 208 bank-width = <2>;
207 device-width = <1>; 209 device-width = <1>;
208 }; 210 };
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index f18490548c78..bdd6e66a79ad 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -163,7 +163,7 @@
163 big-endian; 163 big-endian;
164 }; 164 };
165 165
166 qspi: quadspi@1550000 { 166 qspi: spi@1550000 {
167 compatible = "fsl,ls1021a-qspi"; 167 compatible = "fsl,ls1021a-qspi";
168 #address-cells = <1>; 168 #address-cells = <1>;
169 #size-cells = <0>; 169 #size-cells = <0>;
@@ -330,7 +330,7 @@
330 }; 330 };
331 }; 331 };
332 332
333 dspi0: dspi@2100000 { 333 dspi0: spi@2100000 {
334 compatible = "fsl,ls1021a-v1.0-dspi"; 334 compatible = "fsl,ls1021a-v1.0-dspi";
335 #address-cells = <1>; 335 #address-cells = <1>;
336 #size-cells = <0>; 336 #size-cells = <0>;
@@ -343,7 +343,7 @@
343 status = "disabled"; 343 status = "disabled";
344 }; 344 };
345 345
346 dspi1: dspi@2110000 { 346 dspi1: spi@2110000 {
347 compatible = "fsl,ls1021a-v1.0-dspi"; 347 compatible = "fsl,ls1021a-v1.0-dspi";
348 #address-cells = <1>; 348 #address-cells = <1>;
349 #size-cells = <0>; 349 #size-cells = <0>;
@@ -364,6 +364,8 @@
364 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 364 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
365 clock-names = "i2c"; 365 clock-names = "i2c";
366 clocks = <&clockgen 4 1>; 366 clocks = <&clockgen 4 1>;
367 dma-names = "tx", "rx";
368 dmas = <&edma0 1 39>, <&edma0 1 38>;
367 status = "disabled"; 369 status = "disabled";
368 }; 370 };
369 371
@@ -375,6 +377,8 @@
375 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 377 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
376 clock-names = "i2c"; 378 clock-names = "i2c";
377 clocks = <&clockgen 4 1>; 379 clocks = <&clockgen 4 1>;
380 dma-names = "tx", "rx";
381 dmas = <&edma0 1 37>, <&edma0 1 36>;
378 status = "disabled"; 382 status = "disabled";
379 }; 383 };
380 384
@@ -386,6 +390,8 @@
386 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 390 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
387 clock-names = "i2c"; 391 clock-names = "i2c";
388 clocks = <&clockgen 4 1>; 392 clocks = <&clockgen 4 1>;
393 dma-names = "tx", "rx";
394 dmas = <&edma0 1 35>, <&edma0 1 34>;
389 status = "disabled"; 395 status = "disabled";
390 }; 396 };
391 397
diff --git a/arch/arm/boot/dts/vf500.dtsi b/arch/arm/boot/dts/vf500.dtsi
index bbff0115e2fb..76a0949df4a8 100644
--- a/arch/arm/boot/dts/vf500.dtsi
+++ b/arch/arm/boot/dts/vf500.dtsi
@@ -1,43 +1,6 @@
1/* 1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 * Copyright 2013 Freescale Semiconductor, Inc. 2//
3 * 3// Copyright 2013 Freescale Semiconductor, Inc.
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * Or, alternatively,
19 *
20 * b) Permission is hereby granted, free of charge, to any person
21 * obtaining a copy of this software and associated documentation
22 * files (the "Software"), to deal in the Software without
23 * restriction, including without limitation the rights to use,
24 * copy, modify, merge, publish, distribute, sublicense, and/or
25 * sell copies of the Software, and to permit persons to whom the
26 * Software is furnished to do so, subject to the following
27 * conditions:
28 *
29 * The above copyright notice and this permission notice shall be
30 * included in all copies or substantial portions of the Software.
31 *
32 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
33 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
34 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
35 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
36 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
37 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
38 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
39 * OTHER DEALINGS IN THE SOFTWARE.
40 */
41 4
42#include "vfxxx.dtsi" 5#include "vfxxx.dtsi"
43#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/interrupt-controller/arm-gic.h>
diff --git a/arch/arm/boot/dts/vf610-twr.dts b/arch/arm/boot/dts/vf610-twr.dts
index 6be7a828ae64..59fceea8805d 100644
--- a/arch/arm/boot/dts/vf610-twr.dts
+++ b/arch/arm/boot/dts/vf610-twr.dts
@@ -1,43 +1,6 @@
1/* 1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 * Copyright 2013 Freescale Semiconductor, Inc. 2//
3 * 3// Copyright 2013 Freescale Semiconductor, Inc.
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * Or, alternatively,
19 *
20 * b) Permission is hereby granted, free of charge, to any person
21 * obtaining a copy of this software and associated documentation
22 * files (the "Software"), to deal in the Software without
23 * restriction, including without limitation the rights to use,
24 * copy, modify, merge, publish, distribute, sublicense, and/or
25 * sell copies of the Software, and to permit persons to whom the
26 * Software is furnished to do so, subject to the following
27 * conditions:
28 *
29 * The above copyright notice and this permission notice shall be
30 * included in all copies or substantial portions of the Software.
31 *
32 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
33 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
34 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
35 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
36 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
37 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
38 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
39 * OTHER DEALINGS IN THE SOFTWARE.
40 */
41 4
42/dts-v1/; 5/dts-v1/;
43#include "vf610.dtsi" 6#include "vf610.dtsi"
diff --git a/arch/arm/boot/dts/vf610-zii-cfu1.dts b/arch/arm/boot/dts/vf610-zii-cfu1.dts
index 37777cf22e67..b76c3d0413df 100644
--- a/arch/arm/boot/dts/vf610-zii-cfu1.dts
+++ b/arch/arm/boot/dts/vf610-zii-cfu1.dts
@@ -66,6 +66,15 @@
66 regulator-min-microvolt = <3300000>; 66 regulator-min-microvolt = <3300000>;
67 regulator-max-microvolt = <3300000>; 67 regulator-max-microvolt = <3300000>;
68 }; 68 };
69
70 sff: sfp {
71 compatible = "sff,sff";
72 pinctrl-0 = <&pinctrl_optical>;
73 pinctrl-names = "default";
74 i2c-bus = <&i2c0>;
75 los-gpio = <&gpio4 4 GPIO_ACTIVE_HIGH>;
76 tx-disable-gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
77 };
69}; 78};
70 79
71&adc0 { 80&adc0 {
@@ -113,6 +122,8 @@
113 non-removable; 122 non-removable;
114 no-1-8-v; 123 no-1-8-v;
115 keep-power-in-suspend; 124 keep-power-in-suspend;
125 no-sdio;
126 no-sd;
116 status = "okay"; 127 status = "okay";
117}; 128};
118 129
@@ -120,6 +131,7 @@
120 pinctrl-names = "default"; 131 pinctrl-names = "default";
121 pinctrl-0 = <&pinctrl_esdhc1>; 132 pinctrl-0 = <&pinctrl_esdhc1>;
122 bus-width = <4>; 133 bus-width = <4>;
134 no-sdio;
123 status = "okay"; 135 status = "okay";
124}; 136};
125 137
@@ -170,6 +182,14 @@
170 label = "eth_cu_1000_3"; 182 label = "eth_cu_1000_3";
171 }; 183 };
172 184
185 port@5 {
186 reg = <5>;
187 label = "eth_fc_1000_1";
188 phy-mode = "1000base-x";
189 managed = "in-band-status";
190 sfp = <&sff>;
191 };
192
173 port@6 { 193 port@6 {
174 reg = <6>; 194 reg = <6>;
175 label = "cpu"; 195 label = "cpu";
@@ -289,6 +309,16 @@
289 >; 309 >;
290 }; 310 };
291 311
312 pinctrl_optical: optical-grp {
313 fsl,pins = <
314 /* SFF SD input */
315 VF610_PAD_PTE27__GPIO_132 0x3061
316
317 /* SFF Transmit disable output */
318 VF610_PAD_PTE13__GPIO_118 0x3043
319 >;
320 };
321
292 pinctrl_switch: switch-grp { 322 pinctrl_switch: switch-grp {
293 fsl,pins = < 323 fsl,pins = <
294 VF610_PAD_PTB28__GPIO_98 0x3061 324 VF610_PAD_PTB28__GPIO_98 0x3061
diff --git a/arch/arm/boot/dts/vf610-zii-dev-rev-c.dts b/arch/arm/boot/dts/vf610-zii-dev-rev-c.dts
index 0b1e94c6f25b..6f4a5602cefd 100644
--- a/arch/arm/boot/dts/vf610-zii-dev-rev-c.dts
+++ b/arch/arm/boot/dts/vf610-zii-dev-rev-c.dts
@@ -200,6 +200,13 @@
200 phy-handle = <&switch1phy4>; 200 phy-handle = <&switch1phy4>;
201 }; 201 };
202 202
203 port@9 {
204 reg = <9>;
205 label = "sff2";
206 phy-mode = "sgmii";
207 managed = "in-band-status";
208 sfp = <&sff2>;
209 };
203 210
204 switch1port10: port@10 { 211 switch1port10: port@10 {
205 reg = <10>; 212 reg = <10>;
@@ -245,6 +252,22 @@
245 #size-cells = <0>; 252 #size-cells = <0>;
246 }; 253 };
247 }; 254 };
255
256 sff2: sff2 {
257 /* lower */
258 compatible = "sff,sff";
259 i2c-bus = <&sff2_i2c>;
260 los-gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>;
261 tx-disable-gpios = <&gpio6 14 GPIO_ACTIVE_HIGH>;
262 };
263
264 sff3: sff3 {
265 /* upper */
266 compatible = "sff,sff";
267 i2c-bus = <&sff3_i2c>;
268 los-gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>;
269 tx-disable-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
270 };
248}; 271};
249 272
250&dspi0 { 273&dspi0 {
@@ -329,13 +352,6 @@
329 interrupts = <23 IRQ_TYPE_EDGE_FALLING>; 352 interrupts = <23 IRQ_TYPE_EDGE_FALLING>;
330 gpio-controller; 353 gpio-controller;
331 interrupt-controller; 354 interrupt-controller;
332
333 enet_swr_en {
334 gpio-hog;
335 gpios = <0 GPIO_ACTIVE_HIGH>;
336 output-high;
337 line-name = "enet-swr-en";
338 };
339 }; 355 };
340 356
341 /* 357 /*
@@ -378,26 +394,16 @@
378 reg = <0>; 394 reg = <0>;
379 }; 395 };
380 396
381 i2c@1 { 397 sff2_i2c: i2c@1 {
382 #address-cells = <1>; 398 #address-cells = <1>;
383 #size-cells = <0>; 399 #size-cells = <0>;
384 reg = <1>; 400 reg = <1>;
385
386 sfp2: at24c04@50 {
387 compatible = "atmel,24c02";
388 reg = <0x50>;
389 };
390 }; 401 };
391 402
392 i2c@2 { 403 sff3_i2c: i2c@2 {
393 #address-cells = <1>; 404 #address-cells = <1>;
394 #size-cells = <0>; 405 #size-cells = <0>;
395 reg = <2>; 406 reg = <2>;
396
397 sfp3: at24c04@50 {
398 compatible = "atmel,24c02";
399 reg = <0x50>;
400 };
401 }; 407 };
402 408
403 i2c@3 { 409 i2c@3 {
diff --git a/arch/arm/boot/dts/vf610.dtsi b/arch/arm/boot/dts/vf610.dtsi
index 80fef182c672..7fd39817f8ab 100644
--- a/arch/arm/boot/dts/vf610.dtsi
+++ b/arch/arm/boot/dts/vf610.dtsi
@@ -1,43 +1,7 @@
1/* 1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 * Copyright 2013 Freescale Semiconductor, Inc. 2//
3 * 3// Copyright 2013 Freescale Semiconductor, Inc.
4 * This file is dual-licensed: you can use it either under the terms 4
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * Or, alternatively,
19 *
20 * b) Permission is hereby granted, free of charge, to any person
21 * obtaining a copy of this software and associated documentation
22 * files (the "Software"), to deal in the Software without
23 * restriction, including without limitation the rights to use,
24 * copy, modify, merge, publish, distribute, sublicense, and/or
25 * sell copies of the Software, and to permit persons to whom the
26 * Software is furnished to do so, subject to the following
27 * conditions:
28 *
29 * The above copyright notice and this permission notice shall be
30 * included in all copies or substantial portions of the Software.
31 *
32 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
33 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
34 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
35 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
36 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
37 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
38 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
39 * OTHER DEALINGS IN THE SOFTWARE.
40 */
41 5
42#include "vf500.dtsi" 6#include "vf500.dtsi"
43 7
diff --git a/arch/arm/boot/dts/vfxxx.dtsi b/arch/arm/boot/dts/vfxxx.dtsi
index d392794d9c13..028e0ec30e0c 100644
--- a/arch/arm/boot/dts/vfxxx.dtsi
+++ b/arch/arm/boot/dts/vfxxx.dtsi
@@ -1,43 +1,6 @@
1/* 1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 * Copyright 2013 Freescale Semiconductor, Inc. 2//
3 * 3// Copyright 2013 Freescale Semiconductor, Inc.
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * Or, alternatively,
19 *
20 * b) Permission is hereby granted, free of charge, to any person
21 * obtaining a copy of this software and associated documentation
22 * files (the "Software"), to deal in the Software without
23 * restriction, including without limitation the rights to use,
24 * copy, modify, merge, publish, distribute, sublicense, and/or
25 * sell copies of the Software, and to permit persons to whom the
26 * Software is furnished to do so, subject to the following
27 * conditions:
28 *
29 * The above copyright notice and this permission notice shall be
30 * included in all copies or substantial portions of the Software.
31 *
32 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
33 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
34 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
35 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
36 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
37 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
38 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
39 * OTHER DEALINGS IN THE SOFTWARE.
40 */
41 4
42#include "vf610-pinfunc.h" 5#include "vf610-pinfunc.h"
43#include <dt-bindings/clock/vf610-clock.h> 6#include <dt-bindings/clock/vf610-clock.h>
@@ -190,7 +153,7 @@
190 status = "disabled"; 153 status = "disabled";
191 }; 154 };
192 155
193 dspi0: dspi0@4002c000 { 156 dspi0: spi@4002c000 {
194 #address-cells = <1>; 157 #address-cells = <1>;
195 #size-cells = <0>; 158 #size-cells = <0>;
196 compatible = "fsl,vf610-dspi"; 159 compatible = "fsl,vf610-dspi";
@@ -205,7 +168,7 @@
205 status = "disabled"; 168 status = "disabled";
206 }; 169 };
207 170
208 dspi1: dspi1@4002d000 { 171 dspi1: spi@4002d000 {
209 #address-cells = <1>; 172 #address-cells = <1>;
210 #size-cells = <0>; 173 #size-cells = <0>;
211 compatible = "fsl,vf610-dspi"; 174 compatible = "fsl,vf610-dspi";
@@ -339,7 +302,7 @@
339 status = "disabled"; 302 status = "disabled";
340 }; 303 };
341 304
342 qspi0: quadspi@40044000 { 305 qspi0: spi@40044000 {
343 #address-cells = <1>; 306 #address-cells = <1>;
344 #size-cells = <0>; 307 #size-cells = <0>;
345 compatible = "fsl,vf610-qspi"; 308 compatible = "fsl,vf610-qspi";
@@ -569,7 +532,7 @@
569 status = "disabled"; 532 status = "disabled";
570 }; 533 };
571 534
572 dspi2: dspi2@400ac000 { 535 dspi2: spi@400ac000 {
573 #address-cells = <1>; 536 #address-cells = <1>;
574 #size-cells = <0>; 537 #size-cells = <0>;
575 compatible = "fsl,vf610-dspi"; 538 compatible = "fsl,vf610-dspi";
@@ -584,7 +547,7 @@
584 status = "disabled"; 547 status = "disabled";
585 }; 548 };
586 549
587 dspi3: dspi3@400ad000 { 550 dspi3: spi@400ad000 {
588 #address-cells = <1>; 551 #address-cells = <1>;
589 #size-cells = <0>; 552 #size-cells = <0>;
590 compatible = "fsl,vf610-dspi"; 553 compatible = "fsl,vf610-dspi";
@@ -665,7 +628,7 @@
665 status = "disabled"; 628 status = "disabled";
666 }; 629 };
667 630
668 qspi1: quadspi@400c4000 { 631 qspi1: spi@400c4000 {
669 #address-cells = <1>; 632 #address-cells = <1>;
670 #size-cells = <0>; 633 #size-cells = <0>;
671 compatible = "fsl,vf610-qspi"; 634 compatible = "fsl,vf610-qspi";
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-24 04:53:07 -0400