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authorArnd Bergmann <arnd@arndb.de>2018-10-02 05:32:10 -0400
committerArnd Bergmann <arnd@arndb.de>2018-10-02 05:36:38 -0400
commit55dc97235b6553d27661ee1fb05d882c7c776b96 (patch)
treea49e85c09ec277dbf81e0caef4ab69251d3132f7
parent5908704d98e0aca3765feca7824e90327bcfff5e (diff)
parentca02f96b95ca1a50344e7e2a7bb43fbb825aa3a2 (diff)
Merge tag 'qcom-dts-for-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into next/dt
Qualcomm Device Tree Changes for v4.20 * Fix IRQ constants usage on MSM8974 * Add led, gpio-button, sdcc, and pcie nodes for IPQ8064 * Move/cleanup common nodes for IPQ8064 * Add i2c sensor nodes for MSM8974 Hammerhead * Fixes for SAW, kpss, opp, pci range, and space/tab on IPQ4019 * Update coresight bindings * tag 'qcom-dts-for-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux: ARM: dts: qcom: Update coresight bindings for hardware ports ARM: dts: qcom-msm8974: change invalid flag IRQ NONE to valid value ARM: dts: qcom: ipq4019: fix space vs tab indenting inside qcom-ipq4019.dtsi ARM: dts: qcom: ipq4019: fix PCI range ARM: dts: qcom: ipq4019: fix cpu0's qcom,saw2 reg value ARM: dts: qcom: ipq4019: add cpu operating points for cpufreq support ARM: dts: qcom: ipq4019: use v2 of the kpss bringup mechanism ARM: dts: qcom: msm8974-hammerhead: add device tree bindings for ALS / proximity ARM: dts: qcom: msm8974-hammerhead: add device tree bindings for mpu6515 ARM: dts: qcom: Add led and gpio-button nodes to ipq8064 boards ARM: dts: qcom: Move common nodes to ipq8064-v.1.0.dtsi ARM: dts: qcom: Add sdcc nodes for ipq8064 ARM: dts: qcom: Add pcie nodes for ipq8064 ARM: dts: qcom-msm8974: change invalid flag IRQ NONE to valid value ARM: dts: qcom-msm8974: use named constant for interrupt flag NONE ARM: dts: qcom-msm8974: use named constant for interrupt flag LEVEL HIGH ARM: dts: qcom-msm8974: use named constant for interrupt flag EDGE RISING ARM: dts: qcom-msm8974: use named constant for interrupt type GIC_SPI ARM: dts: qcom-msm8974: use named constant for interrupt type GIC_PPI Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat
-rw-r--r--arch/arm/boot/dts/qcom-apq8064.dtsi71
-rw-r--r--arch/arm/boot/dts/qcom-ipq4019.dtsi143
-rw-r--r--arch/arm/boot/dts/qcom-ipq8064-ap148.dts83
-rw-r--r--arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi125
-rw-r--r--arch/arm/boot/dts/qcom-ipq8064.dtsi286
-rw-r--r--arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts83
-rw-r--r--arch/arm/boot/dts/qcom-msm8974.dtsi198
7 files changed, 731 insertions, 258 deletions
diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
index 4a99c9255104..48c3cf427610 100644
--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -1611,10 +1611,11 @@
1611 clocks = <&rpmcc RPM_QDSS_CLK>; 1611 clocks = <&rpmcc RPM_QDSS_CLK>;
1612 clock-names = "apb_pclk"; 1612 clock-names = "apb_pclk";
1613 1613
1614 port { 1614 in-ports {
1615 etb_in: endpoint { 1615 port {
1616 slave-mode; 1616 etb_in: endpoint {
1617 remote-endpoint = <&replicator_out0>; 1617 remote-endpoint = <&replicator_out0>;
1618 };
1618 }; 1619 };
1619 }; 1620 };
1620 }; 1621 };
@@ -1626,10 +1627,11 @@
1626 clocks = <&rpmcc RPM_QDSS_CLK>; 1627 clocks = <&rpmcc RPM_QDSS_CLK>;
1627 clock-names = "apb_pclk"; 1628 clock-names = "apb_pclk";
1628 1629
1629 port { 1630 in-ports {
1630 tpiu_in: endpoint { 1631 port {
1631 slave-mode; 1632 tpiu_in: endpoint {
1632 remote-endpoint = <&replicator_out1>; 1633 remote-endpoint = <&replicator_out1>;
1634 };
1633 }; 1635 };
1634 }; 1636 };
1635 }; 1637 };
@@ -1640,7 +1642,7 @@
1640 clocks = <&rpmcc RPM_QDSS_CLK>; 1642 clocks = <&rpmcc RPM_QDSS_CLK>;
1641 clock-names = "apb_pclk"; 1643 clock-names = "apb_pclk";
1642 1644
1643 ports { 1645 out-ports {
1644 #address-cells = <1>; 1646 #address-cells = <1>;
1645 #size-cells = <0>; 1647 #size-cells = <0>;
1646 1648
@@ -1656,10 +1658,11 @@
1656 remote-endpoint = <&tpiu_in>; 1658 remote-endpoint = <&tpiu_in>;
1657 }; 1659 };
1658 }; 1660 };
1659 port@2 { 1661 };
1660 reg = <0>; 1662
1663 in-ports {
1664 port {
1661 replicator_in: endpoint { 1665 replicator_in: endpoint {
1662 slave-mode;
1663 remote-endpoint = <&funnel_out>; 1666 remote-endpoint = <&funnel_out>;
1664 }; 1667 };
1665 }; 1668 };
@@ -1673,7 +1676,7 @@
1673 clocks = <&rpmcc RPM_QDSS_CLK>; 1676 clocks = <&rpmcc RPM_QDSS_CLK>;
1674 clock-names = "apb_pclk"; 1677 clock-names = "apb_pclk";
1675 1678
1676 ports { 1679 in-ports {
1677 #address-cells = <1>; 1680 #address-cells = <1>;
1678 #size-cells = <0>; 1681 #size-cells = <0>;
1679 1682
@@ -1687,33 +1690,31 @@
1687 port@0 { 1690 port@0 {
1688 reg = <0>; 1691 reg = <0>;
1689 funnel_in0: endpoint { 1692 funnel_in0: endpoint {
1690 slave-mode;
1691 remote-endpoint = <&etm0_out>; 1693 remote-endpoint = <&etm0_out>;
1692 }; 1694 };
1693 }; 1695 };
1694 port@1 { 1696 port@1 {
1695 reg = <1>; 1697 reg = <1>;
1696 funnel_in1: endpoint { 1698 funnel_in1: endpoint {
1697 slave-mode;
1698 remote-endpoint = <&etm1_out>; 1699 remote-endpoint = <&etm1_out>;
1699 }; 1700 };
1700 }; 1701 };
1701 port@4 { 1702 port@4 {
1702 reg = <4>; 1703 reg = <4>;
1703 funnel_in4: endpoint { 1704 funnel_in4: endpoint {
1704 slave-mode;
1705 remote-endpoint = <&etm2_out>; 1705 remote-endpoint = <&etm2_out>;
1706 }; 1706 };
1707 }; 1707 };
1708 port@5 { 1708 port@5 {
1709 reg = <5>; 1709 reg = <5>;
1710 funnel_in5: endpoint { 1710 funnel_in5: endpoint {
1711 slave-mode;
1712 remote-endpoint = <&etm3_out>; 1711 remote-endpoint = <&etm3_out>;
1713 }; 1712 };
1714 }; 1713 };
1715 port@8 { 1714 };
1716 reg = <0>; 1715
1716 out-ports {
1717 port {
1717 funnel_out: endpoint { 1718 funnel_out: endpoint {
1718 remote-endpoint = <&replicator_in>; 1719 remote-endpoint = <&replicator_in>;
1719 }; 1720 };
@@ -1730,9 +1731,11 @@
1730 1731
1731 cpu = <&CPU0>; 1732 cpu = <&CPU0>;
1732 1733
1733 port { 1734 out-ports {
1734 etm0_out: endpoint { 1735 port {
1735 remote-endpoint = <&funnel_in0>; 1736 etm0_out: endpoint {
1737 remote-endpoint = <&funnel_in0>;
1738 };
1736 }; 1739 };
1737 }; 1740 };
1738 }; 1741 };
@@ -1746,9 +1749,11 @@
1746 1749
1747 cpu = <&CPU1>; 1750 cpu = <&CPU1>;
1748 1751
1749 port { 1752 out-ports {
1750 etm1_out: endpoint { 1753 port {
1751 remote-endpoint = <&funnel_in1>; 1754 etm1_out: endpoint {
1755 remote-endpoint = <&funnel_in1>;
1756 };
1752 }; 1757 };
1753 }; 1758 };
1754 }; 1759 };
@@ -1762,9 +1767,11 @@
1762 1767
1763 cpu = <&CPU2>; 1768 cpu = <&CPU2>;
1764 1769
1765 port { 1770 out-ports {
1766 etm2_out: endpoint { 1771 port {
1767 remote-endpoint = <&funnel_in4>; 1772 etm2_out: endpoint {
1773 remote-endpoint = <&funnel_in4>;
1774 };
1768 }; 1775 };
1769 }; 1776 };
1770 }; 1777 };
@@ -1778,9 +1785,11 @@
1778 1785
1779 cpu = <&CPU3>; 1786 cpu = <&CPU3>;
1780 1787
1781 port { 1788 out-ports {
1782 etm3_out: endpoint { 1789 port {
1783 remote-endpoint = <&funnel_in5>; 1790 etm3_out: endpoint {
1791 remote-endpoint = <&funnel_in5>;
1792 };
1784 }; 1793 };
1785 }; 1794 };
1786 }; 1795 };
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index 78db67337ed4..2d56008d8d6b 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -52,78 +52,85 @@
52 cpu@0 { 52 cpu@0 {
53 device_type = "cpu"; 53 device_type = "cpu";
54 compatible = "arm,cortex-a7"; 54 compatible = "arm,cortex-a7";
55 enable-method = "qcom,kpss-acc-v1"; 55 enable-method = "qcom,kpss-acc-v2";
56 next-level-cache = <&L2>;
56 qcom,acc = <&acc0>; 57 qcom,acc = <&acc0>;
57 qcom,saw = <&saw0>; 58 qcom,saw = <&saw0>;
58 reg = <0x0>; 59 reg = <0x0>;
59 clocks = <&gcc GCC_APPS_CLK_SRC>; 60 clocks = <&gcc GCC_APPS_CLK_SRC>;
60 clock-frequency = <0>; 61 clock-frequency = <0>;
61 operating-points = <
62 /* kHz uV (fixed) */
63 48000 1100000
64 200000 1100000
65 500000 1100000
66 716000 1100000
67 >;
68 clock-latency = <256000>; 62 clock-latency = <256000>;
63 operating-points-v2 = <&cpu0_opp_table>;
69 }; 64 };
70 65
71 cpu@1 { 66 cpu@1 {
72 device_type = "cpu"; 67 device_type = "cpu";
73 compatible = "arm,cortex-a7"; 68 compatible = "arm,cortex-a7";
74 enable-method = "qcom,kpss-acc-v1"; 69 enable-method = "qcom,kpss-acc-v2";
70 next-level-cache = <&L2>;
75 qcom,acc = <&acc1>; 71 qcom,acc = <&acc1>;
76 qcom,saw = <&saw1>; 72 qcom,saw = <&saw1>;
77 reg = <0x1>; 73 reg = <0x1>;
78 clocks = <&gcc GCC_APPS_CLK_SRC>; 74 clocks = <&gcc GCC_APPS_CLK_SRC>;
79 clock-frequency = <0>; 75 clock-frequency = <0>;
80 operating-points = <
81 /* kHz uV (fixed) */
82 48000 1100000
83 200000 1100000
84 500000 1100000
85 666000 1100000
86 >;
87 clock-latency = <256000>; 76 clock-latency = <256000>;
77 operating-points-v2 = <&cpu0_opp_table>;
88 }; 78 };
89 79
90 cpu@2 { 80 cpu@2 {
91 device_type = "cpu"; 81 device_type = "cpu";
92 compatible = "arm,cortex-a7"; 82 compatible = "arm,cortex-a7";
93 enable-method = "qcom,kpss-acc-v1"; 83 enable-method = "qcom,kpss-acc-v2";
84 next-level-cache = <&L2>;
94 qcom,acc = <&acc2>; 85 qcom,acc = <&acc2>;
95 qcom,saw = <&saw2>; 86 qcom,saw = <&saw2>;
96 reg = <0x2>; 87 reg = <0x2>;
97 clocks = <&gcc GCC_APPS_CLK_SRC>; 88 clocks = <&gcc GCC_APPS_CLK_SRC>;
98 clock-frequency = <0>; 89 clock-frequency = <0>;
99 operating-points = <
100 /* kHz uV (fixed) */
101 48000 1100000
102 200000 1100000
103 500000 1100000
104 666000 1100000
105 >;
106 clock-latency = <256000>; 90 clock-latency = <256000>;
91 operating-points-v2 = <&cpu0_opp_table>;
107 }; 92 };
108 93
109 cpu@3 { 94 cpu@3 {
110 device_type = "cpu"; 95 device_type = "cpu";
111 compatible = "arm,cortex-a7"; 96 compatible = "arm,cortex-a7";
112 enable-method = "qcom,kpss-acc-v1"; 97 enable-method = "qcom,kpss-acc-v2";
98 next-level-cache = <&L2>;
113 qcom,acc = <&acc3>; 99 qcom,acc = <&acc3>;
114 qcom,saw = <&saw3>; 100 qcom,saw = <&saw3>;
115 reg = <0x3>; 101 reg = <0x3>;
116 clocks = <&gcc GCC_APPS_CLK_SRC>; 102 clocks = <&gcc GCC_APPS_CLK_SRC>;
117 clock-frequency = <0>; 103 clock-frequency = <0>;
118 operating-points = <
119 /* kHz uV (fixed) */
120 48000 1100000
121 200000 1100000
122 500000 1100000
123 666000 1100000
124 >;
125 clock-latency = <256000>; 104 clock-latency = <256000>;
105 operating-points-v2 = <&cpu0_opp_table>;
126 }; 106 };
107
108 L2: l2-cache {
109 compatible = "cache";
110 cache-level = <2>;
111 };
112 };
113
114 cpu0_opp_table: opp_table0 {
115 compatible = "operating-points-v2";
116 opp-shared;
117
118 opp-48000000 {
119 opp-hz = /bits/ 64 <48000000>;
120 clock-latency-ns = <256000>;
121 };
122 opp-200000000 {
123 opp-hz = /bits/ 64 <200000000>;
124 clock-latency-ns = <256000>;
125 };
126 opp-500000000 {
127 opp-hz = /bits/ 64 <500000000>;
128 clock-latency-ns = <256000>;
129 };
130 opp-716000000 {
131 opp-hz = /bits/ 64 <716000000>;
132 clock-latency-ns = <256000>;
133 };
127 }; 134 };
128 135
129 pmu { 136 pmu {
@@ -291,49 +298,49 @@
291 status = "disabled"; 298 status = "disabled";
292 }; 299 };
293 300
294 acc0: clock-controller@b088000 { 301 acc0: clock-controller@b088000 {
295 compatible = "qcom,kpss-acc-v1"; 302 compatible = "qcom,kpss-acc-v2";
296 reg = <0x0b088000 0x1000>, <0xb008000 0x1000>; 303 reg = <0x0b088000 0x1000>, <0xb008000 0x1000>;
297 }; 304 };
298 305
299 acc1: clock-controller@b098000 { 306 acc1: clock-controller@b098000 {
300 compatible = "qcom,kpss-acc-v1"; 307 compatible = "qcom,kpss-acc-v2";
301 reg = <0x0b098000 0x1000>, <0xb008000 0x1000>; 308 reg = <0x0b098000 0x1000>, <0xb008000 0x1000>;
302 }; 309 };
303 310
304 acc2: clock-controller@b0a8000 { 311 acc2: clock-controller@b0a8000 {
305 compatible = "qcom,kpss-acc-v1"; 312 compatible = "qcom,kpss-acc-v2";
306 reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>; 313 reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>;
307 }; 314 };
308 315
309 acc3: clock-controller@b0b8000 { 316 acc3: clock-controller@b0b8000 {
310 compatible = "qcom,kpss-acc-v1"; 317 compatible = "qcom,kpss-acc-v2";
311 reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>; 318 reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>;
312 }; 319 };
313 320
314 saw0: regulator@b089000 { 321 saw0: regulator@b089000 {
315 compatible = "qcom,saw2"; 322 compatible = "qcom,saw2";
316 reg = <0x02089000 0x1000>, <0x0b009000 0x1000>; 323 reg = <0x0b089000 0x1000>, <0x0b009000 0x1000>;
317 regulator; 324 regulator;
318 }; 325 };
319 326
320 saw1: regulator@b099000 { 327 saw1: regulator@b099000 {
321 compatible = "qcom,saw2"; 328 compatible = "qcom,saw2";
322 reg = <0x0b099000 0x1000>, <0x0b009000 0x1000>; 329 reg = <0x0b099000 0x1000>, <0x0b009000 0x1000>;
323 regulator; 330 regulator;
324 }; 331 };
325 332
326 saw2: regulator@b0a9000 { 333 saw2: regulator@b0a9000 {
327 compatible = "qcom,saw2"; 334 compatible = "qcom,saw2";
328 reg = <0x0b0a9000 0x1000>, <0x0b009000 0x1000>; 335 reg = <0x0b0a9000 0x1000>, <0x0b009000 0x1000>;
329 regulator; 336 regulator;
330 }; 337 };
331 338
332 saw3: regulator@b0b9000 { 339 saw3: regulator@b0b9000 {
333 compatible = "qcom,saw2"; 340 compatible = "qcom,saw2";
334 reg = <0x0b0b9000 0x1000>, <0x0b009000 0x1000>; 341 reg = <0x0b0b9000 0x1000>, <0x0b009000 0x1000>;
335 regulator; 342 regulator;
336 }; 343 };
337 344
338 blsp1_uart1: serial@78af000 { 345 blsp1_uart1: serial@78af000 {
339 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 346 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
@@ -387,7 +394,7 @@
387 #size-cells = <2>; 394 #size-cells = <2>;
388 395
389 ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000 396 ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000
390 0x82000000 0 0x48000000 0x48000000 0 0x10000000>; 397 0x82000000 0 0x40300000 0x40300000 0 0x400000>;
391 398
392 interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>; 399 interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>;
393 interrupt-names = "msi"; 400 interrupt-names = "msi";
diff --git a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
index bcf53e37ed93..554c65e7aa0e 100644
--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
+++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
@@ -2,26 +2,8 @@
2#include "qcom-ipq8064-v1.0.dtsi" 2#include "qcom-ipq8064-v1.0.dtsi"
3 3
4/ { 4/ {
5 model = "Qualcomm IPQ8064/AP148"; 5 model = "Qualcomm Technologies, Inc. IPQ8064/AP-148";
6 compatible = "qcom,ipq8064-ap148", "qcom,ipq8064"; 6 compatible = "qcom,ipq8064-ap148";
7
8 aliases {
9 serial0 = &gsbi4_serial;
10 };
11
12 chosen {
13 stdout-path = "serial0:115200n8";
14 };
15
16 reserved-memory {
17 #address-cells = <1>;
18 #size-cells = <1>;
19 ranges;
20 rsvd@41200000 {
21 reg = <0x41200000 0x300000>;
22 no-map;
23 };
24 };
25 7
26 soc { 8 soc {
27 pinmux@800000 { 9 pinmux@800000 {
@@ -31,73 +13,22 @@
31 bias-disable; 13 bias-disable;
32 }; 14 };
33 15
34 spi_pins: spi_pins { 16 buttons_pins: buttons_pins {
35 mux { 17 mux {
36 pins = "gpio18", "gpio19", "gpio21"; 18 pins = "gpio54", "gpio65";
37 function = "gsbi5"; 19 drive-strength = <2>;
38 drive-strength = <10>; 20 bias-pull-up;
39 bias-none;
40 }; 21 };
41 }; 22 };
42 }; 23 };
43 24
44 gsbi@16300000 { 25 gsbi@16300000 {
45 qcom,mode = <GSBI_PROT_I2C_UART>; 26 i2c@16380000 {
46 status = "ok";
47 serial@16340000 {
48 status = "ok"; 27 status = "ok";
49 };
50
51 i2c4: i2c@16380000 {
52 status = "ok";
53
54 clock-frequency = <200000>; 28 clock-frequency = <200000>;
55
56 pinctrl-0 = <&i2c4_pins>; 29 pinctrl-0 = <&i2c4_pins>;
57 pinctrl-names = "default"; 30 pinctrl-names = "default";
58 }; 31 };
59 }; 32 };
60
61 gsbi5: gsbi@1a200000 {
62 qcom,mode = <GSBI_PROT_SPI>;
63 status = "ok";
64
65 spi4: spi@1a280000 {
66 status = "ok";
67 spi-max-frequency = <50000000>;
68
69 pinctrl-0 = <&spi_pins>;
70 pinctrl-names = "default";
71
72 cs-gpios = <&qcom_pinmux 20 0>;
73
74 flash: m25p80@0 {
75 compatible = "s25fl256s1";
76 #address-cells = <1>;
77 #size-cells = <1>;
78 spi-max-frequency = <50000000>;
79 reg = <0>;
80
81 partition@0 {
82 label = "rootfs";
83 reg = <0x0 0x1000000>;
84 };
85
86 partition@1 {
87 label = "scratch";
88 reg = <0x1000000 0x1000000>;
89 };
90 };
91 };
92 };
93
94 sata-phy@1b400000 {
95 status = "ok";
96 };
97
98 sata@29000000 {
99 ports-implemented = <0x1>;
100 status = "ok";
101 };
102 }; 33 };
103}; 34};
diff --git a/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi b/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi
index e1181194e8d3..e239a0486936 100644
--- a/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi
@@ -1,2 +1,127 @@
1// SPDX-License-Identifier: GPL-2.0 1// SPDX-License-Identifier: GPL-2.0
2#include "qcom-ipq8064.dtsi" 2#include "qcom-ipq8064.dtsi"
3#include <dt-bindings/input/input.h>
4
5/ {
6 model = "Qualcomm Technologies, Inc. IPQ8064-v1.0";
7
8 aliases {
9 serial0 = &gsbi4_serial;
10 };
11
12 chosen {
13 stdout-path = "serial0:115200n8";
14 };
15
16 soc {
17 gsbi@16300000 {
18 qcom,mode = <GSBI_PROT_I2C_UART>;
19 status = "ok";
20
21 serial@16340000 {
22 status = "ok";
23 };
24 };
25
26 gsbi5: gsbi@1a200000 {
27 qcom,mode = <GSBI_PROT_SPI>;
28 status = "ok";
29
30 spi4: spi@1a280000 {
31 status = "ok";
32 spi-max-frequency = <50000000>;
33
34 pinctrl-0 = <&spi_pins>;
35 pinctrl-names = "default";
36
37 cs-gpios = <&qcom_pinmux 20 0>;
38
39 flash: m25p80@0 {
40 compatible = "s25fl256s1";
41 #address-cells = <1>;
42 #size-cells = <1>;
43 spi-max-frequency = <50000000>;
44 reg = <0>;
45
46 partition@0 {
47 label = "rootfs";
48 reg = <0x0 0x1000000>;
49 };
50
51 partition@1 {
52 label = "scratch";
53 reg = <0x1000000 0x1000000>;
54 };
55 };
56 };
57 };
58
59 sata-phy@1b400000 {
60 status = "ok";
61 };
62
63 sata@29000000 {
64 ports-implemented = <0x1>;
65 status = "ok";
66 };
67
68 gpio_keys {
69 compatible = "gpio-keys";
70 pinctrl-0 = <&buttons_pins>;
71 pinctrl-names = "default";
72
73 button@1 {
74 label = "reset";
75 linux,code = <KEY_RESTART>;
76 gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
77 linux,input-type = <1>;
78 debounce-interval = <60>;
79 };
80 button@2 {
81 label = "wps";
82 linux,code = <KEY_WPS_BUTTON>;
83 gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
84 linux,input-type = <1>;
85 debounce-interval = <60>;
86 };
87 };
88
89 leds {
90 compatible = "gpio-leds";
91 pinctrl-0 = <&leds_pins>;
92 pinctrl-names = "default";
93
94 led@7 {
95 label = "led_usb1";
96 gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
97 linux,default-trigger = "usbdev";
98 default-state = "off";
99 };
100
101 led@8 {
102 label = "led_usb3";
103 gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
104 linux,default-trigger = "usbdev";
105 default-state = "off";
106 };
107
108 led@9 {
109 label = "status_led_fail";
110 gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
111 default-state = "off";
112 };
113
114 led@26 {
115 label = "sata_led";
116 gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;
117 default-state = "off";
118 };
119
120 led@53 {
121 label = "status_led_pass";
122 gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
123 default-state = "off";
124 };
125 };
126 };
127};
diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index 70790ac242d1..f793cd1ad6d0 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -2,8 +2,11 @@
2/dts-v1/; 2/dts-v1/;
3 3
4#include "skeleton.dtsi" 4#include "skeleton.dtsi"
5#include <dt-bindings/interrupt-controller/arm-gic.h>
5#include <dt-bindings/clock/qcom,gcc-ipq806x.h> 6#include <dt-bindings/clock/qcom,gcc-ipq806x.h>
6#include <dt-bindings/clock/qcom,lcc-ipq806x.h> 7#include <dt-bindings/clock/qcom,lcc-ipq806x.h>
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/reset/qcom,gcc-ipq806x.h>
7#include <dt-bindings/soc/qcom,gsbi.h> 10#include <dt-bindings/soc/qcom,gsbi.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h>
9 12
@@ -114,6 +117,61 @@
114 interrupt-controller; 117 interrupt-controller;
115 #interrupt-cells = <2>; 118 #interrupt-cells = <2>;
116 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 119 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
120
121 pcie0_pins: pcie0_pinmux {
122 mux {
123 pins = "gpio3";
124 function = "pcie1_rst";
125 drive-strength = <12>;
126 bias-disable;
127 };
128 };
129
130 pcie1_pins: pcie1_pinmux {
131 mux {
132 pins = "gpio48";
133 function = "pcie2_rst";
134 drive-strength = <12>;
135 bias-disable;
136 };
137 };
138
139 pcie2_pins: pcie2_pinmux {
140 mux {
141 pins = "gpio63";
142 function = "pcie3_rst";
143 drive-strength = <12>;
144 bias-disable;
145 };
146 };
147
148 spi_pins: spi_pins {
149 mux {
150 pins = "gpio18", "gpio19", "gpio21";
151 function = "gsbi5";
152 drive-strength = <10>;
153 bias-none;
154 };
155 };
156
157 leds_pins: leds_pins {
158 mux {
159 pins = "gpio7", "gpio8", "gpio9",
160 "gpio26", "gpio53";
161 function = "gpio";
162 drive-strength = <2>;
163 bias-pull-down;
164 output-low;
165 };
166 };
167
168 buttons_pins: buttons_pins {
169 mux {
170 pins = "gpio54";
171 drive-strength = <2>;
172 bias-pull-up;
173 };
174 };
117 }; 175 };
118 176
119 intc: interrupt-controller@2000000 { 177 intc: interrupt-controller@2000000 {
@@ -373,5 +431,233 @@
373 #reset-cells = <1>; 431 #reset-cells = <1>;
374 }; 432 };
375 433
434 pcie0: pci@1b500000 {
435 compatible = "qcom,pcie-ipq8064";
436 reg = <0x1b500000 0x1000
437 0x1b502000 0x80
438 0x1b600000 0x100
439 0x0ff00000 0x100000>;
440 reg-names = "dbi", "elbi", "parf", "config";
441 device_type = "pci";
442 linux,pci-domain = <0>;
443 bus-range = <0x00 0xff>;
444 num-lanes = <1>;
445 #address-cells = <3>;
446 #size-cells = <2>;
447
448 ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00100000 /* downstream I/O */
449 0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
450
451 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
452 interrupt-names = "msi";
453 #interrupt-cells = <1>;
454 interrupt-map-mask = <0 0 0 0x7>;
455 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
456 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
457 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
458 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
459
460 clocks = <&gcc PCIE_A_CLK>,
461 <&gcc PCIE_H_CLK>,
462 <&gcc PCIE_PHY_CLK>,
463 <&gcc PCIE_AUX_CLK>,
464 <&gcc PCIE_ALT_REF_CLK>;
465 clock-names = "core", "iface", "phy", "aux", "ref";
466
467 assigned-clocks = <&gcc PCIE_ALT_REF_CLK>;
468 assigned-clock-rates = <100000000>;
469
470 resets = <&gcc PCIE_ACLK_RESET>,
471 <&gcc PCIE_HCLK_RESET>,
472 <&gcc PCIE_POR_RESET>,
473 <&gcc PCIE_PCI_RESET>,
474 <&gcc PCIE_PHY_RESET>,
475 <&gcc PCIE_EXT_RESET>;
476 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
477
478 pinctrl-0 = <&pcie0_pins>;
479 pinctrl-names = "default";
480
481 status = "disabled";
482 perst-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
483 };
484
485 pcie1: pci@1b700000 {
486 compatible = "qcom,pcie-ipq8064";
487 reg = <0x1b700000 0x1000
488 0x1b702000 0x80
489 0x1b800000 0x100
490 0x31f00000 0x100000>;
491 reg-names = "dbi", "elbi", "parf", "config";
492 device_type = "pci";
493 linux,pci-domain = <1>;
494 bus-range = <0x00 0xff>;
495 num-lanes = <1>;
496 #address-cells = <3>;
497 #size-cells = <2>;
498
499 ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00100000 /* downstream I/O */
500 0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
501
502 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
503 interrupt-names = "msi";
504 #interrupt-cells = <1>;
505 interrupt-map-mask = <0 0 0 0x7>;
506 interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
507 <0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
508 <0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
509 <0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
510
511 clocks = <&gcc PCIE_1_A_CLK>,
512 <&gcc PCIE_1_H_CLK>,
513 <&gcc PCIE_1_PHY_CLK>,
514 <&gcc PCIE_1_AUX_CLK>,
515 <&gcc PCIE_1_ALT_REF_CLK>;
516 clock-names = "core", "iface", "phy", "aux", "ref";
517
518 assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>;
519 assigned-clock-rates = <100000000>;
520
521 resets = <&gcc PCIE_1_ACLK_RESET>,
522 <&gcc PCIE_1_HCLK_RESET>,
523 <&gcc PCIE_1_POR_RESET>,
524 <&gcc PCIE_1_PCI_RESET>,
525 <&gcc PCIE_1_PHY_RESET>,
526 <&gcc PCIE_1_EXT_RESET>;
527 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
528
529 pinctrl-0 = <&pcie1_pins>;
530 pinctrl-names = "default";
531
532 status = "disabled";
533 perst-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
534 };
535
536 pcie2: pci@1b900000 {
537 compatible = "qcom,pcie-ipq8064";
538 reg = <0x1b900000 0x1000
539 0x1b902000 0x80
540 0x1ba00000 0x100
541 0x35f00000 0x100000>;
542 reg-names = "dbi", "elbi", "parf", "config";
543 device_type = "pci";
544 linux,pci-domain = <2>;
545 bus-range = <0x00 0xff>;
546 num-lanes = <1>;
547 #address-cells = <3>;
548 #size-cells = <2>;
549
550 ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00100000 /* downstream I/O */
551 0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */
552
553 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
554 interrupt-names = "msi";
555 #interrupt-cells = <1>;
556 interrupt-map-mask = <0 0 0 0x7>;
557 interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
558 <0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
559 <0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
560 <0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
561
562 clocks = <&gcc PCIE_2_A_CLK>,
563 <&gcc PCIE_2_H_CLK>,
564 <&gcc PCIE_2_PHY_CLK>,
565 <&gcc PCIE_2_AUX_CLK>,
566 <&gcc PCIE_2_ALT_REF_CLK>;
567 clock-names = "core", "iface", "phy", "aux", "ref";
568
569 assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>;
570 assigned-clock-rates = <100000000>;
571
572 resets = <&gcc PCIE_2_ACLK_RESET>,
573 <&gcc PCIE_2_HCLK_RESET>,
574 <&gcc PCIE_2_POR_RESET>,
575 <&gcc PCIE_2_PCI_RESET>,
576 <&gcc PCIE_2_PHY_RESET>,
577 <&gcc PCIE_2_EXT_RESET>;
578 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
579
580 pinctrl-0 = <&pcie2_pins>;
581 pinctrl-names = "default";
582
583 status = "disabled";
584 perst-gpio = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
585 };
586
587 vsdcc_fixed: vsdcc-regulator {
588 compatible = "regulator-fixed";
589 regulator-name = "SDCC Power";
590 regulator-min-microvolt = <3300000>;
591 regulator-max-microvolt = <3300000>;
592 regulator-always-on;
593 };
594
595 sdcc1bam:dma@12402000 {
596 compatible = "qcom,bam-v1.3.0";
597 reg = <0x12402000 0x8000>;
598 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
599 clocks = <&gcc SDC1_H_CLK>;
600 clock-names = "bam_clk";
601 #dma-cells = <1>;
602 qcom,ee = <0>;
603 };
604
605 sdcc3bam:dma@12182000 {
606 compatible = "qcom,bam-v1.3.0";
607 reg = <0x12182000 0x8000>;
608 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
609 clocks = <&gcc SDC3_H_CLK>;
610 clock-names = "bam_clk";
611 #dma-cells = <1>;
612 qcom,ee = <0>;
613 };
614
615 amba {
616 compatible = "simple-bus";
617 #address-cells = <1>;
618 #size-cells = <1>;
619 ranges;
620
621 sdcc@12400000 {
622 status = "disabled";
623 compatible = "arm,pl18x", "arm,primecell";
624 arm,primecell-periphid = <0x00051180>;
625 reg = <0x12400000 0x2000>;
626 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
627 interrupt-names = "cmd_irq";
628 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
629 clock-names = "mclk", "apb_pclk";
630 bus-width = <8>;
631 max-frequency = <96000000>;
632 non-removable;
633 cap-sd-highspeed;
634 cap-mmc-highspeed;
635 mmc-ddr-1_8v;
636 vmmc-supply = <&vsdcc_fixed>;
637 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
638 dma-names = "tx", "rx";
639 };
640
641 sdcc@12180000 {
642 compatible = "arm,pl18x", "arm,primecell";
643 arm,primecell-periphid = <0x00051180>;
644 status = "disabled";
645 reg = <0x12180000 0x2000>;
646 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
647 interrupt-names = "cmd_irq";
648 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
649 clock-names = "mclk", "apb_pclk";
650 bus-width = <8>;
651 cap-sd-highspeed;
652 cap-mmc-highspeed;
653 max-frequency = <192000000>;
654 #mmc-ddr-1_8v;
655 sd-uhs-sdr104;
656 sd-uhs-ddr50;
657 vqmmc-supply = <&vsdcc_fixed>;
658 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
659 dma-names = "tx", "rx";
660 };
661 };
376 }; 662 };
377}; 663};
diff --git a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts
index c2dc9d09484a..ed8f064d0895 100644
--- a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts
+++ b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts
@@ -241,6 +241,33 @@
241 bias-pull-up; 241 bias-pull-up;
242 }; 242 };
243 }; 243 };
244
245 i2c3_pins: i2c3 {
246 mux {
247 pins = "gpio10", "gpio11";
248 function = "blsp_i2c3";
249 drive-strength = <2>;
250 bias-disable;
251 };
252 };
253
254 i2c12_pins: i2c12 {
255 mux {
256 pins = "gpio87", "gpio88";
257 function = "blsp_i2c12";
258 drive-strength = <2>;
259 bias-disable;
260 };
261 };
262
263 mpu6515_pin: mpu6515 {
264 irq {
265 pins = "gpio73";
266 function = "gpio";
267 bias-disable;
268 input-enable;
269 };
270 };
244 }; 271 };
245 272
246 sdhci@f9824900 { 273 sdhci@f9824900 {
@@ -277,6 +304,62 @@
277 linux,code = <KEY_VOLUMEDOWN>; 304 linux,code = <KEY_VOLUMEDOWN>;
278 }; 305 };
279 }; 306 };
307
308 i2c@f9968000 {
309 status = "ok";
310 pinctrl-names = "default";
311 pinctrl-0 = <&i2c12_pins>;
312 clock-frequency = <100000>;
313 qcom,src-freq = <50000000>;
314
315 mpu6515@68 {
316 compatible = "invensense,mpu6515";
317 reg = <0x68>;
318 interrupts-extended = <&msmgpio 73 IRQ_TYPE_EDGE_FALLING>;
319 vddio-supply = <&pm8941_lvs1>;
320
321 pinctrl-names = "default";
322 pinctrl-0 = <&mpu6515_pin>;
323
324 i2c-gate {
325 #address-cells = <1>;
326 #size-cells = <0>;
327 ak8963@f {
328 compatible = "asahi-kasei,ak8963";
329 reg = <0x0f>;
330 // Currently only works in polling mode.
331 // gpios = <&msmgpio 61 0>;
332 vid-supply = <&pm8941_lvs1>;
333 vdd-supply = <&pm8941_l17>;
334 };
335
336 bmp280@76 {
337 compatible = "bosch,bmp280";
338 reg = <0x76>;
339 vdda-supply = <&pm8941_lvs1>;
340 vddd-supply = <&pm8941_l17>;
341 };
342 };
343 };
344 };
345
346 i2c@f9925000 {
347 status = "ok";
348 pinctrl-names = "default";
349 pinctrl-0 = <&i2c3_pins>;
350 clock-frequency = <100000>;
351 qcom,src-freq = <50000000>;
352
353 avago_apds993@39 {
354 compatible = "avago,apds9930";
355 reg = <0x39>;
356 interrupts-extended = <&msmgpio 61 IRQ_TYPE_EDGE_FALLING>;
357 vdd-supply = <&pm8941_l17>;
358 vddio-supply = <&pm8941_lvs1>;
359 led-max-microamp = <100000>;
360 amstaos,proximity-diodes = <0>;
361 };
362 };
280}; 363};
281 364
282&spmi_bus { 365&spmi_bus {
diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi
index d9019a49b292..aba159d5a95a 100644
--- a/arch/arm/boot/dts/qcom-msm8974.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
@@ -67,7 +67,7 @@
67 cpus { 67 cpus {
68 #address-cells = <1>; 68 #address-cells = <1>;
69 #size-cells = <0>; 69 #size-cells = <0>;
70 interrupts = <1 9 0xf04>; 70 interrupts = <GIC_PPI 9 0xf04>;
71 71
72 CPU0: cpu@0 { 72 CPU0: cpu@0 {
73 compatible = "qcom,krait"; 73 compatible = "qcom,krait";
@@ -214,7 +214,7 @@
214 214
215 cpu-pmu { 215 cpu-pmu {
216 compatible = "qcom,krait-pmu"; 216 compatible = "qcom,krait-pmu";
217 interrupts = <1 7 0xf04>; 217 interrupts = <GIC_PPI 7 0xf04>;
218 }; 218 };
219 219
220 clocks { 220 clocks {
@@ -233,17 +233,17 @@
233 233
234 timer { 234 timer {
235 compatible = "arm,armv7-timer"; 235 compatible = "arm,armv7-timer";
236 interrupts = <1 2 0xf08>, 236 interrupts = <GIC_PPI 2 0xf08>,
237 <1 3 0xf08>, 237 <GIC_PPI 3 0xf08>,
238 <1 4 0xf08>, 238 <GIC_PPI 4 0xf08>,
239 <1 1 0xf08>; 239 <GIC_PPI 1 0xf08>;
240 clock-frequency = <19200000>; 240 clock-frequency = <19200000>;
241 }; 241 };
242 242
243 adsp-pil { 243 adsp-pil {
244 compatible = "qcom,msm8974-adsp-pil"; 244 compatible = "qcom,msm8974-adsp-pil";
245 245
246 interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>, 246 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
247 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 247 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
248 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 248 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
249 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 249 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
@@ -275,7 +275,7 @@
275 qcom,smem = <443>, <429>; 275 qcom,smem = <443>, <429>;
276 276
277 interrupt-parent = <&intc>; 277 interrupt-parent = <&intc>;
278 interrupts = <0 158 IRQ_TYPE_EDGE_RISING>; 278 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
279 279
280 qcom,ipc = <&apcs 8 10>; 280 qcom,ipc = <&apcs 8 10>;
281 281
@@ -300,7 +300,7 @@
300 qcom,smem = <435>, <428>; 300 qcom,smem = <435>, <428>;
301 301
302 interrupt-parent = <&intc>; 302 interrupt-parent = <&intc>;
303 interrupts = <0 27 IRQ_TYPE_EDGE_RISING>; 303 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
304 304
305 qcom,ipc = <&apcs 8 14>; 305 qcom,ipc = <&apcs 8 14>;
306 306
@@ -325,7 +325,7 @@
325 qcom,smem = <451>, <431>; 325 qcom,smem = <451>, <431>;
326 326
327 interrupt-parent = <&intc>; 327 interrupt-parent = <&intc>;
328 interrupts = <0 143 IRQ_TYPE_EDGE_RISING>; 328 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
329 329
330 qcom,ipc = <&apcs 8 18>; 330 qcom,ipc = <&apcs 8 18>;
331 331
@@ -364,7 +364,7 @@
364 364
365 modem_smsm: modem@1 { 365 modem_smsm: modem@1 {
366 reg = <1>; 366 reg = <1>;
367 interrupts = <0 26 IRQ_TYPE_EDGE_RISING>; 367 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
368 368
369 interrupt-controller; 369 interrupt-controller;
370 #interrupt-cells = <2>; 370 #interrupt-cells = <2>;
@@ -372,7 +372,7 @@
372 372
373 adsp_smsm: adsp@2 { 373 adsp_smsm: adsp@2 {
374 reg = <2>; 374 reg = <2>;
375 interrupts = <0 157 IRQ_TYPE_EDGE_RISING>; 375 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
376 376
377 interrupt-controller; 377 interrupt-controller;
378 #interrupt-cells = <2>; 378 #interrupt-cells = <2>;
@@ -380,7 +380,7 @@
380 380
381 wcnss_smsm: wcnss@7 { 381 wcnss_smsm: wcnss@7 {
382 reg = <7>; 382 reg = <7>;
383 interrupts = <0 144 IRQ_TYPE_EDGE_RISING>; 383 interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
384 384
385 interrupt-controller; 385 interrupt-controller;
386 #interrupt-cells = <2>; 386 #interrupt-cells = <2>;
@@ -445,50 +445,50 @@
445 445
446 frame@f9021000 { 446 frame@f9021000 {
447 frame-number = <0>; 447 frame-number = <0>;
448 interrupts = <0 8 0x4>, 448 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
449 <0 7 0x4>; 449 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
450 reg = <0xf9021000 0x1000>, 450 reg = <0xf9021000 0x1000>,
451 <0xf9022000 0x1000>; 451 <0xf9022000 0x1000>;
452 }; 452 };
453 453
454 frame@f9023000 { 454 frame@f9023000 {
455 frame-number = <1>; 455 frame-number = <1>;
456 interrupts = <0 9 0x4>; 456 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
457 reg = <0xf9023000 0x1000>; 457 reg = <0xf9023000 0x1000>;
458 status = "disabled"; 458 status = "disabled";
459 }; 459 };
460 460
461 frame@f9024000 { 461 frame@f9024000 {
462 frame-number = <2>; 462 frame-number = <2>;
463 interrupts = <0 10 0x4>; 463 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
464 reg = <0xf9024000 0x1000>; 464 reg = <0xf9024000 0x1000>;
465 status = "disabled"; 465 status = "disabled";
466 }; 466 };
467 467
468 frame@f9025000 { 468 frame@f9025000 {
469 frame-number = <3>; 469 frame-number = <3>;
470 interrupts = <0 11 0x4>; 470 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
471 reg = <0xf9025000 0x1000>; 471 reg = <0xf9025000 0x1000>;
472 status = "disabled"; 472 status = "disabled";
473 }; 473 };
474 474
475 frame@f9026000 { 475 frame@f9026000 {
476 frame-number = <4>; 476 frame-number = <4>;
477 interrupts = <0 12 0x4>; 477 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
478 reg = <0xf9026000 0x1000>; 478 reg = <0xf9026000 0x1000>;
479 status = "disabled"; 479 status = "disabled";
480 }; 480 };
481 481
482 frame@f9027000 { 482 frame@f9027000 {
483 frame-number = <5>; 483 frame-number = <5>;
484 interrupts = <0 13 0x4>; 484 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
485 reg = <0xf9027000 0x1000>; 485 reg = <0xf9027000 0x1000>;
486 status = "disabled"; 486 status = "disabled";
487 }; 487 };
488 488
489 frame@f9028000 { 489 frame@f9028000 {
490 frame-number = <6>; 490 frame-number = <6>;
491 interrupts = <0 14 0x4>; 491 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
492 reg = <0xf9028000 0x1000>; 492 reg = <0xf9028000 0x1000>;
493 status = "disabled"; 493 status = "disabled";
494 }; 494 };
@@ -586,7 +586,7 @@
586 blsp1_uart1: serial@f991d000 { 586 blsp1_uart1: serial@f991d000 {
587 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 587 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
588 reg = <0xf991d000 0x1000>; 588 reg = <0xf991d000 0x1000>;
589 interrupts = <0 107 0x0>; 589 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
590 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 590 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
591 clock-names = "core", "iface"; 591 clock-names = "core", "iface";
592 status = "disabled"; 592 status = "disabled";
@@ -595,7 +595,7 @@
595 blsp1_uart2: serial@f991e000 { 595 blsp1_uart2: serial@f991e000 {
596 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 596 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
597 reg = <0xf991e000 0x1000>; 597 reg = <0xf991e000 0x1000>;
598 interrupts = <0 108 0x0>; 598 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
599 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 599 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
600 clock-names = "core", "iface"; 600 clock-names = "core", "iface";
601 status = "disabled"; 601 status = "disabled";
@@ -605,7 +605,8 @@
605 compatible = "qcom,sdhci-msm-v4"; 605 compatible = "qcom,sdhci-msm-v4";
606 reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; 606 reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
607 reg-names = "hc_mem", "core_mem"; 607 reg-names = "hc_mem", "core_mem";
608 interrupts = <0 123 0>, <0 138 0>; 608 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
609 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
609 interrupt-names = "hc_irq", "pwr_irq"; 610 interrupt-names = "hc_irq", "pwr_irq";
610 clocks = <&gcc GCC_SDCC1_APPS_CLK>, 611 clocks = <&gcc GCC_SDCC1_APPS_CLK>,
611 <&gcc GCC_SDCC1_AHB_CLK>, 612 <&gcc GCC_SDCC1_AHB_CLK>,
@@ -618,8 +619,8 @@
618 compatible = "qcom,sdhci-msm-v4"; 619 compatible = "qcom,sdhci-msm-v4";
619 reg = <0xf9864900 0x11c>, <0xf9864000 0x800>; 620 reg = <0xf9864900 0x11c>, <0xf9864000 0x800>;
620 reg-names = "hc_mem", "core_mem"; 621 reg-names = "hc_mem", "core_mem";
621 interrupts = <GIC_SPI 127 IRQ_TYPE_NONE>, 622 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
622 <GIC_SPI 224 IRQ_TYPE_NONE>; 623 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
623 interrupt-names = "hc_irq", "pwr_irq"; 624 interrupt-names = "hc_irq", "pwr_irq";
624 clocks = <&gcc GCC_SDCC3_APPS_CLK>, 625 clocks = <&gcc GCC_SDCC3_APPS_CLK>,
625 <&gcc GCC_SDCC3_AHB_CLK>, 626 <&gcc GCC_SDCC3_AHB_CLK>,
@@ -632,7 +633,8 @@
632 compatible = "qcom,sdhci-msm-v4"; 633 compatible = "qcom,sdhci-msm-v4";
633 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; 634 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
634 reg-names = "hc_mem", "core_mem"; 635 reg-names = "hc_mem", "core_mem";
635 interrupts = <0 125 0>, <0 221 0>; 636 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
637 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
636 interrupt-names = "hc_irq", "pwr_irq"; 638 interrupt-names = "hc_irq", "pwr_irq";
637 clocks = <&gcc GCC_SDCC2_APPS_CLK>, 639 clocks = <&gcc GCC_SDCC2_APPS_CLK>,
638 <&gcc GCC_SDCC2_AHB_CLK>, 640 <&gcc GCC_SDCC2_AHB_CLK>,
@@ -699,25 +701,36 @@
699 #gpio-cells = <2>; 701 #gpio-cells = <2>;
700 interrupt-controller; 702 interrupt-controller;
701 #interrupt-cells = <2>; 703 #interrupt-cells = <2>;
702 interrupts = <0 208 0>; 704 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
703 }; 705 };
704 706
705 i2c@f9924000 { 707 i2c@f9924000 {
706 status = "disabled"; 708 status = "disabled";
707 compatible = "qcom,i2c-qup-v2.1.1"; 709 compatible = "qcom,i2c-qup-v2.1.1";
708 reg = <0xf9924000 0x1000>; 710 reg = <0xf9924000 0x1000>;
709 interrupts = <0 96 IRQ_TYPE_NONE>; 711 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
710 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 712 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
711 clock-names = "core", "iface"; 713 clock-names = "core", "iface";
712 #address-cells = <1>; 714 #address-cells = <1>;
713 #size-cells = <0>; 715 #size-cells = <0>;
714 }; 716 };
715 717
718 blsp_i2c3: i2c@f9925000 {
719 status = "disabled";
720 compatible = "qcom,i2c-qup-v2.1.1";
721 reg = <0xf9925000 0x1000>;
722 interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
723 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
724 clock-names = "core", "iface";
725 #address-cells = <1>;
726 #size-cells = <0>;
727 };
728
716 blsp_i2c8: i2c@f9964000 { 729 blsp_i2c8: i2c@f9964000 {
717 status = "disabled"; 730 status = "disabled";
718 compatible = "qcom,i2c-qup-v2.1.1"; 731 compatible = "qcom,i2c-qup-v2.1.1";
719 reg = <0xf9964000 0x1000>; 732 reg = <0xf9964000 0x1000>;
720 interrupts = <0 102 IRQ_TYPE_NONE>; 733 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
721 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 734 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
722 clock-names = "core", "iface"; 735 clock-names = "core", "iface";
723 #address-cells = <1>; 736 #address-cells = <1>;
@@ -728,7 +741,7 @@
728 status = "disabled"; 741 status = "disabled";
729 compatible = "qcom,i2c-qup-v2.1.1"; 742 compatible = "qcom,i2c-qup-v2.1.1";
730 reg = <0xf9967000 0x1000>; 743 reg = <0xf9967000 0x1000>;
731 interrupts = <0 105 IRQ_TYPE_NONE>; 744 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
732 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 745 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
733 clock-names = "core", "iface"; 746 clock-names = "core", "iface";
734 #address-cells = <1>; 747 #address-cells = <1>;
@@ -737,6 +750,17 @@
737 dma-names = "tx", "rx"; 750 dma-names = "tx", "rx";
738 }; 751 };
739 752
753 blsp_i2c12: i2c@f9968000 {
754 status = "disabled";
755 compatible = "qcom,i2c-qup-v2.1.1";
756 reg = <0xf9968000 0x1000>;
757 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
758 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
759 clock-names = "core", "iface";
760 #address-cells = <1>;
761 #size-cells = <0>;
762 };
763
740 spmi_bus: spmi@fc4cf000 { 764 spmi_bus: spmi@fc4cf000 {
741 compatible = "qcom,spmi-pmic-arb"; 765 compatible = "qcom,spmi-pmic-arb";
742 reg-names = "core", "intr", "cnfg"; 766 reg-names = "core", "intr", "cnfg";
@@ -744,7 +768,7 @@
744 <0xfc4cb000 0x1000>, 768 <0xfc4cb000 0x1000>,
745 <0xfc4ca000 0x1000>; 769 <0xfc4ca000 0x1000>;
746 interrupt-names = "periph_irq"; 770 interrupt-names = "periph_irq";
747 interrupts = <0 190 0>; 771 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
748 qcom,ee = <0>; 772 qcom,ee = <0>;
749 qcom,channel = <0>; 773 qcom,channel = <0>;
750 #address-cells = <2>; 774 #address-cells = <2>;
@@ -770,10 +794,11 @@
770 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 794 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
771 clock-names = "apb_pclk", "atclk"; 795 clock-names = "apb_pclk", "atclk";
772 796
773 port { 797 in-ports {
774 etr_in: endpoint { 798 port {
775 slave-mode; 799 etr_in: endpoint {
776 remote-endpoint = <&replicator_out0>; 800 remote-endpoint = <&replicator_out0>;
801 };
777 }; 802 };
778 }; 803 };
779 }; 804 };
@@ -785,10 +810,11 @@
785 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 810 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
786 clock-names = "apb_pclk", "atclk"; 811 clock-names = "apb_pclk", "atclk";
787 812
788 port { 813 in-ports {
789 tpiu_in: endpoint { 814 port {
790 slave-mode; 815 tpiu_in: endpoint {
791 remote-endpoint = <&replicator_out1>; 816 remote-endpoint = <&replicator_out1>;
817 };
792 }; 818 };
793 }; 819 };
794 }; 820 };
@@ -800,7 +826,7 @@
800 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 826 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
801 clock-names = "apb_pclk", "atclk"; 827 clock-names = "apb_pclk", "atclk";
802 828
803 ports { 829 out-ports {
804 #address-cells = <1>; 830 #address-cells = <1>;
805 #size-cells = <0>; 831 #size-cells = <0>;
806 832
@@ -816,10 +842,11 @@
816 remote-endpoint = <&tpiu_in>; 842 remote-endpoint = <&tpiu_in>;
817 }; 843 };
818 }; 844 };
819 port@2 { 845 };
820 reg = <0>; 846
847 in-ports {
848 port {
821 replicator_in: endpoint { 849 replicator_in: endpoint {
822 slave-mode;
823 remote-endpoint = <&etf_out>; 850 remote-endpoint = <&etf_out>;
824 }; 851 };
825 }; 852 };
@@ -833,20 +860,17 @@
833 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 860 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
834 clock-names = "apb_pclk", "atclk"; 861 clock-names = "apb_pclk", "atclk";
835 862
836 ports { 863 out-ports {
837 #address-cells = <1>; 864 port {
838 #size-cells = <0>;
839
840 port@0 {
841 reg = <0>;
842 etf_out: endpoint { 865 etf_out: endpoint {
843 remote-endpoint = <&replicator_in>; 866 remote-endpoint = <&replicator_in>;
844 }; 867 };
845 }; 868 };
846 port@1 { 869 };
847 reg = <0>; 870
871 in-ports {
872 port {
848 etf_in: endpoint { 873 etf_in: endpoint {
849 slave-mode;
850 remote-endpoint = <&merger_out>; 874 remote-endpoint = <&merger_out>;
851 }; 875 };
852 }; 876 };
@@ -860,7 +884,7 @@
860 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 884 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
861 clock-names = "apb_pclk", "atclk"; 885 clock-names = "apb_pclk", "atclk";
862 886
863 ports { 887 in-ports {
864 #address-cells = <1>; 888 #address-cells = <1>;
865 #size-cells = <0>; 889 #size-cells = <0>;
866 890
@@ -873,12 +897,13 @@
873 port@1 { 897 port@1 {
874 reg = <1>; 898 reg = <1>;
875 merger_in1: endpoint { 899 merger_in1: endpoint {
876 slave-mode;
877 remote-endpoint = <&funnel1_out>; 900 remote-endpoint = <&funnel1_out>;
878 }; 901 };
879 }; 902 };
880 port@8 { 903 };
881 reg = <0>; 904
905 out-ports {
906 port {
882 merger_out: endpoint { 907 merger_out: endpoint {
883 remote-endpoint = <&etf_in>; 908 remote-endpoint = <&etf_in>;
884 }; 909 };
@@ -893,7 +918,7 @@
893 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 918 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
894 clock-names = "apb_pclk", "atclk"; 919 clock-names = "apb_pclk", "atclk";
895 920
896 ports { 921 in-ports {
897 #address-cells = <1>; 922 #address-cells = <1>;
898 #size-cells = <0>; 923 #size-cells = <0>;
899 924
@@ -910,12 +935,13 @@
910 port@5 { 935 port@5 {
911 reg = <5>; 936 reg = <5>;
912 funnel1_in5: endpoint { 937 funnel1_in5: endpoint {
913 slave-mode;
914 remote-endpoint = <&kpss_out>; 938 remote-endpoint = <&kpss_out>;
915 }; 939 };
916 }; 940 };
917 port@8 { 941 };
918 reg = <0>; 942
943 out-ports {
944 port {
919 funnel1_out: endpoint { 945 funnel1_out: endpoint {
920 remote-endpoint = <&merger_in1>; 946 remote-endpoint = <&merger_in1>;
921 }; 947 };
@@ -930,40 +956,38 @@
930 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 956 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
931 clock-names = "apb_pclk", "atclk"; 957 clock-names = "apb_pclk", "atclk";
932 958
933 ports { 959 in-ports {
934 #address-cells = <1>; 960 #address-cells = <1>;
935 #size-cells = <0>; 961 #size-cells = <0>;
936 962
937 port@0 { 963 port@0 {
938 reg = <0>; 964 reg = <0>;
939 kpss_in0: endpoint { 965 kpss_in0: endpoint {
940 slave-mode;
941 remote-endpoint = <&etm0_out>; 966 remote-endpoint = <&etm0_out>;
942 }; 967 };
943 }; 968 };
944 port@1 { 969 port@1 {
945 reg = <1>; 970 reg = <1>;
946 kpss_in1: endpoint { 971 kpss_in1: endpoint {
947 slave-mode;
948 remote-endpoint = <&etm1_out>; 972 remote-endpoint = <&etm1_out>;
949 }; 973 };
950 }; 974 };
951 port@2 { 975 port@2 {
952 reg = <2>; 976 reg = <2>;
953 kpss_in2: endpoint { 977 kpss_in2: endpoint {
954 slave-mode;
955 remote-endpoint = <&etm2_out>; 978 remote-endpoint = <&etm2_out>;
956 }; 979 };
957 }; 980 };
958 port@3 { 981 port@3 {
959 reg = <3>; 982 reg = <3>;
960 kpss_in3: endpoint { 983 kpss_in3: endpoint {
961 slave-mode;
962 remote-endpoint = <&etm3_out>; 984 remote-endpoint = <&etm3_out>;
963 }; 985 };
964 }; 986 };
965 port@8 { 987 };
966 reg = <0>; 988
989 out-ports {
990 port {
967 kpss_out: endpoint { 991 kpss_out: endpoint {
968 remote-endpoint = <&funnel1_in5>; 992 remote-endpoint = <&funnel1_in5>;
969 }; 993 };
@@ -980,9 +1004,11 @@
980 1004
981 cpu = <&CPU0>; 1005 cpu = <&CPU0>;
982 1006
983 port { 1007 out-ports {
984 etm0_out: endpoint { 1008 port {
985 remote-endpoint = <&kpss_in0>; 1009 etm0_out: endpoint {
1010 remote-endpoint = <&kpss_in0>;
1011 };
986 }; 1012 };
987 }; 1013 };
988 }; 1014 };
@@ -996,9 +1022,11 @@
996 1022
997 cpu = <&CPU1>; 1023 cpu = <&CPU1>;
998 1024
999 port { 1025 out-ports {
1000 etm1_out: endpoint { 1026 port {
1001 remote-endpoint = <&kpss_in1>; 1027 etm1_out: endpoint {
1028 remote-endpoint = <&kpss_in1>;
1029 };
1002 }; 1030 };
1003 }; 1031 };
1004 }; 1032 };
@@ -1012,9 +1040,11 @@
1012 1040
1013 cpu = <&CPU2>; 1041 cpu = <&CPU2>;
1014 1042
1015 port { 1043 out-ports {
1016 etm2_out: endpoint { 1044 port {
1017 remote-endpoint = <&kpss_in2>; 1045 etm2_out: endpoint {
1046 remote-endpoint = <&kpss_in2>;
1047 };
1018 }; 1048 };
1019 }; 1049 };
1020 }; 1050 };
@@ -1028,9 +1058,11 @@
1028 1058
1029 cpu = <&CPU3>; 1059 cpu = <&CPU3>;
1030 1060
1031 port { 1061 out-ports {
1032 etm3_out: endpoint { 1062 port {
1033 remote-endpoint = <&kpss_in3>; 1063 etm3_out: endpoint {
1064 remote-endpoint = <&kpss_in3>;
1065 };
1034 }; 1066 };
1035 }; 1067 };
1036 }; 1068 };
@@ -1040,21 +1072,21 @@
1040 compatible = "qcom,smd"; 1072 compatible = "qcom,smd";
1041 1073
1042 adsp { 1074 adsp {
1043 interrupts = <0 156 IRQ_TYPE_EDGE_RISING>; 1075 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
1044 1076
1045 qcom,ipc = <&apcs 8 8>; 1077 qcom,ipc = <&apcs 8 8>;
1046 qcom,smd-edge = <1>; 1078 qcom,smd-edge = <1>;
1047 }; 1079 };
1048 1080
1049 modem { 1081 modem {
1050 interrupts = <0 25 IRQ_TYPE_EDGE_RISING>; 1082 interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
1051 1083
1052 qcom,ipc = <&apcs 8 12>; 1084 qcom,ipc = <&apcs 8 12>;
1053 qcom,smd-edge = <0>; 1085 qcom,smd-edge = <0>;
1054 }; 1086 };
1055 1087
1056 rpm { 1088 rpm {
1057 interrupts = <0 168 1>; 1089 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
1058 qcom,ipc = <&apcs 8 0>; 1090 qcom,ipc = <&apcs 8 0>;
1059 qcom,smd-edge = <15>; 1091 qcom,smd-edge = <15>;
1060 1092
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-24 09:06:44 -0400